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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_dma.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
emilmont 77:869cf507173a 7 * @brief Header file of DMA HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_DMA_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_DMA_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup DMA
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58
Kojto 99:dbbf35b96557 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 99:dbbf35b96557 60 * @brief DMA Exported Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
emilmont 77:869cf507173a 64 /**
bogdanm 85:024bf7f99721 65 * @brief DMA Configuration Structure definition
emilmont 77:869cf507173a 66 */
emilmont 77:869cf507173a 67 typedef struct
emilmont 77:869cf507173a 68 {
emilmont 77:869cf507173a 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
emilmont 77:869cf507173a 70 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 85:024bf7f99721 71
emilmont 77:869cf507173a 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
emilmont 77:869cf507173a 73 from memory to memory or from peripheral to memory.
emilmont 77:869cf507173a 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 85:024bf7f99721 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 85:024bf7f99721 78
emilmont 77:869cf507173a 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
emilmont 77:869cf507173a 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 85:024bf7f99721 81
emilmont 77:869cf507173a 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 85:024bf7f99721 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
emilmont 77:869cf507173a 84
emilmont 77:869cf507173a 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
emilmont 77:869cf507173a 86 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 85:024bf7f99721 87
emilmont 77:869cf507173a 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
emilmont 77:869cf507173a 89 This parameter can be a value of @ref DMA_mode
emilmont 77:869cf507173a 90 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 85:024bf7f99721 91 data transfer is configured on the selected Stream */
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
emilmont 77:869cf507173a 94 This parameter can be a value of @ref DMA_Priority_level */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
emilmont 77:869cf507173a 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
emilmont 77:869cf507173a 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
emilmont 77:869cf507173a 99 memory-to-memory data transfer is configured on the selected stream */
bogdanm 85:024bf7f99721 100
emilmont 77:869cf507173a 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
emilmont 77:869cf507173a 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 85:024bf7f99721 103
emilmont 77:869cf507173a 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 99:dbbf35b96557 105 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 85:024bf7f99721 106 transaction.
emilmont 77:869cf507173a 107 This parameter can be a value of @ref DMA_Memory_burst
emilmont 77:869cf507173a 108 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 85:024bf7f99721 109
emilmont 77:869cf507173a 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto 122:f9eeca106725 111 It specifies the amount of data to be transferred in a single non interruptible
emilmont 77:869cf507173a 112 transaction.
emilmont 77:869cf507173a 113 This parameter can be a value of @ref DMA_Peripheral_burst
emilmont 77:869cf507173a 114 @note The burst mode is possible only if the address Increment mode is enabled. */
emilmont 77:869cf507173a 115 }DMA_InitTypeDef;
emilmont 77:869cf507173a 116
Kojto 99:dbbf35b96557 117
emilmont 77:869cf507173a 118 /**
bogdanm 85:024bf7f99721 119 * @brief HAL DMA State structures definition
bogdanm 85:024bf7f99721 120 */
emilmont 77:869cf507173a 121 typedef enum
emilmont 77:869cf507173a 122 {
Kojto 122:f9eeca106725 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
Kojto 122:f9eeca106725 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
Kojto 122:f9eeca106725 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
Kojto 122:f9eeca106725 126 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
Kojto 122:f9eeca106725 127 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
Kojto 122:f9eeca106725 128 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
emilmont 77:869cf507173a 129 }HAL_DMA_StateTypeDef;
emilmont 77:869cf507173a 130
emilmont 77:869cf507173a 131 /**
bogdanm 85:024bf7f99721 132 * @brief HAL DMA Error Code structure definition
bogdanm 85:024bf7f99721 133 */
emilmont 77:869cf507173a 134 typedef enum
emilmont 77:869cf507173a 135 {
Kojto 122:f9eeca106725 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 137 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
emilmont 77:869cf507173a 138 }HAL_DMA_LevelCompleteTypeDef;
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 /**
Kojto 122:f9eeca106725 141 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 142 */
Kojto 122:f9eeca106725 143 typedef enum
Kojto 122:f9eeca106725 144 {
Kojto 122:f9eeca106725 145 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 146 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
Kojto 122:f9eeca106725 147 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
Kojto 122:f9eeca106725 148 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
Kojto 122:f9eeca106725 149 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
Kojto 122:f9eeca106725 150 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
Kojto 122:f9eeca106725 151 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
Kojto 122:f9eeca106725 152 }HAL_DMA_CallbackIDTypeDef;
Kojto 122:f9eeca106725 153
Kojto 122:f9eeca106725 154 /**
bogdanm 85:024bf7f99721 155 * @brief DMA handle Structure definition
bogdanm 85:024bf7f99721 156 */
emilmont 77:869cf507173a 157 typedef struct __DMA_HandleTypeDef
bogdanm 85:024bf7f99721 158 {
emilmont 77:869cf507173a 159 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 160
emilmont 77:869cf507173a 161 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 85:024bf7f99721 162
emilmont 77:869cf507173a 163 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 85:024bf7f99721 164
emilmont 77:869cf507173a 165 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 85:024bf7f99721 166
Kojto 122:f9eeca106725 167 void *Parent; /*!< Parent object state */
bogdanm 85:024bf7f99721 168
emilmont 77:869cf507173a 169 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 85:024bf7f99721 170
emilmont 77:869cf507173a 171 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 85:024bf7f99721 172
emilmont 77:869cf507173a 173 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
Kojto 122:f9eeca106725 176
emilmont 77:869cf507173a 177 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 122:f9eeca106725 178
Kojto 122:f9eeca106725 179 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
emilmont 77:869cf507173a 180
Kojto 122:f9eeca106725 181 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 122:f9eeca106725 182
Kojto 110:165afa46840b 183 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
Kojto 110:165afa46840b 184
Kojto 122:f9eeca106725 185 uint32_t StreamIndex; /*!< DMA Stream Index */
Kojto 122:f9eeca106725 186
bogdanm 85:024bf7f99721 187 }DMA_HandleTypeDef;
emilmont 77:869cf507173a 188
Kojto 99:dbbf35b96557 189 /**
Kojto 99:dbbf35b96557 190 * @}
Kojto 99:dbbf35b96557 191 */
Kojto 99:dbbf35b96557 192
emilmont 77:869cf507173a 193 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 194
Kojto 99:dbbf35b96557 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 99:dbbf35b96557 196 * @brief DMA Exported constants
emilmont 77:869cf507173a 197 * @{
emilmont 77:869cf507173a 198 */
emilmont 77:869cf507173a 199
Kojto 99:dbbf35b96557 200 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 99:dbbf35b96557 201 * @brief DMA Error Code
emilmont 77:869cf507173a 202 * @{
emilmont 77:869cf507173a 203 */
Kojto 122:f9eeca106725 204 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
Kojto 122:f9eeca106725 205 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
Kojto 122:f9eeca106725 206 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
Kojto 122:f9eeca106725 207 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
Kojto 122:f9eeca106725 208 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
Kojto 122:f9eeca106725 209 #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
Kojto 122:f9eeca106725 210 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
Kojto 122:f9eeca106725 211 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
emilmont 77:869cf507173a 212 /**
emilmont 77:869cf507173a 213 * @}
emilmont 77:869cf507173a 214 */
emilmont 77:869cf507173a 215
Kojto 99:dbbf35b96557 216 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 99:dbbf35b96557 217 * @brief DMA channel selection
emilmont 77:869cf507173a 218 * @{
emilmont 77:869cf507173a 219 */
Kojto 122:f9eeca106725 220 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
Kojto 122:f9eeca106725 221 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
Kojto 122:f9eeca106725 222 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
Kojto 122:f9eeca106725 223 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
Kojto 122:f9eeca106725 224 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
Kojto 122:f9eeca106725 225 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
Kojto 122:f9eeca106725 226 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
Kojto 122:f9eeca106725 227 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
emilmont 77:869cf507173a 228 /**
emilmont 77:869cf507173a 229 * @}
emilmont 77:869cf507173a 230 */
emilmont 77:869cf507173a 231
Kojto 99:dbbf35b96557 232 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 99:dbbf35b96557 233 * @brief DMA data transfer direction
emilmont 77:869cf507173a 234 * @{
emilmont 77:869cf507173a 235 */
Kojto 122:f9eeca106725 236 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
emilmont 77:869cf507173a 237 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
emilmont 77:869cf507173a 238 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
emilmont 77:869cf507173a 239 /**
emilmont 77:869cf507173a 240 * @}
Kojto 122:f9eeca106725 241 */
emilmont 77:869cf507173a 242
Kojto 99:dbbf35b96557 243 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 99:dbbf35b96557 244 * @brief DMA peripheral incremented mode
emilmont 77:869cf507173a 245 * @{
emilmont 77:869cf507173a 246 */
emilmont 77:869cf507173a 247 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
Kojto 122:f9eeca106725 248 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
emilmont 77:869cf507173a 249 /**
emilmont 77:869cf507173a 250 * @}
emilmont 77:869cf507173a 251 */
emilmont 77:869cf507173a 252
Kojto 99:dbbf35b96557 253 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 99:dbbf35b96557 254 * @brief DMA memory incremented mode
emilmont 77:869cf507173a 255 * @{
emilmont 77:869cf507173a 256 */
emilmont 77:869cf507173a 257 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
Kojto 122:f9eeca106725 258 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
emilmont 77:869cf507173a 259 /**
emilmont 77:869cf507173a 260 * @}
emilmont 77:869cf507173a 261 */
emilmont 77:869cf507173a 262
Kojto 99:dbbf35b96557 263 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 99:dbbf35b96557 264 * @brief DMA peripheral data size
emilmont 77:869cf507173a 265 * @{
emilmont 77:869cf507173a 266 */
Kojto 122:f9eeca106725 267 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
emilmont 77:869cf507173a 268 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
emilmont 77:869cf507173a 269 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
emilmont 77:869cf507173a 270 /**
emilmont 77:869cf507173a 271 * @}
emilmont 77:869cf507173a 272 */
emilmont 77:869cf507173a 273
Kojto 99:dbbf35b96557 274 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 99:dbbf35b96557 275 * @brief DMA memory data size
emilmont 77:869cf507173a 276 * @{
emilmont 77:869cf507173a 277 */
Kojto 122:f9eeca106725 278 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
emilmont 77:869cf507173a 279 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
emilmont 77:869cf507173a 280 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
emilmont 77:869cf507173a 281 /**
emilmont 77:869cf507173a 282 * @}
emilmont 77:869cf507173a 283 */
emilmont 77:869cf507173a 284
Kojto 99:dbbf35b96557 285 /** @defgroup DMA_mode DMA mode
Kojto 99:dbbf35b96557 286 * @brief DMA mode
emilmont 77:869cf507173a 287 * @{
emilmont 77:869cf507173a 288 */
Kojto 122:f9eeca106725 289 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
emilmont 77:869cf507173a 290 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
emilmont 77:869cf507173a 291 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
emilmont 77:869cf507173a 292 /**
emilmont 77:869cf507173a 293 * @}
emilmont 77:869cf507173a 294 */
emilmont 77:869cf507173a 295
Kojto 99:dbbf35b96557 296 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 99:dbbf35b96557 297 * @brief DMA priority levels
emilmont 77:869cf507173a 298 * @{
emilmont 77:869cf507173a 299 */
Kojto 122:f9eeca106725 300 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
emilmont 77:869cf507173a 301 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
emilmont 77:869cf507173a 302 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
emilmont 77:869cf507173a 303 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
emilmont 77:869cf507173a 304 /**
emilmont 77:869cf507173a 305 * @}
emilmont 77:869cf507173a 306 */
emilmont 77:869cf507173a 307
Kojto 99:dbbf35b96557 308 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 99:dbbf35b96557 309 * @brief DMA FIFO direct mode
emilmont 77:869cf507173a 310 * @{
emilmont 77:869cf507173a 311 */
Kojto 122:f9eeca106725 312 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
emilmont 77:869cf507173a 313 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
emilmont 77:869cf507173a 314 /**
emilmont 77:869cf507173a 315 * @}
emilmont 77:869cf507173a 316 */
emilmont 77:869cf507173a 317
Kojto 99:dbbf35b96557 318 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 99:dbbf35b96557 319 * @brief DMA FIFO level
emilmont 77:869cf507173a 320 * @{
emilmont 77:869cf507173a 321 */
Kojto 122:f9eeca106725 322 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
emilmont 77:869cf507173a 323 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
emilmont 77:869cf507173a 324 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
emilmont 77:869cf507173a 325 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
emilmont 77:869cf507173a 326 /**
emilmont 77:869cf507173a 327 * @}
emilmont 77:869cf507173a 328 */
emilmont 77:869cf507173a 329
Kojto 99:dbbf35b96557 330 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 99:dbbf35b96557 331 * @brief DMA memory burst
emilmont 77:869cf507173a 332 * @{
emilmont 77:869cf507173a 333 */
Kojto 122:f9eeca106725 334 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
emilmont 77:869cf507173a 335 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
emilmont 77:869cf507173a 336 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
emilmont 77:869cf507173a 337 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
emilmont 77:869cf507173a 338 /**
emilmont 77:869cf507173a 339 * @}
emilmont 77:869cf507173a 340 */
emilmont 77:869cf507173a 341
Kojto 99:dbbf35b96557 342 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 99:dbbf35b96557 343 * @brief DMA peripheral burst
emilmont 77:869cf507173a 344 * @{
emilmont 77:869cf507173a 345 */
Kojto 122:f9eeca106725 346 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 347 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
Kojto 122:f9eeca106725 348 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
Kojto 122:f9eeca106725 349 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
emilmont 77:869cf507173a 350 /**
emilmont 77:869cf507173a 351 * @}
emilmont 77:869cf507173a 352 */
emilmont 77:869cf507173a 353
Kojto 99:dbbf35b96557 354 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 99:dbbf35b96557 355 * @brief DMA interrupts definition
emilmont 77:869cf507173a 356 * @{
emilmont 77:869cf507173a 357 */
emilmont 77:869cf507173a 358 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
emilmont 77:869cf507173a 359 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
emilmont 77:869cf507173a 360 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
emilmont 77:869cf507173a 361 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
Kojto 122:f9eeca106725 362 #define DMA_IT_FE ((uint32_t)0x00000080U)
emilmont 77:869cf507173a 363 /**
emilmont 77:869cf507173a 364 * @}
emilmont 77:869cf507173a 365 */
emilmont 77:869cf507173a 366
Kojto 99:dbbf35b96557 367 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 99:dbbf35b96557 368 * @brief DMA flag definitions
emilmont 77:869cf507173a 369 * @{
emilmont 77:869cf507173a 370 */
Kojto 122:f9eeca106725 371 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
Kojto 122:f9eeca106725 372 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
Kojto 122:f9eeca106725 373 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 374 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 375 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 376 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 377 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 378 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 379 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 380 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 381 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 382 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 383 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 384 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 385 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 386 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 387 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 388 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 389 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 390 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
emilmont 77:869cf507173a 391 /**
emilmont 77:869cf507173a 392 * @}
emilmont 77:869cf507173a 393 */
Kojto 99:dbbf35b96557 394
emilmont 77:869cf507173a 395 /**
emilmont 77:869cf507173a 396 * @}
emilmont 77:869cf507173a 397 */
Kojto 99:dbbf35b96557 398
emilmont 77:869cf507173a 399 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 400
bogdanm 85:024bf7f99721 401 /** @brief Reset DMA handle state
bogdanm 85:024bf7f99721 402 * @param __HANDLE__: specifies the DMA handle.
bogdanm 85:024bf7f99721 403 * @retval None
bogdanm 85:024bf7f99721 404 */
bogdanm 85:024bf7f99721 405 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 85:024bf7f99721 406
emilmont 77:869cf507173a 407 /**
emilmont 77:869cf507173a 408 * @brief Return the current DMA Stream FIFO filled level.
emilmont 77:869cf507173a 409 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 410 * @retval The FIFO filling state.
emilmont 77:869cf507173a 411 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
emilmont 77:869cf507173a 412 * and not empty.
emilmont 77:869cf507173a 413 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
emilmont 77:869cf507173a 414 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
emilmont 77:869cf507173a 415 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
emilmont 77:869cf507173a 416 * - DMA_FIFOStatus_Empty: when FIFO is empty
emilmont 77:869cf507173a 417 * - DMA_FIFOStatus_Full: when FIFO is full
emilmont 77:869cf507173a 418 */
emilmont 77:869cf507173a 419 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
emilmont 77:869cf507173a 420
emilmont 77:869cf507173a 421 /**
emilmont 77:869cf507173a 422 * @brief Enable the specified DMA Stream.
emilmont 77:869cf507173a 423 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 424 * @retval None
emilmont 77:869cf507173a 425 */
emilmont 77:869cf507173a 426 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
emilmont 77:869cf507173a 427
emilmont 77:869cf507173a 428 /**
emilmont 77:869cf507173a 429 * @brief Disable the specified DMA Stream.
emilmont 77:869cf507173a 430 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 431 * @retval None
emilmont 77:869cf507173a 432 */
emilmont 77:869cf507173a 433 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
emilmont 77:869cf507173a 434
emilmont 77:869cf507173a 435 /* Interrupt & Flag management */
emilmont 77:869cf507173a 436
emilmont 77:869cf507173a 437 /**
emilmont 77:869cf507173a 438 * @brief Return the current DMA Stream transfer complete flag.
emilmont 77:869cf507173a 439 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 440 * @retval The specified transfer complete flag index.
emilmont 77:869cf507173a 441 */
emilmont 77:869cf507173a 442 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
emilmont 77:869cf507173a 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 455 DMA_FLAG_TCIF3_7)
emilmont 77:869cf507173a 456
emilmont 77:869cf507173a 457 /**
emilmont 77:869cf507173a 458 * @brief Return the current DMA Stream half transfer complete flag.
emilmont 77:869cf507173a 459 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 460 * @retval The specified half transfer complete flag index.
emilmont 77:869cf507173a 461 */
emilmont 77:869cf507173a 462 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 475 DMA_FLAG_HTIF3_7)
emilmont 77:869cf507173a 476
emilmont 77:869cf507173a 477 /**
emilmont 77:869cf507173a 478 * @brief Return the current DMA Stream transfer error flag.
emilmont 77:869cf507173a 479 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 480 * @retval The specified transfer error flag index.
emilmont 77:869cf507173a 481 */
emilmont 77:869cf507173a 482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 495 DMA_FLAG_TEIF3_7)
emilmont 77:869cf507173a 496
emilmont 77:869cf507173a 497 /**
emilmont 77:869cf507173a 498 * @brief Return the current DMA Stream FIFO error flag.
emilmont 77:869cf507173a 499 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 500 * @retval The specified FIFO error flag index.
emilmont 77:869cf507173a 501 */
emilmont 77:869cf507173a 502 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 515 DMA_FLAG_FEIF3_7)
emilmont 77:869cf507173a 516
emilmont 77:869cf507173a 517 /**
emilmont 77:869cf507173a 518 * @brief Return the current DMA Stream direct mode error flag.
emilmont 77:869cf507173a 519 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 520 * @retval The specified direct mode error flag index.
emilmont 77:869cf507173a 521 */
emilmont 77:869cf507173a 522 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 523 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 535 DMA_FLAG_DMEIF3_7)
emilmont 77:869cf507173a 536
emilmont 77:869cf507173a 537 /**
emilmont 77:869cf507173a 538 * @brief Get the DMA Stream pending flags.
emilmont 77:869cf507173a 539 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 540 * @param __FLAG__: Get the specified flag.
emilmont 77:869cf507173a 541 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 542 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
emilmont 77:869cf507173a 543 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
emilmont 77:869cf507173a 544 * @arg DMA_FLAG_TEIFx: Transfer error flag.
emilmont 77:869cf507173a 545 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
emilmont 77:869cf507173a 546 * @arg DMA_FLAG_FEIFx: FIFO error flag.
emilmont 77:869cf507173a 547 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
emilmont 77:869cf507173a 548 * @retval The state of FLAG (SET or RESET).
emilmont 77:869cf507173a 549 */
emilmont 77:869cf507173a 550 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
emilmont 77:869cf507173a 551 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
emilmont 77:869cf507173a 552 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
emilmont 77:869cf507173a 553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
emilmont 77:869cf507173a 554
emilmont 77:869cf507173a 555 /**
emilmont 77:869cf507173a 556 * @brief Clear the DMA Stream pending flags.
emilmont 77:869cf507173a 557 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 558 * @param __FLAG__: specifies the flag to clear.
emilmont 77:869cf507173a 559 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 560 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
emilmont 77:869cf507173a 561 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
emilmont 77:869cf507173a 562 * @arg DMA_FLAG_TEIFx: Transfer error flag.
emilmont 77:869cf507173a 563 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
emilmont 77:869cf507173a 564 * @arg DMA_FLAG_FEIFx: FIFO error flag.
emilmont 77:869cf507173a 565 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
emilmont 77:869cf507173a 566 * @retval None
emilmont 77:869cf507173a 567 */
emilmont 77:869cf507173a 568 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 90:cb3d968589d8 569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto 90:cb3d968589d8 570 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto 90:cb3d968589d8 571 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
emilmont 77:869cf507173a 572
emilmont 77:869cf507173a 573 /**
emilmont 77:869cf507173a 574 * @brief Enable the specified DMA Stream interrupts.
emilmont 77:869cf507173a 575 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
emilmont 77:869cf507173a 577 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 578 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 580 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 581 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 582 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 583 * @retval None
emilmont 77:869cf507173a 584 */
emilmont 77:869cf507173a 585 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 586 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
emilmont 77:869cf507173a 587
emilmont 77:869cf507173a 588 /**
emilmont 77:869cf507173a 589 * @brief Disable the specified DMA Stream interrupts.
emilmont 77:869cf507173a 590 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 591 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
emilmont 77:869cf507173a 592 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 593 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 594 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 595 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 596 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 597 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 598 * @retval None
emilmont 77:869cf507173a 599 */
emilmont 77:869cf507173a 600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 601 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
emilmont 77:869cf507173a 602
emilmont 77:869cf507173a 603 /**
Kojto 106:ba1f97679dad 604 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
emilmont 77:869cf507173a 605 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 606 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
emilmont 77:869cf507173a 607 * This parameter can be one of the following values:
emilmont 77:869cf507173a 608 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 609 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 610 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 611 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 612 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 613 * @retval The state of DMA_IT.
emilmont 77:869cf507173a 614 */
bogdanm 81:7d30d6019079 615 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 616 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
emilmont 77:869cf507173a 617 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
emilmont 77:869cf507173a 618
emilmont 77:869cf507173a 619 /**
emilmont 77:869cf507173a 620 * @brief Writes the number of data units to be transferred on the DMA Stream.
emilmont 77:869cf507173a 621 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 622 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
emilmont 77:869cf507173a 623 * Number of data items depends only on the Peripheral data format.
emilmont 77:869cf507173a 624 *
emilmont 77:869cf507173a 625 * @note If Peripheral data format is Bytes: number of data units is equal
emilmont 77:869cf507173a 626 * to total number of bytes to be transferred.
emilmont 77:869cf507173a 627 *
emilmont 77:869cf507173a 628 * @note If Peripheral data format is Half-Word: number of data units is
emilmont 77:869cf507173a 629 * equal to total number of bytes to be transferred / 2.
emilmont 77:869cf507173a 630 *
emilmont 77:869cf507173a 631 * @note If Peripheral data format is Word: number of data units is equal
emilmont 77:869cf507173a 632 * to total number of bytes to be transferred / 4.
emilmont 77:869cf507173a 633 *
emilmont 77:869cf507173a 634 * @retval The number of remaining data units in the current DMAy Streamx transfer.
emilmont 77:869cf507173a 635 */
emilmont 77:869cf507173a 636 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
emilmont 77:869cf507173a 637
emilmont 77:869cf507173a 638 /**
emilmont 77:869cf507173a 639 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
emilmont 77:869cf507173a 640 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 641 *
emilmont 77:869cf507173a 642 * @retval The number of remaining data units in the current DMA Stream transfer.
emilmont 77:869cf507173a 643 */
emilmont 77:869cf507173a 644 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
emilmont 77:869cf507173a 645
emilmont 77:869cf507173a 646
emilmont 77:869cf507173a 647 /* Include DMA HAL Extension module */
emilmont 77:869cf507173a 648 #include "stm32f4xx_hal_dma_ex.h"
emilmont 77:869cf507173a 649
emilmont 77:869cf507173a 650 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 651
Kojto 99:dbbf35b96557 652 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 99:dbbf35b96557 653 * @brief DMA Exported functions
Kojto 99:dbbf35b96557 654 * @{
Kojto 99:dbbf35b96557 655 */
Kojto 99:dbbf35b96557 656
Kojto 99:dbbf35b96557 657 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 658 * @brief Initialization and de-initialization functions
Kojto 99:dbbf35b96557 659 * @{
Kojto 99:dbbf35b96557 660 */
emilmont 77:869cf507173a 661 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 662 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 663 /**
Kojto 99:dbbf35b96557 664 * @}
Kojto 99:dbbf35b96557 665 */
emilmont 77:869cf507173a 666
Kojto 99:dbbf35b96557 667 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 99:dbbf35b96557 668 * @brief I/O operation functions
Kojto 99:dbbf35b96557 669 * @{
Kojto 99:dbbf35b96557 670 */
emilmont 77:869cf507173a 671 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
emilmont 77:869cf507173a 672 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
emilmont 77:869cf507173a 673 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 674 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 675 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
emilmont 77:869cf507173a 676 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 677 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 678 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
Kojto 122:f9eeca106725 679 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
Kojto 122:f9eeca106725 680
Kojto 99:dbbf35b96557 681 /**
Kojto 99:dbbf35b96557 682 * @}
Kojto 99:dbbf35b96557 683 */
emilmont 77:869cf507173a 684
Kojto 99:dbbf35b96557 685 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 99:dbbf35b96557 686 * @brief Peripheral State functions
Kojto 99:dbbf35b96557 687 * @{
Kojto 99:dbbf35b96557 688 */
emilmont 77:869cf507173a 689 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 691 /**
Kojto 99:dbbf35b96557 692 * @}
Kojto 99:dbbf35b96557 693 */
Kojto 99:dbbf35b96557 694 /**
Kojto 99:dbbf35b96557 695 * @}
Kojto 99:dbbf35b96557 696 */
Kojto 99:dbbf35b96557 697 /* Private Constants -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 698 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 99:dbbf35b96557 699 * @brief DMA private defines and constants
Kojto 99:dbbf35b96557 700 * @{
Kojto 99:dbbf35b96557 701 */
Kojto 99:dbbf35b96557 702 /**
Kojto 99:dbbf35b96557 703 * @}
Kojto 99:dbbf35b96557 704 */
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 707 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 99:dbbf35b96557 708 * @brief DMA private macros
Kojto 99:dbbf35b96557 709 * @{
Kojto 99:dbbf35b96557 710 */
Kojto 99:dbbf35b96557 711 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 99:dbbf35b96557 712 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 99:dbbf35b96557 713 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 99:dbbf35b96557 714 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 99:dbbf35b96557 715 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 99:dbbf35b96557 716 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 99:dbbf35b96557 717 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 99:dbbf35b96557 718 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 99:dbbf35b96557 719
Kojto 99:dbbf35b96557 720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 99:dbbf35b96557 721 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 99:dbbf35b96557 722 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 99:dbbf35b96557 723
Kojto 122:f9eeca106725 724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
Kojto 99:dbbf35b96557 725
Kojto 99:dbbf35b96557 726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 99:dbbf35b96557 727 ((STATE) == DMA_PINC_DISABLE))
Kojto 99:dbbf35b96557 728
Kojto 99:dbbf35b96557 729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 99:dbbf35b96557 730 ((STATE) == DMA_MINC_DISABLE))
Kojto 99:dbbf35b96557 731
Kojto 99:dbbf35b96557 732 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 733 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 734 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 99:dbbf35b96557 735
Kojto 99:dbbf35b96557 736 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 737 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 738 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 99:dbbf35b96557 739
Kojto 99:dbbf35b96557 740 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 99:dbbf35b96557 741 ((MODE) == DMA_CIRCULAR) || \
Kojto 99:dbbf35b96557 742 ((MODE) == DMA_PFCTRL))
Kojto 99:dbbf35b96557 743
Kojto 99:dbbf35b96557 744 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 99:dbbf35b96557 745 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 99:dbbf35b96557 746 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 99:dbbf35b96557 747 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 99:dbbf35b96557 748
Kojto 99:dbbf35b96557 749 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 99:dbbf35b96557 750 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 99:dbbf35b96557 751
Kojto 99:dbbf35b96557 752 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 99:dbbf35b96557 753 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 99:dbbf35b96557 754 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 99:dbbf35b96557 755 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 99:dbbf35b96557 756
Kojto 99:dbbf35b96557 757 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 99:dbbf35b96557 758 ((BURST) == DMA_MBURST_INC4) || \
Kojto 99:dbbf35b96557 759 ((BURST) == DMA_MBURST_INC8) || \
Kojto 99:dbbf35b96557 760 ((BURST) == DMA_MBURST_INC16))
Kojto 99:dbbf35b96557 761
Kojto 99:dbbf35b96557 762 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 99:dbbf35b96557 763 ((BURST) == DMA_PBURST_INC4) || \
Kojto 99:dbbf35b96557 764 ((BURST) == DMA_PBURST_INC8) || \
Kojto 99:dbbf35b96557 765 ((BURST) == DMA_PBURST_INC16))
Kojto 99:dbbf35b96557 766 /**
Kojto 99:dbbf35b96557 767 * @}
Kojto 99:dbbf35b96557 768 */
Kojto 99:dbbf35b96557 769
Kojto 99:dbbf35b96557 770 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 771 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 99:dbbf35b96557 772 * @brief DMA private functions
Kojto 99:dbbf35b96557 773 * @{
Kojto 99:dbbf35b96557 774 */
Kojto 99:dbbf35b96557 775 /**
Kojto 99:dbbf35b96557 776 * @}
Kojto 99:dbbf35b96557 777 */
emilmont 77:869cf507173a 778
emilmont 77:869cf507173a 779 /**
emilmont 77:869cf507173a 780 * @}
emilmont 77:869cf507173a 781 */
emilmont 77:869cf507173a 782
emilmont 77:869cf507173a 783 /**
emilmont 77:869cf507173a 784 * @}
emilmont 77:869cf507173a 785 */
emilmont 77:869cf507173a 786
emilmont 77:869cf507173a 787 #ifdef __cplusplus
emilmont 77:869cf507173a 788 }
emilmont 77:869cf507173a 789 #endif
emilmont 77:869cf507173a 790
emilmont 77:869cf507173a 791 #endif /* __STM32F4xx_HAL_DMA_H */
emilmont 77:869cf507173a 792
emilmont 77:869cf507173a 793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/