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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F334R8/stm32f334x8.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
92:4fc01daae5a5 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f334x8.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.3.0
Kojto 122:f9eeca106725 6 * @date 29-April-2015
Kojto 122:f9eeca106725 7 * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
bogdanm 86:04dd9b1680ae 8 *
bogdanm 86:04dd9b1680ae 9 * This file contains:
bogdanm 86:04dd9b1680ae 10 * - Data structures and the address mapping for all peripherals
bogdanm 86:04dd9b1680ae 11 * - Peripheral's registers declarations and bits definition
bogdanm 86:04dd9b1680ae 12 * - Macros to access peripheral’s registers hardware
bogdanm 86:04dd9b1680ae 13 *
bogdanm 86:04dd9b1680ae 14 ******************************************************************************
bogdanm 86:04dd9b1680ae 15 * @attention
bogdanm 86:04dd9b1680ae 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 18 *
bogdanm 86:04dd9b1680ae 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 20 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 22 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 25 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 27 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 28 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 29 *
bogdanm 86:04dd9b1680ae 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 40 *
bogdanm 86:04dd9b1680ae 41 ******************************************************************************
bogdanm 86:04dd9b1680ae 42 */
bogdanm 86:04dd9b1680ae 43
bogdanm 86:04dd9b1680ae 44 /** @addtogroup CMSIS_Device
bogdanm 86:04dd9b1680ae 45 * @{
bogdanm 86:04dd9b1680ae 46 */
bogdanm 86:04dd9b1680ae 47
bogdanm 86:04dd9b1680ae 48 /** @addtogroup stm32f334x8
bogdanm 86:04dd9b1680ae 49 * @{
bogdanm 86:04dd9b1680ae 50 */
bogdanm 86:04dd9b1680ae 51
bogdanm 86:04dd9b1680ae 52 #ifndef __STM32F334x8_H
bogdanm 86:04dd9b1680ae 53 #define __STM32F334x8_H
bogdanm 86:04dd9b1680ae 54
bogdanm 86:04dd9b1680ae 55 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 56 extern "C" {
bogdanm 86:04dd9b1680ae 57 #endif /* __cplusplus */
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 86:04dd9b1680ae 60 * @{
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62
bogdanm 86:04dd9b1680ae 63 /**
bogdanm 86:04dd9b1680ae 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 86:04dd9b1680ae 65 */
Kojto 122:f9eeca106725 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
Kojto 122:f9eeca106725 67 #define __MPU_PRESENT 0U /*!< STM32F334x8 devices do not provide an MPU */
Kojto 122:f9eeca106725 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 70 #ifndef __FPU_PRESENT
Kojto 122:f9eeca106725 71 #define __FPU_PRESENT 1U /*!< STM32F334x8 devices provide an FPU */
Kojto 122:f9eeca106725 72 #endif
bogdanm 86:04dd9b1680ae 73 /**
bogdanm 86:04dd9b1680ae 74 * @}
bogdanm 86:04dd9b1680ae 75 */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 86:04dd9b1680ae 78 * @{
bogdanm 86:04dd9b1680ae 79 */
bogdanm 86:04dd9b1680ae 80
bogdanm 86:04dd9b1680ae 81 /**
Kojto 122:f9eeca106725 82 * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
bogdanm 86:04dd9b1680ae 83 * in @ref Library_configuration_section
bogdanm 86:04dd9b1680ae 84 */
bogdanm 86:04dd9b1680ae 85 typedef enum
bogdanm 86:04dd9b1680ae 86 {
bogdanm 86:04dd9b1680ae 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 86:04dd9b1680ae 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 122:f9eeca106725 89 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
bogdanm 86:04dd9b1680ae 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 86:04dd9b1680ae 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 86:04dd9b1680ae 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 86:04dd9b1680ae 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 86:04dd9b1680ae 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 86:04dd9b1680ae 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 86:04dd9b1680ae 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 86:04dd9b1680ae 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 86:04dd9b1680ae 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 86:04dd9b1680ae 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 86:04dd9b1680ae 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
bogdanm 86:04dd9b1680ae 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
bogdanm 86:04dd9b1680ae 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 86:04dd9b1680ae 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 86:04dd9b1680ae 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 86:04dd9b1680ae 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 86:04dd9b1680ae 106 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
bogdanm 86:04dd9b1680ae 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 86:04dd9b1680ae 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 86:04dd9b1680ae 109 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
bogdanm 86:04dd9b1680ae 110 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
bogdanm 86:04dd9b1680ae 111 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
bogdanm 86:04dd9b1680ae 112 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
bogdanm 86:04dd9b1680ae 113 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
bogdanm 86:04dd9b1680ae 114 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
bogdanm 86:04dd9b1680ae 115 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
bogdanm 86:04dd9b1680ae 116 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
Kojto 122:f9eeca106725 117 CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
Kojto 122:f9eeca106725 118 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
bogdanm 86:04dd9b1680ae 119 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
bogdanm 86:04dd9b1680ae 120 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
bogdanm 86:04dd9b1680ae 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 86:04dd9b1680ae 122 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 86:04dd9b1680ae 123 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 86:04dd9b1680ae 124 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 86:04dd9b1680ae 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 86:04dd9b1680ae 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 86:04dd9b1680ae 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 86:04dd9b1680ae 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
bogdanm 86:04dd9b1680ae 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 86:04dd9b1680ae 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 86:04dd9b1680ae 131 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
bogdanm 86:04dd9b1680ae 132 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
bogdanm 86:04dd9b1680ae 133 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
bogdanm 86:04dd9b1680ae 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 122:f9eeca106725 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
Kojto 122:f9eeca106725 136 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
bogdanm 86:04dd9b1680ae 137 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
Kojto 122:f9eeca106725 138 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
Kojto 122:f9eeca106725 139 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
bogdanm 86:04dd9b1680ae 140 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
bogdanm 86:04dd9b1680ae 141 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
bogdanm 86:04dd9b1680ae 142 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
bogdanm 86:04dd9b1680ae 143 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
bogdanm 86:04dd9b1680ae 144 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
bogdanm 86:04dd9b1680ae 145 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
bogdanm 86:04dd9b1680ae 146 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
Kojto 122:f9eeca106725 147 FPU_IRQn = 81, /*!< Floating point Interrupt */
bogdanm 86:04dd9b1680ae 148 } IRQn_Type;
bogdanm 86:04dd9b1680ae 149
bogdanm 86:04dd9b1680ae 150 /**
bogdanm 86:04dd9b1680ae 151 * @}
bogdanm 86:04dd9b1680ae 152 */
bogdanm 86:04dd9b1680ae 153
bogdanm 86:04dd9b1680ae 154 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 86:04dd9b1680ae 155 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
bogdanm 86:04dd9b1680ae 156 #include <stdint.h>
bogdanm 86:04dd9b1680ae 157
bogdanm 86:04dd9b1680ae 158 /** @addtogroup Peripheral_registers_structures
bogdanm 86:04dd9b1680ae 159 * @{
bogdanm 86:04dd9b1680ae 160 */
bogdanm 86:04dd9b1680ae 161
bogdanm 86:04dd9b1680ae 162 /**
bogdanm 86:04dd9b1680ae 163 * @brief Analog to Digital Converter
bogdanm 86:04dd9b1680ae 164 */
bogdanm 86:04dd9b1680ae 165
bogdanm 86:04dd9b1680ae 166 typedef struct
bogdanm 86:04dd9b1680ae 167 {
bogdanm 86:04dd9b1680ae 168 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 169 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 170 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 171 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 172 uint32_t RESERVED0; /*!< Reserved, 0x010 */
bogdanm 86:04dd9b1680ae 173 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 174 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 175 uint32_t RESERVED1; /*!< Reserved, 0x01C */
bogdanm 86:04dd9b1680ae 176 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 177 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 178 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 179 uint32_t RESERVED2; /*!< Reserved, 0x02C */
bogdanm 86:04dd9b1680ae 180 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 181 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 182 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 183 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 184 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 185 uint32_t RESERVED3; /*!< Reserved, 0x044 */
bogdanm 86:04dd9b1680ae 186 uint32_t RESERVED4; /*!< Reserved, 0x048 */
bogdanm 86:04dd9b1680ae 187 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 188 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
bogdanm 86:04dd9b1680ae 189 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 190 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
bogdanm 86:04dd9b1680ae 191 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
bogdanm 86:04dd9b1680ae 192 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
bogdanm 86:04dd9b1680ae 193 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
bogdanm 86:04dd9b1680ae 194 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
bogdanm 86:04dd9b1680ae 195 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
bogdanm 86:04dd9b1680ae 196 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
bogdanm 86:04dd9b1680ae 197 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
bogdanm 86:04dd9b1680ae 198 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
bogdanm 86:04dd9b1680ae 199 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
bogdanm 86:04dd9b1680ae 200 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
bogdanm 86:04dd9b1680ae 201 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
bogdanm 86:04dd9b1680ae 202 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
bogdanm 86:04dd9b1680ae 203 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
bogdanm 86:04dd9b1680ae 204 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
bogdanm 86:04dd9b1680ae 205
bogdanm 86:04dd9b1680ae 206 } ADC_TypeDef;
bogdanm 86:04dd9b1680ae 207
bogdanm 86:04dd9b1680ae 208 typedef struct
bogdanm 86:04dd9b1680ae 209 {
bogdanm 86:04dd9b1680ae 210 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
bogdanm 86:04dd9b1680ae 211 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
bogdanm 86:04dd9b1680ae 212 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
bogdanm 86:04dd9b1680ae 213 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 86:04dd9b1680ae 214 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
bogdanm 86:04dd9b1680ae 215 } ADC_Common_TypeDef;
bogdanm 86:04dd9b1680ae 216
bogdanm 86:04dd9b1680ae 217 /**
bogdanm 86:04dd9b1680ae 218 * @brief Controller Area Network TxMailBox
bogdanm 86:04dd9b1680ae 219 */
bogdanm 86:04dd9b1680ae 220 typedef struct
bogdanm 86:04dd9b1680ae 221 {
bogdanm 86:04dd9b1680ae 222 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 86:04dd9b1680ae 223 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 86:04dd9b1680ae 224 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 86:04dd9b1680ae 225 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 86:04dd9b1680ae 226 } CAN_TxMailBox_TypeDef;
bogdanm 86:04dd9b1680ae 227
bogdanm 86:04dd9b1680ae 228 /**
bogdanm 86:04dd9b1680ae 229 * @brief Controller Area Network FIFOMailBox
bogdanm 86:04dd9b1680ae 230 */
bogdanm 86:04dd9b1680ae 231 typedef struct
bogdanm 86:04dd9b1680ae 232 {
bogdanm 86:04dd9b1680ae 233 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 86:04dd9b1680ae 234 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 86:04dd9b1680ae 235 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 86:04dd9b1680ae 236 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 86:04dd9b1680ae 237 } CAN_FIFOMailBox_TypeDef;
bogdanm 86:04dd9b1680ae 238
bogdanm 86:04dd9b1680ae 239 /**
bogdanm 86:04dd9b1680ae 240 * @brief Controller Area Network FilterRegister
bogdanm 86:04dd9b1680ae 241 */
bogdanm 86:04dd9b1680ae 242 typedef struct
bogdanm 86:04dd9b1680ae 243 {
bogdanm 86:04dd9b1680ae 244 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 86:04dd9b1680ae 245 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 86:04dd9b1680ae 246 } CAN_FilterRegister_TypeDef;
bogdanm 86:04dd9b1680ae 247
bogdanm 86:04dd9b1680ae 248 /**
bogdanm 86:04dd9b1680ae 249 * @brief Controller Area Network
bogdanm 86:04dd9b1680ae 250 */
bogdanm 86:04dd9b1680ae 251 typedef struct
bogdanm 86:04dd9b1680ae 252 {
bogdanm 86:04dd9b1680ae 253 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 254 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 255 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 256 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 257 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 258 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 259 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 260 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 261 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 86:04dd9b1680ae 262 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 86:04dd9b1680ae 263 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 86:04dd9b1680ae 264 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 86:04dd9b1680ae 265 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 86:04dd9b1680ae 266 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 86:04dd9b1680ae 267 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 86:04dd9b1680ae 268 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 86:04dd9b1680ae 269 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 86:04dd9b1680ae 270 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 86:04dd9b1680ae 271 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 86:04dd9b1680ae 272 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 86:04dd9b1680ae 273 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 86:04dd9b1680ae 274 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 86:04dd9b1680ae 275 } CAN_TypeDef;
bogdanm 86:04dd9b1680ae 276
bogdanm 86:04dd9b1680ae 277 /**
bogdanm 86:04dd9b1680ae 278 * @brief Analog Comparators
bogdanm 86:04dd9b1680ae 279 */
Kojto 122:f9eeca106725 280 typedef struct
Kojto 122:f9eeca106725 281 {
Kojto 122:f9eeca106725 282 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 283 } COMP_TypeDef;
bogdanm 86:04dd9b1680ae 284
bogdanm 86:04dd9b1680ae 285 typedef struct
bogdanm 86:04dd9b1680ae 286 {
Kojto 122:f9eeca106725 287 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
Kojto 122:f9eeca106725 288 } COMP_Common_TypeDef;
bogdanm 86:04dd9b1680ae 289
bogdanm 86:04dd9b1680ae 290 /**
bogdanm 86:04dd9b1680ae 291 * @brief CRC calculation unit
bogdanm 86:04dd9b1680ae 292 */
bogdanm 86:04dd9b1680ae 293
bogdanm 86:04dd9b1680ae 294 typedef struct
bogdanm 86:04dd9b1680ae 295 {
bogdanm 86:04dd9b1680ae 296 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 297 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 298 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 86:04dd9b1680ae 299 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 86:04dd9b1680ae 300 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 301 uint32_t RESERVED2; /*!< Reserved, 0x0C */
bogdanm 86:04dd9b1680ae 302 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 303 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 304 } CRC_TypeDef;
bogdanm 86:04dd9b1680ae 305
bogdanm 86:04dd9b1680ae 306 /**
bogdanm 86:04dd9b1680ae 307 * @brief Digital to Analog Converter
bogdanm 86:04dd9b1680ae 308 */
bogdanm 86:04dd9b1680ae 309
bogdanm 86:04dd9b1680ae 310 typedef struct
bogdanm 86:04dd9b1680ae 311 {
bogdanm 86:04dd9b1680ae 312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 326 } DAC_TypeDef;
bogdanm 86:04dd9b1680ae 327
bogdanm 86:04dd9b1680ae 328 /**
bogdanm 86:04dd9b1680ae 329 * @brief Debug MCU
bogdanm 86:04dd9b1680ae 330 */
bogdanm 86:04dd9b1680ae 331
bogdanm 86:04dd9b1680ae 332 typedef struct
bogdanm 86:04dd9b1680ae 333 {
bogdanm 86:04dd9b1680ae 334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 338 }DBGMCU_TypeDef;
bogdanm 86:04dd9b1680ae 339
bogdanm 86:04dd9b1680ae 340 /**
bogdanm 86:04dd9b1680ae 341 * @brief DMA Controller
bogdanm 86:04dd9b1680ae 342 */
bogdanm 86:04dd9b1680ae 343
bogdanm 86:04dd9b1680ae 344 typedef struct
bogdanm 86:04dd9b1680ae 345 {
bogdanm 86:04dd9b1680ae 346 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 86:04dd9b1680ae 347 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 86:04dd9b1680ae 348 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 86:04dd9b1680ae 349 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 86:04dd9b1680ae 350 } DMA_Channel_TypeDef;
bogdanm 86:04dd9b1680ae 351
bogdanm 86:04dd9b1680ae 352 typedef struct
bogdanm 86:04dd9b1680ae 353 {
Kojto 122:f9eeca106725 354 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 355 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 356 } DMA_TypeDef;
bogdanm 86:04dd9b1680ae 357
bogdanm 86:04dd9b1680ae 358 /**
bogdanm 86:04dd9b1680ae 359 * @brief External Interrupt/Event Controller
bogdanm 86:04dd9b1680ae 360 */
bogdanm 86:04dd9b1680ae 361
bogdanm 86:04dd9b1680ae 362 typedef struct
bogdanm 86:04dd9b1680ae 363 {
Kojto 122:f9eeca106725 364 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 122:f9eeca106725 365 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 122:f9eeca106725 366 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 122:f9eeca106725 367 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 122:f9eeca106725 368 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 122:f9eeca106725 369 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 122:f9eeca106725 370 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 122:f9eeca106725 371 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 372 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
Kojto 122:f9eeca106725 373 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
Kojto 122:f9eeca106725 374 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
Kojto 122:f9eeca106725 375 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
Kojto 122:f9eeca106725 376 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
Kojto 122:f9eeca106725 377 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 378 }EXTI_TypeDef;
bogdanm 86:04dd9b1680ae 379
bogdanm 86:04dd9b1680ae 380 /**
bogdanm 86:04dd9b1680ae 381 * @brief FLASH Registers
bogdanm 86:04dd9b1680ae 382 */
bogdanm 86:04dd9b1680ae 383
bogdanm 86:04dd9b1680ae 384 typedef struct
bogdanm 86:04dd9b1680ae 385 {
bogdanm 86:04dd9b1680ae 386 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 387 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 388 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 389 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 390 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 391 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 392 uint32_t RESERVED; /*!< Reserved, 0x18 */
bogdanm 86:04dd9b1680ae 393 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 394 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 395
bogdanm 86:04dd9b1680ae 396 } FLASH_TypeDef;
bogdanm 86:04dd9b1680ae 397
bogdanm 86:04dd9b1680ae 398 /**
bogdanm 86:04dd9b1680ae 399 * @brief Option Bytes Registers
bogdanm 86:04dd9b1680ae 400 */
bogdanm 86:04dd9b1680ae 401 typedef struct
bogdanm 86:04dd9b1680ae 402 {
bogdanm 86:04dd9b1680ae 403 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 404 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
bogdanm 86:04dd9b1680ae 405 uint16_t RESERVED0; /*!< Reserved, 0x04 */
bogdanm 86:04dd9b1680ae 406 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 86:04dd9b1680ae 407 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 408 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 409 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 410 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
bogdanm 86:04dd9b1680ae 411 } OB_TypeDef;
bogdanm 86:04dd9b1680ae 412
bogdanm 86:04dd9b1680ae 413 /**
bogdanm 86:04dd9b1680ae 414 * @brief General Purpose I/O
bogdanm 86:04dd9b1680ae 415 */
bogdanm 86:04dd9b1680ae 416
bogdanm 86:04dd9b1680ae 417 typedef struct
bogdanm 86:04dd9b1680ae 418 {
bogdanm 86:04dd9b1680ae 419 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 420 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 421 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 422 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 423 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 424 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 122:f9eeca106725 425 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
bogdanm 86:04dd9b1680ae 426 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 427 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 86:04dd9b1680ae 428 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 429 }GPIO_TypeDef;
bogdanm 86:04dd9b1680ae 430
bogdanm 86:04dd9b1680ae 431 /**
bogdanm 86:04dd9b1680ae 432 * @brief Operational Amplifier (OPAMP)
bogdanm 86:04dd9b1680ae 433 */
bogdanm 86:04dd9b1680ae 434
bogdanm 86:04dd9b1680ae 435 typedef struct
bogdanm 86:04dd9b1680ae 436 {
bogdanm 86:04dd9b1680ae 437 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 438 } OPAMP_TypeDef;
bogdanm 86:04dd9b1680ae 439
Kojto 122:f9eeca106725 440 /**
bogdanm 86:04dd9b1680ae 441 * @brief High resolution Timer (HRTIM)
bogdanm 86:04dd9b1680ae 442 */
bogdanm 86:04dd9b1680ae 443 /* HRTIM master registers definition */
bogdanm 86:04dd9b1680ae 444 typedef struct
bogdanm 86:04dd9b1680ae 445 {
bogdanm 86:04dd9b1680ae 446 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 447 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 448 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 449 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 450 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 451 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 452 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 453 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 454 uint32_t RESERVED0; /*!< Reserved, 0x20 */
bogdanm 86:04dd9b1680ae 455 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 456 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 457 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 458 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
bogdanm 86:04dd9b1680ae 459 }HRTIM_Master_TypeDef;
bogdanm 86:04dd9b1680ae 460
bogdanm 86:04dd9b1680ae 461 /* HRTIM Timer A to E registers definition */
bogdanm 86:04dd9b1680ae 462 typedef struct
bogdanm 86:04dd9b1680ae 463 {
bogdanm 86:04dd9b1680ae 464 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 465 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 466 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 467 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 468 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 469 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 470 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 471 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 472 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 473 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 474 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 475 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 476 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 477 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 478 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 479 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 480 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 481 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 482 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 483 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 484 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 485 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 486 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 487 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
bogdanm 86:04dd9b1680ae 488 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 489 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
bogdanm 86:04dd9b1680ae 490 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
bogdanm 86:04dd9b1680ae 491 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
bogdanm 86:04dd9b1680ae 492 }HRTIM_Timerx_TypeDef;
bogdanm 86:04dd9b1680ae 493
bogdanm 86:04dd9b1680ae 494 /* HRTIM common register definition */
bogdanm 86:04dd9b1680ae 495 typedef struct
bogdanm 86:04dd9b1680ae 496 {
bogdanm 86:04dd9b1680ae 497 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 498 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 499 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 500 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 501 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 502 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 503 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 504 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 505 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 506 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 507 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 508 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 509 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 510 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 511 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 512 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 513 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 514 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 515 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 516 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 517 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 518 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 519 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 520 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
bogdanm 86:04dd9b1680ae 521 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 522 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
bogdanm 86:04dd9b1680ae 523 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
bogdanm 86:04dd9b1680ae 524 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
bogdanm 86:04dd9b1680ae 525 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
bogdanm 86:04dd9b1680ae 526 }HRTIM_Common_TypeDef;
bogdanm 86:04dd9b1680ae 527
bogdanm 86:04dd9b1680ae 528 /* HRTIM register definition */
bogdanm 86:04dd9b1680ae 529 typedef struct {
bogdanm 86:04dd9b1680ae 530 HRTIM_Master_TypeDef sMasterRegs;
bogdanm 86:04dd9b1680ae 531 HRTIM_Timerx_TypeDef sTimerxRegs[5];
bogdanm 86:04dd9b1680ae 532 uint32_t RESERVED0[32];
bogdanm 86:04dd9b1680ae 533 HRTIM_Common_TypeDef sCommonRegs;
bogdanm 86:04dd9b1680ae 534 }HRTIM_TypeDef;
bogdanm 86:04dd9b1680ae 535
bogdanm 86:04dd9b1680ae 536 /**
bogdanm 86:04dd9b1680ae 537 * @brief System configuration controller
bogdanm 86:04dd9b1680ae 538 */
bogdanm 86:04dd9b1680ae 539
bogdanm 86:04dd9b1680ae 540 typedef struct
bogdanm 86:04dd9b1680ae 541 {
Kojto 122:f9eeca106725 542 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 543 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
Kojto 122:f9eeca106725 544 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
Kojto 122:f9eeca106725 545 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 546 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 86:04dd9b1680ae 547 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
bogdanm 86:04dd9b1680ae 548 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
bogdanm 86:04dd9b1680ae 549 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
bogdanm 86:04dd9b1680ae 550 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
bogdanm 86:04dd9b1680ae 551 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
bogdanm 86:04dd9b1680ae 552 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
bogdanm 86:04dd9b1680ae 553 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
bogdanm 86:04dd9b1680ae 554 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
bogdanm 86:04dd9b1680ae 555 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
bogdanm 86:04dd9b1680ae 556 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
bogdanm 86:04dd9b1680ae 557 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
bogdanm 86:04dd9b1680ae 558 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
bogdanm 86:04dd9b1680ae 559 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 560 } SYSCFG_TypeDef;
bogdanm 86:04dd9b1680ae 561
bogdanm 86:04dd9b1680ae 562 /**
bogdanm 86:04dd9b1680ae 563 * @brief Inter-integrated Circuit Interface
bogdanm 86:04dd9b1680ae 564 */
bogdanm 86:04dd9b1680ae 565
bogdanm 86:04dd9b1680ae 566 typedef struct
bogdanm 86:04dd9b1680ae 567 {
bogdanm 86:04dd9b1680ae 568 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 569 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 570 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 571 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 572 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 573 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 574 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 575 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 576 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 577 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 578 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 579 }I2C_TypeDef;
bogdanm 86:04dd9b1680ae 580
bogdanm 86:04dd9b1680ae 581 /**
bogdanm 86:04dd9b1680ae 582 * @brief Independent WATCHDOG
bogdanm 86:04dd9b1680ae 583 */
bogdanm 86:04dd9b1680ae 584
bogdanm 86:04dd9b1680ae 585 typedef struct
bogdanm 86:04dd9b1680ae 586 {
bogdanm 86:04dd9b1680ae 587 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 588 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 589 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 590 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 591 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 592 } IWDG_TypeDef;
bogdanm 86:04dd9b1680ae 593
bogdanm 86:04dd9b1680ae 594 /**
bogdanm 86:04dd9b1680ae 595 * @brief Power Control
bogdanm 86:04dd9b1680ae 596 */
bogdanm 86:04dd9b1680ae 597
bogdanm 86:04dd9b1680ae 598 typedef struct
bogdanm 86:04dd9b1680ae 599 {
bogdanm 86:04dd9b1680ae 600 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 601 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 602 } PWR_TypeDef;
bogdanm 86:04dd9b1680ae 603
bogdanm 86:04dd9b1680ae 604 /**
bogdanm 86:04dd9b1680ae 605 * @brief Reset and Clock Control
bogdanm 86:04dd9b1680ae 606 */
bogdanm 86:04dd9b1680ae 607 typedef struct
bogdanm 86:04dd9b1680ae 608 {
bogdanm 86:04dd9b1680ae 609 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 610 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 611 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 612 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 613 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 614 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 615 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 616 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 617 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 618 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 619 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 620 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 621 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 622 } RCC_TypeDef;
bogdanm 86:04dd9b1680ae 623
bogdanm 86:04dd9b1680ae 624 /**
bogdanm 86:04dd9b1680ae 625 * @brief Real-Time Clock
bogdanm 86:04dd9b1680ae 626 */
bogdanm 86:04dd9b1680ae 627
bogdanm 86:04dd9b1680ae 628 typedef struct
bogdanm 86:04dd9b1680ae 629 {
bogdanm 86:04dd9b1680ae 630 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 631 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 632 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 633 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 634 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 635 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 636 uint32_t RESERVED0; /*!< Reserved, 0x18 */
bogdanm 86:04dd9b1680ae 637 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 638 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 639 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 640 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 641 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 642 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 643 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 644 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 645 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 646 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 647 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 648 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 649 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 86:04dd9b1680ae 650 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 651 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 652 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 653 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 86:04dd9b1680ae 654 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 655 } RTC_TypeDef;
bogdanm 86:04dd9b1680ae 656
bogdanm 86:04dd9b1680ae 657
bogdanm 86:04dd9b1680ae 658 /**
bogdanm 86:04dd9b1680ae 659 * @brief Serial Peripheral Interface
bogdanm 86:04dd9b1680ae 660 */
bogdanm 86:04dd9b1680ae 661
bogdanm 86:04dd9b1680ae 662 typedef struct
bogdanm 86:04dd9b1680ae 663 {
bogdanm 86:04dd9b1680ae 664 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 665 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 666 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 667 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 668 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 669 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 670 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 671 } SPI_TypeDef;
bogdanm 86:04dd9b1680ae 672
bogdanm 86:04dd9b1680ae 673 /**
bogdanm 86:04dd9b1680ae 674 * @brief TIM
bogdanm 86:04dd9b1680ae 675 */
bogdanm 86:04dd9b1680ae 676 typedef struct
bogdanm 86:04dd9b1680ae 677 {
bogdanm 86:04dd9b1680ae 678 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 679 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 680 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 681 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 682 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 683 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 684 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 685 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 686 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 687 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 688 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 689 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 690 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 691 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 692 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 693 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 694 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 695 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 696 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 697 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 698 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 699 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 700 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 701 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
bogdanm 86:04dd9b1680ae 702 } TIM_TypeDef;
bogdanm 86:04dd9b1680ae 703
bogdanm 86:04dd9b1680ae 704 /**
bogdanm 86:04dd9b1680ae 705 * @brief Touch Sensing Controller (TSC)
bogdanm 86:04dd9b1680ae 706 */
bogdanm 86:04dd9b1680ae 707 typedef struct
bogdanm 86:04dd9b1680ae 708 {
bogdanm 86:04dd9b1680ae 709 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 710 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 711 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 712 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 713 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 714 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 715 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 716 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 717 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 718 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 719 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 720 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 721 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 722 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 86:04dd9b1680ae 723 } TSC_TypeDef;
bogdanm 86:04dd9b1680ae 724
bogdanm 86:04dd9b1680ae 725 /**
bogdanm 86:04dd9b1680ae 726 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 86:04dd9b1680ae 727 */
bogdanm 86:04dd9b1680ae 728
bogdanm 86:04dd9b1680ae 729 typedef struct
bogdanm 86:04dd9b1680ae 730 {
bogdanm 86:04dd9b1680ae 731 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 732 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 733 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 734 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 735 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 736 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 737 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 738 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 739 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 740 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 741 uint16_t RESERVED1; /*!< Reserved, 0x26 */
bogdanm 86:04dd9b1680ae 742 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 743 uint16_t RESERVED2; /*!< Reserved, 0x2A */
bogdanm 86:04dd9b1680ae 744 } USART_TypeDef;
bogdanm 86:04dd9b1680ae 745
bogdanm 86:04dd9b1680ae 746 /**
bogdanm 86:04dd9b1680ae 747 * @brief Window WATCHDOG
bogdanm 86:04dd9b1680ae 748 */
bogdanm 86:04dd9b1680ae 749 typedef struct
bogdanm 86:04dd9b1680ae 750 {
bogdanm 86:04dd9b1680ae 751 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 752 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 753 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 754 } WWDG_TypeDef;
bogdanm 86:04dd9b1680ae 755
bogdanm 86:04dd9b1680ae 756 /** @addtogroup Peripheral_memory_map
bogdanm 86:04dd9b1680ae 757 * @{
bogdanm 86:04dd9b1680ae 758 */
bogdanm 86:04dd9b1680ae 759
Kojto 122:f9eeca106725 760 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
Kojto 122:f9eeca106725 761 #define CCMDATARAM_BASE ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region */
Kojto 122:f9eeca106725 762 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
Kojto 122:f9eeca106725 763 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
Kojto 122:f9eeca106725 764 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
Kojto 122:f9eeca106725 765 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
bogdanm 86:04dd9b1680ae 766
bogdanm 86:04dd9b1680ae 767
bogdanm 86:04dd9b1680ae 768 /*!< Peripheral memory map */
bogdanm 86:04dd9b1680ae 769 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 770 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 771 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 772 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
Kojto 122:f9eeca106725 773 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000U)
bogdanm 86:04dd9b1680ae 774
bogdanm 86:04dd9b1680ae 775 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 776 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 777 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 778 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
Kojto 122:f9eeca106725 779 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
Kojto 122:f9eeca106725 780 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
Kojto 122:f9eeca106725 781 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
Kojto 122:f9eeca106725 782 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 783 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
Kojto 122:f9eeca106725 784 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
Kojto 122:f9eeca106725 785 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
Kojto 122:f9eeca106725 786 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400U)
Kojto 122:f9eeca106725 787 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
Kojto 122:f9eeca106725 788 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400U)
Kojto 122:f9eeca106725 789 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800U)
bogdanm 86:04dd9b1680ae 790 #define DAC_BASE DAC1_BASE
bogdanm 86:04dd9b1680ae 791
bogdanm 86:04dd9b1680ae 792 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 793 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 794 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020U)
Kojto 122:f9eeca106725 795 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028U)
Kojto 122:f9eeca106725 796 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030U)
bogdanm 86:04dd9b1680ae 797 #define COMP_BASE COMP2_BASE
Kojto 122:f9eeca106725 798 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CU)
bogdanm 86:04dd9b1680ae 799 #define OPAMP_BASE OPAMP2_BASE
Kojto 122:f9eeca106725 800 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 801 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
Kojto 122:f9eeca106725 802 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 803 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
Kojto 122:f9eeca106725 804 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
Kojto 122:f9eeca106725 805 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
Kojto 122:f9eeca106725 806 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
Kojto 122:f9eeca106725 807 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400U)
Kojto 122:f9eeca106725 808 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080U)
Kojto 122:f9eeca106725 809 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100U)
Kojto 122:f9eeca106725 810 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180U)
Kojto 122:f9eeca106725 811 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200U)
Kojto 122:f9eeca106725 812 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280U)
Kojto 122:f9eeca106725 813 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380U)
bogdanm 86:04dd9b1680ae 814
bogdanm 86:04dd9b1680ae 815 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 816 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 817 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008U)
Kojto 122:f9eeca106725 818 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CU)
Kojto 122:f9eeca106725 819 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030U)
Kojto 122:f9eeca106725 820 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044U)
Kojto 122:f9eeca106725 821 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058U)
Kojto 122:f9eeca106725 822 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CU)
Kojto 122:f9eeca106725 823 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080U)
Kojto 122:f9eeca106725 824 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000U)
Kojto 122:f9eeca106725 825 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
Kojto 122:f9eeca106725 826 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< Flash Option Bytes base address */
Kojto 122:f9eeca106725 827 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
Kojto 122:f9eeca106725 828 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
Kojto 122:f9eeca106725 829 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 830 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000U)
bogdanm 86:04dd9b1680ae 831
bogdanm 86:04dd9b1680ae 832 /*!< AHB2 peripherals */
Kojto 122:f9eeca106725 833 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 834 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 835 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800U)
Kojto 122:f9eeca106725 836 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00U)
Kojto 122:f9eeca106725 837 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400U)
bogdanm 86:04dd9b1680ae 838
bogdanm 86:04dd9b1680ae 839 /*!< AHB3 peripherals */
Kojto 122:f9eeca106725 840 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 841 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100U)
Kojto 122:f9eeca106725 842 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300U)
Kojto 122:f9eeca106725 843
Kojto 122:f9eeca106725 844 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
bogdanm 86:04dd9b1680ae 845 /**
bogdanm 86:04dd9b1680ae 846 * @}
bogdanm 86:04dd9b1680ae 847 */
bogdanm 86:04dd9b1680ae 848
bogdanm 86:04dd9b1680ae 849 /** @addtogroup Peripheral_declaration
bogdanm 86:04dd9b1680ae 850 * @{
bogdanm 86:04dd9b1680ae 851 */
bogdanm 86:04dd9b1680ae 852 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
bogdanm 86:04dd9b1680ae 853 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
bogdanm 86:04dd9b1680ae 854 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
bogdanm 86:04dd9b1680ae 855 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
bogdanm 86:04dd9b1680ae 856 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
bogdanm 86:04dd9b1680ae 857 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
bogdanm 86:04dd9b1680ae 858 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
bogdanm 86:04dd9b1680ae 859 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 86:04dd9b1680ae 860 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 86:04dd9b1680ae 861 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 86:04dd9b1680ae 862 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 86:04dd9b1680ae 863 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 86:04dd9b1680ae 864 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 86:04dd9b1680ae 865 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 86:04dd9b1680ae 866 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 86:04dd9b1680ae 867 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 86:04dd9b1680ae 868 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 122:f9eeca106725 869 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
bogdanm 86:04dd9b1680ae 870 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 122:f9eeca106725 871 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 86:04dd9b1680ae 872 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
bogdanm 86:04dd9b1680ae 873 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
bogdanm 86:04dd9b1680ae 874 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm 86:04dd9b1680ae 875 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
bogdanm 86:04dd9b1680ae 876 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
Kojto 122:f9eeca106725 877 /* Legacy define */
bogdanm 86:04dd9b1680ae 878 #define COMP ((COMP_TypeDef *) COMP_BASE)
Kojto 122:f9eeca106725 879 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
bogdanm 86:04dd9b1680ae 880 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
Kojto 122:f9eeca106725 881 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 86:04dd9b1680ae 882 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 86:04dd9b1680ae 883 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 86:04dd9b1680ae 884 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 86:04dd9b1680ae 885 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 86:04dd9b1680ae 886 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm 86:04dd9b1680ae 887 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm 86:04dd9b1680ae 888 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm 86:04dd9b1680ae 889 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 86:04dd9b1680ae 890 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 86:04dd9b1680ae 891 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 86:04dd9b1680ae 892 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 86:04dd9b1680ae 893 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 86:04dd9b1680ae 894 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 86:04dd9b1680ae 895 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 86:04dd9b1680ae 896 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 86:04dd9b1680ae 897 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 86:04dd9b1680ae 898 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 86:04dd9b1680ae 899 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 86:04dd9b1680ae 900 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 86:04dd9b1680ae 901 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 86:04dd9b1680ae 902 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 86:04dd9b1680ae 903 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 86:04dd9b1680ae 904 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 86:04dd9b1680ae 905 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 86:04dd9b1680ae 906 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 86:04dd9b1680ae 907 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 86:04dd9b1680ae 908 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 86:04dd9b1680ae 909 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 122:f9eeca106725 910 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
Kojto 122:f9eeca106725 911 /* Legacy defines */
Kojto 122:f9eeca106725 912 #define ADC1_2_COMMON ADC12_COMMON
Kojto 122:f9eeca106725 913
bogdanm 86:04dd9b1680ae 914 /**
bogdanm 86:04dd9b1680ae 915 * @}
bogdanm 86:04dd9b1680ae 916 */
bogdanm 86:04dd9b1680ae 917
bogdanm 86:04dd9b1680ae 918 /** @addtogroup Exported_constants
bogdanm 86:04dd9b1680ae 919 * @{
bogdanm 86:04dd9b1680ae 920 */
bogdanm 86:04dd9b1680ae 921
bogdanm 86:04dd9b1680ae 922 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 86:04dd9b1680ae 923 * @{
bogdanm 86:04dd9b1680ae 924 */
bogdanm 86:04dd9b1680ae 925
bogdanm 86:04dd9b1680ae 926 /******************************************************************************/
bogdanm 86:04dd9b1680ae 927 /* Peripheral Registers_Bits_Definition */
bogdanm 86:04dd9b1680ae 928 /******************************************************************************/
bogdanm 86:04dd9b1680ae 929
bogdanm 86:04dd9b1680ae 930 /******************************************************************************/
bogdanm 86:04dd9b1680ae 931 /* */
bogdanm 86:04dd9b1680ae 932 /* Analog to Digital Converter SAR (ADC) */
bogdanm 86:04dd9b1680ae 933 /* */
bogdanm 86:04dd9b1680ae 934 /******************************************************************************/
Kojto 122:f9eeca106725 935
Kojto 122:f9eeca106725 936 #define ADC5_V1_1 /*!< ADC IP version */
Kojto 122:f9eeca106725 937
Kojto 122:f9eeca106725 938 /*
Kojto 122:f9eeca106725 939 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 940 */
Kojto 122:f9eeca106725 941 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
Kojto 122:f9eeca106725 942
bogdanm 86:04dd9b1680ae 943 /******************** Bit definition for ADC_ISR register ********************/
Kojto 122:f9eeca106725 944 #define ADC_ISR_ADRDY_Pos (0U)
Kojto 122:f9eeca106725 945 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 946 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
Kojto 122:f9eeca106725 947 #define ADC_ISR_EOSMP_Pos (1U)
Kojto 122:f9eeca106725 948 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 949 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
Kojto 122:f9eeca106725 950 #define ADC_ISR_EOC_Pos (2U)
Kojto 122:f9eeca106725 951 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 952 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 953 #define ADC_ISR_EOS_Pos (3U)
Kojto 122:f9eeca106725 954 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 955 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 956 #define ADC_ISR_OVR_Pos (4U)
Kojto 122:f9eeca106725 957 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 958 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
Kojto 122:f9eeca106725 959 #define ADC_ISR_JEOC_Pos (5U)
Kojto 122:f9eeca106725 960 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 961 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
Kojto 122:f9eeca106725 962 #define ADC_ISR_JEOS_Pos (6U)
Kojto 122:f9eeca106725 963 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 964 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 965 #define ADC_ISR_AWD1_Pos (7U)
Kojto 122:f9eeca106725 966 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 967 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
Kojto 122:f9eeca106725 968 #define ADC_ISR_AWD2_Pos (8U)
Kojto 122:f9eeca106725 969 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 970 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
Kojto 122:f9eeca106725 971 #define ADC_ISR_AWD3_Pos (9U)
Kojto 122:f9eeca106725 972 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 973 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
Kojto 122:f9eeca106725 974 #define ADC_ISR_JQOVF_Pos (10U)
Kojto 122:f9eeca106725 975 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 976 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
Kojto 122:f9eeca106725 977
Kojto 122:f9eeca106725 978 /* Legacy defines */
Kojto 122:f9eeca106725 979 #define ADC_ISR_ADRD (ADC_ISR_ADRDY)
bogdanm 86:04dd9b1680ae 980
bogdanm 86:04dd9b1680ae 981 /******************** Bit definition for ADC_IER register ********************/
Kojto 122:f9eeca106725 982 #define ADC_IER_ADRDYIE_Pos (0U)
Kojto 122:f9eeca106725 983 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 984 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
Kojto 122:f9eeca106725 985 #define ADC_IER_EOSMPIE_Pos (1U)
Kojto 122:f9eeca106725 986 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 987 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
Kojto 122:f9eeca106725 988 #define ADC_IER_EOCIE_Pos (2U)
Kojto 122:f9eeca106725 989 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 990 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
Kojto 122:f9eeca106725 991 #define ADC_IER_EOSIE_Pos (3U)
Kojto 122:f9eeca106725 992 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 993 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
Kojto 122:f9eeca106725 994 #define ADC_IER_OVRIE_Pos (4U)
Kojto 122:f9eeca106725 995 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 996 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
Kojto 122:f9eeca106725 997 #define ADC_IER_JEOCIE_Pos (5U)
Kojto 122:f9eeca106725 998 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 999 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
Kojto 122:f9eeca106725 1000 #define ADC_IER_JEOSIE_Pos (6U)
Kojto 122:f9eeca106725 1001 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1002 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
Kojto 122:f9eeca106725 1003 #define ADC_IER_AWD1IE_Pos (7U)
Kojto 122:f9eeca106725 1004 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1005 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
Kojto 122:f9eeca106725 1006 #define ADC_IER_AWD2IE_Pos (8U)
Kojto 122:f9eeca106725 1007 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1008 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
Kojto 122:f9eeca106725 1009 #define ADC_IER_AWD3IE_Pos (9U)
Kojto 122:f9eeca106725 1010 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1011 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
Kojto 122:f9eeca106725 1012 #define ADC_IER_JQOVFIE_Pos (10U)
Kojto 122:f9eeca106725 1013 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1014 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
Kojto 122:f9eeca106725 1015
Kojto 122:f9eeca106725 1016 /* Legacy defines */
Kojto 122:f9eeca106725 1017 #define ADC_IER_RDY (ADC_IER_ADRDYIE)
Kojto 122:f9eeca106725 1018 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
Kojto 122:f9eeca106725 1019 #define ADC_IER_EOC (ADC_IER_EOCIE)
Kojto 122:f9eeca106725 1020 #define ADC_IER_EOS (ADC_IER_EOSIE)
Kojto 122:f9eeca106725 1021 #define ADC_IER_OVR (ADC_IER_OVRIE)
Kojto 122:f9eeca106725 1022 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
Kojto 122:f9eeca106725 1023 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
Kojto 122:f9eeca106725 1024 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
Kojto 122:f9eeca106725 1025 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
Kojto 122:f9eeca106725 1026 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
Kojto 122:f9eeca106725 1027 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
bogdanm 86:04dd9b1680ae 1028
bogdanm 86:04dd9b1680ae 1029 /******************** Bit definition for ADC_CR register ********************/
Kojto 122:f9eeca106725 1030 #define ADC_CR_ADEN_Pos (0U)
Kojto 122:f9eeca106725 1031 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1032 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
Kojto 122:f9eeca106725 1033 #define ADC_CR_ADDIS_Pos (1U)
Kojto 122:f9eeca106725 1034 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1035 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
Kojto 122:f9eeca106725 1036 #define ADC_CR_ADSTART_Pos (2U)
Kojto 122:f9eeca106725 1037 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1038 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
Kojto 122:f9eeca106725 1039 #define ADC_CR_JADSTART_Pos (3U)
Kojto 122:f9eeca106725 1040 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1041 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
Kojto 122:f9eeca106725 1042 #define ADC_CR_ADSTP_Pos (4U)
Kojto 122:f9eeca106725 1043 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1044 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
Kojto 122:f9eeca106725 1045 #define ADC_CR_JADSTP_Pos (5U)
Kojto 122:f9eeca106725 1046 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1047 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
Kojto 122:f9eeca106725 1048 #define ADC_CR_ADVREGEN_Pos (28U)
Kojto 122:f9eeca106725 1049 #define ADC_CR_ADVREGEN_Msk (0x3U << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 1050 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
Kojto 122:f9eeca106725 1051 #define ADC_CR_ADVREGEN_0 (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1052 #define ADC_CR_ADVREGEN_1 (0x2U << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1053 #define ADC_CR_ADCALDIF_Pos (30U)
Kojto 122:f9eeca106725 1054 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1055 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
Kojto 122:f9eeca106725 1056 #define ADC_CR_ADCAL_Pos (31U)
Kojto 122:f9eeca106725 1057 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1058 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
Kojto 122:f9eeca106725 1059
Kojto 122:f9eeca106725 1060 /******************** Bit definition for ADC_CFGR register ******************/
Kojto 122:f9eeca106725 1061 #define ADC_CFGR_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 1062 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1063 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */
Kojto 122:f9eeca106725 1064 #define ADC_CFGR_DMACFG_Pos (1U)
Kojto 122:f9eeca106725 1065 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1066 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */
Kojto 122:f9eeca106725 1067
Kojto 122:f9eeca106725 1068 #define ADC_CFGR_RES_Pos (3U)
Kojto 122:f9eeca106725 1069 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 1070 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
Kojto 122:f9eeca106725 1071 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1072 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1073
Kojto 122:f9eeca106725 1074 #define ADC_CFGR_ALIGN_Pos (5U)
Kojto 122:f9eeca106725 1075 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1076 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
Kojto 122:f9eeca106725 1077
Kojto 122:f9eeca106725 1078 #define ADC_CFGR_EXTSEL_Pos (6U)
Kojto 122:f9eeca106725 1079 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
Kojto 122:f9eeca106725 1080 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
Kojto 122:f9eeca106725 1081 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1082 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1083 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1084 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1085
Kojto 122:f9eeca106725 1086 #define ADC_CFGR_EXTEN_Pos (10U)
Kojto 122:f9eeca106725 1087 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 1088 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
Kojto 122:f9eeca106725 1089 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1090 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1091
Kojto 122:f9eeca106725 1092 #define ADC_CFGR_OVRMOD_Pos (12U)
Kojto 122:f9eeca106725 1093 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1094 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
Kojto 122:f9eeca106725 1095 #define ADC_CFGR_CONT_Pos (13U)
Kojto 122:f9eeca106725 1096 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1097 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
Kojto 122:f9eeca106725 1098 #define ADC_CFGR_AUTDLY_Pos (14U)
Kojto 122:f9eeca106725 1099 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1100 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
Kojto 122:f9eeca106725 1101
Kojto 122:f9eeca106725 1102 #define ADC_CFGR_DISCEN_Pos (16U)
Kojto 122:f9eeca106725 1103 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1104 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
Kojto 122:f9eeca106725 1105
Kojto 122:f9eeca106725 1106 #define ADC_CFGR_DISCNUM_Pos (17U)
Kojto 122:f9eeca106725 1107 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 1108 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
Kojto 122:f9eeca106725 1109 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1110 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1111 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1112
Kojto 122:f9eeca106725 1113 #define ADC_CFGR_JDISCEN_Pos (20U)
Kojto 122:f9eeca106725 1114 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1115 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
Kojto 122:f9eeca106725 1116 #define ADC_CFGR_JQM_Pos (21U)
Kojto 122:f9eeca106725 1117 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1118 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
Kojto 122:f9eeca106725 1119 #define ADC_CFGR_AWD1SGL_Pos (22U)
Kojto 122:f9eeca106725 1120 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1121 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
Kojto 122:f9eeca106725 1122 #define ADC_CFGR_AWD1EN_Pos (23U)
Kojto 122:f9eeca106725 1123 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1124 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
Kojto 122:f9eeca106725 1125 #define ADC_CFGR_JAWD1EN_Pos (24U)
Kojto 122:f9eeca106725 1126 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1127 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
Kojto 122:f9eeca106725 1128 #define ADC_CFGR_JAUTO_Pos (25U)
Kojto 122:f9eeca106725 1129 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1130 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
Kojto 122:f9eeca106725 1131
Kojto 122:f9eeca106725 1132 #define ADC_CFGR_AWD1CH_Pos (26U)
Kojto 122:f9eeca106725 1133 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1134 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
Kojto 122:f9eeca106725 1135 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1136 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1137 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1138 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1139 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1140
Kojto 122:f9eeca106725 1141 /* Legacy defines */
Kojto 122:f9eeca106725 1142 #define ADC_CFGR_AUTOFF_Pos (15U)
Kojto 122:f9eeca106725 1143 #define ADC_CFGR_AUTOFF_Msk (0x1U << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1144 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */
Kojto 122:f9eeca106725 1145
Kojto 122:f9eeca106725 1146 /******************** Bit definition for ADC_SMPR1 register *****************/
Kojto 122:f9eeca106725 1147 #define ADC_SMPR1_SMP0_Pos (0U)
Kojto 122:f9eeca106725 1148 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 1149 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
Kojto 122:f9eeca106725 1150 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1151 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1152 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1153
Kojto 122:f9eeca106725 1154 #define ADC_SMPR1_SMP1_Pos (3U)
Kojto 122:f9eeca106725 1155 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 1156 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
Kojto 122:f9eeca106725 1157 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1158 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1159 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1160
Kojto 122:f9eeca106725 1161 #define ADC_SMPR1_SMP2_Pos (6U)
Kojto 122:f9eeca106725 1162 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 1163 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
Kojto 122:f9eeca106725 1164 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1165 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1166 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1167
Kojto 122:f9eeca106725 1168 #define ADC_SMPR1_SMP3_Pos (9U)
Kojto 122:f9eeca106725 1169 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 1170 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
Kojto 122:f9eeca106725 1171 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1172 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1173 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1174
Kojto 122:f9eeca106725 1175 #define ADC_SMPR1_SMP4_Pos (12U)
Kojto 122:f9eeca106725 1176 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 1177 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
Kojto 122:f9eeca106725 1178 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1179 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1180 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1181
Kojto 122:f9eeca106725 1182 #define ADC_SMPR1_SMP5_Pos (15U)
Kojto 122:f9eeca106725 1183 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
Kojto 122:f9eeca106725 1184 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
Kojto 122:f9eeca106725 1185 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1186 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1187 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1188
Kojto 122:f9eeca106725 1189 #define ADC_SMPR1_SMP6_Pos (18U)
Kojto 122:f9eeca106725 1190 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
Kojto 122:f9eeca106725 1191 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
Kojto 122:f9eeca106725 1192 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1193 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1194 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1195
Kojto 122:f9eeca106725 1196 #define ADC_SMPR1_SMP7_Pos (21U)
Kojto 122:f9eeca106725 1197 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
Kojto 122:f9eeca106725 1198 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
Kojto 122:f9eeca106725 1199 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1200 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1201 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1202
Kojto 122:f9eeca106725 1203 #define ADC_SMPR1_SMP8_Pos (24U)
Kojto 122:f9eeca106725 1204 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 1205 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
Kojto 122:f9eeca106725 1206 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1207 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1208 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1209
Kojto 122:f9eeca106725 1210 #define ADC_SMPR1_SMP9_Pos (27U)
Kojto 122:f9eeca106725 1211 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
Kojto 122:f9eeca106725 1212 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
Kojto 122:f9eeca106725 1213 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1214 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1215 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1216
Kojto 122:f9eeca106725 1217 /******************** Bit definition for ADC_SMPR2 register *****************/
Kojto 122:f9eeca106725 1218 #define ADC_SMPR2_SMP10_Pos (0U)
Kojto 122:f9eeca106725 1219 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 1220 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
Kojto 122:f9eeca106725 1221 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1222 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1223 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1224
Kojto 122:f9eeca106725 1225 #define ADC_SMPR2_SMP11_Pos (3U)
Kojto 122:f9eeca106725 1226 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 1227 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
Kojto 122:f9eeca106725 1228 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1229 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1230 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1231
Kojto 122:f9eeca106725 1232 #define ADC_SMPR2_SMP12_Pos (6U)
Kojto 122:f9eeca106725 1233 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 1234 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
Kojto 122:f9eeca106725 1235 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1236 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1237 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1238
Kojto 122:f9eeca106725 1239 #define ADC_SMPR2_SMP13_Pos (9U)
Kojto 122:f9eeca106725 1240 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 1241 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
Kojto 122:f9eeca106725 1242 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1243 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1244 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1245
Kojto 122:f9eeca106725 1246 #define ADC_SMPR2_SMP14_Pos (12U)
Kojto 122:f9eeca106725 1247 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 1248 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
Kojto 122:f9eeca106725 1249 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1250 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1251 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1252
Kojto 122:f9eeca106725 1253 #define ADC_SMPR2_SMP15_Pos (15U)
Kojto 122:f9eeca106725 1254 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
Kojto 122:f9eeca106725 1255 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
Kojto 122:f9eeca106725 1256 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1257 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1258 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1259
Kojto 122:f9eeca106725 1260 #define ADC_SMPR2_SMP16_Pos (18U)
Kojto 122:f9eeca106725 1261 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
Kojto 122:f9eeca106725 1262 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
Kojto 122:f9eeca106725 1263 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1264 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1265 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1266
Kojto 122:f9eeca106725 1267 #define ADC_SMPR2_SMP17_Pos (21U)
Kojto 122:f9eeca106725 1268 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
Kojto 122:f9eeca106725 1269 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
Kojto 122:f9eeca106725 1270 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1271 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1272 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1273
Kojto 122:f9eeca106725 1274 #define ADC_SMPR2_SMP18_Pos (24U)
Kojto 122:f9eeca106725 1275 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 1276 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
Kojto 122:f9eeca106725 1277 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1278 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1279 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1280
Kojto 122:f9eeca106725 1281 /******************** Bit definition for ADC_TR1 register *******************/
Kojto 122:f9eeca106725 1282 #define ADC_TR1_LT1_Pos (0U)
Kojto 122:f9eeca106725 1283 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1284 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
Kojto 122:f9eeca106725 1285 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1286 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1287 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1288 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1289 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1290 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1291 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1292 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1293 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1294 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1295 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1296 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1297
Kojto 122:f9eeca106725 1298 #define ADC_TR1_HT1_Pos (16U)
Kojto 122:f9eeca106725 1299 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 1300 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
Kojto 122:f9eeca106725 1301 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1302 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1303 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1304 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1305 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1306 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1307 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1308 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1309 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1310 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1311 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1312 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1313
Kojto 122:f9eeca106725 1314 /******************** Bit definition for ADC_TR2 register *******************/
Kojto 122:f9eeca106725 1315 #define ADC_TR2_LT2_Pos (0U)
Kojto 122:f9eeca106725 1316 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1317 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
Kojto 122:f9eeca106725 1318 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1319 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1320 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1321 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1322 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1323 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1324 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1325 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1326
Kojto 122:f9eeca106725 1327 #define ADC_TR2_HT2_Pos (16U)
Kojto 122:f9eeca106725 1328 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1329 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
Kojto 122:f9eeca106725 1330 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1331 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1332 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1333 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1334 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1335 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1336 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1337 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1338
Kojto 122:f9eeca106725 1339 /******************** Bit definition for ADC_TR3 register *******************/
Kojto 122:f9eeca106725 1340 #define ADC_TR3_LT3_Pos (0U)
Kojto 122:f9eeca106725 1341 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1342 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
Kojto 122:f9eeca106725 1343 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1344 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1345 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1346 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1347 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1348 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1349 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1350 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1351
Kojto 122:f9eeca106725 1352 #define ADC_TR3_HT3_Pos (16U)
Kojto 122:f9eeca106725 1353 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1354 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
Kojto 122:f9eeca106725 1355 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1356 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1357 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1358 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1359 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1360 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1361 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1362 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1363
Kojto 122:f9eeca106725 1364 /******************** Bit definition for ADC_SQR1 register ******************/
Kojto 122:f9eeca106725 1365 #define ADC_SQR1_L_Pos (0U)
Kojto 122:f9eeca106725 1366 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1367 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
Kojto 122:f9eeca106725 1368 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1369 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1370 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1371 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1372
Kojto 122:f9eeca106725 1373 #define ADC_SQR1_SQ1_Pos (6U)
Kojto 122:f9eeca106725 1374 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1375 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
Kojto 122:f9eeca106725 1376 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1377 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1378 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1379 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1380 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1381
Kojto 122:f9eeca106725 1382 #define ADC_SQR1_SQ2_Pos (12U)
Kojto 122:f9eeca106725 1383 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1384 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
Kojto 122:f9eeca106725 1385 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1386 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1387 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1388 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1389 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1390
Kojto 122:f9eeca106725 1391 #define ADC_SQR1_SQ3_Pos (18U)
Kojto 122:f9eeca106725 1392 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1393 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
Kojto 122:f9eeca106725 1394 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1395 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1396 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1397 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1398 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1399
Kojto 122:f9eeca106725 1400 #define ADC_SQR1_SQ4_Pos (24U)
Kojto 122:f9eeca106725 1401 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1402 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
Kojto 122:f9eeca106725 1403 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1404 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1405 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1406 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1407 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1408
Kojto 122:f9eeca106725 1409 /******************** Bit definition for ADC_SQR2 register ******************/
Kojto 122:f9eeca106725 1410 #define ADC_SQR2_SQ5_Pos (0U)
Kojto 122:f9eeca106725 1411 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1412 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
Kojto 122:f9eeca106725 1413 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1414 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1415 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1416 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1417 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1418
Kojto 122:f9eeca106725 1419 #define ADC_SQR2_SQ6_Pos (6U)
Kojto 122:f9eeca106725 1420 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1421 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
Kojto 122:f9eeca106725 1422 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1423 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1424 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1425 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1426 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1427
Kojto 122:f9eeca106725 1428 #define ADC_SQR2_SQ7_Pos (12U)
Kojto 122:f9eeca106725 1429 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1430 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
Kojto 122:f9eeca106725 1431 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1432 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1433 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1434 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1435 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1436
Kojto 122:f9eeca106725 1437 #define ADC_SQR2_SQ8_Pos (18U)
Kojto 122:f9eeca106725 1438 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1439 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
Kojto 122:f9eeca106725 1440 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1441 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1442 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1443 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1444 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1445
Kojto 122:f9eeca106725 1446 #define ADC_SQR2_SQ9_Pos (24U)
Kojto 122:f9eeca106725 1447 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1448 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
Kojto 122:f9eeca106725 1449 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1450 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1451 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1452 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1453 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1454
Kojto 122:f9eeca106725 1455 /******************** Bit definition for ADC_SQR3 register ******************/
Kojto 122:f9eeca106725 1456 #define ADC_SQR3_SQ10_Pos (0U)
Kojto 122:f9eeca106725 1457 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1458 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
Kojto 122:f9eeca106725 1459 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1460 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1461 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1462 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1463 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1464
Kojto 122:f9eeca106725 1465 #define ADC_SQR3_SQ11_Pos (6U)
Kojto 122:f9eeca106725 1466 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1467 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
Kojto 122:f9eeca106725 1468 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1469 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1470 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1471 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1472 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1473
Kojto 122:f9eeca106725 1474 #define ADC_SQR3_SQ12_Pos (12U)
Kojto 122:f9eeca106725 1475 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1476 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
Kojto 122:f9eeca106725 1477 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1478 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1479 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1480 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1481 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1482
Kojto 122:f9eeca106725 1483 #define ADC_SQR3_SQ13_Pos (18U)
Kojto 122:f9eeca106725 1484 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1485 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
Kojto 122:f9eeca106725 1486 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1487 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1488 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1489 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1490 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1491
Kojto 122:f9eeca106725 1492 #define ADC_SQR3_SQ14_Pos (24U)
Kojto 122:f9eeca106725 1493 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1494 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
Kojto 122:f9eeca106725 1495 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1496 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1497 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1498 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1499 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1500
Kojto 122:f9eeca106725 1501 /******************** Bit definition for ADC_SQR4 register ******************/
Kojto 122:f9eeca106725 1502 #define ADC_SQR4_SQ15_Pos (0U)
Kojto 122:f9eeca106725 1503 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1504 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
Kojto 122:f9eeca106725 1505 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1506 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1507 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1508 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1509 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1510
Kojto 122:f9eeca106725 1511 #define ADC_SQR4_SQ16_Pos (6U)
Kojto 122:f9eeca106725 1512 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1513 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
Kojto 122:f9eeca106725 1514 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1515 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1516 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1517 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1518 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1519
bogdanm 86:04dd9b1680ae 1520 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1521 #define ADC_DR_RDATA_Pos (0U)
Kojto 122:f9eeca106725 1522 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1523 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
Kojto 122:f9eeca106725 1524 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1525 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1526 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1527 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1528 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1529 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1530 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1531 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1532 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1533 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1534 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1535 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1536 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1537 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1538 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1539 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1540
Kojto 122:f9eeca106725 1541 /******************** Bit definition for ADC_JSQR register ******************/
Kojto 122:f9eeca106725 1542 #define ADC_JSQR_JL_Pos (0U)
Kojto 122:f9eeca106725 1543 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1544 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
Kojto 122:f9eeca106725 1545 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1546 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1547
Kojto 122:f9eeca106725 1548 #define ADC_JSQR_JEXTSEL_Pos (2U)
Kojto 122:f9eeca106725 1549 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
Kojto 122:f9eeca106725 1550 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
Kojto 122:f9eeca106725 1551 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1552 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1553 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1554 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1555
Kojto 122:f9eeca106725 1556 #define ADC_JSQR_JEXTEN_Pos (6U)
Kojto 122:f9eeca106725 1557 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 1558 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
Kojto 122:f9eeca106725 1559 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1560 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1561
Kojto 122:f9eeca106725 1562 #define ADC_JSQR_JSQ1_Pos (8U)
Kojto 122:f9eeca106725 1563 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 1564 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
Kojto 122:f9eeca106725 1565 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1566 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1567 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1568 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1569 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1570
Kojto 122:f9eeca106725 1571 #define ADC_JSQR_JSQ2_Pos (14U)
Kojto 122:f9eeca106725 1572 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
Kojto 122:f9eeca106725 1573 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
Kojto 122:f9eeca106725 1574 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1575 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1576 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1577 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1578 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1579
Kojto 122:f9eeca106725 1580 #define ADC_JSQR_JSQ3_Pos (20U)
Kojto 122:f9eeca106725 1581 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
Kojto 122:f9eeca106725 1582 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
Kojto 122:f9eeca106725 1583 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1584 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1585 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1586 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1587 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1588
Kojto 122:f9eeca106725 1589 #define ADC_JSQR_JSQ4_Pos (26U)
Kojto 122:f9eeca106725 1590 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1591 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
Kojto 122:f9eeca106725 1592 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1593 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1594 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1595 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1596 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1597
Kojto 122:f9eeca106725 1598
Kojto 122:f9eeca106725 1599 /******************** Bit definition for ADC_OFR1 register ******************/
Kojto 122:f9eeca106725 1600 #define ADC_OFR1_OFFSET1_Pos (0U)
Kojto 122:f9eeca106725 1601 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1602 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
Kojto 122:f9eeca106725 1603 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1604 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1605 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1606 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1607 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1608 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1609 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1610 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1611 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1612 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1613 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1614 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1615
Kojto 122:f9eeca106725 1616 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
Kojto 122:f9eeca106725 1617 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1618 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
Kojto 122:f9eeca106725 1619 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1620 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1621 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1622 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1623 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1624
Kojto 122:f9eeca106725 1625 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
Kojto 122:f9eeca106725 1626 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1627 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
Kojto 122:f9eeca106725 1628
Kojto 122:f9eeca106725 1629 /******************** Bit definition for ADC_OFR2 register ******************/
Kojto 122:f9eeca106725 1630 #define ADC_OFR2_OFFSET2_Pos (0U)
Kojto 122:f9eeca106725 1631 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1632 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
Kojto 122:f9eeca106725 1633 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1634 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1635 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1636 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1637 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1638 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1639 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1640 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1641 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1642 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1643 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1644 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1645
Kojto 122:f9eeca106725 1646 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
Kojto 122:f9eeca106725 1647 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1648 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
Kojto 122:f9eeca106725 1649 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1650 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1651 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1652 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1653 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1654
Kojto 122:f9eeca106725 1655 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
Kojto 122:f9eeca106725 1656 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1657 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
Kojto 122:f9eeca106725 1658
Kojto 122:f9eeca106725 1659 /******************** Bit definition for ADC_OFR3 register ******************/
Kojto 122:f9eeca106725 1660 #define ADC_OFR3_OFFSET3_Pos (0U)
Kojto 122:f9eeca106725 1661 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1662 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
Kojto 122:f9eeca106725 1663 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1664 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1665 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1666 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1667 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1668 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1669 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1670 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1671 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1672 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1673 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1674 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1675
Kojto 122:f9eeca106725 1676 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
Kojto 122:f9eeca106725 1677 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1678 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
Kojto 122:f9eeca106725 1679 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1680 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1681 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1682 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1683 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1684
Kojto 122:f9eeca106725 1685 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
Kojto 122:f9eeca106725 1686 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1687 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
Kojto 122:f9eeca106725 1688
Kojto 122:f9eeca106725 1689 /******************** Bit definition for ADC_OFR4 register ******************/
Kojto 122:f9eeca106725 1690 #define ADC_OFR4_OFFSET4_Pos (0U)
Kojto 122:f9eeca106725 1691 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1692 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
Kojto 122:f9eeca106725 1693 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1694 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1695 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1696 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1697 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1698 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1699 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1700 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1701 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1702 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1703 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1704 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1705
Kojto 122:f9eeca106725 1706 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
Kojto 122:f9eeca106725 1707 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1708 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
Kojto 122:f9eeca106725 1709 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1710 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1711 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1712 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1713 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1714
Kojto 122:f9eeca106725 1715 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
Kojto 122:f9eeca106725 1716 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1717 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
Kojto 122:f9eeca106725 1718
Kojto 122:f9eeca106725 1719 /******************** Bit definition for ADC_JDR1 register ******************/
Kojto 122:f9eeca106725 1720 #define ADC_JDR1_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1721 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1722 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
Kojto 122:f9eeca106725 1723 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1724 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1725 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1726 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1727 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1728 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1729 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1730 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1731 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1732 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1733 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1734 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1735 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1736 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1737 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1738 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1739
Kojto 122:f9eeca106725 1740 /******************** Bit definition for ADC_JDR2 register ******************/
Kojto 122:f9eeca106725 1741 #define ADC_JDR2_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1742 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1743 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
Kojto 122:f9eeca106725 1744 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1745 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1746 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1747 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1748 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1749 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1750 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1751 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1752 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1753 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1754 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1755 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1756 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1757 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1758 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1759 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1760
Kojto 122:f9eeca106725 1761 /******************** Bit definition for ADC_JDR3 register ******************/
Kojto 122:f9eeca106725 1762 #define ADC_JDR3_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1763 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1764 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
Kojto 122:f9eeca106725 1765 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1766 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1767 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1768 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1769 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1770 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1771 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1772 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1773 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1774 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1775 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1776 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1777 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1778 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1779 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1780 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1781
Kojto 122:f9eeca106725 1782 /******************** Bit definition for ADC_JDR4 register ******************/
Kojto 122:f9eeca106725 1783 #define ADC_JDR4_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1784 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1785 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
Kojto 122:f9eeca106725 1786 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1787 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1788 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1789 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1790 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1791 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1792 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1793 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1794 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1795 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1796 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1797 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1798 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1799 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1800 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1801 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1802
Kojto 122:f9eeca106725 1803 /******************** Bit definition for ADC_AWD2CR register ****************/
Kojto 122:f9eeca106725 1804 #define ADC_AWD2CR_AWD2CH_Pos (0U)
Kojto 122:f9eeca106725 1805 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 1806 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
Kojto 122:f9eeca106725 1807 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1808 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1809 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1810 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1811 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1812 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1813 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1814 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1815 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1816 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1817 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1818 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1819 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1820 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1821 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1822 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1823 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1824 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1825 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1826
Kojto 122:f9eeca106725 1827 /******************** Bit definition for ADC_AWD3CR register ****************/
Kojto 122:f9eeca106725 1828 #define ADC_AWD3CR_AWD3CH_Pos (0U)
Kojto 122:f9eeca106725 1829 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 1830 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
Kojto 122:f9eeca106725 1831 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1832 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1833 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1834 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1835 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1836 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1837 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1838 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1839 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1840 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1841 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1842 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1843 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1844 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1845 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1846 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1847 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1848 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1849 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1850
Kojto 122:f9eeca106725 1851 /******************** Bit definition for ADC_DIFSEL register ****************/
Kojto 122:f9eeca106725 1852 #define ADC_DIFSEL_DIFSEL_Pos (0U)
Kojto 122:f9eeca106725 1853 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 1854 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
Kojto 122:f9eeca106725 1855 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1856 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1857 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1858 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1859 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1860 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1861 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1862 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1863 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1864 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1865 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1866 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1867 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1868 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1869 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1870 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1871 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1872 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1873 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1874
Kojto 122:f9eeca106725 1875 /******************** Bit definition for ADC_CALFACT register ***************/
Kojto 122:f9eeca106725 1876 #define ADC_CALFACT_CALFACT_S_Pos (0U)
Kojto 122:f9eeca106725 1877 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 1878 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
Kojto 122:f9eeca106725 1879 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1880 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1881 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1882 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1883 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1884 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1885 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1886
Kojto 122:f9eeca106725 1887 #define ADC_CALFACT_CALFACT_D_Pos (16U)
Kojto 122:f9eeca106725 1888 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 1889 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
Kojto 122:f9eeca106725 1890 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1891 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1892 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1893 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1894 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1895 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1896 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
bogdanm 86:04dd9b1680ae 1897
bogdanm 86:04dd9b1680ae 1898 /************************* ADC Common registers *****************************/
Kojto 122:f9eeca106725 1899 /*************** Bit definition for ADC12_COMMON_CSR register ***************/
Kojto 122:f9eeca106725 1900 #define ADC12_CSR_ADRDY_MST_Pos (0U)
Kojto 122:f9eeca106725 1901 #define ADC12_CSR_ADRDY_MST_Msk (0x1U << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1902 #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
Kojto 122:f9eeca106725 1903 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)
Kojto 122:f9eeca106725 1904 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1905 #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
Kojto 122:f9eeca106725 1906 #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)
Kojto 122:f9eeca106725 1907 #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1908 #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
Kojto 122:f9eeca106725 1909 #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)
Kojto 122:f9eeca106725 1910 #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1911 #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
Kojto 122:f9eeca106725 1912 #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)
Kojto 122:f9eeca106725 1913 #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1914 #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
Kojto 122:f9eeca106725 1915 #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)
Kojto 122:f9eeca106725 1916 #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1917 #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
Kojto 122:f9eeca106725 1918 #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)
Kojto 122:f9eeca106725 1919 #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1920 #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
Kojto 122:f9eeca106725 1921 #define ADC12_CSR_AWD1_MST_Pos (7U)
Kojto 122:f9eeca106725 1922 #define ADC12_CSR_AWD1_MST_Msk (0x1U << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1923 #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
Kojto 122:f9eeca106725 1924 #define ADC12_CSR_AWD2_MST_Pos (8U)
Kojto 122:f9eeca106725 1925 #define ADC12_CSR_AWD2_MST_Msk (0x1U << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1926 #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
Kojto 122:f9eeca106725 1927 #define ADC12_CSR_AWD3_MST_Pos (9U)
Kojto 122:f9eeca106725 1928 #define ADC12_CSR_AWD3_MST_Msk (0x1U << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1929 #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
Kojto 122:f9eeca106725 1930 #define ADC12_CSR_JQOVF_MST_Pos (10U)
Kojto 122:f9eeca106725 1931 #define ADC12_CSR_JQOVF_MST_Msk (0x1U << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1932 #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
Kojto 122:f9eeca106725 1933 #define ADC12_CSR_ADRDY_SLV_Pos (16U)
Kojto 122:f9eeca106725 1934 #define ADC12_CSR_ADRDY_SLV_Msk (0x1U << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1935 #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
Kojto 122:f9eeca106725 1936 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)
Kojto 122:f9eeca106725 1937 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1938 #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
Kojto 122:f9eeca106725 1939 #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)
Kojto 122:f9eeca106725 1940 #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1941 #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
Kojto 122:f9eeca106725 1942 #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)
Kojto 122:f9eeca106725 1943 #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1944 #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
Kojto 122:f9eeca106725 1945 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
Kojto 122:f9eeca106725 1946 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1947 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
Kojto 122:f9eeca106725 1948 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)
Kojto 122:f9eeca106725 1949 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1950 #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
Kojto 122:f9eeca106725 1951 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)
Kojto 122:f9eeca106725 1952 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1953 #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
Kojto 122:f9eeca106725 1954 #define ADC12_CSR_AWD1_SLV_Pos (23U)
Kojto 122:f9eeca106725 1955 #define ADC12_CSR_AWD1_SLV_Msk (0x1U << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1956 #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
Kojto 122:f9eeca106725 1957 #define ADC12_CSR_AWD2_SLV_Pos (24U)
Kojto 122:f9eeca106725 1958 #define ADC12_CSR_AWD2_SLV_Msk (0x1U << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1959 #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
Kojto 122:f9eeca106725 1960 #define ADC12_CSR_AWD3_SLV_Pos (25U)
Kojto 122:f9eeca106725 1961 #define ADC12_CSR_AWD3_SLV_Msk (0x1U << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1962 #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
Kojto 122:f9eeca106725 1963 #define ADC12_CSR_JQOVF_SLV_Pos (26U)
Kojto 122:f9eeca106725 1964 #define ADC12_CSR_JQOVF_SLV_Msk (0x1U << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1965 #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
Kojto 122:f9eeca106725 1966
Kojto 122:f9eeca106725 1967 /*************** Bit definition for ADC34_COMMON_CSR register ***************/
Kojto 122:f9eeca106725 1968 #define ADC34_CSR_ADRDY_MST_Pos (0U)
Kojto 122:f9eeca106725 1969 #define ADC34_CSR_ADRDY_MST_Msk (0x1U << ADC34_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1970 #define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
Kojto 122:f9eeca106725 1971 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)
Kojto 122:f9eeca106725 1972 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1973 #define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
Kojto 122:f9eeca106725 1974 #define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)
Kojto 122:f9eeca106725 1975 #define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1976 #define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
Kojto 122:f9eeca106725 1977 #define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)
Kojto 122:f9eeca106725 1978 #define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1979 #define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
Kojto 122:f9eeca106725 1980 #define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)
Kojto 122:f9eeca106725 1981 #define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1982 #define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
Kojto 122:f9eeca106725 1983 #define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)
Kojto 122:f9eeca106725 1984 #define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1985 #define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
Kojto 122:f9eeca106725 1986 #define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)
Kojto 122:f9eeca106725 1987 #define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1988 #define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
Kojto 122:f9eeca106725 1989 #define ADC34_CSR_AWD1_MST_Pos (7U)
Kojto 122:f9eeca106725 1990 #define ADC34_CSR_AWD1_MST_Msk (0x1U << ADC34_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1991 #define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
Kojto 122:f9eeca106725 1992 #define ADC34_CSR_AWD2_MST_Pos (8U)
Kojto 122:f9eeca106725 1993 #define ADC34_CSR_AWD2_MST_Msk (0x1U << ADC34_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1994 #define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
Kojto 122:f9eeca106725 1995 #define ADC34_CSR_AWD3_MST_Pos (9U)
Kojto 122:f9eeca106725 1996 #define ADC34_CSR_AWD3_MST_Msk (0x1U << ADC34_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1997 #define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
Kojto 122:f9eeca106725 1998 #define ADC34_CSR_JQOVF_MST_Pos (10U)
Kojto 122:f9eeca106725 1999 #define ADC34_CSR_JQOVF_MST_Msk (0x1U << ADC34_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2000 #define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
Kojto 122:f9eeca106725 2001 #define ADC34_CSR_ADRDY_SLV_Pos (16U)
Kojto 122:f9eeca106725 2002 #define ADC34_CSR_ADRDY_SLV_Msk (0x1U << ADC34_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2003 #define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
Kojto 122:f9eeca106725 2004 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)
Kojto 122:f9eeca106725 2005 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2006 #define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
Kojto 122:f9eeca106725 2007 #define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)
Kojto 122:f9eeca106725 2008 #define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2009 #define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
Kojto 122:f9eeca106725 2010 #define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
Kojto 122:f9eeca106725 2011 #define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2012 #define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
Kojto 122:f9eeca106725 2013 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
Kojto 122:f9eeca106725 2014 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2015 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
Kojto 122:f9eeca106725 2016 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
Kojto 122:f9eeca106725 2017 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2018 #define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
Kojto 122:f9eeca106725 2019 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)
Kojto 122:f9eeca106725 2020 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2021 #define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
Kojto 122:f9eeca106725 2022 #define ADC34_CSR_AWD1_SLV_Pos (23U)
Kojto 122:f9eeca106725 2023 #define ADC34_CSR_AWD1_SLV_Msk (0x1U << ADC34_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2024 #define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
Kojto 122:f9eeca106725 2025 #define ADC34_CSR_AWD2_SLV_Pos (24U)
Kojto 122:f9eeca106725 2026 #define ADC34_CSR_AWD2_SLV_Msk (0x1U << ADC34_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2027 #define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
Kojto 122:f9eeca106725 2028 #define ADC34_CSR_AWD3_SLV_Pos (25U)
Kojto 122:f9eeca106725 2029 #define ADC34_CSR_AWD3_SLV_Msk (0x1U << ADC34_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2030 #define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
Kojto 122:f9eeca106725 2031 #define ADC34_CSR_JQOVF_SLV_Pos (26U)
Kojto 122:f9eeca106725 2032 #define ADC34_CSR_JQOVF_SLV_Msk (0x1U << ADC34_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2033 #define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
Kojto 122:f9eeca106725 2034
Kojto 122:f9eeca106725 2035 /*************** Bit definition for ADC12_COMMON_CCR register ***************/
Kojto 122:f9eeca106725 2036 #define ADC12_CCR_MULTI_Pos (0U)
Kojto 122:f9eeca106725 2037 #define ADC12_CCR_MULTI_Msk (0x1FU << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 2038 #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */
Kojto 122:f9eeca106725 2039 #define ADC12_CCR_MULTI_0 (0x01U << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2040 #define ADC12_CCR_MULTI_1 (0x02U << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2041 #define ADC12_CCR_MULTI_2 (0x04U << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2042 #define ADC12_CCR_MULTI_3 (0x08U << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2043 #define ADC12_CCR_MULTI_4 (0x10U << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2044 #define ADC12_CCR_DELAY_Pos (8U)
Kojto 122:f9eeca106725 2045 #define ADC12_CCR_DELAY_Msk (0xFU << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 2046 #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
Kojto 122:f9eeca106725 2047 #define ADC12_CCR_DELAY_0 (0x1U << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2048 #define ADC12_CCR_DELAY_1 (0x2U << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2049 #define ADC12_CCR_DELAY_2 (0x4U << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2050 #define ADC12_CCR_DELAY_3 (0x8U << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2051 #define ADC12_CCR_DMACFG_Pos (13U)
Kojto 122:f9eeca106725 2052 #define ADC12_CCR_DMACFG_Msk (0x1U << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2053 #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
Kojto 122:f9eeca106725 2054 #define ADC12_CCR_MDMA_Pos (14U)
Kojto 122:f9eeca106725 2055 #define ADC12_CCR_MDMA_Msk (0x3U << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 2056 #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
Kojto 122:f9eeca106725 2057 #define ADC12_CCR_MDMA_0 (0x1U << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2058 #define ADC12_CCR_MDMA_1 (0x2U << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2059 #define ADC12_CCR_CKMODE_Pos (16U)
Kojto 122:f9eeca106725 2060 #define ADC12_CCR_CKMODE_Msk (0x3U << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 2061 #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */
Kojto 122:f9eeca106725 2062 #define ADC12_CCR_CKMODE_0 (0x1U << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2063 #define ADC12_CCR_CKMODE_1 (0x2U << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2064 #define ADC12_CCR_VREFEN_Pos (22U)
Kojto 122:f9eeca106725 2065 #define ADC12_CCR_VREFEN_Msk (0x1U << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2066 #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */
Kojto 122:f9eeca106725 2067 #define ADC12_CCR_TSEN_Pos (23U)
Kojto 122:f9eeca106725 2068 #define ADC12_CCR_TSEN_Msk (0x1U << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2069 #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */
Kojto 122:f9eeca106725 2070 #define ADC12_CCR_VBATEN_Pos (24U)
Kojto 122:f9eeca106725 2071 #define ADC12_CCR_VBATEN_Msk (0x1U << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2072 #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */
Kojto 122:f9eeca106725 2073
Kojto 122:f9eeca106725 2074 /*************** Bit definition for ADC12_COMMON_CDR register ***************/
Kojto 122:f9eeca106725 2075 #define ADC12_CDR_RDATA_MST_Pos (0U)
Kojto 122:f9eeca106725 2076 #define ADC12_CDR_RDATA_MST_Msk (0xFFFFU << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 2077 #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
Kojto 122:f9eeca106725 2078 #define ADC12_CDR_RDATA_MST_0 (0x0001U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2079 #define ADC12_CDR_RDATA_MST_1 (0x0002U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2080 #define ADC12_CDR_RDATA_MST_2 (0x0004U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2081 #define ADC12_CDR_RDATA_MST_3 (0x0008U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2082 #define ADC12_CDR_RDATA_MST_4 (0x0010U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2083 #define ADC12_CDR_RDATA_MST_5 (0x0020U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2084 #define ADC12_CDR_RDATA_MST_6 (0x0040U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2085 #define ADC12_CDR_RDATA_MST_7 (0x0080U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2086 #define ADC12_CDR_RDATA_MST_8 (0x0100U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2087 #define ADC12_CDR_RDATA_MST_9 (0x0200U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2088 #define ADC12_CDR_RDATA_MST_10 (0x0400U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2089 #define ADC12_CDR_RDATA_MST_11 (0x0800U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2090 #define ADC12_CDR_RDATA_MST_12 (0x1000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2091 #define ADC12_CDR_RDATA_MST_13 (0x2000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2092 #define ADC12_CDR_RDATA_MST_14 (0x4000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2093 #define ADC12_CDR_RDATA_MST_15 (0x8000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2094
Kojto 122:f9eeca106725 2095 #define ADC12_CDR_RDATA_SLV_Pos (16U)
Kojto 122:f9eeca106725 2096 #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2097 #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
Kojto 122:f9eeca106725 2098 #define ADC12_CDR_RDATA_SLV_0 (0x0001U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2099 #define ADC12_CDR_RDATA_SLV_1 (0x0002U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2100 #define ADC12_CDR_RDATA_SLV_2 (0x0004U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2101 #define ADC12_CDR_RDATA_SLV_3 (0x0008U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2102 #define ADC12_CDR_RDATA_SLV_4 (0x0010U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2103 #define ADC12_CDR_RDATA_SLV_5 (0x0020U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2104 #define ADC12_CDR_RDATA_SLV_6 (0x0040U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2105 #define ADC12_CDR_RDATA_SLV_7 (0x0080U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2106 #define ADC12_CDR_RDATA_SLV_8 (0x0100U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2107 #define ADC12_CDR_RDATA_SLV_9 (0x0200U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2108 #define ADC12_CDR_RDATA_SLV_10 (0x0400U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2109 #define ADC12_CDR_RDATA_SLV_11 (0x0800U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2110 #define ADC12_CDR_RDATA_SLV_12 (0x1000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2111 #define ADC12_CDR_RDATA_SLV_13 (0x2000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2112 #define ADC12_CDR_RDATA_SLV_14 (0x4000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2113 #define ADC12_CDR_RDATA_SLV_15 (0x8000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2114
Kojto 122:f9eeca106725 2115 /******************** Bit definition for ADC_CSR register *******************/
Kojto 122:f9eeca106725 2116 #define ADC_CSR_ADRDY_MST_Pos (0U)
Kojto 122:f9eeca106725 2117 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2118 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
Kojto 122:f9eeca106725 2119 #define ADC_CSR_EOSMP_MST_Pos (1U)
Kojto 122:f9eeca106725 2120 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2121 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
Kojto 122:f9eeca106725 2122 #define ADC_CSR_EOC_MST_Pos (2U)
Kojto 122:f9eeca106725 2123 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2124 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 2125 #define ADC_CSR_EOS_MST_Pos (3U)
Kojto 122:f9eeca106725 2126 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2127 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 2128 #define ADC_CSR_OVR_MST_Pos (4U)
Kojto 122:f9eeca106725 2129 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2130 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
Kojto 122:f9eeca106725 2131 #define ADC_CSR_JEOC_MST_Pos (5U)
Kojto 122:f9eeca106725 2132 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2133 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
Kojto 122:f9eeca106725 2134 #define ADC_CSR_JEOS_MST_Pos (6U)
Kojto 122:f9eeca106725 2135 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2136 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 2137 #define ADC_CSR_AWD1_MST_Pos (7U)
Kojto 122:f9eeca106725 2138 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2139 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
Kojto 122:f9eeca106725 2140 #define ADC_CSR_AWD2_MST_Pos (8U)
Kojto 122:f9eeca106725 2141 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2142 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
Kojto 122:f9eeca106725 2143 #define ADC_CSR_AWD3_MST_Pos (9U)
Kojto 122:f9eeca106725 2144 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2145 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
Kojto 122:f9eeca106725 2146 #define ADC_CSR_JQOVF_MST_Pos (10U)
Kojto 122:f9eeca106725 2147 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2148 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
Kojto 122:f9eeca106725 2149
Kojto 122:f9eeca106725 2150 #define ADC_CSR_ADRDY_SLV_Pos (16U)
Kojto 122:f9eeca106725 2151 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2152 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
Kojto 122:f9eeca106725 2153 #define ADC_CSR_EOSMP_SLV_Pos (17U)
Kojto 122:f9eeca106725 2154 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2155 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
Kojto 122:f9eeca106725 2156 #define ADC_CSR_EOC_SLV_Pos (18U)
Kojto 122:f9eeca106725 2157 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2158 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 2159 #define ADC_CSR_EOS_SLV_Pos (19U)
Kojto 122:f9eeca106725 2160 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2161 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 2162 #define ADC_CSR_OVR_SLV_Pos (20U)
Kojto 122:f9eeca106725 2163 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2164 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
Kojto 122:f9eeca106725 2165 #define ADC_CSR_JEOC_SLV_Pos (21U)
Kojto 122:f9eeca106725 2166 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2167 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
Kojto 122:f9eeca106725 2168 #define ADC_CSR_JEOS_SLV_Pos (22U)
Kojto 122:f9eeca106725 2169 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2170 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 2171 #define ADC_CSR_AWD1_SLV_Pos (23U)
Kojto 122:f9eeca106725 2172 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2173 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
Kojto 122:f9eeca106725 2174 #define ADC_CSR_AWD2_SLV_Pos (24U)
Kojto 122:f9eeca106725 2175 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2176 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
Kojto 122:f9eeca106725 2177 #define ADC_CSR_AWD3_SLV_Pos (25U)
Kojto 122:f9eeca106725 2178 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2179 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
Kojto 122:f9eeca106725 2180 #define ADC_CSR_JQOVF_SLV_Pos (26U)
Kojto 122:f9eeca106725 2181 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2182 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
Kojto 122:f9eeca106725 2183
Kojto 122:f9eeca106725 2184 /* Legacy defines */
Kojto 122:f9eeca106725 2185 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST
Kojto 122:f9eeca106725 2186 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST
Kojto 122:f9eeca106725 2187 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST
Kojto 122:f9eeca106725 2188 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST
Kojto 122:f9eeca106725 2189 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST
Kojto 122:f9eeca106725 2190 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST
Kojto 122:f9eeca106725 2191
Kojto 122:f9eeca106725 2192 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV
Kojto 122:f9eeca106725 2193 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV
Kojto 122:f9eeca106725 2194 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV
Kojto 122:f9eeca106725 2195 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV
Kojto 122:f9eeca106725 2196 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV
Kojto 122:f9eeca106725 2197 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV
Kojto 122:f9eeca106725 2198
Kojto 122:f9eeca106725 2199 /******************** Bit definition for ADC_CCR register *******************/
Kojto 122:f9eeca106725 2200 #define ADC_CCR_DUAL_Pos (0U)
Kojto 122:f9eeca106725 2201 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 2202 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
Kojto 122:f9eeca106725 2203 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2204 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2205 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2206 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2207 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2208
Kojto 122:f9eeca106725 2209 #define ADC_CCR_DELAY_Pos (8U)
Kojto 122:f9eeca106725 2210 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 2211 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
Kojto 122:f9eeca106725 2212 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2213 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2214 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2215 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2216
Kojto 122:f9eeca106725 2217 #define ADC_CCR_DMACFG_Pos (13U)
Kojto 122:f9eeca106725 2218 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2219 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
Kojto 122:f9eeca106725 2220
Kojto 122:f9eeca106725 2221 #define ADC_CCR_MDMA_Pos (14U)
Kojto 122:f9eeca106725 2222 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 2223 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
Kojto 122:f9eeca106725 2224 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2225 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2226
Kojto 122:f9eeca106725 2227 #define ADC_CCR_CKMODE_Pos (16U)
Kojto 122:f9eeca106725 2228 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 2229 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
Kojto 122:f9eeca106725 2230 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2231 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2232
Kojto 122:f9eeca106725 2233 #define ADC_CCR_VREFEN_Pos (22U)
Kojto 122:f9eeca106725 2234 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2235 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
Kojto 122:f9eeca106725 2236 #define ADC_CCR_TSEN_Pos (23U)
Kojto 122:f9eeca106725 2237 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2238 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
Kojto 122:f9eeca106725 2239 #define ADC_CCR_VBATEN_Pos (24U)
Kojto 122:f9eeca106725 2240 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2241 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
Kojto 122:f9eeca106725 2242
Kojto 122:f9eeca106725 2243 /* Legacy defines */
Kojto 122:f9eeca106725 2244 #define ADC_CCR_MULTI (ADC_CCR_DUAL)
Kojto 122:f9eeca106725 2245 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
Kojto 122:f9eeca106725 2246 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
Kojto 122:f9eeca106725 2247 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
Kojto 122:f9eeca106725 2248 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
Kojto 122:f9eeca106725 2249 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
Kojto 122:f9eeca106725 2250
Kojto 122:f9eeca106725 2251 /******************** Bit definition for ADC_CDR register *******************/
Kojto 122:f9eeca106725 2252 #define ADC_CDR_RDATA_MST_Pos (0U)
Kojto 122:f9eeca106725 2253 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 2254 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
Kojto 122:f9eeca106725 2255 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2256 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2257 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2258 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2259 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2260 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2261 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2262 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2263 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2264 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2265 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2266 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2267 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2268 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2269 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2270 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2271
Kojto 122:f9eeca106725 2272 #define ADC_CDR_RDATA_SLV_Pos (16U)
Kojto 122:f9eeca106725 2273 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2274 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
Kojto 122:f9eeca106725 2275 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2276 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2277 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2278 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2279 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2280 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2281 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2282 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2283 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2284 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2285 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2286 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2287 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2288 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2289 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2290 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 2291
bogdanm 86:04dd9b1680ae 2292 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2293 /* */
bogdanm 86:04dd9b1680ae 2294 /* Analog Comparators (COMP) */
bogdanm 86:04dd9b1680ae 2295 /* */
bogdanm 86:04dd9b1680ae 2296 /******************************************************************************/
Kojto 122:f9eeca106725 2297
Kojto 122:f9eeca106725 2298 #define COMP_V1_3_0_0 /*!< Comparator IP version */
Kojto 122:f9eeca106725 2299
bogdanm 86:04dd9b1680ae 2300 /********************** Bit definition for COMP2_CSR register ***************/
Kojto 122:f9eeca106725 2301 #define COMP2_CSR_COMP2EN_Pos (0U)
Kojto 122:f9eeca106725 2302 #define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2303 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
Kojto 122:f9eeca106725 2304 #define COMP2_CSR_COMP2INSEL_Pos (4U)
Kojto 122:f9eeca106725 2305 #define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
Kojto 122:f9eeca106725 2306 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
Kojto 122:f9eeca106725 2307 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
Kojto 122:f9eeca106725 2308 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
Kojto 122:f9eeca106725 2309 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
Kojto 122:f9eeca106725 2310 #define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
Kojto 122:f9eeca106725 2311 #define COMP2_CSR_COMP2OUTSEL_Pos (10U)
Kojto 122:f9eeca106725 2312 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
Kojto 122:f9eeca106725 2313 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
Kojto 122:f9eeca106725 2314 #define COMP2_CSR_COMP2OUTSEL_0 (0x1U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2315 #define COMP2_CSR_COMP2OUTSEL_1 (0x2U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2316 #define COMP2_CSR_COMP2OUTSEL_2 (0x4U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2317 #define COMP2_CSR_COMP2OUTSEL_3 (0x8U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2318 #define COMP2_CSR_COMP2POL_Pos (15U)
Kojto 122:f9eeca106725 2319 #define COMP2_CSR_COMP2POL_Msk (0x1U << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2320 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
Kojto 122:f9eeca106725 2321 #define COMP2_CSR_COMP2BLANKING_Pos (18U)
Kojto 122:f9eeca106725 2322 #define COMP2_CSR_COMP2BLANKING_Msk (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2323 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */
Kojto 122:f9eeca106725 2324 #define COMP2_CSR_COMP2BLANKING_0 (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2325 #define COMP2_CSR_COMP2BLANKING_1 (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2326 #define COMP2_CSR_COMP2BLANKING_2 (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2327 #define COMP2_CSR_COMP2OUT_Pos (30U)
Kojto 122:f9eeca106725 2328 #define COMP2_CSR_COMP2OUT_Msk (0x1U << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2329 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */
Kojto 122:f9eeca106725 2330 #define COMP2_CSR_COMP2LOCK_Pos (31U)
Kojto 122:f9eeca106725 2331 #define COMP2_CSR_COMP2LOCK_Msk (0x1U << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2332 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
bogdanm 86:04dd9b1680ae 2333
bogdanm 86:04dd9b1680ae 2334 /********************** Bit definition for COMP4_CSR register ***************/
Kojto 122:f9eeca106725 2335 #define COMP4_CSR_COMP4EN_Pos (0U)
Kojto 122:f9eeca106725 2336 #define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2337 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
Kojto 122:f9eeca106725 2338 #define COMP4_CSR_COMP4INSEL_Pos (4U)
Kojto 122:f9eeca106725 2339 #define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
Kojto 122:f9eeca106725 2340 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
Kojto 122:f9eeca106725 2341 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
Kojto 122:f9eeca106725 2342 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
Kojto 122:f9eeca106725 2343 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
Kojto 122:f9eeca106725 2344 #define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
Kojto 122:f9eeca106725 2345 #define COMP4_CSR_COMP4OUTSEL_Pos (10U)
Kojto 122:f9eeca106725 2346 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
Kojto 122:f9eeca106725 2347 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
Kojto 122:f9eeca106725 2348 #define COMP4_CSR_COMP4OUTSEL_0 (0x1U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2349 #define COMP4_CSR_COMP4OUTSEL_1 (0x2U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2350 #define COMP4_CSR_COMP4OUTSEL_2 (0x4U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2351 #define COMP4_CSR_COMP4OUTSEL_3 (0x8U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2352 #define COMP4_CSR_COMP4POL_Pos (15U)
Kojto 122:f9eeca106725 2353 #define COMP4_CSR_COMP4POL_Msk (0x1U << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2354 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */
Kojto 122:f9eeca106725 2355 #define COMP4_CSR_COMP4BLANKING_Pos (18U)
Kojto 122:f9eeca106725 2356 #define COMP4_CSR_COMP4BLANKING_Msk (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2357 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */
Kojto 122:f9eeca106725 2358 #define COMP4_CSR_COMP4BLANKING_0 (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2359 #define COMP4_CSR_COMP4BLANKING_1 (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2360 #define COMP4_CSR_COMP4BLANKING_2 (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2361 #define COMP4_CSR_COMP4OUT_Pos (30U)
Kojto 122:f9eeca106725 2362 #define COMP4_CSR_COMP4OUT_Msk (0x1U << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2363 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */
Kojto 122:f9eeca106725 2364 #define COMP4_CSR_COMP4LOCK_Pos (31U)
Kojto 122:f9eeca106725 2365 #define COMP4_CSR_COMP4LOCK_Msk (0x1U << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2366 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */
bogdanm 86:04dd9b1680ae 2367
bogdanm 86:04dd9b1680ae 2368 /********************** Bit definition for COMP6_CSR register ***************/
Kojto 122:f9eeca106725 2369 #define COMP6_CSR_COMP6EN_Pos (0U)
Kojto 122:f9eeca106725 2370 #define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2371 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
Kojto 122:f9eeca106725 2372 #define COMP6_CSR_COMP6INSEL_Pos (4U)
Kojto 122:f9eeca106725 2373 #define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
Kojto 122:f9eeca106725 2374 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
Kojto 122:f9eeca106725 2375 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
Kojto 122:f9eeca106725 2376 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
Kojto 122:f9eeca106725 2377 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
Kojto 122:f9eeca106725 2378 #define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
Kojto 122:f9eeca106725 2379 #define COMP6_CSR_COMP6OUTSEL_Pos (10U)
Kojto 122:f9eeca106725 2380 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
Kojto 122:f9eeca106725 2381 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
Kojto 122:f9eeca106725 2382 #define COMP6_CSR_COMP6OUTSEL_0 (0x1U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2383 #define COMP6_CSR_COMP6OUTSEL_1 (0x2U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2384 #define COMP6_CSR_COMP6OUTSEL_2 (0x4U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2385 #define COMP6_CSR_COMP6OUTSEL_3 (0x8U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2386 #define COMP6_CSR_COMP6POL_Pos (15U)
Kojto 122:f9eeca106725 2387 #define COMP6_CSR_COMP6POL_Msk (0x1U << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2388 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */
Kojto 122:f9eeca106725 2389 #define COMP6_CSR_COMP6BLANKING_Pos (18U)
Kojto 122:f9eeca106725 2390 #define COMP6_CSR_COMP6BLANKING_Msk (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2391 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */
Kojto 122:f9eeca106725 2392 #define COMP6_CSR_COMP6BLANKING_0 (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2393 #define COMP6_CSR_COMP6BLANKING_1 (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2394 #define COMP6_CSR_COMP6BLANKING_2 (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2395 #define COMP6_CSR_COMP6OUT_Pos (30U)
Kojto 122:f9eeca106725 2396 #define COMP6_CSR_COMP6OUT_Msk (0x1U << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2397 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */
Kojto 122:f9eeca106725 2398 #define COMP6_CSR_COMP6LOCK_Pos (31U)
Kojto 122:f9eeca106725 2399 #define COMP6_CSR_COMP6LOCK_Msk (0x1U << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2400 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */
bogdanm 86:04dd9b1680ae 2401
bogdanm 86:04dd9b1680ae 2402 /********************** Bit definition for COMP_CSR register ****************/
Kojto 122:f9eeca106725 2403 #define COMP_CSR_COMPxEN_Pos (0U)
Kojto 122:f9eeca106725 2404 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2405 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
Kojto 122:f9eeca106725 2406 #define COMP_CSR_COMPxINSEL_Pos (4U)
Kojto 122:f9eeca106725 2407 #define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
Kojto 122:f9eeca106725 2408 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
Kojto 122:f9eeca106725 2409 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
Kojto 122:f9eeca106725 2410 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
Kojto 122:f9eeca106725 2411 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
Kojto 122:f9eeca106725 2412 #define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
Kojto 122:f9eeca106725 2413 #define COMP_CSR_COMPxOUTSEL_Pos (10U)
Kojto 122:f9eeca106725 2414 #define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
Kojto 122:f9eeca106725 2415 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
Kojto 122:f9eeca106725 2416 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2417 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2418 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2419 #define COMP_CSR_COMPxOUTSEL_3 (0x8U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2420 #define COMP_CSR_COMPxPOL_Pos (15U)
Kojto 122:f9eeca106725 2421 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2422 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
Kojto 122:f9eeca106725 2423 #define COMP_CSR_COMPxBLANKING_Pos (18U)
Kojto 122:f9eeca106725 2424 #define COMP_CSR_COMPxBLANKING_Msk (0x3U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2425 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */
Kojto 122:f9eeca106725 2426 #define COMP_CSR_COMPxBLANKING_0 (0x1U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2427 #define COMP_CSR_COMPxBLANKING_1 (0x2U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2428 #define COMP_CSR_COMPxBLANKING_2 (0x4U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2429 #define COMP_CSR_COMPxOUT_Pos (30U)
Kojto 122:f9eeca106725 2430 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2431 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
Kojto 122:f9eeca106725 2432 #define COMP_CSR_COMPxLOCK_Pos (31U)
Kojto 122:f9eeca106725 2433 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2434 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
bogdanm 86:04dd9b1680ae 2435
bogdanm 86:04dd9b1680ae 2436 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2437 /* */
bogdanm 86:04dd9b1680ae 2438 /* Operational Amplifier (OPAMP) */
bogdanm 86:04dd9b1680ae 2439 /* */
bogdanm 86:04dd9b1680ae 2440 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2441 /********************* Bit definition for OPAMP2_CSR register ***************/
Kojto 122:f9eeca106725 2442 #define OPAMP2_CSR_OPAMP2EN_Pos (0U)
Kojto 122:f9eeca106725 2443 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1U << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2444 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */
Kojto 122:f9eeca106725 2445 #define OPAMP2_CSR_FORCEVP_Pos (1U)
Kojto 122:f9eeca106725 2446 #define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2447 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
Kojto 122:f9eeca106725 2448 #define OPAMP2_CSR_VPSEL_Pos (2U)
Kojto 122:f9eeca106725 2449 #define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 2450 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */
Kojto 122:f9eeca106725 2451 #define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2452 #define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2453 #define OPAMP2_CSR_VMSEL_Pos (5U)
Kojto 122:f9eeca106725 2454 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 2455 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
Kojto 122:f9eeca106725 2456 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2457 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2458 #define OPAMP2_CSR_TCMEN_Pos (7U)
Kojto 122:f9eeca106725 2459 #define OPAMP2_CSR_TCMEN_Msk (0x1U << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2460 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
Kojto 122:f9eeca106725 2461 #define OPAMP2_CSR_VMSSEL_Pos (8U)
Kojto 122:f9eeca106725 2462 #define OPAMP2_CSR_VMSSEL_Msk (0x1U << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2463 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
Kojto 122:f9eeca106725 2464 #define OPAMP2_CSR_VPSSEL_Pos (9U)
Kojto 122:f9eeca106725 2465 #define OPAMP2_CSR_VPSSEL_Msk (0x3U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 2466 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
Kojto 122:f9eeca106725 2467 #define OPAMP2_CSR_VPSSEL_0 (0x1U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2468 #define OPAMP2_CSR_VPSSEL_1 (0x2U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2469 #define OPAMP2_CSR_CALON_Pos (11U)
Kojto 122:f9eeca106725 2470 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2471 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
Kojto 122:f9eeca106725 2472 #define OPAMP2_CSR_CALSEL_Pos (12U)
Kojto 122:f9eeca106725 2473 #define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 2474 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
Kojto 122:f9eeca106725 2475 #define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2476 #define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2477 #define OPAMP2_CSR_PGGAIN_Pos (14U)
Kojto 122:f9eeca106725 2478 #define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
Kojto 122:f9eeca106725 2479 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
Kojto 122:f9eeca106725 2480 #define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2481 #define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2482 #define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2483 #define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2484 #define OPAMP2_CSR_USERTRIM_Pos (18U)
Kojto 122:f9eeca106725 2485 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2486 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
Kojto 122:f9eeca106725 2487 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)
Kojto 122:f9eeca106725 2488 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
Kojto 122:f9eeca106725 2489 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
Kojto 122:f9eeca106725 2490 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)
Kojto 122:f9eeca106725 2491 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 2492 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
Kojto 122:f9eeca106725 2493 #define OPAMP2_CSR_TSTREF_Pos (29U)
Kojto 122:f9eeca106725 2494 #define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2495 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
Kojto 122:f9eeca106725 2496 #define OPAMP2_CSR_OUTCAL_Pos (30U)
Kojto 122:f9eeca106725 2497 #define OPAMP2_CSR_OUTCAL_Msk (0x1U << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2498 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
Kojto 122:f9eeca106725 2499 #define OPAMP2_CSR_LOCK_Pos (31U)
Kojto 122:f9eeca106725 2500 #define OPAMP2_CSR_LOCK_Msk (0x1U << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2501 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
bogdanm 86:04dd9b1680ae 2502
bogdanm 86:04dd9b1680ae 2503 /********************* Bit definition for OPAMPx_CSR register ***************/
Kojto 122:f9eeca106725 2504 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
Kojto 122:f9eeca106725 2505 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2506 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
Kojto 122:f9eeca106725 2507 #define OPAMP_CSR_FORCEVP_Pos (1U)
Kojto 122:f9eeca106725 2508 #define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2509 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
Kojto 122:f9eeca106725 2510 #define OPAMP_CSR_VPSEL_Pos (2U)
Kojto 122:f9eeca106725 2511 #define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 2512 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
Kojto 122:f9eeca106725 2513 #define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2514 #define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2515 #define OPAMP_CSR_VMSEL_Pos (5U)
Kojto 122:f9eeca106725 2516 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 2517 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
Kojto 122:f9eeca106725 2518 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2519 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2520 #define OPAMP_CSR_TCMEN_Pos (7U)
Kojto 122:f9eeca106725 2521 #define OPAMP_CSR_TCMEN_Msk (0x1U << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2522 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
Kojto 122:f9eeca106725 2523 #define OPAMP_CSR_VMSSEL_Pos (8U)
Kojto 122:f9eeca106725 2524 #define OPAMP_CSR_VMSSEL_Msk (0x1U << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2525 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
Kojto 122:f9eeca106725 2526 #define OPAMP_CSR_VPSSEL_Pos (9U)
Kojto 122:f9eeca106725 2527 #define OPAMP_CSR_VPSSEL_Msk (0x3U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 2528 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
Kojto 122:f9eeca106725 2529 #define OPAMP_CSR_VPSSEL_0 (0x1U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2530 #define OPAMP_CSR_VPSSEL_1 (0x2U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2531 #define OPAMP_CSR_CALON_Pos (11U)
Kojto 122:f9eeca106725 2532 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2533 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
Kojto 122:f9eeca106725 2534 #define OPAMP_CSR_CALSEL_Pos (12U)
Kojto 122:f9eeca106725 2535 #define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 2536 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
Kojto 122:f9eeca106725 2537 #define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2538 #define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2539 #define OPAMP_CSR_PGGAIN_Pos (14U)
Kojto 122:f9eeca106725 2540 #define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
Kojto 122:f9eeca106725 2541 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
Kojto 122:f9eeca106725 2542 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2543 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2544 #define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2545 #define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2546 #define OPAMP_CSR_USERTRIM_Pos (18U)
Kojto 122:f9eeca106725 2547 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2548 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
Kojto 122:f9eeca106725 2549 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
Kojto 122:f9eeca106725 2550 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
Kojto 122:f9eeca106725 2551 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
Kojto 122:f9eeca106725 2552 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
Kojto 122:f9eeca106725 2553 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 2554 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
Kojto 122:f9eeca106725 2555 #define OPAMP_CSR_TSTREF_Pos (29U)
Kojto 122:f9eeca106725 2556 #define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2557 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
Kojto 122:f9eeca106725 2558 #define OPAMP_CSR_OUTCAL_Pos (30U)
Kojto 122:f9eeca106725 2559 #define OPAMP_CSR_OUTCAL_Msk (0x1U << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2560 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
Kojto 122:f9eeca106725 2561 #define OPAMP_CSR_LOCK_Pos (31U)
Kojto 122:f9eeca106725 2562 #define OPAMP_CSR_LOCK_Msk (0x1U << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2563 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
bogdanm 86:04dd9b1680ae 2564
bogdanm 86:04dd9b1680ae 2565 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2566 /* */
bogdanm 86:04dd9b1680ae 2567 /* Controller Area Network (CAN ) */
bogdanm 86:04dd9b1680ae 2568 /* */
bogdanm 86:04dd9b1680ae 2569 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2570 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 2571 #define CAN_MCR_INRQ_Pos (0U)
Kojto 122:f9eeca106725 2572 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2573 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
Kojto 122:f9eeca106725 2574 #define CAN_MCR_SLEEP_Pos (1U)
Kojto 122:f9eeca106725 2575 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2576 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 2577 #define CAN_MCR_TXFP_Pos (2U)
Kojto 122:f9eeca106725 2578 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2579 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 2580 #define CAN_MCR_RFLM_Pos (3U)
Kojto 122:f9eeca106725 2581 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2582 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 2583 #define CAN_MCR_NART_Pos (4U)
Kojto 122:f9eeca106725 2584 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2585 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 2586 #define CAN_MCR_AWUM_Pos (5U)
Kojto 122:f9eeca106725 2587 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2588 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 2589 #define CAN_MCR_ABOM_Pos (6U)
Kojto 122:f9eeca106725 2590 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2591 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 2592 #define CAN_MCR_TTCM_Pos (7U)
Kojto 122:f9eeca106725 2593 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2594 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 2595 #define CAN_MCR_RESET_Pos (15U)
Kojto 122:f9eeca106725 2596 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2597 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
bogdanm 86:04dd9b1680ae 2598
bogdanm 86:04dd9b1680ae 2599 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 2600 #define CAN_MSR_INAK_Pos (0U)
Kojto 122:f9eeca106725 2601 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2602 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 2603 #define CAN_MSR_SLAK_Pos (1U)
Kojto 122:f9eeca106725 2604 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2605 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 2606 #define CAN_MSR_ERRI_Pos (2U)
Kojto 122:f9eeca106725 2607 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2608 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
Kojto 122:f9eeca106725 2609 #define CAN_MSR_WKUI_Pos (3U)
Kojto 122:f9eeca106725 2610 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2611 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 2612 #define CAN_MSR_SLAKI_Pos (4U)
Kojto 122:f9eeca106725 2613 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2614 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 2615 #define CAN_MSR_TXM_Pos (8U)
Kojto 122:f9eeca106725 2616 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2617 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
Kojto 122:f9eeca106725 2618 #define CAN_MSR_RXM_Pos (9U)
Kojto 122:f9eeca106725 2619 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2620 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
Kojto 122:f9eeca106725 2621 #define CAN_MSR_SAMP_Pos (10U)
Kojto 122:f9eeca106725 2622 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2623 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
Kojto 122:f9eeca106725 2624 #define CAN_MSR_RX_Pos (11U)
Kojto 122:f9eeca106725 2625 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2626 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
bogdanm 86:04dd9b1680ae 2627
bogdanm 86:04dd9b1680ae 2628 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 2629 #define CAN_TSR_RQCP0_Pos (0U)
Kojto 122:f9eeca106725 2630 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2631 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 2632 #define CAN_TSR_TXOK0_Pos (1U)
Kojto 122:f9eeca106725 2633 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2634 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 2635 #define CAN_TSR_ALST0_Pos (2U)
Kojto 122:f9eeca106725 2636 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2637 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 2638 #define CAN_TSR_TERR0_Pos (3U)
Kojto 122:f9eeca106725 2639 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2640 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 2641 #define CAN_TSR_ABRQ0_Pos (7U)
Kojto 122:f9eeca106725 2642 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2643 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 2644 #define CAN_TSR_RQCP1_Pos (8U)
Kojto 122:f9eeca106725 2645 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2646 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 2647 #define CAN_TSR_TXOK1_Pos (9U)
Kojto 122:f9eeca106725 2648 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2649 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 2650 #define CAN_TSR_ALST1_Pos (10U)
Kojto 122:f9eeca106725 2651 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2652 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 2653 #define CAN_TSR_TERR1_Pos (11U)
Kojto 122:f9eeca106725 2654 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2655 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 2656 #define CAN_TSR_ABRQ1_Pos (15U)
Kojto 122:f9eeca106725 2657 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2658 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 2659 #define CAN_TSR_RQCP2_Pos (16U)
Kojto 122:f9eeca106725 2660 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2661 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 2662 #define CAN_TSR_TXOK2_Pos (17U)
Kojto 122:f9eeca106725 2663 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2664 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 2665 #define CAN_TSR_ALST2_Pos (18U)
Kojto 122:f9eeca106725 2666 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2667 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 2668 #define CAN_TSR_TERR2_Pos (19U)
Kojto 122:f9eeca106725 2669 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2670 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 2671 #define CAN_TSR_ABRQ2_Pos (23U)
Kojto 122:f9eeca106725 2672 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2673 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 2674 #define CAN_TSR_CODE_Pos (24U)
Kojto 122:f9eeca106725 2675 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2676 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
Kojto 122:f9eeca106725 2677
Kojto 122:f9eeca106725 2678 #define CAN_TSR_TME_Pos (26U)
Kojto 122:f9eeca106725 2679 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
Kojto 122:f9eeca106725 2680 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 2681 #define CAN_TSR_TME0_Pos (26U)
Kojto 122:f9eeca106725 2682 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2683 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 2684 #define CAN_TSR_TME1_Pos (27U)
Kojto 122:f9eeca106725 2685 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2686 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 2687 #define CAN_TSR_TME2_Pos (28U)
Kojto 122:f9eeca106725 2688 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2689 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 2690
Kojto 122:f9eeca106725 2691 #define CAN_TSR_LOW_Pos (29U)
Kojto 122:f9eeca106725 2692 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
Kojto 122:f9eeca106725 2693 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 2694 #define CAN_TSR_LOW0_Pos (29U)
Kojto 122:f9eeca106725 2695 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2696 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 2697 #define CAN_TSR_LOW1_Pos (30U)
Kojto 122:f9eeca106725 2698 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2699 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 2700 #define CAN_TSR_LOW2_Pos (31U)
Kojto 122:f9eeca106725 2701 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2702 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 86:04dd9b1680ae 2703
bogdanm 86:04dd9b1680ae 2704 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 2705 #define CAN_RF0R_FMP0_Pos (0U)
Kojto 122:f9eeca106725 2706 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2707 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 2708 #define CAN_RF0R_FULL0_Pos (3U)
Kojto 122:f9eeca106725 2709 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2710 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 2711 #define CAN_RF0R_FOVR0_Pos (4U)
Kojto 122:f9eeca106725 2712 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2713 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 2714 #define CAN_RF0R_RFOM0_Pos (5U)
Kojto 122:f9eeca106725 2715 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2716 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
bogdanm 86:04dd9b1680ae 2717
bogdanm 86:04dd9b1680ae 2718 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 2719 #define CAN_RF1R_FMP1_Pos (0U)
Kojto 122:f9eeca106725 2720 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2721 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 2722 #define CAN_RF1R_FULL1_Pos (3U)
Kojto 122:f9eeca106725 2723 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2724 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 2725 #define CAN_RF1R_FOVR1_Pos (4U)
Kojto 122:f9eeca106725 2726 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2727 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 2728 #define CAN_RF1R_RFOM1_Pos (5U)
Kojto 122:f9eeca106725 2729 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2730 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
bogdanm 86:04dd9b1680ae 2731
bogdanm 86:04dd9b1680ae 2732 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 2733 #define CAN_IER_TMEIE_Pos (0U)
Kojto 122:f9eeca106725 2734 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2735 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 2736 #define CAN_IER_FMPIE0_Pos (1U)
Kojto 122:f9eeca106725 2737 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2738 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2739 #define CAN_IER_FFIE0_Pos (2U)
Kojto 122:f9eeca106725 2740 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2741 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2742 #define CAN_IER_FOVIE0_Pos (3U)
Kojto 122:f9eeca106725 2743 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2744 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2745 #define CAN_IER_FMPIE1_Pos (4U)
Kojto 122:f9eeca106725 2746 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2747 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2748 #define CAN_IER_FFIE1_Pos (5U)
Kojto 122:f9eeca106725 2749 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2750 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2751 #define CAN_IER_FOVIE1_Pos (6U)
Kojto 122:f9eeca106725 2752 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2753 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2754 #define CAN_IER_EWGIE_Pos (8U)
Kojto 122:f9eeca106725 2755 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2756 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 2757 #define CAN_IER_EPVIE_Pos (9U)
Kojto 122:f9eeca106725 2758 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2759 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 2760 #define CAN_IER_BOFIE_Pos (10U)
Kojto 122:f9eeca106725 2761 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2762 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 2763 #define CAN_IER_LECIE_Pos (11U)
Kojto 122:f9eeca106725 2764 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2765 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 2766 #define CAN_IER_ERRIE_Pos (15U)
Kojto 122:f9eeca106725 2767 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2768 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 2769 #define CAN_IER_WKUIE_Pos (16U)
Kojto 122:f9eeca106725 2770 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2771 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 2772 #define CAN_IER_SLKIE_Pos (17U)
Kojto 122:f9eeca106725 2773 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2774 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
bogdanm 86:04dd9b1680ae 2775
bogdanm 86:04dd9b1680ae 2776 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 2777 #define CAN_ESR_EWGF_Pos (0U)
Kojto 122:f9eeca106725 2778 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2779 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
Kojto 122:f9eeca106725 2780 #define CAN_ESR_EPVF_Pos (1U)
Kojto 122:f9eeca106725 2781 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2782 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
Kojto 122:f9eeca106725 2783 #define CAN_ESR_BOFF_Pos (2U)
Kojto 122:f9eeca106725 2784 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2785 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 2786
Kojto 122:f9eeca106725 2787 #define CAN_ESR_LEC_Pos (4U)
Kojto 122:f9eeca106725 2788 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 2789 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 2790 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2791 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2792 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2793
Kojto 122:f9eeca106725 2794 #define CAN_ESR_TEC_Pos (16U)
Kojto 122:f9eeca106725 2795 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2796 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 2797 #define CAN_ESR_REC_Pos (24U)
Kojto 122:f9eeca106725 2798 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2799 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
bogdanm 86:04dd9b1680ae 2800
bogdanm 86:04dd9b1680ae 2801 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 2802 #define CAN_BTR_BRP_Pos (0U)
Kojto 122:f9eeca106725 2803 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 2804 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 2805 #define CAN_BTR_TS1_Pos (16U)
Kojto 122:f9eeca106725 2806 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 2807 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
Kojto 122:f9eeca106725 2808 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2809 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2810 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2811 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2812 #define CAN_BTR_TS2_Pos (20U)
Kojto 122:f9eeca106725 2813 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 2814 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
Kojto 122:f9eeca106725 2815 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2816 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2817 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2818 #define CAN_BTR_SJW_Pos (24U)
Kojto 122:f9eeca106725 2819 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2820 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 2821 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2822 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2823 #define CAN_BTR_LBKM_Pos (30U)
Kojto 122:f9eeca106725 2824 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2825 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 2826 #define CAN_BTR_SILM_Pos (31U)
Kojto 122:f9eeca106725 2827 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2828 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
bogdanm 86:04dd9b1680ae 2829
bogdanm 86:04dd9b1680ae 2830 /*!<Mailbox registers */
bogdanm 86:04dd9b1680ae 2831 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 2832 #define CAN_TI0R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2833 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2834 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2835 #define CAN_TI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2836 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2837 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2838 #define CAN_TI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2839 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2840 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2841 #define CAN_TI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2842 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2843 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 2844 #define CAN_TI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 2845 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2846 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
bogdanm 86:04dd9b1680ae 2847
bogdanm 86:04dd9b1680ae 2848 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 2849 #define CAN_TDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2850 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2851 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2852 #define CAN_TDT0R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2853 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2854 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2855 #define CAN_TDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2856 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2857 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
bogdanm 86:04dd9b1680ae 2858
bogdanm 86:04dd9b1680ae 2859 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 2860 #define CAN_TDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2861 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2862 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2863 #define CAN_TDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2864 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2865 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2866 #define CAN_TDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2867 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2868 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2869 #define CAN_TDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2870 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2871 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
bogdanm 86:04dd9b1680ae 2872
bogdanm 86:04dd9b1680ae 2873 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 2874 #define CAN_TDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2875 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2876 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2877 #define CAN_TDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2878 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2879 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2880 #define CAN_TDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2881 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2882 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2883 #define CAN_TDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2884 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2885 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
bogdanm 86:04dd9b1680ae 2886
bogdanm 86:04dd9b1680ae 2887 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 2888 #define CAN_TI1R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2889 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2890 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2891 #define CAN_TI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2892 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2893 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2894 #define CAN_TI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2895 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2896 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2897 #define CAN_TI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2898 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2899 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 2900 #define CAN_TI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 2901 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2902 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
bogdanm 86:04dd9b1680ae 2903
bogdanm 86:04dd9b1680ae 2904 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 2905 #define CAN_TDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2906 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2907 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2908 #define CAN_TDT1R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2909 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2910 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2911 #define CAN_TDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2912 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2913 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
bogdanm 86:04dd9b1680ae 2914
bogdanm 86:04dd9b1680ae 2915 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 2916 #define CAN_TDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2917 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2918 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2919 #define CAN_TDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2920 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2921 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2922 #define CAN_TDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2923 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2924 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2925 #define CAN_TDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2926 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2927 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
bogdanm 86:04dd9b1680ae 2928
bogdanm 86:04dd9b1680ae 2929 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 2930 #define CAN_TDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2931 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2932 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2933 #define CAN_TDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2934 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2935 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2936 #define CAN_TDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2937 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2938 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2939 #define CAN_TDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2940 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2941 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
bogdanm 86:04dd9b1680ae 2942
bogdanm 86:04dd9b1680ae 2943 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 2944 #define CAN_TI2R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2945 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2946 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2947 #define CAN_TI2R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2948 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2949 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2950 #define CAN_TI2R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2951 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2952 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2953 #define CAN_TI2R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2954 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2955 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 2956 #define CAN_TI2R_STID_Pos (21U)
Kojto 122:f9eeca106725 2957 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2958 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
bogdanm 86:04dd9b1680ae 2959
bogdanm 86:04dd9b1680ae 2960 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 2961 #define CAN_TDT2R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2962 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2963 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2964 #define CAN_TDT2R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2965 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2966 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2967 #define CAN_TDT2R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2968 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2969 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
bogdanm 86:04dd9b1680ae 2970
bogdanm 86:04dd9b1680ae 2971 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 2972 #define CAN_TDL2R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2973 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2974 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2975 #define CAN_TDL2R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2976 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2977 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2978 #define CAN_TDL2R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2979 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2980 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2981 #define CAN_TDL2R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2982 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2983 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
bogdanm 86:04dd9b1680ae 2984
bogdanm 86:04dd9b1680ae 2985 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 2986 #define CAN_TDH2R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2987 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2988 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2989 #define CAN_TDH2R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2990 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2991 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2992 #define CAN_TDH2R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2993 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2994 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2995 #define CAN_TDH2R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2996 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2997 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
bogdanm 86:04dd9b1680ae 2998
bogdanm 86:04dd9b1680ae 2999 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 3000 #define CAN_RI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 3001 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3002 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 3003 #define CAN_RI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 3004 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3005 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 3006 #define CAN_RI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 3007 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 3008 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 3009 #define CAN_RI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 3010 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 3011 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
bogdanm 86:04dd9b1680ae 3012
bogdanm 86:04dd9b1680ae 3013 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 3014 #define CAN_RDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 3015 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3016 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 3017 #define CAN_RDT0R_FMI_Pos (8U)
Kojto 122:f9eeca106725 3018 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3019 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 3020 #define CAN_RDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 3021 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 3022 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
bogdanm 86:04dd9b1680ae 3023
bogdanm 86:04dd9b1680ae 3024 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 3025 #define CAN_RDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 3026 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 3027 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 3028 #define CAN_RDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 3029 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3030 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 3031 #define CAN_RDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 3032 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 3033 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 3034 #define CAN_RDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 3035 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 3036 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
bogdanm 86:04dd9b1680ae 3037
bogdanm 86:04dd9b1680ae 3038 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 3039 #define CAN_RDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 3040 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 3041 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 3042 #define CAN_RDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 3043 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3044 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 3045 #define CAN_RDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 3046 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 3047 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 3048 #define CAN_RDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 3049 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 3050 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
bogdanm 86:04dd9b1680ae 3051
bogdanm 86:04dd9b1680ae 3052 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 3053 #define CAN_RI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 3054 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3055 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 3056 #define CAN_RI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 3057 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3058 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 3059 #define CAN_RI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 3060 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 3061 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 3062 #define CAN_RI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 3063 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 3064 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
bogdanm 86:04dd9b1680ae 3065
bogdanm 86:04dd9b1680ae 3066 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 3067 #define CAN_RDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 3068 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3069 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 3070 #define CAN_RDT1R_FMI_Pos (8U)
Kojto 122:f9eeca106725 3071 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3072 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 3073 #define CAN_RDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 3074 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 3075 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
bogdanm 86:04dd9b1680ae 3076
bogdanm 86:04dd9b1680ae 3077 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 3078 #define CAN_RDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 3079 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 3080 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 3081 #define CAN_RDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 3082 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3083 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 3084 #define CAN_RDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 3085 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 3086 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 3087 #define CAN_RDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 3088 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 3089 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
bogdanm 86:04dd9b1680ae 3090
bogdanm 86:04dd9b1680ae 3091 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 3092 #define CAN_RDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 3093 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 3094 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 3095 #define CAN_RDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 3096 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3097 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 3098 #define CAN_RDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 3099 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 3100 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 3101 #define CAN_RDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 3102 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 3103 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
bogdanm 86:04dd9b1680ae 3104
bogdanm 86:04dd9b1680ae 3105 /*!<CAN filter registers */
bogdanm 86:04dd9b1680ae 3106 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 3107 #define CAN_FMR_FINIT_Pos (0U)
Kojto 122:f9eeca106725 3108 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3109 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
bogdanm 86:04dd9b1680ae 3110
bogdanm 86:04dd9b1680ae 3111 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 3112 #define CAN_FM1R_FBM_Pos (0U)
Kojto 122:f9eeca106725 3113 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 3114 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
Kojto 122:f9eeca106725 3115 #define CAN_FM1R_FBM0_Pos (0U)
Kojto 122:f9eeca106725 3116 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3117 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 3118 #define CAN_FM1R_FBM1_Pos (1U)
Kojto 122:f9eeca106725 3119 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3120 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 3121 #define CAN_FM1R_FBM2_Pos (2U)
Kojto 122:f9eeca106725 3122 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3123 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 3124 #define CAN_FM1R_FBM3_Pos (3U)
Kojto 122:f9eeca106725 3125 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3126 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 3127 #define CAN_FM1R_FBM4_Pos (4U)
Kojto 122:f9eeca106725 3128 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3129 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 3130 #define CAN_FM1R_FBM5_Pos (5U)
Kojto 122:f9eeca106725 3131 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3132 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 3133 #define CAN_FM1R_FBM6_Pos (6U)
Kojto 122:f9eeca106725 3134 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3135 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 3136 #define CAN_FM1R_FBM7_Pos (7U)
Kojto 122:f9eeca106725 3137 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3138 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 3139 #define CAN_FM1R_FBM8_Pos (8U)
Kojto 122:f9eeca106725 3140 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3141 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 3142 #define CAN_FM1R_FBM9_Pos (9U)
Kojto 122:f9eeca106725 3143 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3144 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 3145 #define CAN_FM1R_FBM10_Pos (10U)
Kojto 122:f9eeca106725 3146 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3147 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 3148 #define CAN_FM1R_FBM11_Pos (11U)
Kojto 122:f9eeca106725 3149 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3150 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 3151 #define CAN_FM1R_FBM12_Pos (12U)
Kojto 122:f9eeca106725 3152 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3153 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 3154 #define CAN_FM1R_FBM13_Pos (13U)
Kojto 122:f9eeca106725 3155 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3156 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
bogdanm 86:04dd9b1680ae 3157
bogdanm 86:04dd9b1680ae 3158 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 3159 #define CAN_FS1R_FSC_Pos (0U)
Kojto 122:f9eeca106725 3160 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 3161 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 3162 #define CAN_FS1R_FSC0_Pos (0U)
Kojto 122:f9eeca106725 3163 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3164 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 3165 #define CAN_FS1R_FSC1_Pos (1U)
Kojto 122:f9eeca106725 3166 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3167 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 3168 #define CAN_FS1R_FSC2_Pos (2U)
Kojto 122:f9eeca106725 3169 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3170 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 3171 #define CAN_FS1R_FSC3_Pos (3U)
Kojto 122:f9eeca106725 3172 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3173 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 3174 #define CAN_FS1R_FSC4_Pos (4U)
Kojto 122:f9eeca106725 3175 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3176 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 3177 #define CAN_FS1R_FSC5_Pos (5U)
Kojto 122:f9eeca106725 3178 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3179 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 3180 #define CAN_FS1R_FSC6_Pos (6U)
Kojto 122:f9eeca106725 3181 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3182 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 3183 #define CAN_FS1R_FSC7_Pos (7U)
Kojto 122:f9eeca106725 3184 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3185 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 3186 #define CAN_FS1R_FSC8_Pos (8U)
Kojto 122:f9eeca106725 3187 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3188 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 3189 #define CAN_FS1R_FSC9_Pos (9U)
Kojto 122:f9eeca106725 3190 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3191 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 3192 #define CAN_FS1R_FSC10_Pos (10U)
Kojto 122:f9eeca106725 3193 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3194 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 3195 #define CAN_FS1R_FSC11_Pos (11U)
Kojto 122:f9eeca106725 3196 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3197 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 3198 #define CAN_FS1R_FSC12_Pos (12U)
Kojto 122:f9eeca106725 3199 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3200 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 3201 #define CAN_FS1R_FSC13_Pos (13U)
Kojto 122:f9eeca106725 3202 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3203 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
bogdanm 86:04dd9b1680ae 3204
bogdanm 86:04dd9b1680ae 3205 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 3206 #define CAN_FFA1R_FFA_Pos (0U)
Kojto 122:f9eeca106725 3207 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 3208 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 3209 #define CAN_FFA1R_FFA0_Pos (0U)
Kojto 122:f9eeca106725 3210 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3211 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
Kojto 122:f9eeca106725 3212 #define CAN_FFA1R_FFA1_Pos (1U)
Kojto 122:f9eeca106725 3213 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3214 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
Kojto 122:f9eeca106725 3215 #define CAN_FFA1R_FFA2_Pos (2U)
Kojto 122:f9eeca106725 3216 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3217 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
Kojto 122:f9eeca106725 3218 #define CAN_FFA1R_FFA3_Pos (3U)
Kojto 122:f9eeca106725 3219 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3220 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
Kojto 122:f9eeca106725 3221 #define CAN_FFA1R_FFA4_Pos (4U)
Kojto 122:f9eeca106725 3222 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3223 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
Kojto 122:f9eeca106725 3224 #define CAN_FFA1R_FFA5_Pos (5U)
Kojto 122:f9eeca106725 3225 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3226 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
Kojto 122:f9eeca106725 3227 #define CAN_FFA1R_FFA6_Pos (6U)
Kojto 122:f9eeca106725 3228 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3229 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
Kojto 122:f9eeca106725 3230 #define CAN_FFA1R_FFA7_Pos (7U)
Kojto 122:f9eeca106725 3231 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3232 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
Kojto 122:f9eeca106725 3233 #define CAN_FFA1R_FFA8_Pos (8U)
Kojto 122:f9eeca106725 3234 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3235 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
Kojto 122:f9eeca106725 3236 #define CAN_FFA1R_FFA9_Pos (9U)
Kojto 122:f9eeca106725 3237 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3238 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
Kojto 122:f9eeca106725 3239 #define CAN_FFA1R_FFA10_Pos (10U)
Kojto 122:f9eeca106725 3240 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3241 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
Kojto 122:f9eeca106725 3242 #define CAN_FFA1R_FFA11_Pos (11U)
Kojto 122:f9eeca106725 3243 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3244 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
Kojto 122:f9eeca106725 3245 #define CAN_FFA1R_FFA12_Pos (12U)
Kojto 122:f9eeca106725 3246 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3247 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
Kojto 122:f9eeca106725 3248 #define CAN_FFA1R_FFA13_Pos (13U)
Kojto 122:f9eeca106725 3249 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3250 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 86:04dd9b1680ae 3251
bogdanm 86:04dd9b1680ae 3252 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 3253 #define CAN_FA1R_FACT_Pos (0U)
Kojto 122:f9eeca106725 3254 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 3255 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
Kojto 122:f9eeca106725 3256 #define CAN_FA1R_FACT0_Pos (0U)
Kojto 122:f9eeca106725 3257 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3258 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
Kojto 122:f9eeca106725 3259 #define CAN_FA1R_FACT1_Pos (1U)
Kojto 122:f9eeca106725 3260 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3261 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
Kojto 122:f9eeca106725 3262 #define CAN_FA1R_FACT2_Pos (2U)
Kojto 122:f9eeca106725 3263 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3264 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
Kojto 122:f9eeca106725 3265 #define CAN_FA1R_FACT3_Pos (3U)
Kojto 122:f9eeca106725 3266 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3267 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
Kojto 122:f9eeca106725 3268 #define CAN_FA1R_FACT4_Pos (4U)
Kojto 122:f9eeca106725 3269 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3270 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
Kojto 122:f9eeca106725 3271 #define CAN_FA1R_FACT5_Pos (5U)
Kojto 122:f9eeca106725 3272 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3273 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
Kojto 122:f9eeca106725 3274 #define CAN_FA1R_FACT6_Pos (6U)
Kojto 122:f9eeca106725 3275 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3276 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
Kojto 122:f9eeca106725 3277 #define CAN_FA1R_FACT7_Pos (7U)
Kojto 122:f9eeca106725 3278 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3279 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
Kojto 122:f9eeca106725 3280 #define CAN_FA1R_FACT8_Pos (8U)
Kojto 122:f9eeca106725 3281 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3282 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
Kojto 122:f9eeca106725 3283 #define CAN_FA1R_FACT9_Pos (9U)
Kojto 122:f9eeca106725 3284 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3285 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
Kojto 122:f9eeca106725 3286 #define CAN_FA1R_FACT10_Pos (10U)
Kojto 122:f9eeca106725 3287 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3288 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
Kojto 122:f9eeca106725 3289 #define CAN_FA1R_FACT11_Pos (11U)
Kojto 122:f9eeca106725 3290 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3291 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
Kojto 122:f9eeca106725 3292 #define CAN_FA1R_FACT12_Pos (12U)
Kojto 122:f9eeca106725 3293 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3294 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
Kojto 122:f9eeca106725 3295 #define CAN_FA1R_FACT13_Pos (13U)
Kojto 122:f9eeca106725 3296 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3297 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
bogdanm 86:04dd9b1680ae 3298
bogdanm 86:04dd9b1680ae 3299 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 3300 #define CAN_F0R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3301 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3302 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3303 #define CAN_F0R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3304 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3305 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3306 #define CAN_F0R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3307 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3308 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3309 #define CAN_F0R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3310 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3311 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3312 #define CAN_F0R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3313 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3314 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3315 #define CAN_F0R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3316 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3317 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3318 #define CAN_F0R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3319 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3320 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3321 #define CAN_F0R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3322 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3323 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3324 #define CAN_F0R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3325 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3326 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3327 #define CAN_F0R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3328 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3329 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3330 #define CAN_F0R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3331 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3332 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3333 #define CAN_F0R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3334 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3335 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3336 #define CAN_F0R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3337 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3338 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3339 #define CAN_F0R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3340 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3341 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3342 #define CAN_F0R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3343 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3344 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3345 #define CAN_F0R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3346 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3347 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3348 #define CAN_F0R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3349 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3350 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3351 #define CAN_F0R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3352 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3353 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3354 #define CAN_F0R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3355 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3356 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3357 #define CAN_F0R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3358 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3359 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3360 #define CAN_F0R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3361 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3362 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3363 #define CAN_F0R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3364 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3365 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3366 #define CAN_F0R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3367 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3368 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3369 #define CAN_F0R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3370 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3371 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3372 #define CAN_F0R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3373 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3374 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3375 #define CAN_F0R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3376 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3377 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3378 #define CAN_F0R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3379 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3380 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3381 #define CAN_F0R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3382 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3383 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3384 #define CAN_F0R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3385 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3386 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3387 #define CAN_F0R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3388 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3389 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3390 #define CAN_F0R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3391 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3392 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3393 #define CAN_F0R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3394 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3395 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3396
bogdanm 86:04dd9b1680ae 3397 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 3398 #define CAN_F1R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3399 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3400 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3401 #define CAN_F1R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3402 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3403 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3404 #define CAN_F1R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3405 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3406 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3407 #define CAN_F1R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3408 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3409 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3410 #define CAN_F1R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3411 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3412 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3413 #define CAN_F1R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3414 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3415 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3416 #define CAN_F1R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3417 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3418 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3419 #define CAN_F1R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3420 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3421 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3422 #define CAN_F1R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3423 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3424 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3425 #define CAN_F1R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3426 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3427 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3428 #define CAN_F1R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3429 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3430 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3431 #define CAN_F1R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3432 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3433 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3434 #define CAN_F1R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3435 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3436 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3437 #define CAN_F1R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3438 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3439 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3440 #define CAN_F1R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3441 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3442 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3443 #define CAN_F1R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3444 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3445 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3446 #define CAN_F1R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3447 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3448 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3449 #define CAN_F1R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3450 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3451 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3452 #define CAN_F1R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3453 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3454 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3455 #define CAN_F1R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3456 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3457 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3458 #define CAN_F1R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3459 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3460 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3461 #define CAN_F1R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3462 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3463 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3464 #define CAN_F1R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3465 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3466 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3467 #define CAN_F1R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3468 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3469 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3470 #define CAN_F1R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3471 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3472 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3473 #define CAN_F1R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3474 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3475 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3476 #define CAN_F1R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3477 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3478 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3479 #define CAN_F1R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3480 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3481 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3482 #define CAN_F1R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3483 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3484 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3485 #define CAN_F1R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3486 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3487 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3488 #define CAN_F1R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3489 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3490 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3491 #define CAN_F1R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3492 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3493 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3494
bogdanm 86:04dd9b1680ae 3495 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 3496 #define CAN_F2R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3497 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3498 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3499 #define CAN_F2R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3500 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3501 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3502 #define CAN_F2R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3503 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3504 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3505 #define CAN_F2R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3506 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3507 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3508 #define CAN_F2R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3509 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3510 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3511 #define CAN_F2R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3512 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3513 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3514 #define CAN_F2R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3515 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3516 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3517 #define CAN_F2R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3518 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3519 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3520 #define CAN_F2R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3521 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3522 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3523 #define CAN_F2R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3524 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3525 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3526 #define CAN_F2R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3527 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3528 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3529 #define CAN_F2R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3530 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3531 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3532 #define CAN_F2R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3533 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3534 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3535 #define CAN_F2R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3536 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3537 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3538 #define CAN_F2R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3539 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3540 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3541 #define CAN_F2R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3542 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3543 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3544 #define CAN_F2R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3545 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3546 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3547 #define CAN_F2R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3548 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3549 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3550 #define CAN_F2R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3551 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3552 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3553 #define CAN_F2R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3554 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3555 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3556 #define CAN_F2R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3557 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3558 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3559 #define CAN_F2R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3560 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3561 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3562 #define CAN_F2R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3563 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3564 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3565 #define CAN_F2R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3566 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3567 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3568 #define CAN_F2R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3569 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3570 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3571 #define CAN_F2R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3572 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3573 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3574 #define CAN_F2R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3575 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3576 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3577 #define CAN_F2R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3578 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3579 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3580 #define CAN_F2R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3581 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3582 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3583 #define CAN_F2R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3584 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3585 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3586 #define CAN_F2R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3587 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3588 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3589 #define CAN_F2R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3590 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3591 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3592
bogdanm 86:04dd9b1680ae 3593 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 3594 #define CAN_F3R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3595 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3596 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3597 #define CAN_F3R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3598 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3599 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3600 #define CAN_F3R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3601 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3602 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3603 #define CAN_F3R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3604 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3605 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3606 #define CAN_F3R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3607 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3608 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3609 #define CAN_F3R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3610 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3611 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3612 #define CAN_F3R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3613 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3614 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3615 #define CAN_F3R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3616 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3617 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3618 #define CAN_F3R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3619 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3620 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3621 #define CAN_F3R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3622 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3623 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3624 #define CAN_F3R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3625 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3626 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3627 #define CAN_F3R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3628 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3629 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3630 #define CAN_F3R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3631 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3632 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3633 #define CAN_F3R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3634 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3635 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3636 #define CAN_F3R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3637 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3638 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3639 #define CAN_F3R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3640 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3641 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3642 #define CAN_F3R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3643 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3644 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3645 #define CAN_F3R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3646 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3647 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3648 #define CAN_F3R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3649 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3650 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3651 #define CAN_F3R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3652 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3653 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3654 #define CAN_F3R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3655 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3656 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3657 #define CAN_F3R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3658 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3659 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3660 #define CAN_F3R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3661 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3662 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3663 #define CAN_F3R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3664 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3665 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3666 #define CAN_F3R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3667 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3668 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3669 #define CAN_F3R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3670 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3671 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3672 #define CAN_F3R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3673 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3674 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3675 #define CAN_F3R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3676 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3677 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3678 #define CAN_F3R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3679 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3680 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3681 #define CAN_F3R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3682 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3683 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3684 #define CAN_F3R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3685 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3686 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3687 #define CAN_F3R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3688 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3689 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3690
bogdanm 86:04dd9b1680ae 3691 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 3692 #define CAN_F4R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3693 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3694 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3695 #define CAN_F4R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3696 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3697 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3698 #define CAN_F4R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3699 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3700 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3701 #define CAN_F4R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3702 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3703 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3704 #define CAN_F4R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3705 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3706 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3707 #define CAN_F4R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3708 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3709 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3710 #define CAN_F4R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3711 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3712 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3713 #define CAN_F4R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3714 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3715 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3716 #define CAN_F4R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3717 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3718 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3719 #define CAN_F4R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3720 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3721 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3722 #define CAN_F4R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3723 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3724 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3725 #define CAN_F4R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3726 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3727 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3728 #define CAN_F4R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3729 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3730 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3731 #define CAN_F4R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3732 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3733 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3734 #define CAN_F4R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3735 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3736 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3737 #define CAN_F4R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3738 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3739 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3740 #define CAN_F4R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3741 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3742 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3743 #define CAN_F4R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3744 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3745 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3746 #define CAN_F4R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3747 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3748 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3749 #define CAN_F4R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3750 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3751 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3752 #define CAN_F4R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3753 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3754 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3755 #define CAN_F4R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3756 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3757 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3758 #define CAN_F4R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3759 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3760 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3761 #define CAN_F4R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3762 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3763 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3764 #define CAN_F4R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3765 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3766 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3767 #define CAN_F4R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3768 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3769 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3770 #define CAN_F4R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3771 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3772 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3773 #define CAN_F4R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3774 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3775 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3776 #define CAN_F4R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3777 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3778 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3779 #define CAN_F4R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3780 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3781 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3782 #define CAN_F4R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3783 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3784 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3785 #define CAN_F4R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3786 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3787 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3788
bogdanm 86:04dd9b1680ae 3789 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 3790 #define CAN_F5R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3791 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3792 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3793 #define CAN_F5R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3794 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3795 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3796 #define CAN_F5R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3797 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3798 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3799 #define CAN_F5R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3800 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3801 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3802 #define CAN_F5R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3803 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3804 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3805 #define CAN_F5R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3806 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3807 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3808 #define CAN_F5R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3809 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3810 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3811 #define CAN_F5R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3812 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3813 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3814 #define CAN_F5R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3815 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3816 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3817 #define CAN_F5R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3818 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3819 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3820 #define CAN_F5R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3821 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3822 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3823 #define CAN_F5R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3824 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3825 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3826 #define CAN_F5R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3827 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3828 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3829 #define CAN_F5R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3830 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3831 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3832 #define CAN_F5R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3833 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3834 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3835 #define CAN_F5R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3836 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3837 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3838 #define CAN_F5R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3839 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3840 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3841 #define CAN_F5R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3842 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3843 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3844 #define CAN_F5R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3845 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3846 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3847 #define CAN_F5R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3848 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3849 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3850 #define CAN_F5R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3851 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3852 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3853 #define CAN_F5R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3854 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3855 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3856 #define CAN_F5R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3857 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3858 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3859 #define CAN_F5R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3860 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3861 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3862 #define CAN_F5R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3863 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3864 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3865 #define CAN_F5R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3866 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3867 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3868 #define CAN_F5R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3869 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3870 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3871 #define CAN_F5R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3872 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3873 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3874 #define CAN_F5R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3875 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3876 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3877 #define CAN_F5R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3878 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3879 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3880 #define CAN_F5R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3881 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3882 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3883 #define CAN_F5R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3884 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3885 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3886
bogdanm 86:04dd9b1680ae 3887 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 3888 #define CAN_F6R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3889 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3890 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3891 #define CAN_F6R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3892 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3893 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3894 #define CAN_F6R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3895 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3896 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3897 #define CAN_F6R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3898 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3899 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3900 #define CAN_F6R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3901 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3902 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3903 #define CAN_F6R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3904 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3905 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3906 #define CAN_F6R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3907 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3908 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3909 #define CAN_F6R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3910 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3911 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3912 #define CAN_F6R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3913 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3914 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3915 #define CAN_F6R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3916 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3917 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3918 #define CAN_F6R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3919 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3920 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3921 #define CAN_F6R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3922 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3923 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3924 #define CAN_F6R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3925 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3926 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3927 #define CAN_F6R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3928 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3929 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3930 #define CAN_F6R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3931 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3932 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3933 #define CAN_F6R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3934 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3935 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3936 #define CAN_F6R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3937 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3938 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3939 #define CAN_F6R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3940 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3941 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3942 #define CAN_F6R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3943 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3944 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3945 #define CAN_F6R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3946 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3947 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3948 #define CAN_F6R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3949 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3950 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3951 #define CAN_F6R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3952 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3953 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3954 #define CAN_F6R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3955 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3956 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3957 #define CAN_F6R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3958 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3959 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3960 #define CAN_F6R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3961 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3962 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3963 #define CAN_F6R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3964 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3965 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3966 #define CAN_F6R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3967 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3968 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3969 #define CAN_F6R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3970 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3971 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3972 #define CAN_F6R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3973 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3974 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3975 #define CAN_F6R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3976 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3977 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3978 #define CAN_F6R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3979 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3980 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3981 #define CAN_F6R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3982 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3983 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 3984
bogdanm 86:04dd9b1680ae 3985 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 3986 #define CAN_F7R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3987 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3988 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3989 #define CAN_F7R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3990 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3991 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3992 #define CAN_F7R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3993 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3994 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3995 #define CAN_F7R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3996 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3997 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3998 #define CAN_F7R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3999 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4000 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4001 #define CAN_F7R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4002 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4003 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4004 #define CAN_F7R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4005 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4006 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4007 #define CAN_F7R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4008 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4009 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4010 #define CAN_F7R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4011 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4012 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4013 #define CAN_F7R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4014 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4015 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4016 #define CAN_F7R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4017 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4018 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4019 #define CAN_F7R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4020 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4021 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4022 #define CAN_F7R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4023 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4024 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4025 #define CAN_F7R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4026 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4027 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4028 #define CAN_F7R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4029 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4030 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4031 #define CAN_F7R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4032 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4033 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4034 #define CAN_F7R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4035 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4036 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4037 #define CAN_F7R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4038 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4039 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4040 #define CAN_F7R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4041 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4042 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4043 #define CAN_F7R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4044 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4045 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4046 #define CAN_F7R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4047 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4048 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4049 #define CAN_F7R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4050 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4051 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4052 #define CAN_F7R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4053 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4054 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4055 #define CAN_F7R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4056 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4057 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4058 #define CAN_F7R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4059 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4060 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4061 #define CAN_F7R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4062 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4063 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4064 #define CAN_F7R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4065 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4066 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4067 #define CAN_F7R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4068 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4069 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4070 #define CAN_F7R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4071 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4072 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4073 #define CAN_F7R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4074 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4075 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4076 #define CAN_F7R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4077 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4078 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4079 #define CAN_F7R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4080 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4081 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4082
bogdanm 86:04dd9b1680ae 4083 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 4084 #define CAN_F8R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4085 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4086 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4087 #define CAN_F8R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4088 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4089 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4090 #define CAN_F8R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4091 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4092 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4093 #define CAN_F8R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4094 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4095 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4096 #define CAN_F8R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4097 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4098 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4099 #define CAN_F8R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4100 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4101 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4102 #define CAN_F8R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4103 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4104 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4105 #define CAN_F8R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4106 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4107 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4108 #define CAN_F8R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4109 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4110 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4111 #define CAN_F8R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4112 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4113 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4114 #define CAN_F8R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4115 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4116 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4117 #define CAN_F8R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4118 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4119 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4120 #define CAN_F8R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4121 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4122 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4123 #define CAN_F8R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4124 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4125 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4126 #define CAN_F8R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4127 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4128 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4129 #define CAN_F8R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4130 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4131 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4132 #define CAN_F8R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4133 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4134 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4135 #define CAN_F8R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4136 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4137 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4138 #define CAN_F8R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4139 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4140 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4141 #define CAN_F8R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4142 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4143 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4144 #define CAN_F8R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4145 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4146 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4147 #define CAN_F8R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4148 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4149 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4150 #define CAN_F8R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4151 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4152 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4153 #define CAN_F8R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4154 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4155 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4156 #define CAN_F8R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4157 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4158 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4159 #define CAN_F8R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4160 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4161 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4162 #define CAN_F8R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4163 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4164 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4165 #define CAN_F8R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4166 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4167 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4168 #define CAN_F8R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4169 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4170 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4171 #define CAN_F8R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4172 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4173 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4174 #define CAN_F8R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4175 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4176 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4177 #define CAN_F8R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4178 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4179 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4180
bogdanm 86:04dd9b1680ae 4181 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 4182 #define CAN_F9R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4183 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4184 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4185 #define CAN_F9R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4186 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4187 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4188 #define CAN_F9R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4189 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4190 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4191 #define CAN_F9R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4192 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4193 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4194 #define CAN_F9R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4195 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4196 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4197 #define CAN_F9R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4198 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4199 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4200 #define CAN_F9R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4201 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4202 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4203 #define CAN_F9R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4204 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4205 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4206 #define CAN_F9R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4207 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4208 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4209 #define CAN_F9R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4210 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4211 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4212 #define CAN_F9R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4213 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4214 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4215 #define CAN_F9R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4216 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4217 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4218 #define CAN_F9R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4219 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4220 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4221 #define CAN_F9R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4222 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4223 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4224 #define CAN_F9R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4225 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4226 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4227 #define CAN_F9R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4228 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4229 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4230 #define CAN_F9R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4231 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4232 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4233 #define CAN_F9R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4234 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4235 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4236 #define CAN_F9R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4237 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4238 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4239 #define CAN_F9R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4240 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4241 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4242 #define CAN_F9R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4243 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4244 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4245 #define CAN_F9R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4246 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4247 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4248 #define CAN_F9R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4249 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4250 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4251 #define CAN_F9R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4252 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4253 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4254 #define CAN_F9R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4255 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4256 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4257 #define CAN_F9R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4258 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4259 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4260 #define CAN_F9R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4261 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4262 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4263 #define CAN_F9R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4264 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4265 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4266 #define CAN_F9R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4267 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4268 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4269 #define CAN_F9R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4270 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4271 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4272 #define CAN_F9R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4273 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4274 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4275 #define CAN_F9R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4276 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4277 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4278
bogdanm 86:04dd9b1680ae 4279 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 4280 #define CAN_F10R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4281 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4282 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4283 #define CAN_F10R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4284 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4285 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4286 #define CAN_F10R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4287 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4288 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4289 #define CAN_F10R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4290 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4291 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4292 #define CAN_F10R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4293 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4294 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4295 #define CAN_F10R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4296 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4297 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4298 #define CAN_F10R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4299 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4300 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4301 #define CAN_F10R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4302 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4303 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4304 #define CAN_F10R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4305 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4306 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4307 #define CAN_F10R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4308 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4309 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4310 #define CAN_F10R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4311 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4312 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4313 #define CAN_F10R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4314 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4315 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4316 #define CAN_F10R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4317 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4318 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4319 #define CAN_F10R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4320 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4321 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4322 #define CAN_F10R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4323 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4324 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4325 #define CAN_F10R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4326 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4327 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4328 #define CAN_F10R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4329 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4330 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4331 #define CAN_F10R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4332 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4333 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4334 #define CAN_F10R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4335 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4336 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4337 #define CAN_F10R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4338 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4339 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4340 #define CAN_F10R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4341 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4342 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4343 #define CAN_F10R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4344 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4345 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4346 #define CAN_F10R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4347 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4348 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4349 #define CAN_F10R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4350 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4351 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4352 #define CAN_F10R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4353 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4354 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4355 #define CAN_F10R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4356 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4357 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4358 #define CAN_F10R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4359 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4360 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4361 #define CAN_F10R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4362 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4363 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4364 #define CAN_F10R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4365 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4366 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4367 #define CAN_F10R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4368 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4369 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4370 #define CAN_F10R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4371 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4372 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4373 #define CAN_F10R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4374 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4375 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4376
bogdanm 86:04dd9b1680ae 4377 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 4378 #define CAN_F11R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4379 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4380 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4381 #define CAN_F11R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4382 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4383 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4384 #define CAN_F11R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4385 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4386 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4387 #define CAN_F11R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4388 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4389 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4390 #define CAN_F11R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4391 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4392 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4393 #define CAN_F11R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4394 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4395 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4396 #define CAN_F11R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4397 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4398 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4399 #define CAN_F11R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4400 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4401 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4402 #define CAN_F11R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4403 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4404 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4405 #define CAN_F11R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4406 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4407 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4408 #define CAN_F11R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4409 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4410 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4411 #define CAN_F11R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4412 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4413 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4414 #define CAN_F11R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4415 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4416 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4417 #define CAN_F11R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4418 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4419 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4420 #define CAN_F11R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4421 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4422 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4423 #define CAN_F11R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4424 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4425 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4426 #define CAN_F11R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4427 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4428 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4429 #define CAN_F11R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4430 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4431 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4432 #define CAN_F11R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4433 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4434 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4435 #define CAN_F11R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4436 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4437 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4438 #define CAN_F11R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4439 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4440 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4441 #define CAN_F11R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4442 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4443 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4444 #define CAN_F11R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4445 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4446 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4447 #define CAN_F11R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4448 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4449 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4450 #define CAN_F11R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4451 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4452 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4453 #define CAN_F11R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4454 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4455 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4456 #define CAN_F11R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4457 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4458 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4459 #define CAN_F11R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4460 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4461 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4462 #define CAN_F11R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4463 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4464 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4465 #define CAN_F11R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4466 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4467 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4468 #define CAN_F11R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4469 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4470 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4471 #define CAN_F11R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4472 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4473 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4474
bogdanm 86:04dd9b1680ae 4475 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 4476 #define CAN_F12R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4477 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4478 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4479 #define CAN_F12R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4480 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4481 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4482 #define CAN_F12R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4483 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4484 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4485 #define CAN_F12R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4486 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4487 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4488 #define CAN_F12R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4489 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4490 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4491 #define CAN_F12R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4492 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4493 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4494 #define CAN_F12R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4495 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4496 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4497 #define CAN_F12R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4498 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4499 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4500 #define CAN_F12R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4501 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4502 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4503 #define CAN_F12R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4504 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4505 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4506 #define CAN_F12R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4507 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4508 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4509 #define CAN_F12R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4510 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4511 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4512 #define CAN_F12R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4513 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4514 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4515 #define CAN_F12R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4516 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4517 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4518 #define CAN_F12R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4519 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4520 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4521 #define CAN_F12R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4522 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4523 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4524 #define CAN_F12R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4525 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4526 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4527 #define CAN_F12R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4528 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4529 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4530 #define CAN_F12R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4531 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4532 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4533 #define CAN_F12R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4534 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4535 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4536 #define CAN_F12R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4537 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4538 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4539 #define CAN_F12R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4540 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4541 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4542 #define CAN_F12R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4543 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4544 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4545 #define CAN_F12R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4546 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4547 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4548 #define CAN_F12R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4549 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4550 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4551 #define CAN_F12R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4552 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4553 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4554 #define CAN_F12R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4555 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4556 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4557 #define CAN_F12R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4558 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4559 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4560 #define CAN_F12R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4561 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4562 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4563 #define CAN_F12R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4564 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4565 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4566 #define CAN_F12R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4567 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4568 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4569 #define CAN_F12R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4570 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4571 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4572
bogdanm 86:04dd9b1680ae 4573 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 4574 #define CAN_F13R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4575 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4576 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4577 #define CAN_F13R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4578 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4579 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4580 #define CAN_F13R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4581 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4582 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4583 #define CAN_F13R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4584 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4585 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4586 #define CAN_F13R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4587 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4588 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4589 #define CAN_F13R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4590 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4591 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4592 #define CAN_F13R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4593 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4594 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4595 #define CAN_F13R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4596 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4597 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4598 #define CAN_F13R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4599 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4600 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4601 #define CAN_F13R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4602 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4603 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4604 #define CAN_F13R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4605 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4606 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4607 #define CAN_F13R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4608 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4609 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4610 #define CAN_F13R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4611 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4612 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4613 #define CAN_F13R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4614 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4615 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4616 #define CAN_F13R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4617 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4618 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4619 #define CAN_F13R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4620 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4621 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4622 #define CAN_F13R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4623 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4624 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4625 #define CAN_F13R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4626 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4627 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4628 #define CAN_F13R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4629 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4630 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4631 #define CAN_F13R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4632 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4633 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4634 #define CAN_F13R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4635 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4636 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4637 #define CAN_F13R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4638 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4639 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4640 #define CAN_F13R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4641 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4642 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4643 #define CAN_F13R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4644 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4645 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4646 #define CAN_F13R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4647 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4648 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4649 #define CAN_F13R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4650 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4651 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4652 #define CAN_F13R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4653 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4654 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4655 #define CAN_F13R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4656 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4657 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4658 #define CAN_F13R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4659 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4660 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4661 #define CAN_F13R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4662 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4663 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4664 #define CAN_F13R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4665 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4666 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4667 #define CAN_F13R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4668 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4669 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4670
bogdanm 86:04dd9b1680ae 4671 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 4672 #define CAN_F0R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4673 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4674 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4675 #define CAN_F0R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4676 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4677 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4678 #define CAN_F0R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4679 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4680 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4681 #define CAN_F0R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4682 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4683 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4684 #define CAN_F0R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4685 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4686 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4687 #define CAN_F0R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4688 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4689 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4690 #define CAN_F0R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4691 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4692 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4693 #define CAN_F0R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4694 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4695 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4696 #define CAN_F0R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4697 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4698 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4699 #define CAN_F0R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4700 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4701 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4702 #define CAN_F0R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4703 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4704 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4705 #define CAN_F0R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4706 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4707 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4708 #define CAN_F0R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4709 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4710 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4711 #define CAN_F0R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4712 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4713 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4714 #define CAN_F0R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4715 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4716 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4717 #define CAN_F0R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4718 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4719 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4720 #define CAN_F0R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4721 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4722 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4723 #define CAN_F0R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4724 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4725 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4726 #define CAN_F0R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4727 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4728 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4729 #define CAN_F0R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4730 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4731 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4732 #define CAN_F0R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4733 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4734 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4735 #define CAN_F0R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4736 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4737 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4738 #define CAN_F0R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4739 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4740 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4741 #define CAN_F0R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4742 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4743 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4744 #define CAN_F0R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4745 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4746 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4747 #define CAN_F0R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4748 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4749 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4750 #define CAN_F0R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4751 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4752 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4753 #define CAN_F0R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4754 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4755 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4756 #define CAN_F0R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4757 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4758 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4759 #define CAN_F0R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4760 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4761 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4762 #define CAN_F0R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4763 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4764 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4765 #define CAN_F0R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4766 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4767 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4768
bogdanm 86:04dd9b1680ae 4769 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 4770 #define CAN_F1R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4771 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4772 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4773 #define CAN_F1R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4774 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4775 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4776 #define CAN_F1R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4777 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4778 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4779 #define CAN_F1R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4780 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4781 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4782 #define CAN_F1R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4783 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4784 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4785 #define CAN_F1R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4786 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4787 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4788 #define CAN_F1R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4789 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4790 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4791 #define CAN_F1R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4792 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4793 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4794 #define CAN_F1R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4795 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4796 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4797 #define CAN_F1R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4798 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4799 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4800 #define CAN_F1R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4801 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4802 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4803 #define CAN_F1R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4804 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4805 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4806 #define CAN_F1R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4807 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4808 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4809 #define CAN_F1R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4810 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4811 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4812 #define CAN_F1R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4813 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4814 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4815 #define CAN_F1R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4816 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4817 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4818 #define CAN_F1R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4819 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4820 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4821 #define CAN_F1R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4822 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4823 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4824 #define CAN_F1R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4825 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4826 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4827 #define CAN_F1R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4828 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4829 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4830 #define CAN_F1R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4831 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4832 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4833 #define CAN_F1R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4834 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4835 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4836 #define CAN_F1R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4837 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4838 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4839 #define CAN_F1R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4840 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4841 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4842 #define CAN_F1R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4843 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4844 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4845 #define CAN_F1R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4846 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4847 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4848 #define CAN_F1R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4849 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4850 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4851 #define CAN_F1R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4852 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4853 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4854 #define CAN_F1R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4855 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4856 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4857 #define CAN_F1R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4858 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4859 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4860 #define CAN_F1R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4861 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4862 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4863 #define CAN_F1R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4864 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4865 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4866
bogdanm 86:04dd9b1680ae 4867 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 4868 #define CAN_F2R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4869 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4870 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4871 #define CAN_F2R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4872 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4873 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4874 #define CAN_F2R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4875 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4876 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4877 #define CAN_F2R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4878 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4879 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4880 #define CAN_F2R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4881 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4882 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4883 #define CAN_F2R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4884 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4885 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4886 #define CAN_F2R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4887 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4888 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4889 #define CAN_F2R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4890 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4891 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4892 #define CAN_F2R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4893 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4894 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4895 #define CAN_F2R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4896 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4897 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4898 #define CAN_F2R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4899 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4900 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4901 #define CAN_F2R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4902 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4903 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4904 #define CAN_F2R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4905 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4906 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4907 #define CAN_F2R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4908 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4909 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4910 #define CAN_F2R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4911 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4912 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4913 #define CAN_F2R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4914 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4915 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4916 #define CAN_F2R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4917 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4918 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4919 #define CAN_F2R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4920 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4921 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4922 #define CAN_F2R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4923 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4924 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4925 #define CAN_F2R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4926 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4927 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4928 #define CAN_F2R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4929 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4930 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4931 #define CAN_F2R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4932 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4933 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4934 #define CAN_F2R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4935 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4936 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4937 #define CAN_F2R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4938 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4939 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4940 #define CAN_F2R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4941 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4942 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4943 #define CAN_F2R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4944 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4945 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4946 #define CAN_F2R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4947 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4948 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4949 #define CAN_F2R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4950 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4951 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4952 #define CAN_F2R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4953 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4954 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4955 #define CAN_F2R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4956 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4957 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4958 #define CAN_F2R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4959 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4960 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4961 #define CAN_F2R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4962 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4963 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 4964
bogdanm 86:04dd9b1680ae 4965 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 4966 #define CAN_F3R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4967 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4968 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4969 #define CAN_F3R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4970 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4971 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4972 #define CAN_F3R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4973 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4974 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4975 #define CAN_F3R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4976 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4977 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4978 #define CAN_F3R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4979 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4980 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4981 #define CAN_F3R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4982 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4983 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4984 #define CAN_F3R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4985 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4986 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4987 #define CAN_F3R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4988 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4989 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4990 #define CAN_F3R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4991 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4992 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4993 #define CAN_F3R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4994 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4995 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4996 #define CAN_F3R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4997 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4998 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4999 #define CAN_F3R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5000 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5001 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5002 #define CAN_F3R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5003 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5004 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5005 #define CAN_F3R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5006 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5007 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5008 #define CAN_F3R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5009 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5010 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5011 #define CAN_F3R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5012 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5013 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5014 #define CAN_F3R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5015 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5016 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5017 #define CAN_F3R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5018 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5019 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5020 #define CAN_F3R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5021 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5022 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5023 #define CAN_F3R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5024 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5025 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5026 #define CAN_F3R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5027 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5028 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5029 #define CAN_F3R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5030 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5031 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5032 #define CAN_F3R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5033 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5034 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5035 #define CAN_F3R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5036 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5037 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5038 #define CAN_F3R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5039 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5040 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5041 #define CAN_F3R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5042 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5043 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5044 #define CAN_F3R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5045 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5046 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5047 #define CAN_F3R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5048 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5049 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5050 #define CAN_F3R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5051 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5052 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5053 #define CAN_F3R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5054 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5055 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5056 #define CAN_F3R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5057 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5058 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5059 #define CAN_F3R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5060 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5061 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5062
bogdanm 86:04dd9b1680ae 5063 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 5064 #define CAN_F4R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5065 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5066 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5067 #define CAN_F4R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5068 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5069 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5070 #define CAN_F4R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5071 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5072 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5073 #define CAN_F4R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5074 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5075 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5076 #define CAN_F4R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5077 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5078 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5079 #define CAN_F4R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5080 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5081 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5082 #define CAN_F4R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5083 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5084 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5085 #define CAN_F4R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5086 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5087 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5088 #define CAN_F4R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5089 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5090 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5091 #define CAN_F4R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5092 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5093 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5094 #define CAN_F4R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5095 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5096 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5097 #define CAN_F4R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5098 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5099 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5100 #define CAN_F4R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5101 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5102 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5103 #define CAN_F4R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5104 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5105 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5106 #define CAN_F4R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5107 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5108 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5109 #define CAN_F4R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5110 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5111 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5112 #define CAN_F4R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5113 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5114 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5115 #define CAN_F4R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5116 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5117 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5118 #define CAN_F4R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5119 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5120 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5121 #define CAN_F4R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5122 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5123 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5124 #define CAN_F4R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5125 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5126 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5127 #define CAN_F4R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5128 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5129 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5130 #define CAN_F4R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5131 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5132 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5133 #define CAN_F4R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5134 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5135 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5136 #define CAN_F4R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5137 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5138 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5139 #define CAN_F4R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5140 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5141 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5142 #define CAN_F4R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5143 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5144 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5145 #define CAN_F4R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5146 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5147 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5148 #define CAN_F4R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5149 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5150 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5151 #define CAN_F4R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5152 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5153 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5154 #define CAN_F4R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5155 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5156 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5157 #define CAN_F4R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5158 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5159 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5160
bogdanm 86:04dd9b1680ae 5161 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 5162 #define CAN_F5R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5163 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5164 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5165 #define CAN_F5R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5166 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5167 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5168 #define CAN_F5R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5169 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5170 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5171 #define CAN_F5R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5172 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5173 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5174 #define CAN_F5R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5175 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5176 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5177 #define CAN_F5R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5178 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5179 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5180 #define CAN_F5R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5181 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5182 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5183 #define CAN_F5R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5184 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5185 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5186 #define CAN_F5R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5187 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5188 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5189 #define CAN_F5R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5190 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5191 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5192 #define CAN_F5R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5193 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5194 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5195 #define CAN_F5R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5196 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5197 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5198 #define CAN_F5R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5199 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5200 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5201 #define CAN_F5R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5202 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5203 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5204 #define CAN_F5R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5205 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5206 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5207 #define CAN_F5R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5208 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5209 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5210 #define CAN_F5R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5211 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5212 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5213 #define CAN_F5R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5214 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5215 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5216 #define CAN_F5R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5217 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5218 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5219 #define CAN_F5R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5220 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5221 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5222 #define CAN_F5R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5223 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5224 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5225 #define CAN_F5R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5226 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5227 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5228 #define CAN_F5R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5229 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5230 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5231 #define CAN_F5R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5232 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5233 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5234 #define CAN_F5R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5235 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5236 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5237 #define CAN_F5R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5238 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5239 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5240 #define CAN_F5R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5241 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5242 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5243 #define CAN_F5R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5244 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5245 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5246 #define CAN_F5R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5247 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5248 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5249 #define CAN_F5R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5250 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5251 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5252 #define CAN_F5R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5253 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5254 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5255 #define CAN_F5R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5256 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5257 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5258
bogdanm 86:04dd9b1680ae 5259 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 5260 #define CAN_F6R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5261 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5262 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5263 #define CAN_F6R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5264 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5265 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5266 #define CAN_F6R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5267 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5268 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5269 #define CAN_F6R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5270 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5271 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5272 #define CAN_F6R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5273 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5274 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5275 #define CAN_F6R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5276 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5277 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5278 #define CAN_F6R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5279 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5280 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5281 #define CAN_F6R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5282 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5283 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5284 #define CAN_F6R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5285 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5286 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5287 #define CAN_F6R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5288 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5289 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5290 #define CAN_F6R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5291 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5292 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5293 #define CAN_F6R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5294 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5295 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5296 #define CAN_F6R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5297 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5298 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5299 #define CAN_F6R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5300 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5301 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5302 #define CAN_F6R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5303 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5304 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5305 #define CAN_F6R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5306 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5307 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5308 #define CAN_F6R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5309 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5310 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5311 #define CAN_F6R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5312 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5313 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5314 #define CAN_F6R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5315 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5316 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5317 #define CAN_F6R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5318 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5319 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5320 #define CAN_F6R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5321 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5322 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5323 #define CAN_F6R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5324 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5325 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5326 #define CAN_F6R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5327 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5328 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5329 #define CAN_F6R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5330 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5331 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5332 #define CAN_F6R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5333 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5334 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5335 #define CAN_F6R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5336 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5337 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5338 #define CAN_F6R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5339 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5340 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5341 #define CAN_F6R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5342 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5343 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5344 #define CAN_F6R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5345 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5346 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5347 #define CAN_F6R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5348 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5349 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5350 #define CAN_F6R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5351 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5352 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5353 #define CAN_F6R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5354 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5355 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5356
bogdanm 86:04dd9b1680ae 5357 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 5358 #define CAN_F7R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5359 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5360 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5361 #define CAN_F7R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5362 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5363 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5364 #define CAN_F7R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5365 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5366 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5367 #define CAN_F7R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5368 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5369 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5370 #define CAN_F7R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5371 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5372 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5373 #define CAN_F7R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5374 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5375 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5376 #define CAN_F7R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5377 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5378 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5379 #define CAN_F7R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5380 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5381 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5382 #define CAN_F7R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5383 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5384 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5385 #define CAN_F7R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5386 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5387 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5388 #define CAN_F7R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5389 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5390 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5391 #define CAN_F7R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5392 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5393 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5394 #define CAN_F7R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5395 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5396 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5397 #define CAN_F7R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5398 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5399 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5400 #define CAN_F7R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5401 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5402 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5403 #define CAN_F7R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5404 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5405 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5406 #define CAN_F7R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5407 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5408 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5409 #define CAN_F7R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5410 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5411 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5412 #define CAN_F7R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5413 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5414 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5415 #define CAN_F7R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5416 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5417 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5418 #define CAN_F7R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5419 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5420 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5421 #define CAN_F7R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5422 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5423 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5424 #define CAN_F7R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5425 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5426 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5427 #define CAN_F7R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5428 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5429 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5430 #define CAN_F7R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5431 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5432 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5433 #define CAN_F7R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5434 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5435 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5436 #define CAN_F7R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5437 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5438 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5439 #define CAN_F7R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5440 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5441 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5442 #define CAN_F7R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5443 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5444 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5445 #define CAN_F7R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5446 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5447 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5448 #define CAN_F7R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5449 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5450 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5451 #define CAN_F7R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5452 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5453 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5454
bogdanm 86:04dd9b1680ae 5455 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 5456 #define CAN_F8R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5457 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5458 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5459 #define CAN_F8R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5460 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5461 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5462 #define CAN_F8R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5463 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5464 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5465 #define CAN_F8R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5466 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5467 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5468 #define CAN_F8R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5469 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5470 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5471 #define CAN_F8R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5472 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5473 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5474 #define CAN_F8R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5475 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5476 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5477 #define CAN_F8R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5478 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5479 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5480 #define CAN_F8R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5481 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5482 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5483 #define CAN_F8R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5484 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5485 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5486 #define CAN_F8R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5487 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5488 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5489 #define CAN_F8R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5490 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5491 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5492 #define CAN_F8R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5493 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5494 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5495 #define CAN_F8R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5496 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5497 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5498 #define CAN_F8R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5499 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5500 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5501 #define CAN_F8R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5502 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5503 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5504 #define CAN_F8R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5505 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5506 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5507 #define CAN_F8R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5508 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5509 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5510 #define CAN_F8R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5511 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5512 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5513 #define CAN_F8R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5514 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5515 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5516 #define CAN_F8R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5517 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5518 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5519 #define CAN_F8R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5520 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5521 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5522 #define CAN_F8R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5523 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5524 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5525 #define CAN_F8R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5526 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5527 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5528 #define CAN_F8R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5529 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5530 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5531 #define CAN_F8R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5532 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5533 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5534 #define CAN_F8R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5535 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5536 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5537 #define CAN_F8R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5538 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5539 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5540 #define CAN_F8R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5541 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5542 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5543 #define CAN_F8R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5544 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5545 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5546 #define CAN_F8R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5547 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5548 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5549 #define CAN_F8R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5550 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5551 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5552
bogdanm 86:04dd9b1680ae 5553 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 5554 #define CAN_F9R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5555 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5556 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5557 #define CAN_F9R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5558 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5559 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5560 #define CAN_F9R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5561 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5562 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5563 #define CAN_F9R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5564 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5565 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5566 #define CAN_F9R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5567 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5568 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5569 #define CAN_F9R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5570 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5571 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5572 #define CAN_F9R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5573 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5574 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5575 #define CAN_F9R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5576 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5577 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5578 #define CAN_F9R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5579 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5580 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5581 #define CAN_F9R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5582 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5583 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5584 #define CAN_F9R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5585 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5586 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5587 #define CAN_F9R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5588 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5589 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5590 #define CAN_F9R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5591 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5592 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5593 #define CAN_F9R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5594 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5595 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5596 #define CAN_F9R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5597 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5598 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5599 #define CAN_F9R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5600 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5601 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5602 #define CAN_F9R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5603 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5604 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5605 #define CAN_F9R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5606 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5607 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5608 #define CAN_F9R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5609 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5610 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5611 #define CAN_F9R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5612 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5613 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5614 #define CAN_F9R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5615 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5616 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5617 #define CAN_F9R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5618 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5619 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5620 #define CAN_F9R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5621 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5622 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5623 #define CAN_F9R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5624 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5625 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5626 #define CAN_F9R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5627 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5628 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5629 #define CAN_F9R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5630 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5631 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5632 #define CAN_F9R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5633 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5634 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5635 #define CAN_F9R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5636 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5637 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5638 #define CAN_F9R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5639 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5640 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5641 #define CAN_F9R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5642 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5643 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5644 #define CAN_F9R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5645 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5646 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5647 #define CAN_F9R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5648 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5649 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5650
bogdanm 86:04dd9b1680ae 5651 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 5652 #define CAN_F10R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5653 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5654 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5655 #define CAN_F10R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5656 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5657 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5658 #define CAN_F10R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5659 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5660 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5661 #define CAN_F10R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5662 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5663 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5664 #define CAN_F10R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5665 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5666 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5667 #define CAN_F10R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5668 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5669 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5670 #define CAN_F10R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5671 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5672 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5673 #define CAN_F10R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5674 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5675 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5676 #define CAN_F10R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5677 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5678 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5679 #define CAN_F10R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5680 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5681 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5682 #define CAN_F10R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5683 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5684 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5685 #define CAN_F10R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5686 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5687 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5688 #define CAN_F10R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5689 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5690 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5691 #define CAN_F10R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5692 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5693 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5694 #define CAN_F10R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5695 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5696 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5697 #define CAN_F10R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5698 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5699 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5700 #define CAN_F10R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5701 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5702 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5703 #define CAN_F10R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5704 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5705 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5706 #define CAN_F10R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5707 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5708 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5709 #define CAN_F10R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5710 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5711 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5712 #define CAN_F10R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5713 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5714 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5715 #define CAN_F10R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5716 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5717 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5718 #define CAN_F10R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5719 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5720 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5721 #define CAN_F10R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5722 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5723 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5724 #define CAN_F10R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5725 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5726 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5727 #define CAN_F10R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5728 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5729 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5730 #define CAN_F10R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5731 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5732 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5733 #define CAN_F10R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5734 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5735 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5736 #define CAN_F10R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5737 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5738 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5739 #define CAN_F10R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5740 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5741 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5742 #define CAN_F10R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5743 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5744 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5745 #define CAN_F10R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5746 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5747 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5748
bogdanm 86:04dd9b1680ae 5749 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 5750 #define CAN_F11R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5751 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5752 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5753 #define CAN_F11R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5754 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5755 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5756 #define CAN_F11R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5757 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5758 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5759 #define CAN_F11R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5760 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5761 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5762 #define CAN_F11R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5763 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5764 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5765 #define CAN_F11R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5766 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5767 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5768 #define CAN_F11R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5769 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5770 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5771 #define CAN_F11R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5772 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5773 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5774 #define CAN_F11R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5775 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5776 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5777 #define CAN_F11R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5778 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5779 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5780 #define CAN_F11R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5781 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5782 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5783 #define CAN_F11R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5784 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5785 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5786 #define CAN_F11R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5787 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5788 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5789 #define CAN_F11R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5790 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5791 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5792 #define CAN_F11R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5793 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5794 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5795 #define CAN_F11R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5796 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5797 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5798 #define CAN_F11R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5799 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5800 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5801 #define CAN_F11R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5802 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5803 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5804 #define CAN_F11R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5805 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5806 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5807 #define CAN_F11R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5808 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5809 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5810 #define CAN_F11R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5811 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5812 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5813 #define CAN_F11R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5814 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5815 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5816 #define CAN_F11R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5817 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5818 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5819 #define CAN_F11R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5820 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5821 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5822 #define CAN_F11R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5823 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5824 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5825 #define CAN_F11R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5826 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5827 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5828 #define CAN_F11R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5829 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5830 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5831 #define CAN_F11R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5832 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5833 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5834 #define CAN_F11R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5835 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5836 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5837 #define CAN_F11R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5838 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5839 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5840 #define CAN_F11R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5841 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5842 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5843 #define CAN_F11R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5844 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5845 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5846
bogdanm 86:04dd9b1680ae 5847 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 5848 #define CAN_F12R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5849 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5850 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5851 #define CAN_F12R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5852 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5853 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5854 #define CAN_F12R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5855 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5856 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5857 #define CAN_F12R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5858 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5859 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5860 #define CAN_F12R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5861 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5862 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5863 #define CAN_F12R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5864 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5865 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5866 #define CAN_F12R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5867 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5868 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5869 #define CAN_F12R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5870 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5871 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5872 #define CAN_F12R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5873 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5874 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5875 #define CAN_F12R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5876 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5877 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5878 #define CAN_F12R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5879 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5880 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5881 #define CAN_F12R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5882 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5883 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5884 #define CAN_F12R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5885 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5886 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5887 #define CAN_F12R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5888 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5889 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5890 #define CAN_F12R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5891 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5892 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5893 #define CAN_F12R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5894 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5895 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5896 #define CAN_F12R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5897 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5898 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5899 #define CAN_F12R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5900 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5901 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5902 #define CAN_F12R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5903 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5904 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5905 #define CAN_F12R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5906 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5907 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5908 #define CAN_F12R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5909 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5910 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5911 #define CAN_F12R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5912 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5913 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5914 #define CAN_F12R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5915 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5916 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5917 #define CAN_F12R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5918 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5919 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5920 #define CAN_F12R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5921 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5922 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5923 #define CAN_F12R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5924 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5925 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5926 #define CAN_F12R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5927 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5928 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5929 #define CAN_F12R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5930 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5931 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5932 #define CAN_F12R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5933 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5934 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5935 #define CAN_F12R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5936 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5937 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5938 #define CAN_F12R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5939 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5940 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5941 #define CAN_F12R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5942 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5943 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 5944
bogdanm 86:04dd9b1680ae 5945 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 5946 #define CAN_F13R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5947 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5948 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5949 #define CAN_F13R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5950 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5951 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5952 #define CAN_F13R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5953 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5954 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5955 #define CAN_F13R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5956 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5957 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5958 #define CAN_F13R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5959 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5960 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5961 #define CAN_F13R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5962 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5963 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5964 #define CAN_F13R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5965 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5966 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5967 #define CAN_F13R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5968 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5969 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5970 #define CAN_F13R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5971 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5972 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5973 #define CAN_F13R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5974 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5975 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5976 #define CAN_F13R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5977 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5978 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5979 #define CAN_F13R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5980 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5981 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5982 #define CAN_F13R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5983 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5984 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5985 #define CAN_F13R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5986 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5987 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5988 #define CAN_F13R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5989 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5990 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5991 #define CAN_F13R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5992 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5993 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5994 #define CAN_F13R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5995 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5996 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5997 #define CAN_F13R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5998 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5999 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 6000 #define CAN_F13R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 6001 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6002 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 6003 #define CAN_F13R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 6004 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6005 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 6006 #define CAN_F13R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 6007 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6008 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 6009 #define CAN_F13R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 6010 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6011 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 6012 #define CAN_F13R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 6013 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6014 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 6015 #define CAN_F13R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 6016 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6017 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 6018 #define CAN_F13R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 6019 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6020 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 6021 #define CAN_F13R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 6022 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6023 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 6024 #define CAN_F13R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 6025 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6026 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 6027 #define CAN_F13R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 6028 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6029 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 6030 #define CAN_F13R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 6031 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6032 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 6033 #define CAN_F13R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 6034 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6035 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 6036 #define CAN_F13R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 6037 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6038 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 6039 #define CAN_F13R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 6040 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6041 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
bogdanm 86:04dd9b1680ae 6042
bogdanm 86:04dd9b1680ae 6043 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6044 /* */
bogdanm 86:04dd9b1680ae 6045 /* CRC calculation unit (CRC) */
bogdanm 86:04dd9b1680ae 6046 /* */
bogdanm 86:04dd9b1680ae 6047 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6048 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 6049 #define CRC_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 6050 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6051 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
bogdanm 86:04dd9b1680ae 6052
bogdanm 86:04dd9b1680ae 6053 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 6054 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
bogdanm 86:04dd9b1680ae 6055
bogdanm 86:04dd9b1680ae 6056 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 6057 #define CRC_CR_RESET_Pos (0U)
Kojto 122:f9eeca106725 6058 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6059 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
Kojto 122:f9eeca106725 6060 #define CRC_CR_POLYSIZE_Pos (3U)
Kojto 122:f9eeca106725 6061 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 6062 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
Kojto 122:f9eeca106725 6063 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6064 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6065 #define CRC_CR_REV_IN_Pos (5U)
Kojto 122:f9eeca106725 6066 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 6067 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
Kojto 122:f9eeca106725 6068 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6069 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6070 #define CRC_CR_REV_OUT_Pos (7U)
Kojto 122:f9eeca106725 6071 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6072 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
bogdanm 86:04dd9b1680ae 6073
bogdanm 86:04dd9b1680ae 6074 /******************* Bit definition for CRC_INIT register *******************/
Kojto 122:f9eeca106725 6075 #define CRC_INIT_INIT_Pos (0U)
Kojto 122:f9eeca106725 6076 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6077 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
bogdanm 86:04dd9b1680ae 6078
bogdanm 86:04dd9b1680ae 6079 /******************* Bit definition for CRC_POL register ********************/
Kojto 122:f9eeca106725 6080 #define CRC_POL_POL_Pos (0U)
Kojto 122:f9eeca106725 6081 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6082 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
bogdanm 86:04dd9b1680ae 6083
bogdanm 86:04dd9b1680ae 6084 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6085 /* */
bogdanm 86:04dd9b1680ae 6086 /* Digital to Analog Converter (DAC) */
bogdanm 86:04dd9b1680ae 6087 /* */
bogdanm 86:04dd9b1680ae 6088 /******************************************************************************/
Kojto 122:f9eeca106725 6089
Kojto 122:f9eeca106725 6090 /*
Kojto 122:f9eeca106725 6091 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 6092 */
Kojto 122:f9eeca106725 6093 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
Kojto 122:f9eeca106725 6094
Kojto 122:f9eeca106725 6095
bogdanm 86:04dd9b1680ae 6096 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 6097 #define DAC_CR_EN1_Pos (0U)
Kojto 122:f9eeca106725 6098 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6099 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
Kojto 122:f9eeca106725 6100 #define DAC_CR_BOFF1_Pos (1U)
Kojto 122:f9eeca106725 6101 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6102 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 6103 #define DAC_CR_OUTEN1_Pos (1U)
Kojto 122:f9eeca106725 6104 #define DAC_CR_OUTEN1_Msk (0x1U << DAC_CR_OUTEN1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6105 #define DAC_CR_OUTEN1 DAC_CR_OUTEN1_Msk /*!< DAC channel1 output switch enable (only for DAC instance: DAC2) */
Kojto 122:f9eeca106725 6106 #define DAC_CR_TEN1_Pos (2U)
Kojto 122:f9eeca106725 6107 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6108 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 6109
Kojto 122:f9eeca106725 6110 #define DAC_CR_TSEL1_Pos (3U)
Kojto 122:f9eeca106725 6111 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 6112 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 6113 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6114 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6115 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6116
Kojto 122:f9eeca106725 6117 #define DAC_CR_WAVE1_Pos (6U)
Kojto 122:f9eeca106725 6118 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 6119 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 6120 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6121 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6122
Kojto 122:f9eeca106725 6123 #define DAC_CR_MAMP1_Pos (8U)
Kojto 122:f9eeca106725 6124 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 6125 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 6126 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6127 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6128 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6129 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6130
Kojto 122:f9eeca106725 6131 #define DAC_CR_DMAEN1_Pos (12U)
Kojto 122:f9eeca106725 6132 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6133 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
Kojto 122:f9eeca106725 6134 #define DAC_CR_DMAUDRIE1_Pos (13U)
Kojto 122:f9eeca106725 6135 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6136 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */
Kojto 122:f9eeca106725 6137 #define DAC_CR_EN2_Pos (16U)
Kojto 122:f9eeca106725 6138 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6139 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
Kojto 122:f9eeca106725 6140 #define DAC_CR_BOFF2_Pos (17U)
Kojto 122:f9eeca106725 6141 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6142 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 6143 #define DAC_CR_OUTEN2_Pos (17U)
Kojto 122:f9eeca106725 6144 #define DAC_CR_OUTEN2_Msk (0x1U << DAC_CR_OUTEN2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6145 #define DAC_CR_OUTEN2 DAC_CR_OUTEN2_Msk /*!< DAC channel2 output switch enable (only for DAC instance: DAC2) */
Kojto 122:f9eeca106725 6146 #define DAC_CR_TEN2_Pos (18U)
Kojto 122:f9eeca106725 6147 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6148 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 6149
Kojto 122:f9eeca106725 6150 #define DAC_CR_TSEL2_Pos (19U)
Kojto 122:f9eeca106725 6151 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
Kojto 122:f9eeca106725 6152 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 6153 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6154 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6155 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6156
Kojto 122:f9eeca106725 6157 #define DAC_CR_WAVE2_Pos (22U)
Kojto 122:f9eeca106725 6158 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 6159 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 6160 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6161 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6162
Kojto 122:f9eeca106725 6163 #define DAC_CR_MAMP2_Pos (24U)
Kojto 122:f9eeca106725 6164 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 6165 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 6166 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6167 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6168 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6169 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6170
Kojto 122:f9eeca106725 6171 #define DAC_CR_DMAEN2_Pos (28U)
Kojto 122:f9eeca106725 6172 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6173 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 6174 #define DAC_CR_DMAUDRIE2_Pos (29U)
Kojto 122:f9eeca106725 6175 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6176 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */
bogdanm 86:04dd9b1680ae 6177
bogdanm 86:04dd9b1680ae 6178 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 6179 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
Kojto 122:f9eeca106725 6180 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6181 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
Kojto 122:f9eeca106725 6182 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
Kojto 122:f9eeca106725 6183 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6184 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
bogdanm 86:04dd9b1680ae 6185
bogdanm 86:04dd9b1680ae 6186 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 6187 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 6188 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6189 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6190
bogdanm 86:04dd9b1680ae 6191 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 6192 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 6193 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 6194 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
bogdanm 86:04dd9b1680ae 6195
bogdanm 86:04dd9b1680ae 6196 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 6197 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 6198 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6199 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6200
bogdanm 86:04dd9b1680ae 6201 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 6202 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 6203 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6204 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6205
bogdanm 86:04dd9b1680ae 6206 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 6207 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
Kojto 122:f9eeca106725 6208 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 6209 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
bogdanm 86:04dd9b1680ae 6210
bogdanm 86:04dd9b1680ae 6211 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 6212 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 6213 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6214 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6215
bogdanm 86:04dd9b1680ae 6216 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 6217 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 6218 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6219 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 6220 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
Kojto 122:f9eeca106725 6221 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 6222 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6223
bogdanm 86:04dd9b1680ae 6224 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 6225 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 6226 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 6227 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 6228 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
Kojto 122:f9eeca106725 6229 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
Kojto 122:f9eeca106725 6230 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
bogdanm 86:04dd9b1680ae 6231
bogdanm 86:04dd9b1680ae 6232 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 6233 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 6234 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6235 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 6236 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
Kojto 122:f9eeca106725 6237 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 6238 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
bogdanm 86:04dd9b1680ae 6239
bogdanm 86:04dd9b1680ae 6240 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 6241 #define DAC_DOR1_DACC1DOR_Pos (0U)
Kojto 122:f9eeca106725 6242 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6243 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
bogdanm 86:04dd9b1680ae 6244
bogdanm 86:04dd9b1680ae 6245 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 6246 #define DAC_DOR2_DACC2DOR_Pos (0U)
Kojto 122:f9eeca106725 6247 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6248 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
bogdanm 86:04dd9b1680ae 6249
bogdanm 86:04dd9b1680ae 6250 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 6251 #define DAC_SR_DMAUDR1_Pos (13U)
Kojto 122:f9eeca106725 6252 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6253 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 6254 #define DAC_SR_DMAUDR2_Pos (29U)
Kojto 122:f9eeca106725 6255 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6256 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
bogdanm 86:04dd9b1680ae 6257
bogdanm 86:04dd9b1680ae 6258 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6259 /* */
bogdanm 86:04dd9b1680ae 6260 /* Debug MCU (DBGMCU) */
bogdanm 86:04dd9b1680ae 6261 /* */
bogdanm 86:04dd9b1680ae 6262 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6263 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 6264 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
Kojto 122:f9eeca106725 6265 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 6266 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
Kojto 122:f9eeca106725 6267 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
Kojto 122:f9eeca106725 6268 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 6269 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
bogdanm 86:04dd9b1680ae 6270
bogdanm 86:04dd9b1680ae 6271 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 6272 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
Kojto 122:f9eeca106725 6273 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6274 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
Kojto 122:f9eeca106725 6275 #define DBGMCU_CR_DBG_STOP_Pos (1U)
Kojto 122:f9eeca106725 6276 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6277 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
Kojto 122:f9eeca106725 6278 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
Kojto 122:f9eeca106725 6279 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6280 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
Kojto 122:f9eeca106725 6281 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
Kojto 122:f9eeca106725 6282 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6283 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
Kojto 122:f9eeca106725 6284
Kojto 122:f9eeca106725 6285 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
Kojto 122:f9eeca106725 6286 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 6287 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
Kojto 122:f9eeca106725 6288 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6289 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
bogdanm 86:04dd9b1680ae 6290
bogdanm 86:04dd9b1680ae 6291 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 122:f9eeca106725 6292 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
Kojto 122:f9eeca106725 6293 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6294 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
Kojto 122:f9eeca106725 6295 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
Kojto 122:f9eeca106725 6296 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6297 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
Kojto 122:f9eeca106725 6298 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
Kojto 122:f9eeca106725 6299 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6300 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
Kojto 122:f9eeca106725 6301 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
Kojto 122:f9eeca106725 6302 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6303 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
Kojto 122:f9eeca106725 6304 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
Kojto 122:f9eeca106725 6305 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6306 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
Kojto 122:f9eeca106725 6307 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
Kojto 122:f9eeca106725 6308 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6309 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
Kojto 122:f9eeca106725 6310 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
Kojto 122:f9eeca106725 6311 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6312 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
Kojto 122:f9eeca106725 6313 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
Kojto 122:f9eeca106725 6314 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6315 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
Kojto 122:f9eeca106725 6316 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
Kojto 122:f9eeca106725 6317 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6318 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
bogdanm 86:04dd9b1680ae 6319
bogdanm 86:04dd9b1680ae 6320 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 122:f9eeca106725 6321 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
Kojto 122:f9eeca106725 6322 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6323 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
Kojto 122:f9eeca106725 6324 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)
Kojto 122:f9eeca106725 6325 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6326 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
Kojto 122:f9eeca106725 6327 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)
Kojto 122:f9eeca106725 6328 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6329 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
Kojto 122:f9eeca106725 6330 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)
Kojto 122:f9eeca106725 6331 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6332 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
Kojto 122:f9eeca106725 6333 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos (8U)
Kojto 122:f9eeca106725 6334 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6335 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk
bogdanm 86:04dd9b1680ae 6336
bogdanm 86:04dd9b1680ae 6337 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6338 /* */
bogdanm 86:04dd9b1680ae 6339 /* DMA Controller (DMA) */
bogdanm 86:04dd9b1680ae 6340 /* */
bogdanm 86:04dd9b1680ae 6341 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6342 /******************* Bit definition for DMA_ISR register ********************/
Kojto 122:f9eeca106725 6343 #define DMA_ISR_GIF1_Pos (0U)
Kojto 122:f9eeca106725 6344 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6345 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
Kojto 122:f9eeca106725 6346 #define DMA_ISR_TCIF1_Pos (1U)
Kojto 122:f9eeca106725 6347 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6348 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
Kojto 122:f9eeca106725 6349 #define DMA_ISR_HTIF1_Pos (2U)
Kojto 122:f9eeca106725 6350 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6351 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
Kojto 122:f9eeca106725 6352 #define DMA_ISR_TEIF1_Pos (3U)
Kojto 122:f9eeca106725 6353 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6354 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
Kojto 122:f9eeca106725 6355 #define DMA_ISR_GIF2_Pos (4U)
Kojto 122:f9eeca106725 6356 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6357 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
Kojto 122:f9eeca106725 6358 #define DMA_ISR_TCIF2_Pos (5U)
Kojto 122:f9eeca106725 6359 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6360 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
Kojto 122:f9eeca106725 6361 #define DMA_ISR_HTIF2_Pos (6U)
Kojto 122:f9eeca106725 6362 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6363 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
Kojto 122:f9eeca106725 6364 #define DMA_ISR_TEIF2_Pos (7U)
Kojto 122:f9eeca106725 6365 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6366 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
Kojto 122:f9eeca106725 6367 #define DMA_ISR_GIF3_Pos (8U)
Kojto 122:f9eeca106725 6368 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6369 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
Kojto 122:f9eeca106725 6370 #define DMA_ISR_TCIF3_Pos (9U)
Kojto 122:f9eeca106725 6371 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6372 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
Kojto 122:f9eeca106725 6373 #define DMA_ISR_HTIF3_Pos (10U)
Kojto 122:f9eeca106725 6374 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6375 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
Kojto 122:f9eeca106725 6376 #define DMA_ISR_TEIF3_Pos (11U)
Kojto 122:f9eeca106725 6377 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6378 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
Kojto 122:f9eeca106725 6379 #define DMA_ISR_GIF4_Pos (12U)
Kojto 122:f9eeca106725 6380 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6381 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
Kojto 122:f9eeca106725 6382 #define DMA_ISR_TCIF4_Pos (13U)
Kojto 122:f9eeca106725 6383 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6384 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
Kojto 122:f9eeca106725 6385 #define DMA_ISR_HTIF4_Pos (14U)
Kojto 122:f9eeca106725 6386 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6387 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
Kojto 122:f9eeca106725 6388 #define DMA_ISR_TEIF4_Pos (15U)
Kojto 122:f9eeca106725 6389 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6390 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
Kojto 122:f9eeca106725 6391 #define DMA_ISR_GIF5_Pos (16U)
Kojto 122:f9eeca106725 6392 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6393 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
Kojto 122:f9eeca106725 6394 #define DMA_ISR_TCIF5_Pos (17U)
Kojto 122:f9eeca106725 6395 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6396 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
Kojto 122:f9eeca106725 6397 #define DMA_ISR_HTIF5_Pos (18U)
Kojto 122:f9eeca106725 6398 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6399 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
Kojto 122:f9eeca106725 6400 #define DMA_ISR_TEIF5_Pos (19U)
Kojto 122:f9eeca106725 6401 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6402 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
Kojto 122:f9eeca106725 6403 #define DMA_ISR_GIF6_Pos (20U)
Kojto 122:f9eeca106725 6404 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6405 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
Kojto 122:f9eeca106725 6406 #define DMA_ISR_TCIF6_Pos (21U)
Kojto 122:f9eeca106725 6407 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6408 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
Kojto 122:f9eeca106725 6409 #define DMA_ISR_HTIF6_Pos (22U)
Kojto 122:f9eeca106725 6410 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6411 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
Kojto 122:f9eeca106725 6412 #define DMA_ISR_TEIF6_Pos (23U)
Kojto 122:f9eeca106725 6413 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6414 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
Kojto 122:f9eeca106725 6415 #define DMA_ISR_GIF7_Pos (24U)
Kojto 122:f9eeca106725 6416 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6417 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
Kojto 122:f9eeca106725 6418 #define DMA_ISR_TCIF7_Pos (25U)
Kojto 122:f9eeca106725 6419 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6420 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
Kojto 122:f9eeca106725 6421 #define DMA_ISR_HTIF7_Pos (26U)
Kojto 122:f9eeca106725 6422 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6423 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
Kojto 122:f9eeca106725 6424 #define DMA_ISR_TEIF7_Pos (27U)
Kojto 122:f9eeca106725 6425 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6426 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
bogdanm 86:04dd9b1680ae 6427
bogdanm 86:04dd9b1680ae 6428 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 122:f9eeca106725 6429 #define DMA_IFCR_CGIF1_Pos (0U)
Kojto 122:f9eeca106725 6430 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6431 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
Kojto 122:f9eeca106725 6432 #define DMA_IFCR_CTCIF1_Pos (1U)
Kojto 122:f9eeca106725 6433 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6434 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
Kojto 122:f9eeca106725 6435 #define DMA_IFCR_CHTIF1_Pos (2U)
Kojto 122:f9eeca106725 6436 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6437 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
Kojto 122:f9eeca106725 6438 #define DMA_IFCR_CTEIF1_Pos (3U)
Kojto 122:f9eeca106725 6439 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6440 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
Kojto 122:f9eeca106725 6441 #define DMA_IFCR_CGIF2_Pos (4U)
Kojto 122:f9eeca106725 6442 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6443 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
Kojto 122:f9eeca106725 6444 #define DMA_IFCR_CTCIF2_Pos (5U)
Kojto 122:f9eeca106725 6445 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6446 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
Kojto 122:f9eeca106725 6447 #define DMA_IFCR_CHTIF2_Pos (6U)
Kojto 122:f9eeca106725 6448 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6449 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
Kojto 122:f9eeca106725 6450 #define DMA_IFCR_CTEIF2_Pos (7U)
Kojto 122:f9eeca106725 6451 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6452 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
Kojto 122:f9eeca106725 6453 #define DMA_IFCR_CGIF3_Pos (8U)
Kojto 122:f9eeca106725 6454 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6455 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
Kojto 122:f9eeca106725 6456 #define DMA_IFCR_CTCIF3_Pos (9U)
Kojto 122:f9eeca106725 6457 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6458 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
Kojto 122:f9eeca106725 6459 #define DMA_IFCR_CHTIF3_Pos (10U)
Kojto 122:f9eeca106725 6460 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6461 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
Kojto 122:f9eeca106725 6462 #define DMA_IFCR_CTEIF3_Pos (11U)
Kojto 122:f9eeca106725 6463 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6464 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
Kojto 122:f9eeca106725 6465 #define DMA_IFCR_CGIF4_Pos (12U)
Kojto 122:f9eeca106725 6466 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6467 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
Kojto 122:f9eeca106725 6468 #define DMA_IFCR_CTCIF4_Pos (13U)
Kojto 122:f9eeca106725 6469 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6470 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
Kojto 122:f9eeca106725 6471 #define DMA_IFCR_CHTIF4_Pos (14U)
Kojto 122:f9eeca106725 6472 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6473 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
Kojto 122:f9eeca106725 6474 #define DMA_IFCR_CTEIF4_Pos (15U)
Kojto 122:f9eeca106725 6475 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6476 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
Kojto 122:f9eeca106725 6477 #define DMA_IFCR_CGIF5_Pos (16U)
Kojto 122:f9eeca106725 6478 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6479 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
Kojto 122:f9eeca106725 6480 #define DMA_IFCR_CTCIF5_Pos (17U)
Kojto 122:f9eeca106725 6481 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6482 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
Kojto 122:f9eeca106725 6483 #define DMA_IFCR_CHTIF5_Pos (18U)
Kojto 122:f9eeca106725 6484 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6485 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
Kojto 122:f9eeca106725 6486 #define DMA_IFCR_CTEIF5_Pos (19U)
Kojto 122:f9eeca106725 6487 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6488 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
Kojto 122:f9eeca106725 6489 #define DMA_IFCR_CGIF6_Pos (20U)
Kojto 122:f9eeca106725 6490 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6491 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
Kojto 122:f9eeca106725 6492 #define DMA_IFCR_CTCIF6_Pos (21U)
Kojto 122:f9eeca106725 6493 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6494 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
Kojto 122:f9eeca106725 6495 #define DMA_IFCR_CHTIF6_Pos (22U)
Kojto 122:f9eeca106725 6496 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6497 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
Kojto 122:f9eeca106725 6498 #define DMA_IFCR_CTEIF6_Pos (23U)
Kojto 122:f9eeca106725 6499 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6500 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
Kojto 122:f9eeca106725 6501 #define DMA_IFCR_CGIF7_Pos (24U)
Kojto 122:f9eeca106725 6502 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6503 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
Kojto 122:f9eeca106725 6504 #define DMA_IFCR_CTCIF7_Pos (25U)
Kojto 122:f9eeca106725 6505 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6506 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
Kojto 122:f9eeca106725 6507 #define DMA_IFCR_CHTIF7_Pos (26U)
Kojto 122:f9eeca106725 6508 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6509 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
Kojto 122:f9eeca106725 6510 #define DMA_IFCR_CTEIF7_Pos (27U)
Kojto 122:f9eeca106725 6511 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6512 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
bogdanm 86:04dd9b1680ae 6513
bogdanm 86:04dd9b1680ae 6514 /******************* Bit definition for DMA_CCR register ********************/
Kojto 122:f9eeca106725 6515 #define DMA_CCR_EN_Pos (0U)
Kojto 122:f9eeca106725 6516 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6517 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
Kojto 122:f9eeca106725 6518 #define DMA_CCR_TCIE_Pos (1U)
Kojto 122:f9eeca106725 6519 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6520 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 6521 #define DMA_CCR_HTIE_Pos (2U)
Kojto 122:f9eeca106725 6522 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6523 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
Kojto 122:f9eeca106725 6524 #define DMA_CCR_TEIE_Pos (3U)
Kojto 122:f9eeca106725 6525 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6526 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
Kojto 122:f9eeca106725 6527 #define DMA_CCR_DIR_Pos (4U)
Kojto 122:f9eeca106725 6528 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6529 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
Kojto 122:f9eeca106725 6530 #define DMA_CCR_CIRC_Pos (5U)
Kojto 122:f9eeca106725 6531 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6532 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
Kojto 122:f9eeca106725 6533 #define DMA_CCR_PINC_Pos (6U)
Kojto 122:f9eeca106725 6534 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6535 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
Kojto 122:f9eeca106725 6536 #define DMA_CCR_MINC_Pos (7U)
Kojto 122:f9eeca106725 6537 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6538 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
Kojto 122:f9eeca106725 6539
Kojto 122:f9eeca106725 6540 #define DMA_CCR_PSIZE_Pos (8U)
Kojto 122:f9eeca106725 6541 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 6542 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 122:f9eeca106725 6543 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6544 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6545
Kojto 122:f9eeca106725 6546 #define DMA_CCR_MSIZE_Pos (10U)
Kojto 122:f9eeca106725 6547 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 6548 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
Kojto 122:f9eeca106725 6549 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6550 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6551
Kojto 122:f9eeca106725 6552 #define DMA_CCR_PL_Pos (12U)
Kojto 122:f9eeca106725 6553 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 6554 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 122:f9eeca106725 6555 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6556 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6557
Kojto 122:f9eeca106725 6558 #define DMA_CCR_MEM2MEM_Pos (14U)
Kojto 122:f9eeca106725 6559 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6560 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
bogdanm 86:04dd9b1680ae 6561
bogdanm 86:04dd9b1680ae 6562 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 122:f9eeca106725 6563 #define DMA_CNDTR_NDT_Pos (0U)
Kojto 122:f9eeca106725 6564 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 6565 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
bogdanm 86:04dd9b1680ae 6566
bogdanm 86:04dd9b1680ae 6567 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 122:f9eeca106725 6568 #define DMA_CPAR_PA_Pos (0U)
Kojto 122:f9eeca106725 6569 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6570 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
bogdanm 86:04dd9b1680ae 6571
bogdanm 86:04dd9b1680ae 6572 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 122:f9eeca106725 6573 #define DMA_CMAR_MA_Pos (0U)
Kojto 122:f9eeca106725 6574 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6575 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
bogdanm 86:04dd9b1680ae 6576
bogdanm 86:04dd9b1680ae 6577 /******************************************************************************/
bogdanm 86:04dd9b1680ae 6578 /* */
bogdanm 86:04dd9b1680ae 6579 /* External Interrupt/Event Controller (EXTI) */
bogdanm 86:04dd9b1680ae 6580 /* */
bogdanm 86:04dd9b1680ae 6581 /******************************************************************************/
Kojto 122:f9eeca106725 6582 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 6583 #define EXTI_IMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 6584 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6585 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 6586 #define EXTI_IMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 6587 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6588 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 6589 #define EXTI_IMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 6590 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6591 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 6592 #define EXTI_IMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 6593 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6594 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 6595 #define EXTI_IMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 6596 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6597 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 6598 #define EXTI_IMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 6599 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6600 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 6601 #define EXTI_IMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 6602 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6603 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 6604 #define EXTI_IMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 6605 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6606 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 6607 #define EXTI_IMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 6608 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6609 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 6610 #define EXTI_IMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 6611 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6612 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 6613 #define EXTI_IMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 6614 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6615 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 6616 #define EXTI_IMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 6617 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6618 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 6619 #define EXTI_IMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 6620 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6621 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 6622 #define EXTI_IMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 6623 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6624 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 6625 #define EXTI_IMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 6626 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6627 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 6628 #define EXTI_IMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 6629 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6630 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 6631 #define EXTI_IMR_MR16_Pos (16U)
Kojto 122:f9eeca106725 6632 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6633 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 6634 #define EXTI_IMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 6635 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6636 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 6637 #define EXTI_IMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 6638 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6639 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 6640 #define EXTI_IMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 6641 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6642 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 6643 #define EXTI_IMR_MR20_Pos (20U)
Kojto 122:f9eeca106725 6644 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6645 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 6646 #define EXTI_IMR_MR21_Pos (21U)
Kojto 122:f9eeca106725 6647 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6648 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 6649 #define EXTI_IMR_MR22_Pos (22U)
Kojto 122:f9eeca106725 6650 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6651 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
Kojto 122:f9eeca106725 6652 #define EXTI_IMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 6653 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6654 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 6655 #define EXTI_IMR_MR24_Pos (24U)
Kojto 122:f9eeca106725 6656 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6657 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
Kojto 122:f9eeca106725 6658 #define EXTI_IMR_MR25_Pos (25U)
Kojto 122:f9eeca106725 6659 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6660 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
Kojto 122:f9eeca106725 6661 #define EXTI_IMR_MR26_Pos (26U)
Kojto 122:f9eeca106725 6662 #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6663 #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
Kojto 122:f9eeca106725 6664 #define EXTI_IMR_MR27_Pos (27U)
Kojto 122:f9eeca106725 6665 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6666 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
Kojto 122:f9eeca106725 6667 #define EXTI_IMR_MR28_Pos (28U)
Kojto 122:f9eeca106725 6668 #define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6669 #define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
Kojto 122:f9eeca106725 6670 #define EXTI_IMR_MR29_Pos (29U)
Kojto 122:f9eeca106725 6671 #define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6672 #define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
Kojto 122:f9eeca106725 6673 #define EXTI_IMR_MR30_Pos (30U)
Kojto 122:f9eeca106725 6674 #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6675 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
Kojto 122:f9eeca106725 6676 #define EXTI_IMR_MR31_Pos (31U)
Kojto 122:f9eeca106725 6677 #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6678 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
Kojto 122:f9eeca106725 6679
Kojto 122:f9eeca106725 6680 /* References Defines */
Kojto 122:f9eeca106725 6681 #define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto 122:f9eeca106725 6682 #define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto 122:f9eeca106725 6683 #define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto 122:f9eeca106725 6684 #define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto 122:f9eeca106725 6685 #define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto 122:f9eeca106725 6686 #define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto 122:f9eeca106725 6687 #define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto 122:f9eeca106725 6688 #define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto 122:f9eeca106725 6689 #define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto 122:f9eeca106725 6690 #define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto 122:f9eeca106725 6691 #define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto 122:f9eeca106725 6692 #define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto 122:f9eeca106725 6693 #define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto 122:f9eeca106725 6694 #define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto 122:f9eeca106725 6695 #define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto 122:f9eeca106725 6696 #define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto 122:f9eeca106725 6697 #define EXTI_IMR_IM16 EXTI_IMR_MR16
Kojto 122:f9eeca106725 6698 #define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto 122:f9eeca106725 6699 #define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto 122:f9eeca106725 6700 #define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto 122:f9eeca106725 6701 #define EXTI_IMR_IM20 EXTI_IMR_MR20
Kojto 122:f9eeca106725 6702 #define EXTI_IMR_IM21 EXTI_IMR_MR21
Kojto 122:f9eeca106725 6703 #define EXTI_IMR_IM22 EXTI_IMR_MR22
Kojto 122:f9eeca106725 6704 #define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto 122:f9eeca106725 6705 #define EXTI_IMR_IM24 EXTI_IMR_MR24
Kojto 122:f9eeca106725 6706 #define EXTI_IMR_IM25 EXTI_IMR_MR25
Kojto 122:f9eeca106725 6707 #define EXTI_IMR_IM26 EXTI_IMR_MR26
Kojto 122:f9eeca106725 6708 #define EXTI_IMR_IM27 EXTI_IMR_MR27
Kojto 122:f9eeca106725 6709 #define EXTI_IMR_IM28 EXTI_IMR_MR28
Kojto 122:f9eeca106725 6710 #define EXTI_IMR_IM29 EXTI_IMR_MR29
Kojto 122:f9eeca106725 6711 #define EXTI_IMR_IM30 EXTI_IMR_MR30
Kojto 122:f9eeca106725 6712 #define EXTI_IMR_IM31 EXTI_IMR_MR31
Kojto 122:f9eeca106725 6713
Kojto 122:f9eeca106725 6714 #define EXTI_IMR_IM_Pos (0U)
Kojto 122:f9eeca106725 6715 #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6716 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
Kojto 122:f9eeca106725 6717
Kojto 122:f9eeca106725 6718 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 6719 #define EXTI_EMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 6720 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6721 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 6722 #define EXTI_EMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 6723 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6724 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 6725 #define EXTI_EMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 6726 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6727 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 6728 #define EXTI_EMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 6729 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6730 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 6731 #define EXTI_EMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 6732 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6733 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 6734 #define EXTI_EMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 6735 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6736 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 6737 #define EXTI_EMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 6738 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6739 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 6740 #define EXTI_EMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 6741 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6742 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 6743 #define EXTI_EMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 6744 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6745 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 6746 #define EXTI_EMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 6747 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6748 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 6749 #define EXTI_EMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 6750 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6751 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 6752 #define EXTI_EMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 6753 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6754 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 6755 #define EXTI_EMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 6756 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6757 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 6758 #define EXTI_EMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 6759 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6760 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 6761 #define EXTI_EMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 6762 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6763 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 6764 #define EXTI_EMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 6765 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6766 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 6767 #define EXTI_EMR_MR16_Pos (16U)
Kojto 122:f9eeca106725 6768 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6769 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 6770 #define EXTI_EMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 6771 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6772 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 6773 #define EXTI_EMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 6774 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6775 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 6776 #define EXTI_EMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 6777 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6778 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 6779 #define EXTI_EMR_MR20_Pos (20U)
Kojto 122:f9eeca106725 6780 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6781 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 6782 #define EXTI_EMR_MR21_Pos (21U)
Kojto 122:f9eeca106725 6783 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6784 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 6785 #define EXTI_EMR_MR22_Pos (22U)
Kojto 122:f9eeca106725 6786 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6787 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
Kojto 122:f9eeca106725 6788 #define EXTI_EMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 6789 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6790 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 6791 #define EXTI_EMR_MR24_Pos (24U)
Kojto 122:f9eeca106725 6792 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6793 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
Kojto 122:f9eeca106725 6794 #define EXTI_EMR_MR25_Pos (25U)
Kojto 122:f9eeca106725 6795 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6796 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
Kojto 122:f9eeca106725 6797 #define EXTI_EMR_MR26_Pos (26U)
Kojto 122:f9eeca106725 6798 #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6799 #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
Kojto 122:f9eeca106725 6800 #define EXTI_EMR_MR27_Pos (27U)
Kojto 122:f9eeca106725 6801 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6802 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
Kojto 122:f9eeca106725 6803 #define EXTI_EMR_MR28_Pos (28U)
Kojto 122:f9eeca106725 6804 #define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6805 #define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
Kojto 122:f9eeca106725 6806 #define EXTI_EMR_MR29_Pos (29U)
Kojto 122:f9eeca106725 6807 #define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6808 #define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
Kojto 122:f9eeca106725 6809 #define EXTI_EMR_MR30_Pos (30U)
Kojto 122:f9eeca106725 6810 #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6811 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
Kojto 122:f9eeca106725 6812 #define EXTI_EMR_MR31_Pos (31U)
Kojto 122:f9eeca106725 6813 #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6814 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
Kojto 122:f9eeca106725 6815
Kojto 122:f9eeca106725 6816 /* References Defines */
Kojto 122:f9eeca106725 6817 #define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto 122:f9eeca106725 6818 #define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto 122:f9eeca106725 6819 #define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto 122:f9eeca106725 6820 #define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto 122:f9eeca106725 6821 #define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto 122:f9eeca106725 6822 #define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto 122:f9eeca106725 6823 #define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto 122:f9eeca106725 6824 #define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto 122:f9eeca106725 6825 #define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto 122:f9eeca106725 6826 #define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto 122:f9eeca106725 6827 #define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto 122:f9eeca106725 6828 #define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto 122:f9eeca106725 6829 #define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto 122:f9eeca106725 6830 #define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto 122:f9eeca106725 6831 #define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto 122:f9eeca106725 6832 #define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto 122:f9eeca106725 6833 #define EXTI_EMR_EM16 EXTI_EMR_MR16
Kojto 122:f9eeca106725 6834 #define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto 122:f9eeca106725 6835 #define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto 122:f9eeca106725 6836 #define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto 122:f9eeca106725 6837 #define EXTI_EMR_EM20 EXTI_EMR_MR20
Kojto 122:f9eeca106725 6838 #define EXTI_EMR_EM21 EXTI_EMR_MR21
Kojto 122:f9eeca106725 6839 #define EXTI_EMR_EM22 EXTI_EMR_MR22
Kojto 122:f9eeca106725 6840 #define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto 122:f9eeca106725 6841 #define EXTI_EMR_EM24 EXTI_EMR_MR24
Kojto 122:f9eeca106725 6842 #define EXTI_EMR_EM25 EXTI_EMR_MR25
Kojto 122:f9eeca106725 6843 #define EXTI_EMR_EM26 EXTI_EMR_MR26
Kojto 122:f9eeca106725 6844 #define EXTI_EMR_EM27 EXTI_EMR_MR27
Kojto 122:f9eeca106725 6845 #define EXTI_EMR_EM28 EXTI_EMR_MR28
Kojto 122:f9eeca106725 6846 #define EXTI_EMR_EM29 EXTI_EMR_MR29
Kojto 122:f9eeca106725 6847 #define EXTI_EMR_EM30 EXTI_EMR_MR30
Kojto 122:f9eeca106725 6848 #define EXTI_EMR_EM31 EXTI_EMR_MR31
Kojto 122:f9eeca106725 6849
Kojto 122:f9eeca106725 6850 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 6851 #define EXTI_RTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 6852 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6853 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6854 #define EXTI_RTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 6855 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6856 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6857 #define EXTI_RTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 6858 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6859 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6860 #define EXTI_RTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 6861 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6862 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6863 #define EXTI_RTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 6864 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6865 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6866 #define EXTI_RTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 6867 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6868 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6869 #define EXTI_RTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 6870 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6871 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6872 #define EXTI_RTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 6873 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6874 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6875 #define EXTI_RTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 6876 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6877 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6878 #define EXTI_RTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 6879 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6880 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6881 #define EXTI_RTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 6882 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6883 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6884 #define EXTI_RTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 6885 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6886 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6887 #define EXTI_RTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 6888 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6889 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6890 #define EXTI_RTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 6891 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6892 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 6893 #define EXTI_RTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 6894 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6895 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 6896 #define EXTI_RTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 6897 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6898 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 6899 #define EXTI_RTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 6900 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6901 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 6902 #define EXTI_RTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 6903 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6904 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 6905 #define EXTI_RTSR_TR18_Pos (18U)
Kojto 122:f9eeca106725 6906 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6907 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 6908 #define EXTI_RTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 6909 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6910 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 6911 #define EXTI_RTSR_TR20_Pos (20U)
Kojto 122:f9eeca106725 6912 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6913 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 6914 #define EXTI_RTSR_TR21_Pos (21U)
Kojto 122:f9eeca106725 6915 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6916 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 6917 #define EXTI_RTSR_TR22_Pos (22U)
Kojto 122:f9eeca106725 6918 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6919 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 6920 #define EXTI_RTSR_TR29_Pos (29U)
Kojto 122:f9eeca106725 6921 #define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 6922 #define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
Kojto 122:f9eeca106725 6923 #define EXTI_RTSR_TR30_Pos (30U)
Kojto 122:f9eeca106725 6924 #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6925 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
Kojto 122:f9eeca106725 6926 #define EXTI_RTSR_TR31_Pos (31U)
Kojto 122:f9eeca106725 6927 #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6928 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
Kojto 122:f9eeca106725 6929
Kojto 122:f9eeca106725 6930 /* References Defines */
Kojto 122:f9eeca106725 6931 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
Kojto 122:f9eeca106725 6932 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
Kojto 122:f9eeca106725 6933 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
Kojto 122:f9eeca106725 6934 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
Kojto 122:f9eeca106725 6935 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
Kojto 122:f9eeca106725 6936 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
Kojto 122:f9eeca106725 6937 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
Kojto 122:f9eeca106725 6938 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
Kojto 122:f9eeca106725 6939 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
Kojto 122:f9eeca106725 6940 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
Kojto 122:f9eeca106725 6941 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
Kojto 122:f9eeca106725 6942 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
Kojto 122:f9eeca106725 6943 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
Kojto 122:f9eeca106725 6944 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
Kojto 122:f9eeca106725 6945 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
Kojto 122:f9eeca106725 6946 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
Kojto 122:f9eeca106725 6947 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
Kojto 122:f9eeca106725 6948 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
Kojto 122:f9eeca106725 6949 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
Kojto 122:f9eeca106725 6950 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
Kojto 122:f9eeca106725 6951 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
Kojto 122:f9eeca106725 6952 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
Kojto 122:f9eeca106725 6953 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
Kojto 122:f9eeca106725 6954 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
Kojto 122:f9eeca106725 6955 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
Kojto 122:f9eeca106725 6956 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
Kojto 122:f9eeca106725 6957
Kojto 122:f9eeca106725 6958 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 6959 #define EXTI_FTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 6960 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6961 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6962 #define EXTI_FTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 6963 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6964 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6965 #define EXTI_FTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 6966 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6967 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6968 #define EXTI_FTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 6969 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6970 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6971 #define EXTI_FTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 6972 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6973 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6974 #define EXTI_FTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 6975 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6976 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6977 #define EXTI_FTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 6978 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6979 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6980 #define EXTI_FTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 6981 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6982 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6983 #define EXTI_FTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 6984 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6985 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6986 #define EXTI_FTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 6987 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6988 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6989 #define EXTI_FTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 6990 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6991 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6992 #define EXTI_FTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 6993 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6994 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6995 #define EXTI_FTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 6996 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6997 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6998 #define EXTI_FTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 6999 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7000 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 7001 #define EXTI_FTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 7002 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7003 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 7004 #define EXTI_FTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 7005 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7006 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 7007 #define EXTI_FTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 7008 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7009 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 7010 #define EXTI_FTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 7011 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7012 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 7013 #define EXTI_FTSR_TR18_Pos (18U)
Kojto 122:f9eeca106725 7014 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7015 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 7016 #define EXTI_FTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 7017 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7018 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 7019 #define EXTI_FTSR_TR20_Pos (20U)
Kojto 122:f9eeca106725 7020 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7021 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 7022 #define EXTI_FTSR_TR21_Pos (21U)
Kojto 122:f9eeca106725 7023 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7024 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 7025 #define EXTI_FTSR_TR22_Pos (22U)
Kojto 122:f9eeca106725 7026 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7027 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 7028 #define EXTI_FTSR_TR29_Pos (29U)
Kojto 122:f9eeca106725 7029 #define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7030 #define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
Kojto 122:f9eeca106725 7031 #define EXTI_FTSR_TR30_Pos (30U)
Kojto 122:f9eeca106725 7032 #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7033 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
Kojto 122:f9eeca106725 7034 #define EXTI_FTSR_TR31_Pos (31U)
Kojto 122:f9eeca106725 7035 #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7036 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
Kojto 122:f9eeca106725 7037
Kojto 122:f9eeca106725 7038 /* References Defines */
Kojto 122:f9eeca106725 7039 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
Kojto 122:f9eeca106725 7040 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
Kojto 122:f9eeca106725 7041 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
Kojto 122:f9eeca106725 7042 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
Kojto 122:f9eeca106725 7043 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
Kojto 122:f9eeca106725 7044 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
Kojto 122:f9eeca106725 7045 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
Kojto 122:f9eeca106725 7046 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
Kojto 122:f9eeca106725 7047 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
Kojto 122:f9eeca106725 7048 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
Kojto 122:f9eeca106725 7049 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
Kojto 122:f9eeca106725 7050 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
Kojto 122:f9eeca106725 7051 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
Kojto 122:f9eeca106725 7052 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
Kojto 122:f9eeca106725 7053 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
Kojto 122:f9eeca106725 7054 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
Kojto 122:f9eeca106725 7055 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
Kojto 122:f9eeca106725 7056 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
Kojto 122:f9eeca106725 7057 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
Kojto 122:f9eeca106725 7058 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
Kojto 122:f9eeca106725 7059 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
Kojto 122:f9eeca106725 7060 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
Kojto 122:f9eeca106725 7061 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
Kojto 122:f9eeca106725 7062 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
Kojto 122:f9eeca106725 7063 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
Kojto 122:f9eeca106725 7064 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
Kojto 122:f9eeca106725 7065
Kojto 122:f9eeca106725 7066 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 7067 #define EXTI_SWIER_SWIER0_Pos (0U)
Kojto 122:f9eeca106725 7068 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7069 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 7070 #define EXTI_SWIER_SWIER1_Pos (1U)
Kojto 122:f9eeca106725 7071 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7072 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 7073 #define EXTI_SWIER_SWIER2_Pos (2U)
Kojto 122:f9eeca106725 7074 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7075 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 7076 #define EXTI_SWIER_SWIER3_Pos (3U)
Kojto 122:f9eeca106725 7077 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7078 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 7079 #define EXTI_SWIER_SWIER4_Pos (4U)
Kojto 122:f9eeca106725 7080 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7081 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 7082 #define EXTI_SWIER_SWIER5_Pos (5U)
Kojto 122:f9eeca106725 7083 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7084 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 7085 #define EXTI_SWIER_SWIER6_Pos (6U)
Kojto 122:f9eeca106725 7086 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7087 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 7088 #define EXTI_SWIER_SWIER7_Pos (7U)
Kojto 122:f9eeca106725 7089 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7090 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 7091 #define EXTI_SWIER_SWIER8_Pos (8U)
Kojto 122:f9eeca106725 7092 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7093 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 7094 #define EXTI_SWIER_SWIER9_Pos (9U)
Kojto 122:f9eeca106725 7095 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7096 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 7097 #define EXTI_SWIER_SWIER10_Pos (10U)
Kojto 122:f9eeca106725 7098 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7099 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 7100 #define EXTI_SWIER_SWIER11_Pos (11U)
Kojto 122:f9eeca106725 7101 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7102 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 7103 #define EXTI_SWIER_SWIER12_Pos (12U)
Kojto 122:f9eeca106725 7104 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7105 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 7106 #define EXTI_SWIER_SWIER13_Pos (13U)
Kojto 122:f9eeca106725 7107 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7108 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 7109 #define EXTI_SWIER_SWIER14_Pos (14U)
Kojto 122:f9eeca106725 7110 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7111 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 7112 #define EXTI_SWIER_SWIER15_Pos (15U)
Kojto 122:f9eeca106725 7113 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7114 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 7115 #define EXTI_SWIER_SWIER16_Pos (16U)
Kojto 122:f9eeca106725 7116 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7117 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 7118 #define EXTI_SWIER_SWIER17_Pos (17U)
Kojto 122:f9eeca106725 7119 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7120 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 7121 #define EXTI_SWIER_SWIER18_Pos (18U)
Kojto 122:f9eeca106725 7122 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7123 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 7124 #define EXTI_SWIER_SWIER19_Pos (19U)
Kojto 122:f9eeca106725 7125 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7126 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 7127 #define EXTI_SWIER_SWIER20_Pos (20U)
Kojto 122:f9eeca106725 7128 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7129 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 7130 #define EXTI_SWIER_SWIER21_Pos (21U)
Kojto 122:f9eeca106725 7131 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7132 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 7133 #define EXTI_SWIER_SWIER22_Pos (22U)
Kojto 122:f9eeca106725 7134 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7135 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
Kojto 122:f9eeca106725 7136 #define EXTI_SWIER_SWIER29_Pos (29U)
Kojto 122:f9eeca106725 7137 #define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7138 #define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
Kojto 122:f9eeca106725 7139 #define EXTI_SWIER_SWIER30_Pos (30U)
Kojto 122:f9eeca106725 7140 #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7141 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
Kojto 122:f9eeca106725 7142 #define EXTI_SWIER_SWIER31_Pos (31U)
Kojto 122:f9eeca106725 7143 #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7144 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
Kojto 122:f9eeca106725 7145
Kojto 122:f9eeca106725 7146 /* References Defines */
Kojto 122:f9eeca106725 7147 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
Kojto 122:f9eeca106725 7148 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
Kojto 122:f9eeca106725 7149 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
Kojto 122:f9eeca106725 7150 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
Kojto 122:f9eeca106725 7151 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
Kojto 122:f9eeca106725 7152 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
Kojto 122:f9eeca106725 7153 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
Kojto 122:f9eeca106725 7154 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
Kojto 122:f9eeca106725 7155 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
Kojto 122:f9eeca106725 7156 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
Kojto 122:f9eeca106725 7157 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
Kojto 122:f9eeca106725 7158 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
Kojto 122:f9eeca106725 7159 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
Kojto 122:f9eeca106725 7160 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
Kojto 122:f9eeca106725 7161 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
Kojto 122:f9eeca106725 7162 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
Kojto 122:f9eeca106725 7163 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
Kojto 122:f9eeca106725 7164 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
Kojto 122:f9eeca106725 7165 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
Kojto 122:f9eeca106725 7166 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
Kojto 122:f9eeca106725 7167 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
Kojto 122:f9eeca106725 7168 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
Kojto 122:f9eeca106725 7169 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
Kojto 122:f9eeca106725 7170 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
Kojto 122:f9eeca106725 7171 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
Kojto 122:f9eeca106725 7172 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
Kojto 122:f9eeca106725 7173
Kojto 122:f9eeca106725 7174 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 7175 #define EXTI_PR_PR0_Pos (0U)
Kojto 122:f9eeca106725 7176 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7177 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 7178 #define EXTI_PR_PR1_Pos (1U)
Kojto 122:f9eeca106725 7179 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7180 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 7181 #define EXTI_PR_PR2_Pos (2U)
Kojto 122:f9eeca106725 7182 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7183 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 7184 #define EXTI_PR_PR3_Pos (3U)
Kojto 122:f9eeca106725 7185 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7186 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 7187 #define EXTI_PR_PR4_Pos (4U)
Kojto 122:f9eeca106725 7188 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7189 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 7190 #define EXTI_PR_PR5_Pos (5U)
Kojto 122:f9eeca106725 7191 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7192 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 7193 #define EXTI_PR_PR6_Pos (6U)
Kojto 122:f9eeca106725 7194 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7195 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 7196 #define EXTI_PR_PR7_Pos (7U)
Kojto 122:f9eeca106725 7197 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7198 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 7199 #define EXTI_PR_PR8_Pos (8U)
Kojto 122:f9eeca106725 7200 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7201 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 7202 #define EXTI_PR_PR9_Pos (9U)
Kojto 122:f9eeca106725 7203 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7204 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 7205 #define EXTI_PR_PR10_Pos (10U)
Kojto 122:f9eeca106725 7206 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7207 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 7208 #define EXTI_PR_PR11_Pos (11U)
Kojto 122:f9eeca106725 7209 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7210 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 7211 #define EXTI_PR_PR12_Pos (12U)
Kojto 122:f9eeca106725 7212 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7213 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 7214 #define EXTI_PR_PR13_Pos (13U)
Kojto 122:f9eeca106725 7215 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7216 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 7217 #define EXTI_PR_PR14_Pos (14U)
Kojto 122:f9eeca106725 7218 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7219 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 7220 #define EXTI_PR_PR15_Pos (15U)
Kojto 122:f9eeca106725 7221 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7222 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 7223 #define EXTI_PR_PR16_Pos (16U)
Kojto 122:f9eeca106725 7224 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7225 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 7226 #define EXTI_PR_PR17_Pos (17U)
Kojto 122:f9eeca106725 7227 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7228 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 7229 #define EXTI_PR_PR18_Pos (18U)
Kojto 122:f9eeca106725 7230 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7231 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 7232 #define EXTI_PR_PR19_Pos (19U)
Kojto 122:f9eeca106725 7233 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7234 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 7235 #define EXTI_PR_PR20_Pos (20U)
Kojto 122:f9eeca106725 7236 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7237 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 7238 #define EXTI_PR_PR21_Pos (21U)
Kojto 122:f9eeca106725 7239 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7240 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 7241 #define EXTI_PR_PR22_Pos (22U)
Kojto 122:f9eeca106725 7242 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7243 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
Kojto 122:f9eeca106725 7244 #define EXTI_PR_PR29_Pos (29U)
Kojto 122:f9eeca106725 7245 #define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7246 #define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
Kojto 122:f9eeca106725 7247 #define EXTI_PR_PR30_Pos (30U)
Kojto 122:f9eeca106725 7248 #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7249 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
Kojto 122:f9eeca106725 7250 #define EXTI_PR_PR31_Pos (31U)
Kojto 122:f9eeca106725 7251 #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7252 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
Kojto 122:f9eeca106725 7253
Kojto 122:f9eeca106725 7254 /* References Defines */
Kojto 122:f9eeca106725 7255 #define EXTI_PR_PIF0 EXTI_PR_PR0
Kojto 122:f9eeca106725 7256 #define EXTI_PR_PIF1 EXTI_PR_PR1
Kojto 122:f9eeca106725 7257 #define EXTI_PR_PIF2 EXTI_PR_PR2
Kojto 122:f9eeca106725 7258 #define EXTI_PR_PIF3 EXTI_PR_PR3
Kojto 122:f9eeca106725 7259 #define EXTI_PR_PIF4 EXTI_PR_PR4
Kojto 122:f9eeca106725 7260 #define EXTI_PR_PIF5 EXTI_PR_PR5
Kojto 122:f9eeca106725 7261 #define EXTI_PR_PIF6 EXTI_PR_PR6
Kojto 122:f9eeca106725 7262 #define EXTI_PR_PIF7 EXTI_PR_PR7
Kojto 122:f9eeca106725 7263 #define EXTI_PR_PIF8 EXTI_PR_PR8
Kojto 122:f9eeca106725 7264 #define EXTI_PR_PIF9 EXTI_PR_PR9
Kojto 122:f9eeca106725 7265 #define EXTI_PR_PIF10 EXTI_PR_PR10
Kojto 122:f9eeca106725 7266 #define EXTI_PR_PIF11 EXTI_PR_PR11
Kojto 122:f9eeca106725 7267 #define EXTI_PR_PIF12 EXTI_PR_PR12
Kojto 122:f9eeca106725 7268 #define EXTI_PR_PIF13 EXTI_PR_PR13
Kojto 122:f9eeca106725 7269 #define EXTI_PR_PIF14 EXTI_PR_PR14
Kojto 122:f9eeca106725 7270 #define EXTI_PR_PIF15 EXTI_PR_PR15
Kojto 122:f9eeca106725 7271 #define EXTI_PR_PIF16 EXTI_PR_PR16
Kojto 122:f9eeca106725 7272 #define EXTI_PR_PIF17 EXTI_PR_PR17
Kojto 122:f9eeca106725 7273 #define EXTI_PR_PIF18 EXTI_PR_PR18
Kojto 122:f9eeca106725 7274 #define EXTI_PR_PIF19 EXTI_PR_PR19
Kojto 122:f9eeca106725 7275 #define EXTI_PR_PIF20 EXTI_PR_PR20
Kojto 122:f9eeca106725 7276 #define EXTI_PR_PIF21 EXTI_PR_PR21
Kojto 122:f9eeca106725 7277 #define EXTI_PR_PIF22 EXTI_PR_PR22
Kojto 122:f9eeca106725 7278 #define EXTI_PR_PIF29 EXTI_PR_PR29
Kojto 122:f9eeca106725 7279 #define EXTI_PR_PIF30 EXTI_PR_PR30
Kojto 122:f9eeca106725 7280 #define EXTI_PR_PIF31 EXTI_PR_PR31
Kojto 122:f9eeca106725 7281
Kojto 122:f9eeca106725 7282 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
Kojto 122:f9eeca106725 7283
Kojto 122:f9eeca106725 7284 /******************* Bit definition for EXTI_IMR2 register ******************/
Kojto 122:f9eeca106725 7285 #define EXTI_IMR2_MR32_Pos (0U)
Kojto 122:f9eeca106725 7286 #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7287 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
Kojto 122:f9eeca106725 7288 #define EXTI_IMR2_MR33_Pos (1U)
Kojto 122:f9eeca106725 7289 #define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7290 #define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
Kojto 122:f9eeca106725 7291 #define EXTI_IMR2_MR34_Pos (2U)
Kojto 122:f9eeca106725 7292 #define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7293 #define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
Kojto 122:f9eeca106725 7294 #define EXTI_IMR2_MR35_Pos (3U)
Kojto 122:f9eeca106725 7295 #define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7296 #define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
Kojto 122:f9eeca106725 7297
Kojto 122:f9eeca106725 7298 /* References Defines */
Kojto 122:f9eeca106725 7299 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
Kojto 122:f9eeca106725 7300 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
Kojto 122:f9eeca106725 7301 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
Kojto 122:f9eeca106725 7302 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
Kojto 122:f9eeca106725 7303
Kojto 122:f9eeca106725 7304 #define EXTI_IMR2_IM_Pos (0U)
Kojto 122:f9eeca106725 7305 #define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7306 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
Kojto 122:f9eeca106725 7307
Kojto 122:f9eeca106725 7308 /******************* Bit definition for EXTI_EMR2 ****************************/
Kojto 122:f9eeca106725 7309 #define EXTI_EMR2_MR32_Pos (0U)
Kojto 122:f9eeca106725 7310 #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7311 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
Kojto 122:f9eeca106725 7312 #define EXTI_EMR2_MR33_Pos (1U)
Kojto 122:f9eeca106725 7313 #define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7314 #define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
Kojto 122:f9eeca106725 7315 #define EXTI_EMR2_MR34_Pos (2U)
Kojto 122:f9eeca106725 7316 #define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7317 #define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
Kojto 122:f9eeca106725 7318 #define EXTI_EMR2_MR35_Pos (3U)
Kojto 122:f9eeca106725 7319 #define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7320 #define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
Kojto 122:f9eeca106725 7321
Kojto 122:f9eeca106725 7322 /* References Defines */
Kojto 122:f9eeca106725 7323 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
Kojto 122:f9eeca106725 7324 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
Kojto 122:f9eeca106725 7325 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
Kojto 122:f9eeca106725 7326 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
Kojto 122:f9eeca106725 7327
Kojto 122:f9eeca106725 7328 /****************** Bit definition for EXTI_RTSR2 register ********************/
Kojto 122:f9eeca106725 7329 #define EXTI_RTSR2_TR32_Pos (0U)
Kojto 122:f9eeca106725 7330 #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7331 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
Kojto 122:f9eeca106725 7332 #define EXTI_RTSR2_TR33_Pos (1U)
Kojto 122:f9eeca106725 7333 #define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7334 #define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
Kojto 122:f9eeca106725 7335
Kojto 122:f9eeca106725 7336 /* References Defines */
Kojto 122:f9eeca106725 7337 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
Kojto 122:f9eeca106725 7338 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
Kojto 122:f9eeca106725 7339
Kojto 122:f9eeca106725 7340 /****************** Bit definition for EXTI_FTSR2 register ******************/
Kojto 122:f9eeca106725 7341 #define EXTI_FTSR2_TR32_Pos (0U)
Kojto 122:f9eeca106725 7342 #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7343 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
Kojto 122:f9eeca106725 7344 #define EXTI_FTSR2_TR33_Pos (1U)
Kojto 122:f9eeca106725 7345 #define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7346 #define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
Kojto 122:f9eeca106725 7347
Kojto 122:f9eeca106725 7348 /* References Defines */
Kojto 122:f9eeca106725 7349 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
Kojto 122:f9eeca106725 7350 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
Kojto 122:f9eeca106725 7351
Kojto 122:f9eeca106725 7352 /****************** Bit definition for EXTI_SWIER2 register *****************/
Kojto 122:f9eeca106725 7353 #define EXTI_SWIER2_SWIER32_Pos (0U)
Kojto 122:f9eeca106725 7354 #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7355 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
Kojto 122:f9eeca106725 7356 #define EXTI_SWIER2_SWIER33_Pos (1U)
Kojto 122:f9eeca106725 7357 #define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7358 #define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
Kojto 122:f9eeca106725 7359
Kojto 122:f9eeca106725 7360 /* References Defines */
Kojto 122:f9eeca106725 7361 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
Kojto 122:f9eeca106725 7362 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
Kojto 122:f9eeca106725 7363
Kojto 122:f9eeca106725 7364 /******************* Bit definition for EXTI_PR2 register *******************/
Kojto 122:f9eeca106725 7365 #define EXTI_PR2_PR32_Pos (0U)
Kojto 122:f9eeca106725 7366 #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7367 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
Kojto 122:f9eeca106725 7368 #define EXTI_PR2_PR33_Pos (1U)
Kojto 122:f9eeca106725 7369 #define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7370 #define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
Kojto 122:f9eeca106725 7371
Kojto 122:f9eeca106725 7372 /* References Defines */
Kojto 122:f9eeca106725 7373 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
Kojto 122:f9eeca106725 7374 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
bogdanm 86:04dd9b1680ae 7375
bogdanm 86:04dd9b1680ae 7376 /******************************************************************************/
bogdanm 86:04dd9b1680ae 7377 /* */
bogdanm 86:04dd9b1680ae 7378 /* FLASH */
bogdanm 86:04dd9b1680ae 7379 /* */
bogdanm 86:04dd9b1680ae 7380 /******************************************************************************/
bogdanm 86:04dd9b1680ae 7381 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 122:f9eeca106725 7382 #define FLASH_ACR_LATENCY_Pos (0U)
Kojto 122:f9eeca106725 7383 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 7384 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
Kojto 122:f9eeca106725 7385 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7386 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7387 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7388
Kojto 122:f9eeca106725 7389 #define FLASH_ACR_HLFCYA_Pos (3U)
Kojto 122:f9eeca106725 7390 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7391 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
Kojto 122:f9eeca106725 7392 #define FLASH_ACR_PRFTBE_Pos (4U)
Kojto 122:f9eeca106725 7393 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7394 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
Kojto 122:f9eeca106725 7395 #define FLASH_ACR_PRFTBS_Pos (5U)
Kojto 122:f9eeca106725 7396 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7397 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
bogdanm 86:04dd9b1680ae 7398
bogdanm 86:04dd9b1680ae 7399 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 122:f9eeca106725 7400 #define FLASH_KEYR_FKEYR_Pos (0U)
Kojto 122:f9eeca106725 7401 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 7402 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
Kojto 122:f9eeca106725 7403
Kojto 122:f9eeca106725 7404 #define RDP_KEY_Pos (0U)
Kojto 122:f9eeca106725 7405 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
Kojto 122:f9eeca106725 7406 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
Kojto 122:f9eeca106725 7407 #define FLASH_KEY1_Pos (0U)
Kojto 122:f9eeca106725 7408 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
Kojto 122:f9eeca106725 7409 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
Kojto 122:f9eeca106725 7410 #define FLASH_KEY2_Pos (0U)
Kojto 122:f9eeca106725 7411 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
Kojto 122:f9eeca106725 7412 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
bogdanm 86:04dd9b1680ae 7413
bogdanm 86:04dd9b1680ae 7414 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 122:f9eeca106725 7415 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
Kojto 122:f9eeca106725 7416 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 7417 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
bogdanm 86:04dd9b1680ae 7418
bogdanm 86:04dd9b1680ae 7419 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
bogdanm 86:04dd9b1680ae 7420 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
bogdanm 86:04dd9b1680ae 7421
bogdanm 86:04dd9b1680ae 7422 /****************** Bit definition for FLASH_SR register *******************/
Kojto 122:f9eeca106725 7423 #define FLASH_SR_BSY_Pos (0U)
Kojto 122:f9eeca106725 7424 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7425 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
Kojto 122:f9eeca106725 7426 #define FLASH_SR_PGERR_Pos (2U)
Kojto 122:f9eeca106725 7427 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7428 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
Kojto 122:f9eeca106725 7429 #define FLASH_SR_WRPERR_Pos (4U)
Kojto 122:f9eeca106725 7430 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7431 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */
Kojto 122:f9eeca106725 7432 #define FLASH_SR_EOP_Pos (5U)
Kojto 122:f9eeca106725 7433 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7434 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
bogdanm 86:04dd9b1680ae 7435
bogdanm 86:04dd9b1680ae 7436 /******************* Bit definition for FLASH_CR register *******************/
Kojto 122:f9eeca106725 7437 #define FLASH_CR_PG_Pos (0U)
Kojto 122:f9eeca106725 7438 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7439 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
Kojto 122:f9eeca106725 7440 #define FLASH_CR_PER_Pos (1U)
Kojto 122:f9eeca106725 7441 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7442 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
Kojto 122:f9eeca106725 7443 #define FLASH_CR_MER_Pos (2U)
Kojto 122:f9eeca106725 7444 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7445 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
Kojto 122:f9eeca106725 7446 #define FLASH_CR_OPTPG_Pos (4U)
Kojto 122:f9eeca106725 7447 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7448 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
Kojto 122:f9eeca106725 7449 #define FLASH_CR_OPTER_Pos (5U)
Kojto 122:f9eeca106725 7450 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7451 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
Kojto 122:f9eeca106725 7452 #define FLASH_CR_STRT_Pos (6U)
Kojto 122:f9eeca106725 7453 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7454 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
Kojto 122:f9eeca106725 7455 #define FLASH_CR_LOCK_Pos (7U)
Kojto 122:f9eeca106725 7456 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7457 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
Kojto 122:f9eeca106725 7458 #define FLASH_CR_OPTWRE_Pos (9U)
Kojto 122:f9eeca106725 7459 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7460 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
Kojto 122:f9eeca106725 7461 #define FLASH_CR_ERRIE_Pos (10U)
Kojto 122:f9eeca106725 7462 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7463 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 7464 #define FLASH_CR_EOPIE_Pos (12U)
Kojto 122:f9eeca106725 7465 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7466 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
Kojto 122:f9eeca106725 7467 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
Kojto 122:f9eeca106725 7468 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7469 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */
bogdanm 86:04dd9b1680ae 7470
bogdanm 86:04dd9b1680ae 7471 /******************* Bit definition for FLASH_AR register *******************/
Kojto 122:f9eeca106725 7472 #define FLASH_AR_FAR_Pos (0U)
Kojto 122:f9eeca106725 7473 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 7474 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
bogdanm 86:04dd9b1680ae 7475
bogdanm 86:04dd9b1680ae 7476 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 122:f9eeca106725 7477 #define FLASH_OBR_OPTERR_Pos (0U)
Kojto 122:f9eeca106725 7478 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7479 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
Kojto 122:f9eeca106725 7480 #define FLASH_OBR_RDPRT_Pos (1U)
Kojto 122:f9eeca106725 7481 #define FLASH_OBR_RDPRT_Msk (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 7482 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
Kojto 122:f9eeca106725 7483 #define FLASH_OBR_RDPRT_1 (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7484 #define FLASH_OBR_RDPRT_2 (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 7485
Kojto 122:f9eeca106725 7486 #define FLASH_OBR_USER_Pos (8U)
Kojto 122:f9eeca106725 7487 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
Kojto 122:f9eeca106725 7488 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
Kojto 122:f9eeca106725 7489 #define FLASH_OBR_IWDG_SW_Pos (8U)
Kojto 122:f9eeca106725 7490 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7491 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
Kojto 122:f9eeca106725 7492 #define FLASH_OBR_nRST_STOP_Pos (9U)
Kojto 122:f9eeca106725 7493 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7494 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
Kojto 122:f9eeca106725 7495 #define FLASH_OBR_nRST_STDBY_Pos (10U)
Kojto 122:f9eeca106725 7496 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7497 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
Kojto 122:f9eeca106725 7498 #define FLASH_OBR_nBOOT1_Pos (12U)
Kojto 122:f9eeca106725 7499 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7500 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
Kojto 122:f9eeca106725 7501 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
Kojto 122:f9eeca106725 7502 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7503 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */
Kojto 122:f9eeca106725 7504 #define FLASH_OBR_SRAM_PE_Pos (14U)
Kojto 122:f9eeca106725 7505 #define FLASH_OBR_SRAM_PE_Msk (0x1U << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7506 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */
Kojto 122:f9eeca106725 7507 #define FLASH_OBR_DATA0_Pos (16U)
Kojto 122:f9eeca106725 7508 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7509 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
Kojto 122:f9eeca106725 7510 #define FLASH_OBR_DATA1_Pos (24U)
Kojto 122:f9eeca106725 7511 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 7512 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
Kojto 122:f9eeca106725 7513
Kojto 122:f9eeca106725 7514 /* Legacy defines */
Kojto 122:f9eeca106725 7515 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
bogdanm 86:04dd9b1680ae 7516
bogdanm 86:04dd9b1680ae 7517 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 122:f9eeca106725 7518 #define FLASH_WRPR_WRP_Pos (0U)
Kojto 122:f9eeca106725 7519 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 7520 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
bogdanm 86:04dd9b1680ae 7521
bogdanm 86:04dd9b1680ae 7522 /*----------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 7523
bogdanm 86:04dd9b1680ae 7524 /****************** Bit definition for OB_RDP register **********************/
Kojto 122:f9eeca106725 7525 #define OB_RDP_RDP_Pos (0U)
Kojto 122:f9eeca106725 7526 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7527 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
Kojto 122:f9eeca106725 7528 #define OB_RDP_nRDP_Pos (8U)
Kojto 122:f9eeca106725 7529 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 7530 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
bogdanm 86:04dd9b1680ae 7531
bogdanm 86:04dd9b1680ae 7532 /****************** Bit definition for OB_USER register *********************/
Kojto 122:f9eeca106725 7533 #define OB_USER_USER_Pos (16U)
Kojto 122:f9eeca106725 7534 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7535 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
Kojto 122:f9eeca106725 7536 #define OB_USER_nUSER_Pos (24U)
Kojto 122:f9eeca106725 7537 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 7538 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
bogdanm 86:04dd9b1680ae 7539
bogdanm 86:04dd9b1680ae 7540 /****************** Bit definition for FLASH_WRP0 register ******************/
Kojto 122:f9eeca106725 7541 #define OB_WRP0_WRP0_Pos (0U)
Kojto 122:f9eeca106725 7542 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7543 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 7544 #define OB_WRP0_nWRP0_Pos (8U)
Kojto 122:f9eeca106725 7545 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 7546 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
bogdanm 86:04dd9b1680ae 7547
bogdanm 86:04dd9b1680ae 7548 /****************** Bit definition for FLASH_WRP1 register ******************/
Kojto 122:f9eeca106725 7549 #define OB_WRP1_WRP1_Pos (16U)
Kojto 122:f9eeca106725 7550 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7551 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 7552 #define OB_WRP1_nWRP1_Pos (24U)
Kojto 122:f9eeca106725 7553 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 7554 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
bogdanm 86:04dd9b1680ae 7555
bogdanm 86:04dd9b1680ae 7556 /****************** Bit definition for FLASH_WRP2 register ******************/
Kojto 122:f9eeca106725 7557 #define OB_WRP2_WRP2_Pos (0U)
Kojto 122:f9eeca106725 7558 #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7559 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 7560 #define OB_WRP2_nWRP2_Pos (8U)
Kojto 122:f9eeca106725 7561 #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 7562 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
bogdanm 86:04dd9b1680ae 7563
bogdanm 86:04dd9b1680ae 7564 /****************** Bit definition for FLASH_WRP3 register ******************/
Kojto 122:f9eeca106725 7565 #define OB_WRP3_WRP3_Pos (16U)
Kojto 122:f9eeca106725 7566 #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7567 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 7568 #define OB_WRP3_nWRP3_Pos (24U)
Kojto 122:f9eeca106725 7569 #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 7570 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 122:f9eeca106725 7571
bogdanm 86:04dd9b1680ae 7572 /******************************************************************************/
bogdanm 86:04dd9b1680ae 7573 /* */
bogdanm 86:04dd9b1680ae 7574 /* General Purpose I/O (GPIO) */
bogdanm 86:04dd9b1680ae 7575 /* */
bogdanm 86:04dd9b1680ae 7576 /******************************************************************************/
bogdanm 86:04dd9b1680ae 7577 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 7578 #define GPIO_MODER_MODER0_Pos (0U)
Kojto 122:f9eeca106725 7579 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7580 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
Kojto 122:f9eeca106725 7581 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7582 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7583 #define GPIO_MODER_MODER1_Pos (2U)
Kojto 122:f9eeca106725 7584 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7585 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
Kojto 122:f9eeca106725 7586 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7587 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7588 #define GPIO_MODER_MODER2_Pos (4U)
Kojto 122:f9eeca106725 7589 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7590 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
Kojto 122:f9eeca106725 7591 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7592 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7593 #define GPIO_MODER_MODER3_Pos (6U)
Kojto 122:f9eeca106725 7594 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7595 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
Kojto 122:f9eeca106725 7596 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7597 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7598 #define GPIO_MODER_MODER4_Pos (8U)
Kojto 122:f9eeca106725 7599 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7600 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
Kojto 122:f9eeca106725 7601 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7602 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7603 #define GPIO_MODER_MODER5_Pos (10U)
Kojto 122:f9eeca106725 7604 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7605 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
Kojto 122:f9eeca106725 7606 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7607 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7608 #define GPIO_MODER_MODER6_Pos (12U)
Kojto 122:f9eeca106725 7609 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7610 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
Kojto 122:f9eeca106725 7611 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7612 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7613 #define GPIO_MODER_MODER7_Pos (14U)
Kojto 122:f9eeca106725 7614 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7615 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
Kojto 122:f9eeca106725 7616 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7617 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7618 #define GPIO_MODER_MODER8_Pos (16U)
Kojto 122:f9eeca106725 7619 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7620 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
Kojto 122:f9eeca106725 7621 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7622 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7623 #define GPIO_MODER_MODER9_Pos (18U)
Kojto 122:f9eeca106725 7624 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7625 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
Kojto 122:f9eeca106725 7626 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7627 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7628 #define GPIO_MODER_MODER10_Pos (20U)
Kojto 122:f9eeca106725 7629 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7630 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
Kojto 122:f9eeca106725 7631 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7632 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7633 #define GPIO_MODER_MODER11_Pos (22U)
Kojto 122:f9eeca106725 7634 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7635 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
Kojto 122:f9eeca106725 7636 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7637 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7638 #define GPIO_MODER_MODER12_Pos (24U)
Kojto 122:f9eeca106725 7639 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7640 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
Kojto 122:f9eeca106725 7641 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7642 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7643 #define GPIO_MODER_MODER13_Pos (26U)
Kojto 122:f9eeca106725 7644 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7645 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
Kojto 122:f9eeca106725 7646 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7647 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7648 #define GPIO_MODER_MODER14_Pos (28U)
Kojto 122:f9eeca106725 7649 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7650 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
Kojto 122:f9eeca106725 7651 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7652 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7653 #define GPIO_MODER_MODER15_Pos (30U)
Kojto 122:f9eeca106725 7654 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7655 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
Kojto 122:f9eeca106725 7656 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7657 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 7658
bogdanm 86:04dd9b1680ae 7659 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 122:f9eeca106725 7660 #define GPIO_OTYPER_OT_0 (0x00000001U)
Kojto 122:f9eeca106725 7661 #define GPIO_OTYPER_OT_1 (0x00000002U)
Kojto 122:f9eeca106725 7662 #define GPIO_OTYPER_OT_2 (0x00000004U)
Kojto 122:f9eeca106725 7663 #define GPIO_OTYPER_OT_3 (0x00000008U)
Kojto 122:f9eeca106725 7664 #define GPIO_OTYPER_OT_4 (0x00000010U)
Kojto 122:f9eeca106725 7665 #define GPIO_OTYPER_OT_5 (0x00000020U)
Kojto 122:f9eeca106725 7666 #define GPIO_OTYPER_OT_6 (0x00000040U)
Kojto 122:f9eeca106725 7667 #define GPIO_OTYPER_OT_7 (0x00000080U)
Kojto 122:f9eeca106725 7668 #define GPIO_OTYPER_OT_8 (0x00000100U)
Kojto 122:f9eeca106725 7669 #define GPIO_OTYPER_OT_9 (0x00000200U)
Kojto 122:f9eeca106725 7670 #define GPIO_OTYPER_OT_10 (0x00000400U)
Kojto 122:f9eeca106725 7671 #define GPIO_OTYPER_OT_11 (0x00000800U)
Kojto 122:f9eeca106725 7672 #define GPIO_OTYPER_OT_12 (0x00001000U)
Kojto 122:f9eeca106725 7673 #define GPIO_OTYPER_OT_13 (0x00002000U)
Kojto 122:f9eeca106725 7674 #define GPIO_OTYPER_OT_14 (0x00004000U)
Kojto 122:f9eeca106725 7675 #define GPIO_OTYPER_OT_15 (0x00008000U)
bogdanm 86:04dd9b1680ae 7676
bogdanm 86:04dd9b1680ae 7677 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 122:f9eeca106725 7678 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
Kojto 122:f9eeca106725 7679 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7680 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
Kojto 122:f9eeca106725 7681 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7682 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7683 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
Kojto 122:f9eeca106725 7684 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7685 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
Kojto 122:f9eeca106725 7686 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7687 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7688 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
Kojto 122:f9eeca106725 7689 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7690 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
Kojto 122:f9eeca106725 7691 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7692 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7693 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
Kojto 122:f9eeca106725 7694 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7695 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
Kojto 122:f9eeca106725 7696 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7697 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7698 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
Kojto 122:f9eeca106725 7699 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7700 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
Kojto 122:f9eeca106725 7701 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7702 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7703 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
Kojto 122:f9eeca106725 7704 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7705 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
Kojto 122:f9eeca106725 7706 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7707 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7708 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
Kojto 122:f9eeca106725 7709 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7710 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
Kojto 122:f9eeca106725 7711 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7712 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7713 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
Kojto 122:f9eeca106725 7714 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7715 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
Kojto 122:f9eeca106725 7716 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7717 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7718 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
Kojto 122:f9eeca106725 7719 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7720 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
Kojto 122:f9eeca106725 7721 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7722 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7723 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
Kojto 122:f9eeca106725 7724 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7725 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
Kojto 122:f9eeca106725 7726 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7727 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7728 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
Kojto 122:f9eeca106725 7729 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7730 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
Kojto 122:f9eeca106725 7731 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7732 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7733 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
Kojto 122:f9eeca106725 7734 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7735 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
Kojto 122:f9eeca106725 7736 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7737 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7738 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
Kojto 122:f9eeca106725 7739 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7740 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
Kojto 122:f9eeca106725 7741 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7742 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7743 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
Kojto 122:f9eeca106725 7744 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7745 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
Kojto 122:f9eeca106725 7746 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7747 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7748 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
Kojto 122:f9eeca106725 7749 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7750 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
Kojto 122:f9eeca106725 7751 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7752 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7753 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
Kojto 122:f9eeca106725 7754 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7755 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
Kojto 122:f9eeca106725 7756 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7757 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 7758
bogdanm 86:04dd9b1680ae 7759 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 122:f9eeca106725 7760 #define GPIO_PUPDR_PUPDR0_Pos (0U)
Kojto 122:f9eeca106725 7761 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7762 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
Kojto 122:f9eeca106725 7763 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7764 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7765 #define GPIO_PUPDR_PUPDR1_Pos (2U)
Kojto 122:f9eeca106725 7766 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7767 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
Kojto 122:f9eeca106725 7768 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7769 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7770 #define GPIO_PUPDR_PUPDR2_Pos (4U)
Kojto 122:f9eeca106725 7771 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7772 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
Kojto 122:f9eeca106725 7773 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7774 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7775 #define GPIO_PUPDR_PUPDR3_Pos (6U)
Kojto 122:f9eeca106725 7776 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7777 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
Kojto 122:f9eeca106725 7778 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7779 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7780 #define GPIO_PUPDR_PUPDR4_Pos (8U)
Kojto 122:f9eeca106725 7781 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7782 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
Kojto 122:f9eeca106725 7783 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7784 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7785 #define GPIO_PUPDR_PUPDR5_Pos (10U)
Kojto 122:f9eeca106725 7786 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7787 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
Kojto 122:f9eeca106725 7788 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7789 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7790 #define GPIO_PUPDR_PUPDR6_Pos (12U)
Kojto 122:f9eeca106725 7791 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7792 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
Kojto 122:f9eeca106725 7793 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7794 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7795 #define GPIO_PUPDR_PUPDR7_Pos (14U)
Kojto 122:f9eeca106725 7796 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7797 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
Kojto 122:f9eeca106725 7798 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7799 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7800 #define GPIO_PUPDR_PUPDR8_Pos (16U)
Kojto 122:f9eeca106725 7801 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7802 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
Kojto 122:f9eeca106725 7803 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7804 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7805 #define GPIO_PUPDR_PUPDR9_Pos (18U)
Kojto 122:f9eeca106725 7806 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7807 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
Kojto 122:f9eeca106725 7808 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7809 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7810 #define GPIO_PUPDR_PUPDR10_Pos (20U)
Kojto 122:f9eeca106725 7811 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7812 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
Kojto 122:f9eeca106725 7813 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7814 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7815 #define GPIO_PUPDR_PUPDR11_Pos (22U)
Kojto 122:f9eeca106725 7816 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7817 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
Kojto 122:f9eeca106725 7818 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7819 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7820 #define GPIO_PUPDR_PUPDR12_Pos (24U)
Kojto 122:f9eeca106725 7821 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7822 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
Kojto 122:f9eeca106725 7823 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7824 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7825 #define GPIO_PUPDR_PUPDR13_Pos (26U)
Kojto 122:f9eeca106725 7826 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7827 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
Kojto 122:f9eeca106725 7828 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7829 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7830 #define GPIO_PUPDR_PUPDR14_Pos (28U)
Kojto 122:f9eeca106725 7831 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7832 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
Kojto 122:f9eeca106725 7833 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7834 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7835 #define GPIO_PUPDR_PUPDR15_Pos (30U)
Kojto 122:f9eeca106725 7836 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7837 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
Kojto 122:f9eeca106725 7838 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7839 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 7840
bogdanm 86:04dd9b1680ae 7841 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 7842 #define GPIO_IDR_0 (0x00000001U)
Kojto 122:f9eeca106725 7843 #define GPIO_IDR_1 (0x00000002U)
Kojto 122:f9eeca106725 7844 #define GPIO_IDR_2 (0x00000004U)
Kojto 122:f9eeca106725 7845 #define GPIO_IDR_3 (0x00000008U)
Kojto 122:f9eeca106725 7846 #define GPIO_IDR_4 (0x00000010U)
Kojto 122:f9eeca106725 7847 #define GPIO_IDR_5 (0x00000020U)
Kojto 122:f9eeca106725 7848 #define GPIO_IDR_6 (0x00000040U)
Kojto 122:f9eeca106725 7849 #define GPIO_IDR_7 (0x00000080U)
Kojto 122:f9eeca106725 7850 #define GPIO_IDR_8 (0x00000100U)
Kojto 122:f9eeca106725 7851 #define GPIO_IDR_9 (0x00000200U)
Kojto 122:f9eeca106725 7852 #define GPIO_IDR_10 (0x00000400U)
Kojto 122:f9eeca106725 7853 #define GPIO_IDR_11 (0x00000800U)
Kojto 122:f9eeca106725 7854 #define GPIO_IDR_12 (0x00001000U)
Kojto 122:f9eeca106725 7855 #define GPIO_IDR_13 (0x00002000U)
Kojto 122:f9eeca106725 7856 #define GPIO_IDR_14 (0x00004000U)
Kojto 122:f9eeca106725 7857 #define GPIO_IDR_15 (0x00008000U)
bogdanm 86:04dd9b1680ae 7858
bogdanm 86:04dd9b1680ae 7859 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 122:f9eeca106725 7860 #define GPIO_ODR_0 (0x00000001U)
Kojto 122:f9eeca106725 7861 #define GPIO_ODR_1 (0x00000002U)
Kojto 122:f9eeca106725 7862 #define GPIO_ODR_2 (0x00000004U)
Kojto 122:f9eeca106725 7863 #define GPIO_ODR_3 (0x00000008U)
Kojto 122:f9eeca106725 7864 #define GPIO_ODR_4 (0x00000010U)
Kojto 122:f9eeca106725 7865 #define GPIO_ODR_5 (0x00000020U)
Kojto 122:f9eeca106725 7866 #define GPIO_ODR_6 (0x00000040U)
Kojto 122:f9eeca106725 7867 #define GPIO_ODR_7 (0x00000080U)
Kojto 122:f9eeca106725 7868 #define GPIO_ODR_8 (0x00000100U)
Kojto 122:f9eeca106725 7869 #define GPIO_ODR_9 (0x00000200U)
Kojto 122:f9eeca106725 7870 #define GPIO_ODR_10 (0x00000400U)
Kojto 122:f9eeca106725 7871 #define GPIO_ODR_11 (0x00000800U)
Kojto 122:f9eeca106725 7872 #define GPIO_ODR_12 (0x00001000U)
Kojto 122:f9eeca106725 7873 #define GPIO_ODR_13 (0x00002000U)
Kojto 122:f9eeca106725 7874 #define GPIO_ODR_14 (0x00004000U)
Kojto 122:f9eeca106725 7875 #define GPIO_ODR_15 (0x00008000U)
bogdanm 86:04dd9b1680ae 7876
bogdanm 86:04dd9b1680ae 7877 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 122:f9eeca106725 7878 #define GPIO_BSRR_BS_0 (0x00000001U)
Kojto 122:f9eeca106725 7879 #define GPIO_BSRR_BS_1 (0x00000002U)
Kojto 122:f9eeca106725 7880 #define GPIO_BSRR_BS_2 (0x00000004U)
Kojto 122:f9eeca106725 7881 #define GPIO_BSRR_BS_3 (0x00000008U)
Kojto 122:f9eeca106725 7882 #define GPIO_BSRR_BS_4 (0x00000010U)
Kojto 122:f9eeca106725 7883 #define GPIO_BSRR_BS_5 (0x00000020U)
Kojto 122:f9eeca106725 7884 #define GPIO_BSRR_BS_6 (0x00000040U)
Kojto 122:f9eeca106725 7885 #define GPIO_BSRR_BS_7 (0x00000080U)
Kojto 122:f9eeca106725 7886 #define GPIO_BSRR_BS_8 (0x00000100U)
Kojto 122:f9eeca106725 7887 #define GPIO_BSRR_BS_9 (0x00000200U)
Kojto 122:f9eeca106725 7888 #define GPIO_BSRR_BS_10 (0x00000400U)
Kojto 122:f9eeca106725 7889 #define GPIO_BSRR_BS_11 (0x00000800U)
Kojto 122:f9eeca106725 7890 #define GPIO_BSRR_BS_12 (0x00001000U)
Kojto 122:f9eeca106725 7891 #define GPIO_BSRR_BS_13 (0x00002000U)
Kojto 122:f9eeca106725 7892 #define GPIO_BSRR_BS_14 (0x00004000U)
Kojto 122:f9eeca106725 7893 #define GPIO_BSRR_BS_15 (0x00008000U)
Kojto 122:f9eeca106725 7894 #define GPIO_BSRR_BR_0 (0x00010000U)
Kojto 122:f9eeca106725 7895 #define GPIO_BSRR_BR_1 (0x00020000U)
Kojto 122:f9eeca106725 7896 #define GPIO_BSRR_BR_2 (0x00040000U)
Kojto 122:f9eeca106725 7897 #define GPIO_BSRR_BR_3 (0x00080000U)
Kojto 122:f9eeca106725 7898 #define GPIO_BSRR_BR_4 (0x00100000U)
Kojto 122:f9eeca106725 7899 #define GPIO_BSRR_BR_5 (0x00200000U)
Kojto 122:f9eeca106725 7900 #define GPIO_BSRR_BR_6 (0x00400000U)
Kojto 122:f9eeca106725 7901 #define GPIO_BSRR_BR_7 (0x00800000U)
Kojto 122:f9eeca106725 7902 #define GPIO_BSRR_BR_8 (0x01000000U)
Kojto 122:f9eeca106725 7903 #define GPIO_BSRR_BR_9 (0x02000000U)
Kojto 122:f9eeca106725 7904 #define GPIO_BSRR_BR_10 (0x04000000U)
Kojto 122:f9eeca106725 7905 #define GPIO_BSRR_BR_11 (0x08000000U)
Kojto 122:f9eeca106725 7906 #define GPIO_BSRR_BR_12 (0x10000000U)
Kojto 122:f9eeca106725 7907 #define GPIO_BSRR_BR_13 (0x20000000U)
Kojto 122:f9eeca106725 7908 #define GPIO_BSRR_BR_14 (0x40000000U)
Kojto 122:f9eeca106725 7909 #define GPIO_BSRR_BR_15 (0x80000000U)
bogdanm 86:04dd9b1680ae 7910
bogdanm 86:04dd9b1680ae 7911 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 122:f9eeca106725 7912 #define GPIO_LCKR_LCK0_Pos (0U)
Kojto 122:f9eeca106725 7913 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7914 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
Kojto 122:f9eeca106725 7915 #define GPIO_LCKR_LCK1_Pos (1U)
Kojto 122:f9eeca106725 7916 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7917 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
Kojto 122:f9eeca106725 7918 #define GPIO_LCKR_LCK2_Pos (2U)
Kojto 122:f9eeca106725 7919 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7920 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
Kojto 122:f9eeca106725 7921 #define GPIO_LCKR_LCK3_Pos (3U)
Kojto 122:f9eeca106725 7922 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7923 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
Kojto 122:f9eeca106725 7924 #define GPIO_LCKR_LCK4_Pos (4U)
Kojto 122:f9eeca106725 7925 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7926 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
Kojto 122:f9eeca106725 7927 #define GPIO_LCKR_LCK5_Pos (5U)
Kojto 122:f9eeca106725 7928 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7929 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
Kojto 122:f9eeca106725 7930 #define GPIO_LCKR_LCK6_Pos (6U)
Kojto 122:f9eeca106725 7931 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7932 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
Kojto 122:f9eeca106725 7933 #define GPIO_LCKR_LCK7_Pos (7U)
Kojto 122:f9eeca106725 7934 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7935 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
Kojto 122:f9eeca106725 7936 #define GPIO_LCKR_LCK8_Pos (8U)
Kojto 122:f9eeca106725 7937 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7938 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
Kojto 122:f9eeca106725 7939 #define GPIO_LCKR_LCK9_Pos (9U)
Kojto 122:f9eeca106725 7940 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7941 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
Kojto 122:f9eeca106725 7942 #define GPIO_LCKR_LCK10_Pos (10U)
Kojto 122:f9eeca106725 7943 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7944 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
Kojto 122:f9eeca106725 7945 #define GPIO_LCKR_LCK11_Pos (11U)
Kojto 122:f9eeca106725 7946 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7947 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
Kojto 122:f9eeca106725 7948 #define GPIO_LCKR_LCK12_Pos (12U)
Kojto 122:f9eeca106725 7949 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7950 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
Kojto 122:f9eeca106725 7951 #define GPIO_LCKR_LCK13_Pos (13U)
Kojto 122:f9eeca106725 7952 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7953 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
Kojto 122:f9eeca106725 7954 #define GPIO_LCKR_LCK14_Pos (14U)
Kojto 122:f9eeca106725 7955 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7956 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
Kojto 122:f9eeca106725 7957 #define GPIO_LCKR_LCK15_Pos (15U)
Kojto 122:f9eeca106725 7958 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7959 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
Kojto 122:f9eeca106725 7960 #define GPIO_LCKR_LCKK_Pos (16U)
Kojto 122:f9eeca106725 7961 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7962 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
bogdanm 86:04dd9b1680ae 7963
bogdanm 86:04dd9b1680ae 7964 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 122:f9eeca106725 7965 #define GPIO_AFRL_AFRL0_Pos (0U)
Kojto 122:f9eeca106725 7966 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7967 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
Kojto 122:f9eeca106725 7968 #define GPIO_AFRL_AFRL1_Pos (4U)
Kojto 122:f9eeca106725 7969 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7970 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
Kojto 122:f9eeca106725 7971 #define GPIO_AFRL_AFRL2_Pos (8U)
Kojto 122:f9eeca106725 7972 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7973 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
Kojto 122:f9eeca106725 7974 #define GPIO_AFRL_AFRL3_Pos (12U)
Kojto 122:f9eeca106725 7975 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 7976 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
Kojto 122:f9eeca106725 7977 #define GPIO_AFRL_AFRL4_Pos (16U)
Kojto 122:f9eeca106725 7978 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7979 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
Kojto 122:f9eeca106725 7980 #define GPIO_AFRL_AFRL5_Pos (20U)
Kojto 122:f9eeca106725 7981 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 7982 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
Kojto 122:f9eeca106725 7983 #define GPIO_AFRL_AFRL6_Pos (24U)
Kojto 122:f9eeca106725 7984 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 7985 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
Kojto 122:f9eeca106725 7986 #define GPIO_AFRL_AFRL7_Pos (28U)
Kojto 122:f9eeca106725 7987 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 7988 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
bogdanm 86:04dd9b1680ae 7989
bogdanm 86:04dd9b1680ae 7990 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 122:f9eeca106725 7991 #define GPIO_AFRH_AFRH0_Pos (0U)
Kojto 122:f9eeca106725 7992 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7993 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
Kojto 122:f9eeca106725 7994 #define GPIO_AFRH_AFRH1_Pos (4U)
Kojto 122:f9eeca106725 7995 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7996 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
Kojto 122:f9eeca106725 7997 #define GPIO_AFRH_AFRH2_Pos (8U)
Kojto 122:f9eeca106725 7998 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7999 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
Kojto 122:f9eeca106725 8000 #define GPIO_AFRH_AFRH3_Pos (12U)
Kojto 122:f9eeca106725 8001 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 8002 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
Kojto 122:f9eeca106725 8003 #define GPIO_AFRH_AFRH4_Pos (16U)
Kojto 122:f9eeca106725 8004 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8005 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
Kojto 122:f9eeca106725 8006 #define GPIO_AFRH_AFRH5_Pos (20U)
Kojto 122:f9eeca106725 8007 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 8008 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
Kojto 122:f9eeca106725 8009 #define GPIO_AFRH_AFRH6_Pos (24U)
Kojto 122:f9eeca106725 8010 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 8011 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
Kojto 122:f9eeca106725 8012 #define GPIO_AFRH_AFRH7_Pos (28U)
Kojto 122:f9eeca106725 8013 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 8014 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
bogdanm 86:04dd9b1680ae 8015
bogdanm 86:04dd9b1680ae 8016 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 122:f9eeca106725 8017 #define GPIO_BRR_BR_0 (0x00000001U)
Kojto 122:f9eeca106725 8018 #define GPIO_BRR_BR_1 (0x00000002U)
Kojto 122:f9eeca106725 8019 #define GPIO_BRR_BR_2 (0x00000004U)
Kojto 122:f9eeca106725 8020 #define GPIO_BRR_BR_3 (0x00000008U)
Kojto 122:f9eeca106725 8021 #define GPIO_BRR_BR_4 (0x00000010U)
Kojto 122:f9eeca106725 8022 #define GPIO_BRR_BR_5 (0x00000020U)
Kojto 122:f9eeca106725 8023 #define GPIO_BRR_BR_6 (0x00000040U)
Kojto 122:f9eeca106725 8024 #define GPIO_BRR_BR_7 (0x00000080U)
Kojto 122:f9eeca106725 8025 #define GPIO_BRR_BR_8 (0x00000100U)
Kojto 122:f9eeca106725 8026 #define GPIO_BRR_BR_9 (0x00000200U)
Kojto 122:f9eeca106725 8027 #define GPIO_BRR_BR_10 (0x00000400U)
Kojto 122:f9eeca106725 8028 #define GPIO_BRR_BR_11 (0x00000800U)
Kojto 122:f9eeca106725 8029 #define GPIO_BRR_BR_12 (0x00001000U)
Kojto 122:f9eeca106725 8030 #define GPIO_BRR_BR_13 (0x00002000U)
Kojto 122:f9eeca106725 8031 #define GPIO_BRR_BR_14 (0x00004000U)
Kojto 122:f9eeca106725 8032 #define GPIO_BRR_BR_15 (0x00008000U)
bogdanm 86:04dd9b1680ae 8033
bogdanm 86:04dd9b1680ae 8034 /******************************************************************************/
bogdanm 86:04dd9b1680ae 8035 /* */
bogdanm 86:04dd9b1680ae 8036 /* High Resolution Timer (HRTIM) */
bogdanm 86:04dd9b1680ae 8037 /* */
bogdanm 86:04dd9b1680ae 8038 /******************************************************************************/
bogdanm 86:04dd9b1680ae 8039 /******************** Master Timer control register ***************************/
Kojto 122:f9eeca106725 8040 #define HRTIM_MCR_CK_PSC_Pos (0U)
Kojto 122:f9eeca106725 8041 #define HRTIM_MCR_CK_PSC_Msk (0x7U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 8042 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
Kojto 122:f9eeca106725 8043 #define HRTIM_MCR_CK_PSC_0 (0x1U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8044 #define HRTIM_MCR_CK_PSC_1 (0x2U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8045 #define HRTIM_MCR_CK_PSC_2 (0x4U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8046
Kojto 122:f9eeca106725 8047 #define HRTIM_MCR_CONT_Pos (3U)
Kojto 122:f9eeca106725 8048 #define HRTIM_MCR_CONT_Msk (0x1U << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8049 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
Kojto 122:f9eeca106725 8050 #define HRTIM_MCR_RETRIG_Pos (4U)
Kojto 122:f9eeca106725 8051 #define HRTIM_MCR_RETRIG_Msk (0x1U << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8052 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
Kojto 122:f9eeca106725 8053 #define HRTIM_MCR_HALF_Pos (5U)
Kojto 122:f9eeca106725 8054 #define HRTIM_MCR_HALF_Msk (0x1U << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8055 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
Kojto 122:f9eeca106725 8056
Kojto 122:f9eeca106725 8057 #define HRTIM_MCR_SYNC_IN_Pos (8U)
Kojto 122:f9eeca106725 8058 #define HRTIM_MCR_SYNC_IN_Msk (0x3U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 8059 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
Kojto 122:f9eeca106725 8060 #define HRTIM_MCR_SYNC_IN_0 (0x1U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8061 #define HRTIM_MCR_SYNC_IN_1 (0x2U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8062 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
Kojto 122:f9eeca106725 8063 #define HRTIM_MCR_SYNCRSTM_Msk (0x1U << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8064 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
Kojto 122:f9eeca106725 8065 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
Kojto 122:f9eeca106725 8066 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1U << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8067 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
Kojto 122:f9eeca106725 8068 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
Kojto 122:f9eeca106725 8069 #define HRTIM_MCR_SYNC_OUT_Msk (0x3U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 8070 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
Kojto 122:f9eeca106725 8071 #define HRTIM_MCR_SYNC_OUT_0 (0x1U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8072 #define HRTIM_MCR_SYNC_OUT_1 (0x2U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8073 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
Kojto 122:f9eeca106725 8074 #define HRTIM_MCR_SYNC_SRC_Msk (0x3U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 8075 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
Kojto 122:f9eeca106725 8076 #define HRTIM_MCR_SYNC_SRC_0 (0x1U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8077 #define HRTIM_MCR_SYNC_SRC_1 (0x2U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8078
Kojto 122:f9eeca106725 8079 #define HRTIM_MCR_MCEN_Pos (16U)
Kojto 122:f9eeca106725 8080 #define HRTIM_MCR_MCEN_Msk (0x1U << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8081 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
Kojto 122:f9eeca106725 8082 #define HRTIM_MCR_TACEN_Pos (17U)
Kojto 122:f9eeca106725 8083 #define HRTIM_MCR_TACEN_Msk (0x1U << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8084 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
Kojto 122:f9eeca106725 8085 #define HRTIM_MCR_TBCEN_Pos (18U)
Kojto 122:f9eeca106725 8086 #define HRTIM_MCR_TBCEN_Msk (0x1U << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8087 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
Kojto 122:f9eeca106725 8088 #define HRTIM_MCR_TCCEN_Pos (19U)
Kojto 122:f9eeca106725 8089 #define HRTIM_MCR_TCCEN_Msk (0x1U << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8090 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
Kojto 122:f9eeca106725 8091 #define HRTIM_MCR_TDCEN_Pos (20U)
Kojto 122:f9eeca106725 8092 #define HRTIM_MCR_TDCEN_Msk (0x1U << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8093 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
Kojto 122:f9eeca106725 8094 #define HRTIM_MCR_TECEN_Pos (21U)
Kojto 122:f9eeca106725 8095 #define HRTIM_MCR_TECEN_Msk (0x1U << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8096 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
Kojto 122:f9eeca106725 8097
Kojto 122:f9eeca106725 8098 #define HRTIM_MCR_DACSYNC_Pos (25U)
Kojto 122:f9eeca106725 8099 #define HRTIM_MCR_DACSYNC_Msk (0x3U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
Kojto 122:f9eeca106725 8100 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
Kojto 122:f9eeca106725 8101 #define HRTIM_MCR_DACSYNC_0 (0x1U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8102 #define HRTIM_MCR_DACSYNC_1 (0x2U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8103
Kojto 122:f9eeca106725 8104 #define HRTIM_MCR_PREEN_Pos (27U)
Kojto 122:f9eeca106725 8105 #define HRTIM_MCR_PREEN_Msk (0x1U << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8106 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
Kojto 122:f9eeca106725 8107 #define HRTIM_MCR_MREPU_Pos (29U)
Kojto 122:f9eeca106725 8108 #define HRTIM_MCR_MREPU_Msk (0x1U << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8109 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
Kojto 122:f9eeca106725 8110
Kojto 122:f9eeca106725 8111 #define HRTIM_MCR_BRSTDMA_Pos (30U)
Kojto 122:f9eeca106725 8112 #define HRTIM_MCR_BRSTDMA_Msk (0x3U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 8113 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
Kojto 122:f9eeca106725 8114 #define HRTIM_MCR_BRSTDMA_0 (0x1U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8115 #define HRTIM_MCR_BRSTDMA_1 (0x2U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 8116
bogdanm 86:04dd9b1680ae 8117 /******************** Master Timer Interrupt status register ******************/
Kojto 122:f9eeca106725 8118 #define HRTIM_MISR_MCMP1_Pos (0U)
Kojto 122:f9eeca106725 8119 #define HRTIM_MISR_MCMP1_Msk (0x1U << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8120 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
Kojto 122:f9eeca106725 8121 #define HRTIM_MISR_MCMP2_Pos (1U)
Kojto 122:f9eeca106725 8122 #define HRTIM_MISR_MCMP2_Msk (0x1U << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8123 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
Kojto 122:f9eeca106725 8124 #define HRTIM_MISR_MCMP3_Pos (2U)
Kojto 122:f9eeca106725 8125 #define HRTIM_MISR_MCMP3_Msk (0x1U << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8126 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
Kojto 122:f9eeca106725 8127 #define HRTIM_MISR_MCMP4_Pos (3U)
Kojto 122:f9eeca106725 8128 #define HRTIM_MISR_MCMP4_Msk (0x1U << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8129 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
Kojto 122:f9eeca106725 8130 #define HRTIM_MISR_MREP_Pos (4U)
Kojto 122:f9eeca106725 8131 #define HRTIM_MISR_MREP_Msk (0x1U << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8132 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
Kojto 122:f9eeca106725 8133 #define HRTIM_MISR_SYNC_Pos (5U)
Kojto 122:f9eeca106725 8134 #define HRTIM_MISR_SYNC_Msk (0x1U << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8135 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
Kojto 122:f9eeca106725 8136 #define HRTIM_MISR_MUPD_Pos (6U)
Kojto 122:f9eeca106725 8137 #define HRTIM_MISR_MUPD_Msk (0x1U << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8138 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
bogdanm 86:04dd9b1680ae 8139
bogdanm 86:04dd9b1680ae 8140 /******************** Master Timer Interrupt clear register *******************/
Kojto 122:f9eeca106725 8141 #define HRTIM_MICR_MCMP1_Pos (0U)
Kojto 122:f9eeca106725 8142 #define HRTIM_MICR_MCMP1_Msk (0x1U << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8143 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
Kojto 122:f9eeca106725 8144 #define HRTIM_MICR_MCMP2_Pos (1U)
Kojto 122:f9eeca106725 8145 #define HRTIM_MICR_MCMP2_Msk (0x1U << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8146 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
Kojto 122:f9eeca106725 8147 #define HRTIM_MICR_MCMP3_Pos (2U)
Kojto 122:f9eeca106725 8148 #define HRTIM_MICR_MCMP3_Msk (0x1U << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8149 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
Kojto 122:f9eeca106725 8150 #define HRTIM_MICR_MCMP4_Pos (3U)
Kojto 122:f9eeca106725 8151 #define HRTIM_MICR_MCMP4_Msk (0x1U << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8152 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
Kojto 122:f9eeca106725 8153 #define HRTIM_MICR_MREP_Pos (4U)
Kojto 122:f9eeca106725 8154 #define HRTIM_MICR_MREP_Msk (0x1U << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8155 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
Kojto 122:f9eeca106725 8156 #define HRTIM_MICR_SYNC_Pos (5U)
Kojto 122:f9eeca106725 8157 #define HRTIM_MICR_SYNC_Msk (0x1U << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8158 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
Kojto 122:f9eeca106725 8159 #define HRTIM_MICR_MUPD_Pos (6U)
Kojto 122:f9eeca106725 8160 #define HRTIM_MICR_MUPD_Msk (0x1U << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8161 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
bogdanm 86:04dd9b1680ae 8162
bogdanm 86:04dd9b1680ae 8163 /******************** Master Timer DMA/Interrupt enable register **************/
Kojto 122:f9eeca106725 8164 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
Kojto 122:f9eeca106725 8165 #define HRTIM_MDIER_MCMP1IE_Msk (0x1U << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8166 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
Kojto 122:f9eeca106725 8167 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
Kojto 122:f9eeca106725 8168 #define HRTIM_MDIER_MCMP2IE_Msk (0x1U << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8169 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
Kojto 122:f9eeca106725 8170 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
Kojto 122:f9eeca106725 8171 #define HRTIM_MDIER_MCMP3IE_Msk (0x1U << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8172 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
Kojto 122:f9eeca106725 8173 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
Kojto 122:f9eeca106725 8174 #define HRTIM_MDIER_MCMP4IE_Msk (0x1U << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8175 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
Kojto 122:f9eeca106725 8176 #define HRTIM_MDIER_MREPIE_Pos (4U)
Kojto 122:f9eeca106725 8177 #define HRTIM_MDIER_MREPIE_Msk (0x1U << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8178 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
Kojto 122:f9eeca106725 8179 #define HRTIM_MDIER_SYNCIE_Pos (5U)
Kojto 122:f9eeca106725 8180 #define HRTIM_MDIER_SYNCIE_Msk (0x1U << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8181 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
Kojto 122:f9eeca106725 8182 #define HRTIM_MDIER_MUPDIE_Pos (6U)
Kojto 122:f9eeca106725 8183 #define HRTIM_MDIER_MUPDIE_Msk (0x1U << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8184 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
Kojto 122:f9eeca106725 8185
Kojto 122:f9eeca106725 8186 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
Kojto 122:f9eeca106725 8187 #define HRTIM_MDIER_MCMP1DE_Msk (0x1U << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8188 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
Kojto 122:f9eeca106725 8189 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
Kojto 122:f9eeca106725 8190 #define HRTIM_MDIER_MCMP2DE_Msk (0x1U << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8191 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
Kojto 122:f9eeca106725 8192 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
Kojto 122:f9eeca106725 8193 #define HRTIM_MDIER_MCMP3DE_Msk (0x1U << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8194 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
Kojto 122:f9eeca106725 8195 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
Kojto 122:f9eeca106725 8196 #define HRTIM_MDIER_MCMP4DE_Msk (0x1U << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8197 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
Kojto 122:f9eeca106725 8198 #define HRTIM_MDIER_MREPDE_Pos (20U)
Kojto 122:f9eeca106725 8199 #define HRTIM_MDIER_MREPDE_Msk (0x1U << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8200 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
Kojto 122:f9eeca106725 8201 #define HRTIM_MDIER_SYNCDE_Pos (21U)
Kojto 122:f9eeca106725 8202 #define HRTIM_MDIER_SYNCDE_Msk (0x1U << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8203 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
Kojto 122:f9eeca106725 8204 #define HRTIM_MDIER_MUPDDE_Pos (22U)
Kojto 122:f9eeca106725 8205 #define HRTIM_MDIER_MUPDDE_Msk (0x1U << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8206 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
bogdanm 86:04dd9b1680ae 8207
bogdanm 86:04dd9b1680ae 8208 /******************* Bit definition for HRTIM_MCNTR register ****************/
Kojto 122:f9eeca106725 8209 #define HRTIM_MCNTR_MCNTR_Pos (0U)
Kojto 122:f9eeca106725 8210 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFFFFFU << HRTIM_MCNTR_MCNTR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8211 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
bogdanm 86:04dd9b1680ae 8212
bogdanm 86:04dd9b1680ae 8213 /******************* Bit definition for HRTIM_MPER register *****************/
Kojto 122:f9eeca106725 8214 #define HRTIM_MPER_MPER_Pos (0U)
Kojto 122:f9eeca106725 8215 #define HRTIM_MPER_MPER_Msk (0xFFFFFFFFU << HRTIM_MPER_MPER_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8216 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
bogdanm 86:04dd9b1680ae 8217
bogdanm 86:04dd9b1680ae 8218 /******************* Bit definition for HRTIM_MREP register *****************/
Kojto 122:f9eeca106725 8219 #define HRTIM_MREP_MREP_Pos (0U)
Kojto 122:f9eeca106725 8220 #define HRTIM_MREP_MREP_Msk (0xFFFFFFFFU << HRTIM_MREP_MREP_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8221 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
bogdanm 86:04dd9b1680ae 8222
bogdanm 86:04dd9b1680ae 8223 /******************* Bit definition for HRTIM_MCMP1R register *****************/
Kojto 122:f9eeca106725 8224 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
Kojto 122:f9eeca106725 8225 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFFFFFU << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8226 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
bogdanm 86:04dd9b1680ae 8227
bogdanm 86:04dd9b1680ae 8228 /******************* Bit definition for HRTIM_MCMP2R register *****************/
Kojto 122:f9eeca106725 8229 #define HRTIM_MCMP2R_MCMP2R_Pos (0U)
Kojto 122:f9eeca106725 8230 #define HRTIM_MCMP2R_MCMP2R_Msk (0xFFFFFFFFU << HRTIM_MCMP2R_MCMP2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8231 #define HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk /*!<Compare Value */
bogdanm 86:04dd9b1680ae 8232
bogdanm 86:04dd9b1680ae 8233 /******************* Bit definition for HRTIM_MCMP3R register *****************/
Kojto 122:f9eeca106725 8234 #define HRTIM_MCMP3R_MCMP3R_Pos (0U)
Kojto 122:f9eeca106725 8235 #define HRTIM_MCMP3R_MCMP3R_Msk (0xFFFFFFFFU << HRTIM_MCMP3R_MCMP3R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8236 #define HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk /*!<Compare Value */
bogdanm 86:04dd9b1680ae 8237
bogdanm 86:04dd9b1680ae 8238 /******************* Bit definition for HRTIM_MCMP4R register *****************/
Kojto 122:f9eeca106725 8239 #define HRTIM_MCMP4R_MCMP4R_Pos (0U)
Kojto 122:f9eeca106725 8240 #define HRTIM_MCMP4R_MCMP4R_Msk (0xFFFFFFFFU << HRTIM_MCMP4R_MCMP4R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8241 #define HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk /*!<Compare Value */
Kojto 122:f9eeca106725 8242
Kojto 122:f9eeca106725 8243 /* Legacy defines */
Kojto 122:f9eeca106725 8244 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
Kojto 122:f9eeca106725 8245 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
Kojto 122:f9eeca106725 8246 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
bogdanm 86:04dd9b1680ae 8247
bogdanm 86:04dd9b1680ae 8248 /******************** Slave control register **********************************/
Kojto 122:f9eeca106725 8249 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
Kojto 122:f9eeca106725 8250 #define HRTIM_TIMCR_CK_PSC_Msk (0x7U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 8251 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
Kojto 122:f9eeca106725 8252 #define HRTIM_TIMCR_CK_PSC_0 (0x1U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8253 #define HRTIM_TIMCR_CK_PSC_1 (0x2U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8254 #define HRTIM_TIMCR_CK_PSC_2 (0x4U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8255
Kojto 122:f9eeca106725 8256 #define HRTIM_TIMCR_CONT_Pos (3U)
Kojto 122:f9eeca106725 8257 #define HRTIM_TIMCR_CONT_Msk (0x1U << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8258 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
Kojto 122:f9eeca106725 8259 #define HRTIM_TIMCR_RETRIG_Pos (4U)
Kojto 122:f9eeca106725 8260 #define HRTIM_TIMCR_RETRIG_Msk (0x1U << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8261 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
Kojto 122:f9eeca106725 8262 #define HRTIM_TIMCR_HALF_Pos (5U)
Kojto 122:f9eeca106725 8263 #define HRTIM_TIMCR_HALF_Msk (0x1U << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8264 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
Kojto 122:f9eeca106725 8265 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
Kojto 122:f9eeca106725 8266 #define HRTIM_TIMCR_PSHPLL_Msk (0x1U << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8267 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
Kojto 122:f9eeca106725 8268
Kojto 122:f9eeca106725 8269 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
Kojto 122:f9eeca106725 8270 #define HRTIM_TIMCR_SYNCRST_Msk (0x1U << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8271 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
Kojto 122:f9eeca106725 8272 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
Kojto 122:f9eeca106725 8273 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1U << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8274 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
Kojto 122:f9eeca106725 8275
Kojto 122:f9eeca106725 8276 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
Kojto 122:f9eeca106725 8277 #define HRTIM_TIMCR_DELCMP2_Msk (0x3U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 8278 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
Kojto 122:f9eeca106725 8279 #define HRTIM_TIMCR_DELCMP2_0 (0x1U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8280 #define HRTIM_TIMCR_DELCMP2_1 (0x2U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8281 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
Kojto 122:f9eeca106725 8282 #define HRTIM_TIMCR_DELCMP4_Msk (0x3U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 8283 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
Kojto 122:f9eeca106725 8284 #define HRTIM_TIMCR_DELCMP4_0 (0x1U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8285 #define HRTIM_TIMCR_DELCMP4_1 (0x2U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8286
Kojto 122:f9eeca106725 8287 #define HRTIM_TIMCR_TREPU_Pos (17U)
Kojto 122:f9eeca106725 8288 #define HRTIM_TIMCR_TREPU_Msk (0x1U << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8289 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
Kojto 122:f9eeca106725 8290 #define HRTIM_TIMCR_TRSTU_Pos (18U)
Kojto 122:f9eeca106725 8291 #define HRTIM_TIMCR_TRSTU_Msk (0x1U << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8292 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
Kojto 122:f9eeca106725 8293 #define HRTIM_TIMCR_TAU_Pos (19U)
Kojto 122:f9eeca106725 8294 #define HRTIM_TIMCR_TAU_Msk (0x1U << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8295 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
Kojto 122:f9eeca106725 8296 #define HRTIM_TIMCR_TBU_Pos (20U)
Kojto 122:f9eeca106725 8297 #define HRTIM_TIMCR_TBU_Msk (0x1U << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8298 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
Kojto 122:f9eeca106725 8299 #define HRTIM_TIMCR_TCU_Pos (21U)
Kojto 122:f9eeca106725 8300 #define HRTIM_TIMCR_TCU_Msk (0x1U << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8301 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
Kojto 122:f9eeca106725 8302 #define HRTIM_TIMCR_TDU_Pos (22U)
Kojto 122:f9eeca106725 8303 #define HRTIM_TIMCR_TDU_Msk (0x1U << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8304 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
Kojto 122:f9eeca106725 8305 #define HRTIM_TIMCR_TEU_Pos (23U)
Kojto 122:f9eeca106725 8306 #define HRTIM_TIMCR_TEU_Msk (0x1U << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8307 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
Kojto 122:f9eeca106725 8308 #define HRTIM_TIMCR_MSTU_Pos (24U)
Kojto 122:f9eeca106725 8309 #define HRTIM_TIMCR_MSTU_Msk (0x1U << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8310 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
Kojto 122:f9eeca106725 8311
Kojto 122:f9eeca106725 8312 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
Kojto 122:f9eeca106725 8313 #define HRTIM_TIMCR_DACSYNC_Msk (0x3U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
Kojto 122:f9eeca106725 8314 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
Kojto 122:f9eeca106725 8315 #define HRTIM_TIMCR_DACSYNC_0 (0x1U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8316 #define HRTIM_TIMCR_DACSYNC_1 (0x2U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8317 #define HRTIM_TIMCR_PREEN_Pos (27U)
Kojto 122:f9eeca106725 8318 #define HRTIM_TIMCR_PREEN_Msk (0x1U << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8319 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
Kojto 122:f9eeca106725 8320
Kojto 122:f9eeca106725 8321 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
Kojto 122:f9eeca106725 8322 #define HRTIM_TIMCR_UPDGAT_Msk (0xFU << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 8323 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
Kojto 122:f9eeca106725 8324 #define HRTIM_TIMCR_UPDGAT_0 (0x1U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8325 #define HRTIM_TIMCR_UPDGAT_1 (0x2U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8326 #define HRTIM_TIMCR_UPDGAT_2 (0x4U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8327 #define HRTIM_TIMCR_UPDGAT_3 (0x8U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 8328
bogdanm 86:04dd9b1680ae 8329 /******************** Slave Interrupt status register **************************/
Kojto 122:f9eeca106725 8330 #define HRTIM_TIMISR_CMP1_Pos (0U)
Kojto 122:f9eeca106725 8331 #define HRTIM_TIMISR_CMP1_Msk (0x1U << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8332 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
Kojto 122:f9eeca106725 8333 #define HRTIM_TIMISR_CMP2_Pos (1U)
Kojto 122:f9eeca106725 8334 #define HRTIM_TIMISR_CMP2_Msk (0x1U << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8335 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
Kojto 122:f9eeca106725 8336 #define HRTIM_TIMISR_CMP3_Pos (2U)
Kojto 122:f9eeca106725 8337 #define HRTIM_TIMISR_CMP3_Msk (0x1U << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8338 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
Kojto 122:f9eeca106725 8339 #define HRTIM_TIMISR_CMP4_Pos (3U)
Kojto 122:f9eeca106725 8340 #define HRTIM_TIMISR_CMP4_Msk (0x1U << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8341 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
Kojto 122:f9eeca106725 8342 #define HRTIM_TIMISR_REP_Pos (4U)
Kojto 122:f9eeca106725 8343 #define HRTIM_TIMISR_REP_Msk (0x1U << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8344 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
Kojto 122:f9eeca106725 8345 #define HRTIM_TIMISR_UPD_Pos (6U)
Kojto 122:f9eeca106725 8346 #define HRTIM_TIMISR_UPD_Msk (0x1U << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8347 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
Kojto 122:f9eeca106725 8348 #define HRTIM_TIMISR_CPT1_Pos (7U)
Kojto 122:f9eeca106725 8349 #define HRTIM_TIMISR_CPT1_Msk (0x1U << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8350 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
Kojto 122:f9eeca106725 8351 #define HRTIM_TIMISR_CPT2_Pos (8U)
Kojto 122:f9eeca106725 8352 #define HRTIM_TIMISR_CPT2_Msk (0x1U << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8353 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
Kojto 122:f9eeca106725 8354 #define HRTIM_TIMISR_SET1_Pos (9U)
Kojto 122:f9eeca106725 8355 #define HRTIM_TIMISR_SET1_Msk (0x1U << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8356 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
Kojto 122:f9eeca106725 8357 #define HRTIM_TIMISR_RST1_Pos (10U)
Kojto 122:f9eeca106725 8358 #define HRTIM_TIMISR_RST1_Msk (0x1U << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8359 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
Kojto 122:f9eeca106725 8360 #define HRTIM_TIMISR_SET2_Pos (11U)
Kojto 122:f9eeca106725 8361 #define HRTIM_TIMISR_SET2_Msk (0x1U << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8362 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
Kojto 122:f9eeca106725 8363 #define HRTIM_TIMISR_RST2_Pos (12U)
Kojto 122:f9eeca106725 8364 #define HRTIM_TIMISR_RST2_Msk (0x1U << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8365 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
Kojto 122:f9eeca106725 8366 #define HRTIM_TIMISR_RST_Pos (13U)
Kojto 122:f9eeca106725 8367 #define HRTIM_TIMISR_RST_Msk (0x1U << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8368 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
Kojto 122:f9eeca106725 8369 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
Kojto 122:f9eeca106725 8370 #define HRTIM_TIMISR_DLYPRT_Msk (0x1U << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8371 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
Kojto 122:f9eeca106725 8372 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
Kojto 122:f9eeca106725 8373 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1U << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8374 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
Kojto 122:f9eeca106725 8375 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
Kojto 122:f9eeca106725 8376 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1U << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8377 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
Kojto 122:f9eeca106725 8378 #define HRTIM_TIMISR_O1STAT_Pos (18U)
Kojto 122:f9eeca106725 8379 #define HRTIM_TIMISR_O1STAT_Msk (0x1U << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8380 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
Kojto 122:f9eeca106725 8381 #define HRTIM_TIMISR_O2STAT_Pos (19U)
Kojto 122:f9eeca106725 8382 #define HRTIM_TIMISR_O2STAT_Msk (0x1U << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8383 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
Kojto 122:f9eeca106725 8384 #define HRTIM_TIMISR_O1CPY_Pos (20U)
Kojto 122:f9eeca106725 8385 #define HRTIM_TIMISR_O1CPY_Msk (0x1U << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8386 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
Kojto 122:f9eeca106725 8387 #define HRTIM_TIMISR_O2CPY_Pos (21U)
Kojto 122:f9eeca106725 8388 #define HRTIM_TIMISR_O2CPY_Msk (0x1U << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8389 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
bogdanm 86:04dd9b1680ae 8390
bogdanm 86:04dd9b1680ae 8391 /******************** Slave Interrupt clear register **************************/
Kojto 122:f9eeca106725 8392 #define HRTIM_TIMICR_CMP1C_Pos (0U)
Kojto 122:f9eeca106725 8393 #define HRTIM_TIMICR_CMP1C_Msk (0x1U << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8394 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
Kojto 122:f9eeca106725 8395 #define HRTIM_TIMICR_CMP2C_Pos (1U)
Kojto 122:f9eeca106725 8396 #define HRTIM_TIMICR_CMP2C_Msk (0x1U << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8397 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
Kojto 122:f9eeca106725 8398 #define HRTIM_TIMICR_CMP3C_Pos (2U)
Kojto 122:f9eeca106725 8399 #define HRTIM_TIMICR_CMP3C_Msk (0x1U << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8400 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
Kojto 122:f9eeca106725 8401 #define HRTIM_TIMICR_CMP4C_Pos (3U)
Kojto 122:f9eeca106725 8402 #define HRTIM_TIMICR_CMP4C_Msk (0x1U << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8403 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
Kojto 122:f9eeca106725 8404 #define HRTIM_TIMICR_REPC_Pos (4U)
Kojto 122:f9eeca106725 8405 #define HRTIM_TIMICR_REPC_Msk (0x1U << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8406 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
Kojto 122:f9eeca106725 8407 #define HRTIM_TIMICR_UPDC_Pos (6U)
Kojto 122:f9eeca106725 8408 #define HRTIM_TIMICR_UPDC_Msk (0x1U << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8409 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
Kojto 122:f9eeca106725 8410 #define HRTIM_TIMICR_CPT1C_Pos (7U)
Kojto 122:f9eeca106725 8411 #define HRTIM_TIMICR_CPT1C_Msk (0x1U << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8412 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
Kojto 122:f9eeca106725 8413 #define HRTIM_TIMICR_CPT2C_Pos (8U)
Kojto 122:f9eeca106725 8414 #define HRTIM_TIMICR_CPT2C_Msk (0x1U << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8415 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
Kojto 122:f9eeca106725 8416 #define HRTIM_TIMICR_SET1C_Pos (9U)
Kojto 122:f9eeca106725 8417 #define HRTIM_TIMICR_SET1C_Msk (0x1U << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8418 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
Kojto 122:f9eeca106725 8419 #define HRTIM_TIMICR_RST1C_Pos (10U)
Kojto 122:f9eeca106725 8420 #define HRTIM_TIMICR_RST1C_Msk (0x1U << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8421 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
Kojto 122:f9eeca106725 8422 #define HRTIM_TIMICR_SET2C_Pos (11U)
Kojto 122:f9eeca106725 8423 #define HRTIM_TIMICR_SET2C_Msk (0x1U << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8424 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
Kojto 122:f9eeca106725 8425 #define HRTIM_TIMICR_RST2C_Pos (12U)
Kojto 122:f9eeca106725 8426 #define HRTIM_TIMICR_RST2C_Msk (0x1U << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8427 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
Kojto 122:f9eeca106725 8428 #define HRTIM_TIMICR_RSTC_Pos (13U)
Kojto 122:f9eeca106725 8429 #define HRTIM_TIMICR_RSTC_Msk (0x1U << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8430 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
Kojto 122:f9eeca106725 8431 #define HRTIM_TIMICR_DLYPRT1C_Pos (14U)
Kojto 122:f9eeca106725 8432 #define HRTIM_TIMICR_DLYPRT1C_Msk (0x1U << HRTIM_TIMICR_DLYPRT1C_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8433 #define HRTIM_TIMICR_DLYPRT1C HRTIM_TIMICR_DLYPRT1C_Msk /*!< Slave output 1 delay protection clear flag */
Kojto 122:f9eeca106725 8434 #define HRTIM_TIMICR_DLYPRT2C_Pos (15U)
Kojto 122:f9eeca106725 8435 #define HRTIM_TIMICR_DLYPRT2C_Msk (0x1U << HRTIM_TIMICR_DLYPRT2C_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8436 #define HRTIM_TIMICR_DLYPRT2C HRTIM_TIMICR_DLYPRT2C_Msk /*!< Slave output 2 delay protection clear flag */
bogdanm 86:04dd9b1680ae 8437
bogdanm 86:04dd9b1680ae 8438 /******************** Slave DMA/Interrupt enable register *********************/
Kojto 122:f9eeca106725 8439 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
Kojto 122:f9eeca106725 8440 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1U << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8441 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
Kojto 122:f9eeca106725 8442 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
Kojto 122:f9eeca106725 8443 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1U << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8444 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
Kojto 122:f9eeca106725 8445 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
Kojto 122:f9eeca106725 8446 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1U << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8447 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
Kojto 122:f9eeca106725 8448 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
Kojto 122:f9eeca106725 8449 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1U << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8450 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
Kojto 122:f9eeca106725 8451 #define HRTIM_TIMDIER_REPIE_Pos (4U)
Kojto 122:f9eeca106725 8452 #define HRTIM_TIMDIER_REPIE_Msk (0x1U << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8453 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
Kojto 122:f9eeca106725 8454 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
Kojto 122:f9eeca106725 8455 #define HRTIM_TIMDIER_UPDIE_Msk (0x1U << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8456 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
Kojto 122:f9eeca106725 8457 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
Kojto 122:f9eeca106725 8458 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1U << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8459 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
Kojto 122:f9eeca106725 8460 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
Kojto 122:f9eeca106725 8461 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1U << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8462 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
Kojto 122:f9eeca106725 8463 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
Kojto 122:f9eeca106725 8464 #define HRTIM_TIMDIER_SET1IE_Msk (0x1U << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8465 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
Kojto 122:f9eeca106725 8466 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
Kojto 122:f9eeca106725 8467 #define HRTIM_TIMDIER_RST1IE_Msk (0x1U << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8468 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
Kojto 122:f9eeca106725 8469 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
Kojto 122:f9eeca106725 8470 #define HRTIM_TIMDIER_SET2IE_Msk (0x1U << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8471 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
Kojto 122:f9eeca106725 8472 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
Kojto 122:f9eeca106725 8473 #define HRTIM_TIMDIER_RST2IE_Msk (0x1U << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8474 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
Kojto 122:f9eeca106725 8475 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
Kojto 122:f9eeca106725 8476 #define HRTIM_TIMDIER_RSTIE_Msk (0x1U << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8477 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
Kojto 122:f9eeca106725 8478 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
Kojto 122:f9eeca106725 8479 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8480 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
Kojto 122:f9eeca106725 8481
Kojto 122:f9eeca106725 8482 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
Kojto 122:f9eeca106725 8483 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1U << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8484 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
Kojto 122:f9eeca106725 8485 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
Kojto 122:f9eeca106725 8486 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1U << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8487 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
Kojto 122:f9eeca106725 8488 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
Kojto 122:f9eeca106725 8489 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1U << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8490 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
Kojto 122:f9eeca106725 8491 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
Kojto 122:f9eeca106725 8492 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1U << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8493 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
Kojto 122:f9eeca106725 8494 #define HRTIM_TIMDIER_REPDE_Pos (20U)
Kojto 122:f9eeca106725 8495 #define HRTIM_TIMDIER_REPDE_Msk (0x1U << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8496 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
Kojto 122:f9eeca106725 8497 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
Kojto 122:f9eeca106725 8498 #define HRTIM_TIMDIER_UPDDE_Msk (0x1U << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8499 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
Kojto 122:f9eeca106725 8500 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
Kojto 122:f9eeca106725 8501 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1U << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8502 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
Kojto 122:f9eeca106725 8503 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
Kojto 122:f9eeca106725 8504 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1U << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8505 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
Kojto 122:f9eeca106725 8506 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
Kojto 122:f9eeca106725 8507 #define HRTIM_TIMDIER_SET1DE_Msk (0x1U << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8508 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
Kojto 122:f9eeca106725 8509 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
Kojto 122:f9eeca106725 8510 #define HRTIM_TIMDIER_RST1DE_Msk (0x1U << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8511 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
Kojto 122:f9eeca106725 8512 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
Kojto 122:f9eeca106725 8513 #define HRTIM_TIMDIER_SET2DE_Msk (0x1U << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8514 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
Kojto 122:f9eeca106725 8515 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
Kojto 122:f9eeca106725 8516 #define HRTIM_TIMDIER_RST2DE_Msk (0x1U << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8517 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
Kojto 122:f9eeca106725 8518 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
Kojto 122:f9eeca106725 8519 #define HRTIM_TIMDIER_RSTDE_Msk (0x1U << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8520 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
Kojto 122:f9eeca106725 8521 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
Kojto 122:f9eeca106725 8522 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8523 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
bogdanm 86:04dd9b1680ae 8524
bogdanm 86:04dd9b1680ae 8525 /****************** Bit definition for HRTIM_CNTR register ****************/
Kojto 122:f9eeca106725 8526 #define HRTIM_CNTR_CNTR_Pos (0U)
Kojto 122:f9eeca106725 8527 #define HRTIM_CNTR_CNTR_Msk (0xFFFFFFFFU << HRTIM_CNTR_CNTR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8528 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
bogdanm 86:04dd9b1680ae 8529
bogdanm 86:04dd9b1680ae 8530 /******************* Bit definition for HRTIM_PER register *****************/
Kojto 122:f9eeca106725 8531 #define HRTIM_PER_PER_Pos (0U)
Kojto 122:f9eeca106725 8532 #define HRTIM_PER_PER_Msk (0xFFFFFFFFU << HRTIM_PER_PER_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8533 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
bogdanm 86:04dd9b1680ae 8534
bogdanm 86:04dd9b1680ae 8535 /******************* Bit definition for HRTIM_REP register *****************/
Kojto 122:f9eeca106725 8536 #define HRTIM_REP_REP_Pos (0U)
Kojto 122:f9eeca106725 8537 #define HRTIM_REP_REP_Msk (0xFFFFFFFFU << HRTIM_REP_REP_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8538 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
bogdanm 86:04dd9b1680ae 8539
bogdanm 86:04dd9b1680ae 8540 /******************* Bit definition for HRTIM_CMP1R register *****************/
Kojto 122:f9eeca106725 8541 #define HRTIM_CMP1R_CMP1R_Pos (0U)
Kojto 122:f9eeca106725 8542 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFFFFFU << HRTIM_CMP1R_CMP1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8543 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
bogdanm 86:04dd9b1680ae 8544
bogdanm 86:04dd9b1680ae 8545 /******************* Bit definition for HRTIM_CMP1CR register *****************/
Kojto 122:f9eeca106725 8546 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
Kojto 122:f9eeca106725 8547 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFU << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8548 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
bogdanm 86:04dd9b1680ae 8549
bogdanm 86:04dd9b1680ae 8550 /******************* Bit definition for HRTIM_CMP2R register *****************/
Kojto 122:f9eeca106725 8551 #define HRTIM_CMP2R_CMP2R_Pos (0U)
Kojto 122:f9eeca106725 8552 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFFFFFU << HRTIM_CMP2R_CMP2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8553 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
bogdanm 86:04dd9b1680ae 8554
bogdanm 86:04dd9b1680ae 8555 /******************* Bit definition for HRTIM_CMP3R register *****************/
Kojto 122:f9eeca106725 8556 #define HRTIM_CMP3R_CMP3R_Pos (0U)
Kojto 122:f9eeca106725 8557 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFFFFFU << HRTIM_CMP3R_CMP3R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8558 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
bogdanm 86:04dd9b1680ae 8559
bogdanm 86:04dd9b1680ae 8560 /******************* Bit definition for HRTIM_CMP4R register *****************/
Kojto 122:f9eeca106725 8561 #define HRTIM_CMP4R_CMP4R_Pos (0U)
Kojto 122:f9eeca106725 8562 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFFFFFU << HRTIM_CMP4R_CMP4R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8563 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
bogdanm 86:04dd9b1680ae 8564
bogdanm 86:04dd9b1680ae 8565 /******************* Bit definition for HRTIM_CPT1R register ****************/
Kojto 122:f9eeca106725 8566 #define HRTIM_CPT1R_CPT1R_Pos (0U)
Kojto 122:f9eeca106725 8567 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFFFFFU << HRTIM_CPT1R_CPT1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8568 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
bogdanm 86:04dd9b1680ae 8569
bogdanm 86:04dd9b1680ae 8570 /******************* Bit definition for HRTIM_CPT2R register ****************/
Kojto 122:f9eeca106725 8571 #define HRTIM_CPT2R_CPT2R_Pos (0U)
Kojto 122:f9eeca106725 8572 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFFFFFU << HRTIM_CPT2R_CPT2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 8573 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
bogdanm 86:04dd9b1680ae 8574
bogdanm 86:04dd9b1680ae 8575 /******************** Bit definition for Slave Deadtime register **************/
Kojto 122:f9eeca106725 8576 #define HRTIM_DTR_DTR_Pos (0U)
Kojto 122:f9eeca106725 8577 #define HRTIM_DTR_DTR_Msk (0x1FFU << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 8578 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
Kojto 122:f9eeca106725 8579 #define HRTIM_DTR_DTR_0 (0x001U << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8580 #define HRTIM_DTR_DTR_1 (0x002U << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8581 #define HRTIM_DTR_DTR_2 (0x004U << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8582 #define HRTIM_DTR_DTR_3 (0x008U << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8583 #define HRTIM_DTR_DTR_4 (0x010U << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8584 #define HRTIM_DTR_DTR_5 (0x020U << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8585 #define HRTIM_DTR_DTR_6 (0x040U << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8586 #define HRTIM_DTR_DTR_7 (0x080U << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8587 #define HRTIM_DTR_DTR_8 (0x100U << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8588 #define HRTIM_DTR_SDTR_Pos (9U)
Kojto 122:f9eeca106725 8589 #define HRTIM_DTR_SDTR_Msk (0x1U << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8590 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
Kojto 122:f9eeca106725 8591 #define HRTIM_DTR_DTPRSC_Pos (10U)
Kojto 122:f9eeca106725 8592 #define HRTIM_DTR_DTPRSC_Msk (0x7U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
Kojto 122:f9eeca106725 8593 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
Kojto 122:f9eeca106725 8594 #define HRTIM_DTR_DTPRSC_0 (0x1U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8595 #define HRTIM_DTR_DTPRSC_1 (0x2U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8596 #define HRTIM_DTR_DTPRSC_2 (0x4U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8597 #define HRTIM_DTR_DTRSLK_Pos (14U)
Kojto 122:f9eeca106725 8598 #define HRTIM_DTR_DTRSLK_Msk (0x1U << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8599 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
Kojto 122:f9eeca106725 8600 #define HRTIM_DTR_DTRLK_Pos (15U)
Kojto 122:f9eeca106725 8601 #define HRTIM_DTR_DTRLK_Msk (0x1U << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8602 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
Kojto 122:f9eeca106725 8603 #define HRTIM_DTR_DTF_Pos (16U)
Kojto 122:f9eeca106725 8604 #define HRTIM_DTR_DTF_Msk (0x1FFU << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
Kojto 122:f9eeca106725 8605 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
Kojto 122:f9eeca106725 8606 #define HRTIM_DTR_DTF_0 (0x001U << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8607 #define HRTIM_DTR_DTF_1 (0x002U << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8608 #define HRTIM_DTR_DTF_2 (0x004U << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8609 #define HRTIM_DTR_DTF_3 (0x008U << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8610 #define HRTIM_DTR_DTF_4 (0x010U << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8611 #define HRTIM_DTR_DTF_5 (0x020U << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8612 #define HRTIM_DTR_DTF_6 (0x040U << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8613 #define HRTIM_DTR_DTF_7 (0x080U << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8614 #define HRTIM_DTR_DTF_8 (0x100U << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8615 #define HRTIM_DTR_SDTF_Pos (25U)
Kojto 122:f9eeca106725 8616 #define HRTIM_DTR_SDTF_Msk (0x1U << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8617 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
Kojto 122:f9eeca106725 8618 #define HRTIM_DTR_DTFSLK_Pos (30U)
Kojto 122:f9eeca106725 8619 #define HRTIM_DTR_DTFSLK_Msk (0x1U << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8620 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
Kojto 122:f9eeca106725 8621 #define HRTIM_DTR_DTFLK_Pos (31U)
Kojto 122:f9eeca106725 8622 #define HRTIM_DTR_DTFLK_Msk (0x1U << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8623 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
bogdanm 86:04dd9b1680ae 8624
bogdanm 86:04dd9b1680ae 8625 /**** Bit definition for Slave Output 1 set register **************************/
Kojto 122:f9eeca106725 8626 #define HRTIM_SET1R_SST_Pos (0U)
Kojto 122:f9eeca106725 8627 #define HRTIM_SET1R_SST_Msk (0x1U << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8628 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
Kojto 122:f9eeca106725 8629 #define HRTIM_SET1R_RESYNC_Pos (1U)
Kojto 122:f9eeca106725 8630 #define HRTIM_SET1R_RESYNC_Msk (0x1U << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8631 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
Kojto 122:f9eeca106725 8632 #define HRTIM_SET1R_PER_Pos (2U)
Kojto 122:f9eeca106725 8633 #define HRTIM_SET1R_PER_Msk (0x1U << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8634 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
Kojto 122:f9eeca106725 8635 #define HRTIM_SET1R_CMP1_Pos (3U)
Kojto 122:f9eeca106725 8636 #define HRTIM_SET1R_CMP1_Msk (0x1U << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8637 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 8638 #define HRTIM_SET1R_CMP2_Pos (4U)
Kojto 122:f9eeca106725 8639 #define HRTIM_SET1R_CMP2_Msk (0x1U << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8640 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 8641 #define HRTIM_SET1R_CMP3_Pos (5U)
Kojto 122:f9eeca106725 8642 #define HRTIM_SET1R_CMP3_Msk (0x1U << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8643 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
Kojto 122:f9eeca106725 8644 #define HRTIM_SET1R_CMP4_Pos (6U)
Kojto 122:f9eeca106725 8645 #define HRTIM_SET1R_CMP4_Msk (0x1U << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8646 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
Kojto 122:f9eeca106725 8647
Kojto 122:f9eeca106725 8648 #define HRTIM_SET1R_MSTPER_Pos (7U)
Kojto 122:f9eeca106725 8649 #define HRTIM_SET1R_MSTPER_Msk (0x1U << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8650 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
Kojto 122:f9eeca106725 8651 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
Kojto 122:f9eeca106725 8652 #define HRTIM_SET1R_MSTCMP1_Msk (0x1U << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8653 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
Kojto 122:f9eeca106725 8654 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
Kojto 122:f9eeca106725 8655 #define HRTIM_SET1R_MSTCMP2_Msk (0x1U << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8656 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
Kojto 122:f9eeca106725 8657 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
Kojto 122:f9eeca106725 8658 #define HRTIM_SET1R_MSTCMP3_Msk (0x1U << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8659 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
Kojto 122:f9eeca106725 8660 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
Kojto 122:f9eeca106725 8661 #define HRTIM_SET1R_MSTCMP4_Msk (0x1U << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8662 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
Kojto 122:f9eeca106725 8663
Kojto 122:f9eeca106725 8664 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
Kojto 122:f9eeca106725 8665 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1U << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8666 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
Kojto 122:f9eeca106725 8667 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
Kojto 122:f9eeca106725 8668 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1U << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8669 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
Kojto 122:f9eeca106725 8670 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
Kojto 122:f9eeca106725 8671 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1U << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8672 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
Kojto 122:f9eeca106725 8673 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
Kojto 122:f9eeca106725 8674 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1U << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8675 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
Kojto 122:f9eeca106725 8676 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
Kojto 122:f9eeca106725 8677 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1U << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8678 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
Kojto 122:f9eeca106725 8679 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
Kojto 122:f9eeca106725 8680 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1U << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8681 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
Kojto 122:f9eeca106725 8682 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
Kojto 122:f9eeca106725 8683 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1U << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8684 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
Kojto 122:f9eeca106725 8685 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
Kojto 122:f9eeca106725 8686 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1U << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8687 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
Kojto 122:f9eeca106725 8688 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
Kojto 122:f9eeca106725 8689 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1U << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8690 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
Kojto 122:f9eeca106725 8691
Kojto 122:f9eeca106725 8692 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
Kojto 122:f9eeca106725 8693 #define HRTIM_SET1R_EXTVNT1_Msk (0x1U << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8694 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
Kojto 122:f9eeca106725 8695 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
Kojto 122:f9eeca106725 8696 #define HRTIM_SET1R_EXTVNT2_Msk (0x1U << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8697 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
Kojto 122:f9eeca106725 8698 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
Kojto 122:f9eeca106725 8699 #define HRTIM_SET1R_EXTVNT3_Msk (0x1U << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8700 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
Kojto 122:f9eeca106725 8701 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
Kojto 122:f9eeca106725 8702 #define HRTIM_SET1R_EXTVNT4_Msk (0x1U << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8703 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
Kojto 122:f9eeca106725 8704 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
Kojto 122:f9eeca106725 8705 #define HRTIM_SET1R_EXTVNT5_Msk (0x1U << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8706 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
Kojto 122:f9eeca106725 8707 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
Kojto 122:f9eeca106725 8708 #define HRTIM_SET1R_EXTVNT6_Msk (0x1U << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8709 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
Kojto 122:f9eeca106725 8710 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
Kojto 122:f9eeca106725 8711 #define HRTIM_SET1R_EXTVNT7_Msk (0x1U << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8712 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
Kojto 122:f9eeca106725 8713 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
Kojto 122:f9eeca106725 8714 #define HRTIM_SET1R_EXTVNT8_Msk (0x1U << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8715 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
Kojto 122:f9eeca106725 8716 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
Kojto 122:f9eeca106725 8717 #define HRTIM_SET1R_EXTVNT9_Msk (0x1U << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8718 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
Kojto 122:f9eeca106725 8719 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
Kojto 122:f9eeca106725 8720 #define HRTIM_SET1R_EXTVNT10_Msk (0x1U << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8721 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
Kojto 122:f9eeca106725 8722
Kojto 122:f9eeca106725 8723 #define HRTIM_SET1R_UPDATE_Pos (31U)
Kojto 122:f9eeca106725 8724 #define HRTIM_SET1R_UPDATE_Msk (0x1U << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8725 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
bogdanm 86:04dd9b1680ae 8726
bogdanm 86:04dd9b1680ae 8727 /**** Bit definition for Slave Output 1 reset register ************************/
Kojto 122:f9eeca106725 8728 #define HRTIM_RST1R_SRT_Pos (0U)
Kojto 122:f9eeca106725 8729 #define HRTIM_RST1R_SRT_Msk (0x1U << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8730 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
Kojto 122:f9eeca106725 8731 #define HRTIM_RST1R_RESYNC_Pos (1U)
Kojto 122:f9eeca106725 8732 #define HRTIM_RST1R_RESYNC_Msk (0x1U << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8733 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
Kojto 122:f9eeca106725 8734 #define HRTIM_RST1R_PER_Pos (2U)
Kojto 122:f9eeca106725 8735 #define HRTIM_RST1R_PER_Msk (0x1U << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8736 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
Kojto 122:f9eeca106725 8737 #define HRTIM_RST1R_CMP1_Pos (3U)
Kojto 122:f9eeca106725 8738 #define HRTIM_RST1R_CMP1_Msk (0x1U << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8739 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 8740 #define HRTIM_RST1R_CMP2_Pos (4U)
Kojto 122:f9eeca106725 8741 #define HRTIM_RST1R_CMP2_Msk (0x1U << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8742 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 8743 #define HRTIM_RST1R_CMP3_Pos (5U)
Kojto 122:f9eeca106725 8744 #define HRTIM_RST1R_CMP3_Msk (0x1U << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8745 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
Kojto 122:f9eeca106725 8746 #define HRTIM_RST1R_CMP4_Pos (6U)
Kojto 122:f9eeca106725 8747 #define HRTIM_RST1R_CMP4_Msk (0x1U << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8748 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
Kojto 122:f9eeca106725 8749
Kojto 122:f9eeca106725 8750 #define HRTIM_RST1R_MSTPER_Pos (7U)
Kojto 122:f9eeca106725 8751 #define HRTIM_RST1R_MSTPER_Msk (0x1U << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8752 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
Kojto 122:f9eeca106725 8753 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
Kojto 122:f9eeca106725 8754 #define HRTIM_RST1R_MSTCMP1_Msk (0x1U << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8755 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
Kojto 122:f9eeca106725 8756 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
Kojto 122:f9eeca106725 8757 #define HRTIM_RST1R_MSTCMP2_Msk (0x1U << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8758 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
Kojto 122:f9eeca106725 8759 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
Kojto 122:f9eeca106725 8760 #define HRTIM_RST1R_MSTCMP3_Msk (0x1U << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8761 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
Kojto 122:f9eeca106725 8762 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
Kojto 122:f9eeca106725 8763 #define HRTIM_RST1R_MSTCMP4_Msk (0x1U << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8764 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
Kojto 122:f9eeca106725 8765
Kojto 122:f9eeca106725 8766 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
Kojto 122:f9eeca106725 8767 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1U << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8768 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
Kojto 122:f9eeca106725 8769 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
Kojto 122:f9eeca106725 8770 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1U << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8771 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
Kojto 122:f9eeca106725 8772 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
Kojto 122:f9eeca106725 8773 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1U << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8774 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
Kojto 122:f9eeca106725 8775 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
Kojto 122:f9eeca106725 8776 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1U << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8777 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
Kojto 122:f9eeca106725 8778 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
Kojto 122:f9eeca106725 8779 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1U << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8780 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
Kojto 122:f9eeca106725 8781 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
Kojto 122:f9eeca106725 8782 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1U << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8783 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
Kojto 122:f9eeca106725 8784 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
Kojto 122:f9eeca106725 8785 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1U << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8786 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
Kojto 122:f9eeca106725 8787 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
Kojto 122:f9eeca106725 8788 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1U << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8789 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
Kojto 122:f9eeca106725 8790 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
Kojto 122:f9eeca106725 8791 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1U << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8792 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
Kojto 122:f9eeca106725 8793
Kojto 122:f9eeca106725 8794 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
Kojto 122:f9eeca106725 8795 #define HRTIM_RST1R_EXTVNT1_Msk (0x1U << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8796 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
Kojto 122:f9eeca106725 8797 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
Kojto 122:f9eeca106725 8798 #define HRTIM_RST1R_EXTVNT2_Msk (0x1U << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8799 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
Kojto 122:f9eeca106725 8800 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
Kojto 122:f9eeca106725 8801 #define HRTIM_RST1R_EXTVNT3_Msk (0x1U << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8802 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
Kojto 122:f9eeca106725 8803 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
Kojto 122:f9eeca106725 8804 #define HRTIM_RST1R_EXTVNT4_Msk (0x1U << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8805 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
Kojto 122:f9eeca106725 8806 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
Kojto 122:f9eeca106725 8807 #define HRTIM_RST1R_EXTVNT5_Msk (0x1U << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8808 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
Kojto 122:f9eeca106725 8809 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
Kojto 122:f9eeca106725 8810 #define HRTIM_RST1R_EXTVNT6_Msk (0x1U << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8811 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
Kojto 122:f9eeca106725 8812 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
Kojto 122:f9eeca106725 8813 #define HRTIM_RST1R_EXTVNT7_Msk (0x1U << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8814 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
Kojto 122:f9eeca106725 8815 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
Kojto 122:f9eeca106725 8816 #define HRTIM_RST1R_EXTVNT8_Msk (0x1U << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8817 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
Kojto 122:f9eeca106725 8818 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
Kojto 122:f9eeca106725 8819 #define HRTIM_RST1R_EXTVNT9_Msk (0x1U << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8820 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
Kojto 122:f9eeca106725 8821 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
Kojto 122:f9eeca106725 8822 #define HRTIM_RST1R_EXTVNT10_Msk (0x1U << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8823 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
Kojto 122:f9eeca106725 8824
Kojto 122:f9eeca106725 8825 #define HRTIM_RST1R_UPDATE_Pos (31U)
Kojto 122:f9eeca106725 8826 #define HRTIM_RST1R_UPDATE_Msk (0x1U << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8827 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
bogdanm 86:04dd9b1680ae 8828
bogdanm 86:04dd9b1680ae 8829
bogdanm 86:04dd9b1680ae 8830 /**** Bit definition for Slave Output 2 set register **************************/
Kojto 122:f9eeca106725 8831 #define HRTIM_SET2R_SST_Pos (0U)
Kojto 122:f9eeca106725 8832 #define HRTIM_SET2R_SST_Msk (0x1U << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8833 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
Kojto 122:f9eeca106725 8834 #define HRTIM_SET2R_RESYNC_Pos (1U)
Kojto 122:f9eeca106725 8835 #define HRTIM_SET2R_RESYNC_Msk (0x1U << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8836 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
Kojto 122:f9eeca106725 8837 #define HRTIM_SET2R_PER_Pos (2U)
Kojto 122:f9eeca106725 8838 #define HRTIM_SET2R_PER_Msk (0x1U << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8839 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
Kojto 122:f9eeca106725 8840 #define HRTIM_SET2R_CMP1_Pos (3U)
Kojto 122:f9eeca106725 8841 #define HRTIM_SET2R_CMP1_Msk (0x1U << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8842 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 8843 #define HRTIM_SET2R_CMP2_Pos (4U)
Kojto 122:f9eeca106725 8844 #define HRTIM_SET2R_CMP2_Msk (0x1U << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8845 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 8846 #define HRTIM_SET2R_CMP3_Pos (5U)
Kojto 122:f9eeca106725 8847 #define HRTIM_SET2R_CMP3_Msk (0x1U << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8848 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
Kojto 122:f9eeca106725 8849 #define HRTIM_SET2R_CMP4_Pos (6U)
Kojto 122:f9eeca106725 8850 #define HRTIM_SET2R_CMP4_Msk (0x1U << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8851 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
Kojto 122:f9eeca106725 8852
Kojto 122:f9eeca106725 8853 #define HRTIM_SET2R_MSTPER_Pos (7U)
Kojto 122:f9eeca106725 8854 #define HRTIM_SET2R_MSTPER_Msk (0x1U << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8855 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
Kojto 122:f9eeca106725 8856 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
Kojto 122:f9eeca106725 8857 #define HRTIM_SET2R_MSTCMP1_Msk (0x1U << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8858 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
Kojto 122:f9eeca106725 8859 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
Kojto 122:f9eeca106725 8860 #define HRTIM_SET2R_MSTCMP2_Msk (0x1U << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8861 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
Kojto 122:f9eeca106725 8862 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
Kojto 122:f9eeca106725 8863 #define HRTIM_SET2R_MSTCMP3_Msk (0x1U << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8864 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
Kojto 122:f9eeca106725 8865 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
Kojto 122:f9eeca106725 8866 #define HRTIM_SET2R_MSTCMP4_Msk (0x1U << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8867 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
Kojto 122:f9eeca106725 8868
Kojto 122:f9eeca106725 8869 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
Kojto 122:f9eeca106725 8870 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1U << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8871 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
Kojto 122:f9eeca106725 8872 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
Kojto 122:f9eeca106725 8873 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1U << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8874 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
Kojto 122:f9eeca106725 8875 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
Kojto 122:f9eeca106725 8876 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1U << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8877 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
Kojto 122:f9eeca106725 8878 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
Kojto 122:f9eeca106725 8879 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1U << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8880 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
Kojto 122:f9eeca106725 8881 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
Kojto 122:f9eeca106725 8882 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1U << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8883 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
Kojto 122:f9eeca106725 8884 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
Kojto 122:f9eeca106725 8885 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1U << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8886 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
Kojto 122:f9eeca106725 8887 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
Kojto 122:f9eeca106725 8888 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1U << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8889 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
Kojto 122:f9eeca106725 8890 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
Kojto 122:f9eeca106725 8891 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1U << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8892 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
Kojto 122:f9eeca106725 8893 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
Kojto 122:f9eeca106725 8894 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1U << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8895 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
Kojto 122:f9eeca106725 8896
Kojto 122:f9eeca106725 8897 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
Kojto 122:f9eeca106725 8898 #define HRTIM_SET2R_EXTVNT1_Msk (0x1U << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8899 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
Kojto 122:f9eeca106725 8900 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
Kojto 122:f9eeca106725 8901 #define HRTIM_SET2R_EXTVNT2_Msk (0x1U << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8902 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
Kojto 122:f9eeca106725 8903 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
Kojto 122:f9eeca106725 8904 #define HRTIM_SET2R_EXTVNT3_Msk (0x1U << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8905 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
Kojto 122:f9eeca106725 8906 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
Kojto 122:f9eeca106725 8907 #define HRTIM_SET2R_EXTVNT4_Msk (0x1U << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8908 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
Kojto 122:f9eeca106725 8909 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
Kojto 122:f9eeca106725 8910 #define HRTIM_SET2R_EXTVNT5_Msk (0x1U << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8911 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
Kojto 122:f9eeca106725 8912 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
Kojto 122:f9eeca106725 8913 #define HRTIM_SET2R_EXTVNT6_Msk (0x1U << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8914 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
Kojto 122:f9eeca106725 8915 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
Kojto 122:f9eeca106725 8916 #define HRTIM_SET2R_EXTVNT7_Msk (0x1U << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8917 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
Kojto 122:f9eeca106725 8918 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
Kojto 122:f9eeca106725 8919 #define HRTIM_SET2R_EXTVNT8_Msk (0x1U << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8920 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
Kojto 122:f9eeca106725 8921 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
Kojto 122:f9eeca106725 8922 #define HRTIM_SET2R_EXTVNT9_Msk (0x1U << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8923 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
Kojto 122:f9eeca106725 8924 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
Kojto 122:f9eeca106725 8925 #define HRTIM_SET2R_EXTVNT10_Msk (0x1U << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8926 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
Kojto 122:f9eeca106725 8927
Kojto 122:f9eeca106725 8928 #define HRTIM_SET2R_UPDATE_Pos (31U)
Kojto 122:f9eeca106725 8929 #define HRTIM_SET2R_UPDATE_Msk (0x1U << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8930 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
bogdanm 86:04dd9b1680ae 8931
bogdanm 86:04dd9b1680ae 8932 /**** Bit definition for Slave Output 2 reset register ************************/
Kojto 122:f9eeca106725 8933 #define HRTIM_RST2R_SRT_Pos (0U)
Kojto 122:f9eeca106725 8934 #define HRTIM_RST2R_SRT_Msk (0x1U << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8935 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
Kojto 122:f9eeca106725 8936 #define HRTIM_RST2R_RESYNC_Pos (1U)
Kojto 122:f9eeca106725 8937 #define HRTIM_RST2R_RESYNC_Msk (0x1U << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8938 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
Kojto 122:f9eeca106725 8939 #define HRTIM_RST2R_PER_Pos (2U)
Kojto 122:f9eeca106725 8940 #define HRTIM_RST2R_PER_Msk (0x1U << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8941 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
Kojto 122:f9eeca106725 8942 #define HRTIM_RST2R_CMP1_Pos (3U)
Kojto 122:f9eeca106725 8943 #define HRTIM_RST2R_CMP1_Msk (0x1U << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8944 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 8945 #define HRTIM_RST2R_CMP2_Pos (4U)
Kojto 122:f9eeca106725 8946 #define HRTIM_RST2R_CMP2_Msk (0x1U << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8947 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 8948 #define HRTIM_RST2R_CMP3_Pos (5U)
Kojto 122:f9eeca106725 8949 #define HRTIM_RST2R_CMP3_Msk (0x1U << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8950 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
Kojto 122:f9eeca106725 8951 #define HRTIM_RST2R_CMP4_Pos (6U)
Kojto 122:f9eeca106725 8952 #define HRTIM_RST2R_CMP4_Msk (0x1U << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8953 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
Kojto 122:f9eeca106725 8954
Kojto 122:f9eeca106725 8955 #define HRTIM_RST2R_MSTPER_Pos (7U)
Kojto 122:f9eeca106725 8956 #define HRTIM_RST2R_MSTPER_Msk (0x1U << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8957 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
Kojto 122:f9eeca106725 8958 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
Kojto 122:f9eeca106725 8959 #define HRTIM_RST2R_MSTCMP1_Msk (0x1U << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8960 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
Kojto 122:f9eeca106725 8961 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
Kojto 122:f9eeca106725 8962 #define HRTIM_RST2R_MSTCMP2_Msk (0x1U << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8963 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
Kojto 122:f9eeca106725 8964 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
Kojto 122:f9eeca106725 8965 #define HRTIM_RST2R_MSTCMP3_Msk (0x1U << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8966 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
Kojto 122:f9eeca106725 8967 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
Kojto 122:f9eeca106725 8968 #define HRTIM_RST2R_MSTCMP4_Msk (0x1U << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8969 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
Kojto 122:f9eeca106725 8970
Kojto 122:f9eeca106725 8971 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
Kojto 122:f9eeca106725 8972 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1U << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8973 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
Kojto 122:f9eeca106725 8974 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
Kojto 122:f9eeca106725 8975 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1U << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8976 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
Kojto 122:f9eeca106725 8977 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
Kojto 122:f9eeca106725 8978 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1U << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8979 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
Kojto 122:f9eeca106725 8980 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
Kojto 122:f9eeca106725 8981 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1U << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8982 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
Kojto 122:f9eeca106725 8983 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
Kojto 122:f9eeca106725 8984 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1U << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8985 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
Kojto 122:f9eeca106725 8986 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
Kojto 122:f9eeca106725 8987 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1U << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8988 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
Kojto 122:f9eeca106725 8989 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
Kojto 122:f9eeca106725 8990 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1U << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8991 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
Kojto 122:f9eeca106725 8992 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
Kojto 122:f9eeca106725 8993 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1U << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8994 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
Kojto 122:f9eeca106725 8995 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
Kojto 122:f9eeca106725 8996 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1U << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8997 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
Kojto 122:f9eeca106725 8998
Kojto 122:f9eeca106725 8999 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
Kojto 122:f9eeca106725 9000 #define HRTIM_RST2R_EXTVNT1_Msk (0x1U << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9001 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
Kojto 122:f9eeca106725 9002 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
Kojto 122:f9eeca106725 9003 #define HRTIM_RST2R_EXTVNT2_Msk (0x1U << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9004 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
Kojto 122:f9eeca106725 9005 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
Kojto 122:f9eeca106725 9006 #define HRTIM_RST2R_EXTVNT3_Msk (0x1U << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9007 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
Kojto 122:f9eeca106725 9008 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
Kojto 122:f9eeca106725 9009 #define HRTIM_RST2R_EXTVNT4_Msk (0x1U << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9010 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
Kojto 122:f9eeca106725 9011 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
Kojto 122:f9eeca106725 9012 #define HRTIM_RST2R_EXTVNT5_Msk (0x1U << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9013 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
Kojto 122:f9eeca106725 9014 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
Kojto 122:f9eeca106725 9015 #define HRTIM_RST2R_EXTVNT6_Msk (0x1U << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9016 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
Kojto 122:f9eeca106725 9017 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
Kojto 122:f9eeca106725 9018 #define HRTIM_RST2R_EXTVNT7_Msk (0x1U << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9019 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
Kojto 122:f9eeca106725 9020 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
Kojto 122:f9eeca106725 9021 #define HRTIM_RST2R_EXTVNT8_Msk (0x1U << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9022 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
Kojto 122:f9eeca106725 9023 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
Kojto 122:f9eeca106725 9024 #define HRTIM_RST2R_EXTVNT9_Msk (0x1U << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9025 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
Kojto 122:f9eeca106725 9026 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
Kojto 122:f9eeca106725 9027 #define HRTIM_RST2R_EXTVNT10_Msk (0x1U << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9028 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
Kojto 122:f9eeca106725 9029
Kojto 122:f9eeca106725 9030 #define HRTIM_RST2R_UPDATE_Pos (31U)
Kojto 122:f9eeca106725 9031 #define HRTIM_RST2R_UPDATE_Msk (0x1U << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9032 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
bogdanm 86:04dd9b1680ae 9033
bogdanm 86:04dd9b1680ae 9034 /**** Bit definition for Slave external event filtering register 1 ***********/
Kojto 122:f9eeca106725 9035 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
Kojto 122:f9eeca106725 9036 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1U << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9037 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
Kojto 122:f9eeca106725 9038 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
Kojto 122:f9eeca106725 9039 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFU << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
Kojto 122:f9eeca106725 9040 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
Kojto 122:f9eeca106725 9041 #define HRTIM_EEFR1_EE1FLTR_0 (0x1U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9042 #define HRTIM_EEFR1_EE1FLTR_1 (0x2U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9043 #define HRTIM_EEFR1_EE1FLTR_2 (0x4U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9044 #define HRTIM_EEFR1_EE1FLTR_3 (0x8U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9045
Kojto 122:f9eeca106725 9046 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
Kojto 122:f9eeca106725 9047 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1U << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9048 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
Kojto 122:f9eeca106725 9049 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
Kojto 122:f9eeca106725 9050 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFU << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
Kojto 122:f9eeca106725 9051 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
Kojto 122:f9eeca106725 9052 #define HRTIM_EEFR1_EE2FLTR_0 (0x1U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9053 #define HRTIM_EEFR1_EE2FLTR_1 (0x2U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9054 #define HRTIM_EEFR1_EE2FLTR_2 (0x4U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9055 #define HRTIM_EEFR1_EE2FLTR_3 (0x8U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9056
Kojto 122:f9eeca106725 9057 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
Kojto 122:f9eeca106725 9058 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1U << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9059 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
Kojto 122:f9eeca106725 9060 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
Kojto 122:f9eeca106725 9061 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFU << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
Kojto 122:f9eeca106725 9062 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
Kojto 122:f9eeca106725 9063 #define HRTIM_EEFR1_EE3FLTR_0 (0x1U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9064 #define HRTIM_EEFR1_EE3FLTR_1 (0x2U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9065 #define HRTIM_EEFR1_EE3FLTR_2 (0x4U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9066 #define HRTIM_EEFR1_EE3FLTR_3 (0x8U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9067
Kojto 122:f9eeca106725 9068 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
Kojto 122:f9eeca106725 9069 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1U << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9070 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
Kojto 122:f9eeca106725 9071 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
Kojto 122:f9eeca106725 9072 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFU << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
Kojto 122:f9eeca106725 9073 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
Kojto 122:f9eeca106725 9074 #define HRTIM_EEFR1_EE4FLTR_0 (0x1U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9075 #define HRTIM_EEFR1_EE4FLTR_1 (0x2U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9076 #define HRTIM_EEFR1_EE4FLTR_2 (0x4U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9077 #define HRTIM_EEFR1_EE4FLTR_3 (0x8U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9078
Kojto 122:f9eeca106725 9079 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
Kojto 122:f9eeca106725 9080 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1U << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9081 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
Kojto 122:f9eeca106725 9082 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
Kojto 122:f9eeca106725 9083 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFU << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
Kojto 122:f9eeca106725 9084 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
Kojto 122:f9eeca106725 9085 #define HRTIM_EEFR1_EE5FLTR_0 (0x1U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9086 #define HRTIM_EEFR1_EE5FLTR_1 (0x2U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9087 #define HRTIM_EEFR1_EE5FLTR_2 (0x4U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9088 #define HRTIM_EEFR1_EE5FLTR_3 (0x8U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
bogdanm 86:04dd9b1680ae 9089
bogdanm 86:04dd9b1680ae 9090 /**** Bit definition for Slave external event filtering register 2 ***********/
Kojto 122:f9eeca106725 9091 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
Kojto 122:f9eeca106725 9092 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1U << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9093 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
Kojto 122:f9eeca106725 9094 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
Kojto 122:f9eeca106725 9095 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFU << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
Kojto 122:f9eeca106725 9096 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
Kojto 122:f9eeca106725 9097 #define HRTIM_EEFR2_EE6FLTR_0 (0x1U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9098 #define HRTIM_EEFR2_EE6FLTR_1 (0x2U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9099 #define HRTIM_EEFR2_EE6FLTR_2 (0x4U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9100 #define HRTIM_EEFR2_EE6FLTR_3 (0x8U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9101
Kojto 122:f9eeca106725 9102 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
Kojto 122:f9eeca106725 9103 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1U << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9104 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
Kojto 122:f9eeca106725 9105 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
Kojto 122:f9eeca106725 9106 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFU << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
Kojto 122:f9eeca106725 9107 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
Kojto 122:f9eeca106725 9108 #define HRTIM_EEFR2_EE7FLTR_0 (0x1U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9109 #define HRTIM_EEFR2_EE7FLTR_1 (0x2U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9110 #define HRTIM_EEFR2_EE7FLTR_2 (0x4U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9111 #define HRTIM_EEFR2_EE7FLTR_3 (0x8U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9112
Kojto 122:f9eeca106725 9113 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
Kojto 122:f9eeca106725 9114 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1U << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9115 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
Kojto 122:f9eeca106725 9116 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
Kojto 122:f9eeca106725 9117 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFU << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
Kojto 122:f9eeca106725 9118 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
Kojto 122:f9eeca106725 9119 #define HRTIM_EEFR2_EE8FLTR_0 (0x1U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9120 #define HRTIM_EEFR2_EE8FLTR_1 (0x2U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9121 #define HRTIM_EEFR2_EE8FLTR_2 (0x4U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9122 #define HRTIM_EEFR2_EE8FLTR_3 (0x8U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9123
Kojto 122:f9eeca106725 9124 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
Kojto 122:f9eeca106725 9125 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1U << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9126 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
Kojto 122:f9eeca106725 9127 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
Kojto 122:f9eeca106725 9128 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFU << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
Kojto 122:f9eeca106725 9129 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
Kojto 122:f9eeca106725 9130 #define HRTIM_EEFR2_EE9FLTR_0 (0x1U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9131 #define HRTIM_EEFR2_EE9FLTR_1 (0x2U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9132 #define HRTIM_EEFR2_EE9FLTR_2 (0x4U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9133 #define HRTIM_EEFR2_EE9FLTR_3 (0x8U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9134
Kojto 122:f9eeca106725 9135 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
Kojto 122:f9eeca106725 9136 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1U << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9137 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
Kojto 122:f9eeca106725 9138 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
Kojto 122:f9eeca106725 9139 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFU << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
Kojto 122:f9eeca106725 9140 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
Kojto 122:f9eeca106725 9141 #define HRTIM_EEFR2_EE10FLTR_0 (0x1U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9142 #define HRTIM_EEFR2_EE10FLTR_1 (0x2U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9143 #define HRTIM_EEFR2_EE10FLTR_2 (0x4U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9144 #define HRTIM_EEFR2_EE10FLTR_3 (0x8U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
bogdanm 86:04dd9b1680ae 9145
bogdanm 86:04dd9b1680ae 9146 /**** Bit definition for Slave Timer reset register ***************************/
Kojto 122:f9eeca106725 9147 #define HRTIM_RSTR_UPDATE_Pos (1U)
Kojto 122:f9eeca106725 9148 #define HRTIM_RSTR_UPDATE_Msk (0x1U << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9149 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
Kojto 122:f9eeca106725 9150 #define HRTIM_RSTR_CMP2_Pos (2U)
Kojto 122:f9eeca106725 9151 #define HRTIM_RSTR_CMP2_Msk (0x1U << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9152 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
Kojto 122:f9eeca106725 9153 #define HRTIM_RSTR_CMP4_Pos (3U)
Kojto 122:f9eeca106725 9154 #define HRTIM_RSTR_CMP4_Msk (0x1U << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9155 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
Kojto 122:f9eeca106725 9156
Kojto 122:f9eeca106725 9157 #define HRTIM_RSTR_MSTPER_Pos (4U)
Kojto 122:f9eeca106725 9158 #define HRTIM_RSTR_MSTPER_Msk (0x1U << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9159 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
Kojto 122:f9eeca106725 9160 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
Kojto 122:f9eeca106725 9161 #define HRTIM_RSTR_MSTCMP1_Msk (0x1U << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9162 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
Kojto 122:f9eeca106725 9163 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
Kojto 122:f9eeca106725 9164 #define HRTIM_RSTR_MSTCMP2_Msk (0x1U << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9165 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
Kojto 122:f9eeca106725 9166 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
Kojto 122:f9eeca106725 9167 #define HRTIM_RSTR_MSTCMP3_Msk (0x1U << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9168 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
Kojto 122:f9eeca106725 9169 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
Kojto 122:f9eeca106725 9170 #define HRTIM_RSTR_MSTCMP4_Msk (0x1U << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9171 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
Kojto 122:f9eeca106725 9172
Kojto 122:f9eeca106725 9173 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
Kojto 122:f9eeca106725 9174 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1U << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9175 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
Kojto 122:f9eeca106725 9176 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
Kojto 122:f9eeca106725 9177 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1U << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9178 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
Kojto 122:f9eeca106725 9179 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
Kojto 122:f9eeca106725 9180 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1U << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9181 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
Kojto 122:f9eeca106725 9182 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
Kojto 122:f9eeca106725 9183 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1U << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9184 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
Kojto 122:f9eeca106725 9185 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
Kojto 122:f9eeca106725 9186 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1U << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9187 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
Kojto 122:f9eeca106725 9188 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
Kojto 122:f9eeca106725 9189 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1U << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9190 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
Kojto 122:f9eeca106725 9191 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
Kojto 122:f9eeca106725 9192 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1U << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9193 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
Kojto 122:f9eeca106725 9194 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
Kojto 122:f9eeca106725 9195 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1U << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9196 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
Kojto 122:f9eeca106725 9197 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
Kojto 122:f9eeca106725 9198 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1U << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9199 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
Kojto 122:f9eeca106725 9200 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
Kojto 122:f9eeca106725 9201 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1U << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9202 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
Kojto 122:f9eeca106725 9203
Kojto 122:f9eeca106725 9204 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
Kojto 122:f9eeca106725 9205 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1U << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9206 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
Kojto 122:f9eeca106725 9207 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
Kojto 122:f9eeca106725 9208 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1U << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9209 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
Kojto 122:f9eeca106725 9210 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
Kojto 122:f9eeca106725 9211 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1U << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9212 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
Kojto 122:f9eeca106725 9213
Kojto 122:f9eeca106725 9214 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
Kojto 122:f9eeca106725 9215 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1U << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9216 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
Kojto 122:f9eeca106725 9217 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
Kojto 122:f9eeca106725 9218 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1U << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9219 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
Kojto 122:f9eeca106725 9220 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
Kojto 122:f9eeca106725 9221 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1U << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9222 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
Kojto 122:f9eeca106725 9223
Kojto 122:f9eeca106725 9224 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
Kojto 122:f9eeca106725 9225 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1U << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9226 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
Kojto 122:f9eeca106725 9227 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
Kojto 122:f9eeca106725 9228 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1U << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9229 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
Kojto 122:f9eeca106725 9230 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
Kojto 122:f9eeca106725 9231 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1U << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9232 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
Kojto 122:f9eeca106725 9233
Kojto 122:f9eeca106725 9234 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
Kojto 122:f9eeca106725 9235 #define HRTIM_RSTR_TIMECMP1_Msk (0x1U << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9236 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
Kojto 122:f9eeca106725 9237 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
Kojto 122:f9eeca106725 9238 #define HRTIM_RSTR_TIMECMP2_Msk (0x1U << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9239 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
Kojto 122:f9eeca106725 9240 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
Kojto 122:f9eeca106725 9241 #define HRTIM_RSTR_TIMECMP4_Msk (0x1U << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9242 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
bogdanm 86:04dd9b1680ae 9243
bogdanm 86:04dd9b1680ae 9244 /**** Bit definition for Slave Timer Chopper register *************************/
Kojto 122:f9eeca106725 9245 #define HRTIM_CHPR_CARFRQ_Pos (0U)
Kojto 122:f9eeca106725 9246 #define HRTIM_CHPR_CARFRQ_Msk (0xFU << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9247 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
Kojto 122:f9eeca106725 9248 #define HRTIM_CHPR_CARFRQ_0 (0x1U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9249 #define HRTIM_CHPR_CARFRQ_1 (0x2U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9250 #define HRTIM_CHPR_CARFRQ_2 (0x4U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9251 #define HRTIM_CHPR_CARFRQ_3 (0x8U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9252
Kojto 122:f9eeca106725 9253 #define HRTIM_CHPR_CARDTY_Pos (4U)
Kojto 122:f9eeca106725 9254 #define HRTIM_CHPR_CARDTY_Msk (0x7U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 9255 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
Kojto 122:f9eeca106725 9256 #define HRTIM_CHPR_CARDTY_0 (0x1U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9257 #define HRTIM_CHPR_CARDTY_1 (0x2U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9258 #define HRTIM_CHPR_CARDTY_2 (0x4U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9259
Kojto 122:f9eeca106725 9260 #define HRTIM_CHPR_STRPW_Pos (7U)
Kojto 122:f9eeca106725 9261 #define HRTIM_CHPR_STRPW_Msk (0xFU << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
Kojto 122:f9eeca106725 9262 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
Kojto 122:f9eeca106725 9263 #define HRTIM_CHPR_STRPW_0 (0x1U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9264 #define HRTIM_CHPR_STRPW_1 (0x2U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9265 #define HRTIM_CHPR_STRPW_2 (0x4U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9266 #define HRTIM_CHPR_STRPW_3 (0x8U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
bogdanm 86:04dd9b1680ae 9267
bogdanm 86:04dd9b1680ae 9268 /**** Bit definition for Slave Timer Capture 1 control register ***************/
Kojto 122:f9eeca106725 9269 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
Kojto 122:f9eeca106725 9270 #define HRTIM_CPT1CR_SWCPT_Msk (0x1U << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9271 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
Kojto 122:f9eeca106725 9272 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
Kojto 122:f9eeca106725 9273 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1U << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9274 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
Kojto 122:f9eeca106725 9275 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
Kojto 122:f9eeca106725 9276 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9277 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
Kojto 122:f9eeca106725 9278 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
Kojto 122:f9eeca106725 9279 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9280 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
Kojto 122:f9eeca106725 9281 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
Kojto 122:f9eeca106725 9282 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9283 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
Kojto 122:f9eeca106725 9284 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
Kojto 122:f9eeca106725 9285 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9286 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
Kojto 122:f9eeca106725 9287 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
Kojto 122:f9eeca106725 9288 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9289 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
Kojto 122:f9eeca106725 9290 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
Kojto 122:f9eeca106725 9291 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9292 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
Kojto 122:f9eeca106725 9293 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
Kojto 122:f9eeca106725 9294 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9295 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
Kojto 122:f9eeca106725 9296 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
Kojto 122:f9eeca106725 9297 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9298 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
Kojto 122:f9eeca106725 9299 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
Kojto 122:f9eeca106725 9300 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9301 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
Kojto 122:f9eeca106725 9302 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
Kojto 122:f9eeca106725 9303 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9304 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
Kojto 122:f9eeca106725 9305
Kojto 122:f9eeca106725 9306 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
Kojto 122:f9eeca106725 9307 #define HRTIM_CPT1CR_TA1SET_Msk (0x1U << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9308 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
Kojto 122:f9eeca106725 9309 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
Kojto 122:f9eeca106725 9310 #define HRTIM_CPT1CR_TA1RST_Msk (0x1U << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9311 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
Kojto 122:f9eeca106725 9312 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
Kojto 122:f9eeca106725 9313 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1U << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9314 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 9315 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
Kojto 122:f9eeca106725 9316 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1U << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9317 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 9318
Kojto 122:f9eeca106725 9319 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
Kojto 122:f9eeca106725 9320 #define HRTIM_CPT1CR_TB1SET_Msk (0x1U << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9321 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
Kojto 122:f9eeca106725 9322 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
Kojto 122:f9eeca106725 9323 #define HRTIM_CPT1CR_TB1RST_Msk (0x1U << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9324 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
Kojto 122:f9eeca106725 9325 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
Kojto 122:f9eeca106725 9326 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9327 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
Kojto 122:f9eeca106725 9328 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
Kojto 122:f9eeca106725 9329 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9330 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
Kojto 122:f9eeca106725 9331
Kojto 122:f9eeca106725 9332 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
Kojto 122:f9eeca106725 9333 #define HRTIM_CPT1CR_TC1SET_Msk (0x1U << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9334 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
Kojto 122:f9eeca106725 9335 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
Kojto 122:f9eeca106725 9336 #define HRTIM_CPT1CR_TC1RST_Msk (0x1U << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9337 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
Kojto 122:f9eeca106725 9338 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
Kojto 122:f9eeca106725 9339 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9340 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
Kojto 122:f9eeca106725 9341 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
Kojto 122:f9eeca106725 9342 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9343 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
Kojto 122:f9eeca106725 9344
Kojto 122:f9eeca106725 9345 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
Kojto 122:f9eeca106725 9346 #define HRTIM_CPT1CR_TD1SET_Msk (0x1U << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9347 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
Kojto 122:f9eeca106725 9348 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
Kojto 122:f9eeca106725 9349 #define HRTIM_CPT1CR_TD1RST_Msk (0x1U << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9350 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
Kojto 122:f9eeca106725 9351 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
Kojto 122:f9eeca106725 9352 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9353 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
Kojto 122:f9eeca106725 9354 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
Kojto 122:f9eeca106725 9355 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9356 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
Kojto 122:f9eeca106725 9357
Kojto 122:f9eeca106725 9358 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
Kojto 122:f9eeca106725 9359 #define HRTIM_CPT1CR_TE1SET_Msk (0x1U << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9360 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
Kojto 122:f9eeca106725 9361 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
Kojto 122:f9eeca106725 9362 #define HRTIM_CPT1CR_TE1RST_Msk (0x1U << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9363 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
Kojto 122:f9eeca106725 9364 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
Kojto 122:f9eeca106725 9365 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1U << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9366 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
Kojto 122:f9eeca106725 9367 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
Kojto 122:f9eeca106725 9368 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1U << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9369 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
bogdanm 86:04dd9b1680ae 9370
bogdanm 86:04dd9b1680ae 9371 /**** Bit definition for Slave Timer Capture 2 control register ***************/
Kojto 122:f9eeca106725 9372 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
Kojto 122:f9eeca106725 9373 #define HRTIM_CPT2CR_SWCPT_Msk (0x1U << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9374 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
Kojto 122:f9eeca106725 9375 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
Kojto 122:f9eeca106725 9376 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1U << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9377 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
Kojto 122:f9eeca106725 9378 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
Kojto 122:f9eeca106725 9379 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9380 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
Kojto 122:f9eeca106725 9381 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
Kojto 122:f9eeca106725 9382 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9383 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
Kojto 122:f9eeca106725 9384 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
Kojto 122:f9eeca106725 9385 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9386 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
Kojto 122:f9eeca106725 9387 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
Kojto 122:f9eeca106725 9388 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9389 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
Kojto 122:f9eeca106725 9390 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
Kojto 122:f9eeca106725 9391 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9392 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
Kojto 122:f9eeca106725 9393 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
Kojto 122:f9eeca106725 9394 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9395 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
Kojto 122:f9eeca106725 9396 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
Kojto 122:f9eeca106725 9397 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9398 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
Kojto 122:f9eeca106725 9399 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
Kojto 122:f9eeca106725 9400 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9401 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
Kojto 122:f9eeca106725 9402 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
Kojto 122:f9eeca106725 9403 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9404 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
Kojto 122:f9eeca106725 9405 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
Kojto 122:f9eeca106725 9406 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9407 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
Kojto 122:f9eeca106725 9408
Kojto 122:f9eeca106725 9409 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
Kojto 122:f9eeca106725 9410 #define HRTIM_CPT2CR_TA1SET_Msk (0x1U << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9411 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
Kojto 122:f9eeca106725 9412 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
Kojto 122:f9eeca106725 9413 #define HRTIM_CPT2CR_TA1RST_Msk (0x1U << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9414 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
Kojto 122:f9eeca106725 9415 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
Kojto 122:f9eeca106725 9416 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1U << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9417 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 9418 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
Kojto 122:f9eeca106725 9419 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1U << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9420 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 9421
Kojto 122:f9eeca106725 9422 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
Kojto 122:f9eeca106725 9423 #define HRTIM_CPT2CR_TB1SET_Msk (0x1U << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9424 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
Kojto 122:f9eeca106725 9425 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
Kojto 122:f9eeca106725 9426 #define HRTIM_CPT2CR_TB1RST_Msk (0x1U << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9427 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
Kojto 122:f9eeca106725 9428 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
Kojto 122:f9eeca106725 9429 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9430 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
Kojto 122:f9eeca106725 9431 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
Kojto 122:f9eeca106725 9432 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9433 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
Kojto 122:f9eeca106725 9434
Kojto 122:f9eeca106725 9435 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
Kojto 122:f9eeca106725 9436 #define HRTIM_CPT2CR_TC1SET_Msk (0x1U << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9437 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
Kojto 122:f9eeca106725 9438 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
Kojto 122:f9eeca106725 9439 #define HRTIM_CPT2CR_TC1RST_Msk (0x1U << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9440 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
Kojto 122:f9eeca106725 9441 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
Kojto 122:f9eeca106725 9442 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9443 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
Kojto 122:f9eeca106725 9444 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
Kojto 122:f9eeca106725 9445 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9446 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
Kojto 122:f9eeca106725 9447
Kojto 122:f9eeca106725 9448 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
Kojto 122:f9eeca106725 9449 #define HRTIM_CPT2CR_TD1SET_Msk (0x1U << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9450 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
Kojto 122:f9eeca106725 9451 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
Kojto 122:f9eeca106725 9452 #define HRTIM_CPT2CR_TD1RST_Msk (0x1U << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9453 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
Kojto 122:f9eeca106725 9454 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
Kojto 122:f9eeca106725 9455 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9456 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
Kojto 122:f9eeca106725 9457 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
Kojto 122:f9eeca106725 9458 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9459 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
Kojto 122:f9eeca106725 9460
Kojto 122:f9eeca106725 9461 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
Kojto 122:f9eeca106725 9462 #define HRTIM_CPT2CR_TE1SET_Msk (0x1U << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9463 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
Kojto 122:f9eeca106725 9464 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
Kojto 122:f9eeca106725 9465 #define HRTIM_CPT2CR_TE1RST_Msk (0x1U << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9466 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
Kojto 122:f9eeca106725 9467 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
Kojto 122:f9eeca106725 9468 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1U << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9469 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
Kojto 122:f9eeca106725 9470 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
Kojto 122:f9eeca106725 9471 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1U << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9472 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
bogdanm 86:04dd9b1680ae 9473
bogdanm 86:04dd9b1680ae 9474 /**** Bit definition for Slave Timer Output register **************************/
Kojto 122:f9eeca106725 9475 #define HRTIM_OUTR_POL1_Pos (1U)
Kojto 122:f9eeca106725 9476 #define HRTIM_OUTR_POL1_Msk (0x1U << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9477 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
Kojto 122:f9eeca106725 9478 #define HRTIM_OUTR_IDLM1_Pos (2U)
Kojto 122:f9eeca106725 9479 #define HRTIM_OUTR_IDLM1_Msk (0x1U << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9480 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
Kojto 122:f9eeca106725 9481 #define HRTIM_OUTR_IDLES1_Pos (3U)
Kojto 122:f9eeca106725 9482 #define HRTIM_OUTR_IDLES1_Msk (0x1U << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9483 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
Kojto 122:f9eeca106725 9484 #define HRTIM_OUTR_FAULT1_Pos (4U)
Kojto 122:f9eeca106725 9485 #define HRTIM_OUTR_FAULT1_Msk (0x3U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 9486 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
Kojto 122:f9eeca106725 9487 #define HRTIM_OUTR_FAULT1_0 (0x1U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9488 #define HRTIM_OUTR_FAULT1_1 (0x2U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9489 #define HRTIM_OUTR_CHP1_Pos (6U)
Kojto 122:f9eeca106725 9490 #define HRTIM_OUTR_CHP1_Msk (0x1U << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9491 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
Kojto 122:f9eeca106725 9492 #define HRTIM_OUTR_DIDL1_Pos (7U)
Kojto 122:f9eeca106725 9493 #define HRTIM_OUTR_DIDL1_Msk (0x1U << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9494 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
Kojto 122:f9eeca106725 9495
Kojto 122:f9eeca106725 9496 #define HRTIM_OUTR_DTEN_Pos (8U)
Kojto 122:f9eeca106725 9497 #define HRTIM_OUTR_DTEN_Msk (0x1U << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9498 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
Kojto 122:f9eeca106725 9499 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
Kojto 122:f9eeca106725 9500 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1U << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9501 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
Kojto 122:f9eeca106725 9502 #define HRTIM_OUTR_DLYPRT_Pos (10U)
Kojto 122:f9eeca106725 9503 #define HRTIM_OUTR_DLYPRT_Msk (0x7U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
Kojto 122:f9eeca106725 9504 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
Kojto 122:f9eeca106725 9505 #define HRTIM_OUTR_DLYPRT_0 (0x1U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9506 #define HRTIM_OUTR_DLYPRT_1 (0x2U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9507 #define HRTIM_OUTR_DLYPRT_2 (0x4U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9508
Kojto 122:f9eeca106725 9509 #define HRTIM_OUTR_POL2_Pos (17U)
Kojto 122:f9eeca106725 9510 #define HRTIM_OUTR_POL2_Msk (0x1U << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9511 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
Kojto 122:f9eeca106725 9512 #define HRTIM_OUTR_IDLM2_Pos (18U)
Kojto 122:f9eeca106725 9513 #define HRTIM_OUTR_IDLM2_Msk (0x1U << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9514 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
Kojto 122:f9eeca106725 9515 #define HRTIM_OUTR_IDLES2_Pos (19U)
Kojto 122:f9eeca106725 9516 #define HRTIM_OUTR_IDLES2_Msk (0x1U << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9517 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
Kojto 122:f9eeca106725 9518 #define HRTIM_OUTR_FAULT2_Pos (20U)
Kojto 122:f9eeca106725 9519 #define HRTIM_OUTR_FAULT2_Msk (0x3U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 9520 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
Kojto 122:f9eeca106725 9521 #define HRTIM_OUTR_FAULT2_0 (0x1U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9522 #define HRTIM_OUTR_FAULT2_1 (0x2U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9523 #define HRTIM_OUTR_CHP2_Pos (22U)
Kojto 122:f9eeca106725 9524 #define HRTIM_OUTR_CHP2_Msk (0x1U << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9525 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
Kojto 122:f9eeca106725 9526 #define HRTIM_OUTR_DIDL2_Pos (23U)
Kojto 122:f9eeca106725 9527 #define HRTIM_OUTR_DIDL2_Msk (0x1U << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9528 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
bogdanm 86:04dd9b1680ae 9529
bogdanm 86:04dd9b1680ae 9530 /**** Bit definition for Slave Timer Fault register ***************************/
Kojto 122:f9eeca106725 9531 #define HRTIM_FLTR_FLT1EN_Pos (0U)
Kojto 122:f9eeca106725 9532 #define HRTIM_FLTR_FLT1EN_Msk (0x1U << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9533 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
Kojto 122:f9eeca106725 9534 #define HRTIM_FLTR_FLT2EN_Pos (1U)
Kojto 122:f9eeca106725 9535 #define HRTIM_FLTR_FLT2EN_Msk (0x1U << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9536 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
Kojto 122:f9eeca106725 9537 #define HRTIM_FLTR_FLT3EN_Pos (2U)
Kojto 122:f9eeca106725 9538 #define HRTIM_FLTR_FLT3EN_Msk (0x1U << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9539 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
Kojto 122:f9eeca106725 9540 #define HRTIM_FLTR_FLT4EN_Pos (3U)
Kojto 122:f9eeca106725 9541 #define HRTIM_FLTR_FLT4EN_Msk (0x1U << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9542 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
Kojto 122:f9eeca106725 9543 #define HRTIM_FLTR_FLT5EN_Pos (4U)
Kojto 122:f9eeca106725 9544 #define HRTIM_FLTR_FLT5EN_Msk (0x1U << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9545 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
Kojto 122:f9eeca106725 9546 #define HRTIM_FLTR_FLTLCK_Pos (31U)
Kojto 122:f9eeca106725 9547 #define HRTIM_FLTR_FLTLCK_Msk (0x1U << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9548 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
bogdanm 86:04dd9b1680ae 9549
bogdanm 86:04dd9b1680ae 9550 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
Kojto 122:f9eeca106725 9551 #define HRTIM_CR1_MUDIS_Pos (0U)
Kojto 122:f9eeca106725 9552 #define HRTIM_CR1_MUDIS_Msk (0x1U << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9553 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
Kojto 122:f9eeca106725 9554 #define HRTIM_CR1_TAUDIS_Pos (1U)
Kojto 122:f9eeca106725 9555 #define HRTIM_CR1_TAUDIS_Msk (0x1U << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9556 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
Kojto 122:f9eeca106725 9557 #define HRTIM_CR1_TBUDIS_Pos (2U)
Kojto 122:f9eeca106725 9558 #define HRTIM_CR1_TBUDIS_Msk (0x1U << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9559 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
Kojto 122:f9eeca106725 9560 #define HRTIM_CR1_TCUDIS_Pos (3U)
Kojto 122:f9eeca106725 9561 #define HRTIM_CR1_TCUDIS_Msk (0x1U << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9562 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
Kojto 122:f9eeca106725 9563 #define HRTIM_CR1_TDUDIS_Pos (4U)
Kojto 122:f9eeca106725 9564 #define HRTIM_CR1_TDUDIS_Msk (0x1U << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9565 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
Kojto 122:f9eeca106725 9566 #define HRTIM_CR1_TEUDIS_Pos (5U)
Kojto 122:f9eeca106725 9567 #define HRTIM_CR1_TEUDIS_Msk (0x1U << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9568 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
Kojto 122:f9eeca106725 9569 #define HRTIM_CR1_ADC1USRC_Pos (16U)
Kojto 122:f9eeca106725 9570 #define HRTIM_CR1_ADC1USRC_Msk (0x7U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
Kojto 122:f9eeca106725 9571 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
Kojto 122:f9eeca106725 9572 #define HRTIM_CR1_ADC1USRC_0 (0x1U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9573 #define HRTIM_CR1_ADC1USRC_1 (0x2U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9574 #define HRTIM_CR1_ADC1USRC_2 (0x4U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9575 #define HRTIM_CR1_ADC2USRC_Pos (19U)
Kojto 122:f9eeca106725 9576 #define HRTIM_CR1_ADC2USRC_Msk (0x7U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
Kojto 122:f9eeca106725 9577 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
Kojto 122:f9eeca106725 9578 #define HRTIM_CR1_ADC2USRC_0 (0x1U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9579 #define HRTIM_CR1_ADC2USRC_1 (0x2U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9580 #define HRTIM_CR1_ADC2USRC_2 (0x4U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9581 #define HRTIM_CR1_ADC3USRC_Pos (22U)
Kojto 122:f9eeca106725 9582 #define HRTIM_CR1_ADC3USRC_Msk (0x7U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
Kojto 122:f9eeca106725 9583 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
Kojto 122:f9eeca106725 9584 #define HRTIM_CR1_ADC3USRC_0 (0x1U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9585 #define HRTIM_CR1_ADC3USRC_1 (0x2U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9586 #define HRTIM_CR1_ADC3USRC_2 (0x4U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9587 #define HRTIM_CR1_ADC4USRC_Pos (25U)
Kojto 122:f9eeca106725 9588 #define HRTIM_CR1_ADC4USRC_Msk (0x7U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
Kojto 122:f9eeca106725 9589 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
Kojto 122:f9eeca106725 9590 #define HRTIM_CR1_ADC4USRC_0 (0x1U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9591 #define HRTIM_CR1_ADC4USRC_1 (0x2U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9592 #define HRTIM_CR1_ADC4USRC_2 (0x0U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
bogdanm 86:04dd9b1680ae 9593
bogdanm 86:04dd9b1680ae 9594 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
Kojto 122:f9eeca106725 9595 #define HRTIM_CR2_MSWU_Pos (0U)
Kojto 122:f9eeca106725 9596 #define HRTIM_CR2_MSWU_Msk (0x1U << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9597 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
Kojto 122:f9eeca106725 9598 #define HRTIM_CR2_TASWU_Pos (1U)
Kojto 122:f9eeca106725 9599 #define HRTIM_CR2_TASWU_Msk (0x1U << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9600 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
Kojto 122:f9eeca106725 9601 #define HRTIM_CR2_TBSWU_Pos (2U)
Kojto 122:f9eeca106725 9602 #define HRTIM_CR2_TBSWU_Msk (0x1U << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9603 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
Kojto 122:f9eeca106725 9604 #define HRTIM_CR2_TCSWU_Pos (3U)
Kojto 122:f9eeca106725 9605 #define HRTIM_CR2_TCSWU_Msk (0x1U << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9606 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
Kojto 122:f9eeca106725 9607 #define HRTIM_CR2_TDSWU_Pos (4U)
Kojto 122:f9eeca106725 9608 #define HRTIM_CR2_TDSWU_Msk (0x1U << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9609 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
Kojto 122:f9eeca106725 9610 #define HRTIM_CR2_TESWU_Pos (5U)
Kojto 122:f9eeca106725 9611 #define HRTIM_CR2_TESWU_Msk (0x1U << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9612 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
Kojto 122:f9eeca106725 9613 #define HRTIM_CR2_MRST_Pos (8U)
Kojto 122:f9eeca106725 9614 #define HRTIM_CR2_MRST_Msk (0x1U << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9615 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
Kojto 122:f9eeca106725 9616 #define HRTIM_CR2_TARST_Pos (9U)
Kojto 122:f9eeca106725 9617 #define HRTIM_CR2_TARST_Msk (0x1U << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9618 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
Kojto 122:f9eeca106725 9619 #define HRTIM_CR2_TBRST_Pos (10U)
Kojto 122:f9eeca106725 9620 #define HRTIM_CR2_TBRST_Msk (0x1U << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9621 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
Kojto 122:f9eeca106725 9622 #define HRTIM_CR2_TCRST_Pos (11U)
Kojto 122:f9eeca106725 9623 #define HRTIM_CR2_TCRST_Msk (0x1U << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9624 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
Kojto 122:f9eeca106725 9625 #define HRTIM_CR2_TDRST_Pos (12U)
Kojto 122:f9eeca106725 9626 #define HRTIM_CR2_TDRST_Msk (0x1U << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9627 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
Kojto 122:f9eeca106725 9628 #define HRTIM_CR2_TERST_Pos (13U)
Kojto 122:f9eeca106725 9629 #define HRTIM_CR2_TERST_Msk (0x1U << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9630 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
bogdanm 86:04dd9b1680ae 9631
bogdanm 86:04dd9b1680ae 9632 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
Kojto 122:f9eeca106725 9633 #define HRTIM_ISR_FLT1_Pos (0U)
Kojto 122:f9eeca106725 9634 #define HRTIM_ISR_FLT1_Msk (0x1U << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9635 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
Kojto 122:f9eeca106725 9636 #define HRTIM_ISR_FLT2_Pos (1U)
Kojto 122:f9eeca106725 9637 #define HRTIM_ISR_FLT2_Msk (0x1U << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9638 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
Kojto 122:f9eeca106725 9639 #define HRTIM_ISR_FLT3_Pos (2U)
Kojto 122:f9eeca106725 9640 #define HRTIM_ISR_FLT3_Msk (0x1U << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9641 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
Kojto 122:f9eeca106725 9642 #define HRTIM_ISR_FLT4_Pos (3U)
Kojto 122:f9eeca106725 9643 #define HRTIM_ISR_FLT4_Msk (0x1U << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9644 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
Kojto 122:f9eeca106725 9645 #define HRTIM_ISR_FLT5_Pos (4U)
Kojto 122:f9eeca106725 9646 #define HRTIM_ISR_FLT5_Msk (0x1U << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9647 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
Kojto 122:f9eeca106725 9648 #define HRTIM_ISR_SYSFLT_Pos (5U)
Kojto 122:f9eeca106725 9649 #define HRTIM_ISR_SYSFLT_Msk (0x1U << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9650 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
Kojto 122:f9eeca106725 9651 #define HRTIM_ISR_DLLRDY_Pos (16U)
Kojto 122:f9eeca106725 9652 #define HRTIM_ISR_DLLRDY_Msk (0x1U << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9653 #define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */
Kojto 122:f9eeca106725 9654 #define HRTIM_ISR_BMPER_Pos (17U)
Kojto 122:f9eeca106725 9655 #define HRTIM_ISR_BMPER_Msk (0x1U << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9656 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
bogdanm 86:04dd9b1680ae 9657
bogdanm 86:04dd9b1680ae 9658 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
Kojto 122:f9eeca106725 9659 #define HRTIM_ICR_FLT1C_Pos (0U)
Kojto 122:f9eeca106725 9660 #define HRTIM_ICR_FLT1C_Msk (0x1U << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9661 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
Kojto 122:f9eeca106725 9662 #define HRTIM_ICR_FLT2C_Pos (1U)
Kojto 122:f9eeca106725 9663 #define HRTIM_ICR_FLT2C_Msk (0x1U << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9664 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
Kojto 122:f9eeca106725 9665 #define HRTIM_ICR_FLT3C_Pos (2U)
Kojto 122:f9eeca106725 9666 #define HRTIM_ICR_FLT3C_Msk (0x1U << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9667 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
Kojto 122:f9eeca106725 9668 #define HRTIM_ICR_FLT4C_Pos (3U)
Kojto 122:f9eeca106725 9669 #define HRTIM_ICR_FLT4C_Msk (0x1U << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9670 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
Kojto 122:f9eeca106725 9671 #define HRTIM_ICR_FLT5C_Pos (4U)
Kojto 122:f9eeca106725 9672 #define HRTIM_ICR_FLT5C_Msk (0x1U << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9673 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
Kojto 122:f9eeca106725 9674 #define HRTIM_ICR_SYSFLTC_Pos (5U)
Kojto 122:f9eeca106725 9675 #define HRTIM_ICR_SYSFLTC_Msk (0x1U << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9676 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
Kojto 122:f9eeca106725 9677 #define HRTIM_ICR_DLLRDYC_Pos (16U)
Kojto 122:f9eeca106725 9678 #define HRTIM_ICR_DLLRDYC_Msk (0x1U << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9679 #define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */
Kojto 122:f9eeca106725 9680 #define HRTIM_ICR_BMPERC_Pos (17U)
Kojto 122:f9eeca106725 9681 #define HRTIM_ICR_BMPERC_Msk (0x1U << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9682 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
bogdanm 86:04dd9b1680ae 9683
bogdanm 86:04dd9b1680ae 9684 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
Kojto 122:f9eeca106725 9685 #define HRTIM_IER_FLT1_Pos (0U)
Kojto 122:f9eeca106725 9686 #define HRTIM_IER_FLT1_Msk (0x1U << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9687 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
Kojto 122:f9eeca106725 9688 #define HRTIM_IER_FLT2_Pos (1U)
Kojto 122:f9eeca106725 9689 #define HRTIM_IER_FLT2_Msk (0x1U << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9690 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
Kojto 122:f9eeca106725 9691 #define HRTIM_IER_FLT3_Pos (2U)
Kojto 122:f9eeca106725 9692 #define HRTIM_IER_FLT3_Msk (0x1U << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9693 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
Kojto 122:f9eeca106725 9694 #define HRTIM_IER_FLT4_Pos (3U)
Kojto 122:f9eeca106725 9695 #define HRTIM_IER_FLT4_Msk (0x1U << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9696 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
Kojto 122:f9eeca106725 9697 #define HRTIM_IER_FLT5_Pos (4U)
Kojto 122:f9eeca106725 9698 #define HRTIM_IER_FLT5_Msk (0x1U << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9699 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
Kojto 122:f9eeca106725 9700 #define HRTIM_IER_SYSFLT_Pos (5U)
Kojto 122:f9eeca106725 9701 #define HRTIM_IER_SYSFLT_Msk (0x1U << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9702 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
Kojto 122:f9eeca106725 9703 #define HRTIM_IER_DLLRDY_Pos (16U)
Kojto 122:f9eeca106725 9704 #define HRTIM_IER_DLLRDY_Msk (0x1U << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9705 #define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */
Kojto 122:f9eeca106725 9706 #define HRTIM_IER_BMPER_Pos (17U)
Kojto 122:f9eeca106725 9707 #define HRTIM_IER_BMPER_Msk (0x1U << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9708 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
bogdanm 86:04dd9b1680ae 9709
bogdanm 86:04dd9b1680ae 9710 /**** Bit definition for Common HRTIM Timer output enable register ************/
Kojto 122:f9eeca106725 9711 #define HRTIM_OENR_TA1OEN_Pos (0U)
Kojto 122:f9eeca106725 9712 #define HRTIM_OENR_TA1OEN_Msk (0x1U << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9713 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
Kojto 122:f9eeca106725 9714 #define HRTIM_OENR_TA2OEN_Pos (1U)
Kojto 122:f9eeca106725 9715 #define HRTIM_OENR_TA2OEN_Msk (0x1U << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9716 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
Kojto 122:f9eeca106725 9717 #define HRTIM_OENR_TB1OEN_Pos (2U)
Kojto 122:f9eeca106725 9718 #define HRTIM_OENR_TB1OEN_Msk (0x1U << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9719 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
Kojto 122:f9eeca106725 9720 #define HRTIM_OENR_TB2OEN_Pos (3U)
Kojto 122:f9eeca106725 9721 #define HRTIM_OENR_TB2OEN_Msk (0x1U << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9722 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
Kojto 122:f9eeca106725 9723 #define HRTIM_OENR_TC1OEN_Pos (4U)
Kojto 122:f9eeca106725 9724 #define HRTIM_OENR_TC1OEN_Msk (0x1U << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9725 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
Kojto 122:f9eeca106725 9726 #define HRTIM_OENR_TC2OEN_Pos (5U)
Kojto 122:f9eeca106725 9727 #define HRTIM_OENR_TC2OEN_Msk (0x1U << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9728 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
Kojto 122:f9eeca106725 9729 #define HRTIM_OENR_TD1OEN_Pos (6U)
Kojto 122:f9eeca106725 9730 #define HRTIM_OENR_TD1OEN_Msk (0x1U << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9731 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
Kojto 122:f9eeca106725 9732 #define HRTIM_OENR_TD2OEN_Pos (7U)
Kojto 122:f9eeca106725 9733 #define HRTIM_OENR_TD2OEN_Msk (0x1U << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9734 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
Kojto 122:f9eeca106725 9735 #define HRTIM_OENR_TE1OEN_Pos (8U)
Kojto 122:f9eeca106725 9736 #define HRTIM_OENR_TE1OEN_Msk (0x1U << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9737 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
Kojto 122:f9eeca106725 9738 #define HRTIM_OENR_TE2OEN_Pos (9U)
Kojto 122:f9eeca106725 9739 #define HRTIM_OENR_TE2OEN_Msk (0x1U << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9740 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
bogdanm 86:04dd9b1680ae 9741
bogdanm 86:04dd9b1680ae 9742 /**** Bit definition for Common HRTIM Timer output disable register ***********/
Kojto 122:f9eeca106725 9743 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
Kojto 122:f9eeca106725 9744 #define HRTIM_ODISR_TA1ODIS_Msk (0x1U << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9745 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
Kojto 122:f9eeca106725 9746 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
Kojto 122:f9eeca106725 9747 #define HRTIM_ODISR_TA2ODIS_Msk (0x1U << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9748 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
Kojto 122:f9eeca106725 9749 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
Kojto 122:f9eeca106725 9750 #define HRTIM_ODISR_TB1ODIS_Msk (0x1U << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9751 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
Kojto 122:f9eeca106725 9752 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
Kojto 122:f9eeca106725 9753 #define HRTIM_ODISR_TB2ODIS_Msk (0x1U << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9754 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
Kojto 122:f9eeca106725 9755 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
Kojto 122:f9eeca106725 9756 #define HRTIM_ODISR_TC1ODIS_Msk (0x1U << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9757 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
Kojto 122:f9eeca106725 9758 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
Kojto 122:f9eeca106725 9759 #define HRTIM_ODISR_TC2ODIS_Msk (0x1U << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9760 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
Kojto 122:f9eeca106725 9761 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
Kojto 122:f9eeca106725 9762 #define HRTIM_ODISR_TD1ODIS_Msk (0x1U << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9763 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
Kojto 122:f9eeca106725 9764 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
Kojto 122:f9eeca106725 9765 #define HRTIM_ODISR_TD2ODIS_Msk (0x1U << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9766 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
Kojto 122:f9eeca106725 9767 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
Kojto 122:f9eeca106725 9768 #define HRTIM_ODISR_TE1ODIS_Msk (0x1U << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9769 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
Kojto 122:f9eeca106725 9770 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
Kojto 122:f9eeca106725 9771 #define HRTIM_ODISR_TE2ODIS_Msk (0x1U << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9772 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
bogdanm 86:04dd9b1680ae 9773
bogdanm 86:04dd9b1680ae 9774 /**** Bit definition for Common HRTIM Timer output disable status register *****/
Kojto 122:f9eeca106725 9775 #define HRTIM_ODSR_TA1ODS_Pos (0U)
Kojto 122:f9eeca106725 9776 #define HRTIM_ODSR_TA1ODS_Msk (0x1U << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9777 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
Kojto 122:f9eeca106725 9778 #define HRTIM_ODSR_TA2ODS_Pos (1U)
Kojto 122:f9eeca106725 9779 #define HRTIM_ODSR_TA2ODS_Msk (0x1U << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9780 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
Kojto 122:f9eeca106725 9781 #define HRTIM_ODSR_TB1ODS_Pos (2U)
Kojto 122:f9eeca106725 9782 #define HRTIM_ODSR_TB1ODS_Msk (0x1U << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9783 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
Kojto 122:f9eeca106725 9784 #define HRTIM_ODSR_TB2ODS_Pos (3U)
Kojto 122:f9eeca106725 9785 #define HRTIM_ODSR_TB2ODS_Msk (0x1U << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9786 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
Kojto 122:f9eeca106725 9787 #define HRTIM_ODSR_TC1ODS_Pos (4U)
Kojto 122:f9eeca106725 9788 #define HRTIM_ODSR_TC1ODS_Msk (0x1U << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9789 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
Kojto 122:f9eeca106725 9790 #define HRTIM_ODSR_TC2ODS_Pos (5U)
Kojto 122:f9eeca106725 9791 #define HRTIM_ODSR_TC2ODS_Msk (0x1U << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9792 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
Kojto 122:f9eeca106725 9793 #define HRTIM_ODSR_TD1ODS_Pos (6U)
Kojto 122:f9eeca106725 9794 #define HRTIM_ODSR_TD1ODS_Msk (0x1U << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9795 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
Kojto 122:f9eeca106725 9796 #define HRTIM_ODSR_TD2ODS_Pos (7U)
Kojto 122:f9eeca106725 9797 #define HRTIM_ODSR_TD2ODS_Msk (0x1U << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9798 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
Kojto 122:f9eeca106725 9799 #define HRTIM_ODSR_TE1ODS_Pos (8U)
Kojto 122:f9eeca106725 9800 #define HRTIM_ODSR_TE1ODS_Msk (0x1U << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9801 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
Kojto 122:f9eeca106725 9802 #define HRTIM_ODSR_TE2ODS_Pos (9U)
Kojto 122:f9eeca106725 9803 #define HRTIM_ODSR_TE2ODS_Msk (0x1U << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9804 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
bogdanm 86:04dd9b1680ae 9805
bogdanm 86:04dd9b1680ae 9806 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
Kojto 122:f9eeca106725 9807 #define HRTIM_BMCR_BME_Pos (0U)
Kojto 122:f9eeca106725 9808 #define HRTIM_BMCR_BME_Msk (0x1U << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9809 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
Kojto 122:f9eeca106725 9810 #define HRTIM_BMCR_BMOM_Pos (1U)
Kojto 122:f9eeca106725 9811 #define HRTIM_BMCR_BMOM_Msk (0x1U << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9812 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
Kojto 122:f9eeca106725 9813 #define HRTIM_BMCR_BMCLK_Pos (2U)
Kojto 122:f9eeca106725 9814 #define HRTIM_BMCR_BMCLK_Msk (0xFU << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
Kojto 122:f9eeca106725 9815 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
Kojto 122:f9eeca106725 9816 #define HRTIM_BMCR_BMCLK_0 (0x1U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9817 #define HRTIM_BMCR_BMCLK_1 (0x2U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9818 #define HRTIM_BMCR_BMCLK_2 (0x4U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9819 #define HRTIM_BMCR_BMCLK_3 (0x8U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9820 #define HRTIM_BMCR_BMPRSC_Pos (6U)
Kojto 122:f9eeca106725 9821 #define HRTIM_BMCR_BMPRSC_Msk (0xFU << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
Kojto 122:f9eeca106725 9822 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
Kojto 122:f9eeca106725 9823 #define HRTIM_BMCR_BMPRSC_0 (0x1U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9824 #define HRTIM_BMCR_BMPRSC_1 (0x2U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9825 #define HRTIM_BMCR_BMPRSC_2 (0x4U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9826 #define HRTIM_BMCR_BMPRSC_3 (0x8U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9827 #define HRTIM_BMCR_BMPREN_Pos (10U)
Kojto 122:f9eeca106725 9828 #define HRTIM_BMCR_BMPREN_Msk (0x1U << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9829 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
Kojto 122:f9eeca106725 9830 #define HRTIM_BMCR_MTBM_Pos (16U)
Kojto 122:f9eeca106725 9831 #define HRTIM_BMCR_MTBM_Msk (0x1U << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9832 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
Kojto 122:f9eeca106725 9833 #define HRTIM_BMCR_TABM_Pos (17U)
Kojto 122:f9eeca106725 9834 #define HRTIM_BMCR_TABM_Msk (0x1U << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9835 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
Kojto 122:f9eeca106725 9836 #define HRTIM_BMCR_TBBM_Pos (18U)
Kojto 122:f9eeca106725 9837 #define HRTIM_BMCR_TBBM_Msk (0x1U << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9838 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
Kojto 122:f9eeca106725 9839 #define HRTIM_BMCR_TCBM_Pos (19U)
Kojto 122:f9eeca106725 9840 #define HRTIM_BMCR_TCBM_Msk (0x1U << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9841 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
Kojto 122:f9eeca106725 9842 #define HRTIM_BMCR_TDBM_Pos (20U)
Kojto 122:f9eeca106725 9843 #define HRTIM_BMCR_TDBM_Msk (0x1U << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9844 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
Kojto 122:f9eeca106725 9845 #define HRTIM_BMCR_TEBM_Pos (21U)
Kojto 122:f9eeca106725 9846 #define HRTIM_BMCR_TEBM_Msk (0x1U << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9847 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
Kojto 122:f9eeca106725 9848 #define HRTIM_BMCR_BMSTAT_Pos (31U)
Kojto 122:f9eeca106725 9849 #define HRTIM_BMCR_BMSTAT_Msk (0x1U << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9850 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
bogdanm 86:04dd9b1680ae 9851
bogdanm 86:04dd9b1680ae 9852 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
Kojto 122:f9eeca106725 9853 #define HRTIM_BMTRGR_SW_Pos (0U)
Kojto 122:f9eeca106725 9854 #define HRTIM_BMTRGR_SW_Msk (0x1U << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9855 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
Kojto 122:f9eeca106725 9856 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
Kojto 122:f9eeca106725 9857 #define HRTIM_BMTRGR_MSTRST_Msk (0x1U << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9858 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
Kojto 122:f9eeca106725 9859 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
Kojto 122:f9eeca106725 9860 #define HRTIM_BMTRGR_MSTREP_Msk (0x1U << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9861 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
Kojto 122:f9eeca106725 9862 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
Kojto 122:f9eeca106725 9863 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1U << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9864 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
Kojto 122:f9eeca106725 9865 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
Kojto 122:f9eeca106725 9866 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1U << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9867 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
Kojto 122:f9eeca106725 9868 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
Kojto 122:f9eeca106725 9869 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1U << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9870 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
Kojto 122:f9eeca106725 9871 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
Kojto 122:f9eeca106725 9872 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1U << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9873 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
Kojto 122:f9eeca106725 9874 #define HRTIM_BMTRGR_TARST_Pos (7U)
Kojto 122:f9eeca106725 9875 #define HRTIM_BMTRGR_TARST_Msk (0x1U << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9876 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
Kojto 122:f9eeca106725 9877 #define HRTIM_BMTRGR_TAREP_Pos (8U)
Kojto 122:f9eeca106725 9878 #define HRTIM_BMTRGR_TAREP_Msk (0x1U << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9879 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
Kojto 122:f9eeca106725 9880 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
Kojto 122:f9eeca106725 9881 #define HRTIM_BMTRGR_TACMP1_Msk (0x1U << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9882 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
Kojto 122:f9eeca106725 9883 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
Kojto 122:f9eeca106725 9884 #define HRTIM_BMTRGR_TACMP2_Msk (0x1U << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9885 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
Kojto 122:f9eeca106725 9886 #define HRTIM_BMTRGR_TBRST_Pos (11U)
Kojto 122:f9eeca106725 9887 #define HRTIM_BMTRGR_TBRST_Msk (0x1U << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9888 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
Kojto 122:f9eeca106725 9889 #define HRTIM_BMTRGR_TBREP_Pos (12U)
Kojto 122:f9eeca106725 9890 #define HRTIM_BMTRGR_TBREP_Msk (0x1U << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9891 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
Kojto 122:f9eeca106725 9892 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
Kojto 122:f9eeca106725 9893 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1U << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9894 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
Kojto 122:f9eeca106725 9895 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
Kojto 122:f9eeca106725 9896 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1U << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9897 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
Kojto 122:f9eeca106725 9898 #define HRTIM_BMTRGR_TCRST_Pos (15U)
Kojto 122:f9eeca106725 9899 #define HRTIM_BMTRGR_TCRST_Msk (0x1U << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9900 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
Kojto 122:f9eeca106725 9901 #define HRTIM_BMTRGR_TCREP_Pos (16U)
Kojto 122:f9eeca106725 9902 #define HRTIM_BMTRGR_TCREP_Msk (0x1U << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9903 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
Kojto 122:f9eeca106725 9904 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
Kojto 122:f9eeca106725 9905 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1U << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9906 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
Kojto 122:f9eeca106725 9907 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
Kojto 122:f9eeca106725 9908 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1U << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9909 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
Kojto 122:f9eeca106725 9910 #define HRTIM_BMTRGR_TDRST_Pos (19U)
Kojto 122:f9eeca106725 9911 #define HRTIM_BMTRGR_TDRST_Msk (0x1U << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9912 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
Kojto 122:f9eeca106725 9913 #define HRTIM_BMTRGR_TDREP_Pos (20U)
Kojto 122:f9eeca106725 9914 #define HRTIM_BMTRGR_TDREP_Msk (0x1U << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9915 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
Kojto 122:f9eeca106725 9916 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
Kojto 122:f9eeca106725 9917 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1U << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9918 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
Kojto 122:f9eeca106725 9919 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
Kojto 122:f9eeca106725 9920 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1U << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9921 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
Kojto 122:f9eeca106725 9922 #define HRTIM_BMTRGR_TERST_Pos (23U)
Kojto 122:f9eeca106725 9923 #define HRTIM_BMTRGR_TERST_Msk (0x1U << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9924 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
Kojto 122:f9eeca106725 9925 #define HRTIM_BMTRGR_TEREP_Pos (24U)
Kojto 122:f9eeca106725 9926 #define HRTIM_BMTRGR_TEREP_Msk (0x1U << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9927 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
Kojto 122:f9eeca106725 9928 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
Kojto 122:f9eeca106725 9929 #define HRTIM_BMTRGR_TECMP1_Msk (0x1U << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9930 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
Kojto 122:f9eeca106725 9931 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
Kojto 122:f9eeca106725 9932 #define HRTIM_BMTRGR_TECMP2_Msk (0x1U << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9933 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
Kojto 122:f9eeca106725 9934 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
Kojto 122:f9eeca106725 9935 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1U << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9936 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
Kojto 122:f9eeca106725 9937 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
Kojto 122:f9eeca106725 9938 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1U << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9939 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
Kojto 122:f9eeca106725 9940 #define HRTIM_BMTRGR_EEV7_Pos (29U)
Kojto 122:f9eeca106725 9941 #define HRTIM_BMTRGR_EEV7_Msk (0x1U << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9942 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
Kojto 122:f9eeca106725 9943 #define HRTIM_BMTRGR_EEV8_Pos (30U)
Kojto 122:f9eeca106725 9944 #define HRTIM_BMTRGR_EEV8_Msk (0x1U << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9945 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
Kojto 122:f9eeca106725 9946 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
Kojto 122:f9eeca106725 9947 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1U << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9948 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
bogdanm 86:04dd9b1680ae 9949
bogdanm 86:04dd9b1680ae 9950 /******************* Bit definition for HRTIM_BMCMPR register ***************/
Kojto 122:f9eeca106725 9951 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
Kojto 122:f9eeca106725 9952 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFU << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 9953 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
bogdanm 86:04dd9b1680ae 9954
bogdanm 86:04dd9b1680ae 9955 /******************* Bit definition for HRTIM_BMPER register ****************/
Kojto 122:f9eeca106725 9956 #define HRTIM_BMPER_BMPER_Pos (0U)
Kojto 122:f9eeca106725 9957 #define HRTIM_BMPER_BMPER_Msk (0xFFFFU << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 9958 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
bogdanm 86:04dd9b1680ae 9959
bogdanm 86:04dd9b1680ae 9960 /******************* Bit definition for HRTIM_EECR1 register ****************/
Kojto 122:f9eeca106725 9961 #define HRTIM_EECR1_EE1SRC_Pos (0U)
Kojto 122:f9eeca106725 9962 #define HRTIM_EECR1_EE1SRC_Msk (0x3U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 9963 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
Kojto 122:f9eeca106725 9964 #define HRTIM_EECR1_EE1SRC_0 (0x1U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9965 #define HRTIM_EECR1_EE1SRC_1 (0x2U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9966 #define HRTIM_EECR1_EE1POL_Pos (2U)
Kojto 122:f9eeca106725 9967 #define HRTIM_EECR1_EE1POL_Msk (0x1U << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9968 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
Kojto 122:f9eeca106725 9969 #define HRTIM_EECR1_EE1SNS_Pos (3U)
Kojto 122:f9eeca106725 9970 #define HRTIM_EECR1_EE1SNS_Msk (0x3U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 9971 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
Kojto 122:f9eeca106725 9972 #define HRTIM_EECR1_EE1SNS_0 (0x1U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9973 #define HRTIM_EECR1_EE1SNS_1 (0x2U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9974 #define HRTIM_EECR1_EE1FAST_Pos (5U)
Kojto 122:f9eeca106725 9975 #define HRTIM_EECR1_EE1FAST_Msk (0x1U << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9976 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
Kojto 122:f9eeca106725 9977
Kojto 122:f9eeca106725 9978 #define HRTIM_EECR1_EE2SRC_Pos (6U)
Kojto 122:f9eeca106725 9979 #define HRTIM_EECR1_EE2SRC_Msk (0x3U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 9980 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
Kojto 122:f9eeca106725 9981 #define HRTIM_EECR1_EE2SRC_0 (0x1U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9982 #define HRTIM_EECR1_EE2SRC_1 (0x2U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9983 #define HRTIM_EECR1_EE2POL_Pos (8U)
Kojto 122:f9eeca106725 9984 #define HRTIM_EECR1_EE2POL_Msk (0x1U << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9985 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
Kojto 122:f9eeca106725 9986 #define HRTIM_EECR1_EE2SNS_Pos (9U)
Kojto 122:f9eeca106725 9987 #define HRTIM_EECR1_EE2SNS_Msk (0x3U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 9988 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
Kojto 122:f9eeca106725 9989 #define HRTIM_EECR1_EE2SNS_0 (0x1U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9990 #define HRTIM_EECR1_EE2SNS_1 (0x2U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9991 #define HRTIM_EECR1_EE2FAST_Pos (11U)
Kojto 122:f9eeca106725 9992 #define HRTIM_EECR1_EE2FAST_Msk (0x1U << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9993 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
Kojto 122:f9eeca106725 9994
Kojto 122:f9eeca106725 9995 #define HRTIM_EECR1_EE3SRC_Pos (12U)
Kojto 122:f9eeca106725 9996 #define HRTIM_EECR1_EE3SRC_Msk (0x3U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 9997 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
Kojto 122:f9eeca106725 9998 #define HRTIM_EECR1_EE3SRC_0 (0x1U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9999 #define HRTIM_EECR1_EE3SRC_1 (0x2U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10000 #define HRTIM_EECR1_EE3POL_Pos (14U)
Kojto 122:f9eeca106725 10001 #define HRTIM_EECR1_EE3POL_Msk (0x1U << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10002 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
Kojto 122:f9eeca106725 10003 #define HRTIM_EECR1_EE3SNS_Pos (15U)
Kojto 122:f9eeca106725 10004 #define HRTIM_EECR1_EE3SNS_Msk (0x3U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
Kojto 122:f9eeca106725 10005 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
Kojto 122:f9eeca106725 10006 #define HRTIM_EECR1_EE3SNS_0 (0x1U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10007 #define HRTIM_EECR1_EE3SNS_1 (0x2U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10008 #define HRTIM_EECR1_EE3FAST_Pos (17U)
Kojto 122:f9eeca106725 10009 #define HRTIM_EECR1_EE3FAST_Msk (0x1U << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10010 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
Kojto 122:f9eeca106725 10011
Kojto 122:f9eeca106725 10012 #define HRTIM_EECR1_EE4SRC_Pos (18U)
Kojto 122:f9eeca106725 10013 #define HRTIM_EECR1_EE4SRC_Msk (0x3U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 10014 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
Kojto 122:f9eeca106725 10015 #define HRTIM_EECR1_EE4SRC_0 (0x1U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10016 #define HRTIM_EECR1_EE4SRC_1 (0x2U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10017 #define HRTIM_EECR1_EE4POL_Pos (20U)
Kojto 122:f9eeca106725 10018 #define HRTIM_EECR1_EE4POL_Msk (0x1U << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10019 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
Kojto 122:f9eeca106725 10020 #define HRTIM_EECR1_EE4SNS_Pos (21U)
Kojto 122:f9eeca106725 10021 #define HRTIM_EECR1_EE4SNS_Msk (0x3U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 10022 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
Kojto 122:f9eeca106725 10023 #define HRTIM_EECR1_EE4SNS_0 (0x1U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10024 #define HRTIM_EECR1_EE4SNS_1 (0x2U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10025 #define HRTIM_EECR1_EE4FAST_Pos (23U)
Kojto 122:f9eeca106725 10026 #define HRTIM_EECR1_EE4FAST_Msk (0x1U << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10027 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
Kojto 122:f9eeca106725 10028
Kojto 122:f9eeca106725 10029 #define HRTIM_EECR1_EE5SRC_Pos (24U)
Kojto 122:f9eeca106725 10030 #define HRTIM_EECR1_EE5SRC_Msk (0x3U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 10031 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
Kojto 122:f9eeca106725 10032 #define HRTIM_EECR1_EE5SRC_0 (0x1U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10033 #define HRTIM_EECR1_EE5SRC_1 (0x2U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10034 #define HRTIM_EECR1_EE5POL_Pos (26U)
Kojto 122:f9eeca106725 10035 #define HRTIM_EECR1_EE5POL_Msk (0x1U << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10036 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
Kojto 122:f9eeca106725 10037 #define HRTIM_EECR1_EE5SNS_Pos (27U)
Kojto 122:f9eeca106725 10038 #define HRTIM_EECR1_EE5SNS_Msk (0x3U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
Kojto 122:f9eeca106725 10039 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
Kojto 122:f9eeca106725 10040 #define HRTIM_EECR1_EE5SNS_0 (0x1U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10041 #define HRTIM_EECR1_EE5SNS_1 (0x2U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10042 #define HRTIM_EECR1_EE5FAST_Pos (29U)
Kojto 122:f9eeca106725 10043 #define HRTIM_EECR1_EE5FAST_Msk (0x1U << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10044 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
bogdanm 86:04dd9b1680ae 10045
bogdanm 86:04dd9b1680ae 10046 /******************* Bit definition for HRTIM_EECR2 register ****************/
Kojto 122:f9eeca106725 10047 #define HRTIM_EECR2_EE6SRC_Pos (0U)
Kojto 122:f9eeca106725 10048 #define HRTIM_EECR2_EE6SRC_Msk (0x3U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10049 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
Kojto 122:f9eeca106725 10050 #define HRTIM_EECR2_EE6SRC_0 (0x1U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10051 #define HRTIM_EECR2_EE6SRC_1 (0x2U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10052 #define HRTIM_EECR2_EE6POL_Pos (2U)
Kojto 122:f9eeca106725 10053 #define HRTIM_EECR2_EE6POL_Msk (0x1U << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10054 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
Kojto 122:f9eeca106725 10055 #define HRTIM_EECR2_EE6SNS_Pos (3U)
Kojto 122:f9eeca106725 10056 #define HRTIM_EECR2_EE6SNS_Msk (0x3U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 10057 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
Kojto 122:f9eeca106725 10058 #define HRTIM_EECR2_EE6SNS_0 (0x1U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10059 #define HRTIM_EECR2_EE6SNS_1 (0x2U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10060
Kojto 122:f9eeca106725 10061 #define HRTIM_EECR2_EE7SRC_Pos (6U)
Kojto 122:f9eeca106725 10062 #define HRTIM_EECR2_EE7SRC_Msk (0x3U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 10063 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
Kojto 122:f9eeca106725 10064 #define HRTIM_EECR2_EE7SRC_0 (0x1U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10065 #define HRTIM_EECR2_EE7SRC_1 (0x2U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10066 #define HRTIM_EECR2_EE7POL_Pos (8U)
Kojto 122:f9eeca106725 10067 #define HRTIM_EECR2_EE7POL_Msk (0x1U << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10068 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
Kojto 122:f9eeca106725 10069 #define HRTIM_EECR2_EE7SNS_Pos (9U)
Kojto 122:f9eeca106725 10070 #define HRTIM_EECR2_EE7SNS_Msk (0x3U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 10071 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
Kojto 122:f9eeca106725 10072 #define HRTIM_EECR2_EE7SNS_0 (0x1U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10073 #define HRTIM_EECR2_EE7SNS_1 (0x2U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10074
Kojto 122:f9eeca106725 10075 #define HRTIM_EECR2_EE8SRC_Pos (12U)
Kojto 122:f9eeca106725 10076 #define HRTIM_EECR2_EE8SRC_Msk (0x3U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 10077 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
Kojto 122:f9eeca106725 10078 #define HRTIM_EECR2_EE8SRC_0 (0x1U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10079 #define HRTIM_EECR2_EE8SRC_1 (0x2U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10080 #define HRTIM_EECR2_EE8POL_Pos (14U)
Kojto 122:f9eeca106725 10081 #define HRTIM_EECR2_EE8POL_Msk (0x1U << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10082 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
Kojto 122:f9eeca106725 10083 #define HRTIM_EECR2_EE8SNS_Pos (15U)
Kojto 122:f9eeca106725 10084 #define HRTIM_EECR2_EE8SNS_Msk (0x3U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
Kojto 122:f9eeca106725 10085 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
Kojto 122:f9eeca106725 10086 #define HRTIM_EECR2_EE8SNS_0 (0x1U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10087 #define HRTIM_EECR2_EE8SNS_1 (0x2U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10088
Kojto 122:f9eeca106725 10089 #define HRTIM_EECR2_EE9SRC_Pos (18U)
Kojto 122:f9eeca106725 10090 #define HRTIM_EECR2_EE9SRC_Msk (0x3U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 10091 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
Kojto 122:f9eeca106725 10092 #define HRTIM_EECR2_EE9SRC_0 (0x1U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10093 #define HRTIM_EECR2_EE9SRC_1 (0x2U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10094 #define HRTIM_EECR2_EE9POL_Pos (20U)
Kojto 122:f9eeca106725 10095 #define HRTIM_EECR2_EE9POL_Msk (0x1U << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10096 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
Kojto 122:f9eeca106725 10097 #define HRTIM_EECR2_EE9SNS_Pos (21U)
Kojto 122:f9eeca106725 10098 #define HRTIM_EECR2_EE9SNS_Msk (0x3U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 10099 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
Kojto 122:f9eeca106725 10100 #define HRTIM_EECR2_EE9SNS_0 (0x1U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10101 #define HRTIM_EECR2_EE9SNS_1 (0x2U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10102
Kojto 122:f9eeca106725 10103 #define HRTIM_EECR2_EE10SRC_Pos (24U)
Kojto 122:f9eeca106725 10104 #define HRTIM_EECR2_EE10SRC_Msk (0x3U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 10105 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
Kojto 122:f9eeca106725 10106 #define HRTIM_EECR2_EE10SRC_0 (0x1U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10107 #define HRTIM_EECR2_EE10SRC_1 (0x2U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10108 #define HRTIM_EECR2_EE10POL_Pos (26U)
Kojto 122:f9eeca106725 10109 #define HRTIM_EECR2_EE10POL_Msk (0x1U << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10110 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
Kojto 122:f9eeca106725 10111 #define HRTIM_EECR2_EE10SNS_Pos (27U)
Kojto 122:f9eeca106725 10112 #define HRTIM_EECR2_EE10SNS_Msk (0x3U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
Kojto 122:f9eeca106725 10113 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
Kojto 122:f9eeca106725 10114 #define HRTIM_EECR2_EE10SNS_0 (0x1U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10115 #define HRTIM_EECR2_EE10SNS_1 (0x2U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
bogdanm 86:04dd9b1680ae 10116
bogdanm 86:04dd9b1680ae 10117 /******************* Bit definition for HRTIM_EECR3 register ****************/
Kojto 122:f9eeca106725 10118 #define HRTIM_EECR3_EE6F_Pos (0U)
Kojto 122:f9eeca106725 10119 #define HRTIM_EECR3_EE6F_Msk (0xFU << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 10120 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
Kojto 122:f9eeca106725 10121 #define HRTIM_EECR3_EE6F_0 (0x1U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10122 #define HRTIM_EECR3_EE6F_1 (0x2U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10123 #define HRTIM_EECR3_EE6F_2 (0x4U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10124 #define HRTIM_EECR3_EE6F_3 (0x8U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10125 #define HRTIM_EECR3_EE7F_Pos (6U)
Kojto 122:f9eeca106725 10126 #define HRTIM_EECR3_EE7F_Msk (0xFU << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
Kojto 122:f9eeca106725 10127 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
Kojto 122:f9eeca106725 10128 #define HRTIM_EECR3_EE7F_0 (0x1U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10129 #define HRTIM_EECR3_EE7F_1 (0x2U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10130 #define HRTIM_EECR3_EE7F_2 (0x4U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10131 #define HRTIM_EECR3_EE7F_3 (0x8U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10132 #define HRTIM_EECR3_EE8F_Pos (12U)
Kojto 122:f9eeca106725 10133 #define HRTIM_EECR3_EE8F_Msk (0xFU << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 10134 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
Kojto 122:f9eeca106725 10135 #define HRTIM_EECR3_EE8F_0 (0x1U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10136 #define HRTIM_EECR3_EE8F_1 (0x2U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10137 #define HRTIM_EECR3_EE8F_2 (0x4U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10138 #define HRTIM_EECR3_EE8F_3 (0x8U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10139 #define HRTIM_EECR3_EE9F_Pos (18U)
Kojto 122:f9eeca106725 10140 #define HRTIM_EECR3_EE9F_Msk (0xFU << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
Kojto 122:f9eeca106725 10141 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
Kojto 122:f9eeca106725 10142 #define HRTIM_EECR3_EE9F_0 (0x1U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10143 #define HRTIM_EECR3_EE9F_1 (0x2U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10144 #define HRTIM_EECR3_EE9F_2 (0x4U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10145 #define HRTIM_EECR3_EE9F_3 (0x8U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10146 #define HRTIM_EECR3_EE10F_Pos (24U)
Kojto 122:f9eeca106725 10147 #define HRTIM_EECR3_EE10F_Msk (0xFU << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10148 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
Kojto 122:f9eeca106725 10149 #define HRTIM_EECR3_EE10F_0 (0x1U << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10150 #define HRTIM_EECR3_EE10F_1 (0x2U << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10151 #define HRTIM_EECR3_EE10F_2 (0x4U << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10152 #define HRTIM_EECR3_EE10F_3 (0x8U << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10153 #define HRTIM_EECR3_EEVSD_Pos (30U)
Kojto 122:f9eeca106725 10154 #define HRTIM_EECR3_EEVSD_Msk (0x3U << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 10155 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
Kojto 122:f9eeca106725 10156 #define HRTIM_EECR3_EEVSD_0 (0x1U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10157 #define HRTIM_EECR3_EEVSD_1 (0x2U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 10158
bogdanm 86:04dd9b1680ae 10159 /******************* Bit definition for HRTIM_ADC1R register ****************/
Kojto 122:f9eeca106725 10160 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
Kojto 122:f9eeca106725 10161 #define HRTIM_ADC1R_AD1MC1_Msk (0x1U << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10162 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
Kojto 122:f9eeca106725 10163 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
Kojto 122:f9eeca106725 10164 #define HRTIM_ADC1R_AD1MC2_Msk (0x1U << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10165 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
Kojto 122:f9eeca106725 10166 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
Kojto 122:f9eeca106725 10167 #define HRTIM_ADC1R_AD1MC3_Msk (0x1U << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10168 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
Kojto 122:f9eeca106725 10169 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
Kojto 122:f9eeca106725 10170 #define HRTIM_ADC1R_AD1MC4_Msk (0x1U << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10171 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
Kojto 122:f9eeca106725 10172 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
Kojto 122:f9eeca106725 10173 #define HRTIM_ADC1R_AD1MPER_Msk (0x1U << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10174 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
Kojto 122:f9eeca106725 10175 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
Kojto 122:f9eeca106725 10176 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1U << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10177 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
Kojto 122:f9eeca106725 10178 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
Kojto 122:f9eeca106725 10179 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1U << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10180 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
Kojto 122:f9eeca106725 10181 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
Kojto 122:f9eeca106725 10182 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1U << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10183 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
Kojto 122:f9eeca106725 10184 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
Kojto 122:f9eeca106725 10185 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1U << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10186 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
Kojto 122:f9eeca106725 10187 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
Kojto 122:f9eeca106725 10188 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1U << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10189 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
Kojto 122:f9eeca106725 10190 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
Kojto 122:f9eeca106725 10191 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1U << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10192 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
Kojto 122:f9eeca106725 10193 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
Kojto 122:f9eeca106725 10194 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1U << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10195 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
Kojto 122:f9eeca106725 10196 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
Kojto 122:f9eeca106725 10197 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1U << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10198 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
Kojto 122:f9eeca106725 10199 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
Kojto 122:f9eeca106725 10200 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1U << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10201 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
Kojto 122:f9eeca106725 10202 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
Kojto 122:f9eeca106725 10203 #define HRTIM_ADC1R_AD1TARST_Msk (0x1U << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10204 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
Kojto 122:f9eeca106725 10205 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
Kojto 122:f9eeca106725 10206 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1U << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10207 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
Kojto 122:f9eeca106725 10208 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
Kojto 122:f9eeca106725 10209 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1U << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10210 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
Kojto 122:f9eeca106725 10211 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
Kojto 122:f9eeca106725 10212 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1U << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10213 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
Kojto 122:f9eeca106725 10214 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
Kojto 122:f9eeca106725 10215 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1U << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10216 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
Kojto 122:f9eeca106725 10217 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
Kojto 122:f9eeca106725 10218 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1U << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10219 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
Kojto 122:f9eeca106725 10220 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
Kojto 122:f9eeca106725 10221 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1U << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10222 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
Kojto 122:f9eeca106725 10223 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
Kojto 122:f9eeca106725 10224 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1U << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10225 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
Kojto 122:f9eeca106725 10226 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
Kojto 122:f9eeca106725 10227 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1U << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10228 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
Kojto 122:f9eeca106725 10229 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
Kojto 122:f9eeca106725 10230 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1U << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10231 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
Kojto 122:f9eeca106725 10232 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
Kojto 122:f9eeca106725 10233 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1U << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10234 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
Kojto 122:f9eeca106725 10235 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
Kojto 122:f9eeca106725 10236 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1U << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10237 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
Kojto 122:f9eeca106725 10238 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
Kojto 122:f9eeca106725 10239 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1U << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10240 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
Kojto 122:f9eeca106725 10241 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
Kojto 122:f9eeca106725 10242 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1U << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10243 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
Kojto 122:f9eeca106725 10244 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
Kojto 122:f9eeca106725 10245 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1U << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10246 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
Kojto 122:f9eeca106725 10247 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
Kojto 122:f9eeca106725 10248 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1U << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10249 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
Kojto 122:f9eeca106725 10250 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
Kojto 122:f9eeca106725 10251 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1U << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10252 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
Kojto 122:f9eeca106725 10253 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
Kojto 122:f9eeca106725 10254 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1U << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10255 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
bogdanm 86:04dd9b1680ae 10256
bogdanm 86:04dd9b1680ae 10257 /******************* Bit definition for HRTIM_ADC2R register ****************/
Kojto 122:f9eeca106725 10258 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
Kojto 122:f9eeca106725 10259 #define HRTIM_ADC2R_AD2MC1_Msk (0x1U << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10260 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
Kojto 122:f9eeca106725 10261 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
Kojto 122:f9eeca106725 10262 #define HRTIM_ADC2R_AD2MC2_Msk (0x1U << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10263 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
Kojto 122:f9eeca106725 10264 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
Kojto 122:f9eeca106725 10265 #define HRTIM_ADC2R_AD2MC3_Msk (0x1U << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10266 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
Kojto 122:f9eeca106725 10267 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
Kojto 122:f9eeca106725 10268 #define HRTIM_ADC2R_AD2MC4_Msk (0x1U << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10269 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
Kojto 122:f9eeca106725 10270 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
Kojto 122:f9eeca106725 10271 #define HRTIM_ADC2R_AD2MPER_Msk (0x1U << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10272 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
Kojto 122:f9eeca106725 10273 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
Kojto 122:f9eeca106725 10274 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1U << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10275 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
Kojto 122:f9eeca106725 10276 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
Kojto 122:f9eeca106725 10277 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1U << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10278 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
Kojto 122:f9eeca106725 10279 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
Kojto 122:f9eeca106725 10280 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1U << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10281 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
Kojto 122:f9eeca106725 10282 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
Kojto 122:f9eeca106725 10283 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1U << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10284 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
Kojto 122:f9eeca106725 10285 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
Kojto 122:f9eeca106725 10286 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1U << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10287 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
Kojto 122:f9eeca106725 10288 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
Kojto 122:f9eeca106725 10289 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1U << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10290 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
Kojto 122:f9eeca106725 10291 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
Kojto 122:f9eeca106725 10292 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1U << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10293 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
Kojto 122:f9eeca106725 10294 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
Kojto 122:f9eeca106725 10295 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1U << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10296 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
Kojto 122:f9eeca106725 10297 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
Kojto 122:f9eeca106725 10298 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1U << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10299 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
Kojto 122:f9eeca106725 10300 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
Kojto 122:f9eeca106725 10301 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1U << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10302 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
Kojto 122:f9eeca106725 10303 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
Kojto 122:f9eeca106725 10304 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1U << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10305 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
Kojto 122:f9eeca106725 10306 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
Kojto 122:f9eeca106725 10307 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1U << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10308 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
Kojto 122:f9eeca106725 10309 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
Kojto 122:f9eeca106725 10310 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1U << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10311 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
Kojto 122:f9eeca106725 10312 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
Kojto 122:f9eeca106725 10313 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1U << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10314 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
Kojto 122:f9eeca106725 10315 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
Kojto 122:f9eeca106725 10316 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1U << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10317 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
Kojto 122:f9eeca106725 10318 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
Kojto 122:f9eeca106725 10319 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1U << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10320 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
Kojto 122:f9eeca106725 10321 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
Kojto 122:f9eeca106725 10322 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1U << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10323 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
Kojto 122:f9eeca106725 10324 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
Kojto 122:f9eeca106725 10325 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1U << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10326 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
Kojto 122:f9eeca106725 10327 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
Kojto 122:f9eeca106725 10328 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1U << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10329 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
Kojto 122:f9eeca106725 10330 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
Kojto 122:f9eeca106725 10331 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1U << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10332 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
Kojto 122:f9eeca106725 10333 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
Kojto 122:f9eeca106725 10334 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1U << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10335 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
Kojto 122:f9eeca106725 10336 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
Kojto 122:f9eeca106725 10337 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1U << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10338 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
Kojto 122:f9eeca106725 10339 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
Kojto 122:f9eeca106725 10340 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1U << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10341 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
Kojto 122:f9eeca106725 10342 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
Kojto 122:f9eeca106725 10343 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1U << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10344 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
Kojto 122:f9eeca106725 10345 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
Kojto 122:f9eeca106725 10346 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1U << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10347 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
Kojto 122:f9eeca106725 10348 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
Kojto 122:f9eeca106725 10349 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1U << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10350 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
Kojto 122:f9eeca106725 10351 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
Kojto 122:f9eeca106725 10352 #define HRTIM_ADC2R_AD2TERST_Msk (0x1U << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10353 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
bogdanm 86:04dd9b1680ae 10354
bogdanm 86:04dd9b1680ae 10355 /******************* Bit definition for HRTIM_ADC3R register ****************/
Kojto 122:f9eeca106725 10356 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
Kojto 122:f9eeca106725 10357 #define HRTIM_ADC3R_AD3MC1_Msk (0x1U << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10358 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
Kojto 122:f9eeca106725 10359 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
Kojto 122:f9eeca106725 10360 #define HRTIM_ADC3R_AD3MC2_Msk (0x1U << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10361 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
Kojto 122:f9eeca106725 10362 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
Kojto 122:f9eeca106725 10363 #define HRTIM_ADC3R_AD3MC3_Msk (0x1U << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10364 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
Kojto 122:f9eeca106725 10365 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
Kojto 122:f9eeca106725 10366 #define HRTIM_ADC3R_AD3MC4_Msk (0x1U << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10367 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
Kojto 122:f9eeca106725 10368 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
Kojto 122:f9eeca106725 10369 #define HRTIM_ADC3R_AD3MPER_Msk (0x1U << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10370 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
Kojto 122:f9eeca106725 10371 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
Kojto 122:f9eeca106725 10372 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1U << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10373 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
Kojto 122:f9eeca106725 10374 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
Kojto 122:f9eeca106725 10375 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1U << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10376 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
Kojto 122:f9eeca106725 10377 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
Kojto 122:f9eeca106725 10378 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1U << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10379 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
Kojto 122:f9eeca106725 10380 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
Kojto 122:f9eeca106725 10381 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1U << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10382 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
Kojto 122:f9eeca106725 10383 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
Kojto 122:f9eeca106725 10384 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1U << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10385 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
Kojto 122:f9eeca106725 10386 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
Kojto 122:f9eeca106725 10387 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1U << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10388 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
Kojto 122:f9eeca106725 10389 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
Kojto 122:f9eeca106725 10390 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1U << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10391 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
Kojto 122:f9eeca106725 10392 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
Kojto 122:f9eeca106725 10393 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1U << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10394 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
Kojto 122:f9eeca106725 10395 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
Kojto 122:f9eeca106725 10396 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1U << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10397 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
Kojto 122:f9eeca106725 10398 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
Kojto 122:f9eeca106725 10399 #define HRTIM_ADC3R_AD3TARST_Msk (0x1U << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10400 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
Kojto 122:f9eeca106725 10401 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
Kojto 122:f9eeca106725 10402 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1U << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10403 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
Kojto 122:f9eeca106725 10404 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
Kojto 122:f9eeca106725 10405 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1U << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10406 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
Kojto 122:f9eeca106725 10407 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
Kojto 122:f9eeca106725 10408 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1U << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10409 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
Kojto 122:f9eeca106725 10410 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
Kojto 122:f9eeca106725 10411 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1U << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10412 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
Kojto 122:f9eeca106725 10413 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
Kojto 122:f9eeca106725 10414 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1U << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10415 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
Kojto 122:f9eeca106725 10416 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
Kojto 122:f9eeca106725 10417 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1U << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10418 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
Kojto 122:f9eeca106725 10419 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
Kojto 122:f9eeca106725 10420 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1U << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10421 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
Kojto 122:f9eeca106725 10422 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
Kojto 122:f9eeca106725 10423 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1U << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10424 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
Kojto 122:f9eeca106725 10425 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
Kojto 122:f9eeca106725 10426 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1U << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10427 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
Kojto 122:f9eeca106725 10428 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
Kojto 122:f9eeca106725 10429 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1U << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10430 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
Kojto 122:f9eeca106725 10431 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
Kojto 122:f9eeca106725 10432 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1U << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10433 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
Kojto 122:f9eeca106725 10434 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
Kojto 122:f9eeca106725 10435 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1U << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10436 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
Kojto 122:f9eeca106725 10437 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
Kojto 122:f9eeca106725 10438 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1U << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10439 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
Kojto 122:f9eeca106725 10440 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
Kojto 122:f9eeca106725 10441 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1U << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10442 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
Kojto 122:f9eeca106725 10443 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
Kojto 122:f9eeca106725 10444 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1U << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10445 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
Kojto 122:f9eeca106725 10446 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
Kojto 122:f9eeca106725 10447 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1U << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10448 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
Kojto 122:f9eeca106725 10449 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
Kojto 122:f9eeca106725 10450 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1U << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10451 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
bogdanm 86:04dd9b1680ae 10452
bogdanm 86:04dd9b1680ae 10453 /******************* Bit definition for HRTIM_ADC4R register ****************/
Kojto 122:f9eeca106725 10454 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
Kojto 122:f9eeca106725 10455 #define HRTIM_ADC4R_AD4MC1_Msk (0x1U << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10456 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
Kojto 122:f9eeca106725 10457 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
Kojto 122:f9eeca106725 10458 #define HRTIM_ADC4R_AD4MC2_Msk (0x1U << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10459 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
Kojto 122:f9eeca106725 10460 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
Kojto 122:f9eeca106725 10461 #define HRTIM_ADC4R_AD4MC3_Msk (0x1U << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10462 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
Kojto 122:f9eeca106725 10463 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
Kojto 122:f9eeca106725 10464 #define HRTIM_ADC4R_AD4MC4_Msk (0x1U << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10465 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
Kojto 122:f9eeca106725 10466 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
Kojto 122:f9eeca106725 10467 #define HRTIM_ADC4R_AD4MPER_Msk (0x1U << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10468 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
Kojto 122:f9eeca106725 10469 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
Kojto 122:f9eeca106725 10470 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1U << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10471 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
Kojto 122:f9eeca106725 10472 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
Kojto 122:f9eeca106725 10473 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1U << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10474 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
Kojto 122:f9eeca106725 10475 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
Kojto 122:f9eeca106725 10476 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1U << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10477 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
Kojto 122:f9eeca106725 10478 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
Kojto 122:f9eeca106725 10479 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1U << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10480 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
Kojto 122:f9eeca106725 10481 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
Kojto 122:f9eeca106725 10482 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1U << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10483 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
Kojto 122:f9eeca106725 10484 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
Kojto 122:f9eeca106725 10485 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1U << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10486 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
Kojto 122:f9eeca106725 10487 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
Kojto 122:f9eeca106725 10488 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1U << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10489 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
Kojto 122:f9eeca106725 10490 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
Kojto 122:f9eeca106725 10491 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1U << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10492 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
Kojto 122:f9eeca106725 10493 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
Kojto 122:f9eeca106725 10494 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1U << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10495 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
Kojto 122:f9eeca106725 10496 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
Kojto 122:f9eeca106725 10497 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1U << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10498 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
Kojto 122:f9eeca106725 10499 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
Kojto 122:f9eeca106725 10500 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1U << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10501 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
Kojto 122:f9eeca106725 10502 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
Kojto 122:f9eeca106725 10503 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1U << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10504 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
Kojto 122:f9eeca106725 10505 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
Kojto 122:f9eeca106725 10506 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1U << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10507 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
Kojto 122:f9eeca106725 10508 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
Kojto 122:f9eeca106725 10509 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1U << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10510 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
Kojto 122:f9eeca106725 10511 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
Kojto 122:f9eeca106725 10512 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1U << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10513 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
Kojto 122:f9eeca106725 10514 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
Kojto 122:f9eeca106725 10515 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1U << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10516 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
Kojto 122:f9eeca106725 10517 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
Kojto 122:f9eeca106725 10518 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1U << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10519 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
Kojto 122:f9eeca106725 10520 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
Kojto 122:f9eeca106725 10521 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1U << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10522 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
Kojto 122:f9eeca106725 10523 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
Kojto 122:f9eeca106725 10524 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1U << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10525 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
Kojto 122:f9eeca106725 10526 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
Kojto 122:f9eeca106725 10527 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1U << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10528 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
Kojto 122:f9eeca106725 10529 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
Kojto 122:f9eeca106725 10530 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1U << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10531 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
Kojto 122:f9eeca106725 10532 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
Kojto 122:f9eeca106725 10533 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1U << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10534 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
Kojto 122:f9eeca106725 10535 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
Kojto 122:f9eeca106725 10536 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1U << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10537 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
Kojto 122:f9eeca106725 10538 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
Kojto 122:f9eeca106725 10539 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1U << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10540 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
Kojto 122:f9eeca106725 10541 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
Kojto 122:f9eeca106725 10542 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1U << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10543 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
Kojto 122:f9eeca106725 10544 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
Kojto 122:f9eeca106725 10545 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1U << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10546 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
Kojto 122:f9eeca106725 10547 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
Kojto 122:f9eeca106725 10548 #define HRTIM_ADC4R_AD4TERST_Msk (0x1U << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10549 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
bogdanm 86:04dd9b1680ae 10550
bogdanm 86:04dd9b1680ae 10551 /******************* Bit definition for HRTIM_DLLCR register ****************/
Kojto 122:f9eeca106725 10552 #define HRTIM_DLLCR_CAL_Pos (0U)
Kojto 122:f9eeca106725 10553 #define HRTIM_DLLCR_CAL_Msk (0x1U << HRTIM_DLLCR_CAL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10554 #define HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk /*!< DLL calibration start */
Kojto 122:f9eeca106725 10555 #define HRTIM_DLLCR_CALEN_Pos (1U)
Kojto 122:f9eeca106725 10556 #define HRTIM_DLLCR_CALEN_Msk (0x1U << HRTIM_DLLCR_CALEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10557 #define HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk /*!< DLL calibration enable */
Kojto 122:f9eeca106725 10558 #define HRTIM_DLLCR_CALRTE_Pos (2U)
Kojto 122:f9eeca106725 10559 #define HRTIM_DLLCR_CALRTE_Msk (0x3U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 10560 #define HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk /*!< DLL calibration rate */
Kojto 122:f9eeca106725 10561 #define HRTIM_DLLCR_CALRTE_0 (0x1U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10562 #define HRTIM_DLLCR_CALRTE_1 (0x2U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 10563
bogdanm 86:04dd9b1680ae 10564 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
Kojto 122:f9eeca106725 10565 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
Kojto 122:f9eeca106725 10566 #define HRTIM_FLTINR1_FLT1E_Msk (0x1U << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10567 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
Kojto 122:f9eeca106725 10568 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
Kojto 122:f9eeca106725 10569 #define HRTIM_FLTINR1_FLT1P_Msk (0x1U << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10570 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
Kojto 122:f9eeca106725 10571 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
Kojto 122:f9eeca106725 10572 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1U << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10573 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
Kojto 122:f9eeca106725 10574 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
Kojto 122:f9eeca106725 10575 #define HRTIM_FLTINR1_FLT1F_Msk (0xFU << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
Kojto 122:f9eeca106725 10576 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
Kojto 122:f9eeca106725 10577 #define HRTIM_FLTINR1_FLT1F_0 (0x1U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10578 #define HRTIM_FLTINR1_FLT1F_1 (0x2U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10579 #define HRTIM_FLTINR1_FLT1F_2 (0x4U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10580 #define HRTIM_FLTINR1_FLT1F_3 (0x8U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10581 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
Kojto 122:f9eeca106725 10582 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1U << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10583 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
Kojto 122:f9eeca106725 10584
Kojto 122:f9eeca106725 10585 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
Kojto 122:f9eeca106725 10586 #define HRTIM_FLTINR1_FLT2E_Msk (0x1U << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10587 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
Kojto 122:f9eeca106725 10588 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
Kojto 122:f9eeca106725 10589 #define HRTIM_FLTINR1_FLT2P_Msk (0x1U << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10590 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
Kojto 122:f9eeca106725 10591 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
Kojto 122:f9eeca106725 10592 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1U << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10593 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
Kojto 122:f9eeca106725 10594 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
Kojto 122:f9eeca106725 10595 #define HRTIM_FLTINR1_FLT2F_Msk (0xFU << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
Kojto 122:f9eeca106725 10596 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
Kojto 122:f9eeca106725 10597 #define HRTIM_FLTINR1_FLT2F_0 (0x1U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10598 #define HRTIM_FLTINR1_FLT2F_1 (0x2U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10599 #define HRTIM_FLTINR1_FLT2F_2 (0x4U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10600 #define HRTIM_FLTINR1_FLT2F_3 (0x8U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10601 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
Kojto 122:f9eeca106725 10602 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1U << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10603 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
Kojto 122:f9eeca106725 10604
Kojto 122:f9eeca106725 10605 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
Kojto 122:f9eeca106725 10606 #define HRTIM_FLTINR1_FLT3E_Msk (0x1U << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10607 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
Kojto 122:f9eeca106725 10608 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
Kojto 122:f9eeca106725 10609 #define HRTIM_FLTINR1_FLT3P_Msk (0x1U << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10610 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
Kojto 122:f9eeca106725 10611 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
Kojto 122:f9eeca106725 10612 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1U << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10613 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
Kojto 122:f9eeca106725 10614 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
Kojto 122:f9eeca106725 10615 #define HRTIM_FLTINR1_FLT3F_Msk (0xFU << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
Kojto 122:f9eeca106725 10616 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
Kojto 122:f9eeca106725 10617 #define HRTIM_FLTINR1_FLT3F_0 (0x1U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10618 #define HRTIM_FLTINR1_FLT3F_1 (0x2U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10619 #define HRTIM_FLTINR1_FLT3F_2 (0x4U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10620 #define HRTIM_FLTINR1_FLT3F_3 (0x8U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10621 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
Kojto 122:f9eeca106725 10622 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1U << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10623 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
Kojto 122:f9eeca106725 10624
Kojto 122:f9eeca106725 10625 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
Kojto 122:f9eeca106725 10626 #define HRTIM_FLTINR1_FLT4E_Msk (0x1U << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10627 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
Kojto 122:f9eeca106725 10628 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
Kojto 122:f9eeca106725 10629 #define HRTIM_FLTINR1_FLT4P_Msk (0x1U << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10630 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
Kojto 122:f9eeca106725 10631 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
Kojto 122:f9eeca106725 10632 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1U << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10633 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
Kojto 122:f9eeca106725 10634 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
Kojto 122:f9eeca106725 10635 #define HRTIM_FLTINR1_FLT4F_Msk (0xFU << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
Kojto 122:f9eeca106725 10636 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
Kojto 122:f9eeca106725 10637 #define HRTIM_FLTINR1_FLT4F_0 (0x1U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10638 #define HRTIM_FLTINR1_FLT4F_1 (0x2U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10639 #define HRTIM_FLTINR1_FLT4F_2 (0x4U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10640 #define HRTIM_FLTINR1_FLT4F_3 (0x8U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10641 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
Kojto 122:f9eeca106725 10642 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1U << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10643 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
bogdanm 86:04dd9b1680ae 10644
bogdanm 86:04dd9b1680ae 10645 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
Kojto 122:f9eeca106725 10646 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
Kojto 122:f9eeca106725 10647 #define HRTIM_FLTINR2_FLT5E_Msk (0x1U << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10648 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
Kojto 122:f9eeca106725 10649 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
Kojto 122:f9eeca106725 10650 #define HRTIM_FLTINR2_FLT5P_Msk (0x1U << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10651 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
Kojto 122:f9eeca106725 10652 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
Kojto 122:f9eeca106725 10653 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1U << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10654 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
Kojto 122:f9eeca106725 10655 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
Kojto 122:f9eeca106725 10656 #define HRTIM_FLTINR2_FLT5F_Msk (0xFU << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
Kojto 122:f9eeca106725 10657 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
Kojto 122:f9eeca106725 10658 #define HRTIM_FLTINR2_FLT5F_0 (0x1U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10659 #define HRTIM_FLTINR2_FLT5F_1 (0x2U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10660 #define HRTIM_FLTINR2_FLT5F_2 (0x4U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10661 #define HRTIM_FLTINR2_FLT5F_3 (0x8U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10662 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
Kojto 122:f9eeca106725 10663 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1U << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10664 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
Kojto 122:f9eeca106725 10665 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
Kojto 122:f9eeca106725 10666 #define HRTIM_FLTINR2_FLTSD_Msk (0x3U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 10667 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
Kojto 122:f9eeca106725 10668 #define HRTIM_FLTINR2_FLTSD_0 (0x1U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10669 #define HRTIM_FLTINR2_FLTSD_1 (0x2U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
bogdanm 86:04dd9b1680ae 10670
bogdanm 86:04dd9b1680ae 10671 /******************* Bit definition for HRTIM_BDMUPR register ***************/
Kojto 122:f9eeca106725 10672 #define HRTIM_BDMUPR_MCR_Pos (0U)
Kojto 122:f9eeca106725 10673 #define HRTIM_BDMUPR_MCR_Msk (0x1U << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10674 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
Kojto 122:f9eeca106725 10675 #define HRTIM_BDMUPR_MICR_Pos (1U)
Kojto 122:f9eeca106725 10676 #define HRTIM_BDMUPR_MICR_Msk (0x1U << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10677 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
Kojto 122:f9eeca106725 10678 #define HRTIM_BDMUPR_MDIER_Pos (2U)
Kojto 122:f9eeca106725 10679 #define HRTIM_BDMUPR_MDIER_Msk (0x1U << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10680 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
Kojto 122:f9eeca106725 10681 #define HRTIM_BDMUPR_MCNT_Pos (3U)
Kojto 122:f9eeca106725 10682 #define HRTIM_BDMUPR_MCNT_Msk (0x1U << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10683 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
Kojto 122:f9eeca106725 10684 #define HRTIM_BDMUPR_MPER_Pos (4U)
Kojto 122:f9eeca106725 10685 #define HRTIM_BDMUPR_MPER_Msk (0x1U << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10686 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
Kojto 122:f9eeca106725 10687 #define HRTIM_BDMUPR_MREP_Pos (5U)
Kojto 122:f9eeca106725 10688 #define HRTIM_BDMUPR_MREP_Msk (0x1U << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10689 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
Kojto 122:f9eeca106725 10690 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
Kojto 122:f9eeca106725 10691 #define HRTIM_BDMUPR_MCMP1_Msk (0x1U << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10692 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
Kojto 122:f9eeca106725 10693 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
Kojto 122:f9eeca106725 10694 #define HRTIM_BDMUPR_MCMP2_Msk (0x1U << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10695 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
Kojto 122:f9eeca106725 10696 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
Kojto 122:f9eeca106725 10697 #define HRTIM_BDMUPR_MCMP3_Msk (0x1U << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10698 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
Kojto 122:f9eeca106725 10699 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
Kojto 122:f9eeca106725 10700 #define HRTIM_BDMUPR_MCMP4_Msk (0x1U << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10701 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
bogdanm 86:04dd9b1680ae 10702
bogdanm 86:04dd9b1680ae 10703 /******************* Bit definition for HRTIM_BDTUPR register ***************/
Kojto 122:f9eeca106725 10704 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
Kojto 122:f9eeca106725 10705 #define HRTIM_BDTUPR_TIMCR_Msk (0x1U << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10706 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
Kojto 122:f9eeca106725 10707 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
Kojto 122:f9eeca106725 10708 #define HRTIM_BDTUPR_TIMICR_Msk (0x1U << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10709 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
Kojto 122:f9eeca106725 10710 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
Kojto 122:f9eeca106725 10711 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1U << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10712 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
Kojto 122:f9eeca106725 10713 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
Kojto 122:f9eeca106725 10714 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1U << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10715 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
Kojto 122:f9eeca106725 10716 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
Kojto 122:f9eeca106725 10717 #define HRTIM_BDTUPR_TIMPER_Msk (0x1U << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10718 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
Kojto 122:f9eeca106725 10719 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
Kojto 122:f9eeca106725 10720 #define HRTIM_BDTUPR_TIMREP_Msk (0x1U << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10721 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
Kojto 122:f9eeca106725 10722 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
Kojto 122:f9eeca106725 10723 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1U << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10724 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
Kojto 122:f9eeca106725 10725 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
Kojto 122:f9eeca106725 10726 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1U << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10727 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
Kojto 122:f9eeca106725 10728 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
Kojto 122:f9eeca106725 10729 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1U << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10730 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
Kojto 122:f9eeca106725 10731 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
Kojto 122:f9eeca106725 10732 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1U << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10733 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
Kojto 122:f9eeca106725 10734 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
Kojto 122:f9eeca106725 10735 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1U << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10736 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
Kojto 122:f9eeca106725 10737 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
Kojto 122:f9eeca106725 10738 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1U << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10739 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
Kojto 122:f9eeca106725 10740 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
Kojto 122:f9eeca106725 10741 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1U << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10742 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
Kojto 122:f9eeca106725 10743 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
Kojto 122:f9eeca106725 10744 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1U << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10745 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
Kojto 122:f9eeca106725 10746 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
Kojto 122:f9eeca106725 10747 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1U << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10748 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
Kojto 122:f9eeca106725 10749 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
Kojto 122:f9eeca106725 10750 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10751 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
Kojto 122:f9eeca106725 10752 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
Kojto 122:f9eeca106725 10753 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10754 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
Kojto 122:f9eeca106725 10755 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
Kojto 122:f9eeca106725 10756 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1U << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10757 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
Kojto 122:f9eeca106725 10758 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
Kojto 122:f9eeca106725 10759 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1U << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10760 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
Kojto 122:f9eeca106725 10761 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
Kojto 122:f9eeca106725 10762 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1U << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10763 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
Kojto 122:f9eeca106725 10764 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
Kojto 122:f9eeca106725 10765 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1U << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10766 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
bogdanm 86:04dd9b1680ae 10767
bogdanm 86:04dd9b1680ae 10768 /******************* Bit definition for HRTIM_BDMADR register ***************/
Kojto 122:f9eeca106725 10769 #define HRTIM_BDMADR_BDMADR_Pos (0U)
Kojto 122:f9eeca106725 10770 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFU << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10771 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
bogdanm 86:04dd9b1680ae 10772
bogdanm 86:04dd9b1680ae 10773 /******************************************************************************/
bogdanm 86:04dd9b1680ae 10774 /* */
bogdanm 86:04dd9b1680ae 10775 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 86:04dd9b1680ae 10776 /* */
bogdanm 86:04dd9b1680ae 10777 /******************************************************************************/
bogdanm 86:04dd9b1680ae 10778 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 10779 #define I2C_CR1_PE_Pos (0U)
Kojto 122:f9eeca106725 10780 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10781 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
Kojto 122:f9eeca106725 10782 #define I2C_CR1_TXIE_Pos (1U)
Kojto 122:f9eeca106725 10783 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10784 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
Kojto 122:f9eeca106725 10785 #define I2C_CR1_RXIE_Pos (2U)
Kojto 122:f9eeca106725 10786 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10787 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
Kojto 122:f9eeca106725 10788 #define I2C_CR1_ADDRIE_Pos (3U)
Kojto 122:f9eeca106725 10789 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10790 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 10791 #define I2C_CR1_NACKIE_Pos (4U)
Kojto 122:f9eeca106725 10792 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10793 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 10794 #define I2C_CR1_STOPIE_Pos (5U)
Kojto 122:f9eeca106725 10795 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10796 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 10797 #define I2C_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 10798 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10799 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 10800 #define I2C_CR1_ERRIE_Pos (7U)
Kojto 122:f9eeca106725 10801 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10802 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 10803 #define I2C_CR1_DNF_Pos (8U)
Kojto 122:f9eeca106725 10804 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10805 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
Kojto 122:f9eeca106725 10806 #define I2C_CR1_ANFOFF_Pos (12U)
Kojto 122:f9eeca106725 10807 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10808 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 10809 #define I2C_CR1_SWRST_Pos (13U)
Kojto 122:f9eeca106725 10810 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10811 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
Kojto 122:f9eeca106725 10812 #define I2C_CR1_TXDMAEN_Pos (14U)
Kojto 122:f9eeca106725 10813 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10814 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 10815 #define I2C_CR1_RXDMAEN_Pos (15U)
Kojto 122:f9eeca106725 10816 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10817 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 10818 #define I2C_CR1_SBC_Pos (16U)
Kojto 122:f9eeca106725 10819 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10820 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
Kojto 122:f9eeca106725 10821 #define I2C_CR1_NOSTRETCH_Pos (17U)
Kojto 122:f9eeca106725 10822 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10823 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
Kojto 122:f9eeca106725 10824 #define I2C_CR1_WUPEN_Pos (18U)
Kojto 122:f9eeca106725 10825 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10826 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
Kojto 122:f9eeca106725 10827 #define I2C_CR1_GCEN_Pos (19U)
Kojto 122:f9eeca106725 10828 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10829 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
Kojto 122:f9eeca106725 10830 #define I2C_CR1_SMBHEN_Pos (20U)
Kojto 122:f9eeca106725 10831 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10832 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
Kojto 122:f9eeca106725 10833 #define I2C_CR1_SMBDEN_Pos (21U)
Kojto 122:f9eeca106725 10834 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10835 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 10836 #define I2C_CR1_ALERTEN_Pos (22U)
Kojto 122:f9eeca106725 10837 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10838 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
Kojto 122:f9eeca106725 10839 #define I2C_CR1_PECEN_Pos (23U)
Kojto 122:f9eeca106725 10840 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10841 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
Kojto 122:f9eeca106725 10842
Kojto 122:f9eeca106725 10843 /* Legacy defines */
Kojto 122:f9eeca106725 10844 #define I2C_CR1_DFN I2C_CR1_DNF
bogdanm 86:04dd9b1680ae 10845
bogdanm 86:04dd9b1680ae 10846 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 10847 #define I2C_CR2_SADD_Pos (0U)
Kojto 122:f9eeca106725 10848 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 10849 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 10850 #define I2C_CR2_RD_WRN_Pos (10U)
Kojto 122:f9eeca106725 10851 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10852 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 10853 #define I2C_CR2_ADD10_Pos (11U)
Kojto 122:f9eeca106725 10854 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10855 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 10856 #define I2C_CR2_HEAD10R_Pos (12U)
Kojto 122:f9eeca106725 10857 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10858 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 10859 #define I2C_CR2_START_Pos (13U)
Kojto 122:f9eeca106725 10860 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10861 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
Kojto 122:f9eeca106725 10862 #define I2C_CR2_STOP_Pos (14U)
Kojto 122:f9eeca106725 10863 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10864 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 10865 #define I2C_CR2_NACK_Pos (15U)
Kojto 122:f9eeca106725 10866 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10867 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 10868 #define I2C_CR2_NBYTES_Pos (16U)
Kojto 122:f9eeca106725 10869 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 10870 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
Kojto 122:f9eeca106725 10871 #define I2C_CR2_RELOAD_Pos (24U)
Kojto 122:f9eeca106725 10872 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10873 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 10874 #define I2C_CR2_AUTOEND_Pos (25U)
Kojto 122:f9eeca106725 10875 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10876 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 10877 #define I2C_CR2_PECBYTE_Pos (26U)
Kojto 122:f9eeca106725 10878 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10879 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
bogdanm 86:04dd9b1680ae 10880
bogdanm 86:04dd9b1680ae 10881 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 10882 #define I2C_OAR1_OA1_Pos (0U)
Kojto 122:f9eeca106725 10883 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 10884 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
Kojto 122:f9eeca106725 10885 #define I2C_OAR1_OA1MODE_Pos (10U)
Kojto 122:f9eeca106725 10886 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10887 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 10888 #define I2C_OAR1_OA1EN_Pos (15U)
Kojto 122:f9eeca106725 10889 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10890 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
bogdanm 86:04dd9b1680ae 10891
bogdanm 86:04dd9b1680ae 10892 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 122:f9eeca106725 10893 #define I2C_OAR2_OA2_Pos (1U)
Kojto 122:f9eeca106725 10894 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
Kojto 122:f9eeca106725 10895 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
Kojto 122:f9eeca106725 10896 #define I2C_OAR2_OA2MSK_Pos (8U)
Kojto 122:f9eeca106725 10897 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 10898 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
Kojto 122:f9eeca106725 10899 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
Kojto 122:f9eeca106725 10900 #define I2C_OAR2_OA2MASK01_Pos (8U)
Kojto 122:f9eeca106725 10901 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10902 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 122:f9eeca106725 10903 #define I2C_OAR2_OA2MASK02_Pos (9U)
Kojto 122:f9eeca106725 10904 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10905 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 122:f9eeca106725 10906 #define I2C_OAR2_OA2MASK03_Pos (8U)
Kojto 122:f9eeca106725 10907 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 10908 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 122:f9eeca106725 10909 #define I2C_OAR2_OA2MASK04_Pos (10U)
Kojto 122:f9eeca106725 10910 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10911 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 122:f9eeca106725 10912 #define I2C_OAR2_OA2MASK05_Pos (8U)
Kojto 122:f9eeca106725 10913 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 10914 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 122:f9eeca106725 10915 #define I2C_OAR2_OA2MASK06_Pos (9U)
Kojto 122:f9eeca106725 10916 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 10917 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 122:f9eeca106725 10918 #define I2C_OAR2_OA2MASK07_Pos (8U)
Kojto 122:f9eeca106725 10919 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 10920 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
Kojto 122:f9eeca106725 10921 #define I2C_OAR2_OA2EN_Pos (15U)
Kojto 122:f9eeca106725 10922 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10923 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
bogdanm 86:04dd9b1680ae 10924
bogdanm 86:04dd9b1680ae 10925 /******************* Bit definition for I2C_TIMINGR register *****************/
Kojto 122:f9eeca106725 10926 #define I2C_TIMINGR_SCLL_Pos (0U)
Kojto 122:f9eeca106725 10927 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 10928 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 10929 #define I2C_TIMINGR_SCLH_Pos (8U)
Kojto 122:f9eeca106725 10930 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 10931 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 10932 #define I2C_TIMINGR_SDADEL_Pos (16U)
Kojto 122:f9eeca106725 10933 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 10934 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
Kojto 122:f9eeca106725 10935 #define I2C_TIMINGR_SCLDEL_Pos (20U)
Kojto 122:f9eeca106725 10936 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 10937 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
Kojto 122:f9eeca106725 10938 #define I2C_TIMINGR_PRESC_Pos (28U)
Kojto 122:f9eeca106725 10939 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 10940 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
bogdanm 86:04dd9b1680ae 10941
bogdanm 86:04dd9b1680ae 10942 /******************* Bit definition for I2C_TIMEOUTR register *****************/
Kojto 122:f9eeca106725 10943 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
Kojto 122:f9eeca106725 10944 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 10945 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
Kojto 122:f9eeca106725 10946 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
Kojto 122:f9eeca106725 10947 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10948 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 10949 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
Kojto 122:f9eeca106725 10950 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10951 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
Kojto 122:f9eeca106725 10952 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
Kojto 122:f9eeca106725 10953 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 10954 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
Kojto 122:f9eeca106725 10955 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
Kojto 122:f9eeca106725 10956 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10957 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
bogdanm 86:04dd9b1680ae 10958
bogdanm 86:04dd9b1680ae 10959 /****************** Bit definition for I2C_ISR register *********************/
Kojto 122:f9eeca106725 10960 #define I2C_ISR_TXE_Pos (0U)
Kojto 122:f9eeca106725 10961 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10962 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
Kojto 122:f9eeca106725 10963 #define I2C_ISR_TXIS_Pos (1U)
Kojto 122:f9eeca106725 10964 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10965 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 10966 #define I2C_ISR_RXNE_Pos (2U)
Kojto 122:f9eeca106725 10967 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10968 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
Kojto 122:f9eeca106725 10969 #define I2C_ISR_ADDR_Pos (3U)
Kojto 122:f9eeca106725 10970 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10971 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
Kojto 122:f9eeca106725 10972 #define I2C_ISR_NACKF_Pos (4U)
Kojto 122:f9eeca106725 10973 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10974 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
Kojto 122:f9eeca106725 10975 #define I2C_ISR_STOPF_Pos (5U)
Kojto 122:f9eeca106725 10976 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10977 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
Kojto 122:f9eeca106725 10978 #define I2C_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 10979 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10980 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 10981 #define I2C_ISR_TCR_Pos (7U)
Kojto 122:f9eeca106725 10982 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10983 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
Kojto 122:f9eeca106725 10984 #define I2C_ISR_BERR_Pos (8U)
Kojto 122:f9eeca106725 10985 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10986 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
Kojto 122:f9eeca106725 10987 #define I2C_ISR_ARLO_Pos (9U)
Kojto 122:f9eeca106725 10988 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10989 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
Kojto 122:f9eeca106725 10990 #define I2C_ISR_OVR_Pos (10U)
Kojto 122:f9eeca106725 10991 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10992 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 10993 #define I2C_ISR_PECERR_Pos (11U)
Kojto 122:f9eeca106725 10994 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10995 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
Kojto 122:f9eeca106725 10996 #define I2C_ISR_TIMEOUT_Pos (12U)
Kojto 122:f9eeca106725 10997 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10998 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 10999 #define I2C_ISR_ALERT_Pos (13U)
Kojto 122:f9eeca106725 11000 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11001 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
Kojto 122:f9eeca106725 11002 #define I2C_ISR_BUSY_Pos (15U)
Kojto 122:f9eeca106725 11003 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11004 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
Kojto 122:f9eeca106725 11005 #define I2C_ISR_DIR_Pos (16U)
Kojto 122:f9eeca106725 11006 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11007 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 11008 #define I2C_ISR_ADDCODE_Pos (17U)
Kojto 122:f9eeca106725 11009 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 11010 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
bogdanm 86:04dd9b1680ae 11011
bogdanm 86:04dd9b1680ae 11012 /****************** Bit definition for I2C_ICR register *********************/
Kojto 122:f9eeca106725 11013 #define I2C_ICR_ADDRCF_Pos (3U)
Kojto 122:f9eeca106725 11014 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11015 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
Kojto 122:f9eeca106725 11016 #define I2C_ICR_NACKCF_Pos (4U)
Kojto 122:f9eeca106725 11017 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11018 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
Kojto 122:f9eeca106725 11019 #define I2C_ICR_STOPCF_Pos (5U)
Kojto 122:f9eeca106725 11020 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11021 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 11022 #define I2C_ICR_BERRCF_Pos (8U)
Kojto 122:f9eeca106725 11023 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11024 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
Kojto 122:f9eeca106725 11025 #define I2C_ICR_ARLOCF_Pos (9U)
Kojto 122:f9eeca106725 11026 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11027 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 11028 #define I2C_ICR_OVRCF_Pos (10U)
Kojto 122:f9eeca106725 11029 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11030 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 11031 #define I2C_ICR_PECCF_Pos (11U)
Kojto 122:f9eeca106725 11032 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11033 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
Kojto 122:f9eeca106725 11034 #define I2C_ICR_TIMOUTCF_Pos (12U)
Kojto 122:f9eeca106725 11035 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11036 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
Kojto 122:f9eeca106725 11037 #define I2C_ICR_ALERTCF_Pos (13U)
Kojto 122:f9eeca106725 11038 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11039 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
bogdanm 86:04dd9b1680ae 11040
bogdanm 86:04dd9b1680ae 11041 /****************** Bit definition for I2C_PECR register ********************/
Kojto 122:f9eeca106725 11042 #define I2C_PECR_PEC_Pos (0U)
Kojto 122:f9eeca106725 11043 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11044 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
bogdanm 86:04dd9b1680ae 11045
bogdanm 86:04dd9b1680ae 11046 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 11047 #define I2C_RXDR_RXDATA_Pos (0U)
Kojto 122:f9eeca106725 11048 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11049 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
bogdanm 86:04dd9b1680ae 11050
bogdanm 86:04dd9b1680ae 11051 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 122:f9eeca106725 11052 #define I2C_TXDR_TXDATA_Pos (0U)
Kojto 122:f9eeca106725 11053 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11054 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
bogdanm 86:04dd9b1680ae 11055
bogdanm 86:04dd9b1680ae 11056
bogdanm 86:04dd9b1680ae 11057 /******************************************************************************/
bogdanm 86:04dd9b1680ae 11058 /* */
bogdanm 86:04dd9b1680ae 11059 /* Independent WATCHDOG (IWDG) */
bogdanm 86:04dd9b1680ae 11060 /* */
bogdanm 86:04dd9b1680ae 11061 /******************************************************************************/
bogdanm 86:04dd9b1680ae 11062 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 11063 #define IWDG_KR_KEY_Pos (0U)
Kojto 122:f9eeca106725 11064 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11065 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
bogdanm 86:04dd9b1680ae 11066
bogdanm 86:04dd9b1680ae 11067 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 11068 #define IWDG_PR_PR_Pos (0U)
Kojto 122:f9eeca106725 11069 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11070 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 11071 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11072 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11073 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
bogdanm 86:04dd9b1680ae 11074
bogdanm 86:04dd9b1680ae 11075 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 11076 #define IWDG_RLR_RL_Pos (0U)
Kojto 122:f9eeca106725 11077 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 11078 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
bogdanm 86:04dd9b1680ae 11079
bogdanm 86:04dd9b1680ae 11080 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 11081 #define IWDG_SR_PVU_Pos (0U)
Kojto 122:f9eeca106725 11082 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11083 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 11084 #define IWDG_SR_RVU_Pos (1U)
Kojto 122:f9eeca106725 11085 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11086 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
Kojto 122:f9eeca106725 11087 #define IWDG_SR_WVU_Pos (2U)
Kojto 122:f9eeca106725 11088 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11089 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
bogdanm 86:04dd9b1680ae 11090
bogdanm 86:04dd9b1680ae 11091 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 11092 #define IWDG_WINR_WIN_Pos (0U)
Kojto 122:f9eeca106725 11093 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 11094 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
bogdanm 86:04dd9b1680ae 11095
bogdanm 86:04dd9b1680ae 11096 /******************************************************************************/
bogdanm 86:04dd9b1680ae 11097 /* */
bogdanm 86:04dd9b1680ae 11098 /* Power Control */
bogdanm 86:04dd9b1680ae 11099 /* */
bogdanm 86:04dd9b1680ae 11100 /******************************************************************************/
Kojto 122:f9eeca106725 11101 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
bogdanm 86:04dd9b1680ae 11102 /******************** Bit definition for PWR_CR register ********************/
Kojto 122:f9eeca106725 11103 #define PWR_CR_LPDS_Pos (0U)
Kojto 122:f9eeca106725 11104 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11105 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
Kojto 122:f9eeca106725 11106 #define PWR_CR_PDDS_Pos (1U)
Kojto 122:f9eeca106725 11107 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11108 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 11109 #define PWR_CR_CWUF_Pos (2U)
Kojto 122:f9eeca106725 11110 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11111 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 11112 #define PWR_CR_CSBF_Pos (3U)
Kojto 122:f9eeca106725 11113 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11114 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 11115 #define PWR_CR_PVDE_Pos (4U)
Kojto 122:f9eeca106725 11116 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11117 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 11118
Kojto 122:f9eeca106725 11119 #define PWR_CR_PLS_Pos (5U)
Kojto 122:f9eeca106725 11120 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 11121 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 11122 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11123 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11124 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
bogdanm 86:04dd9b1680ae 11125
bogdanm 86:04dd9b1680ae 11126 /*!< PVD level configuration */
Kojto 122:f9eeca106725 11127 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
Kojto 122:f9eeca106725 11128 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
Kojto 122:f9eeca106725 11129 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
Kojto 122:f9eeca106725 11130 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
Kojto 122:f9eeca106725 11131 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
Kojto 122:f9eeca106725 11132 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
Kojto 122:f9eeca106725 11133 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
Kojto 122:f9eeca106725 11134 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
Kojto 122:f9eeca106725 11135
Kojto 122:f9eeca106725 11136 #define PWR_CR_DBP_Pos (8U)
Kojto 122:f9eeca106725 11137 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11138 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
bogdanm 86:04dd9b1680ae 11139
bogdanm 86:04dd9b1680ae 11140 /******************* Bit definition for PWR_CSR register ********************/
Kojto 122:f9eeca106725 11141 #define PWR_CSR_WUF_Pos (0U)
Kojto 122:f9eeca106725 11142 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11143 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
Kojto 122:f9eeca106725 11144 #define PWR_CSR_SBF_Pos (1U)
Kojto 122:f9eeca106725 11145 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11146 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
Kojto 122:f9eeca106725 11147 #define PWR_CSR_PVDO_Pos (2U)
Kojto 122:f9eeca106725 11148 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11149 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
Kojto 122:f9eeca106725 11150
Kojto 122:f9eeca106725 11151 #define PWR_CSR_EWUP1_Pos (8U)
Kojto 122:f9eeca106725 11152 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11153 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
Kojto 122:f9eeca106725 11154 #define PWR_CSR_EWUP2_Pos (9U)
Kojto 122:f9eeca106725 11155 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11156 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
Kojto 122:f9eeca106725 11157 #define PWR_CSR_EWUP3_Pos (10U)
Kojto 122:f9eeca106725 11158 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11159 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
bogdanm 86:04dd9b1680ae 11160
bogdanm 86:04dd9b1680ae 11161 /******************************************************************************/
bogdanm 86:04dd9b1680ae 11162 /* */
bogdanm 86:04dd9b1680ae 11163 /* Reset and Clock Control */
bogdanm 86:04dd9b1680ae 11164 /* */
bogdanm 86:04dd9b1680ae 11165 /******************************************************************************/
Kojto 122:f9eeca106725 11166 /*
Kojto 122:f9eeca106725 11167 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 11168 */
Kojto 122:f9eeca106725 11169
bogdanm 86:04dd9b1680ae 11170 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 11171 #define RCC_CR_HSION_Pos (0U)
Kojto 122:f9eeca106725 11172 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11173 #define RCC_CR_HSION RCC_CR_HSION_Msk
Kojto 122:f9eeca106725 11174 #define RCC_CR_HSIRDY_Pos (1U)
Kojto 122:f9eeca106725 11175 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11176 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
Kojto 122:f9eeca106725 11177
Kojto 122:f9eeca106725 11178 #define RCC_CR_HSITRIM_Pos (3U)
Kojto 122:f9eeca106725 11179 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
Kojto 122:f9eeca106725 11180 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
Kojto 122:f9eeca106725 11181 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11182 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11183 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11184 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11185 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11186
Kojto 122:f9eeca106725 11187 #define RCC_CR_HSICAL_Pos (8U)
Kojto 122:f9eeca106725 11188 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 11189 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
Kojto 122:f9eeca106725 11190 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11191 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11192 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11193 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11194 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11195 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11196 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11197 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11198
Kojto 122:f9eeca106725 11199 #define RCC_CR_HSEON_Pos (16U)
Kojto 122:f9eeca106725 11200 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11201 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
Kojto 122:f9eeca106725 11202 #define RCC_CR_HSERDY_Pos (17U)
Kojto 122:f9eeca106725 11203 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11204 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
Kojto 122:f9eeca106725 11205 #define RCC_CR_HSEBYP_Pos (18U)
Kojto 122:f9eeca106725 11206 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11207 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
Kojto 122:f9eeca106725 11208 #define RCC_CR_CSSON_Pos (19U)
Kojto 122:f9eeca106725 11209 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11210 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
Kojto 122:f9eeca106725 11211 #define RCC_CR_PLLON_Pos (24U)
Kojto 122:f9eeca106725 11212 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11213 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
Kojto 122:f9eeca106725 11214 #define RCC_CR_PLLRDY_Pos (25U)
Kojto 122:f9eeca106725 11215 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11216 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
bogdanm 86:04dd9b1680ae 11217
bogdanm 86:04dd9b1680ae 11218 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 86:04dd9b1680ae 11219 /*!< SW configuration */
Kojto 122:f9eeca106725 11220 #define RCC_CFGR_SW_Pos (0U)
Kojto 122:f9eeca106725 11221 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 11222 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 11223 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11224 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11225
Kojto 122:f9eeca106725 11226 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 11227 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 11228 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
bogdanm 86:04dd9b1680ae 11229
bogdanm 86:04dd9b1680ae 11230 /*!< SWS configuration */
Kojto 122:f9eeca106725 11231 #define RCC_CFGR_SWS_Pos (2U)
Kojto 122:f9eeca106725 11232 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 11233 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 11234 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11235 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11236
Kojto 122:f9eeca106725 11237 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 11238 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 11239 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
bogdanm 86:04dd9b1680ae 11240
bogdanm 86:04dd9b1680ae 11241 /*!< HPRE configuration */
Kojto 122:f9eeca106725 11242 #define RCC_CFGR_HPRE_Pos (4U)
Kojto 122:f9eeca106725 11243 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 11244 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 11245 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11246 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11247 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11248 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11249
Kojto 122:f9eeca106725 11250 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 11251 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 11252 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 11253 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 11254 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 11255 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 11256 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 11257 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 11258 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
bogdanm 86:04dd9b1680ae 11259
bogdanm 86:04dd9b1680ae 11260 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 11261 #define RCC_CFGR_PPRE1_Pos (8U)
Kojto 122:f9eeca106725 11262 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11263 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 11264 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11265 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11266 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11267
Kojto 122:f9eeca106725 11268 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 11269 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 11270 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 11271 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 11272 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
bogdanm 86:04dd9b1680ae 11273
bogdanm 86:04dd9b1680ae 11274 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 11275 #define RCC_CFGR_PPRE2_Pos (11U)
Kojto 122:f9eeca106725 11276 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
Kojto 122:f9eeca106725 11277 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 11278 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11279 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11280 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11281
Kojto 122:f9eeca106725 11282 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 11283 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 11284 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 11285 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 11286 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 11287
Kojto 122:f9eeca106725 11288 #define RCC_CFGR_PLLSRC_Pos (16U)
Kojto 122:f9eeca106725 11289 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11290 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
Kojto 122:f9eeca106725 11291 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 122:f9eeca106725 11292 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 11293
Kojto 122:f9eeca106725 11294 #define RCC_CFGR_PLLXTPRE_Pos (17U)
Kojto 122:f9eeca106725 11295 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11296 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
Kojto 122:f9eeca106725 11297 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 122:f9eeca106725 11298 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
bogdanm 86:04dd9b1680ae 11299
bogdanm 86:04dd9b1680ae 11300 /*!< PLLMUL configuration */
Kojto 122:f9eeca106725 11301 #define RCC_CFGR_PLLMUL_Pos (18U)
Kojto 122:f9eeca106725 11302 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
Kojto 122:f9eeca106725 11303 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 122:f9eeca106725 11304 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11305 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11306 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11307 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11308
Kojto 122:f9eeca106725 11309 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
Kojto 122:f9eeca106725 11310 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
Kojto 122:f9eeca106725 11311 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
Kojto 122:f9eeca106725 11312 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
Kojto 122:f9eeca106725 11313 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
Kojto 122:f9eeca106725 11314 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
Kojto 122:f9eeca106725 11315 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
Kojto 122:f9eeca106725 11316 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
Kojto 122:f9eeca106725 11317 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
Kojto 122:f9eeca106725 11318 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
Kojto 122:f9eeca106725 11319 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
Kojto 122:f9eeca106725 11320 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
Kojto 122:f9eeca106725 11321 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
Kojto 122:f9eeca106725 11322 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
Kojto 122:f9eeca106725 11323 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
bogdanm 86:04dd9b1680ae 11324
bogdanm 86:04dd9b1680ae 11325 /*!< MCO configuration */
Kojto 122:f9eeca106725 11326 #define RCC_CFGR_MCO_Pos (24U)
Kojto 122:f9eeca106725 11327 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 11328 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
Kojto 122:f9eeca106725 11329 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11330 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11331 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11332
Kojto 122:f9eeca106725 11333 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 11334 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
Kojto 122:f9eeca106725 11335 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
Kojto 122:f9eeca106725 11336 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
Kojto 122:f9eeca106725 11337 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
Kojto 122:f9eeca106725 11338 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
Kojto 122:f9eeca106725 11339 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 122:f9eeca106725 11340
Kojto 122:f9eeca106725 11341 #define RCC_CFGR_MCOPRE_Pos (28U)
Kojto 122:f9eeca106725 11342 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
Kojto 122:f9eeca106725 11343 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
Kojto 122:f9eeca106725 11344 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11345 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11346 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 11347
Kojto 122:f9eeca106725 11348 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
Kojto 122:f9eeca106725 11349 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
Kojto 122:f9eeca106725 11350 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
Kojto 122:f9eeca106725 11351 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
Kojto 122:f9eeca106725 11352 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
Kojto 122:f9eeca106725 11353 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
Kojto 122:f9eeca106725 11354 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
Kojto 122:f9eeca106725 11355 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
Kojto 122:f9eeca106725 11356
Kojto 122:f9eeca106725 11357 #define RCC_CFGR_PLLNODIV_Pos (31U)
Kojto 122:f9eeca106725 11358 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 11359 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */
Kojto 122:f9eeca106725 11360
Kojto 122:f9eeca106725 11361 /* Reference defines */
Kojto 122:f9eeca106725 11362 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
Kojto 122:f9eeca106725 11363 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
Kojto 122:f9eeca106725 11364 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
Kojto 122:f9eeca106725 11365 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
Kojto 122:f9eeca106725 11366 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 122:f9eeca106725 11367 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
Kojto 122:f9eeca106725 11368 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
Kojto 122:f9eeca106725 11369 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 122:f9eeca106725 11370 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
Kojto 122:f9eeca106725 11371 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
Kojto 122:f9eeca106725 11372 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
bogdanm 86:04dd9b1680ae 11373
bogdanm 86:04dd9b1680ae 11374 /********************* Bit definition for RCC_CIR register ********************/
Kojto 122:f9eeca106725 11375 #define RCC_CIR_LSIRDYF_Pos (0U)
Kojto 122:f9eeca106725 11376 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11377 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 11378 #define RCC_CIR_LSERDYF_Pos (1U)
Kojto 122:f9eeca106725 11379 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11380 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 11381 #define RCC_CIR_HSIRDYF_Pos (2U)
Kojto 122:f9eeca106725 11382 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11383 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
Kojto 122:f9eeca106725 11384 #define RCC_CIR_HSERDYF_Pos (3U)
Kojto 122:f9eeca106725 11385 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11386 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 11387 #define RCC_CIR_PLLRDYF_Pos (4U)
Kojto 122:f9eeca106725 11388 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11389 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 11390 #define RCC_CIR_CSSF_Pos (7U)
Kojto 122:f9eeca106725 11391 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11392 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 11393 #define RCC_CIR_LSIRDYIE_Pos (8U)
Kojto 122:f9eeca106725 11394 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11395 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 11396 #define RCC_CIR_LSERDYIE_Pos (9U)
Kojto 122:f9eeca106725 11397 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11398 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 11399 #define RCC_CIR_HSIRDYIE_Pos (10U)
Kojto 122:f9eeca106725 11400 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11401 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 11402 #define RCC_CIR_HSERDYIE_Pos (11U)
Kojto 122:f9eeca106725 11403 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11404 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 11405 #define RCC_CIR_PLLRDYIE_Pos (12U)
Kojto 122:f9eeca106725 11406 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11407 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
Kojto 122:f9eeca106725 11408 #define RCC_CIR_LSIRDYC_Pos (16U)
Kojto 122:f9eeca106725 11409 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11410 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 11411 #define RCC_CIR_LSERDYC_Pos (17U)
Kojto 122:f9eeca106725 11412 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11413 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 11414 #define RCC_CIR_HSIRDYC_Pos (18U)
Kojto 122:f9eeca106725 11415 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11416 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 11417 #define RCC_CIR_HSERDYC_Pos (19U)
Kojto 122:f9eeca106725 11418 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11419 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 11420 #define RCC_CIR_PLLRDYC_Pos (20U)
Kojto 122:f9eeca106725 11421 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11422 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
Kojto 122:f9eeca106725 11423 #define RCC_CIR_CSSC_Pos (23U)
Kojto 122:f9eeca106725 11424 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11425 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
bogdanm 86:04dd9b1680ae 11426
bogdanm 86:04dd9b1680ae 11427 /****************** Bit definition for RCC_APB2RSTR register *****************/
Kojto 122:f9eeca106725 11428 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
Kojto 122:f9eeca106725 11429 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11430 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
Kojto 122:f9eeca106725 11431 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
Kojto 122:f9eeca106725 11432 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11433 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
Kojto 122:f9eeca106725 11434 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
Kojto 122:f9eeca106725 11435 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11436 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
Kojto 122:f9eeca106725 11437 #define RCC_APB2RSTR_USART1RST_Pos (14U)
Kojto 122:f9eeca106725 11438 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11439 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
Kojto 122:f9eeca106725 11440 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
Kojto 122:f9eeca106725 11441 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11442 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
Kojto 122:f9eeca106725 11443 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
Kojto 122:f9eeca106725 11444 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11445 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
Kojto 122:f9eeca106725 11446 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
Kojto 122:f9eeca106725 11447 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11448 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
Kojto 122:f9eeca106725 11449 #define RCC_APB2RSTR_HRTIM1RST_Pos (29U)
Kojto 122:f9eeca106725 11450 #define RCC_APB2RSTR_HRTIM1RST_Msk (0x1U << RCC_APB2RSTR_HRTIM1RST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11451 #define RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk /*!< HRTIM1 reset */
bogdanm 86:04dd9b1680ae 11452
bogdanm 86:04dd9b1680ae 11453 /****************** Bit definition for RCC_APB1RSTR register ******************/
Kojto 122:f9eeca106725 11454 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
Kojto 122:f9eeca106725 11455 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11456 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
Kojto 122:f9eeca106725 11457 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
Kojto 122:f9eeca106725 11458 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11459 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
Kojto 122:f9eeca106725 11460 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
Kojto 122:f9eeca106725 11461 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11462 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
Kojto 122:f9eeca106725 11463 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
Kojto 122:f9eeca106725 11464 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11465 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
Kojto 122:f9eeca106725 11466 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
Kojto 122:f9eeca106725 11467 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11468 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
Kojto 122:f9eeca106725 11469 #define RCC_APB1RSTR_USART2RST_Pos (17U)
Kojto 122:f9eeca106725 11470 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11471 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
Kojto 122:f9eeca106725 11472 #define RCC_APB1RSTR_USART3RST_Pos (18U)
Kojto 122:f9eeca106725 11473 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11474 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
Kojto 122:f9eeca106725 11475 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
Kojto 122:f9eeca106725 11476 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11477 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
Kojto 122:f9eeca106725 11478 #define RCC_APB1RSTR_CANRST_Pos (25U)
Kojto 122:f9eeca106725 11479 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11480 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
Kojto 122:f9eeca106725 11481 #define RCC_APB1RSTR_DAC2RST_Pos (26U)
Kojto 122:f9eeca106725 11482 #define RCC_APB1RSTR_DAC2RST_Msk (0x1U << RCC_APB1RSTR_DAC2RST_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11483 #define RCC_APB1RSTR_DAC2RST RCC_APB1RSTR_DAC2RST_Msk /*!< DAC 2 reset */
Kojto 122:f9eeca106725 11484 #define RCC_APB1RSTR_PWRRST_Pos (28U)
Kojto 122:f9eeca106725 11485 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11486 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
Kojto 122:f9eeca106725 11487 #define RCC_APB1RSTR_DAC1RST_Pos (29U)
Kojto 122:f9eeca106725 11488 #define RCC_APB1RSTR_DAC1RST_Msk (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11489 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */
bogdanm 86:04dd9b1680ae 11490
bogdanm 86:04dd9b1680ae 11491 /****************** Bit definition for RCC_AHBENR register ******************/
Kojto 122:f9eeca106725 11492 #define RCC_AHBENR_DMA1EN_Pos (0U)
Kojto 122:f9eeca106725 11493 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11494 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
Kojto 122:f9eeca106725 11495 #define RCC_AHBENR_SRAMEN_Pos (2U)
Kojto 122:f9eeca106725 11496 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11497 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
Kojto 122:f9eeca106725 11498 #define RCC_AHBENR_FLITFEN_Pos (4U)
Kojto 122:f9eeca106725 11499 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11500 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
Kojto 122:f9eeca106725 11501 #define RCC_AHBENR_CRCEN_Pos (6U)
Kojto 122:f9eeca106725 11502 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11503 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
Kojto 122:f9eeca106725 11504 #define RCC_AHBENR_GPIOAEN_Pos (17U)
Kojto 122:f9eeca106725 11505 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11506 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
Kojto 122:f9eeca106725 11507 #define RCC_AHBENR_GPIOBEN_Pos (18U)
Kojto 122:f9eeca106725 11508 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11509 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
Kojto 122:f9eeca106725 11510 #define RCC_AHBENR_GPIOCEN_Pos (19U)
Kojto 122:f9eeca106725 11511 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11512 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
Kojto 122:f9eeca106725 11513 #define RCC_AHBENR_GPIODEN_Pos (20U)
Kojto 122:f9eeca106725 11514 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11515 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
Kojto 122:f9eeca106725 11516 #define RCC_AHBENR_GPIOFEN_Pos (22U)
Kojto 122:f9eeca106725 11517 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11518 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
Kojto 122:f9eeca106725 11519 #define RCC_AHBENR_TSCEN_Pos (24U)
Kojto 122:f9eeca106725 11520 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11521 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */
Kojto 122:f9eeca106725 11522 #define RCC_AHBENR_ADC12EN_Pos (28U)
Kojto 122:f9eeca106725 11523 #define RCC_AHBENR_ADC12EN_Msk (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11524 #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */
bogdanm 86:04dd9b1680ae 11525
bogdanm 86:04dd9b1680ae 11526 /***************** Bit definition for RCC_APB2ENR register ******************/
Kojto 122:f9eeca106725 11527 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
Kojto 122:f9eeca106725 11528 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11529 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
Kojto 122:f9eeca106725 11530 #define RCC_APB2ENR_TIM1EN_Pos (11U)
Kojto 122:f9eeca106725 11531 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11532 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
Kojto 122:f9eeca106725 11533 #define RCC_APB2ENR_SPI1EN_Pos (12U)
Kojto 122:f9eeca106725 11534 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11535 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
Kojto 122:f9eeca106725 11536 #define RCC_APB2ENR_USART1EN_Pos (14U)
Kojto 122:f9eeca106725 11537 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11538 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
Kojto 122:f9eeca106725 11539 #define RCC_APB2ENR_TIM15EN_Pos (16U)
Kojto 122:f9eeca106725 11540 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11541 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
Kojto 122:f9eeca106725 11542 #define RCC_APB2ENR_TIM16EN_Pos (17U)
Kojto 122:f9eeca106725 11543 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11544 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
Kojto 122:f9eeca106725 11545 #define RCC_APB2ENR_TIM17EN_Pos (18U)
Kojto 122:f9eeca106725 11546 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11547 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
Kojto 122:f9eeca106725 11548 #define RCC_APB2ENR_HRTIM1EN_Pos (29U)
Kojto 122:f9eeca106725 11549 #define RCC_APB2ENR_HRTIM1EN_Msk (0x1U << RCC_APB2ENR_HRTIM1EN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11550 #define RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk /*!< HRTIM1 reset */
bogdanm 86:04dd9b1680ae 11551
bogdanm 86:04dd9b1680ae 11552 /****************** Bit definition for RCC_APB1ENR register ******************/
Kojto 122:f9eeca106725 11553 #define RCC_APB1ENR_TIM2EN_Pos (0U)
Kojto 122:f9eeca106725 11554 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11555 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
Kojto 122:f9eeca106725 11556 #define RCC_APB1ENR_TIM3EN_Pos (1U)
Kojto 122:f9eeca106725 11557 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11558 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
Kojto 122:f9eeca106725 11559 #define RCC_APB1ENR_TIM6EN_Pos (4U)
Kojto 122:f9eeca106725 11560 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11561 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
Kojto 122:f9eeca106725 11562 #define RCC_APB1ENR_TIM7EN_Pos (5U)
Kojto 122:f9eeca106725 11563 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11564 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
Kojto 122:f9eeca106725 11565 #define RCC_APB1ENR_WWDGEN_Pos (11U)
Kojto 122:f9eeca106725 11566 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11567 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
Kojto 122:f9eeca106725 11568 #define RCC_APB1ENR_USART2EN_Pos (17U)
Kojto 122:f9eeca106725 11569 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11570 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
Kojto 122:f9eeca106725 11571 #define RCC_APB1ENR_USART3EN_Pos (18U)
Kojto 122:f9eeca106725 11572 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11573 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
Kojto 122:f9eeca106725 11574 #define RCC_APB1ENR_I2C1EN_Pos (21U)
Kojto 122:f9eeca106725 11575 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11576 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
Kojto 122:f9eeca106725 11577 #define RCC_APB1ENR_CANEN_Pos (25U)
Kojto 122:f9eeca106725 11578 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11579 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
Kojto 122:f9eeca106725 11580 #define RCC_APB1ENR_DAC2EN_Pos (26U)
Kojto 122:f9eeca106725 11581 #define RCC_APB1ENR_DAC2EN_Msk (0x1U << RCC_APB1ENR_DAC2EN_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11582 #define RCC_APB1ENR_DAC2EN RCC_APB1ENR_DAC2EN_Msk /*!< DAC 2 clock enable */
Kojto 122:f9eeca106725 11583 #define RCC_APB1ENR_PWREN_Pos (28U)
Kojto 122:f9eeca106725 11584 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11585 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
Kojto 122:f9eeca106725 11586 #define RCC_APB1ENR_DAC1EN_Pos (29U)
Kojto 122:f9eeca106725 11587 #define RCC_APB1ENR_DAC1EN_Msk (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11588 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */
bogdanm 86:04dd9b1680ae 11589
bogdanm 86:04dd9b1680ae 11590 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 11591 #define RCC_BDCR_LSE_Pos (0U)
Kojto 122:f9eeca106725 11592 #define RCC_BDCR_LSE_Msk (0x7U << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11593 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */
Kojto 122:f9eeca106725 11594 #define RCC_BDCR_LSEON_Pos (0U)
Kojto 122:f9eeca106725 11595 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11596 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
Kojto 122:f9eeca106725 11597 #define RCC_BDCR_LSERDY_Pos (1U)
Kojto 122:f9eeca106725 11598 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11599 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
Kojto 122:f9eeca106725 11600 #define RCC_BDCR_LSEBYP_Pos (2U)
Kojto 122:f9eeca106725 11601 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11602 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
Kojto 122:f9eeca106725 11603
Kojto 122:f9eeca106725 11604 #define RCC_BDCR_LSEDRV_Pos (3U)
Kojto 122:f9eeca106725 11605 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 11606 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 122:f9eeca106725 11607 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11608 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11609
Kojto 122:f9eeca106725 11610 #define RCC_BDCR_RTCSEL_Pos (8U)
Kojto 122:f9eeca106725 11611 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 11612 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 122:f9eeca106725 11613 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11614 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
bogdanm 86:04dd9b1680ae 11615
bogdanm 86:04dd9b1680ae 11616 /*!< RTC configuration */
Kojto 122:f9eeca106725 11617 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 11618 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 11619 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 11620 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 122:f9eeca106725 11621
Kojto 122:f9eeca106725 11622 #define RCC_BDCR_RTCEN_Pos (15U)
Kojto 122:f9eeca106725 11623 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11624 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
Kojto 122:f9eeca106725 11625 #define RCC_BDCR_BDRST_Pos (16U)
Kojto 122:f9eeca106725 11626 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11627 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
bogdanm 86:04dd9b1680ae 11628
bogdanm 86:04dd9b1680ae 11629 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 11630 #define RCC_CSR_LSION_Pos (0U)
Kojto 122:f9eeca106725 11631 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11632 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
Kojto 122:f9eeca106725 11633 #define RCC_CSR_LSIRDY_Pos (1U)
Kojto 122:f9eeca106725 11634 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11635 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
Kojto 122:f9eeca106725 11636 #define RCC_CSR_V18PWRRSTF_Pos (23U)
Kojto 122:f9eeca106725 11637 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11638 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
Kojto 122:f9eeca106725 11639 #define RCC_CSR_RMVF_Pos (24U)
Kojto 122:f9eeca106725 11640 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11641 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
Kojto 122:f9eeca106725 11642 #define RCC_CSR_OBLRSTF_Pos (25U)
Kojto 122:f9eeca106725 11643 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11644 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
Kojto 122:f9eeca106725 11645 #define RCC_CSR_PINRSTF_Pos (26U)
Kojto 122:f9eeca106725 11646 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11647 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
Kojto 122:f9eeca106725 11648 #define RCC_CSR_PORRSTF_Pos (27U)
Kojto 122:f9eeca106725 11649 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 11650 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
Kojto 122:f9eeca106725 11651 #define RCC_CSR_SFTRSTF_Pos (28U)
Kojto 122:f9eeca106725 11652 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11653 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
Kojto 122:f9eeca106725 11654 #define RCC_CSR_IWDGRSTF_Pos (29U)
Kojto 122:f9eeca106725 11655 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 11656 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 11657 #define RCC_CSR_WWDGRSTF_Pos (30U)
Kojto 122:f9eeca106725 11658 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 11659 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 11660 #define RCC_CSR_LPWRRSTF_Pos (31U)
Kojto 122:f9eeca106725 11661 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 11662 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
bogdanm 86:04dd9b1680ae 11663
bogdanm 86:04dd9b1680ae 11664 /******************* Bit definition for RCC_AHBRSTR register ****************/
Kojto 122:f9eeca106725 11665 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
Kojto 122:f9eeca106725 11666 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11667 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
Kojto 122:f9eeca106725 11668 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
Kojto 122:f9eeca106725 11669 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11670 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
Kojto 122:f9eeca106725 11671 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
Kojto 122:f9eeca106725 11672 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11673 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
Kojto 122:f9eeca106725 11674 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
Kojto 122:f9eeca106725 11675 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11676 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
Kojto 122:f9eeca106725 11677 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
Kojto 122:f9eeca106725 11678 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11679 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
Kojto 122:f9eeca106725 11680 #define RCC_AHBRSTR_TSCRST_Pos (24U)
Kojto 122:f9eeca106725 11681 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11682 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
Kojto 122:f9eeca106725 11683 #define RCC_AHBRSTR_ADC12RST_Pos (28U)
Kojto 122:f9eeca106725 11684 #define RCC_AHBRSTR_ADC12RST_Msk (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11685 #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */
bogdanm 86:04dd9b1680ae 11686
bogdanm 86:04dd9b1680ae 11687 /******************* Bit definition for RCC_CFGR2 register ******************/
bogdanm 86:04dd9b1680ae 11688 /*!< PREDIV configuration */
Kojto 122:f9eeca106725 11689 #define RCC_CFGR2_PREDIV_Pos (0U)
Kojto 122:f9eeca106725 11690 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 11691 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
Kojto 122:f9eeca106725 11692 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11693 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11694 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11695 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11696
Kojto 122:f9eeca106725 11697 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
Kojto 122:f9eeca106725 11698 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
Kojto 122:f9eeca106725 11699 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
Kojto 122:f9eeca106725 11700 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
Kojto 122:f9eeca106725 11701 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
Kojto 122:f9eeca106725 11702 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
Kojto 122:f9eeca106725 11703 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
Kojto 122:f9eeca106725 11704 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
Kojto 122:f9eeca106725 11705 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
Kojto 122:f9eeca106725 11706 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
Kojto 122:f9eeca106725 11707 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
Kojto 122:f9eeca106725 11708 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
Kojto 122:f9eeca106725 11709 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
Kojto 122:f9eeca106725 11710 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
Kojto 122:f9eeca106725 11711 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
Kojto 122:f9eeca106725 11712 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
bogdanm 86:04dd9b1680ae 11713
bogdanm 86:04dd9b1680ae 11714 /*!< ADCPRE12 configuration */
Kojto 122:f9eeca106725 11715 #define RCC_CFGR2_ADCPRE12_Pos (4U)
Kojto 122:f9eeca106725 11716 #define RCC_CFGR2_ADCPRE12_Msk (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
Kojto 122:f9eeca106725 11717 #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */
Kojto 122:f9eeca106725 11718 #define RCC_CFGR2_ADCPRE12_0 (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11719 #define RCC_CFGR2_ADCPRE12_1 (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11720 #define RCC_CFGR2_ADCPRE12_2 (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11721 #define RCC_CFGR2_ADCPRE12_3 (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11722 #define RCC_CFGR2_ADCPRE12_4 (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11723
Kojto 122:f9eeca106725 11724 #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
Kojto 122:f9eeca106725 11725 #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */
Kojto 122:f9eeca106725 11726 #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */
Kojto 122:f9eeca106725 11727 #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */
Kojto 122:f9eeca106725 11728 #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */
Kojto 122:f9eeca106725 11729 #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */
Kojto 122:f9eeca106725 11730 #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */
Kojto 122:f9eeca106725 11731 #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */
Kojto 122:f9eeca106725 11732 #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */
Kojto 122:f9eeca106725 11733 #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */
Kojto 122:f9eeca106725 11734 #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */
Kojto 122:f9eeca106725 11735 #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */
Kojto 122:f9eeca106725 11736 #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */
bogdanm 86:04dd9b1680ae 11737
bogdanm 86:04dd9b1680ae 11738 /******************* Bit definition for RCC_CFGR3 register ******************/
Kojto 122:f9eeca106725 11739 #define RCC_CFGR3_USART1SW_Pos (0U)
Kojto 122:f9eeca106725 11740 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 11741 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
Kojto 122:f9eeca106725 11742 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11743 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11744
Kojto 122:f9eeca106725 11745 #define RCC_CFGR3_USART1SW_PCLK1 (0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
Kojto 122:f9eeca106725 11746 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
Kojto 122:f9eeca106725 11747 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 122:f9eeca106725 11748 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 122:f9eeca106725 11749 /* Legacy defines */
Kojto 122:f9eeca106725 11750 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
Kojto 122:f9eeca106725 11751
Kojto 122:f9eeca106725 11752 #define RCC_CFGR3_I2CSW_Pos (4U)
Kojto 122:f9eeca106725 11753 #define RCC_CFGR3_I2CSW_Msk (0x1U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11754 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */
Kojto 122:f9eeca106725 11755 #define RCC_CFGR3_I2C1SW_Pos (4U)
Kojto 122:f9eeca106725 11756 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11757 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
Kojto 122:f9eeca106725 11758
Kojto 122:f9eeca106725 11759 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 122:f9eeca106725 11760 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
Kojto 122:f9eeca106725 11761 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11762 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
Kojto 122:f9eeca106725 11763 #define RCC_CFGR3_TIMSW_Pos (8U)
Kojto 122:f9eeca106725 11764 #define RCC_CFGR3_TIMSW_Msk (0x1U << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11765 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Kojto 122:f9eeca106725 11766 #define RCC_CFGR3_TIM1SW_Pos (8U)
Kojto 122:f9eeca106725 11767 #define RCC_CFGR3_TIM1SW_Msk (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11768 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */
Kojto 122:f9eeca106725 11769 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */
Kojto 122:f9eeca106725 11770 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U)
Kojto 122:f9eeca106725 11771 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11772 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */
Kojto 122:f9eeca106725 11773
Kojto 122:f9eeca106725 11774 #define RCC_CFGR3_HRTIMSW_Pos (12U)
Kojto 122:f9eeca106725 11775 #define RCC_CFGR3_HRTIMSW_Msk (0x1U << RCC_CFGR3_HRTIMSW_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11776 #define RCC_CFGR3_HRTIMSW RCC_CFGR3_HRTIMSW_Msk /*!< HRTIM1SW bits */
Kojto 122:f9eeca106725 11777 #define RCC_CFGR3_HRTIM1SW_Pos (12U)
Kojto 122:f9eeca106725 11778 #define RCC_CFGR3_HRTIM1SW_Msk (0x1U << RCC_CFGR3_HRTIM1SW_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11779 #define RCC_CFGR3_HRTIM1SW RCC_CFGR3_HRTIM1SW_Msk /*!< HRTIM1SW bits */
Kojto 122:f9eeca106725 11780
Kojto 122:f9eeca106725 11781 #define RCC_CFGR3_HRTIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as HRTIM1 clock source */
Kojto 122:f9eeca106725 11782 #define RCC_CFGR3_HRTIM1SW_PLL_Pos (12U)
Kojto 122:f9eeca106725 11783 #define RCC_CFGR3_HRTIM1SW_PLL_Msk (0x1U << RCC_CFGR3_HRTIM1SW_PLL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11784 #define RCC_CFGR3_HRTIM1SW_PLL RCC_CFGR3_HRTIM1SW_PLL_Msk /*!< PLL clock used as HRTIM1 clock source */
Kojto 122:f9eeca106725 11785
Kojto 122:f9eeca106725 11786 /* Legacy defines */
Kojto 122:f9eeca106725 11787 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2
Kojto 122:f9eeca106725 11788 #define RCC_CFGR3_HRTIM1SW_HCLK RCC_CFGR3_HRTIM1SW_PCLK2
bogdanm 86:04dd9b1680ae 11789
bogdanm 86:04dd9b1680ae 11790 /******************************************************************************/
bogdanm 86:04dd9b1680ae 11791 /* */
bogdanm 86:04dd9b1680ae 11792 /* Real-Time Clock (RTC) */
bogdanm 86:04dd9b1680ae 11793 /* */
bogdanm 86:04dd9b1680ae 11794 /******************************************************************************/
Kojto 122:f9eeca106725 11795 /*
Kojto 122:f9eeca106725 11796 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 11797 */
Kojto 122:f9eeca106725 11798 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
Kojto 122:f9eeca106725 11799 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Kojto 122:f9eeca106725 11800 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
Kojto 122:f9eeca106725 11801 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
Kojto 122:f9eeca106725 11802
bogdanm 86:04dd9b1680ae 11803 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 11804 #define RTC_TR_PM_Pos (22U)
Kojto 122:f9eeca106725 11805 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11806 #define RTC_TR_PM RTC_TR_PM_Msk
Kojto 122:f9eeca106725 11807 #define RTC_TR_HT_Pos (20U)
Kojto 122:f9eeca106725 11808 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 11809 #define RTC_TR_HT RTC_TR_HT_Msk
Kojto 122:f9eeca106725 11810 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11811 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11812 #define RTC_TR_HU_Pos (16U)
Kojto 122:f9eeca106725 11813 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 11814 #define RTC_TR_HU RTC_TR_HU_Msk
Kojto 122:f9eeca106725 11815 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11816 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11817 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11818 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11819 #define RTC_TR_MNT_Pos (12U)
Kojto 122:f9eeca106725 11820 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 11821 #define RTC_TR_MNT RTC_TR_MNT_Msk
Kojto 122:f9eeca106725 11822 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11823 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11824 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11825 #define RTC_TR_MNU_Pos (8U)
Kojto 122:f9eeca106725 11826 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 11827 #define RTC_TR_MNU RTC_TR_MNU_Msk
Kojto 122:f9eeca106725 11828 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11829 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11830 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11831 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11832 #define RTC_TR_ST_Pos (4U)
Kojto 122:f9eeca106725 11833 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11834 #define RTC_TR_ST RTC_TR_ST_Msk
Kojto 122:f9eeca106725 11835 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11836 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11837 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11838 #define RTC_TR_SU_Pos (0U)
Kojto 122:f9eeca106725 11839 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 11840 #define RTC_TR_SU RTC_TR_SU_Msk
Kojto 122:f9eeca106725 11841 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11842 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11843 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11844 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 11845
bogdanm 86:04dd9b1680ae 11846 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 11847 #define RTC_DR_YT_Pos (20U)
Kojto 122:f9eeca106725 11848 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 11849 #define RTC_DR_YT RTC_DR_YT_Msk
Kojto 122:f9eeca106725 11850 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11851 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11852 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11853 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11854 #define RTC_DR_YU_Pos (16U)
Kojto 122:f9eeca106725 11855 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 11856 #define RTC_DR_YU RTC_DR_YU_Msk
Kojto 122:f9eeca106725 11857 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11858 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11859 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11860 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11861 #define RTC_DR_WDU_Pos (13U)
Kojto 122:f9eeca106725 11862 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 11863 #define RTC_DR_WDU RTC_DR_WDU_Msk
Kojto 122:f9eeca106725 11864 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11865 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11866 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11867 #define RTC_DR_MT_Pos (12U)
Kojto 122:f9eeca106725 11868 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11869 #define RTC_DR_MT RTC_DR_MT_Msk
Kojto 122:f9eeca106725 11870 #define RTC_DR_MU_Pos (8U)
Kojto 122:f9eeca106725 11871 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 11872 #define RTC_DR_MU RTC_DR_MU_Msk
Kojto 122:f9eeca106725 11873 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11874 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11875 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11876 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11877 #define RTC_DR_DT_Pos (4U)
Kojto 122:f9eeca106725 11878 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 11879 #define RTC_DR_DT RTC_DR_DT_Msk
Kojto 122:f9eeca106725 11880 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11881 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11882 #define RTC_DR_DU_Pos (0U)
Kojto 122:f9eeca106725 11883 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 11884 #define RTC_DR_DU RTC_DR_DU_Msk
Kojto 122:f9eeca106725 11885 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11886 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11887 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11888 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 11889
bogdanm 86:04dd9b1680ae 11890 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 11891 #define RTC_CR_COE_Pos (23U)
Kojto 122:f9eeca106725 11892 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11893 #define RTC_CR_COE RTC_CR_COE_Msk
Kojto 122:f9eeca106725 11894 #define RTC_CR_OSEL_Pos (21U)
Kojto 122:f9eeca106725 11895 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 11896 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
Kojto 122:f9eeca106725 11897 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11898 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11899 #define RTC_CR_POL_Pos (20U)
Kojto 122:f9eeca106725 11900 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11901 #define RTC_CR_POL RTC_CR_POL_Msk
Kojto 122:f9eeca106725 11902 #define RTC_CR_COSEL_Pos (19U)
Kojto 122:f9eeca106725 11903 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11904 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
Kojto 122:f9eeca106725 11905 #define RTC_CR_BCK_Pos (18U)
Kojto 122:f9eeca106725 11906 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11907 #define RTC_CR_BCK RTC_CR_BCK_Msk
Kojto 122:f9eeca106725 11908 #define RTC_CR_SUB1H_Pos (17U)
Kojto 122:f9eeca106725 11909 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11910 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
Kojto 122:f9eeca106725 11911 #define RTC_CR_ADD1H_Pos (16U)
Kojto 122:f9eeca106725 11912 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11913 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
Kojto 122:f9eeca106725 11914 #define RTC_CR_TSIE_Pos (15U)
Kojto 122:f9eeca106725 11915 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11916 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
Kojto 122:f9eeca106725 11917 #define RTC_CR_WUTIE_Pos (14U)
Kojto 122:f9eeca106725 11918 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11919 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
Kojto 122:f9eeca106725 11920 #define RTC_CR_ALRBIE_Pos (13U)
Kojto 122:f9eeca106725 11921 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11922 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
Kojto 122:f9eeca106725 11923 #define RTC_CR_ALRAIE_Pos (12U)
Kojto 122:f9eeca106725 11924 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11925 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
Kojto 122:f9eeca106725 11926 #define RTC_CR_TSE_Pos (11U)
Kojto 122:f9eeca106725 11927 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11928 #define RTC_CR_TSE RTC_CR_TSE_Msk
Kojto 122:f9eeca106725 11929 #define RTC_CR_WUTE_Pos (10U)
Kojto 122:f9eeca106725 11930 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11931 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
Kojto 122:f9eeca106725 11932 #define RTC_CR_ALRBE_Pos (9U)
Kojto 122:f9eeca106725 11933 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11934 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
Kojto 122:f9eeca106725 11935 #define RTC_CR_ALRAE_Pos (8U)
Kojto 122:f9eeca106725 11936 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11937 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
Kojto 122:f9eeca106725 11938 #define RTC_CR_FMT_Pos (6U)
Kojto 122:f9eeca106725 11939 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11940 #define RTC_CR_FMT RTC_CR_FMT_Msk
Kojto 122:f9eeca106725 11941 #define RTC_CR_BYPSHAD_Pos (5U)
Kojto 122:f9eeca106725 11942 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11943 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
Kojto 122:f9eeca106725 11944 #define RTC_CR_REFCKON_Pos (4U)
Kojto 122:f9eeca106725 11945 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11946 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
Kojto 122:f9eeca106725 11947 #define RTC_CR_TSEDGE_Pos (3U)
Kojto 122:f9eeca106725 11948 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11949 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
Kojto 122:f9eeca106725 11950 #define RTC_CR_WUCKSEL_Pos (0U)
Kojto 122:f9eeca106725 11951 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11952 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
Kojto 122:f9eeca106725 11953 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11954 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11955 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
bogdanm 86:04dd9b1680ae 11956
bogdanm 86:04dd9b1680ae 11957 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 11958 #define RTC_ISR_RECALPF_Pos (16U)
Kojto 122:f9eeca106725 11959 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11960 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
Kojto 122:f9eeca106725 11961 #define RTC_ISR_TAMP2F_Pos (14U)
Kojto 122:f9eeca106725 11962 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11963 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
Kojto 122:f9eeca106725 11964 #define RTC_ISR_TAMP1F_Pos (13U)
Kojto 122:f9eeca106725 11965 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11966 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
Kojto 122:f9eeca106725 11967 #define RTC_ISR_TSOVF_Pos (12U)
Kojto 122:f9eeca106725 11968 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11969 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
Kojto 122:f9eeca106725 11970 #define RTC_ISR_TSF_Pos (11U)
Kojto 122:f9eeca106725 11971 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11972 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
Kojto 122:f9eeca106725 11973 #define RTC_ISR_WUTF_Pos (10U)
Kojto 122:f9eeca106725 11974 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11975 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
Kojto 122:f9eeca106725 11976 #define RTC_ISR_ALRBF_Pos (9U)
Kojto 122:f9eeca106725 11977 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11978 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
Kojto 122:f9eeca106725 11979 #define RTC_ISR_ALRAF_Pos (8U)
Kojto 122:f9eeca106725 11980 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11981 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
Kojto 122:f9eeca106725 11982 #define RTC_ISR_INIT_Pos (7U)
Kojto 122:f9eeca106725 11983 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11984 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
Kojto 122:f9eeca106725 11985 #define RTC_ISR_INITF_Pos (6U)
Kojto 122:f9eeca106725 11986 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11987 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
Kojto 122:f9eeca106725 11988 #define RTC_ISR_RSF_Pos (5U)
Kojto 122:f9eeca106725 11989 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11990 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
Kojto 122:f9eeca106725 11991 #define RTC_ISR_INITS_Pos (4U)
Kojto 122:f9eeca106725 11992 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11993 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
Kojto 122:f9eeca106725 11994 #define RTC_ISR_SHPF_Pos (3U)
Kojto 122:f9eeca106725 11995 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11996 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
Kojto 122:f9eeca106725 11997 #define RTC_ISR_WUTWF_Pos (2U)
Kojto 122:f9eeca106725 11998 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11999 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
Kojto 122:f9eeca106725 12000 #define RTC_ISR_ALRBWF_Pos (1U)
Kojto 122:f9eeca106725 12001 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12002 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
Kojto 122:f9eeca106725 12003 #define RTC_ISR_ALRAWF_Pos (0U)
Kojto 122:f9eeca106725 12004 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12005 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
bogdanm 86:04dd9b1680ae 12006
bogdanm 86:04dd9b1680ae 12007 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 12008 #define RTC_PRER_PREDIV_A_Pos (16U)
Kojto 122:f9eeca106725 12009 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 12010 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
Kojto 122:f9eeca106725 12011 #define RTC_PRER_PREDIV_S_Pos (0U)
Kojto 122:f9eeca106725 12012 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 12013 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
bogdanm 86:04dd9b1680ae 12014
bogdanm 86:04dd9b1680ae 12015 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 12016 #define RTC_WUTR_WUT_Pos (0U)
Kojto 122:f9eeca106725 12017 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12018 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
bogdanm 86:04dd9b1680ae 12019
bogdanm 86:04dd9b1680ae 12020 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 12021 #define RTC_ALRMAR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 12022 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12023 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
Kojto 122:f9eeca106725 12024 #define RTC_ALRMAR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 12025 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12026 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
Kojto 122:f9eeca106725 12027 #define RTC_ALRMAR_DT_Pos (28U)
Kojto 122:f9eeca106725 12028 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 12029 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
Kojto 122:f9eeca106725 12030 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 12031 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 12032 #define RTC_ALRMAR_DU_Pos (24U)
Kojto 122:f9eeca106725 12033 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 12034 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
Kojto 122:f9eeca106725 12035 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12036 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12037 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12038 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12039 #define RTC_ALRMAR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 12040 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12041 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
Kojto 122:f9eeca106725 12042 #define RTC_ALRMAR_PM_Pos (22U)
Kojto 122:f9eeca106725 12043 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12044 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
Kojto 122:f9eeca106725 12045 #define RTC_ALRMAR_HT_Pos (20U)
Kojto 122:f9eeca106725 12046 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 12047 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
Kojto 122:f9eeca106725 12048 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12049 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12050 #define RTC_ALRMAR_HU_Pos (16U)
Kojto 122:f9eeca106725 12051 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 12052 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
Kojto 122:f9eeca106725 12053 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12054 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12055 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12056 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12057 #define RTC_ALRMAR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 12058 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12059 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
Kojto 122:f9eeca106725 12060 #define RTC_ALRMAR_MNT_Pos (12U)
Kojto 122:f9eeca106725 12061 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 12062 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
Kojto 122:f9eeca106725 12063 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12064 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12065 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12066 #define RTC_ALRMAR_MNU_Pos (8U)
Kojto 122:f9eeca106725 12067 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12068 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
Kojto 122:f9eeca106725 12069 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12070 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12071 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12072 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12073 #define RTC_ALRMAR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 12074 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12075 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
Kojto 122:f9eeca106725 12076 #define RTC_ALRMAR_ST_Pos (4U)
Kojto 122:f9eeca106725 12077 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 12078 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
Kojto 122:f9eeca106725 12079 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12080 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12081 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12082 #define RTC_ALRMAR_SU_Pos (0U)
Kojto 122:f9eeca106725 12083 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12084 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
Kojto 122:f9eeca106725 12085 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12086 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12087 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12088 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 12089
bogdanm 86:04dd9b1680ae 12090 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 12091 #define RTC_ALRMBR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 12092 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12093 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
Kojto 122:f9eeca106725 12094 #define RTC_ALRMBR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 12095 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12096 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
Kojto 122:f9eeca106725 12097 #define RTC_ALRMBR_DT_Pos (28U)
Kojto 122:f9eeca106725 12098 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 12099 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
Kojto 122:f9eeca106725 12100 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 12101 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 12102 #define RTC_ALRMBR_DU_Pos (24U)
Kojto 122:f9eeca106725 12103 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 12104 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
Kojto 122:f9eeca106725 12105 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12106 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12107 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12108 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12109 #define RTC_ALRMBR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 12110 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12111 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
Kojto 122:f9eeca106725 12112 #define RTC_ALRMBR_PM_Pos (22U)
Kojto 122:f9eeca106725 12113 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12114 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
Kojto 122:f9eeca106725 12115 #define RTC_ALRMBR_HT_Pos (20U)
Kojto 122:f9eeca106725 12116 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 12117 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
Kojto 122:f9eeca106725 12118 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12119 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12120 #define RTC_ALRMBR_HU_Pos (16U)
Kojto 122:f9eeca106725 12121 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 12122 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
Kojto 122:f9eeca106725 12123 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12124 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12125 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12126 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12127 #define RTC_ALRMBR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 12128 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12129 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
Kojto 122:f9eeca106725 12130 #define RTC_ALRMBR_MNT_Pos (12U)
Kojto 122:f9eeca106725 12131 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 12132 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
Kojto 122:f9eeca106725 12133 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12134 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12135 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12136 #define RTC_ALRMBR_MNU_Pos (8U)
Kojto 122:f9eeca106725 12137 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12138 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
Kojto 122:f9eeca106725 12139 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12140 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12141 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12142 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12143 #define RTC_ALRMBR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 12144 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12145 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
Kojto 122:f9eeca106725 12146 #define RTC_ALRMBR_ST_Pos (4U)
Kojto 122:f9eeca106725 12147 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 12148 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
Kojto 122:f9eeca106725 12149 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12150 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12151 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12152 #define RTC_ALRMBR_SU_Pos (0U)
Kojto 122:f9eeca106725 12153 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12154 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
Kojto 122:f9eeca106725 12155 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12156 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12157 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12158 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 12159
bogdanm 86:04dd9b1680ae 12160 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 12161 #define RTC_WPR_KEY_Pos (0U)
Kojto 122:f9eeca106725 12162 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 12163 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
bogdanm 86:04dd9b1680ae 12164
bogdanm 86:04dd9b1680ae 12165 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 12166 #define RTC_SSR_SS_Pos (0U)
Kojto 122:f9eeca106725 12167 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12168 #define RTC_SSR_SS RTC_SSR_SS_Msk
bogdanm 86:04dd9b1680ae 12169
bogdanm 86:04dd9b1680ae 12170 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 12171 #define RTC_SHIFTR_SUBFS_Pos (0U)
Kojto 122:f9eeca106725 12172 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 12173 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
Kojto 122:f9eeca106725 12174 #define RTC_SHIFTR_ADD1S_Pos (31U)
Kojto 122:f9eeca106725 12175 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12176 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
bogdanm 86:04dd9b1680ae 12177
bogdanm 86:04dd9b1680ae 12178 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 12179 #define RTC_TSTR_PM_Pos (22U)
Kojto 122:f9eeca106725 12180 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12181 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
Kojto 122:f9eeca106725 12182 #define RTC_TSTR_HT_Pos (20U)
Kojto 122:f9eeca106725 12183 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 12184 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
Kojto 122:f9eeca106725 12185 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12186 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12187 #define RTC_TSTR_HU_Pos (16U)
Kojto 122:f9eeca106725 12188 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 12189 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
Kojto 122:f9eeca106725 12190 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12191 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12192 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12193 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12194 #define RTC_TSTR_MNT_Pos (12U)
Kojto 122:f9eeca106725 12195 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 12196 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
Kojto 122:f9eeca106725 12197 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12198 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12199 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12200 #define RTC_TSTR_MNU_Pos (8U)
Kojto 122:f9eeca106725 12201 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12202 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
Kojto 122:f9eeca106725 12203 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12204 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12205 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12206 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12207 #define RTC_TSTR_ST_Pos (4U)
Kojto 122:f9eeca106725 12208 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 12209 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
Kojto 122:f9eeca106725 12210 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12211 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12212 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12213 #define RTC_TSTR_SU_Pos (0U)
Kojto 122:f9eeca106725 12214 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12215 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
Kojto 122:f9eeca106725 12216 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12217 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12218 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12219 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 12220
bogdanm 86:04dd9b1680ae 12221 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 12222 #define RTC_TSDR_WDU_Pos (13U)
Kojto 122:f9eeca106725 12223 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 12224 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
Kojto 122:f9eeca106725 12225 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12226 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12227 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12228 #define RTC_TSDR_MT_Pos (12U)
Kojto 122:f9eeca106725 12229 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12230 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
Kojto 122:f9eeca106725 12231 #define RTC_TSDR_MU_Pos (8U)
Kojto 122:f9eeca106725 12232 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12233 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
Kojto 122:f9eeca106725 12234 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12235 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12236 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12237 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12238 #define RTC_TSDR_DT_Pos (4U)
Kojto 122:f9eeca106725 12239 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 12240 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
Kojto 122:f9eeca106725 12241 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12242 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12243 #define RTC_TSDR_DU_Pos (0U)
Kojto 122:f9eeca106725 12244 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12245 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
Kojto 122:f9eeca106725 12246 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12247 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12248 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12249 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 12250
bogdanm 86:04dd9b1680ae 12251 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 12252 #define RTC_TSSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 12253 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12254 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
bogdanm 86:04dd9b1680ae 12255
bogdanm 86:04dd9b1680ae 12256 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 12257 #define RTC_CALR_CALP_Pos (15U)
Kojto 122:f9eeca106725 12258 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12259 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
Kojto 122:f9eeca106725 12260 #define RTC_CALR_CALW8_Pos (14U)
Kojto 122:f9eeca106725 12261 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12262 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
Kojto 122:f9eeca106725 12263 #define RTC_CALR_CALW16_Pos (13U)
Kojto 122:f9eeca106725 12264 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12265 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
Kojto 122:f9eeca106725 12266 #define RTC_CALR_CALM_Pos (0U)
Kojto 122:f9eeca106725 12267 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 12268 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
Kojto 122:f9eeca106725 12269 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12270 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12271 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12272 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12273 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12274 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12275 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12276 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12277 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
bogdanm 86:04dd9b1680ae 12278
bogdanm 86:04dd9b1680ae 12279 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 122:f9eeca106725 12280 #define RTC_TAFCR_PC15MODE_Pos (23U)
Kojto 122:f9eeca106725 12281 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12282 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
Kojto 122:f9eeca106725 12283 #define RTC_TAFCR_PC15VALUE_Pos (22U)
Kojto 122:f9eeca106725 12284 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12285 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
Kojto 122:f9eeca106725 12286 #define RTC_TAFCR_PC14MODE_Pos (21U)
Kojto 122:f9eeca106725 12287 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12288 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
Kojto 122:f9eeca106725 12289 #define RTC_TAFCR_PC14VALUE_Pos (20U)
Kojto 122:f9eeca106725 12290 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12291 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
Kojto 122:f9eeca106725 12292 #define RTC_TAFCR_PC13MODE_Pos (19U)
Kojto 122:f9eeca106725 12293 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12294 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
Kojto 122:f9eeca106725 12295 #define RTC_TAFCR_PC13VALUE_Pos (18U)
Kojto 122:f9eeca106725 12296 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12297 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
Kojto 122:f9eeca106725 12298 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
Kojto 122:f9eeca106725 12299 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12300 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
Kojto 122:f9eeca106725 12301 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
Kojto 122:f9eeca106725 12302 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 12303 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
Kojto 122:f9eeca106725 12304 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12305 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12306 #define RTC_TAFCR_TAMPFLT_Pos (11U)
Kojto 122:f9eeca106725 12307 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 12308 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
Kojto 122:f9eeca106725 12309 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12310 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12311 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
Kojto 122:f9eeca106725 12312 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 12313 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
Kojto 122:f9eeca106725 12314 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12315 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12316 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12317 #define RTC_TAFCR_TAMPTS_Pos (7U)
Kojto 122:f9eeca106725 12318 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12319 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
Kojto 122:f9eeca106725 12320 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
Kojto 122:f9eeca106725 12321 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12322 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
Kojto 122:f9eeca106725 12323 #define RTC_TAFCR_TAMP2E_Pos (3U)
Kojto 122:f9eeca106725 12324 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12325 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
Kojto 122:f9eeca106725 12326 #define RTC_TAFCR_TAMPIE_Pos (2U)
Kojto 122:f9eeca106725 12327 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12328 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
Kojto 122:f9eeca106725 12329 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
Kojto 122:f9eeca106725 12330 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12331 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
Kojto 122:f9eeca106725 12332 #define RTC_TAFCR_TAMP1E_Pos (0U)
Kojto 122:f9eeca106725 12333 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12334 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
Kojto 122:f9eeca106725 12335
Kojto 122:f9eeca106725 12336 /* Reference defines */
Kojto 122:f9eeca106725 12337 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
bogdanm 86:04dd9b1680ae 12338
bogdanm 86:04dd9b1680ae 12339 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 12340 #define RTC_ALRMASSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 12341 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 12342 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
Kojto 122:f9eeca106725 12343 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12344 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12345 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12346 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12347 #define RTC_ALRMASSR_SS_Pos (0U)
Kojto 122:f9eeca106725 12348 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 12349 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
bogdanm 86:04dd9b1680ae 12350
bogdanm 86:04dd9b1680ae 12351 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 12352 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 12353 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 12354 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
Kojto 122:f9eeca106725 12355 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12356 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12357 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12358 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12359 #define RTC_ALRMBSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 12360 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 12361 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
bogdanm 86:04dd9b1680ae 12362
bogdanm 86:04dd9b1680ae 12363 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 12364 #define RTC_BKP0R_Pos (0U)
Kojto 122:f9eeca106725 12365 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12366 #define RTC_BKP0R RTC_BKP0R_Msk
bogdanm 86:04dd9b1680ae 12367
bogdanm 86:04dd9b1680ae 12368 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 12369 #define RTC_BKP1R_Pos (0U)
Kojto 122:f9eeca106725 12370 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12371 #define RTC_BKP1R RTC_BKP1R_Msk
bogdanm 86:04dd9b1680ae 12372
bogdanm 86:04dd9b1680ae 12373 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 12374 #define RTC_BKP2R_Pos (0U)
Kojto 122:f9eeca106725 12375 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12376 #define RTC_BKP2R RTC_BKP2R_Msk
bogdanm 86:04dd9b1680ae 12377
bogdanm 86:04dd9b1680ae 12378 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 12379 #define RTC_BKP3R_Pos (0U)
Kojto 122:f9eeca106725 12380 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12381 #define RTC_BKP3R RTC_BKP3R_Msk
bogdanm 86:04dd9b1680ae 12382
bogdanm 86:04dd9b1680ae 12383 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 12384 #define RTC_BKP4R_Pos (0U)
Kojto 122:f9eeca106725 12385 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12386 #define RTC_BKP4R RTC_BKP4R_Msk
bogdanm 86:04dd9b1680ae 12387
bogdanm 86:04dd9b1680ae 12388 /******************** Number of backup registers ******************************/
Kojto 122:f9eeca106725 12389 #define RTC_BKP_NUMBER 5
bogdanm 86:04dd9b1680ae 12390
bogdanm 86:04dd9b1680ae 12391 /******************************************************************************/
bogdanm 86:04dd9b1680ae 12392 /* */
bogdanm 86:04dd9b1680ae 12393 /* Serial Peripheral Interface (SPI) */
bogdanm 86:04dd9b1680ae 12394 /* */
bogdanm 86:04dd9b1680ae 12395 /******************************************************************************/
Kojto 122:f9eeca106725 12396
Kojto 122:f9eeca106725 12397 /*
Kojto 122:f9eeca106725 12398 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 12399 */
Kojto 122:f9eeca106725 12400 /* Note: No specific macro feature on this device */
Kojto 122:f9eeca106725 12401
bogdanm 86:04dd9b1680ae 12402 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 12403 #define SPI_CR1_CPHA_Pos (0U)
Kojto 122:f9eeca106725 12404 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12405 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 12406 #define SPI_CR1_CPOL_Pos (1U)
Kojto 122:f9eeca106725 12407 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12408 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 12409 #define SPI_CR1_MSTR_Pos (2U)
Kojto 122:f9eeca106725 12410 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12411 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
Kojto 122:f9eeca106725 12412 #define SPI_CR1_BR_Pos (3U)
Kojto 122:f9eeca106725 12413 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 12414 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 12415 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12416 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12417 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12418 #define SPI_CR1_SPE_Pos (6U)
Kojto 122:f9eeca106725 12419 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12420 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Kojto 122:f9eeca106725 12421 #define SPI_CR1_LSBFIRST_Pos (7U)
Kojto 122:f9eeca106725 12422 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12423 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
Kojto 122:f9eeca106725 12424 #define SPI_CR1_SSI_Pos (8U)
Kojto 122:f9eeca106725 12425 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12426 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
Kojto 122:f9eeca106725 12427 #define SPI_CR1_SSM_Pos (9U)
Kojto 122:f9eeca106725 12428 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12429 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
Kojto 122:f9eeca106725 12430 #define SPI_CR1_RXONLY_Pos (10U)
Kojto 122:f9eeca106725 12431 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12432 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
Kojto 122:f9eeca106725 12433 #define SPI_CR1_CRCL_Pos (11U)
Kojto 122:f9eeca106725 12434 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12435 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Kojto 122:f9eeca106725 12436 #define SPI_CR1_CRCNEXT_Pos (12U)
Kojto 122:f9eeca106725 12437 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12438 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
Kojto 122:f9eeca106725 12439 #define SPI_CR1_CRCEN_Pos (13U)
Kojto 122:f9eeca106725 12440 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12441 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
Kojto 122:f9eeca106725 12442 #define SPI_CR1_BIDIOE_Pos (14U)
Kojto 122:f9eeca106725 12443 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12444 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
Kojto 122:f9eeca106725 12445 #define SPI_CR1_BIDIMODE_Pos (15U)
Kojto 122:f9eeca106725 12446 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12447 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
bogdanm 86:04dd9b1680ae 12448
bogdanm 86:04dd9b1680ae 12449 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 12450 #define SPI_CR2_RXDMAEN_Pos (0U)
Kojto 122:f9eeca106725 12451 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12452 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 12453 #define SPI_CR2_TXDMAEN_Pos (1U)
Kojto 122:f9eeca106725 12454 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12455 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 12456 #define SPI_CR2_SSOE_Pos (2U)
Kojto 122:f9eeca106725 12457 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12458 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
Kojto 122:f9eeca106725 12459 #define SPI_CR2_NSSP_Pos (3U)
Kojto 122:f9eeca106725 12460 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12461 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
Kojto 122:f9eeca106725 12462 #define SPI_CR2_FRF_Pos (4U)
Kojto 122:f9eeca106725 12463 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12464 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
Kojto 122:f9eeca106725 12465 #define SPI_CR2_ERRIE_Pos (5U)
Kojto 122:f9eeca106725 12466 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12467 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 12468 #define SPI_CR2_RXNEIE_Pos (6U)
Kojto 122:f9eeca106725 12469 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12470 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 12471 #define SPI_CR2_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 12472 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12473 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
Kojto 122:f9eeca106725 12474 #define SPI_CR2_DS_Pos (8U)
Kojto 122:f9eeca106725 12475 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12476 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
Kojto 122:f9eeca106725 12477 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12478 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12479 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12480 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12481 #define SPI_CR2_FRXTH_Pos (12U)
Kojto 122:f9eeca106725 12482 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12483 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
Kojto 122:f9eeca106725 12484 #define SPI_CR2_LDMARX_Pos (13U)
Kojto 122:f9eeca106725 12485 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12486 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
Kojto 122:f9eeca106725 12487 #define SPI_CR2_LDMATX_Pos (14U)
Kojto 122:f9eeca106725 12488 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12489 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
bogdanm 86:04dd9b1680ae 12490
bogdanm 86:04dd9b1680ae 12491 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 12492 #define SPI_SR_RXNE_Pos (0U)
Kojto 122:f9eeca106725 12493 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12494 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 12495 #define SPI_SR_TXE_Pos (1U)
Kojto 122:f9eeca106725 12496 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12497 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 12498 #define SPI_SR_CHSIDE_Pos (2U)
Kojto 122:f9eeca106725 12499 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12500 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
Kojto 122:f9eeca106725 12501 #define SPI_SR_UDR_Pos (3U)
Kojto 122:f9eeca106725 12502 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12503 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Kojto 122:f9eeca106725 12504 #define SPI_SR_CRCERR_Pos (4U)
Kojto 122:f9eeca106725 12505 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12506 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
Kojto 122:f9eeca106725 12507 #define SPI_SR_MODF_Pos (5U)
Kojto 122:f9eeca106725 12508 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12509 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
Kojto 122:f9eeca106725 12510 #define SPI_SR_OVR_Pos (6U)
Kojto 122:f9eeca106725 12511 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12512 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
Kojto 122:f9eeca106725 12513 #define SPI_SR_BSY_Pos (7U)
Kojto 122:f9eeca106725 12514 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12515 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
Kojto 122:f9eeca106725 12516 #define SPI_SR_FRE_Pos (8U)
Kojto 122:f9eeca106725 12517 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12518 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
Kojto 122:f9eeca106725 12519 #define SPI_SR_FRLVL_Pos (9U)
Kojto 122:f9eeca106725 12520 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 12521 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
Kojto 122:f9eeca106725 12522 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12523 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12524 #define SPI_SR_FTLVL_Pos (11U)
Kojto 122:f9eeca106725 12525 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 12526 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
Kojto 122:f9eeca106725 12527 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12528 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
bogdanm 86:04dd9b1680ae 12529
bogdanm 86:04dd9b1680ae 12530 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 12531 #define SPI_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 12532 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12533 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
bogdanm 86:04dd9b1680ae 12534
bogdanm 86:04dd9b1680ae 12535 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 12536 #define SPI_CRCPR_CRCPOLY_Pos (0U)
Kojto 122:f9eeca106725 12537 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12538 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
bogdanm 86:04dd9b1680ae 12539
bogdanm 86:04dd9b1680ae 12540 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 12541 #define SPI_RXCRCR_RXCRC_Pos (0U)
Kojto 122:f9eeca106725 12542 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12543 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
bogdanm 86:04dd9b1680ae 12544
bogdanm 86:04dd9b1680ae 12545 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 12546 #define SPI_TXCRCR_TXCRC_Pos (0U)
Kojto 122:f9eeca106725 12547 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12548 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
bogdanm 86:04dd9b1680ae 12549
bogdanm 86:04dd9b1680ae 12550 /******************************************************************************/
bogdanm 86:04dd9b1680ae 12551 /* */
bogdanm 86:04dd9b1680ae 12552 /* System Configuration(SYSCFG) */
bogdanm 86:04dd9b1680ae 12553 /* */
bogdanm 86:04dd9b1680ae 12554 /******************************************************************************/
Kojto 122:f9eeca106725 12555 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 122:f9eeca106725 12556 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
Kojto 122:f9eeca106725 12557 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 12558 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 12559 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 12560 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 12561 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)
Kojto 122:f9eeca106725 12562 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12563 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
Kojto 122:f9eeca106725 12564 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)
Kojto 122:f9eeca106725 12565 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12566 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
Kojto 122:f9eeca106725 12567 #define SYSCFG_CFGR1_DMA_RMP_Pos (11U)
Kojto 122:f9eeca106725 12568 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x0000F800 */
Kojto 122:f9eeca106725 12569 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
Kojto 122:f9eeca106725 12570 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
Kojto 122:f9eeca106725 12571 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12572 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
Kojto 122:f9eeca106725 12573 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
Kojto 122:f9eeca106725 12574 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12575 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
Kojto 122:f9eeca106725 12576 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)
Kojto 122:f9eeca106725 12577 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12578 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
Kojto 122:f9eeca106725 12579 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)
Kojto 122:f9eeca106725 12580 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12581 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
Kojto 122:f9eeca106725 12582 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos (15U)
Kojto 122:f9eeca106725 12583 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12584 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk /*!< DAC2 CH1 DMA remap */
Kojto 122:f9eeca106725 12585 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
Kojto 122:f9eeca106725 12586 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12587 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
Kojto 122:f9eeca106725 12588 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
Kojto 122:f9eeca106725 12589 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12590 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
Kojto 122:f9eeca106725 12591 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
Kojto 122:f9eeca106725 12592 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12593 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
Kojto 122:f9eeca106725 12594 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
Kojto 122:f9eeca106725 12595 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12596 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
Kojto 122:f9eeca106725 12597 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
Kojto 122:f9eeca106725 12598 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12599 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
Kojto 122:f9eeca106725 12600 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)
Kojto 122:f9eeca106725 12601 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 12602 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
Kojto 122:f9eeca106725 12603 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12604 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12605 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)
Kojto 122:f9eeca106725 12606 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12607 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
Kojto 122:f9eeca106725 12608 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)
Kojto 122:f9eeca106725 12609 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12610 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
Kojto 122:f9eeca106725 12611 #define SYSCFG_CFGR1_FPU_IE_Pos (26U)
Kojto 122:f9eeca106725 12612 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
Kojto 122:f9eeca106725 12613 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */
Kojto 122:f9eeca106725 12614 #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12615 #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12616 #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 12617 #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 12618 #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12619 #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 12620
bogdanm 86:04dd9b1680ae 12621 /***************** Bit definition for SYSCFG_RCR register *******************/
Kojto 122:f9eeca106725 12622 #define SYSCFG_RCR_PAGE0_Pos (0U)
Kojto 122:f9eeca106725 12623 #define SYSCFG_RCR_PAGE0_Msk (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12624 #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */
Kojto 122:f9eeca106725 12625 #define SYSCFG_RCR_PAGE1_Pos (1U)
Kojto 122:f9eeca106725 12626 #define SYSCFG_RCR_PAGE1_Msk (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12627 #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */
Kojto 122:f9eeca106725 12628 #define SYSCFG_RCR_PAGE2_Pos (2U)
Kojto 122:f9eeca106725 12629 #define SYSCFG_RCR_PAGE2_Msk (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12630 #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */
Kojto 122:f9eeca106725 12631 #define SYSCFG_RCR_PAGE3_Pos (3U)
Kojto 122:f9eeca106725 12632 #define SYSCFG_RCR_PAGE3_Msk (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12633 #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */
bogdanm 86:04dd9b1680ae 12634
bogdanm 86:04dd9b1680ae 12635 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 12636 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
Kojto 122:f9eeca106725 12637 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12638 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
Kojto 122:f9eeca106725 12639 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
Kojto 122:f9eeca106725 12640 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 12641 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
Kojto 122:f9eeca106725 12642 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
Kojto 122:f9eeca106725 12643 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12644 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
Kojto 122:f9eeca106725 12645 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
Kojto 122:f9eeca106725 12646 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 12647 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
bogdanm 86:04dd9b1680ae 12648
bogdanm 86:04dd9b1680ae 12649 /*!<*
bogdanm 86:04dd9b1680ae 12650 * @brief EXTI0 configuration
bogdanm 86:04dd9b1680ae 12651 */
Kojto 122:f9eeca106725 12652 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
Kojto 122:f9eeca106725 12653 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
Kojto 122:f9eeca106725 12654 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
Kojto 122:f9eeca106725 12655 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
Kojto 122:f9eeca106725 12656 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
Kojto 122:f9eeca106725 12657 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
bogdanm 86:04dd9b1680ae 12658
bogdanm 86:04dd9b1680ae 12659 /*!<*
bogdanm 86:04dd9b1680ae 12660 * @brief EXTI1 configuration
bogdanm 86:04dd9b1680ae 12661 */
Kojto 122:f9eeca106725 12662 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
Kojto 122:f9eeca106725 12663 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
Kojto 122:f9eeca106725 12664 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
Kojto 122:f9eeca106725 12665 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
Kojto 122:f9eeca106725 12666 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
Kojto 122:f9eeca106725 12667 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
bogdanm 86:04dd9b1680ae 12668
bogdanm 86:04dd9b1680ae 12669 /*!<*
bogdanm 86:04dd9b1680ae 12670 * @brief EXTI2 configuration
bogdanm 86:04dd9b1680ae 12671 */
Kojto 122:f9eeca106725 12672 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
Kojto 122:f9eeca106725 12673 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
Kojto 122:f9eeca106725 12674 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
Kojto 122:f9eeca106725 12675 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
Kojto 122:f9eeca106725 12676 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
Kojto 122:f9eeca106725 12677 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
bogdanm 86:04dd9b1680ae 12678
bogdanm 86:04dd9b1680ae 12679 /*!<*
bogdanm 86:04dd9b1680ae 12680 * @brief EXTI3 configuration
bogdanm 86:04dd9b1680ae 12681 */
Kojto 122:f9eeca106725 12682 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
Kojto 122:f9eeca106725 12683 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
Kojto 122:f9eeca106725 12684 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
Kojto 122:f9eeca106725 12685 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
Kojto 122:f9eeca106725 12686 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
bogdanm 86:04dd9b1680ae 12687
bogdanm 86:04dd9b1680ae 12688 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 12689 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
Kojto 122:f9eeca106725 12690 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12691 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
Kojto 122:f9eeca106725 12692 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
Kojto 122:f9eeca106725 12693 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 12694 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
Kojto 122:f9eeca106725 12695 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
Kojto 122:f9eeca106725 12696 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12697 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
Kojto 122:f9eeca106725 12698 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
Kojto 122:f9eeca106725 12699 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 12700 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
bogdanm 86:04dd9b1680ae 12701
bogdanm 86:04dd9b1680ae 12702 /*!<*
bogdanm 86:04dd9b1680ae 12703 * @brief EXTI4 configuration
bogdanm 86:04dd9b1680ae 12704 */
Kojto 122:f9eeca106725 12705 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
Kojto 122:f9eeca106725 12706 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
Kojto 122:f9eeca106725 12707 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
Kojto 122:f9eeca106725 12708 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
Kojto 122:f9eeca106725 12709 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
Kojto 122:f9eeca106725 12710 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
bogdanm 86:04dd9b1680ae 12711
bogdanm 86:04dd9b1680ae 12712 /*!<*
bogdanm 86:04dd9b1680ae 12713 * @brief EXTI5 configuration
bogdanm 86:04dd9b1680ae 12714 */
Kojto 122:f9eeca106725 12715 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
Kojto 122:f9eeca106725 12716 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
Kojto 122:f9eeca106725 12717 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
Kojto 122:f9eeca106725 12718 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
Kojto 122:f9eeca106725 12719 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
Kojto 122:f9eeca106725 12720 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
bogdanm 86:04dd9b1680ae 12721
bogdanm 86:04dd9b1680ae 12722 /*!<*
bogdanm 86:04dd9b1680ae 12723 * @brief EXTI6 configuration
bogdanm 86:04dd9b1680ae 12724 */
Kojto 122:f9eeca106725 12725 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
Kojto 122:f9eeca106725 12726 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
Kojto 122:f9eeca106725 12727 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
Kojto 122:f9eeca106725 12728 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
Kojto 122:f9eeca106725 12729 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
Kojto 122:f9eeca106725 12730 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
bogdanm 86:04dd9b1680ae 12731
bogdanm 86:04dd9b1680ae 12732 /*!<*
bogdanm 86:04dd9b1680ae 12733 * @brief EXTI7 configuration
bogdanm 86:04dd9b1680ae 12734 */
Kojto 122:f9eeca106725 12735 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
Kojto 122:f9eeca106725 12736 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
Kojto 122:f9eeca106725 12737 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
Kojto 122:f9eeca106725 12738 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
Kojto 122:f9eeca106725 12739 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
bogdanm 86:04dd9b1680ae 12740
bogdanm 86:04dd9b1680ae 12741 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 12742 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
Kojto 122:f9eeca106725 12743 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12744 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
Kojto 122:f9eeca106725 12745 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
Kojto 122:f9eeca106725 12746 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 12747 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
Kojto 122:f9eeca106725 12748 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
Kojto 122:f9eeca106725 12749 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12750 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
Kojto 122:f9eeca106725 12751 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
Kojto 122:f9eeca106725 12752 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 12753 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
bogdanm 86:04dd9b1680ae 12754
bogdanm 86:04dd9b1680ae 12755 /*!<*
bogdanm 86:04dd9b1680ae 12756 * @brief EXTI8 configuration
bogdanm 86:04dd9b1680ae 12757 */
Kojto 122:f9eeca106725 12758 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
Kojto 122:f9eeca106725 12759 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
Kojto 122:f9eeca106725 12760 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
Kojto 122:f9eeca106725 12761 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
Kojto 122:f9eeca106725 12762 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
bogdanm 86:04dd9b1680ae 12763
bogdanm 86:04dd9b1680ae 12764 /*!<*
bogdanm 86:04dd9b1680ae 12765 * @brief EXTI9 configuration
bogdanm 86:04dd9b1680ae 12766 */
Kojto 122:f9eeca106725 12767 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
Kojto 122:f9eeca106725 12768 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
Kojto 122:f9eeca106725 12769 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
Kojto 122:f9eeca106725 12770 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
Kojto 122:f9eeca106725 12771 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
Kojto 122:f9eeca106725 12772 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
bogdanm 86:04dd9b1680ae 12773
bogdanm 86:04dd9b1680ae 12774 /*!<*
bogdanm 86:04dd9b1680ae 12775 * @brief EXTI10 configuration
bogdanm 86:04dd9b1680ae 12776 */
Kojto 122:f9eeca106725 12777 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
Kojto 122:f9eeca106725 12778 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
Kojto 122:f9eeca106725 12779 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
Kojto 122:f9eeca106725 12780 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
Kojto 122:f9eeca106725 12781 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
Kojto 122:f9eeca106725 12782 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
bogdanm 86:04dd9b1680ae 12783
bogdanm 86:04dd9b1680ae 12784 /*!<*
bogdanm 86:04dd9b1680ae 12785 * @brief EXTI11 configuration
bogdanm 86:04dd9b1680ae 12786 */
Kojto 122:f9eeca106725 12787 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
Kojto 122:f9eeca106725 12788 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
Kojto 122:f9eeca106725 12789 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
Kojto 122:f9eeca106725 12790 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
Kojto 122:f9eeca106725 12791 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
bogdanm 86:04dd9b1680ae 12792
bogdanm 86:04dd9b1680ae 12793 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
Kojto 122:f9eeca106725 12794 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
Kojto 122:f9eeca106725 12795 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 12796 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
Kojto 122:f9eeca106725 12797 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
Kojto 122:f9eeca106725 12798 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 12799 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
Kojto 122:f9eeca106725 12800 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
Kojto 122:f9eeca106725 12801 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 12802 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
Kojto 122:f9eeca106725 12803 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
Kojto 122:f9eeca106725 12804 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 12805 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
bogdanm 86:04dd9b1680ae 12806
bogdanm 86:04dd9b1680ae 12807 /*!<*
bogdanm 86:04dd9b1680ae 12808 * @brief EXTI12 configuration
bogdanm 86:04dd9b1680ae 12809 */
Kojto 122:f9eeca106725 12810 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
Kojto 122:f9eeca106725 12811 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
Kojto 122:f9eeca106725 12812 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
Kojto 122:f9eeca106725 12813 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
Kojto 122:f9eeca106725 12814 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
bogdanm 86:04dd9b1680ae 12815
bogdanm 86:04dd9b1680ae 12816 /*!<*
bogdanm 86:04dd9b1680ae 12817 * @brief EXTI13 configuration
bogdanm 86:04dd9b1680ae 12818 */
Kojto 122:f9eeca106725 12819 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
Kojto 122:f9eeca106725 12820 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
Kojto 122:f9eeca106725 12821 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
Kojto 122:f9eeca106725 12822 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
Kojto 122:f9eeca106725 12823 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
bogdanm 86:04dd9b1680ae 12824
bogdanm 86:04dd9b1680ae 12825 /*!<*
bogdanm 86:04dd9b1680ae 12826 * @brief EXTI14 configuration
bogdanm 86:04dd9b1680ae 12827 */
Kojto 122:f9eeca106725 12828 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
Kojto 122:f9eeca106725 12829 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
Kojto 122:f9eeca106725 12830 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
Kojto 122:f9eeca106725 12831 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
Kojto 122:f9eeca106725 12832 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
bogdanm 86:04dd9b1680ae 12833
bogdanm 86:04dd9b1680ae 12834 /*!<*
bogdanm 86:04dd9b1680ae 12835 * @brief EXTI15 configuration
bogdanm 86:04dd9b1680ae 12836 */
Kojto 122:f9eeca106725 12837 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
Kojto 122:f9eeca106725 12838 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
Kojto 122:f9eeca106725 12839 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
Kojto 122:f9eeca106725 12840 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
Kojto 122:f9eeca106725 12841 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
Kojto 122:f9eeca106725 12842
Kojto 122:f9eeca106725 12843 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 122:f9eeca106725 12844 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
Kojto 122:f9eeca106725 12845 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12846 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
Kojto 122:f9eeca106725 12847 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
Kojto 122:f9eeca106725 12848 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12849 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
Kojto 122:f9eeca106725 12850 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
Kojto 122:f9eeca106725 12851 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12852 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
Kojto 122:f9eeca106725 12853 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)
Kojto 122:f9eeca106725 12854 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12855 #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
Kojto 122:f9eeca106725 12856 #define SYSCFG_CFGR2_SRAM_PE_Pos (8U)
Kojto 122:f9eeca106725 12857 #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12858 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */
bogdanm 86:04dd9b1680ae 12859
bogdanm 86:04dd9b1680ae 12860 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
Kojto 122:f9eeca106725 12861 #define SYSCFG_CFGR3_DMA_RMP_Pos (0U)
Kojto 122:f9eeca106725 12862 #define SYSCFG_CFGR3_DMA_RMP_Msk (0x3FFU << SYSCFG_CFGR3_DMA_RMP_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 12863 #define SYSCFG_CFGR3_DMA_RMP SYSCFG_CFGR3_DMA_RMP_Msk /*!< DMA remap mask */
Kojto 122:f9eeca106725 12864 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos (0U)
Kojto 122:f9eeca106725 12865 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 12866 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk /*!< SPI1 RX DMA remap */
Kojto 122:f9eeca106725 12867 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12868 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12869 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos (2U)
Kojto 122:f9eeca106725 12870 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 12871 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk /*!< SPI1 TX DMA remap */
Kojto 122:f9eeca106725 12872 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12873 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12874 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos (4U)
Kojto 122:f9eeca106725 12875 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 12876 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
Kojto 122:f9eeca106725 12877 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12878 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12879 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos (6U)
Kojto 122:f9eeca106725 12880 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 12881 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
Kojto 122:f9eeca106725 12882 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12883 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12884 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Pos (8U)
Kojto 122:f9eeca106725 12885 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 12886 #define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */
Kojto 122:f9eeca106725 12887 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12888 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12889 #define SYSCFG_CFGR3_TRIGGER_RMP_Pos (16U)
Kojto 122:f9eeca106725 12890 #define SYSCFG_CFGR3_TRIGGER_RMP_Msk (0x3U << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 12891 #define SYSCFG_CFGR3_TRIGGER_RMP SYSCFG_CFGR3_TRIGGER_RMP_Msk /*!< Trigger remap mask */
Kojto 122:f9eeca106725 12892 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos (16U)
Kojto 122:f9eeca106725 12893 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12894 #define SYSCFG_CFGR3_DAC1_TRG3_RMP SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */
Kojto 122:f9eeca106725 12895 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos (17U)
Kojto 122:f9eeca106725 12896 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12897 #define SYSCFG_CFGR3_DAC1_TRG5_RMP SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */
bogdanm 86:04dd9b1680ae 12898
bogdanm 86:04dd9b1680ae 12899 /******************************************************************************/
bogdanm 86:04dd9b1680ae 12900 /* */
bogdanm 86:04dd9b1680ae 12901 /* TIM */
bogdanm 86:04dd9b1680ae 12902 /* */
bogdanm 86:04dd9b1680ae 12903 /******************************************************************************/
bogdanm 86:04dd9b1680ae 12904 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 12905 #define TIM_CR1_CEN_Pos (0U)
Kojto 122:f9eeca106725 12906 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12907 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
Kojto 122:f9eeca106725 12908 #define TIM_CR1_UDIS_Pos (1U)
Kojto 122:f9eeca106725 12909 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12910 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
Kojto 122:f9eeca106725 12911 #define TIM_CR1_URS_Pos (2U)
Kojto 122:f9eeca106725 12912 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12913 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
Kojto 122:f9eeca106725 12914 #define TIM_CR1_OPM_Pos (3U)
Kojto 122:f9eeca106725 12915 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12916 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
Kojto 122:f9eeca106725 12917 #define TIM_CR1_DIR_Pos (4U)
Kojto 122:f9eeca106725 12918 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12919 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
Kojto 122:f9eeca106725 12920
Kojto 122:f9eeca106725 12921 #define TIM_CR1_CMS_Pos (5U)
Kojto 122:f9eeca106725 12922 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 12923 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 12924 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12925 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12926
Kojto 122:f9eeca106725 12927 #define TIM_CR1_ARPE_Pos (7U)
Kojto 122:f9eeca106725 12928 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12929 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 12930
Kojto 122:f9eeca106725 12931 #define TIM_CR1_CKD_Pos (8U)
Kojto 122:f9eeca106725 12932 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 12933 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 12934 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12935 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12936
Kojto 122:f9eeca106725 12937 #define TIM_CR1_UIFREMAP_Pos (11U)
Kojto 122:f9eeca106725 12938 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12939 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
bogdanm 86:04dd9b1680ae 12940
bogdanm 86:04dd9b1680ae 12941 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 12942 #define TIM_CR2_CCPC_Pos (0U)
Kojto 122:f9eeca106725 12943 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12944 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 12945 #define TIM_CR2_CCUS_Pos (2U)
Kojto 122:f9eeca106725 12946 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12947 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 12948 #define TIM_CR2_CCDS_Pos (3U)
Kojto 122:f9eeca106725 12949 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12950 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 12951
Kojto 122:f9eeca106725 12952 #define TIM_CR2_MMS_Pos (4U)
Kojto 122:f9eeca106725 12953 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 12954 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 12955 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12956 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12957 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12958
Kojto 122:f9eeca106725 12959 #define TIM_CR2_TI1S_Pos (7U)
Kojto 122:f9eeca106725 12960 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12961 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
Kojto 122:f9eeca106725 12962 #define TIM_CR2_OIS1_Pos (8U)
Kojto 122:f9eeca106725 12963 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12964 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 12965 #define TIM_CR2_OIS1N_Pos (9U)
Kojto 122:f9eeca106725 12966 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12967 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 12968 #define TIM_CR2_OIS2_Pos (10U)
Kojto 122:f9eeca106725 12969 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12970 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 12971 #define TIM_CR2_OIS2N_Pos (11U)
Kojto 122:f9eeca106725 12972 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12973 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 12974 #define TIM_CR2_OIS3_Pos (12U)
Kojto 122:f9eeca106725 12975 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12976 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 12977 #define TIM_CR2_OIS3N_Pos (13U)
Kojto 122:f9eeca106725 12978 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12979 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 12980 #define TIM_CR2_OIS4_Pos (14U)
Kojto 122:f9eeca106725 12981 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12982 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 12983 #define TIM_CR2_OIS5_Pos (16U)
Kojto 122:f9eeca106725 12984 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12985 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 12986 #define TIM_CR2_OIS6_Pos (18U)
Kojto 122:f9eeca106725 12987 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12988 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 12989
Kojto 122:f9eeca106725 12990 #define TIM_CR2_MMS2_Pos (20U)
Kojto 122:f9eeca106725 12991 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 12992 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 12993 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12994 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12995 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12996 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
bogdanm 86:04dd9b1680ae 12997
bogdanm 86:04dd9b1680ae 12998 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 12999 #define TIM_SMCR_SMS_Pos (0U)
Kojto 122:f9eeca106725 13000 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
Kojto 122:f9eeca106725 13001 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 13002 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 13003 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 13004 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */
Kojto 122:f9eeca106725 13005 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 13006
Kojto 122:f9eeca106725 13007 #define TIM_SMCR_OCCS_Pos (3U)
Kojto 122:f9eeca106725 13008 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13009 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
Kojto 122:f9eeca106725 13010
Kojto 122:f9eeca106725 13011 #define TIM_SMCR_TS_Pos (4U)
Kojto 122:f9eeca106725 13012 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 13013 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 13014 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13015 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13016 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13017
Kojto 122:f9eeca106725 13018 #define TIM_SMCR_MSM_Pos (7U)
Kojto 122:f9eeca106725 13019 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13020 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
Kojto 122:f9eeca106725 13021
Kojto 122:f9eeca106725 13022 #define TIM_SMCR_ETF_Pos (8U)
Kojto 122:f9eeca106725 13023 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 13024 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 13025 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13026 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13027 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13028 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13029
Kojto 122:f9eeca106725 13030 #define TIM_SMCR_ETPS_Pos (12U)
Kojto 122:f9eeca106725 13031 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 13032 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 13033 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13034 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13035
Kojto 122:f9eeca106725 13036 #define TIM_SMCR_ECE_Pos (14U)
Kojto 122:f9eeca106725 13037 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13038 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
Kojto 122:f9eeca106725 13039 #define TIM_SMCR_ETP_Pos (15U)
Kojto 122:f9eeca106725 13040 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13041 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
bogdanm 86:04dd9b1680ae 13042
bogdanm 86:04dd9b1680ae 13043 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 13044 #define TIM_DIER_UIE_Pos (0U)
Kojto 122:f9eeca106725 13045 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13046 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
Kojto 122:f9eeca106725 13047 #define TIM_DIER_CC1IE_Pos (1U)
Kojto 122:f9eeca106725 13048 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13049 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 13050 #define TIM_DIER_CC2IE_Pos (2U)
Kojto 122:f9eeca106725 13051 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13052 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 13053 #define TIM_DIER_CC3IE_Pos (3U)
Kojto 122:f9eeca106725 13054 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13055 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 13056 #define TIM_DIER_CC4IE_Pos (4U)
Kojto 122:f9eeca106725 13057 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13058 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 13059 #define TIM_DIER_COMIE_Pos (5U)
Kojto 122:f9eeca106725 13060 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13061 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
Kojto 122:f9eeca106725 13062 #define TIM_DIER_TIE_Pos (6U)
Kojto 122:f9eeca106725 13063 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13064 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 13065 #define TIM_DIER_BIE_Pos (7U)
Kojto 122:f9eeca106725 13066 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13067 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
Kojto 122:f9eeca106725 13068 #define TIM_DIER_UDE_Pos (8U)
Kojto 122:f9eeca106725 13069 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13070 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
Kojto 122:f9eeca106725 13071 #define TIM_DIER_CC1DE_Pos (9U)
Kojto 122:f9eeca106725 13072 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13073 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 13074 #define TIM_DIER_CC2DE_Pos (10U)
Kojto 122:f9eeca106725 13075 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13076 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 13077 #define TIM_DIER_CC3DE_Pos (11U)
Kojto 122:f9eeca106725 13078 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13079 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 13080 #define TIM_DIER_CC4DE_Pos (12U)
Kojto 122:f9eeca106725 13081 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13082 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 13083 #define TIM_DIER_COMDE_Pos (13U)
Kojto 122:f9eeca106725 13084 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13085 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
Kojto 122:f9eeca106725 13086 #define TIM_DIER_TDE_Pos (14U)
Kojto 122:f9eeca106725 13087 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13088 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
bogdanm 86:04dd9b1680ae 13089
bogdanm 86:04dd9b1680ae 13090 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 13091 #define TIM_SR_UIF_Pos (0U)
Kojto 122:f9eeca106725 13092 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13093 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 13094 #define TIM_SR_CC1IF_Pos (1U)
Kojto 122:f9eeca106725 13095 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13096 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 13097 #define TIM_SR_CC2IF_Pos (2U)
Kojto 122:f9eeca106725 13098 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13099 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 13100 #define TIM_SR_CC3IF_Pos (3U)
Kojto 122:f9eeca106725 13101 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13102 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 13103 #define TIM_SR_CC4IF_Pos (4U)
Kojto 122:f9eeca106725 13104 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13105 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 13106 #define TIM_SR_COMIF_Pos (5U)
Kojto 122:f9eeca106725 13107 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13108 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 13109 #define TIM_SR_TIF_Pos (6U)
Kojto 122:f9eeca106725 13110 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13111 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 13112 #define TIM_SR_BIF_Pos (7U)
Kojto 122:f9eeca106725 13113 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13114 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 13115 #define TIM_SR_B2IF_Pos (8U)
Kojto 122:f9eeca106725 13116 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13117 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
Kojto 122:f9eeca106725 13118 #define TIM_SR_CC1OF_Pos (9U)
Kojto 122:f9eeca106725 13119 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13120 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 13121 #define TIM_SR_CC2OF_Pos (10U)
Kojto 122:f9eeca106725 13122 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13123 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 13124 #define TIM_SR_CC3OF_Pos (11U)
Kojto 122:f9eeca106725 13125 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13126 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 13127 #define TIM_SR_CC4OF_Pos (12U)
Kojto 122:f9eeca106725 13128 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13129 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
Kojto 122:f9eeca106725 13130 #define TIM_SR_CC5IF_Pos (16U)
Kojto 122:f9eeca106725 13131 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13132 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
Kojto 122:f9eeca106725 13133 #define TIM_SR_CC6IF_Pos (17U)
Kojto 122:f9eeca106725 13134 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13135 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
bogdanm 86:04dd9b1680ae 13136
bogdanm 86:04dd9b1680ae 13137 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 13138 #define TIM_EGR_UG_Pos (0U)
Kojto 122:f9eeca106725 13139 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13140 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
Kojto 122:f9eeca106725 13141 #define TIM_EGR_CC1G_Pos (1U)
Kojto 122:f9eeca106725 13142 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13143 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 13144 #define TIM_EGR_CC2G_Pos (2U)
Kojto 122:f9eeca106725 13145 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13146 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 13147 #define TIM_EGR_CC3G_Pos (3U)
Kojto 122:f9eeca106725 13148 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13149 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 13150 #define TIM_EGR_CC4G_Pos (4U)
Kojto 122:f9eeca106725 13151 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13152 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 13153 #define TIM_EGR_COMG_Pos (5U)
Kojto 122:f9eeca106725 13154 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13155 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 13156 #define TIM_EGR_TG_Pos (6U)
Kojto 122:f9eeca106725 13157 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13158 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
Kojto 122:f9eeca106725 13159 #define TIM_EGR_BG_Pos (7U)
Kojto 122:f9eeca106725 13160 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13161 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
Kojto 122:f9eeca106725 13162 #define TIM_EGR_B2G_Pos (8U)
Kojto 122:f9eeca106725 13163 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13164 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
bogdanm 86:04dd9b1680ae 13165
bogdanm 86:04dd9b1680ae 13166 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 13167 #define TIM_CCMR1_CC1S_Pos (0U)
Kojto 122:f9eeca106725 13168 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 13169 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 13170 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13171 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13172
Kojto 122:f9eeca106725 13173 #define TIM_CCMR1_OC1FE_Pos (2U)
Kojto 122:f9eeca106725 13174 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13175 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 13176 #define TIM_CCMR1_OC1PE_Pos (3U)
Kojto 122:f9eeca106725 13177 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13178 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 13179
Kojto 122:f9eeca106725 13180 #define TIM_CCMR1_OC1M_Pos (4U)
Kojto 122:f9eeca106725 13181 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 13182 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 13183 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 13184 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 13185 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 13186 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 13187
Kojto 122:f9eeca106725 13188 #define TIM_CCMR1_OC1CE_Pos (7U)
Kojto 122:f9eeca106725 13189 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13190 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 13191
Kojto 122:f9eeca106725 13192 #define TIM_CCMR1_CC2S_Pos (8U)
Kojto 122:f9eeca106725 13193 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 13194 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 13195 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13196 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13197
Kojto 122:f9eeca106725 13198 #define TIM_CCMR1_OC2FE_Pos (10U)
Kojto 122:f9eeca106725 13199 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13200 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 13201 #define TIM_CCMR1_OC2PE_Pos (11U)
Kojto 122:f9eeca106725 13202 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13203 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 13204
Kojto 122:f9eeca106725 13205 #define TIM_CCMR1_OC2M_Pos (12U)
Kojto 122:f9eeca106725 13206 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 13207 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 13208 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 13209 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 13210 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 13211 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 13212
Kojto 122:f9eeca106725 13213 #define TIM_CCMR1_OC2CE_Pos (15U)
Kojto 122:f9eeca106725 13214 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13215 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
bogdanm 86:04dd9b1680ae 13216
bogdanm 86:04dd9b1680ae 13217 /*----------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 13218
Kojto 122:f9eeca106725 13219 #define TIM_CCMR1_IC1PSC_Pos (2U)
Kojto 122:f9eeca106725 13220 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 13221 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 13222 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13223 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13224
Kojto 122:f9eeca106725 13225 #define TIM_CCMR1_IC1F_Pos (4U)
Kojto 122:f9eeca106725 13226 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 13227 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 13228 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13229 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13230 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13231 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13232
Kojto 122:f9eeca106725 13233 #define TIM_CCMR1_IC2PSC_Pos (10U)
Kojto 122:f9eeca106725 13234 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 13235 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 13236 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13237 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13238
Kojto 122:f9eeca106725 13239 #define TIM_CCMR1_IC2F_Pos (12U)
Kojto 122:f9eeca106725 13240 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 13241 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 13242 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13243 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13244 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13245 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
bogdanm 86:04dd9b1680ae 13246
bogdanm 86:04dd9b1680ae 13247 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 13248 #define TIM_CCMR2_CC3S_Pos (0U)
Kojto 122:f9eeca106725 13249 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 13250 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 13251 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13252 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13253
Kojto 122:f9eeca106725 13254 #define TIM_CCMR2_OC3FE_Pos (2U)
Kojto 122:f9eeca106725 13255 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13256 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 13257 #define TIM_CCMR2_OC3PE_Pos (3U)
Kojto 122:f9eeca106725 13258 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13259 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 13260
Kojto 122:f9eeca106725 13261 #define TIM_CCMR2_OC3M_Pos (4U)
Kojto 122:f9eeca106725 13262 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 13263 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 13264 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 13265 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 13266 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 13267 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 13268
Kojto 122:f9eeca106725 13269 #define TIM_CCMR2_OC3CE_Pos (7U)
Kojto 122:f9eeca106725 13270 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13271 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 13272
Kojto 122:f9eeca106725 13273 #define TIM_CCMR2_CC4S_Pos (8U)
Kojto 122:f9eeca106725 13274 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 13275 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 13276 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13277 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13278
Kojto 122:f9eeca106725 13279 #define TIM_CCMR2_OC4FE_Pos (10U)
Kojto 122:f9eeca106725 13280 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13281 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 13282 #define TIM_CCMR2_OC4PE_Pos (11U)
Kojto 122:f9eeca106725 13283 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13284 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 13285
Kojto 122:f9eeca106725 13286 #define TIM_CCMR2_OC4M_Pos (12U)
Kojto 122:f9eeca106725 13287 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 13288 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 13289 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 13290 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 13291 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 13292 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 13293
Kojto 122:f9eeca106725 13294 #define TIM_CCMR2_OC4CE_Pos (15U)
Kojto 122:f9eeca106725 13295 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13296 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
bogdanm 86:04dd9b1680ae 13297
bogdanm 86:04dd9b1680ae 13298 /*----------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 13299
Kojto 122:f9eeca106725 13300 #define TIM_CCMR2_IC3PSC_Pos (2U)
Kojto 122:f9eeca106725 13301 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 13302 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 13303 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13304 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13305
Kojto 122:f9eeca106725 13306 #define TIM_CCMR2_IC3F_Pos (4U)
Kojto 122:f9eeca106725 13307 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 13308 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 13309 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13310 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13311 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13312 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13313
Kojto 122:f9eeca106725 13314 #define TIM_CCMR2_IC4PSC_Pos (10U)
Kojto 122:f9eeca106725 13315 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 13316 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 13317 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13318 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13319
Kojto 122:f9eeca106725 13320 #define TIM_CCMR2_IC4F_Pos (12U)
Kojto 122:f9eeca106725 13321 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 13322 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 13323 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13324 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13325 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13326 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
bogdanm 86:04dd9b1680ae 13327
bogdanm 86:04dd9b1680ae 13328 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 13329 #define TIM_CCER_CC1E_Pos (0U)
Kojto 122:f9eeca106725 13330 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13331 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 13332 #define TIM_CCER_CC1P_Pos (1U)
Kojto 122:f9eeca106725 13333 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13334 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 13335 #define TIM_CCER_CC1NE_Pos (2U)
Kojto 122:f9eeca106725 13336 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13337 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 13338 #define TIM_CCER_CC1NP_Pos (3U)
Kojto 122:f9eeca106725 13339 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13340 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 13341 #define TIM_CCER_CC2E_Pos (4U)
Kojto 122:f9eeca106725 13342 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13343 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 13344 #define TIM_CCER_CC2P_Pos (5U)
Kojto 122:f9eeca106725 13345 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13346 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 13347 #define TIM_CCER_CC2NE_Pos (6U)
Kojto 122:f9eeca106725 13348 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13349 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 13350 #define TIM_CCER_CC2NP_Pos (7U)
Kojto 122:f9eeca106725 13351 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13352 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 13353 #define TIM_CCER_CC3E_Pos (8U)
Kojto 122:f9eeca106725 13354 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13355 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 13356 #define TIM_CCER_CC3P_Pos (9U)
Kojto 122:f9eeca106725 13357 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13358 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 13359 #define TIM_CCER_CC3NE_Pos (10U)
Kojto 122:f9eeca106725 13360 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13361 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 13362 #define TIM_CCER_CC3NP_Pos (11U)
Kojto 122:f9eeca106725 13363 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13364 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 13365 #define TIM_CCER_CC4E_Pos (12U)
Kojto 122:f9eeca106725 13366 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13367 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 13368 #define TIM_CCER_CC4P_Pos (13U)
Kojto 122:f9eeca106725 13369 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13370 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 13371 #define TIM_CCER_CC4NP_Pos (15U)
Kojto 122:f9eeca106725 13372 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13373 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 122:f9eeca106725 13374 #define TIM_CCER_CC5E_Pos (16U)
Kojto 122:f9eeca106725 13375 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13376 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
Kojto 122:f9eeca106725 13377 #define TIM_CCER_CC5P_Pos (17U)
Kojto 122:f9eeca106725 13378 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13379 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
Kojto 122:f9eeca106725 13380 #define TIM_CCER_CC6E_Pos (20U)
Kojto 122:f9eeca106725 13381 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13382 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
Kojto 122:f9eeca106725 13383 #define TIM_CCER_CC6P_Pos (21U)
Kojto 122:f9eeca106725 13384 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13385 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
bogdanm 86:04dd9b1680ae 13386
bogdanm 86:04dd9b1680ae 13387 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 13388 #define TIM_CNT_CNT_Pos (0U)
Kojto 122:f9eeca106725 13389 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 13390 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
Kojto 122:f9eeca106725 13391 #define TIM_CNT_UIFCPY_Pos (31U)
Kojto 122:f9eeca106725 13392 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13393 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
bogdanm 86:04dd9b1680ae 13394
bogdanm 86:04dd9b1680ae 13395 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 13396 #define TIM_PSC_PSC_Pos (0U)
Kojto 122:f9eeca106725 13397 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13398 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
bogdanm 86:04dd9b1680ae 13399
bogdanm 86:04dd9b1680ae 13400 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 13401 #define TIM_ARR_ARR_Pos (0U)
Kojto 122:f9eeca106725 13402 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 13403 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
bogdanm 86:04dd9b1680ae 13404
bogdanm 86:04dd9b1680ae 13405 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 13406 #define TIM_RCR_REP_Pos (0U)
Kojto 122:f9eeca106725 13407 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13408 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
bogdanm 86:04dd9b1680ae 13409
bogdanm 86:04dd9b1680ae 13410 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 13411 #define TIM_CCR1_CCR1_Pos (0U)
Kojto 122:f9eeca106725 13412 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13413 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
bogdanm 86:04dd9b1680ae 13414
bogdanm 86:04dd9b1680ae 13415 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 13416 #define TIM_CCR2_CCR2_Pos (0U)
Kojto 122:f9eeca106725 13417 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13418 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
bogdanm 86:04dd9b1680ae 13419
bogdanm 86:04dd9b1680ae 13420 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 13421 #define TIM_CCR3_CCR3_Pos (0U)
Kojto 122:f9eeca106725 13422 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13423 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
bogdanm 86:04dd9b1680ae 13424
bogdanm 86:04dd9b1680ae 13425 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 13426 #define TIM_CCR4_CCR4_Pos (0U)
Kojto 122:f9eeca106725 13427 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13428 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
bogdanm 86:04dd9b1680ae 13429
bogdanm 86:04dd9b1680ae 13430 /******************* Bit definition for TIM_CCR5 register *******************/
Kojto 122:f9eeca106725 13431 #define TIM_CCR5_CCR5_Pos (0U)
Kojto 122:f9eeca106725 13432 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 13433 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
Kojto 122:f9eeca106725 13434 #define TIM_CCR5_GC5C1_Pos (29U)
Kojto 122:f9eeca106725 13435 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 13436 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
Kojto 122:f9eeca106725 13437 #define TIM_CCR5_GC5C2_Pos (30U)
Kojto 122:f9eeca106725 13438 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 13439 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
Kojto 122:f9eeca106725 13440 #define TIM_CCR5_GC5C3_Pos (31U)
Kojto 122:f9eeca106725 13441 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13442 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
bogdanm 86:04dd9b1680ae 13443
bogdanm 86:04dd9b1680ae 13444 /******************* Bit definition for TIM_CCR6 register *******************/
Kojto 122:f9eeca106725 13445 #define TIM_CCR6_CCR6_Pos (0U)
Kojto 122:f9eeca106725 13446 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13447 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
bogdanm 86:04dd9b1680ae 13448
bogdanm 86:04dd9b1680ae 13449 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 13450 #define TIM_BDTR_DTG_Pos (0U)
Kojto 122:f9eeca106725 13451 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 13452 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 13453 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13454 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13455 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13456 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13457 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13458 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13459 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13460 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13461
Kojto 122:f9eeca106725 13462 #define TIM_BDTR_LOCK_Pos (8U)
Kojto 122:f9eeca106725 13463 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 13464 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 13465 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13466 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13467
Kojto 122:f9eeca106725 13468 #define TIM_BDTR_OSSI_Pos (10U)
Kojto 122:f9eeca106725 13469 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13470 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 13471 #define TIM_BDTR_OSSR_Pos (11U)
Kojto 122:f9eeca106725 13472 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13473 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 13474 #define TIM_BDTR_BKE_Pos (12U)
Kojto 122:f9eeca106725 13475 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13476 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
Kojto 122:f9eeca106725 13477 #define TIM_BDTR_BKP_Pos (13U)
Kojto 122:f9eeca106725 13478 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13479 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
Kojto 122:f9eeca106725 13480 #define TIM_BDTR_AOE_Pos (14U)
Kojto 122:f9eeca106725 13481 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13482 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
Kojto 122:f9eeca106725 13483 #define TIM_BDTR_MOE_Pos (15U)
Kojto 122:f9eeca106725 13484 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13485 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
Kojto 122:f9eeca106725 13486
Kojto 122:f9eeca106725 13487 #define TIM_BDTR_BKF_Pos (16U)
Kojto 122:f9eeca106725 13488 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 13489 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
Kojto 122:f9eeca106725 13490 #define TIM_BDTR_BK2F_Pos (20U)
Kojto 122:f9eeca106725 13491 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 13492 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
Kojto 122:f9eeca106725 13493
Kojto 122:f9eeca106725 13494 #define TIM_BDTR_BK2E_Pos (24U)
Kojto 122:f9eeca106725 13495 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13496 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
Kojto 122:f9eeca106725 13497 #define TIM_BDTR_BK2P_Pos (25U)
Kojto 122:f9eeca106725 13498 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13499 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
bogdanm 86:04dd9b1680ae 13500
bogdanm 86:04dd9b1680ae 13501 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 13502 #define TIM_DCR_DBA_Pos (0U)
Kojto 122:f9eeca106725 13503 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 13504 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 13505 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13506 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13507 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13508 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13509 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13510
Kojto 122:f9eeca106725 13511 #define TIM_DCR_DBL_Pos (8U)
Kojto 122:f9eeca106725 13512 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 13513 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 13514 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13515 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13516 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13517 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13518 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
bogdanm 86:04dd9b1680ae 13519
bogdanm 86:04dd9b1680ae 13520 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 13521 #define TIM_DMAR_DMAB_Pos (0U)
Kojto 122:f9eeca106725 13522 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 13523 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
bogdanm 86:04dd9b1680ae 13524
bogdanm 86:04dd9b1680ae 13525 /******************* Bit definition for TIM16_OR register *********************/
Kojto 122:f9eeca106725 13526 #define TIM16_OR_TI1_RMP_Pos (0U)
Kojto 122:f9eeca106725 13527 #define TIM16_OR_TI1_RMP_Msk (0x3U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 13528 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
Kojto 122:f9eeca106725 13529 #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13530 #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */
bogdanm 86:04dd9b1680ae 13531
bogdanm 86:04dd9b1680ae 13532 /******************* Bit definition for TIM1_OR register *********************/
Kojto 122:f9eeca106725 13533 #define TIM1_OR_ETR_RMP_Pos (0U)
Kojto 122:f9eeca106725 13534 #define TIM1_OR_ETR_RMP_Msk (0xFU << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 13535 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
Kojto 122:f9eeca106725 13536 #define TIM1_OR_ETR_RMP_0 (0x1U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13537 #define TIM1_OR_ETR_RMP_1 (0x2U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13538 #define TIM1_OR_ETR_RMP_2 (0x4U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13539 #define TIM1_OR_ETR_RMP_3 (0x8U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */
bogdanm 86:04dd9b1680ae 13540
bogdanm 86:04dd9b1680ae 13541 /****************** Bit definition for TIM_CCMR3 register *******************/
Kojto 122:f9eeca106725 13542 #define TIM_CCMR3_OC5FE_Pos (2U)
Kojto 122:f9eeca106725 13543 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13544 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
Kojto 122:f9eeca106725 13545 #define TIM_CCMR3_OC5PE_Pos (3U)
Kojto 122:f9eeca106725 13546 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13547 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
Kojto 122:f9eeca106725 13548
Kojto 122:f9eeca106725 13549 #define TIM_CCMR3_OC5M_Pos (4U)
Kojto 122:f9eeca106725 13550 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 13551 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
Kojto 122:f9eeca106725 13552 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13553 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13554 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13555 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13556
Kojto 122:f9eeca106725 13557 #define TIM_CCMR3_OC5CE_Pos (7U)
Kojto 122:f9eeca106725 13558 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13559 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
Kojto 122:f9eeca106725 13560
Kojto 122:f9eeca106725 13561 #define TIM_CCMR3_OC6FE_Pos (10U)
Kojto 122:f9eeca106725 13562 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13563 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
Kojto 122:f9eeca106725 13564 #define TIM_CCMR3_OC6PE_Pos (11U)
Kojto 122:f9eeca106725 13565 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13566 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
Kojto 122:f9eeca106725 13567
Kojto 122:f9eeca106725 13568 #define TIM_CCMR3_OC6M_Pos (12U)
Kojto 122:f9eeca106725 13569 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 13570 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
Kojto 122:f9eeca106725 13571 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13572 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13573 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13574 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13575
Kojto 122:f9eeca106725 13576 #define TIM_CCMR3_OC6CE_Pos (15U)
Kojto 122:f9eeca106725 13577 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13578 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
bogdanm 86:04dd9b1680ae 13579
bogdanm 86:04dd9b1680ae 13580 /******************************************************************************/
bogdanm 86:04dd9b1680ae 13581 /* */
bogdanm 86:04dd9b1680ae 13582 /* Touch Sensing Controller (TSC) */
bogdanm 86:04dd9b1680ae 13583 /* */
bogdanm 86:04dd9b1680ae 13584 /******************************************************************************/
bogdanm 86:04dd9b1680ae 13585 /******************* Bit definition for TSC_CR register *********************/
Kojto 122:f9eeca106725 13586 #define TSC_CR_TSCE_Pos (0U)
Kojto 122:f9eeca106725 13587 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13588 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
Kojto 122:f9eeca106725 13589 #define TSC_CR_START_Pos (1U)
Kojto 122:f9eeca106725 13590 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13591 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
Kojto 122:f9eeca106725 13592 #define TSC_CR_AM_Pos (2U)
Kojto 122:f9eeca106725 13593 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13594 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
Kojto 122:f9eeca106725 13595 #define TSC_CR_SYNCPOL_Pos (3U)
Kojto 122:f9eeca106725 13596 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13597 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
Kojto 122:f9eeca106725 13598 #define TSC_CR_IODEF_Pos (4U)
Kojto 122:f9eeca106725 13599 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13600 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
Kojto 122:f9eeca106725 13601
Kojto 122:f9eeca106725 13602 #define TSC_CR_MCV_Pos (5U)
Kojto 122:f9eeca106725 13603 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 13604 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
Kojto 122:f9eeca106725 13605 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13606 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13607 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13608
Kojto 122:f9eeca106725 13609 #define TSC_CR_PGPSC_Pos (12U)
Kojto 122:f9eeca106725 13610 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 13611 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 122:f9eeca106725 13612 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13613 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13614 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13615
Kojto 122:f9eeca106725 13616 #define TSC_CR_SSPSC_Pos (15U)
Kojto 122:f9eeca106725 13617 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13618 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
Kojto 122:f9eeca106725 13619 #define TSC_CR_SSE_Pos (16U)
Kojto 122:f9eeca106725 13620 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13621 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
Kojto 122:f9eeca106725 13622
Kojto 122:f9eeca106725 13623 #define TSC_CR_SSD_Pos (17U)
Kojto 122:f9eeca106725 13624 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 13625 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 122:f9eeca106725 13626 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13627 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13628 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13629 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13630 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13631 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13632 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13633
Kojto 122:f9eeca106725 13634 #define TSC_CR_CTPL_Pos (24U)
Kojto 122:f9eeca106725 13635 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 13636 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 122:f9eeca106725 13637 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13638 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13639 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13640 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13641
Kojto 122:f9eeca106725 13642 #define TSC_CR_CTPH_Pos (28U)
Kojto 122:f9eeca106725 13643 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 13644 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 122:f9eeca106725 13645 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 13646 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 13647 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 13648 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
bogdanm 86:04dd9b1680ae 13649
bogdanm 86:04dd9b1680ae 13650 /******************* Bit definition for TSC_IER register ********************/
Kojto 122:f9eeca106725 13651 #define TSC_IER_EOAIE_Pos (0U)
Kojto 122:f9eeca106725 13652 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13653 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
Kojto 122:f9eeca106725 13654 #define TSC_IER_MCEIE_Pos (1U)
Kojto 122:f9eeca106725 13655 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13656 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
bogdanm 86:04dd9b1680ae 13657
bogdanm 86:04dd9b1680ae 13658 /******************* Bit definition for TSC_ICR register ********************/
Kojto 122:f9eeca106725 13659 #define TSC_ICR_EOAIC_Pos (0U)
Kojto 122:f9eeca106725 13660 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13661 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
Kojto 122:f9eeca106725 13662 #define TSC_ICR_MCEIC_Pos (1U)
Kojto 122:f9eeca106725 13663 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13664 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
bogdanm 86:04dd9b1680ae 13665
bogdanm 86:04dd9b1680ae 13666 /******************* Bit definition for TSC_ISR register ********************/
Kojto 122:f9eeca106725 13667 #define TSC_ISR_EOAF_Pos (0U)
Kojto 122:f9eeca106725 13668 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13669 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
Kojto 122:f9eeca106725 13670 #define TSC_ISR_MCEF_Pos (1U)
Kojto 122:f9eeca106725 13671 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13672 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
bogdanm 86:04dd9b1680ae 13673
bogdanm 86:04dd9b1680ae 13674 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 122:f9eeca106725 13675 #define TSC_IOHCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 13676 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13677 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13678 #define TSC_IOHCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 13679 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13680 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13681 #define TSC_IOHCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 13682 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13683 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13684 #define TSC_IOHCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 13685 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13686 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13687 #define TSC_IOHCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 13688 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13689 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13690 #define TSC_IOHCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 13691 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13692 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13693 #define TSC_IOHCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 13694 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13695 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13696 #define TSC_IOHCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 13697 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13698 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13699 #define TSC_IOHCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 13700 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13701 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13702 #define TSC_IOHCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 13703 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13704 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13705 #define TSC_IOHCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 13706 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13707 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13708 #define TSC_IOHCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 13709 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13710 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13711 #define TSC_IOHCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 13712 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13713 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13714 #define TSC_IOHCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 13715 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13716 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13717 #define TSC_IOHCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 13718 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13719 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13720 #define TSC_IOHCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 13721 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13722 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13723 #define TSC_IOHCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 13724 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13725 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13726 #define TSC_IOHCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 13727 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13728 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13729 #define TSC_IOHCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 13730 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13731 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13732 #define TSC_IOHCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 13733 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13734 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13735 #define TSC_IOHCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 13736 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13737 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13738 #define TSC_IOHCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 13739 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13740 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13741 #define TSC_IOHCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 13742 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13743 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13744 #define TSC_IOHCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 13745 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13746 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13747 #define TSC_IOHCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 13748 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13749 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13750 #define TSC_IOHCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 13751 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13752 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13753 #define TSC_IOHCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 13754 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13755 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13756 #define TSC_IOHCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 13757 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13758 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13759 #define TSC_IOHCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 13760 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 13761 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13762 #define TSC_IOHCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 13763 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 13764 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13765 #define TSC_IOHCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 13766 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 13767 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 13768 #define TSC_IOHCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 13769 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13770 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
bogdanm 86:04dd9b1680ae 13771
bogdanm 86:04dd9b1680ae 13772 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 122:f9eeca106725 13773 #define TSC_IOASCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 13774 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13775 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
Kojto 122:f9eeca106725 13776 #define TSC_IOASCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 13777 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13778 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
Kojto 122:f9eeca106725 13779 #define TSC_IOASCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 13780 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13781 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
Kojto 122:f9eeca106725 13782 #define TSC_IOASCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 13783 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13784 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
Kojto 122:f9eeca106725 13785 #define TSC_IOASCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 13786 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13787 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
Kojto 122:f9eeca106725 13788 #define TSC_IOASCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 13789 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13790 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
Kojto 122:f9eeca106725 13791 #define TSC_IOASCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 13792 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13793 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
Kojto 122:f9eeca106725 13794 #define TSC_IOASCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 13795 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13796 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
Kojto 122:f9eeca106725 13797 #define TSC_IOASCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 13798 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13799 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
Kojto 122:f9eeca106725 13800 #define TSC_IOASCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 13801 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13802 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
Kojto 122:f9eeca106725 13803 #define TSC_IOASCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 13804 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13805 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
Kojto 122:f9eeca106725 13806 #define TSC_IOASCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 13807 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13808 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
Kojto 122:f9eeca106725 13809 #define TSC_IOASCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 13810 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13811 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
Kojto 122:f9eeca106725 13812 #define TSC_IOASCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 13813 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13814 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
Kojto 122:f9eeca106725 13815 #define TSC_IOASCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 13816 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13817 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
Kojto 122:f9eeca106725 13818 #define TSC_IOASCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 13819 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13820 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
Kojto 122:f9eeca106725 13821 #define TSC_IOASCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 13822 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13823 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
Kojto 122:f9eeca106725 13824 #define TSC_IOASCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 13825 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13826 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
Kojto 122:f9eeca106725 13827 #define TSC_IOASCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 13828 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13829 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
Kojto 122:f9eeca106725 13830 #define TSC_IOASCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 13831 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13832 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
Kojto 122:f9eeca106725 13833 #define TSC_IOASCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 13834 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13835 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
Kojto 122:f9eeca106725 13836 #define TSC_IOASCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 13837 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13838 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
Kojto 122:f9eeca106725 13839 #define TSC_IOASCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 13840 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13841 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
Kojto 122:f9eeca106725 13842 #define TSC_IOASCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 13843 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13844 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
Kojto 122:f9eeca106725 13845 #define TSC_IOASCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 13846 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13847 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
Kojto 122:f9eeca106725 13848 #define TSC_IOASCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 13849 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13850 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
Kojto 122:f9eeca106725 13851 #define TSC_IOASCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 13852 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13853 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
Kojto 122:f9eeca106725 13854 #define TSC_IOASCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 13855 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13856 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
Kojto 122:f9eeca106725 13857 #define TSC_IOASCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 13858 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 13859 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
Kojto 122:f9eeca106725 13860 #define TSC_IOASCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 13861 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 13862 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
Kojto 122:f9eeca106725 13863 #define TSC_IOASCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 13864 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 13865 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
Kojto 122:f9eeca106725 13866 #define TSC_IOASCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 13867 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13868 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
bogdanm 86:04dd9b1680ae 13869
bogdanm 86:04dd9b1680ae 13870 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 122:f9eeca106725 13871 #define TSC_IOSCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 13872 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13873 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
Kojto 122:f9eeca106725 13874 #define TSC_IOSCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 13875 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13876 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
Kojto 122:f9eeca106725 13877 #define TSC_IOSCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 13878 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13879 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
Kojto 122:f9eeca106725 13880 #define TSC_IOSCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 13881 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13882 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
Kojto 122:f9eeca106725 13883 #define TSC_IOSCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 13884 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13885 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
Kojto 122:f9eeca106725 13886 #define TSC_IOSCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 13887 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13888 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
Kojto 122:f9eeca106725 13889 #define TSC_IOSCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 13890 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13891 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
Kojto 122:f9eeca106725 13892 #define TSC_IOSCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 13893 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13894 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
Kojto 122:f9eeca106725 13895 #define TSC_IOSCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 13896 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13897 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
Kojto 122:f9eeca106725 13898 #define TSC_IOSCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 13899 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13900 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
Kojto 122:f9eeca106725 13901 #define TSC_IOSCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 13902 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13903 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
Kojto 122:f9eeca106725 13904 #define TSC_IOSCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 13905 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13906 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
Kojto 122:f9eeca106725 13907 #define TSC_IOSCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 13908 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13909 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
Kojto 122:f9eeca106725 13910 #define TSC_IOSCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 13911 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13912 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
Kojto 122:f9eeca106725 13913 #define TSC_IOSCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 13914 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13915 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
Kojto 122:f9eeca106725 13916 #define TSC_IOSCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 13917 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13918 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
Kojto 122:f9eeca106725 13919 #define TSC_IOSCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 13920 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13921 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
Kojto 122:f9eeca106725 13922 #define TSC_IOSCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 13923 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13924 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
Kojto 122:f9eeca106725 13925 #define TSC_IOSCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 13926 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13927 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
Kojto 122:f9eeca106725 13928 #define TSC_IOSCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 13929 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13930 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
Kojto 122:f9eeca106725 13931 #define TSC_IOSCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 13932 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13933 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
Kojto 122:f9eeca106725 13934 #define TSC_IOSCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 13935 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13936 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
Kojto 122:f9eeca106725 13937 #define TSC_IOSCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 13938 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13939 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
Kojto 122:f9eeca106725 13940 #define TSC_IOSCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 13941 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13942 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
Kojto 122:f9eeca106725 13943 #define TSC_IOSCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 13944 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13945 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
Kojto 122:f9eeca106725 13946 #define TSC_IOSCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 13947 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13948 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
Kojto 122:f9eeca106725 13949 #define TSC_IOSCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 13950 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13951 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
Kojto 122:f9eeca106725 13952 #define TSC_IOSCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 13953 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13954 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
Kojto 122:f9eeca106725 13955 #define TSC_IOSCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 13956 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 13957 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
Kojto 122:f9eeca106725 13958 #define TSC_IOSCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 13959 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 13960 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
Kojto 122:f9eeca106725 13961 #define TSC_IOSCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 13962 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 13963 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
Kojto 122:f9eeca106725 13964 #define TSC_IOSCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 13965 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13966 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
bogdanm 86:04dd9b1680ae 13967
bogdanm 86:04dd9b1680ae 13968 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 122:f9eeca106725 13969 #define TSC_IOCCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 13970 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13971 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
Kojto 122:f9eeca106725 13972 #define TSC_IOCCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 13973 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13974 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
Kojto 122:f9eeca106725 13975 #define TSC_IOCCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 13976 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13977 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
Kojto 122:f9eeca106725 13978 #define TSC_IOCCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 13979 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13980 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
Kojto 122:f9eeca106725 13981 #define TSC_IOCCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 13982 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13983 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
Kojto 122:f9eeca106725 13984 #define TSC_IOCCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 13985 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13986 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
Kojto 122:f9eeca106725 13987 #define TSC_IOCCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 13988 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13989 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
Kojto 122:f9eeca106725 13990 #define TSC_IOCCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 13991 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13992 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
Kojto 122:f9eeca106725 13993 #define TSC_IOCCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 13994 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13995 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
Kojto 122:f9eeca106725 13996 #define TSC_IOCCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 13997 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13998 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
Kojto 122:f9eeca106725 13999 #define TSC_IOCCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 14000 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14001 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
Kojto 122:f9eeca106725 14002 #define TSC_IOCCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 14003 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14004 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
Kojto 122:f9eeca106725 14005 #define TSC_IOCCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 14006 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14007 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
Kojto 122:f9eeca106725 14008 #define TSC_IOCCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 14009 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14010 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
Kojto 122:f9eeca106725 14011 #define TSC_IOCCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 14012 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14013 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
Kojto 122:f9eeca106725 14014 #define TSC_IOCCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 14015 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14016 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
Kojto 122:f9eeca106725 14017 #define TSC_IOCCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 14018 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 14019 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
Kojto 122:f9eeca106725 14020 #define TSC_IOCCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 14021 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14022 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
Kojto 122:f9eeca106725 14023 #define TSC_IOCCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 14024 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14025 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
Kojto 122:f9eeca106725 14026 #define TSC_IOCCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 14027 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14028 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
Kojto 122:f9eeca106725 14029 #define TSC_IOCCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 14030 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14031 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
Kojto 122:f9eeca106725 14032 #define TSC_IOCCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 14033 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14034 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
Kojto 122:f9eeca106725 14035 #define TSC_IOCCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 14036 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14037 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
Kojto 122:f9eeca106725 14038 #define TSC_IOCCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 14039 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 14040 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
Kojto 122:f9eeca106725 14041 #define TSC_IOCCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 14042 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 14043 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
Kojto 122:f9eeca106725 14044 #define TSC_IOCCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 14045 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 14046 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
Kojto 122:f9eeca106725 14047 #define TSC_IOCCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 14048 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 14049 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
Kojto 122:f9eeca106725 14050 #define TSC_IOCCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 14051 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 14052 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
Kojto 122:f9eeca106725 14053 #define TSC_IOCCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 14054 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 14055 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
Kojto 122:f9eeca106725 14056 #define TSC_IOCCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 14057 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 14058 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
Kojto 122:f9eeca106725 14059 #define TSC_IOCCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 14060 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 14061 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
Kojto 122:f9eeca106725 14062 #define TSC_IOCCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 14063 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 14064 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
bogdanm 86:04dd9b1680ae 14065
bogdanm 86:04dd9b1680ae 14066 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 122:f9eeca106725 14067 #define TSC_IOGCSR_G1E_Pos (0U)
Kojto 122:f9eeca106725 14068 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14069 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
Kojto 122:f9eeca106725 14070 #define TSC_IOGCSR_G2E_Pos (1U)
Kojto 122:f9eeca106725 14071 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14072 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
Kojto 122:f9eeca106725 14073 #define TSC_IOGCSR_G3E_Pos (2U)
Kojto 122:f9eeca106725 14074 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14075 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
Kojto 122:f9eeca106725 14076 #define TSC_IOGCSR_G4E_Pos (3U)
Kojto 122:f9eeca106725 14077 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14078 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
Kojto 122:f9eeca106725 14079 #define TSC_IOGCSR_G5E_Pos (4U)
Kojto 122:f9eeca106725 14080 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14081 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
Kojto 122:f9eeca106725 14082 #define TSC_IOGCSR_G6E_Pos (5U)
Kojto 122:f9eeca106725 14083 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14084 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
Kojto 122:f9eeca106725 14085 #define TSC_IOGCSR_G7E_Pos (6U)
Kojto 122:f9eeca106725 14086 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14087 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
Kojto 122:f9eeca106725 14088 #define TSC_IOGCSR_G8E_Pos (7U)
Kojto 122:f9eeca106725 14089 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14090 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
Kojto 122:f9eeca106725 14091 #define TSC_IOGCSR_G1S_Pos (16U)
Kojto 122:f9eeca106725 14092 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 14093 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
Kojto 122:f9eeca106725 14094 #define TSC_IOGCSR_G2S_Pos (17U)
Kojto 122:f9eeca106725 14095 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14096 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
Kojto 122:f9eeca106725 14097 #define TSC_IOGCSR_G3S_Pos (18U)
Kojto 122:f9eeca106725 14098 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14099 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
Kojto 122:f9eeca106725 14100 #define TSC_IOGCSR_G4S_Pos (19U)
Kojto 122:f9eeca106725 14101 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14102 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
Kojto 122:f9eeca106725 14103 #define TSC_IOGCSR_G5S_Pos (20U)
Kojto 122:f9eeca106725 14104 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14105 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
Kojto 122:f9eeca106725 14106 #define TSC_IOGCSR_G6S_Pos (21U)
Kojto 122:f9eeca106725 14107 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14108 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
Kojto 122:f9eeca106725 14109 #define TSC_IOGCSR_G7S_Pos (22U)
Kojto 122:f9eeca106725 14110 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14111 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
Kojto 122:f9eeca106725 14112 #define TSC_IOGCSR_G8S_Pos (23U)
Kojto 122:f9eeca106725 14113 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 14114 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
bogdanm 86:04dd9b1680ae 14115
bogdanm 86:04dd9b1680ae 14116 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 122:f9eeca106725 14117 #define TSC_IOGXCR_CNT_Pos (0U)
Kojto 122:f9eeca106725 14118 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 14119 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
bogdanm 86:04dd9b1680ae 14120
bogdanm 86:04dd9b1680ae 14121 /******************************************************************************/
bogdanm 86:04dd9b1680ae 14122 /* */
bogdanm 86:04dd9b1680ae 14123 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 86:04dd9b1680ae 14124 /* */
bogdanm 86:04dd9b1680ae 14125 /******************************************************************************/
Kojto 122:f9eeca106725 14126
Kojto 122:f9eeca106725 14127 /*
Kojto 122:f9eeca106725 14128 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
Kojto 122:f9eeca106725 14129 */
Kojto 122:f9eeca106725 14130
Kojto 122:f9eeca106725 14131 /* Support of 7 bits data length feature */
Kojto 122:f9eeca106725 14132 #define USART_7BITS_SUPPORT
Kojto 122:f9eeca106725 14133
bogdanm 86:04dd9b1680ae 14134 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 14135 #define USART_CR1_UE_Pos (0U)
Kojto 122:f9eeca106725 14136 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14137 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
Kojto 122:f9eeca106725 14138 #define USART_CR1_UESM_Pos (1U)
Kojto 122:f9eeca106725 14139 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14140 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
Kojto 122:f9eeca106725 14141 #define USART_CR1_RE_Pos (2U)
Kojto 122:f9eeca106725 14142 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14143 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
Kojto 122:f9eeca106725 14144 #define USART_CR1_TE_Pos (3U)
Kojto 122:f9eeca106725 14145 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14146 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
Kojto 122:f9eeca106725 14147 #define USART_CR1_IDLEIE_Pos (4U)
Kojto 122:f9eeca106725 14148 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14149 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 14150 #define USART_CR1_RXNEIE_Pos (5U)
Kojto 122:f9eeca106725 14151 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14152 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 14153 #define USART_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 14154 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14155 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 14156 #define USART_CR1_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 14157 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14158 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
Kojto 122:f9eeca106725 14159 #define USART_CR1_PEIE_Pos (8U)
Kojto 122:f9eeca106725 14160 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14161 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 14162 #define USART_CR1_PS_Pos (9U)
Kojto 122:f9eeca106725 14163 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14164 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
Kojto 122:f9eeca106725 14165 #define USART_CR1_PCE_Pos (10U)
Kojto 122:f9eeca106725 14166 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14167 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
Kojto 122:f9eeca106725 14168 #define USART_CR1_WAKE_Pos (11U)
Kojto 122:f9eeca106725 14169 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14170 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
Kojto 122:f9eeca106725 14171 #define USART_CR1_M0_Pos (12U)
Kojto 122:f9eeca106725 14172 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14173 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
Kojto 122:f9eeca106725 14174 #define USART_CR1_MME_Pos (13U)
Kojto 122:f9eeca106725 14175 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14176 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
Kojto 122:f9eeca106725 14177 #define USART_CR1_CMIE_Pos (14U)
Kojto 122:f9eeca106725 14178 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14179 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
Kojto 122:f9eeca106725 14180 #define USART_CR1_OVER8_Pos (15U)
Kojto 122:f9eeca106725 14181 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14182 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 122:f9eeca106725 14183 #define USART_CR1_DEDT_Pos (16U)
Kojto 122:f9eeca106725 14184 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 14185 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 122:f9eeca106725 14186 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 14187 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14188 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14189 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14190 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14191 #define USART_CR1_DEAT_Pos (21U)
Kojto 122:f9eeca106725 14192 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
Kojto 122:f9eeca106725 14193 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 122:f9eeca106725 14194 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14195 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14196 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 14197 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 14198 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 14199 #define USART_CR1_RTOIE_Pos (26U)
Kojto 122:f9eeca106725 14200 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 14201 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
Kojto 122:f9eeca106725 14202 #define USART_CR1_EOBIE_Pos (27U)
Kojto 122:f9eeca106725 14203 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 14204 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
Kojto 122:f9eeca106725 14205 #define USART_CR1_M1_Pos (28U)
Kojto 122:f9eeca106725 14206 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 14207 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
Kojto 122:f9eeca106725 14208 #define USART_CR1_M_Pos (12U)
Kojto 122:f9eeca106725 14209 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
Kojto 122:f9eeca106725 14210 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
bogdanm 86:04dd9b1680ae 14211
bogdanm 86:04dd9b1680ae 14212 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 14213 #define USART_CR2_ADDM7_Pos (4U)
Kojto 122:f9eeca106725 14214 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14215 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
Kojto 122:f9eeca106725 14216 #define USART_CR2_LBDL_Pos (5U)
Kojto 122:f9eeca106725 14217 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14218 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
Kojto 122:f9eeca106725 14219 #define USART_CR2_LBDIE_Pos (6U)
Kojto 122:f9eeca106725 14220 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14221 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 14222 #define USART_CR2_LBCL_Pos (8U)
Kojto 122:f9eeca106725 14223 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14224 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 14225 #define USART_CR2_CPHA_Pos (9U)
Kojto 122:f9eeca106725 14226 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14227 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 14228 #define USART_CR2_CPOL_Pos (10U)
Kojto 122:f9eeca106725 14229 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14230 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 14231 #define USART_CR2_CLKEN_Pos (11U)
Kojto 122:f9eeca106725 14232 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14233 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
Kojto 122:f9eeca106725 14234 #define USART_CR2_STOP_Pos (12U)
Kojto 122:f9eeca106725 14235 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 14236 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 14237 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14238 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14239 #define USART_CR2_LINEN_Pos (14U)
Kojto 122:f9eeca106725 14240 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14241 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
Kojto 122:f9eeca106725 14242 #define USART_CR2_SWAP_Pos (15U)
Kojto 122:f9eeca106725 14243 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14244 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
Kojto 122:f9eeca106725 14245 #define USART_CR2_RXINV_Pos (16U)
Kojto 122:f9eeca106725 14246 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 14247 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
Kojto 122:f9eeca106725 14248 #define USART_CR2_TXINV_Pos (17U)
Kojto 122:f9eeca106725 14249 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14250 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
Kojto 122:f9eeca106725 14251 #define USART_CR2_DATAINV_Pos (18U)
Kojto 122:f9eeca106725 14252 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14253 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
Kojto 122:f9eeca106725 14254 #define USART_CR2_MSBFIRST_Pos (19U)
Kojto 122:f9eeca106725 14255 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14256 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
Kojto 122:f9eeca106725 14257 #define USART_CR2_ABREN_Pos (20U)
Kojto 122:f9eeca106725 14258 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14259 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
Kojto 122:f9eeca106725 14260 #define USART_CR2_ABRMODE_Pos (21U)
Kojto 122:f9eeca106725 14261 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 14262 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 122:f9eeca106725 14263 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14264 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14265 #define USART_CR2_RTOEN_Pos (23U)
Kojto 122:f9eeca106725 14266 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 14267 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
Kojto 122:f9eeca106725 14268 #define USART_CR2_ADD_Pos (24U)
Kojto 122:f9eeca106725 14269 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 14270 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
bogdanm 86:04dd9b1680ae 14271
bogdanm 86:04dd9b1680ae 14272 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 14273 #define USART_CR3_EIE_Pos (0U)
Kojto 122:f9eeca106725 14274 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14275 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 14276 #define USART_CR3_IREN_Pos (1U)
Kojto 122:f9eeca106725 14277 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14278 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
Kojto 122:f9eeca106725 14279 #define USART_CR3_IRLP_Pos (2U)
Kojto 122:f9eeca106725 14280 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14281 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
Kojto 122:f9eeca106725 14282 #define USART_CR3_HDSEL_Pos (3U)
Kojto 122:f9eeca106725 14283 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14284 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 14285 #define USART_CR3_NACK_Pos (4U)
Kojto 122:f9eeca106725 14286 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14287 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
Kojto 122:f9eeca106725 14288 #define USART_CR3_SCEN_Pos (5U)
Kojto 122:f9eeca106725 14289 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14290 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
Kojto 122:f9eeca106725 14291 #define USART_CR3_DMAR_Pos (6U)
Kojto 122:f9eeca106725 14292 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14293 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 14294 #define USART_CR3_DMAT_Pos (7U)
Kojto 122:f9eeca106725 14295 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14296 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 14297 #define USART_CR3_RTSE_Pos (8U)
Kojto 122:f9eeca106725 14298 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14299 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
Kojto 122:f9eeca106725 14300 #define USART_CR3_CTSE_Pos (9U)
Kojto 122:f9eeca106725 14301 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14302 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
Kojto 122:f9eeca106725 14303 #define USART_CR3_CTSIE_Pos (10U)
Kojto 122:f9eeca106725 14304 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14305 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 14306 #define USART_CR3_ONEBIT_Pos (11U)
Kojto 122:f9eeca106725 14307 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14308 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
Kojto 122:f9eeca106725 14309 #define USART_CR3_OVRDIS_Pos (12U)
Kojto 122:f9eeca106725 14310 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14311 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
Kojto 122:f9eeca106725 14312 #define USART_CR3_DDRE_Pos (13U)
Kojto 122:f9eeca106725 14313 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14314 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
Kojto 122:f9eeca106725 14315 #define USART_CR3_DEM_Pos (14U)
Kojto 122:f9eeca106725 14316 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14317 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
Kojto 122:f9eeca106725 14318 #define USART_CR3_DEP_Pos (15U)
Kojto 122:f9eeca106725 14319 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14320 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
Kojto 122:f9eeca106725 14321 #define USART_CR3_SCARCNT_Pos (17U)
Kojto 122:f9eeca106725 14322 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 14323 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 122:f9eeca106725 14324 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14325 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14326 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14327 #define USART_CR3_WUS_Pos (20U)
Kojto 122:f9eeca106725 14328 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 14329 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 122:f9eeca106725 14330 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14331 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14332 #define USART_CR3_WUFIE_Pos (22U)
Kojto 122:f9eeca106725 14333 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14334 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
bogdanm 86:04dd9b1680ae 14335
bogdanm 86:04dd9b1680ae 14336 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 14337 #define USART_BRR_DIV_FRACTION_Pos (0U)
Kojto 122:f9eeca106725 14338 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 14339 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 14340 #define USART_BRR_DIV_MANTISSA_Pos (4U)
Kojto 122:f9eeca106725 14341 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 14342 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
bogdanm 86:04dd9b1680ae 14343
bogdanm 86:04dd9b1680ae 14344 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 14345 #define USART_GTPR_PSC_Pos (0U)
Kojto 122:f9eeca106725 14346 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 14347 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 14348 #define USART_GTPR_GT_Pos (8U)
Kojto 122:f9eeca106725 14349 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 14350 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
bogdanm 86:04dd9b1680ae 14351
bogdanm 86:04dd9b1680ae 14352
bogdanm 86:04dd9b1680ae 14353 /******************* Bit definition for USART_RTOR register *****************/
Kojto 122:f9eeca106725 14354 #define USART_RTOR_RTO_Pos (0U)
Kojto 122:f9eeca106725 14355 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
Kojto 122:f9eeca106725 14356 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
Kojto 122:f9eeca106725 14357 #define USART_RTOR_BLEN_Pos (24U)
Kojto 122:f9eeca106725 14358 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 14359 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
bogdanm 86:04dd9b1680ae 14360
bogdanm 86:04dd9b1680ae 14361 /******************* Bit definition for USART_RQR register ******************/
Kojto 122:f9eeca106725 14362 #define USART_RQR_ABRRQ_Pos (0U)
Kojto 122:f9eeca106725 14363 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14364 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
Kojto 122:f9eeca106725 14365 #define USART_RQR_SBKRQ_Pos (1U)
Kojto 122:f9eeca106725 14366 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14367 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
Kojto 122:f9eeca106725 14368 #define USART_RQR_MMRQ_Pos (2U)
Kojto 122:f9eeca106725 14369 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14370 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
Kojto 122:f9eeca106725 14371 #define USART_RQR_RXFRQ_Pos (3U)
Kojto 122:f9eeca106725 14372 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14373 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
Kojto 122:f9eeca106725 14374 #define USART_RQR_TXFRQ_Pos (4U)
Kojto 122:f9eeca106725 14375 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14376 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
bogdanm 86:04dd9b1680ae 14377
bogdanm 86:04dd9b1680ae 14378 /******************* Bit definition for USART_ISR register ******************/
Kojto 122:f9eeca106725 14379 #define USART_ISR_PE_Pos (0U)
Kojto 122:f9eeca106725 14380 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14381 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
Kojto 122:f9eeca106725 14382 #define USART_ISR_FE_Pos (1U)
Kojto 122:f9eeca106725 14383 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14384 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
Kojto 122:f9eeca106725 14385 #define USART_ISR_NE_Pos (2U)
Kojto 122:f9eeca106725 14386 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14387 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
Kojto 122:f9eeca106725 14388 #define USART_ISR_ORE_Pos (3U)
Kojto 122:f9eeca106725 14389 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14390 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
Kojto 122:f9eeca106725 14391 #define USART_ISR_IDLE_Pos (4U)
Kojto 122:f9eeca106725 14392 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14393 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
Kojto 122:f9eeca106725 14394 #define USART_ISR_RXNE_Pos (5U)
Kojto 122:f9eeca106725 14395 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14396 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 14397 #define USART_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 14398 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14399 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
Kojto 122:f9eeca106725 14400 #define USART_ISR_TXE_Pos (7U)
Kojto 122:f9eeca106725 14401 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14402 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 14403 #define USART_ISR_LBDF_Pos (8U)
Kojto 122:f9eeca106725 14404 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14405 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
Kojto 122:f9eeca106725 14406 #define USART_ISR_CTSIF_Pos (9U)
Kojto 122:f9eeca106725 14407 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14408 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
Kojto 122:f9eeca106725 14409 #define USART_ISR_CTS_Pos (10U)
Kojto 122:f9eeca106725 14410 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14411 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
Kojto 122:f9eeca106725 14412 #define USART_ISR_RTOF_Pos (11U)
Kojto 122:f9eeca106725 14413 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14414 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
Kojto 122:f9eeca106725 14415 #define USART_ISR_EOBF_Pos (12U)
Kojto 122:f9eeca106725 14416 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14417 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
Kojto 122:f9eeca106725 14418 #define USART_ISR_ABRE_Pos (14U)
Kojto 122:f9eeca106725 14419 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14420 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
Kojto 122:f9eeca106725 14421 #define USART_ISR_ABRF_Pos (15U)
Kojto 122:f9eeca106725 14422 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14423 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
Kojto 122:f9eeca106725 14424 #define USART_ISR_BUSY_Pos (16U)
Kojto 122:f9eeca106725 14425 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 14426 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
Kojto 122:f9eeca106725 14427 #define USART_ISR_CMF_Pos (17U)
Kojto 122:f9eeca106725 14428 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14429 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
Kojto 122:f9eeca106725 14430 #define USART_ISR_SBKF_Pos (18U)
Kojto 122:f9eeca106725 14431 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 14432 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
Kojto 122:f9eeca106725 14433 #define USART_ISR_RWU_Pos (19U)
Kojto 122:f9eeca106725 14434 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 14435 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
Kojto 122:f9eeca106725 14436 #define USART_ISR_WUF_Pos (20U)
Kojto 122:f9eeca106725 14437 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14438 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
Kojto 122:f9eeca106725 14439 #define USART_ISR_TEACK_Pos (21U)
Kojto 122:f9eeca106725 14440 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 14441 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
Kojto 122:f9eeca106725 14442 #define USART_ISR_REACK_Pos (22U)
Kojto 122:f9eeca106725 14443 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 14444 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
bogdanm 86:04dd9b1680ae 14445
bogdanm 86:04dd9b1680ae 14446 /******************* Bit definition for USART_ICR register ******************/
Kojto 122:f9eeca106725 14447 #define USART_ICR_PECF_Pos (0U)
Kojto 122:f9eeca106725 14448 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14449 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
Kojto 122:f9eeca106725 14450 #define USART_ICR_FECF_Pos (1U)
Kojto 122:f9eeca106725 14451 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14452 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
Kojto 122:f9eeca106725 14453 #define USART_ICR_NCF_Pos (2U)
Kojto 122:f9eeca106725 14454 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14455 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
Kojto 122:f9eeca106725 14456 #define USART_ICR_ORECF_Pos (3U)
Kojto 122:f9eeca106725 14457 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14458 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
Kojto 122:f9eeca106725 14459 #define USART_ICR_IDLECF_Pos (4U)
Kojto 122:f9eeca106725 14460 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14461 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
Kojto 122:f9eeca106725 14462 #define USART_ICR_TCCF_Pos (6U)
Kojto 122:f9eeca106725 14463 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14464 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
Kojto 122:f9eeca106725 14465 #define USART_ICR_LBDCF_Pos (8U)
Kojto 122:f9eeca106725 14466 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14467 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
Kojto 122:f9eeca106725 14468 #define USART_ICR_CTSCF_Pos (9U)
Kojto 122:f9eeca106725 14469 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14470 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
Kojto 122:f9eeca106725 14471 #define USART_ICR_RTOCF_Pos (11U)
Kojto 122:f9eeca106725 14472 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14473 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
Kojto 122:f9eeca106725 14474 #define USART_ICR_EOBCF_Pos (12U)
Kojto 122:f9eeca106725 14475 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14476 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
Kojto 122:f9eeca106725 14477 #define USART_ICR_CMCF_Pos (17U)
Kojto 122:f9eeca106725 14478 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 14479 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
Kojto 122:f9eeca106725 14480 #define USART_ICR_WUCF_Pos (20U)
Kojto 122:f9eeca106725 14481 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 14482 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
bogdanm 86:04dd9b1680ae 14483
bogdanm 86:04dd9b1680ae 14484 /******************* Bit definition for USART_RDR register ******************/
Kojto 122:f9eeca106725 14485 #define USART_RDR_RDR_Pos (0U)
Kojto 122:f9eeca106725 14486 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 14487 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 86:04dd9b1680ae 14488
bogdanm 86:04dd9b1680ae 14489 /******************* Bit definition for USART_TDR register ******************/
Kojto 122:f9eeca106725 14490 #define USART_TDR_TDR_Pos (0U)
Kojto 122:f9eeca106725 14491 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 14492 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 86:04dd9b1680ae 14493
bogdanm 86:04dd9b1680ae 14494 /******************************************************************************/
bogdanm 86:04dd9b1680ae 14495 /* */
bogdanm 86:04dd9b1680ae 14496 /* Window WATCHDOG */
bogdanm 86:04dd9b1680ae 14497 /* */
bogdanm 86:04dd9b1680ae 14498 /******************************************************************************/
bogdanm 86:04dd9b1680ae 14499 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 14500 #define WWDG_CR_T_Pos (0U)
Kojto 122:f9eeca106725 14501 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 14502 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 14503 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14504 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14505 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14506 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14507 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14508 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14509 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14510
Kojto 122:f9eeca106725 14511 /* Legacy defines */
Kojto 122:f9eeca106725 14512 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 14513 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 14514 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 14515 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 14516 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 14517 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 14518 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 14519
Kojto 122:f9eeca106725 14520 #define WWDG_CR_WDGA_Pos (7U)
Kojto 122:f9eeca106725 14521 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14522 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
bogdanm 86:04dd9b1680ae 14523
bogdanm 86:04dd9b1680ae 14524 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 14525 #define WWDG_CFR_W_Pos (0U)
Kojto 122:f9eeca106725 14526 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 14527 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 14528 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14529 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 14530 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 14531 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 14532 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 14533 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 14534 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 14535
Kojto 122:f9eeca106725 14536 /* Legacy defines */
Kojto 122:f9eeca106725 14537 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 14538 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 14539 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 14540 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 14541 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 14542 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 14543 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 14544
Kojto 122:f9eeca106725 14545 #define WWDG_CFR_WDGTB_Pos (7U)
Kojto 122:f9eeca106725 14546 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
Kojto 122:f9eeca106725 14547 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 14548 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 14549 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 14550
Kojto 122:f9eeca106725 14551 /* Legacy defines */
Kojto 122:f9eeca106725 14552 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 14553 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 14554
Kojto 122:f9eeca106725 14555 #define WWDG_CFR_EWI_Pos (9U)
Kojto 122:f9eeca106725 14556 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 14557 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
bogdanm 86:04dd9b1680ae 14558
bogdanm 86:04dd9b1680ae 14559 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 14560 #define WWDG_SR_EWIF_Pos (0U)
Kojto 122:f9eeca106725 14561 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 14562 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
bogdanm 86:04dd9b1680ae 14563
bogdanm 86:04dd9b1680ae 14564 /**
bogdanm 86:04dd9b1680ae 14565 * @}
bogdanm 86:04dd9b1680ae 14566 */
bogdanm 86:04dd9b1680ae 14567
bogdanm 86:04dd9b1680ae 14568 /**
bogdanm 86:04dd9b1680ae 14569 * @}
bogdanm 86:04dd9b1680ae 14570 */
bogdanm 86:04dd9b1680ae 14571
bogdanm 86:04dd9b1680ae 14572 /** @addtogroup Exported_macros
bogdanm 86:04dd9b1680ae 14573 * @{
bogdanm 86:04dd9b1680ae 14574 */
bogdanm 86:04dd9b1680ae 14575
bogdanm 86:04dd9b1680ae 14576 /****************************** ADC Instances *********************************/
bogdanm 86:04dd9b1680ae 14577 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
bogdanm 86:04dd9b1680ae 14578 ((INSTANCE) == ADC2))
Kojto 122:f9eeca106725 14579
bogdanm 86:04dd9b1680ae 14580 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
bogdanm 86:04dd9b1680ae 14581
Kojto 122:f9eeca106725 14582 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
bogdanm 86:04dd9b1680ae 14583 /****************************** CAN Instances *********************************/
bogdanm 86:04dd9b1680ae 14584 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
bogdanm 86:04dd9b1680ae 14585
bogdanm 86:04dd9b1680ae 14586 /****************************** COMP Instances ********************************/
bogdanm 86:04dd9b1680ae 14587 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
bogdanm 86:04dd9b1680ae 14588 ((INSTANCE) == COMP4) || \
bogdanm 86:04dd9b1680ae 14589 ((INSTANCE) == COMP6))
bogdanm 86:04dd9b1680ae 14590
Kojto 122:f9eeca106725 14591 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U)
Kojto 122:f9eeca106725 14592
bogdanm 86:04dd9b1680ae 14593 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
Kojto 122:f9eeca106725 14594 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0U)
bogdanm 86:04dd9b1680ae 14595
bogdanm 86:04dd9b1680ae 14596 /******************** COMP Instances with window mode capability **************/
Kojto 122:f9eeca106725 14597 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U)
bogdanm 86:04dd9b1680ae 14598
bogdanm 86:04dd9b1680ae 14599 /****************************** CRC Instances *********************************/
bogdanm 86:04dd9b1680ae 14600 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 86:04dd9b1680ae 14601
bogdanm 86:04dd9b1680ae 14602 /****************************** DAC Instances *********************************/
bogdanm 86:04dd9b1680ae 14603 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
bogdanm 86:04dd9b1680ae 14604 ((INSTANCE) == DAC2))
bogdanm 86:04dd9b1680ae 14605
bogdanm 86:04dd9b1680ae 14606 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 86:04dd9b1680ae 14607 ((((INSTANCE) == DAC1) && \
bogdanm 86:04dd9b1680ae 14608 (((CHANNEL) == DAC_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14609 ((CHANNEL) == DAC_CHANNEL_2))) \
bogdanm 86:04dd9b1680ae 14610 || \
bogdanm 86:04dd9b1680ae 14611 (((INSTANCE) == DAC2) && \
bogdanm 86:04dd9b1680ae 14612 (((CHANNEL) == DAC_CHANNEL_1))))
bogdanm 86:04dd9b1680ae 14613
bogdanm 86:04dd9b1680ae 14614 /****************************** DMA Instances *********************************/
bogdanm 86:04dd9b1680ae 14615 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
bogdanm 86:04dd9b1680ae 14616 ((INSTANCE) == DMA1_Channel2) || \
bogdanm 86:04dd9b1680ae 14617 ((INSTANCE) == DMA1_Channel3) || \
bogdanm 86:04dd9b1680ae 14618 ((INSTANCE) == DMA1_Channel4) || \
bogdanm 86:04dd9b1680ae 14619 ((INSTANCE) == DMA1_Channel5) || \
bogdanm 86:04dd9b1680ae 14620 ((INSTANCE) == DMA1_Channel6) || \
bogdanm 86:04dd9b1680ae 14621 ((INSTANCE) == DMA1_Channel7))
bogdanm 86:04dd9b1680ae 14622
bogdanm 86:04dd9b1680ae 14623 /****************************** GPIO Instances ********************************/
Kojto 122:f9eeca106725 14624 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 122:f9eeca106725 14625 ((INSTANCE) == GPIOB) || \
Kojto 122:f9eeca106725 14626 ((INSTANCE) == GPIOC) || \
Kojto 122:f9eeca106725 14627 ((INSTANCE) == GPIOD) || \
Kojto 122:f9eeca106725 14628 ((INSTANCE) == GPIOF))
Kojto 122:f9eeca106725 14629
Kojto 122:f9eeca106725 14630 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 122:f9eeca106725 14631 ((INSTANCE) == GPIOB) || \
Kojto 122:f9eeca106725 14632 ((INSTANCE) == GPIOC) || \
Kojto 122:f9eeca106725 14633 ((INSTANCE) == GPIOD) || \
Kojto 122:f9eeca106725 14634 ((INSTANCE) == GPIOF))
Kojto 122:f9eeca106725 14635
Kojto 122:f9eeca106725 14636 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 122:f9eeca106725 14637 ((INSTANCE) == GPIOB) || \
Kojto 122:f9eeca106725 14638 ((INSTANCE) == GPIOC) || \
Kojto 122:f9eeca106725 14639 ((INSTANCE) == GPIOD) || \
Kojto 122:f9eeca106725 14640 ((INSTANCE) == GPIOF))
bogdanm 86:04dd9b1680ae 14641
bogdanm 86:04dd9b1680ae 14642 /****************************** HRTIM Instances *********************************/
bogdanm 86:04dd9b1680ae 14643 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
bogdanm 86:04dd9b1680ae 14644
bogdanm 86:04dd9b1680ae 14645 /****************************** I2C Instances *********************************/
Kojto 122:f9eeca106725 14646 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 122:f9eeca106725 14647
Kojto 122:f9eeca106725 14648 /****************** I2C Instances : wakeup capability from stop modes *********/
Kojto 122:f9eeca106725 14649 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 14650
Kojto 122:f9eeca106725 14651
Kojto 122:f9eeca106725 14652 /****************************** OPAMP Instances *******************************/
Kojto 122:f9eeca106725 14653 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
bogdanm 86:04dd9b1680ae 14654
bogdanm 86:04dd9b1680ae 14655 /****************************** IWDG Instances ********************************/
bogdanm 86:04dd9b1680ae 14656 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 86:04dd9b1680ae 14657
bogdanm 86:04dd9b1680ae 14658 /****************************** RTC Instances *********************************/
bogdanm 86:04dd9b1680ae 14659 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 86:04dd9b1680ae 14660
bogdanm 86:04dd9b1680ae 14661 /****************************** SMBUS Instances *******************************/
Kojto 122:f9eeca106725 14662 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm 86:04dd9b1680ae 14663
bogdanm 86:04dd9b1680ae 14664 /****************************** SPI Instances *********************************/
Kojto 122:f9eeca106725 14665 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
bogdanm 86:04dd9b1680ae 14666
bogdanm 86:04dd9b1680ae 14667 /******************* TIM Instances : All supported instances ******************/
bogdanm 86:04dd9b1680ae 14668 #define IS_TIM_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14669 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14670 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14671 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14672 ((INSTANCE) == TIM6) || \
bogdanm 86:04dd9b1680ae 14673 ((INSTANCE) == TIM7) || \
bogdanm 86:04dd9b1680ae 14674 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14675 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14676 ((INSTANCE) == TIM17))
Kojto 122:f9eeca106725 14677
bogdanm 86:04dd9b1680ae 14678 /******************* TIM Instances : at least 1 capture/compare channel *******/
bogdanm 86:04dd9b1680ae 14679 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14680 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14681 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14682 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14683 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14684 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14685 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14686
bogdanm 86:04dd9b1680ae 14687 /****************** TIM Instances : at least 2 capture/compare channels *******/
bogdanm 86:04dd9b1680ae 14688 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14689 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14690 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14691 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14692 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14693
bogdanm 86:04dd9b1680ae 14694 /****************** TIM Instances : at least 3 capture/compare channels *******/
bogdanm 86:04dd9b1680ae 14695 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14696 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14697 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14698 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14699
bogdanm 86:04dd9b1680ae 14700 /****************** TIM Instances : at least 4 capture/compare channels *******/
bogdanm 86:04dd9b1680ae 14701 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14702 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14703 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14704 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14705
bogdanm 86:04dd9b1680ae 14706 /****************** TIM Instances : at least 5 capture/compare channels *******/
bogdanm 86:04dd9b1680ae 14707 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14708 (((INSTANCE) == TIM1))
bogdanm 86:04dd9b1680ae 14709
bogdanm 86:04dd9b1680ae 14710 /****************** TIM Instances : at least 6 capture/compare channels *******/
bogdanm 86:04dd9b1680ae 14711 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14712 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 14713
bogdanm 86:04dd9b1680ae 14714 /************************** TIM Instances : Advanced-control timers ***********/
bogdanm 86:04dd9b1680ae 14715
bogdanm 86:04dd9b1680ae 14716 /****************** TIM Instances : supporting clock selection ****************/
bogdanm 86:04dd9b1680ae 14717 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14718 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14719 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14720 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14721 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14722
bogdanm 86:04dd9b1680ae 14723 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
bogdanm 86:04dd9b1680ae 14724 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14725 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14726 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14727 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14728
bogdanm 86:04dd9b1680ae 14729 /****************** TIM Instances : supporting external clock mode 2 **********/
bogdanm 86:04dd9b1680ae 14730 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14731 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14732 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14733 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14734
bogdanm 86:04dd9b1680ae 14735 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
bogdanm 86:04dd9b1680ae 14736 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14737 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14738 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14739 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14740 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14741
bogdanm 86:04dd9b1680ae 14742 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
bogdanm 86:04dd9b1680ae 14743 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14744 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14745 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14746 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14747 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14748
bogdanm 86:04dd9b1680ae 14749 /****************** TIM Instances : supporting OCxREF clear *******************/
bogdanm 86:04dd9b1680ae 14750 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14751 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14752 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14753 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14754
bogdanm 86:04dd9b1680ae 14755 /****************** TIM Instances : supporting encoder interface **************/
bogdanm 86:04dd9b1680ae 14756 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14757 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14758 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14759 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14760
bogdanm 86:04dd9b1680ae 14761 /****************** TIM Instances : supporting Hall interface *****************/
bogdanm 86:04dd9b1680ae 14762 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 122:f9eeca106725 14763 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 14764
Kojto 122:f9eeca106725 14765 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
Kojto 122:f9eeca106725 14766 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 14767
Kojto 122:f9eeca106725 14768 /**************** TIM Instances : external trigger input available ************/
Kojto 122:f9eeca106725 14769 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14770 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14771 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14772
bogdanm 86:04dd9b1680ae 14773 /****************** TIM Instances : supporting input XOR function *************/
bogdanm 86:04dd9b1680ae 14774 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14775 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14776 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14777 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14778 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14779
bogdanm 86:04dd9b1680ae 14780 /****************** TIM Instances : supporting master mode ********************/
bogdanm 86:04dd9b1680ae 14781 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14782 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14783 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14784 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14785 ((INSTANCE) == TIM6) || \
bogdanm 86:04dd9b1680ae 14786 ((INSTANCE) == TIM7) || \
bogdanm 86:04dd9b1680ae 14787 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14788
bogdanm 86:04dd9b1680ae 14789 /****************** TIM Instances : supporting slave mode *********************/
bogdanm 86:04dd9b1680ae 14790 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14791 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14792 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14793 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14794 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14795
bogdanm 86:04dd9b1680ae 14796 /****************** TIM Instances : supporting synchronization ****************/
bogdanm 86:04dd9b1680ae 14797 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14798 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14799 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14800 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14801 ((INSTANCE) == TIM6) || \
bogdanm 86:04dd9b1680ae 14802 ((INSTANCE) == TIM7) || \
bogdanm 86:04dd9b1680ae 14803 ((INSTANCE) == TIM15))
bogdanm 86:04dd9b1680ae 14804
bogdanm 86:04dd9b1680ae 14805 /****************** TIM Instances : supporting 32 bits counter ****************/
bogdanm 86:04dd9b1680ae 14806 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14807 ((INSTANCE) == TIM2)
bogdanm 86:04dd9b1680ae 14808
bogdanm 86:04dd9b1680ae 14809 /****************** TIM Instances : supporting DMA burst **********************/
bogdanm 86:04dd9b1680ae 14810 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14811 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14812 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14813 ((INSTANCE) == TIM3) || \
Kojto 122:f9eeca106725 14814 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14815 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14816 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14817
bogdanm 86:04dd9b1680ae 14818 /****************** TIM Instances : supporting the break function *************/
bogdanm 86:04dd9b1680ae 14819 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14820 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14821 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14822 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14823 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14824
bogdanm 86:04dd9b1680ae 14825 /****************** TIM Instances : supporting input/output channel(s) ********/
bogdanm 86:04dd9b1680ae 14826 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 86:04dd9b1680ae 14827 ((((INSTANCE) == TIM1) && \
bogdanm 86:04dd9b1680ae 14828 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14829 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 14830 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 14831 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 86:04dd9b1680ae 14832 ((CHANNEL) == TIM_CHANNEL_5) || \
bogdanm 86:04dd9b1680ae 14833 ((CHANNEL) == TIM_CHANNEL_6))) \
bogdanm 86:04dd9b1680ae 14834 || \
bogdanm 86:04dd9b1680ae 14835 (((INSTANCE) == TIM2) && \
bogdanm 86:04dd9b1680ae 14836 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14837 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 14838 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 14839 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 14840 || \
bogdanm 86:04dd9b1680ae 14841 (((INSTANCE) == TIM3) && \
bogdanm 86:04dd9b1680ae 14842 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14843 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 14844 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 14845 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 14846 || \
bogdanm 86:04dd9b1680ae 14847 (((INSTANCE) == TIM15) && \
bogdanm 86:04dd9b1680ae 14848 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14849 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 86:04dd9b1680ae 14850 || \
bogdanm 86:04dd9b1680ae 14851 (((INSTANCE) == TIM16) && \
bogdanm 86:04dd9b1680ae 14852 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 86:04dd9b1680ae 14853 || \
bogdanm 86:04dd9b1680ae 14854 (((INSTANCE) == TIM17) && \
bogdanm 86:04dd9b1680ae 14855 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 86:04dd9b1680ae 14856
bogdanm 86:04dd9b1680ae 14857 /****************** TIM Instances : supporting complementary output(s) ********/
bogdanm 86:04dd9b1680ae 14858 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 86:04dd9b1680ae 14859 ((((INSTANCE) == TIM1) && \
bogdanm 86:04dd9b1680ae 14860 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 14861 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 14862 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 86:04dd9b1680ae 14863 || \
bogdanm 86:04dd9b1680ae 14864 (((INSTANCE) == TIM15) && \
bogdanm 86:04dd9b1680ae 14865 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 86:04dd9b1680ae 14866 || \
bogdanm 86:04dd9b1680ae 14867 (((INSTANCE) == TIM16) && \
bogdanm 86:04dd9b1680ae 14868 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 86:04dd9b1680ae 14869 || \
bogdanm 86:04dd9b1680ae 14870 (((INSTANCE) == TIM17) && \
bogdanm 86:04dd9b1680ae 14871 ((CHANNEL) == TIM_CHANNEL_1)))
bogdanm 86:04dd9b1680ae 14872
bogdanm 86:04dd9b1680ae 14873 /****************** TIM Instances : supporting counting mode selection ********/
bogdanm 86:04dd9b1680ae 14874 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14875 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14876 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14877 ((INSTANCE) == TIM3))
bogdanm 86:04dd9b1680ae 14878
bogdanm 86:04dd9b1680ae 14879 /****************** TIM Instances : supporting repetition counter *************/
bogdanm 86:04dd9b1680ae 14880 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14881 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14882 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14883 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14884 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14885
bogdanm 86:04dd9b1680ae 14886 /****************** TIM Instances : supporting clock division *****************/
bogdanm 86:04dd9b1680ae 14887 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14888 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14889 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14890 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14891 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14892 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14893 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14894
bogdanm 86:04dd9b1680ae 14895 /****************** TIM Instances : supporting 2 break inputs *****************/
bogdanm 86:04dd9b1680ae 14896 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14897 (((INSTANCE) == TIM1))
bogdanm 86:04dd9b1680ae 14898
bogdanm 86:04dd9b1680ae 14899 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
bogdanm 86:04dd9b1680ae 14900 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14901 (((INSTANCE) == TIM1))
bogdanm 86:04dd9b1680ae 14902
bogdanm 86:04dd9b1680ae 14903 /****************** TIM Instances : supporting DMA generation on Update events*/
bogdanm 86:04dd9b1680ae 14904 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14905 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14906 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14907 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14908 ((INSTANCE) == TIM6) || \
bogdanm 86:04dd9b1680ae 14909 ((INSTANCE) == TIM7) || \
bogdanm 86:04dd9b1680ae 14910 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14911 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14912 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14913
bogdanm 86:04dd9b1680ae 14914 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
bogdanm 86:04dd9b1680ae 14915 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14916 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14917 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 14918 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 14919 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14920 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14921 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14922
bogdanm 86:04dd9b1680ae 14923 /****************** TIM Instances : supporting commutation event generation ***/
bogdanm 86:04dd9b1680ae 14924 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14925 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14926 ((INSTANCE) == TIM15) || \
bogdanm 86:04dd9b1680ae 14927 ((INSTANCE) == TIM16) || \
bogdanm 86:04dd9b1680ae 14928 ((INSTANCE) == TIM17))
bogdanm 86:04dd9b1680ae 14929
bogdanm 86:04dd9b1680ae 14930 /****************** TIM Instances : supporting remapping capability ***********/
bogdanm 86:04dd9b1680ae 14931 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
bogdanm 86:04dd9b1680ae 14932 (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 14933 ((INSTANCE) == TIM16))
bogdanm 86:04dd9b1680ae 14934
bogdanm 86:04dd9b1680ae 14935 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
bogdanm 86:04dd9b1680ae 14936 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
bogdanm 86:04dd9b1680ae 14937 (((INSTANCE) == TIM1))
bogdanm 86:04dd9b1680ae 14938
bogdanm 86:04dd9b1680ae 14939 /****************************** TSC Instances *********************************/
bogdanm 86:04dd9b1680ae 14940 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
bogdanm 86:04dd9b1680ae 14941
bogdanm 86:04dd9b1680ae 14942 /******************** USART Instances : Synchronous mode **********************/
bogdanm 86:04dd9b1680ae 14943 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 14944 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 14945 ((INSTANCE) == USART3))
bogdanm 86:04dd9b1680ae 14946
bogdanm 86:04dd9b1680ae 14947 /****************** USART Instances : Auto Baud Rate detection ****************/
bogdanm 86:04dd9b1680ae 14948 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 86:04dd9b1680ae 14949
bogdanm 86:04dd9b1680ae 14950 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 86:04dd9b1680ae 14951 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 14952 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 14953 ((INSTANCE) == USART3))
bogdanm 86:04dd9b1680ae 14954
bogdanm 86:04dd9b1680ae 14955 /******************** UART Instances : Half-Duplex mode **********************/
bogdanm 86:04dd9b1680ae 14956 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 14957 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 14958 ((INSTANCE) == USART3))
bogdanm 86:04dd9b1680ae 14959
bogdanm 86:04dd9b1680ae 14960 /******************** UART Instances : LIN mode **********************/
bogdanm 86:04dd9b1680ae 14961 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 122:f9eeca106725 14962
bogdanm 86:04dd9b1680ae 14963 /******************** UART Instances : Wake-up from Stop mode **********************/
bogdanm 86:04dd9b1680ae 14964 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 86:04dd9b1680ae 14965
bogdanm 86:04dd9b1680ae 14966 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 86:04dd9b1680ae 14967 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 14968 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 14969 ((INSTANCE) == USART3))
bogdanm 86:04dd9b1680ae 14970
bogdanm 86:04dd9b1680ae 14971 /****************** UART Instances : Auto Baud Rate detection *****************/
bogdanm 86:04dd9b1680ae 14972 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 86:04dd9b1680ae 14973
bogdanm 86:04dd9b1680ae 14974 /****************** UART Instances : Driver Enable ****************************/
bogdanm 86:04dd9b1680ae 14975 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 14976 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 14977 ((INSTANCE) == USART3))
bogdanm 86:04dd9b1680ae 14978
bogdanm 86:04dd9b1680ae 14979 /********************* UART Instances : Smard card mode ***********************/
bogdanm 86:04dd9b1680ae 14980 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 86:04dd9b1680ae 14981
bogdanm 86:04dd9b1680ae 14982 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 86:04dd9b1680ae 14983 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 86:04dd9b1680ae 14984
Kojto 122:f9eeca106725 14985 /******************** UART Instances : Support of continuous communication using DMA ****/
Kojto 122:f9eeca106725 14986 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
bogdanm 86:04dd9b1680ae 14987 /****************************** WWDG Instances ********************************/
bogdanm 86:04dd9b1680ae 14988 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 86:04dd9b1680ae 14989
bogdanm 86:04dd9b1680ae 14990 /**
bogdanm 86:04dd9b1680ae 14991 * @}
bogdanm 86:04dd9b1680ae 14992 */
bogdanm 86:04dd9b1680ae 14993
bogdanm 86:04dd9b1680ae 14994
bogdanm 86:04dd9b1680ae 14995 /******************************************************************************/
bogdanm 86:04dd9b1680ae 14996 /* For a painless codes migration between the STM32F3xx device product */
bogdanm 86:04dd9b1680ae 14997 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 86:04dd9b1680ae 14998 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 86:04dd9b1680ae 14999 /* No need to update developed interrupt code when moving across */
bogdanm 86:04dd9b1680ae 15000 /* product lines within the same STM32F3 Family */
bogdanm 86:04dd9b1680ae 15001 /******************************************************************************/
bogdanm 86:04dd9b1680ae 15002
bogdanm 86:04dd9b1680ae 15003 /* Aliases for __IRQn */
Kojto 122:f9eeca106725 15004 #define ADC1_IRQn ADC1_2_IRQn
Kojto 122:f9eeca106725 15005 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
Kojto 122:f9eeca106725 15006 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
Kojto 122:f9eeca106725 15007 #define COMP1_2_IRQn COMP2_IRQn
Kojto 122:f9eeca106725 15008 #define COMP1_2_3_IRQn COMP2_IRQn
Kojto 122:f9eeca106725 15009 #define COMP_IRQn COMP2_IRQn
Kojto 122:f9eeca106725 15010 #define COMP4_5_6_IRQn COMP4_6_IRQn
Kojto 122:f9eeca106725 15011 #define I2C3_ER_IRQn HRTIM1_FLT_IRQn
Kojto 122:f9eeca106725 15012 #define I2C3_EV_IRQn HRTIM1_TIME_IRQn
Kojto 122:f9eeca106725 15013 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
Kojto 122:f9eeca106725 15014 #define TIM18_DAC2_IRQn TIM1_CC_IRQn
Kojto 122:f9eeca106725 15015 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
Kojto 122:f9eeca106725 15016 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
Kojto 122:f9eeca106725 15017 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn
Kojto 122:f9eeca106725 15018 #define TIM7_IRQn TIM7_DAC2_IRQn
Kojto 122:f9eeca106725 15019
bogdanm 86:04dd9b1680ae 15020
bogdanm 86:04dd9b1680ae 15021 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 15022 #define ADC1_IRQHandler ADC1_2_IRQHandler
Kojto 122:f9eeca106725 15023 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
Kojto 122:f9eeca106725 15024 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
Kojto 122:f9eeca106725 15025 #define COMP1_2_IRQHandler COMP2_IRQHandler
Kojto 122:f9eeca106725 15026 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
Kojto 122:f9eeca106725 15027 #define COMP_IRQHandler COMP2_IRQHandler
Kojto 122:f9eeca106725 15028 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
Kojto 122:f9eeca106725 15029 #define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler
Kojto 122:f9eeca106725 15030 #define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler
Kojto 122:f9eeca106725 15031 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
Kojto 122:f9eeca106725 15032 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
Kojto 122:f9eeca106725 15033 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
Kojto 122:f9eeca106725 15034 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
Kojto 122:f9eeca106725 15035 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
Kojto 122:f9eeca106725 15036 #define TIM7_IRQHandler TIM7_DAC2_IRQHandler
Kojto 122:f9eeca106725 15037
bogdanm 86:04dd9b1680ae 15038
bogdanm 86:04dd9b1680ae 15039 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 15040 }
bogdanm 86:04dd9b1680ae 15041 #endif /* __cplusplus */
bogdanm 86:04dd9b1680ae 15042
bogdanm 86:04dd9b1680ae 15043 #endif /* __STM32F334x8_H */
bogdanm 86:04dd9b1680ae 15044
bogdanm 86:04dd9b1680ae 15045 /**
bogdanm 86:04dd9b1680ae 15046 * @}
bogdanm 86:04dd9b1680ae 15047 */
bogdanm 86:04dd9b1680ae 15048
bogdanm 86:04dd9b1680ae 15049 /**
bogdanm 86:04dd9b1680ae 15050 * @}
bogdanm 86:04dd9b1680ae 15051 */
bogdanm 86:04dd9b1680ae 15052
bogdanm 86:04dd9b1680ae 15053 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/