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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F091RC/stm32f091xc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
121:6c34061e7c34 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f091xc.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.3.0
Kojto 122:f9eeca106725 6 * @date 27-May-2016
Kojto 122:f9eeca106725 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
Kojto 122:f9eeca106725 8 * This file contains all the peripheral register's definitions, bits
Kojto 122:f9eeca106725 9 * definitions and memory mapping for STM32F0xx devices.
Kojto 122:f9eeca106725 10 *
Kojto 90:cb3d968589d8 11 * This file contains:
Kojto 90:cb3d968589d8 12 * - Data structures and the address mapping for all peripherals
Kojto 90:cb3d968589d8 13 * - Peripheral's registers declarations and bits definition
Kojto 90:cb3d968589d8 14 * - Macros to access peripheral’s registers hardware
Kojto 122:f9eeca106725 15 *
Kojto 90:cb3d968589d8 16 ******************************************************************************
Kojto 90:cb3d968589d8 17 * @attention
Kojto 90:cb3d968589d8 18 *
Kojto 122:f9eeca106725 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 20 *
Kojto 90:cb3d968589d8 21 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 22 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 23 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 24 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 26 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 27 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 29 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 30 * without specific prior written permission.
Kojto 90:cb3d968589d8 31 *
Kojto 90:cb3d968589d8 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 *
Kojto 90:cb3d968589d8 43 ******************************************************************************
Kojto 90:cb3d968589d8 44 */
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /** @addtogroup CMSIS
Kojto 90:cb3d968589d8 47 * @{
Kojto 90:cb3d968589d8 48 */
Kojto 90:cb3d968589d8 49
Kojto 90:cb3d968589d8 50 /** @addtogroup stm32f091xc
Kojto 90:cb3d968589d8 51 * @{
Kojto 90:cb3d968589d8 52 */
Kojto 122:f9eeca106725 53
Kojto 90:cb3d968589d8 54 #ifndef __STM32F091xC_H
Kojto 90:cb3d968589d8 55 #define __STM32F091xC_H
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 #ifdef __cplusplus
Kojto 90:cb3d968589d8 58 extern "C" {
Kojto 90:cb3d968589d8 59 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 60
Kojto 122:f9eeca106725 61 /** @addtogroup Configuration_section_for_CMSIS
Kojto 90:cb3d968589d8 62 * @{
Kojto 90:cb3d968589d8 63 */
Kojto 90:cb3d968589d8 64 /**
Kojto 90:cb3d968589d8 65 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 90:cb3d968589d8 66 */
Kojto 90:cb3d968589d8 67 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 90:cb3d968589d8 68 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 90:cb3d968589d8 69 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 122:f9eeca106725 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 71
Kojto 90:cb3d968589d8 72 /**
Kojto 90:cb3d968589d8 73 * @}
Kojto 90:cb3d968589d8 74 */
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 90:cb3d968589d8 77 * @{
Kojto 90:cb3d968589d8 78 */
Kojto 90:cb3d968589d8 79
Kojto 90:cb3d968589d8 80 /**
Kojto 122:f9eeca106725 81 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
Kojto 122:f9eeca106725 82 * in @ref Library_configuration_section
Kojto 90:cb3d968589d8 83 */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 /*!< Interrupt Number Definition */
Kojto 90:cb3d968589d8 86 typedef enum
Kojto 90:cb3d968589d8 87 {
Kojto 90:cb3d968589d8 88 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 90:cb3d968589d8 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 90:cb3d968589d8 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 90:cb3d968589d8 91 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 90:cb3d968589d8 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 90:cb3d968589d8 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 90:cb3d968589d8 94
Kojto 122:f9eeca106725 95 /****** STM32F0 specific Interrupt Numbers ******************************************************************/
Kojto 122:f9eeca106725 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 122:f9eeca106725 97 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */
Kojto 90:cb3d968589d8 98 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 90:cb3d968589d8 99 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 122:f9eeca106725 100 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */
Kojto 122:f9eeca106725 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
Kojto 122:f9eeca106725 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
Kojto 122:f9eeca106725 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
Kojto 90:cb3d968589d8 104 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
Kojto 90:cb3d968589d8 105 DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 90:cb3d968589d8 106 DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */
Kojto 122:f9eeca106725 107 DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupt */
Kojto 122:f9eeca106725 108 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
Kojto 122:f9eeca106725 109 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
Kojto 90:cb3d968589d8 110 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 90:cb3d968589d8 111 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
Kojto 90:cb3d968589d8 112 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 122:f9eeca106725 113 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */
Kojto 90:cb3d968589d8 114 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
Kojto 90:cb3d968589d8 115 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 90:cb3d968589d8 116 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
Kojto 90:cb3d968589d8 117 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 90:cb3d968589d8 118 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 90:cb3d968589d8 119 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 90:cb3d968589d8 120 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
Kojto 90:cb3d968589d8 121 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 90:cb3d968589d8 122 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Kojto 90:cb3d968589d8 123 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Kojto 90:cb3d968589d8 124 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
Kojto 122:f9eeca106725 125 USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupt */
Kojto 90:cb3d968589d8 126 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
Kojto 90:cb3d968589d8 127 } IRQn_Type;
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 /**
Kojto 90:cb3d968589d8 130 * @}
Kojto 90:cb3d968589d8 131 */
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 90:cb3d968589d8 134 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 90:cb3d968589d8 135 #include <stdint.h>
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 /** @addtogroup Peripheral_registers_structures
Kojto 90:cb3d968589d8 138 * @{
Kojto 90:cb3d968589d8 139 */
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /**
Kojto 90:cb3d968589d8 142 * @brief Analog to Digital Converter
Kojto 90:cb3d968589d8 143 */
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 typedef struct
Kojto 90:cb3d968589d8 146 {
Kojto 122:f9eeca106725 147 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 148 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
Kojto 122:f9eeca106725 149 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 150 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
Kojto 122:f9eeca106725 151 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
Kojto 122:f9eeca106725 152 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
Kojto 122:f9eeca106725 153 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 122:f9eeca106725 154 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 155 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
Kojto 122:f9eeca106725 156 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 122:f9eeca106725 157 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
Kojto 122:f9eeca106725 158 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 122:f9eeca106725 159 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
Kojto 122:f9eeca106725 160 } ADC_TypeDef;
Kojto 90:cb3d968589d8 161
Kojto 90:cb3d968589d8 162 typedef struct
Kojto 90:cb3d968589d8 163 {
Kojto 122:f9eeca106725 164 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
Kojto 122:f9eeca106725 165 } ADC_Common_TypeDef;
Kojto 122:f9eeca106725 166
Kojto 122:f9eeca106725 167 /**
Kojto 90:cb3d968589d8 168 * @brief Controller Area Network TxMailBox
Kojto 90:cb3d968589d8 169 */
Kojto 90:cb3d968589d8 170 typedef struct
Kojto 90:cb3d968589d8 171 {
Kojto 90:cb3d968589d8 172 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 90:cb3d968589d8 173 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 90:cb3d968589d8 174 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 90:cb3d968589d8 175 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 90:cb3d968589d8 176 }CAN_TxMailBox_TypeDef;
Kojto 90:cb3d968589d8 177
Kojto 90:cb3d968589d8 178 /**
Kojto 90:cb3d968589d8 179 * @brief Controller Area Network FIFOMailBox
Kojto 90:cb3d968589d8 180 */
Kojto 90:cb3d968589d8 181 typedef struct
Kojto 90:cb3d968589d8 182 {
Kojto 90:cb3d968589d8 183 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 90:cb3d968589d8 184 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 90:cb3d968589d8 185 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 90:cb3d968589d8 186 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 90:cb3d968589d8 187 }CAN_FIFOMailBox_TypeDef;
Kojto 90:cb3d968589d8 188
Kojto 90:cb3d968589d8 189 /**
Kojto 90:cb3d968589d8 190 * @brief Controller Area Network FilterRegister
Kojto 90:cb3d968589d8 191 */
Kojto 90:cb3d968589d8 192 typedef struct
Kojto 90:cb3d968589d8 193 {
Kojto 90:cb3d968589d8 194 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 90:cb3d968589d8 195 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 90:cb3d968589d8 196 }CAN_FilterRegister_TypeDef;
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 /**
Kojto 90:cb3d968589d8 199 * @brief Controller Area Network
Kojto 90:cb3d968589d8 200 */
Kojto 90:cb3d968589d8 201 typedef struct
Kojto 90:cb3d968589d8 202 {
Kojto 90:cb3d968589d8 203 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 204 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 205 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 206 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 207 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 208 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 209 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 210 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 211 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 90:cb3d968589d8 212 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 90:cb3d968589d8 213 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 90:cb3d968589d8 214 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 90:cb3d968589d8 215 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 90:cb3d968589d8 216 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 90:cb3d968589d8 217 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 90:cb3d968589d8 218 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 90:cb3d968589d8 219 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 90:cb3d968589d8 220 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 90:cb3d968589d8 221 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 90:cb3d968589d8 222 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 90:cb3d968589d8 223 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 90:cb3d968589d8 224 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 90:cb3d968589d8 225 }CAN_TypeDef;
Kojto 90:cb3d968589d8 226
Kojto 90:cb3d968589d8 227 /**
Kojto 90:cb3d968589d8 228 * @brief HDMI-CEC
Kojto 90:cb3d968589d8 229 */
Kojto 90:cb3d968589d8 230
Kojto 90:cb3d968589d8 231 typedef struct
Kojto 90:cb3d968589d8 232 {
Kojto 90:cb3d968589d8 233 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 90:cb3d968589d8 234 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 90:cb3d968589d8 235 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 90:cb3d968589d8 236 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 90:cb3d968589d8 237 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 90:cb3d968589d8 238 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 90:cb3d968589d8 239 }CEC_TypeDef;
Kojto 90:cb3d968589d8 240
Kojto 122:f9eeca106725 241 /**
Kojto 122:f9eeca106725 242 * @brief Comparator
Kojto 90:cb3d968589d8 243 */
Kojto 90:cb3d968589d8 244
Kojto 90:cb3d968589d8 245 typedef struct
Kojto 90:cb3d968589d8 246 {
Kojto 122:f9eeca106725 247 __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 248 } COMP_TypeDef;
Kojto 90:cb3d968589d8 249
Kojto 90:cb3d968589d8 250 typedef struct
Kojto 90:cb3d968589d8 251 {
Kojto 122:f9eeca106725 252 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
Kojto 122:f9eeca106725 253 } COMP_Common_TypeDef;
Kojto 122:f9eeca106725 254
Kojto 122:f9eeca106725 255 /* Legacy defines */
Kojto 122:f9eeca106725 256 typedef struct
Kojto 122:f9eeca106725 257 {
Kojto 122:f9eeca106725 258 __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */
Kojto 122:f9eeca106725 259 }COMP1_2_TypeDef;
Kojto 122:f9eeca106725 260
Kojto 122:f9eeca106725 261 /**
Kojto 90:cb3d968589d8 262 * @brief CRC calculation unit
Kojto 90:cb3d968589d8 263 */
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265 typedef struct
Kojto 90:cb3d968589d8 266 {
Kojto 90:cb3d968589d8 267 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 268 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 269 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 90:cb3d968589d8 270 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 122:f9eeca106725 271 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 272 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 90:cb3d968589d8 273 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 274 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 122:f9eeca106725 275 } CRC_TypeDef;
Kojto 122:f9eeca106725 276
Kojto 122:f9eeca106725 277 /**
Kojto 90:cb3d968589d8 278 * @brief Clock Recovery System
Kojto 90:cb3d968589d8 279 */
Kojto 90:cb3d968589d8 280 typedef struct
Kojto 90:cb3d968589d8 281 {
Kojto 90:cb3d968589d8 282 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 283 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 284 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 285 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 286 }CRS_TypeDef;
Kojto 90:cb3d968589d8 287
Kojto 90:cb3d968589d8 288 /**
Kojto 90:cb3d968589d8 289 * @brief Digital to Analog Converter
Kojto 90:cb3d968589d8 290 */
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 typedef struct
Kojto 90:cb3d968589d8 293 {
Kojto 122:f9eeca106725 294 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 295 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 122:f9eeca106725 296 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 122:f9eeca106725 297 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 122:f9eeca106725 298 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 122:f9eeca106725 299 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 122:f9eeca106725 300 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 122:f9eeca106725 301 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 122:f9eeca106725 302 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 122:f9eeca106725 303 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 122:f9eeca106725 304 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 122:f9eeca106725 305 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 122:f9eeca106725 306 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 122:f9eeca106725 307 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 122:f9eeca106725 308 } DAC_TypeDef;
Kojto 122:f9eeca106725 309
Kojto 122:f9eeca106725 310 /**
Kojto 90:cb3d968589d8 311 * @brief Debug MCU
Kojto 90:cb3d968589d8 312 */
Kojto 90:cb3d968589d8 313
Kojto 90:cb3d968589d8 314 typedef struct
Kojto 90:cb3d968589d8 315 {
Kojto 90:cb3d968589d8 316 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 90:cb3d968589d8 317 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 318 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 319 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 320 }DBGMCU_TypeDef;
Kojto 90:cb3d968589d8 321
Kojto 122:f9eeca106725 322 /**
Kojto 90:cb3d968589d8 323 * @brief DMA Controller
Kojto 90:cb3d968589d8 324 */
Kojto 90:cb3d968589d8 325
Kojto 90:cb3d968589d8 326 typedef struct
Kojto 90:cb3d968589d8 327 {
Kojto 122:f9eeca106725 328 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 122:f9eeca106725 329 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 122:f9eeca106725 330 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 122:f9eeca106725 331 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 122:f9eeca106725 332 } DMA_Channel_TypeDef;
Kojto 90:cb3d968589d8 333
Kojto 90:cb3d968589d8 334 typedef struct
Kojto 90:cb3d968589d8 335 {
Kojto 122:f9eeca106725 336 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 337 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 338 uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */
Kojto 93:e188a91d3eaa 339 __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */
Kojto 122:f9eeca106725 340 } DMA_TypeDef;
Kojto 90:cb3d968589d8 341
Kojto 90:cb3d968589d8 342 /**
Kojto 90:cb3d968589d8 343 * @brief External Interrupt/Event Controller
Kojto 90:cb3d968589d8 344 */
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 typedef struct
Kojto 90:cb3d968589d8 347 {
Kojto 122:f9eeca106725 348 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 122:f9eeca106725 349 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 122:f9eeca106725 350 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 122:f9eeca106725 351 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 122:f9eeca106725 352 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 122:f9eeca106725 353 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 122:f9eeca106725 354 } EXTI_TypeDef;
Kojto 90:cb3d968589d8 355
Kojto 90:cb3d968589d8 356 /**
Kojto 90:cb3d968589d8 357 * @brief FLASH Registers
Kojto 90:cb3d968589d8 358 */
Kojto 90:cb3d968589d8 359 typedef struct
Kojto 90:cb3d968589d8 360 {
Kojto 90:cb3d968589d8 361 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 362 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 363 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 364 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 365 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 366 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 367 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 90:cb3d968589d8 368 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 369 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 122:f9eeca106725 370 } FLASH_TypeDef;
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 /**
Kojto 90:cb3d968589d8 373 * @brief Option Bytes Registers
Kojto 90:cb3d968589d8 374 */
Kojto 90:cb3d968589d8 375 typedef struct
Kojto 90:cb3d968589d8 376 {
Kojto 90:cb3d968589d8 377 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 90:cb3d968589d8 378 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 90:cb3d968589d8 379 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 90:cb3d968589d8 380 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 90:cb3d968589d8 381 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 90:cb3d968589d8 382 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 90:cb3d968589d8 383 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
Kojto 90:cb3d968589d8 384 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
Kojto 122:f9eeca106725 385 } OB_TypeDef;
Kojto 122:f9eeca106725 386
Kojto 122:f9eeca106725 387 /**
Kojto 90:cb3d968589d8 388 * @brief General Purpose I/O
Kojto 90:cb3d968589d8 389 */
Kojto 90:cb3d968589d8 390
Kojto 90:cb3d968589d8 391 typedef struct
Kojto 90:cb3d968589d8 392 {
Kojto 122:f9eeca106725 393 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 122:f9eeca106725 394 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 122:f9eeca106725 395 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 122:f9eeca106725 396 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 122:f9eeca106725 397 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 122:f9eeca106725 398 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 399 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 122:f9eeca106725 400 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 401 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 122:f9eeca106725 402 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 122:f9eeca106725 403 } GPIO_TypeDef;
Kojto 122:f9eeca106725 404
Kojto 122:f9eeca106725 405 /**
Kojto 90:cb3d968589d8 406 * @brief SysTem Configuration
Kojto 90:cb3d968589d8 407 */
Kojto 90:cb3d968589d8 408
Kojto 90:cb3d968589d8 409 typedef struct
Kojto 90:cb3d968589d8 410 {
Kojto 90:cb3d968589d8 411 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 412 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 90:cb3d968589d8 413 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 90:cb3d968589d8 414 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 122:f9eeca106725 415 uint32_t RESERVED1[25]; /*!< Reserved + COMP, 0x1C */
Kojto 90:cb3d968589d8 416 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
Kojto 122:f9eeca106725 417 } SYSCFG_TypeDef;
Kojto 90:cb3d968589d8 418
Kojto 90:cb3d968589d8 419 /**
Kojto 90:cb3d968589d8 420 * @brief Inter-integrated Circuit Interface
Kojto 90:cb3d968589d8 421 */
Kojto 90:cb3d968589d8 422
Kojto 90:cb3d968589d8 423 typedef struct
Kojto 90:cb3d968589d8 424 {
Kojto 122:f9eeca106725 425 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 426 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 427 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 428 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 429 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 430 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 431 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 432 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 433 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 434 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 435 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 436 } I2C_TypeDef;
Kojto 122:f9eeca106725 437
Kojto 122:f9eeca106725 438 /**
Kojto 90:cb3d968589d8 439 * @brief Independent WATCHDOG
Kojto 90:cb3d968589d8 440 */
Kojto 90:cb3d968589d8 441
Kojto 90:cb3d968589d8 442 typedef struct
Kojto 90:cb3d968589d8 443 {
Kojto 90:cb3d968589d8 444 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 445 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 446 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 447 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 448 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 122:f9eeca106725 449 } IWDG_TypeDef;
Kojto 122:f9eeca106725 450
Kojto 122:f9eeca106725 451 /**
Kojto 90:cb3d968589d8 452 * @brief Power Control
Kojto 90:cb3d968589d8 453 */
Kojto 90:cb3d968589d8 454
Kojto 90:cb3d968589d8 455 typedef struct
Kojto 90:cb3d968589d8 456 {
Kojto 122:f9eeca106725 457 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 458 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 459 } PWR_TypeDef;
Kojto 122:f9eeca106725 460
Kojto 122:f9eeca106725 461 /**
Kojto 90:cb3d968589d8 462 * @brief Reset and Clock Control
Kojto 90:cb3d968589d8 463 */
Kojto 108:34e6b704fe68 464
Kojto 90:cb3d968589d8 465 typedef struct
Kojto 90:cb3d968589d8 466 {
Kojto 122:f9eeca106725 467 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 468 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 469 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 470 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 471 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 472 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 473 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 474 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 475 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 476 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 477 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 478 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 90:cb3d968589d8 479 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 90:cb3d968589d8 480 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 122:f9eeca106725 481 } RCC_TypeDef;
Kojto 90:cb3d968589d8 482
Kojto 90:cb3d968589d8 483 /**
Kojto 90:cb3d968589d8 484 * @brief Real-Time Clock
Kojto 90:cb3d968589d8 485 */
Kojto 90:cb3d968589d8 486 typedef struct
Kojto 90:cb3d968589d8 487 {
Kojto 122:f9eeca106725 488 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 122:f9eeca106725 489 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 122:f9eeca106725 490 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 491 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 492 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 493 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 122:f9eeca106725 494 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
Kojto 122:f9eeca106725 495 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 122:f9eeca106725 496 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
Kojto 122:f9eeca106725 497 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 122:f9eeca106725 498 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 122:f9eeca106725 499 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 122:f9eeca106725 500 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 122:f9eeca106725 501 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 122:f9eeca106725 502 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 122:f9eeca106725 503 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 122:f9eeca106725 504 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 122:f9eeca106725 505 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 122:f9eeca106725 506 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
Kojto 122:f9eeca106725 507 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
Kojto 122:f9eeca106725 508 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 122:f9eeca106725 509 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 122:f9eeca106725 510 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 122:f9eeca106725 511 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 122:f9eeca106725 512 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 122:f9eeca106725 513 } RTC_TypeDef;
Kojto 122:f9eeca106725 514
Kojto 122:f9eeca106725 515 /**
Kojto 90:cb3d968589d8 516 * @brief Serial Peripheral Interface
Kojto 90:cb3d968589d8 517 */
Kojto 90:cb3d968589d8 518
Kojto 90:cb3d968589d8 519 typedef struct
Kojto 90:cb3d968589d8 520 {
Kojto 122:f9eeca106725 521 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 122:f9eeca106725 522 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 523 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 524 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 122:f9eeca106725 525 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 122:f9eeca106725 526 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 122:f9eeca106725 527 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 122:f9eeca106725 528 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 122:f9eeca106725 529 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 122:f9eeca106725 530 } SPI_TypeDef;
Kojto 122:f9eeca106725 531
Kojto 122:f9eeca106725 532 /**
Kojto 90:cb3d968589d8 533 * @brief TIM
Kojto 90:cb3d968589d8 534 */
Kojto 90:cb3d968589d8 535 typedef struct
Kojto 90:cb3d968589d8 536 {
Kojto 122:f9eeca106725 537 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 538 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 539 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 540 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 122:f9eeca106725 541 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 542 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 122:f9eeca106725 543 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 122:f9eeca106725 544 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 122:f9eeca106725 545 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 122:f9eeca106725 546 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 122:f9eeca106725 547 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 122:f9eeca106725 548 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 549 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 122:f9eeca106725 550 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 122:f9eeca106725 551 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 122:f9eeca106725 552 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 122:f9eeca106725 553 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 90:cb3d968589d8 554 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 122:f9eeca106725 555 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 556 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 122:f9eeca106725 557 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 122:f9eeca106725 558 } TIM_TypeDef;
Kojto 90:cb3d968589d8 559
Kojto 90:cb3d968589d8 560 /**
Kojto 90:cb3d968589d8 561 * @brief Touch Sensing Controller (TSC)
Kojto 90:cb3d968589d8 562 */
Kojto 90:cb3d968589d8 563 typedef struct
Kojto 90:cb3d968589d8 564 {
Kojto 90:cb3d968589d8 565 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 566 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 567 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 568 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 569 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 570 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 90:cb3d968589d8 571 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 572 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 90:cb3d968589d8 573 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 574 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 90:cb3d968589d8 575 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 576 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 90:cb3d968589d8 577 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 578 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Kojto 90:cb3d968589d8 579 }TSC_TypeDef;
Kojto 90:cb3d968589d8 580
Kojto 122:f9eeca106725 581 /**
Kojto 90:cb3d968589d8 582 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 90:cb3d968589d8 583 */
Kojto 122:f9eeca106725 584
Kojto 90:cb3d968589d8 585 typedef struct
Kojto 90:cb3d968589d8 586 {
Kojto 90:cb3d968589d8 587 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 588 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 589 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 90:cb3d968589d8 590 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 591 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 592 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 593 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 594 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 595 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 596 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 597 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 90:cb3d968589d8 598 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 599 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 122:f9eeca106725 600 } USART_TypeDef;
Kojto 122:f9eeca106725 601
Kojto 122:f9eeca106725 602 /**
Kojto 90:cb3d968589d8 603 * @brief Window WATCHDOG
Kojto 90:cb3d968589d8 604 */
Kojto 90:cb3d968589d8 605 typedef struct
Kojto 90:cb3d968589d8 606 {
Kojto 90:cb3d968589d8 607 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 608 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 609 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 610 } WWDG_TypeDef;
Kojto 122:f9eeca106725 611
Kojto 122:f9eeca106725 612 /**
Kojto 90:cb3d968589d8 613 * @}
Kojto 90:cb3d968589d8 614 */
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 /** @addtogroup Peripheral_memory_map
Kojto 90:cb3d968589d8 617 * @{
Kojto 90:cb3d968589d8 618 */
Kojto 90:cb3d968589d8 619
Kojto 122:f9eeca106725 620 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
Kojto 122:f9eeca106725 621 #define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< FLASH END address of bank1 */
Kojto 122:f9eeca106725 622 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
Kojto 122:f9eeca106725 623 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
Kojto 90:cb3d968589d8 624
Kojto 90:cb3d968589d8 625 /*!< Peripheral memory map */
Kojto 90:cb3d968589d8 626 #define APBPERIPH_BASE PERIPH_BASE
Kojto 90:cb3d968589d8 627 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 90:cb3d968589d8 628 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 90:cb3d968589d8 629
Kojto 122:f9eeca106725 630 /*!< APB peripherals */
Kojto 90:cb3d968589d8 631 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 632 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 633 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 634 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
Kojto 90:cb3d968589d8 635 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 90:cb3d968589d8 636 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 90:cb3d968589d8 637 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 90:cb3d968589d8 638 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 639 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 90:cb3d968589d8 640 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 90:cb3d968589d8 641 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
Kojto 90:cb3d968589d8 642 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
Kojto 90:cb3d968589d8 643 #define USART5_BASE (APBPERIPH_BASE + 0x00005000)
Kojto 90:cb3d968589d8 644 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 90:cb3d968589d8 645 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto 90:cb3d968589d8 646 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
Kojto 90:cb3d968589d8 647 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
Kojto 90:cb3d968589d8 648 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 90:cb3d968589d8 649 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
Kojto 108:34e6b704fe68 650
Kojto 90:cb3d968589d8 651 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
Kojto 90:cb3d968589d8 652
Kojto 90:cb3d968589d8 653 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 90:cb3d968589d8 654 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
Kojto 90:cb3d968589d8 655 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 90:cb3d968589d8 656 #define USART6_BASE (APBPERIPH_BASE + 0x00011400)
Kojto 90:cb3d968589d8 657 #define USART7_BASE (APBPERIPH_BASE + 0x00011800)
Kojto 90:cb3d968589d8 658 #define USART8_BASE (APBPERIPH_BASE + 0x00011C00)
Kojto 90:cb3d968589d8 659 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 90:cb3d968589d8 660 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 90:cb3d968589d8 661 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 90:cb3d968589d8 662 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 90:cb3d968589d8 663 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 90:cb3d968589d8 664 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Kojto 90:cb3d968589d8 665 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 90:cb3d968589d8 666 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 90:cb3d968589d8 667 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 90:cb3d968589d8 668
Kojto 122:f9eeca106725 669 /*!< AHB peripherals */
Kojto 90:cb3d968589d8 670 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 671 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 90:cb3d968589d8 672 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 90:cb3d968589d8 673 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 90:cb3d968589d8 674 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 90:cb3d968589d8 675 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 90:cb3d968589d8 676 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Kojto 90:cb3d968589d8 677 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Kojto 90:cb3d968589d8 678 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 679 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
Kojto 90:cb3d968589d8 680 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
Kojto 90:cb3d968589d8 681 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
Kojto 90:cb3d968589d8 682 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
Kojto 90:cb3d968589d8 683 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
Kojto 90:cb3d968589d8 684
Kojto 90:cb3d968589d8 685 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 686 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 122:f9eeca106725 687 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
Kojto 122:f9eeca106725 688 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
Kojto 122:f9eeca106725 689 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
Kojto 90:cb3d968589d8 690 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 691 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
Kojto 90:cb3d968589d8 692
Kojto 122:f9eeca106725 693 /*!< AHB2 peripherals */
Kojto 90:cb3d968589d8 694 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 695 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 696 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 90:cb3d968589d8 697 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto 90:cb3d968589d8 698 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 699 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 90:cb3d968589d8 700
Kojto 90:cb3d968589d8 701 /**
Kojto 90:cb3d968589d8 702 * @}
Kojto 90:cb3d968589d8 703 */
Kojto 122:f9eeca106725 704
Kojto 90:cb3d968589d8 705 /** @addtogroup Peripheral_declaration
Kojto 90:cb3d968589d8 706 * @{
Kojto 122:f9eeca106725 707 */
Kojto 90:cb3d968589d8 708
Kojto 90:cb3d968589d8 709 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 90:cb3d968589d8 710 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 90:cb3d968589d8 711 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 90:cb3d968589d8 712 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 90:cb3d968589d8 713 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 90:cb3d968589d8 714 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 90:cb3d968589d8 715 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 90:cb3d968589d8 716 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 90:cb3d968589d8 717 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 90:cb3d968589d8 718 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 90:cb3d968589d8 719 #define USART4 ((USART_TypeDef *) USART4_BASE)
Kojto 90:cb3d968589d8 720 #define USART5 ((USART_TypeDef *) USART5_BASE)
Kojto 90:cb3d968589d8 721 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 90:cb3d968589d8 722 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 121:6c34061e7c34 723 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
Kojto 90:cb3d968589d8 724 #define CRS ((CRS_TypeDef *) CRS_BASE)
Kojto 90:cb3d968589d8 725 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 122:f9eeca106725 726 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
Kojto 122:f9eeca106725 727 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
Kojto 90:cb3d968589d8 728 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 90:cb3d968589d8 729 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 90:cb3d968589d8 730 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
Kojto 90:cb3d968589d8 731 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
Kojto 122:f9eeca106725 732 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE)
Kojto 122:f9eeca106725 733 #define COMP ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */
Kojto 90:cb3d968589d8 734 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 90:cb3d968589d8 735 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 90:cb3d968589d8 736 #define USART7 ((USART_TypeDef *) USART7_BASE)
Kojto 90:cb3d968589d8 737 #define USART8 ((USART_TypeDef *) USART8_BASE)
Kojto 90:cb3d968589d8 738 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 122:f9eeca106725 739 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 122:f9eeca106725 740 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
Kojto 90:cb3d968589d8 741 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 90:cb3d968589d8 742 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 122:f9eeca106725 743 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 90:cb3d968589d8 744 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 90:cb3d968589d8 745 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 90:cb3d968589d8 746 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 90:cb3d968589d8 747 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 90:cb3d968589d8 748 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 90:cb3d968589d8 749 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 90:cb3d968589d8 750 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 90:cb3d968589d8 751 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 90:cb3d968589d8 752 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 90:cb3d968589d8 753 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 90:cb3d968589d8 754 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 90:cb3d968589d8 755 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 90:cb3d968589d8 756 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 90:cb3d968589d8 757 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 90:cb3d968589d8 758 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Kojto 90:cb3d968589d8 759 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Kojto 90:cb3d968589d8 760 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Kojto 90:cb3d968589d8 761 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Kojto 90:cb3d968589d8 762 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Kojto 90:cb3d968589d8 763 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 90:cb3d968589d8 764 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 90:cb3d968589d8 765 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 90:cb3d968589d8 766 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 90:cb3d968589d8 767 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 90:cb3d968589d8 768 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 90:cb3d968589d8 769 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 90:cb3d968589d8 770 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 90:cb3d968589d8 771 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 90:cb3d968589d8 772 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 90:cb3d968589d8 773 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 90:cb3d968589d8 774 /**
Kojto 90:cb3d968589d8 775 * @}
Kojto 90:cb3d968589d8 776 */
Kojto 90:cb3d968589d8 777
Kojto 90:cb3d968589d8 778 /** @addtogroup Exported_constants
Kojto 90:cb3d968589d8 779 * @{
Kojto 90:cb3d968589d8 780 */
Kojto 90:cb3d968589d8 781
Kojto 90:cb3d968589d8 782 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 90:cb3d968589d8 783 * @{
Kojto 90:cb3d968589d8 784 */
Kojto 90:cb3d968589d8 785
Kojto 90:cb3d968589d8 786 /******************************************************************************/
Kojto 90:cb3d968589d8 787 /* Peripheral Registers Bits Definition */
Kojto 90:cb3d968589d8 788 /******************************************************************************/
Kojto 122:f9eeca106725 789
Kojto 90:cb3d968589d8 790 /******************************************************************************/
Kojto 90:cb3d968589d8 791 /* */
Kojto 90:cb3d968589d8 792 /* Analog to Digital Converter (ADC) */
Kojto 90:cb3d968589d8 793 /* */
Kojto 90:cb3d968589d8 794 /******************************************************************************/
Kojto 122:f9eeca106725 795
Kojto 122:f9eeca106725 796 /*
Kojto 122:f9eeca106725 797 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 798 */
Kojto 122:f9eeca106725 799 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
Kojto 122:f9eeca106725 800
Kojto 90:cb3d968589d8 801 /******************** Bits definition for ADC_ISR register ******************/
Kojto 122:f9eeca106725 802 #define ADC_ISR_ADRDY_Pos (0U)
Kojto 122:f9eeca106725 803 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 804 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
Kojto 122:f9eeca106725 805 #define ADC_ISR_EOSMP_Pos (1U)
Kojto 122:f9eeca106725 806 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 807 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
Kojto 122:f9eeca106725 808 #define ADC_ISR_EOC_Pos (2U)
Kojto 122:f9eeca106725 809 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 810 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 811 #define ADC_ISR_EOS_Pos (3U)
Kojto 122:f9eeca106725 812 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 813 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 814 #define ADC_ISR_OVR_Pos (4U)
Kojto 122:f9eeca106725 815 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 816 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
Kojto 122:f9eeca106725 817 #define ADC_ISR_AWD1_Pos (7U)
Kojto 122:f9eeca106725 818 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 819 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
Kojto 122:f9eeca106725 820
Kojto 122:f9eeca106725 821 /* Legacy defines */
Kojto 122:f9eeca106725 822 #define ADC_ISR_AWD (ADC_ISR_AWD1)
Kojto 122:f9eeca106725 823 #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
Kojto 90:cb3d968589d8 824
Kojto 90:cb3d968589d8 825 /******************** Bits definition for ADC_IER register ******************/
Kojto 122:f9eeca106725 826 #define ADC_IER_ADRDYIE_Pos (0U)
Kojto 122:f9eeca106725 827 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 828 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
Kojto 122:f9eeca106725 829 #define ADC_IER_EOSMPIE_Pos (1U)
Kojto 122:f9eeca106725 830 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 831 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
Kojto 122:f9eeca106725 832 #define ADC_IER_EOCIE_Pos (2U)
Kojto 122:f9eeca106725 833 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 834 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
Kojto 122:f9eeca106725 835 #define ADC_IER_EOSIE_Pos (3U)
Kojto 122:f9eeca106725 836 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 837 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
Kojto 122:f9eeca106725 838 #define ADC_IER_OVRIE_Pos (4U)
Kojto 122:f9eeca106725 839 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 840 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
Kojto 122:f9eeca106725 841 #define ADC_IER_AWD1IE_Pos (7U)
Kojto 122:f9eeca106725 842 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 843 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 /* Legacy defines */
Kojto 122:f9eeca106725 846 #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
Kojto 122:f9eeca106725 847 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849 /******************** Bits definition for ADC_CR register *******************/
Kojto 122:f9eeca106725 850 #define ADC_CR_ADEN_Pos (0U)
Kojto 122:f9eeca106725 851 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 852 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
Kojto 122:f9eeca106725 853 #define ADC_CR_ADDIS_Pos (1U)
Kojto 122:f9eeca106725 854 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 855 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
Kojto 122:f9eeca106725 856 #define ADC_CR_ADSTART_Pos (2U)
Kojto 122:f9eeca106725 857 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 858 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
Kojto 122:f9eeca106725 859 #define ADC_CR_ADSTP_Pos (4U)
Kojto 122:f9eeca106725 860 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 861 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
Kojto 122:f9eeca106725 862 #define ADC_CR_ADCAL_Pos (31U)
Kojto 122:f9eeca106725 863 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 864 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
Kojto 90:cb3d968589d8 865
Kojto 90:cb3d968589d8 866 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 122:f9eeca106725 867 #define ADC_CFGR1_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 868 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 869 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
Kojto 122:f9eeca106725 870 #define ADC_CFGR1_DMACFG_Pos (1U)
Kojto 122:f9eeca106725 871 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 872 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
Kojto 122:f9eeca106725 873 #define ADC_CFGR1_SCANDIR_Pos (2U)
Kojto 122:f9eeca106725 874 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 875 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
Kojto 122:f9eeca106725 876
Kojto 122:f9eeca106725 877 #define ADC_CFGR1_RES_Pos (3U)
Kojto 122:f9eeca106725 878 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 879 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
Kojto 122:f9eeca106725 880 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 881 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 882
Kojto 122:f9eeca106725 883 #define ADC_CFGR1_ALIGN_Pos (5U)
Kojto 122:f9eeca106725 884 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 885 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
Kojto 122:f9eeca106725 886
Kojto 122:f9eeca106725 887 #define ADC_CFGR1_EXTSEL_Pos (6U)
Kojto 122:f9eeca106725 888 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 889 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
Kojto 122:f9eeca106725 890 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 891 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 892 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 893
Kojto 122:f9eeca106725 894 #define ADC_CFGR1_EXTEN_Pos (10U)
Kojto 122:f9eeca106725 895 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 896 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
Kojto 122:f9eeca106725 897 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 898 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 899
Kojto 122:f9eeca106725 900 #define ADC_CFGR1_OVRMOD_Pos (12U)
Kojto 122:f9eeca106725 901 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 902 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
Kojto 122:f9eeca106725 903 #define ADC_CFGR1_CONT_Pos (13U)
Kojto 122:f9eeca106725 904 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 905 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
Kojto 122:f9eeca106725 906 #define ADC_CFGR1_WAIT_Pos (14U)
Kojto 122:f9eeca106725 907 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 908 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
Kojto 122:f9eeca106725 909 #define ADC_CFGR1_AUTOFF_Pos (15U)
Kojto 122:f9eeca106725 910 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 911 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
Kojto 122:f9eeca106725 912 #define ADC_CFGR1_DISCEN_Pos (16U)
Kojto 122:f9eeca106725 913 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 914 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
Kojto 122:f9eeca106725 915
Kojto 122:f9eeca106725 916 #define ADC_CFGR1_AWD1SGL_Pos (22U)
Kojto 122:f9eeca106725 917 #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 918 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
Kojto 122:f9eeca106725 919 #define ADC_CFGR1_AWD1EN_Pos (23U)
Kojto 122:f9eeca106725 920 #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 921 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
Kojto 122:f9eeca106725 922
Kojto 122:f9eeca106725 923 #define ADC_CFGR1_AWD1CH_Pos (26U)
Kojto 122:f9eeca106725 924 #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 925 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
Kojto 122:f9eeca106725 926 #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 927 #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 928 #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 929 #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 930 #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 931
Kojto 122:f9eeca106725 932 /* Legacy defines */
Kojto 122:f9eeca106725 933 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
Kojto 122:f9eeca106725 934 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
Kojto 122:f9eeca106725 935 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
Kojto 122:f9eeca106725 936 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
Kojto 122:f9eeca106725 937 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
Kojto 122:f9eeca106725 938 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
Kojto 122:f9eeca106725 939 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
Kojto 122:f9eeca106725 940 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
Kojto 122:f9eeca106725 941 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
Kojto 90:cb3d968589d8 942
Kojto 90:cb3d968589d8 943 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 122:f9eeca106725 944 #define ADC_CFGR2_CKMODE_Pos (30U)
Kojto 122:f9eeca106725 945 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 946 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
Kojto 122:f9eeca106725 947 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 948 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 949
Kojto 122:f9eeca106725 950 /* Legacy defines */
Kojto 122:f9eeca106725 951 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
Kojto 122:f9eeca106725 952 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Kojto 90:cb3d968589d8 953
Kojto 90:cb3d968589d8 954 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 122:f9eeca106725 955 #define ADC_SMPR_SMP_Pos (0U)
Kojto 122:f9eeca106725 956 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 957 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
Kojto 122:f9eeca106725 958 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 959 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 960 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 961
Kojto 122:f9eeca106725 962 /* Legacy defines */
Kojto 122:f9eeca106725 963 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 122:f9eeca106725 964 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
Kojto 122:f9eeca106725 965 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
Kojto 122:f9eeca106725 966 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
Kojto 90:cb3d968589d8 967
Kojto 90:cb3d968589d8 968 /******************* Bit definition for ADC_TR register ********************/
Kojto 122:f9eeca106725 969 #define ADC_TR1_LT1_Pos (0U)
Kojto 122:f9eeca106725 970 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 971 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
Kojto 122:f9eeca106725 972 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 973 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 974 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 975 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 976 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 977 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 978 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 979 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 980 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 981 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 982 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 983 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 984
Kojto 122:f9eeca106725 985 #define ADC_TR1_HT1_Pos (16U)
Kojto 122:f9eeca106725 986 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 987 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
Kojto 122:f9eeca106725 988 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 989 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 990 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 991 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 992 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 993 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 994 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 995 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 996 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 997 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 998 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 999 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1000
Kojto 122:f9eeca106725 1001 /* Legacy defines */
Kojto 122:f9eeca106725 1002 #define ADC_TR_HT (ADC_TR1_HT1)
Kojto 122:f9eeca106725 1003 #define ADC_TR_LT (ADC_TR1_LT1)
Kojto 122:f9eeca106725 1004 #define ADC_HTR_HT (ADC_TR1_HT1)
Kojto 122:f9eeca106725 1005 #define ADC_LTR_LT (ADC_TR1_LT1)
Kojto 90:cb3d968589d8 1006
Kojto 90:cb3d968589d8 1007 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 122:f9eeca106725 1008 #define ADC_CHSELR_CHSEL_Pos (0U)
Kojto 122:f9eeca106725 1009 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 1010 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1011 #define ADC_CHSELR_CHSEL18_Pos (18U)
Kojto 122:f9eeca106725 1012 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1013 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1014 #define ADC_CHSELR_CHSEL17_Pos (17U)
Kojto 122:f9eeca106725 1015 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1016 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1017 #define ADC_CHSELR_CHSEL16_Pos (16U)
Kojto 122:f9eeca106725 1018 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1019 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1020 #define ADC_CHSELR_CHSEL15_Pos (15U)
Kojto 122:f9eeca106725 1021 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1022 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1023 #define ADC_CHSELR_CHSEL14_Pos (14U)
Kojto 122:f9eeca106725 1024 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1025 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1026 #define ADC_CHSELR_CHSEL13_Pos (13U)
Kojto 122:f9eeca106725 1027 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1028 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1029 #define ADC_CHSELR_CHSEL12_Pos (12U)
Kojto 122:f9eeca106725 1030 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1031 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1032 #define ADC_CHSELR_CHSEL11_Pos (11U)
Kojto 122:f9eeca106725 1033 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1034 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1035 #define ADC_CHSELR_CHSEL10_Pos (10U)
Kojto 122:f9eeca106725 1036 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1037 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1038 #define ADC_CHSELR_CHSEL9_Pos (9U)
Kojto 122:f9eeca106725 1039 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1040 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1041 #define ADC_CHSELR_CHSEL8_Pos (8U)
Kojto 122:f9eeca106725 1042 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1043 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1044 #define ADC_CHSELR_CHSEL7_Pos (7U)
Kojto 122:f9eeca106725 1045 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1046 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1047 #define ADC_CHSELR_CHSEL6_Pos (6U)
Kojto 122:f9eeca106725 1048 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1049 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1050 #define ADC_CHSELR_CHSEL5_Pos (5U)
Kojto 122:f9eeca106725 1051 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1052 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1053 #define ADC_CHSELR_CHSEL4_Pos (4U)
Kojto 122:f9eeca106725 1054 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1055 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1056 #define ADC_CHSELR_CHSEL3_Pos (3U)
Kojto 122:f9eeca106725 1057 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1058 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1059 #define ADC_CHSELR_CHSEL2_Pos (2U)
Kojto 122:f9eeca106725 1060 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1061 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1062 #define ADC_CHSELR_CHSEL1_Pos (1U)
Kojto 122:f9eeca106725 1063 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1064 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 1065 #define ADC_CHSELR_CHSEL0_Pos (0U)
Kojto 122:f9eeca106725 1066 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1067 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 90:cb3d968589d8 1068
Kojto 90:cb3d968589d8 1069 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1070 #define ADC_DR_DATA_Pos (0U)
Kojto 122:f9eeca106725 1071 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1072 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
Kojto 122:f9eeca106725 1073 #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1074 #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1075 #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1076 #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1077 #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1078 #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1079 #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1080 #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1081 #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1082 #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1083 #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1084 #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1085 #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1086 #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1087 #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1088 #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1089
Kojto 122:f9eeca106725 1090 /************************* ADC Common registers *****************************/
Kojto 90:cb3d968589d8 1091 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1092 #define ADC_CCR_VREFEN_Pos (22U)
Kojto 122:f9eeca106725 1093 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1094 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
Kojto 122:f9eeca106725 1095 #define ADC_CCR_TSEN_Pos (23U)
Kojto 122:f9eeca106725 1096 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1097 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
Kojto 122:f9eeca106725 1098
Kojto 122:f9eeca106725 1099 #define ADC_CCR_VBATEN_Pos (24U)
Kojto 122:f9eeca106725 1100 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1101 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
Kojto 90:cb3d968589d8 1102
Kojto 90:cb3d968589d8 1103 /******************************************************************************/
Kojto 90:cb3d968589d8 1104 /* */
Kojto 90:cb3d968589d8 1105 /* Controller Area Network (CAN ) */
Kojto 90:cb3d968589d8 1106 /* */
Kojto 90:cb3d968589d8 1107 /******************************************************************************/
Kojto 90:cb3d968589d8 1108 /*!<CAN control and status registers */
Kojto 90:cb3d968589d8 1109 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 1110 #define CAN_MCR_INRQ_Pos (0U)
Kojto 122:f9eeca106725 1111 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1112 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
Kojto 122:f9eeca106725 1113 #define CAN_MCR_SLEEP_Pos (1U)
Kojto 122:f9eeca106725 1114 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1115 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 1116 #define CAN_MCR_TXFP_Pos (2U)
Kojto 122:f9eeca106725 1117 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1118 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 1119 #define CAN_MCR_RFLM_Pos (3U)
Kojto 122:f9eeca106725 1120 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1121 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 1122 #define CAN_MCR_NART_Pos (4U)
Kojto 122:f9eeca106725 1123 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1124 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 1125 #define CAN_MCR_AWUM_Pos (5U)
Kojto 122:f9eeca106725 1126 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1127 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 1128 #define CAN_MCR_ABOM_Pos (6U)
Kojto 122:f9eeca106725 1129 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1130 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 1131 #define CAN_MCR_TTCM_Pos (7U)
Kojto 122:f9eeca106725 1132 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1133 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 1134 #define CAN_MCR_RESET_Pos (15U)
Kojto 122:f9eeca106725 1135 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1136 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
Kojto 90:cb3d968589d8 1137
Kojto 90:cb3d968589d8 1138 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 1139 #define CAN_MSR_INAK_Pos (0U)
Kojto 122:f9eeca106725 1140 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1141 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 1142 #define CAN_MSR_SLAK_Pos (1U)
Kojto 122:f9eeca106725 1143 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1144 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 1145 #define CAN_MSR_ERRI_Pos (2U)
Kojto 122:f9eeca106725 1146 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1147 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
Kojto 122:f9eeca106725 1148 #define CAN_MSR_WKUI_Pos (3U)
Kojto 122:f9eeca106725 1149 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1150 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 1151 #define CAN_MSR_SLAKI_Pos (4U)
Kojto 122:f9eeca106725 1152 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1153 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 1154 #define CAN_MSR_TXM_Pos (8U)
Kojto 122:f9eeca106725 1155 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1156 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
Kojto 122:f9eeca106725 1157 #define CAN_MSR_RXM_Pos (9U)
Kojto 122:f9eeca106725 1158 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1159 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
Kojto 122:f9eeca106725 1160 #define CAN_MSR_SAMP_Pos (10U)
Kojto 122:f9eeca106725 1161 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1162 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
Kojto 122:f9eeca106725 1163 #define CAN_MSR_RX_Pos (11U)
Kojto 122:f9eeca106725 1164 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1165 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
Kojto 90:cb3d968589d8 1166
Kojto 90:cb3d968589d8 1167 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 1168 #define CAN_TSR_RQCP0_Pos (0U)
Kojto 122:f9eeca106725 1169 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1170 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 1171 #define CAN_TSR_TXOK0_Pos (1U)
Kojto 122:f9eeca106725 1172 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1173 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 1174 #define CAN_TSR_ALST0_Pos (2U)
Kojto 122:f9eeca106725 1175 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1176 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 1177 #define CAN_TSR_TERR0_Pos (3U)
Kojto 122:f9eeca106725 1178 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1179 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 1180 #define CAN_TSR_ABRQ0_Pos (7U)
Kojto 122:f9eeca106725 1181 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1182 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 1183 #define CAN_TSR_RQCP1_Pos (8U)
Kojto 122:f9eeca106725 1184 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1185 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 1186 #define CAN_TSR_TXOK1_Pos (9U)
Kojto 122:f9eeca106725 1187 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1188 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 1189 #define CAN_TSR_ALST1_Pos (10U)
Kojto 122:f9eeca106725 1190 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1191 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 1192 #define CAN_TSR_TERR1_Pos (11U)
Kojto 122:f9eeca106725 1193 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1194 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 1195 #define CAN_TSR_ABRQ1_Pos (15U)
Kojto 122:f9eeca106725 1196 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1197 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 1198 #define CAN_TSR_RQCP2_Pos (16U)
Kojto 122:f9eeca106725 1199 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1200 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 1201 #define CAN_TSR_TXOK2_Pos (17U)
Kojto 122:f9eeca106725 1202 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1203 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 1204 #define CAN_TSR_ALST2_Pos (18U)
Kojto 122:f9eeca106725 1205 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1206 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 1207 #define CAN_TSR_TERR2_Pos (19U)
Kojto 122:f9eeca106725 1208 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1209 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 1210 #define CAN_TSR_ABRQ2_Pos (23U)
Kojto 122:f9eeca106725 1211 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1212 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 1213 #define CAN_TSR_CODE_Pos (24U)
Kojto 122:f9eeca106725 1214 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 1215 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
Kojto 122:f9eeca106725 1216
Kojto 122:f9eeca106725 1217 #define CAN_TSR_TME_Pos (26U)
Kojto 122:f9eeca106725 1218 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
Kojto 122:f9eeca106725 1219 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 1220 #define CAN_TSR_TME0_Pos (26U)
Kojto 122:f9eeca106725 1221 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1222 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 1223 #define CAN_TSR_TME1_Pos (27U)
Kojto 122:f9eeca106725 1224 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1225 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 1226 #define CAN_TSR_TME2_Pos (28U)
Kojto 122:f9eeca106725 1227 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1228 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 1229
Kojto 122:f9eeca106725 1230 #define CAN_TSR_LOW_Pos (29U)
Kojto 122:f9eeca106725 1231 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
Kojto 122:f9eeca106725 1232 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 1233 #define CAN_TSR_LOW0_Pos (29U)
Kojto 122:f9eeca106725 1234 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1235 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 1236 #define CAN_TSR_LOW1_Pos (30U)
Kojto 122:f9eeca106725 1237 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1238 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 1239 #define CAN_TSR_LOW2_Pos (31U)
Kojto 122:f9eeca106725 1240 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1241 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 90:cb3d968589d8 1242
Kojto 90:cb3d968589d8 1243 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 1244 #define CAN_RF0R_FMP0_Pos (0U)
Kojto 122:f9eeca106725 1245 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1246 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 1247 #define CAN_RF0R_FULL0_Pos (3U)
Kojto 122:f9eeca106725 1248 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1249 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 1250 #define CAN_RF0R_FOVR0_Pos (4U)
Kojto 122:f9eeca106725 1251 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1252 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 1253 #define CAN_RF0R_RFOM0_Pos (5U)
Kojto 122:f9eeca106725 1254 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1255 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
Kojto 90:cb3d968589d8 1256
Kojto 90:cb3d968589d8 1257 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 1258 #define CAN_RF1R_FMP1_Pos (0U)
Kojto 122:f9eeca106725 1259 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1260 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 1261 #define CAN_RF1R_FULL1_Pos (3U)
Kojto 122:f9eeca106725 1262 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1263 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 1264 #define CAN_RF1R_FOVR1_Pos (4U)
Kojto 122:f9eeca106725 1265 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1266 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 1267 #define CAN_RF1R_RFOM1_Pos (5U)
Kojto 122:f9eeca106725 1268 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1269 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
Kojto 90:cb3d968589d8 1270
Kojto 90:cb3d968589d8 1271 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 1272 #define CAN_IER_TMEIE_Pos (0U)
Kojto 122:f9eeca106725 1273 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1274 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 1275 #define CAN_IER_FMPIE0_Pos (1U)
Kojto 122:f9eeca106725 1276 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1277 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1278 #define CAN_IER_FFIE0_Pos (2U)
Kojto 122:f9eeca106725 1279 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1280 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1281 #define CAN_IER_FOVIE0_Pos (3U)
Kojto 122:f9eeca106725 1282 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1283 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1284 #define CAN_IER_FMPIE1_Pos (4U)
Kojto 122:f9eeca106725 1285 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1286 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1287 #define CAN_IER_FFIE1_Pos (5U)
Kojto 122:f9eeca106725 1288 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1289 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1290 #define CAN_IER_FOVIE1_Pos (6U)
Kojto 122:f9eeca106725 1291 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1292 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1293 #define CAN_IER_EWGIE_Pos (8U)
Kojto 122:f9eeca106725 1294 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1295 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 1296 #define CAN_IER_EPVIE_Pos (9U)
Kojto 122:f9eeca106725 1297 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1298 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 1299 #define CAN_IER_BOFIE_Pos (10U)
Kojto 122:f9eeca106725 1300 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1301 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 1302 #define CAN_IER_LECIE_Pos (11U)
Kojto 122:f9eeca106725 1303 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1304 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 1305 #define CAN_IER_ERRIE_Pos (15U)
Kojto 122:f9eeca106725 1306 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1307 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 1308 #define CAN_IER_WKUIE_Pos (16U)
Kojto 122:f9eeca106725 1309 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1310 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 1311 #define CAN_IER_SLKIE_Pos (17U)
Kojto 122:f9eeca106725 1312 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1313 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
Kojto 90:cb3d968589d8 1314
Kojto 90:cb3d968589d8 1315 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 1316 #define CAN_ESR_EWGF_Pos (0U)
Kojto 122:f9eeca106725 1317 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1318 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
Kojto 122:f9eeca106725 1319 #define CAN_ESR_EPVF_Pos (1U)
Kojto 122:f9eeca106725 1320 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1321 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
Kojto 122:f9eeca106725 1322 #define CAN_ESR_BOFF_Pos (2U)
Kojto 122:f9eeca106725 1323 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1324 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 1325
Kojto 122:f9eeca106725 1326 #define CAN_ESR_LEC_Pos (4U)
Kojto 122:f9eeca106725 1327 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 1328 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 1329 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1330 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1331 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1332
Kojto 122:f9eeca106725 1333 #define CAN_ESR_TEC_Pos (16U)
Kojto 122:f9eeca106725 1334 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1335 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 1336 #define CAN_ESR_REC_Pos (24U)
Kojto 122:f9eeca106725 1337 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1338 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
Kojto 90:cb3d968589d8 1339
Kojto 90:cb3d968589d8 1340 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 1341 #define CAN_BTR_BRP_Pos (0U)
Kojto 122:f9eeca106725 1342 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 1343 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 1344 #define CAN_BTR_TS1_Pos (16U)
Kojto 122:f9eeca106725 1345 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 1346 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
Kojto 122:f9eeca106725 1347 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1348 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1349 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1350 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1351 #define CAN_BTR_TS2_Pos (20U)
Kojto 122:f9eeca106725 1352 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 1353 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
Kojto 122:f9eeca106725 1354 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1355 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1356 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1357 #define CAN_BTR_SJW_Pos (24U)
Kojto 122:f9eeca106725 1358 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 1359 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 1360 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1361 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1362 #define CAN_BTR_LBKM_Pos (30U)
Kojto 122:f9eeca106725 1363 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1364 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 1365 #define CAN_BTR_SILM_Pos (31U)
Kojto 122:f9eeca106725 1366 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1367 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
Kojto 90:cb3d968589d8 1368
Kojto 90:cb3d968589d8 1369 /*!<Mailbox registers */
Kojto 90:cb3d968589d8 1370 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 1371 #define CAN_TI0R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 1372 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1373 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1374 #define CAN_TI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 1375 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1376 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1377 #define CAN_TI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 1378 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1379 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 1380 #define CAN_TI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 1381 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 1382 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 1383 #define CAN_TI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 1384 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 1385 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1386
Kojto 90:cb3d968589d8 1387 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 1388 #define CAN_TDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 1389 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1390 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 1391 #define CAN_TDT0R_TGT_Pos (8U)
Kojto 122:f9eeca106725 1392 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1393 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1394 #define CAN_TDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 1395 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 1396 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1397
Kojto 90:cb3d968589d8 1398 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 1399 #define CAN_TDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 1400 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1401 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 1402 #define CAN_TDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 1403 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1404 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 1405 #define CAN_TDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 1406 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1407 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 1408 #define CAN_TDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 1409 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1410 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1411
Kojto 90:cb3d968589d8 1412 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 1413 #define CAN_TDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 1414 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1415 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 1416 #define CAN_TDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 1417 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1418 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 1419 #define CAN_TDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 1420 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1421 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 1422 #define CAN_TDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 1423 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1424 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1425
Kojto 90:cb3d968589d8 1426 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 1427 #define CAN_TI1R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 1428 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1429 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1430 #define CAN_TI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 1431 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1432 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1433 #define CAN_TI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 1434 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1435 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 1436 #define CAN_TI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 1437 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 1438 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 1439 #define CAN_TI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 1440 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 1441 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1442
Kojto 90:cb3d968589d8 1443 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 1444 #define CAN_TDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 1445 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1446 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 1447 #define CAN_TDT1R_TGT_Pos (8U)
Kojto 122:f9eeca106725 1448 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1449 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1450 #define CAN_TDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 1451 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 1452 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1453
Kojto 90:cb3d968589d8 1454 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 1455 #define CAN_TDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 1456 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1457 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 1458 #define CAN_TDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 1459 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1460 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 1461 #define CAN_TDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 1462 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1463 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 1464 #define CAN_TDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 1465 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1466 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1467
Kojto 90:cb3d968589d8 1468 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 1469 #define CAN_TDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 1470 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1471 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 1472 #define CAN_TDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 1473 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1474 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 1475 #define CAN_TDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 1476 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1477 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 1478 #define CAN_TDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 1479 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1480 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1481
Kojto 90:cb3d968589d8 1482 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 1483 #define CAN_TI2R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 1484 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1485 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1486 #define CAN_TI2R_RTR_Pos (1U)
Kojto 122:f9eeca106725 1487 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1488 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1489 #define CAN_TI2R_IDE_Pos (2U)
Kojto 122:f9eeca106725 1490 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1491 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 1492 #define CAN_TI2R_EXID_Pos (3U)
Kojto 122:f9eeca106725 1493 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 1494 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 1495 #define CAN_TI2R_STID_Pos (21U)
Kojto 122:f9eeca106725 1496 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 1497 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1498
Kojto 90:cb3d968589d8 1499 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 1500 #define CAN_TDT2R_DLC_Pos (0U)
Kojto 122:f9eeca106725 1501 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1502 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 1503 #define CAN_TDT2R_TGT_Pos (8U)
Kojto 122:f9eeca106725 1504 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1505 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1506 #define CAN_TDT2R_TIME_Pos (16U)
Kojto 122:f9eeca106725 1507 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 1508 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1509
Kojto 90:cb3d968589d8 1510 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 1511 #define CAN_TDL2R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 1512 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1513 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 1514 #define CAN_TDL2R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 1515 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1516 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 1517 #define CAN_TDL2R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 1518 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1519 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 1520 #define CAN_TDL2R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 1521 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1522 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1523
Kojto 90:cb3d968589d8 1524 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 1525 #define CAN_TDH2R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 1526 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1527 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 1528 #define CAN_TDH2R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 1529 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1530 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 1531 #define CAN_TDH2R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 1532 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1533 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 1534 #define CAN_TDH2R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 1535 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1536 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1537
Kojto 90:cb3d968589d8 1538 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 1539 #define CAN_RI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 1540 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1541 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1542 #define CAN_RI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 1543 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1544 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 1545 #define CAN_RI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 1546 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 1547 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 1548 #define CAN_RI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 1549 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 1550 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1551
Kojto 90:cb3d968589d8 1552 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 1553 #define CAN_RDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 1554 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1555 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 1556 #define CAN_RDT0R_FMI_Pos (8U)
Kojto 122:f9eeca106725 1557 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1558 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 1559 #define CAN_RDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 1560 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 1561 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1562
Kojto 90:cb3d968589d8 1563 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 1564 #define CAN_RDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 1565 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1566 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 1567 #define CAN_RDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 1568 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1569 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 1570 #define CAN_RDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 1571 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1572 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 1573 #define CAN_RDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 1574 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1575 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1576
Kojto 90:cb3d968589d8 1577 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 1578 #define CAN_RDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 1579 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1580 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 1581 #define CAN_RDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 1582 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1583 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 1584 #define CAN_RDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 1585 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1586 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 1587 #define CAN_RDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 1588 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1589 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1590
Kojto 90:cb3d968589d8 1591 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 1592 #define CAN_RI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 1593 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1594 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1595 #define CAN_RI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 1596 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1597 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 1598 #define CAN_RI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 1599 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 1600 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 1601 #define CAN_RI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 1602 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 1603 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1604
Kojto 90:cb3d968589d8 1605 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 1606 #define CAN_RDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 1607 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1608 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 1609 #define CAN_RDT1R_FMI_Pos (8U)
Kojto 122:f9eeca106725 1610 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1611 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 1612 #define CAN_RDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 1613 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 1614 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1615
Kojto 90:cb3d968589d8 1616 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 1617 #define CAN_RDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 1618 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1619 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 1620 #define CAN_RDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 1621 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1622 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 1623 #define CAN_RDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 1624 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1625 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 1626 #define CAN_RDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 1627 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1628 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1629
Kojto 90:cb3d968589d8 1630 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 1631 #define CAN_RDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 1632 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1633 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 1634 #define CAN_RDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 1635 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1636 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 1637 #define CAN_RDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 1638 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1639 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 1640 #define CAN_RDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 1641 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1642 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1643
Kojto 90:cb3d968589d8 1644 /*!<CAN filter registers */
Kojto 90:cb3d968589d8 1645 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 1646 #define CAN_FMR_FINIT_Pos (0U)
Kojto 122:f9eeca106725 1647 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1648 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
Kojto 122:f9eeca106725 1649 #define CAN_FMR_CAN2SB_Pos (8U)
Kojto 122:f9eeca106725 1650 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
Kojto 122:f9eeca106725 1651 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
Kojto 90:cb3d968589d8 1652
Kojto 90:cb3d968589d8 1653 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 1654 #define CAN_FM1R_FBM_Pos (0U)
Kojto 122:f9eeca106725 1655 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
Kojto 122:f9eeca106725 1656 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
Kojto 122:f9eeca106725 1657 #define CAN_FM1R_FBM0_Pos (0U)
Kojto 122:f9eeca106725 1658 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1659 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 1660 #define CAN_FM1R_FBM1_Pos (1U)
Kojto 122:f9eeca106725 1661 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1662 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 1663 #define CAN_FM1R_FBM2_Pos (2U)
Kojto 122:f9eeca106725 1664 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1665 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 1666 #define CAN_FM1R_FBM3_Pos (3U)
Kojto 122:f9eeca106725 1667 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1668 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 1669 #define CAN_FM1R_FBM4_Pos (4U)
Kojto 122:f9eeca106725 1670 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1671 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 1672 #define CAN_FM1R_FBM5_Pos (5U)
Kojto 122:f9eeca106725 1673 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1674 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 1675 #define CAN_FM1R_FBM6_Pos (6U)
Kojto 122:f9eeca106725 1676 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1677 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 1678 #define CAN_FM1R_FBM7_Pos (7U)
Kojto 122:f9eeca106725 1679 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1680 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 1681 #define CAN_FM1R_FBM8_Pos (8U)
Kojto 122:f9eeca106725 1682 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1683 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 1684 #define CAN_FM1R_FBM9_Pos (9U)
Kojto 122:f9eeca106725 1685 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1686 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 1687 #define CAN_FM1R_FBM10_Pos (10U)
Kojto 122:f9eeca106725 1688 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1689 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 1690 #define CAN_FM1R_FBM11_Pos (11U)
Kojto 122:f9eeca106725 1691 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1692 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 1693 #define CAN_FM1R_FBM12_Pos (12U)
Kojto 122:f9eeca106725 1694 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1695 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 1696 #define CAN_FM1R_FBM13_Pos (13U)
Kojto 122:f9eeca106725 1697 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1698 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
Kojto 122:f9eeca106725 1699 #define CAN_FM1R_FBM14_Pos (14U)
Kojto 122:f9eeca106725 1700 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1701 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
Kojto 122:f9eeca106725 1702 #define CAN_FM1R_FBM15_Pos (15U)
Kojto 122:f9eeca106725 1703 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1704 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
Kojto 122:f9eeca106725 1705 #define CAN_FM1R_FBM16_Pos (16U)
Kojto 122:f9eeca106725 1706 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1707 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
Kojto 122:f9eeca106725 1708 #define CAN_FM1R_FBM17_Pos (17U)
Kojto 122:f9eeca106725 1709 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1710 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
Kojto 122:f9eeca106725 1711 #define CAN_FM1R_FBM18_Pos (18U)
Kojto 122:f9eeca106725 1712 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1713 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
Kojto 122:f9eeca106725 1714 #define CAN_FM1R_FBM19_Pos (19U)
Kojto 122:f9eeca106725 1715 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1716 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
Kojto 122:f9eeca106725 1717 #define CAN_FM1R_FBM20_Pos (20U)
Kojto 122:f9eeca106725 1718 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1719 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
Kojto 122:f9eeca106725 1720 #define CAN_FM1R_FBM21_Pos (21U)
Kojto 122:f9eeca106725 1721 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1722 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
Kojto 122:f9eeca106725 1723 #define CAN_FM1R_FBM22_Pos (22U)
Kojto 122:f9eeca106725 1724 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1725 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
Kojto 122:f9eeca106725 1726 #define CAN_FM1R_FBM23_Pos (23U)
Kojto 122:f9eeca106725 1727 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1728 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
Kojto 122:f9eeca106725 1729 #define CAN_FM1R_FBM24_Pos (24U)
Kojto 122:f9eeca106725 1730 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1731 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
Kojto 122:f9eeca106725 1732 #define CAN_FM1R_FBM25_Pos (25U)
Kojto 122:f9eeca106725 1733 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1734 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
Kojto 122:f9eeca106725 1735 #define CAN_FM1R_FBM26_Pos (26U)
Kojto 122:f9eeca106725 1736 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1737 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
Kojto 122:f9eeca106725 1738 #define CAN_FM1R_FBM27_Pos (27U)
Kojto 122:f9eeca106725 1739 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1740 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
Kojto 90:cb3d968589d8 1741
Kojto 90:cb3d968589d8 1742 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 1743 #define CAN_FS1R_FSC_Pos (0U)
Kojto 122:f9eeca106725 1744 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
Kojto 122:f9eeca106725 1745 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 1746 #define CAN_FS1R_FSC0_Pos (0U)
Kojto 122:f9eeca106725 1747 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1748 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 1749 #define CAN_FS1R_FSC1_Pos (1U)
Kojto 122:f9eeca106725 1750 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1751 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 1752 #define CAN_FS1R_FSC2_Pos (2U)
Kojto 122:f9eeca106725 1753 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1754 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 1755 #define CAN_FS1R_FSC3_Pos (3U)
Kojto 122:f9eeca106725 1756 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1757 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 1758 #define CAN_FS1R_FSC4_Pos (4U)
Kojto 122:f9eeca106725 1759 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1760 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 1761 #define CAN_FS1R_FSC5_Pos (5U)
Kojto 122:f9eeca106725 1762 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1763 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 1764 #define CAN_FS1R_FSC6_Pos (6U)
Kojto 122:f9eeca106725 1765 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1766 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 1767 #define CAN_FS1R_FSC7_Pos (7U)
Kojto 122:f9eeca106725 1768 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1769 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 1770 #define CAN_FS1R_FSC8_Pos (8U)
Kojto 122:f9eeca106725 1771 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1772 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 1773 #define CAN_FS1R_FSC9_Pos (9U)
Kojto 122:f9eeca106725 1774 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1775 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 1776 #define CAN_FS1R_FSC10_Pos (10U)
Kojto 122:f9eeca106725 1777 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1778 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 1779 #define CAN_FS1R_FSC11_Pos (11U)
Kojto 122:f9eeca106725 1780 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1781 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 1782 #define CAN_FS1R_FSC12_Pos (12U)
Kojto 122:f9eeca106725 1783 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1784 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 1785 #define CAN_FS1R_FSC13_Pos (13U)
Kojto 122:f9eeca106725 1786 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1787 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
Kojto 122:f9eeca106725 1788 #define CAN_FS1R_FSC14_Pos (14U)
Kojto 122:f9eeca106725 1789 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1790 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
Kojto 122:f9eeca106725 1791 #define CAN_FS1R_FSC15_Pos (15U)
Kojto 122:f9eeca106725 1792 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1793 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
Kojto 122:f9eeca106725 1794 #define CAN_FS1R_FSC16_Pos (16U)
Kojto 122:f9eeca106725 1795 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1796 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
Kojto 122:f9eeca106725 1797 #define CAN_FS1R_FSC17_Pos (17U)
Kojto 122:f9eeca106725 1798 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1799 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
Kojto 122:f9eeca106725 1800 #define CAN_FS1R_FSC18_Pos (18U)
Kojto 122:f9eeca106725 1801 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1802 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
Kojto 122:f9eeca106725 1803 #define CAN_FS1R_FSC19_Pos (19U)
Kojto 122:f9eeca106725 1804 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1805 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
Kojto 122:f9eeca106725 1806 #define CAN_FS1R_FSC20_Pos (20U)
Kojto 122:f9eeca106725 1807 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1808 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
Kojto 122:f9eeca106725 1809 #define CAN_FS1R_FSC21_Pos (21U)
Kojto 122:f9eeca106725 1810 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1811 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
Kojto 122:f9eeca106725 1812 #define CAN_FS1R_FSC22_Pos (22U)
Kojto 122:f9eeca106725 1813 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1814 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
Kojto 122:f9eeca106725 1815 #define CAN_FS1R_FSC23_Pos (23U)
Kojto 122:f9eeca106725 1816 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1817 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
Kojto 122:f9eeca106725 1818 #define CAN_FS1R_FSC24_Pos (24U)
Kojto 122:f9eeca106725 1819 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1820 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
Kojto 122:f9eeca106725 1821 #define CAN_FS1R_FSC25_Pos (25U)
Kojto 122:f9eeca106725 1822 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1823 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
Kojto 122:f9eeca106725 1824 #define CAN_FS1R_FSC26_Pos (26U)
Kojto 122:f9eeca106725 1825 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1826 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
Kojto 122:f9eeca106725 1827 #define CAN_FS1R_FSC27_Pos (27U)
Kojto 122:f9eeca106725 1828 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1829 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
Kojto 90:cb3d968589d8 1830
Kojto 90:cb3d968589d8 1831 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 1832 #define CAN_FFA1R_FFA_Pos (0U)
Kojto 122:f9eeca106725 1833 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
Kojto 122:f9eeca106725 1834 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 1835 #define CAN_FFA1R_FFA0_Pos (0U)
Kojto 122:f9eeca106725 1836 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1837 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
Kojto 122:f9eeca106725 1838 #define CAN_FFA1R_FFA1_Pos (1U)
Kojto 122:f9eeca106725 1839 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1840 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
Kojto 122:f9eeca106725 1841 #define CAN_FFA1R_FFA2_Pos (2U)
Kojto 122:f9eeca106725 1842 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1843 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
Kojto 122:f9eeca106725 1844 #define CAN_FFA1R_FFA3_Pos (3U)
Kojto 122:f9eeca106725 1845 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1846 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
Kojto 122:f9eeca106725 1847 #define CAN_FFA1R_FFA4_Pos (4U)
Kojto 122:f9eeca106725 1848 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1849 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
Kojto 122:f9eeca106725 1850 #define CAN_FFA1R_FFA5_Pos (5U)
Kojto 122:f9eeca106725 1851 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1852 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
Kojto 122:f9eeca106725 1853 #define CAN_FFA1R_FFA6_Pos (6U)
Kojto 122:f9eeca106725 1854 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1855 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
Kojto 122:f9eeca106725 1856 #define CAN_FFA1R_FFA7_Pos (7U)
Kojto 122:f9eeca106725 1857 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1858 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
Kojto 122:f9eeca106725 1859 #define CAN_FFA1R_FFA8_Pos (8U)
Kojto 122:f9eeca106725 1860 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1861 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
Kojto 122:f9eeca106725 1862 #define CAN_FFA1R_FFA9_Pos (9U)
Kojto 122:f9eeca106725 1863 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1864 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
Kojto 122:f9eeca106725 1865 #define CAN_FFA1R_FFA10_Pos (10U)
Kojto 122:f9eeca106725 1866 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1867 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
Kojto 122:f9eeca106725 1868 #define CAN_FFA1R_FFA11_Pos (11U)
Kojto 122:f9eeca106725 1869 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1870 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
Kojto 122:f9eeca106725 1871 #define CAN_FFA1R_FFA12_Pos (12U)
Kojto 122:f9eeca106725 1872 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1873 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
Kojto 122:f9eeca106725 1874 #define CAN_FFA1R_FFA13_Pos (13U)
Kojto 122:f9eeca106725 1875 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1876 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
Kojto 122:f9eeca106725 1877 #define CAN_FFA1R_FFA14_Pos (14U)
Kojto 122:f9eeca106725 1878 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1879 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
Kojto 122:f9eeca106725 1880 #define CAN_FFA1R_FFA15_Pos (15U)
Kojto 122:f9eeca106725 1881 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1882 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
Kojto 122:f9eeca106725 1883 #define CAN_FFA1R_FFA16_Pos (16U)
Kojto 122:f9eeca106725 1884 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1885 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
Kojto 122:f9eeca106725 1886 #define CAN_FFA1R_FFA17_Pos (17U)
Kojto 122:f9eeca106725 1887 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1888 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
Kojto 122:f9eeca106725 1889 #define CAN_FFA1R_FFA18_Pos (18U)
Kojto 122:f9eeca106725 1890 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1891 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
Kojto 122:f9eeca106725 1892 #define CAN_FFA1R_FFA19_Pos (19U)
Kojto 122:f9eeca106725 1893 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1894 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
Kojto 122:f9eeca106725 1895 #define CAN_FFA1R_FFA20_Pos (20U)
Kojto 122:f9eeca106725 1896 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1897 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
Kojto 122:f9eeca106725 1898 #define CAN_FFA1R_FFA21_Pos (21U)
Kojto 122:f9eeca106725 1899 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1900 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
Kojto 122:f9eeca106725 1901 #define CAN_FFA1R_FFA22_Pos (22U)
Kojto 122:f9eeca106725 1902 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1903 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
Kojto 122:f9eeca106725 1904 #define CAN_FFA1R_FFA23_Pos (23U)
Kojto 122:f9eeca106725 1905 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1906 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
Kojto 122:f9eeca106725 1907 #define CAN_FFA1R_FFA24_Pos (24U)
Kojto 122:f9eeca106725 1908 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1909 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
Kojto 122:f9eeca106725 1910 #define CAN_FFA1R_FFA25_Pos (25U)
Kojto 122:f9eeca106725 1911 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1912 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
Kojto 122:f9eeca106725 1913 #define CAN_FFA1R_FFA26_Pos (26U)
Kojto 122:f9eeca106725 1914 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1915 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
Kojto 122:f9eeca106725 1916 #define CAN_FFA1R_FFA27_Pos (27U)
Kojto 122:f9eeca106725 1917 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1918 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
Kojto 90:cb3d968589d8 1919
Kojto 90:cb3d968589d8 1920 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 1921 #define CAN_FA1R_FACT_Pos (0U)
Kojto 122:f9eeca106725 1922 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
Kojto 122:f9eeca106725 1923 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
Kojto 122:f9eeca106725 1924 #define CAN_FA1R_FACT0_Pos (0U)
Kojto 122:f9eeca106725 1925 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1926 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
Kojto 122:f9eeca106725 1927 #define CAN_FA1R_FACT1_Pos (1U)
Kojto 122:f9eeca106725 1928 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1929 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
Kojto 122:f9eeca106725 1930 #define CAN_FA1R_FACT2_Pos (2U)
Kojto 122:f9eeca106725 1931 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1932 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
Kojto 122:f9eeca106725 1933 #define CAN_FA1R_FACT3_Pos (3U)
Kojto 122:f9eeca106725 1934 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1935 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
Kojto 122:f9eeca106725 1936 #define CAN_FA1R_FACT4_Pos (4U)
Kojto 122:f9eeca106725 1937 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1938 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
Kojto 122:f9eeca106725 1939 #define CAN_FA1R_FACT5_Pos (5U)
Kojto 122:f9eeca106725 1940 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1941 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
Kojto 122:f9eeca106725 1942 #define CAN_FA1R_FACT6_Pos (6U)
Kojto 122:f9eeca106725 1943 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1944 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
Kojto 122:f9eeca106725 1945 #define CAN_FA1R_FACT7_Pos (7U)
Kojto 122:f9eeca106725 1946 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1947 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
Kojto 122:f9eeca106725 1948 #define CAN_FA1R_FACT8_Pos (8U)
Kojto 122:f9eeca106725 1949 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1950 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
Kojto 122:f9eeca106725 1951 #define CAN_FA1R_FACT9_Pos (9U)
Kojto 122:f9eeca106725 1952 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1953 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
Kojto 122:f9eeca106725 1954 #define CAN_FA1R_FACT10_Pos (10U)
Kojto 122:f9eeca106725 1955 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1956 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
Kojto 122:f9eeca106725 1957 #define CAN_FA1R_FACT11_Pos (11U)
Kojto 122:f9eeca106725 1958 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1959 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
Kojto 122:f9eeca106725 1960 #define CAN_FA1R_FACT12_Pos (12U)
Kojto 122:f9eeca106725 1961 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1962 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
Kojto 122:f9eeca106725 1963 #define CAN_FA1R_FACT13_Pos (13U)
Kojto 122:f9eeca106725 1964 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1965 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
Kojto 122:f9eeca106725 1966 #define CAN_FA1R_FACT14_Pos (14U)
Kojto 122:f9eeca106725 1967 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1968 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
Kojto 122:f9eeca106725 1969 #define CAN_FA1R_FACT15_Pos (15U)
Kojto 122:f9eeca106725 1970 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1971 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
Kojto 122:f9eeca106725 1972 #define CAN_FA1R_FACT16_Pos (16U)
Kojto 122:f9eeca106725 1973 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1974 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
Kojto 122:f9eeca106725 1975 #define CAN_FA1R_FACT17_Pos (17U)
Kojto 122:f9eeca106725 1976 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1977 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
Kojto 122:f9eeca106725 1978 #define CAN_FA1R_FACT18_Pos (18U)
Kojto 122:f9eeca106725 1979 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1980 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
Kojto 122:f9eeca106725 1981 #define CAN_FA1R_FACT19_Pos (19U)
Kojto 122:f9eeca106725 1982 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1983 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
Kojto 122:f9eeca106725 1984 #define CAN_FA1R_FACT20_Pos (20U)
Kojto 122:f9eeca106725 1985 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1986 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
Kojto 122:f9eeca106725 1987 #define CAN_FA1R_FACT21_Pos (21U)
Kojto 122:f9eeca106725 1988 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1989 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
Kojto 122:f9eeca106725 1990 #define CAN_FA1R_FACT22_Pos (22U)
Kojto 122:f9eeca106725 1991 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1992 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
Kojto 122:f9eeca106725 1993 #define CAN_FA1R_FACT23_Pos (23U)
Kojto 122:f9eeca106725 1994 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1995 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
Kojto 122:f9eeca106725 1996 #define CAN_FA1R_FACT24_Pos (24U)
Kojto 122:f9eeca106725 1997 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1998 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
Kojto 122:f9eeca106725 1999 #define CAN_FA1R_FACT25_Pos (25U)
Kojto 122:f9eeca106725 2000 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2001 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
Kojto 122:f9eeca106725 2002 #define CAN_FA1R_FACT26_Pos (26U)
Kojto 122:f9eeca106725 2003 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2004 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
Kojto 122:f9eeca106725 2005 #define CAN_FA1R_FACT27_Pos (27U)
Kojto 122:f9eeca106725 2006 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2007 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
Kojto 90:cb3d968589d8 2008
Kojto 90:cb3d968589d8 2009 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 2010 #define CAN_F0R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2011 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2012 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2013 #define CAN_F0R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2014 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2015 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2016 #define CAN_F0R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2017 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2018 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2019 #define CAN_F0R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2020 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2021 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2022 #define CAN_F0R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2023 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2024 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2025 #define CAN_F0R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2026 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2027 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2028 #define CAN_F0R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2029 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2030 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2031 #define CAN_F0R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2032 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2033 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2034 #define CAN_F0R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2035 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2036 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2037 #define CAN_F0R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2038 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2039 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2040 #define CAN_F0R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2041 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2042 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2043 #define CAN_F0R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2044 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2045 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2046 #define CAN_F0R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2047 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2048 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2049 #define CAN_F0R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2050 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2051 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2052 #define CAN_F0R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2053 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2054 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2055 #define CAN_F0R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2056 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2057 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2058 #define CAN_F0R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2059 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2060 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2061 #define CAN_F0R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2062 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2063 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2064 #define CAN_F0R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2065 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2066 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2067 #define CAN_F0R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2068 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2069 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2070 #define CAN_F0R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2071 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2072 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2073 #define CAN_F0R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2074 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2075 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2076 #define CAN_F0R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2077 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2078 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2079 #define CAN_F0R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2080 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2081 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2082 #define CAN_F0R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2083 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2084 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2085 #define CAN_F0R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2086 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2087 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2088 #define CAN_F0R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2089 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2090 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2091 #define CAN_F0R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2092 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2093 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2094 #define CAN_F0R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2095 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2096 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2097 #define CAN_F0R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2098 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2099 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2100 #define CAN_F0R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2101 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2102 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2103 #define CAN_F0R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2104 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2105 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2106
Kojto 90:cb3d968589d8 2107 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 2108 #define CAN_F1R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2109 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2110 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2111 #define CAN_F1R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2112 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2113 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2114 #define CAN_F1R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2115 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2116 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2117 #define CAN_F1R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2118 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2119 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2120 #define CAN_F1R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2121 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2122 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2123 #define CAN_F1R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2124 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2125 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2126 #define CAN_F1R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2127 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2128 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2129 #define CAN_F1R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2130 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2131 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2132 #define CAN_F1R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2133 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2134 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2135 #define CAN_F1R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2136 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2137 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2138 #define CAN_F1R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2139 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2140 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2141 #define CAN_F1R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2142 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2143 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2144 #define CAN_F1R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2145 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2146 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2147 #define CAN_F1R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2148 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2149 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2150 #define CAN_F1R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2151 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2152 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2153 #define CAN_F1R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2154 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2155 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2156 #define CAN_F1R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2157 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2158 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2159 #define CAN_F1R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2160 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2161 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2162 #define CAN_F1R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2163 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2164 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2165 #define CAN_F1R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2166 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2167 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2168 #define CAN_F1R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2169 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2170 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2171 #define CAN_F1R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2172 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2173 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2174 #define CAN_F1R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2175 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2176 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2177 #define CAN_F1R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2178 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2179 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2180 #define CAN_F1R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2181 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2182 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2183 #define CAN_F1R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2184 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2185 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2186 #define CAN_F1R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2187 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2188 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2189 #define CAN_F1R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2190 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2191 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2192 #define CAN_F1R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2193 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2194 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2195 #define CAN_F1R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2196 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2197 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2198 #define CAN_F1R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2199 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2200 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2201 #define CAN_F1R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2202 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2203 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2204
Kojto 90:cb3d968589d8 2205 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 2206 #define CAN_F2R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2207 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2208 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2209 #define CAN_F2R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2210 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2211 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2212 #define CAN_F2R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2213 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2214 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2215 #define CAN_F2R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2216 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2217 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2218 #define CAN_F2R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2219 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2220 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2221 #define CAN_F2R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2222 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2223 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2224 #define CAN_F2R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2225 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2226 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2227 #define CAN_F2R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2228 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2229 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2230 #define CAN_F2R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2231 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2232 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2233 #define CAN_F2R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2234 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2235 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2236 #define CAN_F2R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2237 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2238 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2239 #define CAN_F2R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2240 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2241 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2242 #define CAN_F2R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2243 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2244 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2245 #define CAN_F2R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2246 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2247 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2248 #define CAN_F2R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2249 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2250 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2251 #define CAN_F2R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2252 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2253 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2254 #define CAN_F2R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2255 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2256 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2257 #define CAN_F2R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2258 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2259 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2260 #define CAN_F2R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2261 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2262 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2263 #define CAN_F2R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2264 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2265 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2266 #define CAN_F2R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2267 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2268 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2269 #define CAN_F2R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2270 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2271 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2272 #define CAN_F2R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2273 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2274 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2275 #define CAN_F2R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2276 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2277 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2278 #define CAN_F2R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2279 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2280 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2281 #define CAN_F2R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2282 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2283 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2284 #define CAN_F2R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2285 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2286 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2287 #define CAN_F2R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2288 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2289 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2290 #define CAN_F2R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2291 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2292 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2293 #define CAN_F2R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2294 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2295 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2296 #define CAN_F2R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2297 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2298 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2299 #define CAN_F2R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2300 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2301 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2302
Kojto 90:cb3d968589d8 2303 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 2304 #define CAN_F3R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2305 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2306 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2307 #define CAN_F3R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2308 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2309 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2310 #define CAN_F3R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2311 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2312 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2313 #define CAN_F3R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2314 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2315 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2316 #define CAN_F3R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2317 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2318 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2319 #define CAN_F3R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2320 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2321 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2322 #define CAN_F3R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2323 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2324 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2325 #define CAN_F3R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2326 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2327 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2328 #define CAN_F3R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2329 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2330 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2331 #define CAN_F3R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2332 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2333 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2334 #define CAN_F3R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2335 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2336 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2337 #define CAN_F3R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2338 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2339 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2340 #define CAN_F3R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2341 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2342 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2343 #define CAN_F3R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2344 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2345 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2346 #define CAN_F3R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2347 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2348 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2349 #define CAN_F3R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2350 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2351 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2352 #define CAN_F3R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2353 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2354 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2355 #define CAN_F3R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2356 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2357 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2358 #define CAN_F3R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2359 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2360 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2361 #define CAN_F3R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2362 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2363 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2364 #define CAN_F3R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2365 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2366 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2367 #define CAN_F3R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2368 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2369 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2370 #define CAN_F3R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2371 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2372 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2373 #define CAN_F3R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2374 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2375 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2376 #define CAN_F3R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2377 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2378 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2379 #define CAN_F3R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2380 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2381 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2382 #define CAN_F3R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2383 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2384 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2385 #define CAN_F3R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2386 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2387 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2388 #define CAN_F3R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2389 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2390 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2391 #define CAN_F3R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2392 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2393 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2394 #define CAN_F3R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2395 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2396 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2397 #define CAN_F3R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2398 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2399 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2400
Kojto 90:cb3d968589d8 2401 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 2402 #define CAN_F4R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2403 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2404 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2405 #define CAN_F4R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2406 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2407 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2408 #define CAN_F4R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2409 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2410 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2411 #define CAN_F4R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2412 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2413 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2414 #define CAN_F4R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2415 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2416 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2417 #define CAN_F4R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2418 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2419 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2420 #define CAN_F4R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2421 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2422 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2423 #define CAN_F4R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2424 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2425 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2426 #define CAN_F4R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2427 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2428 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2429 #define CAN_F4R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2430 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2431 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2432 #define CAN_F4R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2433 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2434 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2435 #define CAN_F4R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2436 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2437 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2438 #define CAN_F4R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2439 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2440 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2441 #define CAN_F4R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2442 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2443 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2444 #define CAN_F4R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2445 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2446 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2447 #define CAN_F4R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2448 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2449 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2450 #define CAN_F4R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2451 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2452 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2453 #define CAN_F4R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2454 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2455 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2456 #define CAN_F4R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2457 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2458 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2459 #define CAN_F4R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2460 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2461 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2462 #define CAN_F4R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2463 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2464 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2465 #define CAN_F4R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2466 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2467 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2468 #define CAN_F4R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2469 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2470 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2471 #define CAN_F4R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2472 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2473 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2474 #define CAN_F4R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2475 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2476 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2477 #define CAN_F4R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2478 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2479 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2480 #define CAN_F4R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2481 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2482 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2483 #define CAN_F4R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2484 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2485 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2486 #define CAN_F4R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2487 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2488 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2489 #define CAN_F4R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2490 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2491 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2492 #define CAN_F4R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2493 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2494 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2495 #define CAN_F4R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2496 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2497 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2498
Kojto 90:cb3d968589d8 2499 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 2500 #define CAN_F5R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2501 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2502 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2503 #define CAN_F5R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2504 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2505 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2506 #define CAN_F5R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2507 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2508 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2509 #define CAN_F5R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2510 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2511 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2512 #define CAN_F5R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2513 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2514 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2515 #define CAN_F5R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2516 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2517 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2518 #define CAN_F5R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2519 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2520 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2521 #define CAN_F5R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2522 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2523 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2524 #define CAN_F5R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2525 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2526 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2527 #define CAN_F5R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2528 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2529 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2530 #define CAN_F5R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2531 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2532 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2533 #define CAN_F5R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2534 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2535 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2536 #define CAN_F5R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2537 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2538 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2539 #define CAN_F5R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2540 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2541 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2542 #define CAN_F5R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2543 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2544 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2545 #define CAN_F5R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2546 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2547 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2548 #define CAN_F5R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2549 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2550 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2551 #define CAN_F5R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2552 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2553 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2554 #define CAN_F5R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2555 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2556 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2557 #define CAN_F5R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2558 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2559 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2560 #define CAN_F5R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2561 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2562 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2563 #define CAN_F5R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2564 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2565 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2566 #define CAN_F5R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2567 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2568 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2569 #define CAN_F5R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2570 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2571 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2572 #define CAN_F5R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2573 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2574 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2575 #define CAN_F5R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2576 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2577 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2578 #define CAN_F5R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2579 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2580 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2581 #define CAN_F5R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2582 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2583 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2584 #define CAN_F5R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2585 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2586 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2587 #define CAN_F5R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2588 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2589 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2590 #define CAN_F5R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2591 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2592 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2593 #define CAN_F5R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2594 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2595 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2596
Kojto 90:cb3d968589d8 2597 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 2598 #define CAN_F6R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2599 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2600 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2601 #define CAN_F6R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2602 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2603 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2604 #define CAN_F6R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2605 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2606 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2607 #define CAN_F6R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2608 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2609 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2610 #define CAN_F6R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2611 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2612 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2613 #define CAN_F6R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2614 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2615 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2616 #define CAN_F6R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2617 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2618 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2619 #define CAN_F6R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2620 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2621 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2622 #define CAN_F6R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2623 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2624 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2625 #define CAN_F6R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2626 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2627 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2628 #define CAN_F6R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2629 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2630 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2631 #define CAN_F6R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2632 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2633 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2634 #define CAN_F6R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2635 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2636 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2637 #define CAN_F6R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2638 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2639 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2640 #define CAN_F6R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2641 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2642 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2643 #define CAN_F6R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2644 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2645 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2646 #define CAN_F6R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2647 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2648 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2649 #define CAN_F6R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2650 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2651 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2652 #define CAN_F6R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2653 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2654 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2655 #define CAN_F6R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2656 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2657 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2658 #define CAN_F6R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2659 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2660 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2661 #define CAN_F6R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2662 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2663 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2664 #define CAN_F6R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2665 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2666 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2667 #define CAN_F6R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2668 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2669 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2670 #define CAN_F6R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2671 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2672 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2673 #define CAN_F6R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2674 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2675 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2676 #define CAN_F6R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2677 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2678 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2679 #define CAN_F6R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2680 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2681 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2682 #define CAN_F6R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2683 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2684 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2685 #define CAN_F6R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2686 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2687 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2688 #define CAN_F6R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2689 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2690 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2691 #define CAN_F6R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2692 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2693 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2694
Kojto 90:cb3d968589d8 2695 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 2696 #define CAN_F7R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2697 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2698 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2699 #define CAN_F7R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2700 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2701 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2702 #define CAN_F7R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2703 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2704 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2705 #define CAN_F7R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2706 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2707 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2708 #define CAN_F7R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2709 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2710 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2711 #define CAN_F7R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2712 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2713 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2714 #define CAN_F7R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2715 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2716 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2717 #define CAN_F7R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2718 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2719 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2720 #define CAN_F7R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2721 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2722 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2723 #define CAN_F7R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2724 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2725 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2726 #define CAN_F7R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2727 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2728 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2729 #define CAN_F7R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2730 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2731 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2732 #define CAN_F7R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2733 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2734 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2735 #define CAN_F7R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2736 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2737 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2738 #define CAN_F7R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2739 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2740 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2741 #define CAN_F7R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2742 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2743 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2744 #define CAN_F7R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2745 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2746 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2747 #define CAN_F7R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2748 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2749 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2750 #define CAN_F7R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2751 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2752 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2753 #define CAN_F7R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2754 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2755 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2756 #define CAN_F7R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2757 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2758 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2759 #define CAN_F7R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2760 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2761 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2762 #define CAN_F7R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2763 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2764 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2765 #define CAN_F7R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2766 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2767 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2768 #define CAN_F7R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2769 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2770 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2771 #define CAN_F7R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2772 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2773 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2774 #define CAN_F7R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2775 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2776 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2777 #define CAN_F7R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2778 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2779 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2780 #define CAN_F7R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2781 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2782 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2783 #define CAN_F7R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2784 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2785 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2786 #define CAN_F7R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2787 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2788 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2789 #define CAN_F7R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2790 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2791 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2792
Kojto 90:cb3d968589d8 2793 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 2794 #define CAN_F8R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2795 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2796 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2797 #define CAN_F8R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2798 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2799 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2800 #define CAN_F8R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2801 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2802 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2803 #define CAN_F8R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2804 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2805 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2806 #define CAN_F8R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2807 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2808 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2809 #define CAN_F8R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2810 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2811 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2812 #define CAN_F8R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2813 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2814 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2815 #define CAN_F8R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2816 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2817 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2818 #define CAN_F8R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2819 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2820 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2821 #define CAN_F8R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2822 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2823 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2824 #define CAN_F8R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2825 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2826 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2827 #define CAN_F8R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2828 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2829 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2830 #define CAN_F8R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2831 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2832 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2833 #define CAN_F8R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2834 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2835 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2836 #define CAN_F8R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2837 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2838 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2839 #define CAN_F8R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2840 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2841 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2842 #define CAN_F8R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2843 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2844 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2845 #define CAN_F8R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2846 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2847 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2848 #define CAN_F8R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2849 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2850 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2851 #define CAN_F8R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2852 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2853 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2854 #define CAN_F8R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2855 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2856 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2857 #define CAN_F8R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2858 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2859 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2860 #define CAN_F8R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2861 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2862 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2863 #define CAN_F8R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2864 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2865 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2866 #define CAN_F8R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2867 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2868 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2869 #define CAN_F8R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2870 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2871 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2872 #define CAN_F8R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2873 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2874 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2875 #define CAN_F8R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2876 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2877 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2878 #define CAN_F8R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2879 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2880 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2881 #define CAN_F8R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2882 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2883 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2884 #define CAN_F8R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2885 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2886 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2887 #define CAN_F8R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2888 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2889 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2890
Kojto 90:cb3d968589d8 2891 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 2892 #define CAN_F9R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2893 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2894 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2895 #define CAN_F9R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2896 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2897 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2898 #define CAN_F9R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2899 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2900 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2901 #define CAN_F9R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2902 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2903 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2904 #define CAN_F9R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2905 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2906 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2907 #define CAN_F9R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2908 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2909 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2910 #define CAN_F9R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2911 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2912 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2913 #define CAN_F9R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2914 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2915 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2916 #define CAN_F9R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2917 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2918 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2919 #define CAN_F9R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2920 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2921 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2922 #define CAN_F9R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2923 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2924 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2925 #define CAN_F9R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2926 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2927 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2928 #define CAN_F9R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2929 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2930 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2931 #define CAN_F9R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2932 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2933 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2934 #define CAN_F9R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2935 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2936 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2937 #define CAN_F9R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2938 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2939 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2940 #define CAN_F9R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2941 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2942 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2943 #define CAN_F9R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2944 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2945 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2946 #define CAN_F9R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2947 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2948 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2949 #define CAN_F9R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2950 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2951 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2952 #define CAN_F9R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2953 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2954 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2955 #define CAN_F9R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2956 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2957 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2958 #define CAN_F9R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2959 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2960 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2961 #define CAN_F9R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2962 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2963 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2964 #define CAN_F9R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2965 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2966 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2967 #define CAN_F9R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2968 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2969 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2970 #define CAN_F9R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2971 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2972 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2973 #define CAN_F9R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2974 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2975 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2976 #define CAN_F9R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2977 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2978 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2979 #define CAN_F9R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2980 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2981 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2982 #define CAN_F9R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 2983 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2984 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2985 #define CAN_F9R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 2986 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2987 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2988
Kojto 90:cb3d968589d8 2989 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 2990 #define CAN_F10R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2991 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2992 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2993 #define CAN_F10R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2994 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2995 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2996 #define CAN_F10R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2997 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2998 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2999 #define CAN_F10R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3000 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3001 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3002 #define CAN_F10R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3003 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3004 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3005 #define CAN_F10R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3006 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3007 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3008 #define CAN_F10R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3009 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3010 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3011 #define CAN_F10R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3012 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3013 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3014 #define CAN_F10R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3015 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3016 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3017 #define CAN_F10R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3018 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3019 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3020 #define CAN_F10R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3021 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3022 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3023 #define CAN_F10R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3024 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3025 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3026 #define CAN_F10R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3027 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3028 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3029 #define CAN_F10R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3030 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3031 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3032 #define CAN_F10R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3033 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3034 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3035 #define CAN_F10R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3036 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3037 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3038 #define CAN_F10R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3039 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3040 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3041 #define CAN_F10R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3042 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3043 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3044 #define CAN_F10R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3045 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3046 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3047 #define CAN_F10R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3048 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3049 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3050 #define CAN_F10R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3051 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3052 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3053 #define CAN_F10R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3054 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3055 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3056 #define CAN_F10R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3057 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3058 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3059 #define CAN_F10R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3060 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3061 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3062 #define CAN_F10R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3063 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3064 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3065 #define CAN_F10R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3066 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3067 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3068 #define CAN_F10R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3069 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3070 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3071 #define CAN_F10R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3072 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3073 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3074 #define CAN_F10R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3075 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3076 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3077 #define CAN_F10R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3078 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3079 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3080 #define CAN_F10R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3081 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3082 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3083 #define CAN_F10R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3084 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3085 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3086
Kojto 90:cb3d968589d8 3087 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 3088 #define CAN_F11R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3089 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3090 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3091 #define CAN_F11R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3092 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3093 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3094 #define CAN_F11R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3095 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3096 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3097 #define CAN_F11R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3098 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3099 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3100 #define CAN_F11R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3101 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3102 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3103 #define CAN_F11R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3104 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3105 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3106 #define CAN_F11R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3107 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3108 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3109 #define CAN_F11R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3110 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3111 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3112 #define CAN_F11R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3113 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3114 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3115 #define CAN_F11R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3116 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3117 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3118 #define CAN_F11R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3119 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3120 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3121 #define CAN_F11R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3122 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3123 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3124 #define CAN_F11R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3125 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3126 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3127 #define CAN_F11R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3128 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3129 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3130 #define CAN_F11R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3131 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3132 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3133 #define CAN_F11R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3134 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3135 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3136 #define CAN_F11R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3137 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3138 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3139 #define CAN_F11R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3140 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3141 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3142 #define CAN_F11R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3143 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3144 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3145 #define CAN_F11R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3146 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3147 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3148 #define CAN_F11R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3149 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3150 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3151 #define CAN_F11R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3152 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3153 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3154 #define CAN_F11R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3155 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3156 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3157 #define CAN_F11R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3158 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3159 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3160 #define CAN_F11R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3161 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3162 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3163 #define CAN_F11R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3164 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3165 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3166 #define CAN_F11R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3167 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3168 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3169 #define CAN_F11R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3170 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3171 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3172 #define CAN_F11R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3173 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3174 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3175 #define CAN_F11R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3176 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3177 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3178 #define CAN_F11R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3179 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3180 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3181 #define CAN_F11R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3182 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3183 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3184
Kojto 90:cb3d968589d8 3185 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 3186 #define CAN_F12R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3187 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3188 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3189 #define CAN_F12R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3190 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3191 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3192 #define CAN_F12R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3193 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3194 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3195 #define CAN_F12R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3196 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3197 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3198 #define CAN_F12R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3199 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3200 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3201 #define CAN_F12R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3202 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3203 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3204 #define CAN_F12R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3205 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3206 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3207 #define CAN_F12R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3208 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3209 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3210 #define CAN_F12R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3211 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3212 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3213 #define CAN_F12R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3214 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3215 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3216 #define CAN_F12R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3217 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3218 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3219 #define CAN_F12R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3220 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3221 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3222 #define CAN_F12R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3223 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3224 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3225 #define CAN_F12R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3226 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3227 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3228 #define CAN_F12R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3229 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3230 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3231 #define CAN_F12R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3232 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3233 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3234 #define CAN_F12R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3235 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3236 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3237 #define CAN_F12R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3238 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3239 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3240 #define CAN_F12R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3241 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3242 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3243 #define CAN_F12R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3244 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3245 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3246 #define CAN_F12R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3247 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3248 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3249 #define CAN_F12R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3250 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3251 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3252 #define CAN_F12R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3253 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3254 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3255 #define CAN_F12R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3256 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3257 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3258 #define CAN_F12R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3259 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3260 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3261 #define CAN_F12R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3262 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3263 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3264 #define CAN_F12R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3265 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3266 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3267 #define CAN_F12R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3268 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3269 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3270 #define CAN_F12R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3271 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3272 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3273 #define CAN_F12R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3274 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3275 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3276 #define CAN_F12R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3277 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3278 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3279 #define CAN_F12R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3280 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3281 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3282
Kojto 90:cb3d968589d8 3283 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 3284 #define CAN_F13R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3285 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3286 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3287 #define CAN_F13R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3288 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3289 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3290 #define CAN_F13R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3291 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3292 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3293 #define CAN_F13R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3294 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3295 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3296 #define CAN_F13R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3297 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3298 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3299 #define CAN_F13R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3300 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3301 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3302 #define CAN_F13R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3303 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3304 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3305 #define CAN_F13R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3306 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3307 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3308 #define CAN_F13R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3309 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3310 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3311 #define CAN_F13R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3312 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3313 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3314 #define CAN_F13R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3315 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3316 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3317 #define CAN_F13R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3318 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3319 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3320 #define CAN_F13R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3321 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3322 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3323 #define CAN_F13R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3324 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3325 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3326 #define CAN_F13R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3327 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3328 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3329 #define CAN_F13R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3330 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3331 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3332 #define CAN_F13R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3333 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3334 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3335 #define CAN_F13R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3336 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3337 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3338 #define CAN_F13R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3339 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3340 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3341 #define CAN_F13R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3342 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3343 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3344 #define CAN_F13R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3345 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3346 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3347 #define CAN_F13R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3348 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3349 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3350 #define CAN_F13R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3351 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3352 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3353 #define CAN_F13R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3354 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3355 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3356 #define CAN_F13R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3357 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3358 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3359 #define CAN_F13R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3360 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3361 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3362 #define CAN_F13R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3363 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3364 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3365 #define CAN_F13R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3366 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3367 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3368 #define CAN_F13R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3369 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3370 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3371 #define CAN_F13R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3372 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3373 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3374 #define CAN_F13R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3375 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3376 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3377 #define CAN_F13R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3378 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3379 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3380
Kojto 90:cb3d968589d8 3381 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 3382 #define CAN_F0R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3383 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3384 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3385 #define CAN_F0R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3386 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3387 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3388 #define CAN_F0R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3389 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3390 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3391 #define CAN_F0R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3392 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3393 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3394 #define CAN_F0R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3395 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3396 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3397 #define CAN_F0R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3398 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3399 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3400 #define CAN_F0R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3401 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3402 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3403 #define CAN_F0R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3404 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3405 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3406 #define CAN_F0R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3407 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3408 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3409 #define CAN_F0R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3410 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3411 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3412 #define CAN_F0R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3413 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3414 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3415 #define CAN_F0R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3416 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3417 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3418 #define CAN_F0R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3419 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3420 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3421 #define CAN_F0R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3422 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3423 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3424 #define CAN_F0R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3425 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3426 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3427 #define CAN_F0R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3428 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3429 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3430 #define CAN_F0R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3431 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3432 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3433 #define CAN_F0R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3434 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3435 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3436 #define CAN_F0R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3437 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3438 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3439 #define CAN_F0R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3440 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3441 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3442 #define CAN_F0R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3443 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3444 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3445 #define CAN_F0R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3446 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3447 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3448 #define CAN_F0R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3449 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3450 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3451 #define CAN_F0R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3452 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3453 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3454 #define CAN_F0R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3455 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3456 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3457 #define CAN_F0R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3458 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3459 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3460 #define CAN_F0R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3461 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3462 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3463 #define CAN_F0R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3464 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3465 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3466 #define CAN_F0R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3467 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3468 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3469 #define CAN_F0R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3470 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3471 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3472 #define CAN_F0R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3473 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3474 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3475 #define CAN_F0R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3476 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3477 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3478
Kojto 90:cb3d968589d8 3479 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 3480 #define CAN_F1R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3481 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3482 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3483 #define CAN_F1R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3484 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3485 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3486 #define CAN_F1R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3487 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3488 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3489 #define CAN_F1R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3490 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3491 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3492 #define CAN_F1R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3493 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3494 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3495 #define CAN_F1R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3496 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3497 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3498 #define CAN_F1R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3499 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3500 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3501 #define CAN_F1R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3502 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3503 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3504 #define CAN_F1R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3505 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3506 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3507 #define CAN_F1R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3508 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3509 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3510 #define CAN_F1R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3511 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3512 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3513 #define CAN_F1R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3514 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3515 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3516 #define CAN_F1R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3517 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3518 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3519 #define CAN_F1R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3520 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3521 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3522 #define CAN_F1R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3523 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3524 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3525 #define CAN_F1R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3526 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3527 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3528 #define CAN_F1R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3529 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3530 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3531 #define CAN_F1R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3532 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3533 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3534 #define CAN_F1R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3535 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3536 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3537 #define CAN_F1R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3538 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3539 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3540 #define CAN_F1R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3541 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3542 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3543 #define CAN_F1R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3544 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3545 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3546 #define CAN_F1R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3547 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3548 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3549 #define CAN_F1R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3550 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3551 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3552 #define CAN_F1R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3553 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3554 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3555 #define CAN_F1R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3556 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3557 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3558 #define CAN_F1R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3559 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3560 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3561 #define CAN_F1R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3562 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3563 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3564 #define CAN_F1R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3565 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3566 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3567 #define CAN_F1R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3568 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3569 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3570 #define CAN_F1R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3571 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3572 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3573 #define CAN_F1R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3574 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3575 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3576
Kojto 90:cb3d968589d8 3577 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 3578 #define CAN_F2R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3579 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3580 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3581 #define CAN_F2R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3582 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3583 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3584 #define CAN_F2R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3585 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3586 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3587 #define CAN_F2R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3588 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3589 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3590 #define CAN_F2R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3591 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3592 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3593 #define CAN_F2R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3594 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3595 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3596 #define CAN_F2R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3597 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3598 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3599 #define CAN_F2R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3600 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3601 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3602 #define CAN_F2R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3603 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3604 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3605 #define CAN_F2R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3606 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3607 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3608 #define CAN_F2R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3609 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3610 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3611 #define CAN_F2R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3612 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3613 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3614 #define CAN_F2R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3615 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3616 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3617 #define CAN_F2R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3618 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3619 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3620 #define CAN_F2R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3621 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3622 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3623 #define CAN_F2R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3624 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3625 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3626 #define CAN_F2R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3627 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3628 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3629 #define CAN_F2R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3630 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3631 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3632 #define CAN_F2R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3633 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3634 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3635 #define CAN_F2R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3636 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3637 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3638 #define CAN_F2R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3639 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3640 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3641 #define CAN_F2R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3642 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3643 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3644 #define CAN_F2R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3645 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3646 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3647 #define CAN_F2R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3648 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3649 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3650 #define CAN_F2R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3651 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3652 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3653 #define CAN_F2R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3654 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3655 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3656 #define CAN_F2R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3657 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3658 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3659 #define CAN_F2R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3660 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3661 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3662 #define CAN_F2R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3663 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3664 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3665 #define CAN_F2R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3666 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3667 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3668 #define CAN_F2R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3669 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3670 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3671 #define CAN_F2R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3672 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3673 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3674
Kojto 90:cb3d968589d8 3675 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 3676 #define CAN_F3R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3677 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3678 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3679 #define CAN_F3R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3680 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3681 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3682 #define CAN_F3R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3683 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3684 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3685 #define CAN_F3R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3686 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3687 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3688 #define CAN_F3R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3689 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3690 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3691 #define CAN_F3R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3692 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3693 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3694 #define CAN_F3R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3695 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3696 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3697 #define CAN_F3R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3698 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3699 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3700 #define CAN_F3R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3701 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3702 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3703 #define CAN_F3R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3704 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3705 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3706 #define CAN_F3R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3707 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3708 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3709 #define CAN_F3R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3710 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3711 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3712 #define CAN_F3R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3713 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3714 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3715 #define CAN_F3R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3716 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3717 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3718 #define CAN_F3R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3719 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3720 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3721 #define CAN_F3R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3722 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3723 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3724 #define CAN_F3R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3725 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3726 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3727 #define CAN_F3R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3728 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3729 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3730 #define CAN_F3R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3731 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3732 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3733 #define CAN_F3R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3734 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3735 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3736 #define CAN_F3R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3737 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3738 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3739 #define CAN_F3R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3740 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3741 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3742 #define CAN_F3R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3743 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3744 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3745 #define CAN_F3R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3746 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3747 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3748 #define CAN_F3R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3749 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3750 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3751 #define CAN_F3R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3752 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3753 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3754 #define CAN_F3R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3755 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3756 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3757 #define CAN_F3R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3758 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3759 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3760 #define CAN_F3R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3761 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3762 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3763 #define CAN_F3R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3764 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3765 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3766 #define CAN_F3R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3767 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3768 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3769 #define CAN_F3R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3770 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3771 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3772
Kojto 90:cb3d968589d8 3773 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 3774 #define CAN_F4R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3775 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3776 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3777 #define CAN_F4R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3778 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3779 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3780 #define CAN_F4R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3781 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3782 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3783 #define CAN_F4R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3784 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3785 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3786 #define CAN_F4R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3787 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3788 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3789 #define CAN_F4R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3790 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3791 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3792 #define CAN_F4R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3793 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3794 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3795 #define CAN_F4R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3796 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3797 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3798 #define CAN_F4R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3799 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3800 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3801 #define CAN_F4R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3802 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3803 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3804 #define CAN_F4R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3805 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3806 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3807 #define CAN_F4R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3808 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3809 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3810 #define CAN_F4R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3811 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3812 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3813 #define CAN_F4R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3814 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3815 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3816 #define CAN_F4R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3817 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3818 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3819 #define CAN_F4R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3820 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3821 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3822 #define CAN_F4R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3823 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3824 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3825 #define CAN_F4R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3826 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3827 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3828 #define CAN_F4R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3829 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3830 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3831 #define CAN_F4R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3832 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3833 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3834 #define CAN_F4R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3835 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3836 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3837 #define CAN_F4R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3838 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3839 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3840 #define CAN_F4R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3841 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3842 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3843 #define CAN_F4R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3844 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3845 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3846 #define CAN_F4R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3847 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3848 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3849 #define CAN_F4R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3850 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3851 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3852 #define CAN_F4R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3853 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3854 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3855 #define CAN_F4R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3856 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3857 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3858 #define CAN_F4R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3859 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3860 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3861 #define CAN_F4R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3862 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3863 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3864 #define CAN_F4R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3865 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3866 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3867 #define CAN_F4R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3868 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3869 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3870
Kojto 90:cb3d968589d8 3871 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 3872 #define CAN_F5R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3873 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3874 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3875 #define CAN_F5R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3876 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3877 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3878 #define CAN_F5R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3879 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3880 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3881 #define CAN_F5R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3882 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3883 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3884 #define CAN_F5R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3885 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3886 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3887 #define CAN_F5R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3888 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3889 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3890 #define CAN_F5R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3891 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3892 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3893 #define CAN_F5R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3894 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3895 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3896 #define CAN_F5R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3897 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3898 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3899 #define CAN_F5R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3900 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3901 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3902 #define CAN_F5R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 3903 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3904 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3905 #define CAN_F5R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 3906 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3907 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3908 #define CAN_F5R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 3909 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3910 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3911 #define CAN_F5R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 3912 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3913 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3914 #define CAN_F5R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 3915 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3916 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3917 #define CAN_F5R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 3918 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3919 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3920 #define CAN_F5R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 3921 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3922 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3923 #define CAN_F5R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 3924 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3925 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3926 #define CAN_F5R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 3927 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3928 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3929 #define CAN_F5R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 3930 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3931 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3932 #define CAN_F5R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 3933 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3934 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3935 #define CAN_F5R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 3936 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3937 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3938 #define CAN_F5R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 3939 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3940 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3941 #define CAN_F5R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 3942 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3943 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3944 #define CAN_F5R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 3945 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3946 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3947 #define CAN_F5R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 3948 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3949 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3950 #define CAN_F5R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 3951 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3952 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3953 #define CAN_F5R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 3954 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3955 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3956 #define CAN_F5R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 3957 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3958 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3959 #define CAN_F5R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 3960 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3961 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3962 #define CAN_F5R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 3963 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3964 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3965 #define CAN_F5R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 3966 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3967 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 3968
Kojto 90:cb3d968589d8 3969 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 3970 #define CAN_F6R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 3971 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3972 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3973 #define CAN_F6R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 3974 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3975 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3976 #define CAN_F6R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 3977 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3978 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3979 #define CAN_F6R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 3980 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3981 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3982 #define CAN_F6R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 3983 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3984 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3985 #define CAN_F6R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 3986 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3987 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3988 #define CAN_F6R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 3989 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3990 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3991 #define CAN_F6R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 3992 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3993 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3994 #define CAN_F6R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 3995 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3996 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3997 #define CAN_F6R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 3998 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3999 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4000 #define CAN_F6R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4001 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4002 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4003 #define CAN_F6R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4004 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4005 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4006 #define CAN_F6R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4007 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4008 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4009 #define CAN_F6R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4010 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4011 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4012 #define CAN_F6R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4013 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4014 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4015 #define CAN_F6R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4016 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4017 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4018 #define CAN_F6R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4019 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4020 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4021 #define CAN_F6R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4022 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4023 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4024 #define CAN_F6R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4025 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4026 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4027 #define CAN_F6R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4028 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4029 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4030 #define CAN_F6R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4031 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4032 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4033 #define CAN_F6R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4034 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4035 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4036 #define CAN_F6R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4037 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4038 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4039 #define CAN_F6R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4040 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4041 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4042 #define CAN_F6R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4043 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4044 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4045 #define CAN_F6R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4046 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4047 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4048 #define CAN_F6R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4049 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4050 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4051 #define CAN_F6R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4052 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4053 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4054 #define CAN_F6R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4055 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4056 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4057 #define CAN_F6R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4058 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4059 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4060 #define CAN_F6R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4061 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4062 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4063 #define CAN_F6R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4064 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4065 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4066
Kojto 90:cb3d968589d8 4067 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 4068 #define CAN_F7R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4069 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4070 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4071 #define CAN_F7R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4072 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4073 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4074 #define CAN_F7R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4075 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4076 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4077 #define CAN_F7R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4078 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4079 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4080 #define CAN_F7R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4081 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4082 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4083 #define CAN_F7R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4084 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4085 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4086 #define CAN_F7R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4087 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4088 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4089 #define CAN_F7R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4090 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4091 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4092 #define CAN_F7R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4093 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4094 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4095 #define CAN_F7R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4096 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4097 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4098 #define CAN_F7R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4099 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4100 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4101 #define CAN_F7R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4102 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4103 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4104 #define CAN_F7R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4105 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4106 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4107 #define CAN_F7R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4108 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4109 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4110 #define CAN_F7R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4111 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4112 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4113 #define CAN_F7R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4114 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4115 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4116 #define CAN_F7R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4117 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4118 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4119 #define CAN_F7R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4120 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4121 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4122 #define CAN_F7R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4123 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4124 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4125 #define CAN_F7R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4126 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4127 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4128 #define CAN_F7R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4129 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4130 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4131 #define CAN_F7R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4132 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4133 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4134 #define CAN_F7R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4135 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4136 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4137 #define CAN_F7R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4138 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4139 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4140 #define CAN_F7R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4141 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4142 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4143 #define CAN_F7R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4144 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4145 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4146 #define CAN_F7R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4147 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4148 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4149 #define CAN_F7R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4150 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4151 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4152 #define CAN_F7R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4153 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4154 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4155 #define CAN_F7R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4156 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4157 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4158 #define CAN_F7R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4159 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4160 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4161 #define CAN_F7R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4162 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4163 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4164
Kojto 90:cb3d968589d8 4165 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 4166 #define CAN_F8R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4167 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4168 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4169 #define CAN_F8R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4170 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4171 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4172 #define CAN_F8R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4173 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4174 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4175 #define CAN_F8R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4176 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4177 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4178 #define CAN_F8R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4179 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4180 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4181 #define CAN_F8R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4182 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4183 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4184 #define CAN_F8R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4185 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4186 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4187 #define CAN_F8R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4188 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4189 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4190 #define CAN_F8R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4191 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4192 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4193 #define CAN_F8R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4194 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4195 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4196 #define CAN_F8R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4197 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4198 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4199 #define CAN_F8R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4200 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4201 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4202 #define CAN_F8R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4203 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4204 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4205 #define CAN_F8R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4206 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4207 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4208 #define CAN_F8R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4209 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4210 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4211 #define CAN_F8R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4212 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4213 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4214 #define CAN_F8R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4215 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4216 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4217 #define CAN_F8R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4218 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4219 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4220 #define CAN_F8R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4221 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4222 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4223 #define CAN_F8R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4224 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4225 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4226 #define CAN_F8R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4227 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4228 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4229 #define CAN_F8R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4230 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4231 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4232 #define CAN_F8R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4233 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4234 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4235 #define CAN_F8R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4236 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4237 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4238 #define CAN_F8R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4239 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4240 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4241 #define CAN_F8R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4242 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4243 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4244 #define CAN_F8R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4245 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4246 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4247 #define CAN_F8R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4248 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4249 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4250 #define CAN_F8R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4251 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4252 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4253 #define CAN_F8R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4254 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4255 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4256 #define CAN_F8R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4257 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4258 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4259 #define CAN_F8R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4260 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4261 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4262
Kojto 90:cb3d968589d8 4263 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 4264 #define CAN_F9R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4265 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4266 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4267 #define CAN_F9R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4268 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4269 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4270 #define CAN_F9R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4271 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4272 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4273 #define CAN_F9R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4274 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4275 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4276 #define CAN_F9R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4277 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4278 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4279 #define CAN_F9R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4280 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4281 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4282 #define CAN_F9R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4283 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4284 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4285 #define CAN_F9R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4286 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4287 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4288 #define CAN_F9R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4289 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4290 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4291 #define CAN_F9R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4292 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4293 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4294 #define CAN_F9R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4295 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4296 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4297 #define CAN_F9R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4298 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4299 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4300 #define CAN_F9R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4301 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4302 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4303 #define CAN_F9R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4304 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4305 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4306 #define CAN_F9R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4307 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4308 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4309 #define CAN_F9R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4310 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4311 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4312 #define CAN_F9R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4313 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4314 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4315 #define CAN_F9R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4316 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4317 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4318 #define CAN_F9R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4319 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4320 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4321 #define CAN_F9R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4322 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4323 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4324 #define CAN_F9R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4325 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4326 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4327 #define CAN_F9R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4328 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4329 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4330 #define CAN_F9R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4331 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4332 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4333 #define CAN_F9R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4334 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4335 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4336 #define CAN_F9R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4337 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4338 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4339 #define CAN_F9R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4340 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4341 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4342 #define CAN_F9R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4343 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4344 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4345 #define CAN_F9R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4346 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4347 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4348 #define CAN_F9R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4349 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4350 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4351 #define CAN_F9R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4352 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4353 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4354 #define CAN_F9R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4355 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4356 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4357 #define CAN_F9R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4358 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4359 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4360
Kojto 90:cb3d968589d8 4361 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 4362 #define CAN_F10R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4363 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4364 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4365 #define CAN_F10R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4366 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4367 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4368 #define CAN_F10R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4369 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4370 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4371 #define CAN_F10R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4372 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4373 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4374 #define CAN_F10R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4375 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4376 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4377 #define CAN_F10R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4378 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4379 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4380 #define CAN_F10R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4381 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4382 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4383 #define CAN_F10R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4384 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4385 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4386 #define CAN_F10R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4387 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4388 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4389 #define CAN_F10R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4390 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4391 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4392 #define CAN_F10R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4393 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4394 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4395 #define CAN_F10R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4396 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4397 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4398 #define CAN_F10R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4399 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4400 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4401 #define CAN_F10R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4402 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4403 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4404 #define CAN_F10R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4405 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4406 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4407 #define CAN_F10R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4408 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4409 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4410 #define CAN_F10R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4411 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4412 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4413 #define CAN_F10R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4414 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4415 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4416 #define CAN_F10R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4417 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4418 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4419 #define CAN_F10R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4420 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4421 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4422 #define CAN_F10R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4423 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4424 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4425 #define CAN_F10R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4426 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4427 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4428 #define CAN_F10R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4429 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4430 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4431 #define CAN_F10R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4432 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4433 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4434 #define CAN_F10R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4435 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4436 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4437 #define CAN_F10R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4438 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4439 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4440 #define CAN_F10R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4441 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4442 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4443 #define CAN_F10R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4444 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4445 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4446 #define CAN_F10R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4447 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4448 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4449 #define CAN_F10R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4450 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4451 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4452 #define CAN_F10R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4453 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4454 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4455 #define CAN_F10R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4456 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4457 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4458
Kojto 90:cb3d968589d8 4459 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 4460 #define CAN_F11R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4461 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4462 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4463 #define CAN_F11R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4464 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4465 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4466 #define CAN_F11R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4467 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4468 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4469 #define CAN_F11R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4470 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4471 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4472 #define CAN_F11R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4473 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4474 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4475 #define CAN_F11R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4476 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4477 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4478 #define CAN_F11R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4479 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4480 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4481 #define CAN_F11R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4482 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4483 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4484 #define CAN_F11R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4485 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4486 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4487 #define CAN_F11R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4488 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4489 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4490 #define CAN_F11R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4491 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4492 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4493 #define CAN_F11R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4494 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4495 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4496 #define CAN_F11R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4497 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4498 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4499 #define CAN_F11R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4500 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4501 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4502 #define CAN_F11R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4503 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4504 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4505 #define CAN_F11R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4506 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4507 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4508 #define CAN_F11R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4509 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4510 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4511 #define CAN_F11R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4512 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4513 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4514 #define CAN_F11R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4515 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4516 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4517 #define CAN_F11R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4518 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4519 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4520 #define CAN_F11R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4521 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4522 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4523 #define CAN_F11R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4524 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4525 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4526 #define CAN_F11R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4527 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4528 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4529 #define CAN_F11R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4530 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4531 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4532 #define CAN_F11R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4533 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4534 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4535 #define CAN_F11R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4536 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4537 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4538 #define CAN_F11R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4539 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4540 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4541 #define CAN_F11R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4542 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4543 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4544 #define CAN_F11R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4545 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4546 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4547 #define CAN_F11R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4548 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4549 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4550 #define CAN_F11R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4551 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4552 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4553 #define CAN_F11R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4554 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4555 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4556
Kojto 90:cb3d968589d8 4557 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 4558 #define CAN_F12R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4559 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4560 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4561 #define CAN_F12R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4562 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4563 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4564 #define CAN_F12R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4565 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4566 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4567 #define CAN_F12R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4568 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4569 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4570 #define CAN_F12R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4571 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4572 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4573 #define CAN_F12R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4574 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4575 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4576 #define CAN_F12R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4577 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4578 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4579 #define CAN_F12R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4580 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4581 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4582 #define CAN_F12R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4583 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4584 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4585 #define CAN_F12R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4586 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4587 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4588 #define CAN_F12R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4589 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4590 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4591 #define CAN_F12R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4592 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4593 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4594 #define CAN_F12R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4595 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4596 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4597 #define CAN_F12R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4598 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4599 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4600 #define CAN_F12R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4601 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4602 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4603 #define CAN_F12R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4604 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4605 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4606 #define CAN_F12R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4607 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4608 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4609 #define CAN_F12R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4610 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4611 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4612 #define CAN_F12R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4613 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4614 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4615 #define CAN_F12R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4616 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4617 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4618 #define CAN_F12R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4619 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4620 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4621 #define CAN_F12R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4622 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4623 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4624 #define CAN_F12R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4625 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4626 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4627 #define CAN_F12R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4628 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4629 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4630 #define CAN_F12R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4631 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4632 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4633 #define CAN_F12R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4634 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4635 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4636 #define CAN_F12R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4637 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4638 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4639 #define CAN_F12R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4640 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4641 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4642 #define CAN_F12R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4643 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4644 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4645 #define CAN_F12R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4646 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4647 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4648 #define CAN_F12R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4649 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4650 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4651 #define CAN_F12R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4652 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4653 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4654
Kojto 90:cb3d968589d8 4655 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 4656 #define CAN_F13R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4657 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4658 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4659 #define CAN_F13R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4660 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4661 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4662 #define CAN_F13R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4663 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4664 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4665 #define CAN_F13R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4666 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4667 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4668 #define CAN_F13R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4669 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4670 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4671 #define CAN_F13R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4672 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4673 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4674 #define CAN_F13R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4675 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4676 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4677 #define CAN_F13R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4678 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4679 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4680 #define CAN_F13R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4681 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4682 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4683 #define CAN_F13R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4684 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4685 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4686 #define CAN_F13R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4687 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4688 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4689 #define CAN_F13R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4690 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4691 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4692 #define CAN_F13R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4693 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4694 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4695 #define CAN_F13R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4696 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4697 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4698 #define CAN_F13R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4699 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4700 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4701 #define CAN_F13R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4702 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4703 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4704 #define CAN_F13R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4705 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4706 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4707 #define CAN_F13R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4708 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4709 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4710 #define CAN_F13R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4711 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4712 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4713 #define CAN_F13R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4714 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4715 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4716 #define CAN_F13R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4717 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4718 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4719 #define CAN_F13R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4720 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4721 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4722 #define CAN_F13R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4723 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4724 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4725 #define CAN_F13R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4726 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4727 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4728 #define CAN_F13R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4729 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4730 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4731 #define CAN_F13R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4732 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4733 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4734 #define CAN_F13R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4735 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4736 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4737 #define CAN_F13R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4738 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4739 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4740 #define CAN_F13R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4741 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4742 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4743 #define CAN_F13R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4744 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4745 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4746 #define CAN_F13R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4747 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4748 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4749 #define CAN_F13R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4750 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4751 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 4752
Kojto 90:cb3d968589d8 4753 /******************************************************************************/
Kojto 90:cb3d968589d8 4754 /* */
Kojto 90:cb3d968589d8 4755 /* HDMI-CEC (CEC) */
Kojto 90:cb3d968589d8 4756 /* */
Kojto 90:cb3d968589d8 4757 /******************************************************************************/
Kojto 90:cb3d968589d8 4758
Kojto 90:cb3d968589d8 4759 /******************* Bit definition for CEC_CR register *********************/
Kojto 122:f9eeca106725 4760 #define CEC_CR_CECEN_Pos (0U)
Kojto 122:f9eeca106725 4761 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4762 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
Kojto 122:f9eeca106725 4763 #define CEC_CR_TXSOM_Pos (1U)
Kojto 122:f9eeca106725 4764 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4765 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
Kojto 122:f9eeca106725 4766 #define CEC_CR_TXEOM_Pos (2U)
Kojto 122:f9eeca106725 4767 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4768 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
Kojto 90:cb3d968589d8 4769
Kojto 90:cb3d968589d8 4770 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 122:f9eeca106725 4771 #define CEC_CFGR_SFT_Pos (0U)
Kojto 122:f9eeca106725 4772 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 4773 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
Kojto 122:f9eeca106725 4774 #define CEC_CFGR_RXTOL_Pos (3U)
Kojto 122:f9eeca106725 4775 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4776 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
Kojto 122:f9eeca106725 4777 #define CEC_CFGR_BRESTP_Pos (4U)
Kojto 122:f9eeca106725 4778 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4779 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
Kojto 122:f9eeca106725 4780 #define CEC_CFGR_BREGEN_Pos (5U)
Kojto 122:f9eeca106725 4781 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4782 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
Kojto 122:f9eeca106725 4783 #define CEC_CFGR_LBPEGEN_Pos (6U)
Kojto 122:f9eeca106725 4784 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4785 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */
Kojto 122:f9eeca106725 4786 #define CEC_CFGR_BRDNOGEN_Pos (7U)
Kojto 122:f9eeca106725 4787 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4788 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */
Kojto 122:f9eeca106725 4789 #define CEC_CFGR_SFTOPT_Pos (8U)
Kojto 122:f9eeca106725 4790 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4791 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
Kojto 122:f9eeca106725 4792 #define CEC_CFGR_OAR_Pos (16U)
Kojto 122:f9eeca106725 4793 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
Kojto 122:f9eeca106725 4794 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
Kojto 122:f9eeca106725 4795 #define CEC_CFGR_LSTN_Pos (31U)
Kojto 122:f9eeca106725 4796 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4797 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
Kojto 90:cb3d968589d8 4798
Kojto 90:cb3d968589d8 4799 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 122:f9eeca106725 4800 #define CEC_TXDR_TXD_Pos (0U)
Kojto 122:f9eeca106725 4801 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 4802 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
Kojto 90:cb3d968589d8 4803
Kojto 90:cb3d968589d8 4804 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 122:f9eeca106725 4805 #define CEC_TXDR_RXD_Pos (0U)
Kojto 122:f9eeca106725 4806 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 4807 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
Kojto 90:cb3d968589d8 4808
Kojto 90:cb3d968589d8 4809 /******************* Bit definition for CEC_ISR register ********************/
Kojto 122:f9eeca106725 4810 #define CEC_ISR_RXBR_Pos (0U)
Kojto 122:f9eeca106725 4811 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4812 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
Kojto 122:f9eeca106725 4813 #define CEC_ISR_RXEND_Pos (1U)
Kojto 122:f9eeca106725 4814 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4815 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
Kojto 122:f9eeca106725 4816 #define CEC_ISR_RXOVR_Pos (2U)
Kojto 122:f9eeca106725 4817 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4818 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
Kojto 122:f9eeca106725 4819 #define CEC_ISR_BRE_Pos (3U)
Kojto 122:f9eeca106725 4820 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4821 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
Kojto 122:f9eeca106725 4822 #define CEC_ISR_SBPE_Pos (4U)
Kojto 122:f9eeca106725 4823 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4824 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
Kojto 122:f9eeca106725 4825 #define CEC_ISR_LBPE_Pos (5U)
Kojto 122:f9eeca106725 4826 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4827 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
Kojto 122:f9eeca106725 4828 #define CEC_ISR_RXACKE_Pos (6U)
Kojto 122:f9eeca106725 4829 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4830 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
Kojto 122:f9eeca106725 4831 #define CEC_ISR_ARBLST_Pos (7U)
Kojto 122:f9eeca106725 4832 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4833 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
Kojto 122:f9eeca106725 4834 #define CEC_ISR_TXBR_Pos (8U)
Kojto 122:f9eeca106725 4835 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4836 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
Kojto 122:f9eeca106725 4837 #define CEC_ISR_TXEND_Pos (9U)
Kojto 122:f9eeca106725 4838 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4839 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
Kojto 122:f9eeca106725 4840 #define CEC_ISR_TXUDR_Pos (10U)
Kojto 122:f9eeca106725 4841 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4842 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
Kojto 122:f9eeca106725 4843 #define CEC_ISR_TXERR_Pos (11U)
Kojto 122:f9eeca106725 4844 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4845 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
Kojto 122:f9eeca106725 4846 #define CEC_ISR_TXACKE_Pos (12U)
Kojto 122:f9eeca106725 4847 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4848 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
Kojto 90:cb3d968589d8 4849
Kojto 90:cb3d968589d8 4850 /******************* Bit definition for CEC_IER register ********************/
Kojto 122:f9eeca106725 4851 #define CEC_IER_RXBRIE_Pos (0U)
Kojto 122:f9eeca106725 4852 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4853 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
Kojto 122:f9eeca106725 4854 #define CEC_IER_RXENDIE_Pos (1U)
Kojto 122:f9eeca106725 4855 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4856 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
Kojto 122:f9eeca106725 4857 #define CEC_IER_RXOVRIE_Pos (2U)
Kojto 122:f9eeca106725 4858 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4859 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
Kojto 122:f9eeca106725 4860 #define CEC_IER_BREIE_Pos (3U)
Kojto 122:f9eeca106725 4861 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4862 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 122:f9eeca106725 4863 #define CEC_IER_SBPEIE_Pos (4U)
Kojto 122:f9eeca106725 4864 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4865 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
Kojto 122:f9eeca106725 4866 #define CEC_IER_LBPEIE_Pos (5U)
Kojto 122:f9eeca106725 4867 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4868 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 122:f9eeca106725 4869 #define CEC_IER_RXACKEIE_Pos (6U)
Kojto 122:f9eeca106725 4870 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4871 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 122:f9eeca106725 4872 #define CEC_IER_ARBLSTIE_Pos (7U)
Kojto 122:f9eeca106725 4873 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4874 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
Kojto 122:f9eeca106725 4875 #define CEC_IER_TXBRIE_Pos (8U)
Kojto 122:f9eeca106725 4876 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4877 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
Kojto 122:f9eeca106725 4878 #define CEC_IER_TXENDIE_Pos (9U)
Kojto 122:f9eeca106725 4879 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4880 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
Kojto 122:f9eeca106725 4881 #define CEC_IER_TXUDRIE_Pos (10U)
Kojto 122:f9eeca106725 4882 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4883 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 122:f9eeca106725 4884 #define CEC_IER_TXERRIE_Pos (11U)
Kojto 122:f9eeca106725 4885 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4886 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
Kojto 122:f9eeca106725 4887 #define CEC_IER_TXACKEIE_Pos (12U)
Kojto 122:f9eeca106725 4888 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4889 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 90:cb3d968589d8 4890
Kojto 90:cb3d968589d8 4891 /******************************************************************************/
Kojto 90:cb3d968589d8 4892 /* */
Kojto 90:cb3d968589d8 4893 /* Analog Comparators (COMP) */
Kojto 90:cb3d968589d8 4894 /* */
Kojto 90:cb3d968589d8 4895 /******************************************************************************/
Kojto 90:cb3d968589d8 4896 /*********************** Bit definition for COMP_CSR register ***************/
Kojto 90:cb3d968589d8 4897 /* COMP1 bits definition */
Kojto 122:f9eeca106725 4898 #define COMP_CSR_COMP1EN_Pos (0U)
Kojto 122:f9eeca106725 4899 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4900 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
Kojto 122:f9eeca106725 4901 #define COMP_CSR_COMP1SW1_Pos (1U)
Kojto 122:f9eeca106725 4902 #define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4903 #define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */
Kojto 122:f9eeca106725 4904 #define COMP_CSR_COMP1MODE_Pos (2U)
Kojto 122:f9eeca106725 4905 #define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 4906 #define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */
Kojto 122:f9eeca106725 4907 #define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4908 #define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4909 #define COMP_CSR_COMP1INSEL_Pos (4U)
Kojto 122:f9eeca106725 4910 #define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4911 #define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */
Kojto 122:f9eeca106725 4912 #define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4913 #define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4914 #define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4915 #define COMP_CSR_COMP1OUTSEL_Pos (8U)
Kojto 122:f9eeca106725 4916 #define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 4917 #define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
Kojto 122:f9eeca106725 4918 #define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4919 #define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4920 #define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4921 #define COMP_CSR_COMP1POL_Pos (11U)
Kojto 122:f9eeca106725 4922 #define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4923 #define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */
Kojto 122:f9eeca106725 4924 #define COMP_CSR_COMP1HYST_Pos (12U)
Kojto 122:f9eeca106725 4925 #define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 4926 #define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */
Kojto 122:f9eeca106725 4927 #define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4928 #define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4929 #define COMP_CSR_COMP1OUT_Pos (14U)
Kojto 122:f9eeca106725 4930 #define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4931 #define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */
Kojto 122:f9eeca106725 4932 #define COMP_CSR_COMP1LOCK_Pos (15U)
Kojto 122:f9eeca106725 4933 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4934 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
Kojto 90:cb3d968589d8 4935 /* COMP2 bits definition */
Kojto 122:f9eeca106725 4936 #define COMP_CSR_COMP2EN_Pos (16U)
Kojto 122:f9eeca106725 4937 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4938 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
Kojto 122:f9eeca106725 4939 #define COMP_CSR_COMP2MODE_Pos (18U)
Kojto 122:f9eeca106725 4940 #define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 4941 #define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */
Kojto 122:f9eeca106725 4942 #define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4943 #define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4944 #define COMP_CSR_COMP2INSEL_Pos (20U)
Kojto 122:f9eeca106725 4945 #define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 4946 #define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
Kojto 122:f9eeca106725 4947 #define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4948 #define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4949 #define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4950 #define COMP_CSR_WNDWEN_Pos (23U)
Kojto 122:f9eeca106725 4951 #define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4952 #define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
Kojto 122:f9eeca106725 4953 #define COMP_CSR_COMP2OUTSEL_Pos (24U)
Kojto 122:f9eeca106725 4954 #define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 4955 #define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
Kojto 122:f9eeca106725 4956 #define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4957 #define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4958 #define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4959 #define COMP_CSR_COMP2POL_Pos (27U)
Kojto 122:f9eeca106725 4960 #define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4961 #define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
Kojto 122:f9eeca106725 4962 #define COMP_CSR_COMP2HYST_Pos (28U)
Kojto 122:f9eeca106725 4963 #define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 4964 #define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */
Kojto 122:f9eeca106725 4965 #define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4966 #define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4967 #define COMP_CSR_COMP2OUT_Pos (30U)
Kojto 122:f9eeca106725 4968 #define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4969 #define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */
Kojto 122:f9eeca106725 4970 #define COMP_CSR_COMP2LOCK_Pos (31U)
Kojto 122:f9eeca106725 4971 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4972 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
Kojto 90:cb3d968589d8 4973 /* COMPx bits definition */
Kojto 122:f9eeca106725 4974 #define COMP_CSR_COMPxEN_Pos (0U)
Kojto 122:f9eeca106725 4975 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4976 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
Kojto 122:f9eeca106725 4977 #define COMP_CSR_COMPxMODE_Pos (2U)
Kojto 122:f9eeca106725 4978 #define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 4979 #define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */
Kojto 122:f9eeca106725 4980 #define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4981 #define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4982 #define COMP_CSR_COMPxINSEL_Pos (4U)
Kojto 122:f9eeca106725 4983 #define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4984 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
Kojto 122:f9eeca106725 4985 #define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4986 #define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4987 #define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4988 #define COMP_CSR_COMPxOUTSEL_Pos (8U)
Kojto 122:f9eeca106725 4989 #define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 4990 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
Kojto 122:f9eeca106725 4991 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4992 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4993 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4994 #define COMP_CSR_COMPxPOL_Pos (11U)
Kojto 122:f9eeca106725 4995 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4996 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
Kojto 122:f9eeca106725 4997 #define COMP_CSR_COMPxHYST_Pos (12U)
Kojto 122:f9eeca106725 4998 #define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 4999 #define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */
Kojto 122:f9eeca106725 5000 #define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5001 #define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5002 #define COMP_CSR_COMPxOUT_Pos (14U)
Kojto 122:f9eeca106725 5003 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5004 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
Kojto 122:f9eeca106725 5005 #define COMP_CSR_COMPxLOCK_Pos (15U)
Kojto 122:f9eeca106725 5006 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5007 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
Kojto 90:cb3d968589d8 5008
Kojto 90:cb3d968589d8 5009 /******************************************************************************/
Kojto 90:cb3d968589d8 5010 /* */
Kojto 90:cb3d968589d8 5011 /* CRC calculation unit (CRC) */
Kojto 90:cb3d968589d8 5012 /* */
Kojto 90:cb3d968589d8 5013 /******************************************************************************/
Kojto 122:f9eeca106725 5014
Kojto 122:f9eeca106725 5015 /*
Kojto 122:f9eeca106725 5016 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 5017 */
Kojto 122:f9eeca106725 5018
Kojto 122:f9eeca106725 5019 /* Support of Programmable Polynomial size and value feature */
Kojto 122:f9eeca106725 5020 #define CRC_PROG_POLYNOMIAL_SUPPORT
Kojto 122:f9eeca106725 5021
Kojto 90:cb3d968589d8 5022 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 5023 #define CRC_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 5024 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5025 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
Kojto 90:cb3d968589d8 5026
Kojto 90:cb3d968589d8 5027 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 5028 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
Kojto 90:cb3d968589d8 5029
Kojto 90:cb3d968589d8 5030 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 5031 #define CRC_CR_RESET_Pos (0U)
Kojto 122:f9eeca106725 5032 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5033 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
Kojto 122:f9eeca106725 5034 #define CRC_CR_POLYSIZE_Pos (3U)
Kojto 122:f9eeca106725 5035 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 5036 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
Kojto 122:f9eeca106725 5037 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5038 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5039 #define CRC_CR_REV_IN_Pos (5U)
Kojto 122:f9eeca106725 5040 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 5041 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
Kojto 122:f9eeca106725 5042 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5043 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5044 #define CRC_CR_REV_OUT_Pos (7U)
Kojto 122:f9eeca106725 5045 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5046 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
Kojto 90:cb3d968589d8 5047
Kojto 90:cb3d968589d8 5048 /******************* Bit definition for CRC_INIT register *******************/
Kojto 122:f9eeca106725 5049 #define CRC_INIT_INIT_Pos (0U)
Kojto 122:f9eeca106725 5050 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5051 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
Kojto 90:cb3d968589d8 5052
Kojto 90:cb3d968589d8 5053 /******************* Bit definition for CRC_POL register ********************/
Kojto 122:f9eeca106725 5054 #define CRC_POL_POL_Pos (0U)
Kojto 122:f9eeca106725 5055 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5056 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
Kojto 90:cb3d968589d8 5057
Kojto 90:cb3d968589d8 5058 /******************************************************************************/
Kojto 90:cb3d968589d8 5059 /* */
Kojto 90:cb3d968589d8 5060 /* CRS Clock Recovery System */
Kojto 90:cb3d968589d8 5061 /******************************************************************************/
Kojto 90:cb3d968589d8 5062
Kojto 90:cb3d968589d8 5063 /******************* Bit definition for CRS_CR register *********************/
Kojto 122:f9eeca106725 5064 #define CRS_CR_SYNCOKIE_Pos (0U)
Kojto 122:f9eeca106725 5065 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5066 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
Kojto 122:f9eeca106725 5067 #define CRS_CR_SYNCWARNIE_Pos (1U)
Kojto 122:f9eeca106725 5068 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5069 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
Kojto 122:f9eeca106725 5070 #define CRS_CR_ERRIE_Pos (2U)
Kojto 122:f9eeca106725 5071 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5072 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
Kojto 122:f9eeca106725 5073 #define CRS_CR_ESYNCIE_Pos (3U)
Kojto 122:f9eeca106725 5074 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5075 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
Kojto 122:f9eeca106725 5076 #define CRS_CR_CEN_Pos (5U)
Kojto 122:f9eeca106725 5077 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5078 #define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
Kojto 122:f9eeca106725 5079 #define CRS_CR_AUTOTRIMEN_Pos (6U)
Kojto 122:f9eeca106725 5080 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5081 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
Kojto 122:f9eeca106725 5082 #define CRS_CR_SWSYNC_Pos (7U)
Kojto 122:f9eeca106725 5083 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5084 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
Kojto 122:f9eeca106725 5085 #define CRS_CR_TRIM_Pos (8U)
Kojto 122:f9eeca106725 5086 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
Kojto 122:f9eeca106725 5087 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
Kojto 90:cb3d968589d8 5088
Kojto 90:cb3d968589d8 5089 /******************* Bit definition for CRS_CFGR register *********************/
Kojto 122:f9eeca106725 5090 #define CRS_CFGR_RELOAD_Pos (0U)
Kojto 122:f9eeca106725 5091 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 5092 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
Kojto 122:f9eeca106725 5093 #define CRS_CFGR_FELIM_Pos (16U)
Kojto 122:f9eeca106725 5094 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 5095 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
Kojto 122:f9eeca106725 5096
Kojto 122:f9eeca106725 5097 #define CRS_CFGR_SYNCDIV_Pos (24U)
Kojto 122:f9eeca106725 5098 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 5099 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
Kojto 122:f9eeca106725 5100 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5101 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5102 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5103
Kojto 122:f9eeca106725 5104 #define CRS_CFGR_SYNCSRC_Pos (28U)
Kojto 122:f9eeca106725 5105 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 5106 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
Kojto 122:f9eeca106725 5107 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5108 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5109
Kojto 122:f9eeca106725 5110 #define CRS_CFGR_SYNCPOL_Pos (31U)
Kojto 122:f9eeca106725 5111 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5112 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
Kojto 90:cb3d968589d8 5113
Kojto 90:cb3d968589d8 5114 /******************* Bit definition for CRS_ISR register *********************/
Kojto 122:f9eeca106725 5115 #define CRS_ISR_SYNCOKF_Pos (0U)
Kojto 122:f9eeca106725 5116 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5117 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
Kojto 122:f9eeca106725 5118 #define CRS_ISR_SYNCWARNF_Pos (1U)
Kojto 122:f9eeca106725 5119 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5120 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
Kojto 122:f9eeca106725 5121 #define CRS_ISR_ERRF_Pos (2U)
Kojto 122:f9eeca106725 5122 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5123 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
Kojto 122:f9eeca106725 5124 #define CRS_ISR_ESYNCF_Pos (3U)
Kojto 122:f9eeca106725 5125 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5126 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
Kojto 122:f9eeca106725 5127 #define CRS_ISR_SYNCERR_Pos (8U)
Kojto 122:f9eeca106725 5128 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5129 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
Kojto 122:f9eeca106725 5130 #define CRS_ISR_SYNCMISS_Pos (9U)
Kojto 122:f9eeca106725 5131 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5132 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
Kojto 122:f9eeca106725 5133 #define CRS_ISR_TRIMOVF_Pos (10U)
Kojto 122:f9eeca106725 5134 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5135 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
Kojto 122:f9eeca106725 5136 #define CRS_ISR_FEDIR_Pos (15U)
Kojto 122:f9eeca106725 5137 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5138 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
Kojto 122:f9eeca106725 5139 #define CRS_ISR_FECAP_Pos (16U)
Kojto 122:f9eeca106725 5140 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 5141 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
Kojto 90:cb3d968589d8 5142
Kojto 90:cb3d968589d8 5143 /******************* Bit definition for CRS_ICR register *********************/
Kojto 122:f9eeca106725 5144 #define CRS_ICR_SYNCOKC_Pos (0U)
Kojto 122:f9eeca106725 5145 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5146 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
Kojto 122:f9eeca106725 5147 #define CRS_ICR_SYNCWARNC_Pos (1U)
Kojto 122:f9eeca106725 5148 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5149 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
Kojto 122:f9eeca106725 5150 #define CRS_ICR_ERRC_Pos (2U)
Kojto 122:f9eeca106725 5151 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5152 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
Kojto 122:f9eeca106725 5153 #define CRS_ICR_ESYNCC_Pos (3U)
Kojto 122:f9eeca106725 5154 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5155 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
Kojto 90:cb3d968589d8 5156
Kojto 90:cb3d968589d8 5157 /******************************************************************************/
Kojto 90:cb3d968589d8 5158 /* */
Kojto 90:cb3d968589d8 5159 /* Digital to Analog Converter (DAC) */
Kojto 90:cb3d968589d8 5160 /* */
Kojto 90:cb3d968589d8 5161 /******************************************************************************/
Kojto 122:f9eeca106725 5162
Kojto 122:f9eeca106725 5163 /*
Kojto 122:f9eeca106725 5164 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 5165 */
Kojto 122:f9eeca106725 5166 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
Kojto 122:f9eeca106725 5167
Kojto 90:cb3d968589d8 5168 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 5169 #define DAC_CR_EN1_Pos (0U)
Kojto 122:f9eeca106725 5170 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5171 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
Kojto 122:f9eeca106725 5172 #define DAC_CR_BOFF1_Pos (1U)
Kojto 122:f9eeca106725 5173 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5174 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 5175 #define DAC_CR_TEN1_Pos (2U)
Kojto 122:f9eeca106725 5176 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5177 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 5178
Kojto 122:f9eeca106725 5179 #define DAC_CR_TSEL1_Pos (3U)
Kojto 122:f9eeca106725 5180 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 5181 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 5182 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5183 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5184 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5185
Kojto 122:f9eeca106725 5186 #define DAC_CR_WAVE1_Pos (6U)
Kojto 122:f9eeca106725 5187 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 5188 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 5189 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5190 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5191
Kojto 122:f9eeca106725 5192 #define DAC_CR_MAMP1_Pos (8U)
Kojto 122:f9eeca106725 5193 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 5194 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 5195 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5196 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5197 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5198 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5199
Kojto 122:f9eeca106725 5200 #define DAC_CR_DMAEN1_Pos (12U)
Kojto 122:f9eeca106725 5201 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5202 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
Kojto 122:f9eeca106725 5203 #define DAC_CR_DMAUDRIE1_Pos (13U)
Kojto 122:f9eeca106725 5204 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5205 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */
Kojto 122:f9eeca106725 5206
Kojto 122:f9eeca106725 5207 #define DAC_CR_EN2_Pos (16U)
Kojto 122:f9eeca106725 5208 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5209 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
Kojto 122:f9eeca106725 5210 #define DAC_CR_BOFF2_Pos (17U)
Kojto 122:f9eeca106725 5211 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5212 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 5213 #define DAC_CR_TEN2_Pos (18U)
Kojto 122:f9eeca106725 5214 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5215 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 5216
Kojto 122:f9eeca106725 5217 #define DAC_CR_TSEL2_Pos (19U)
Kojto 122:f9eeca106725 5218 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
Kojto 122:f9eeca106725 5219 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 5220 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5221 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5222 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5223
Kojto 122:f9eeca106725 5224 #define DAC_CR_WAVE2_Pos (22U)
Kojto 122:f9eeca106725 5225 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 5226 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 5227 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5228 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5229
Kojto 122:f9eeca106725 5230 #define DAC_CR_MAMP2_Pos (24U)
Kojto 122:f9eeca106725 5231 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 5232 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 5233 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5234 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5235 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5236 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5237
Kojto 122:f9eeca106725 5238 #define DAC_CR_DMAEN2_Pos (28U)
Kojto 122:f9eeca106725 5239 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5240 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 5241 #define DAC_CR_DMAUDRIE2_Pos (29U)
Kojto 122:f9eeca106725 5242 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5243 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA Underrun Interrupt enable */
Kojto 90:cb3d968589d8 5244
Kojto 90:cb3d968589d8 5245 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 5246 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
Kojto 122:f9eeca106725 5247 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5248 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
Kojto 122:f9eeca106725 5249 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
Kojto 122:f9eeca106725 5250 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5251 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
Kojto 90:cb3d968589d8 5252
Kojto 90:cb3d968589d8 5253 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 5254 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5255 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5256 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
Kojto 90:cb3d968589d8 5257
Kojto 90:cb3d968589d8 5258 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 5259 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 5260 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5261 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
Kojto 90:cb3d968589d8 5262
Kojto 90:cb3d968589d8 5263 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 5264 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5265 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5266 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
Kojto 90:cb3d968589d8 5267
Kojto 90:cb3d968589d8 5268 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 5269 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 5270 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5271 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 5272
Kojto 90:cb3d968589d8 5273 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 5274 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
Kojto 122:f9eeca106725 5275 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5276 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 5277
Kojto 90:cb3d968589d8 5278 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 5279 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 5280 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5281 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 5282
Kojto 90:cb3d968589d8 5283 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 5284 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5285 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5286 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 5287 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
Kojto 122:f9eeca106725 5288 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 5289 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 5290
Kojto 90:cb3d968589d8 5291 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 5292 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 5293 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5294 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 5295 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
Kojto 122:f9eeca106725 5296 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
Kojto 122:f9eeca106725 5297 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 5298
Kojto 90:cb3d968589d8 5299 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 5300 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5301 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5302 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 5303 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
Kojto 122:f9eeca106725 5304 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 5305 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 5306
Kojto 90:cb3d968589d8 5307 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 5308 #define DAC_DOR1_DACC1DOR_Pos (0U)
Kojto 122:f9eeca106725 5309 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5310 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
Kojto 90:cb3d968589d8 5311
Kojto 90:cb3d968589d8 5312 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 5313 #define DAC_DOR2_DACC2DOR_Pos (0U)
Kojto 122:f9eeca106725 5314 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5315 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
Kojto 90:cb3d968589d8 5316
Kojto 90:cb3d968589d8 5317 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 5318 #define DAC_SR_DMAUDR1_Pos (13U)
Kojto 122:f9eeca106725 5319 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5320 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 5321 #define DAC_SR_DMAUDR2_Pos (29U)
Kojto 122:f9eeca106725 5322 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5323 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
Kojto 90:cb3d968589d8 5324
Kojto 90:cb3d968589d8 5325 /******************************************************************************/
Kojto 90:cb3d968589d8 5326 /* */
Kojto 90:cb3d968589d8 5327 /* Debug MCU (DBGMCU) */
Kojto 90:cb3d968589d8 5328 /* */
Kojto 90:cb3d968589d8 5329 /******************************************************************************/
Kojto 90:cb3d968589d8 5330
Kojto 90:cb3d968589d8 5331 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 122:f9eeca106725 5332 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
Kojto 122:f9eeca106725 5333 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5334 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
Kojto 122:f9eeca106725 5335
Kojto 122:f9eeca106725 5336 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
Kojto 122:f9eeca106725 5337 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 5338 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 122:f9eeca106725 5339 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5340 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5341 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5342 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5343 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5344 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5345 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5346 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5347 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5348 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5349 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5350 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5351 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5352 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5353 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5354 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 5355
Kojto 90:cb3d968589d8 5356 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 122:f9eeca106725 5357 #define DBGMCU_CR_DBG_STOP_Pos (1U)
Kojto 122:f9eeca106725 5358 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5359 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
Kojto 122:f9eeca106725 5360 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
Kojto 122:f9eeca106725 5361 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5362 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
Kojto 90:cb3d968589d8 5363
Kojto 90:cb3d968589d8 5364 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 122:f9eeca106725 5365 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
Kojto 122:f9eeca106725 5366 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5367 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
Kojto 122:f9eeca106725 5368 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
Kojto 122:f9eeca106725 5369 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5370 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
Kojto 122:f9eeca106725 5371 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
Kojto 122:f9eeca106725 5372 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5373 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
Kojto 122:f9eeca106725 5374 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
Kojto 122:f9eeca106725 5375 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5376 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
Kojto 122:f9eeca106725 5377 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
Kojto 122:f9eeca106725 5378 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5379 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
Kojto 122:f9eeca106725 5380 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
Kojto 122:f9eeca106725 5381 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5382 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
Kojto 122:f9eeca106725 5383 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
Kojto 122:f9eeca106725 5384 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5385 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 5386 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
Kojto 122:f9eeca106725 5387 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5388 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 5389 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
Kojto 122:f9eeca106725 5390 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5391 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 122:f9eeca106725 5392 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
Kojto 122:f9eeca106725 5393 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5394 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk /*!< CAN debug stopped when Core is halted */
Kojto 90:cb3d968589d8 5395
Kojto 90:cb3d968589d8 5396 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 122:f9eeca106725 5397 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
Kojto 122:f9eeca106725 5398 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5399 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
Kojto 122:f9eeca106725 5400 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
Kojto 122:f9eeca106725 5401 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5402 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */
Kojto 122:f9eeca106725 5403 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
Kojto 122:f9eeca106725 5404 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5405 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
Kojto 122:f9eeca106725 5406 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
Kojto 122:f9eeca106725 5407 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5408 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
Kojto 90:cb3d968589d8 5409
Kojto 90:cb3d968589d8 5410 /******************************************************************************/
Kojto 90:cb3d968589d8 5411 /* */
Kojto 90:cb3d968589d8 5412 /* DMA Controller (DMA) */
Kojto 90:cb3d968589d8 5413 /* */
Kojto 90:cb3d968589d8 5414 /******************************************************************************/
Kojto 90:cb3d968589d8 5415 /******************* Bit definition for DMA_ISR register ********************/
Kojto 122:f9eeca106725 5416 #define DMA_ISR_GIF1_Pos (0U)
Kojto 122:f9eeca106725 5417 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5418 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
Kojto 122:f9eeca106725 5419 #define DMA_ISR_TCIF1_Pos (1U)
Kojto 122:f9eeca106725 5420 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5421 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
Kojto 122:f9eeca106725 5422 #define DMA_ISR_HTIF1_Pos (2U)
Kojto 122:f9eeca106725 5423 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5424 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
Kojto 122:f9eeca106725 5425 #define DMA_ISR_TEIF1_Pos (3U)
Kojto 122:f9eeca106725 5426 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5427 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
Kojto 122:f9eeca106725 5428 #define DMA_ISR_GIF2_Pos (4U)
Kojto 122:f9eeca106725 5429 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5430 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
Kojto 122:f9eeca106725 5431 #define DMA_ISR_TCIF2_Pos (5U)
Kojto 122:f9eeca106725 5432 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5433 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
Kojto 122:f9eeca106725 5434 #define DMA_ISR_HTIF2_Pos (6U)
Kojto 122:f9eeca106725 5435 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5436 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
Kojto 122:f9eeca106725 5437 #define DMA_ISR_TEIF2_Pos (7U)
Kojto 122:f9eeca106725 5438 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5439 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
Kojto 122:f9eeca106725 5440 #define DMA_ISR_GIF3_Pos (8U)
Kojto 122:f9eeca106725 5441 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5442 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
Kojto 122:f9eeca106725 5443 #define DMA_ISR_TCIF3_Pos (9U)
Kojto 122:f9eeca106725 5444 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5445 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
Kojto 122:f9eeca106725 5446 #define DMA_ISR_HTIF3_Pos (10U)
Kojto 122:f9eeca106725 5447 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5448 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
Kojto 122:f9eeca106725 5449 #define DMA_ISR_TEIF3_Pos (11U)
Kojto 122:f9eeca106725 5450 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5451 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
Kojto 122:f9eeca106725 5452 #define DMA_ISR_GIF4_Pos (12U)
Kojto 122:f9eeca106725 5453 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5454 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
Kojto 122:f9eeca106725 5455 #define DMA_ISR_TCIF4_Pos (13U)
Kojto 122:f9eeca106725 5456 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5457 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
Kojto 122:f9eeca106725 5458 #define DMA_ISR_HTIF4_Pos (14U)
Kojto 122:f9eeca106725 5459 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5460 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
Kojto 122:f9eeca106725 5461 #define DMA_ISR_TEIF4_Pos (15U)
Kojto 122:f9eeca106725 5462 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5463 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
Kojto 122:f9eeca106725 5464 #define DMA_ISR_GIF5_Pos (16U)
Kojto 122:f9eeca106725 5465 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5466 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
Kojto 122:f9eeca106725 5467 #define DMA_ISR_TCIF5_Pos (17U)
Kojto 122:f9eeca106725 5468 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5469 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
Kojto 122:f9eeca106725 5470 #define DMA_ISR_HTIF5_Pos (18U)
Kojto 122:f9eeca106725 5471 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5472 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
Kojto 122:f9eeca106725 5473 #define DMA_ISR_TEIF5_Pos (19U)
Kojto 122:f9eeca106725 5474 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5475 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
Kojto 122:f9eeca106725 5476 #define DMA_ISR_GIF6_Pos (20U)
Kojto 122:f9eeca106725 5477 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5478 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
Kojto 122:f9eeca106725 5479 #define DMA_ISR_TCIF6_Pos (21U)
Kojto 122:f9eeca106725 5480 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5481 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
Kojto 122:f9eeca106725 5482 #define DMA_ISR_HTIF6_Pos (22U)
Kojto 122:f9eeca106725 5483 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5484 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
Kojto 122:f9eeca106725 5485 #define DMA_ISR_TEIF6_Pos (23U)
Kojto 122:f9eeca106725 5486 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5487 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
Kojto 122:f9eeca106725 5488 #define DMA_ISR_GIF7_Pos (24U)
Kojto 122:f9eeca106725 5489 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5490 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
Kojto 122:f9eeca106725 5491 #define DMA_ISR_TCIF7_Pos (25U)
Kojto 122:f9eeca106725 5492 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5493 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
Kojto 122:f9eeca106725 5494 #define DMA_ISR_HTIF7_Pos (26U)
Kojto 122:f9eeca106725 5495 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5496 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
Kojto 122:f9eeca106725 5497 #define DMA_ISR_TEIF7_Pos (27U)
Kojto 122:f9eeca106725 5498 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5499 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
Kojto 90:cb3d968589d8 5500
Kojto 90:cb3d968589d8 5501 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 122:f9eeca106725 5502 #define DMA_IFCR_CGIF1_Pos (0U)
Kojto 122:f9eeca106725 5503 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5504 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
Kojto 122:f9eeca106725 5505 #define DMA_IFCR_CTCIF1_Pos (1U)
Kojto 122:f9eeca106725 5506 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5507 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
Kojto 122:f9eeca106725 5508 #define DMA_IFCR_CHTIF1_Pos (2U)
Kojto 122:f9eeca106725 5509 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5510 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
Kojto 122:f9eeca106725 5511 #define DMA_IFCR_CTEIF1_Pos (3U)
Kojto 122:f9eeca106725 5512 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5513 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
Kojto 122:f9eeca106725 5514 #define DMA_IFCR_CGIF2_Pos (4U)
Kojto 122:f9eeca106725 5515 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5516 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
Kojto 122:f9eeca106725 5517 #define DMA_IFCR_CTCIF2_Pos (5U)
Kojto 122:f9eeca106725 5518 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5519 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
Kojto 122:f9eeca106725 5520 #define DMA_IFCR_CHTIF2_Pos (6U)
Kojto 122:f9eeca106725 5521 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5522 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
Kojto 122:f9eeca106725 5523 #define DMA_IFCR_CTEIF2_Pos (7U)
Kojto 122:f9eeca106725 5524 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5525 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
Kojto 122:f9eeca106725 5526 #define DMA_IFCR_CGIF3_Pos (8U)
Kojto 122:f9eeca106725 5527 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5528 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
Kojto 122:f9eeca106725 5529 #define DMA_IFCR_CTCIF3_Pos (9U)
Kojto 122:f9eeca106725 5530 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5531 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
Kojto 122:f9eeca106725 5532 #define DMA_IFCR_CHTIF3_Pos (10U)
Kojto 122:f9eeca106725 5533 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5534 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
Kojto 122:f9eeca106725 5535 #define DMA_IFCR_CTEIF3_Pos (11U)
Kojto 122:f9eeca106725 5536 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5537 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
Kojto 122:f9eeca106725 5538 #define DMA_IFCR_CGIF4_Pos (12U)
Kojto 122:f9eeca106725 5539 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5540 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
Kojto 122:f9eeca106725 5541 #define DMA_IFCR_CTCIF4_Pos (13U)
Kojto 122:f9eeca106725 5542 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5543 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
Kojto 122:f9eeca106725 5544 #define DMA_IFCR_CHTIF4_Pos (14U)
Kojto 122:f9eeca106725 5545 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5546 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
Kojto 122:f9eeca106725 5547 #define DMA_IFCR_CTEIF4_Pos (15U)
Kojto 122:f9eeca106725 5548 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5549 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
Kojto 122:f9eeca106725 5550 #define DMA_IFCR_CGIF5_Pos (16U)
Kojto 122:f9eeca106725 5551 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5552 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
Kojto 122:f9eeca106725 5553 #define DMA_IFCR_CTCIF5_Pos (17U)
Kojto 122:f9eeca106725 5554 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5555 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
Kojto 122:f9eeca106725 5556 #define DMA_IFCR_CHTIF5_Pos (18U)
Kojto 122:f9eeca106725 5557 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5558 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
Kojto 122:f9eeca106725 5559 #define DMA_IFCR_CTEIF5_Pos (19U)
Kojto 122:f9eeca106725 5560 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5561 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
Kojto 122:f9eeca106725 5562 #define DMA_IFCR_CGIF6_Pos (20U)
Kojto 122:f9eeca106725 5563 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5564 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
Kojto 122:f9eeca106725 5565 #define DMA_IFCR_CTCIF6_Pos (21U)
Kojto 122:f9eeca106725 5566 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5567 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
Kojto 122:f9eeca106725 5568 #define DMA_IFCR_CHTIF6_Pos (22U)
Kojto 122:f9eeca106725 5569 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5570 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
Kojto 122:f9eeca106725 5571 #define DMA_IFCR_CTEIF6_Pos (23U)
Kojto 122:f9eeca106725 5572 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5573 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
Kojto 122:f9eeca106725 5574 #define DMA_IFCR_CGIF7_Pos (24U)
Kojto 122:f9eeca106725 5575 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5576 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
Kojto 122:f9eeca106725 5577 #define DMA_IFCR_CTCIF7_Pos (25U)
Kojto 122:f9eeca106725 5578 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5579 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
Kojto 122:f9eeca106725 5580 #define DMA_IFCR_CHTIF7_Pos (26U)
Kojto 122:f9eeca106725 5581 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5582 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
Kojto 122:f9eeca106725 5583 #define DMA_IFCR_CTEIF7_Pos (27U)
Kojto 122:f9eeca106725 5584 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5585 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
Kojto 90:cb3d968589d8 5586
Kojto 90:cb3d968589d8 5587 /******************* Bit definition for DMA_CCR register ********************/
Kojto 122:f9eeca106725 5588 #define DMA_CCR_EN_Pos (0U)
Kojto 122:f9eeca106725 5589 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5590 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
Kojto 122:f9eeca106725 5591 #define DMA_CCR_TCIE_Pos (1U)
Kojto 122:f9eeca106725 5592 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5593 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 5594 #define DMA_CCR_HTIE_Pos (2U)
Kojto 122:f9eeca106725 5595 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5596 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
Kojto 122:f9eeca106725 5597 #define DMA_CCR_TEIE_Pos (3U)
Kojto 122:f9eeca106725 5598 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5599 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
Kojto 122:f9eeca106725 5600 #define DMA_CCR_DIR_Pos (4U)
Kojto 122:f9eeca106725 5601 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5602 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
Kojto 122:f9eeca106725 5603 #define DMA_CCR_CIRC_Pos (5U)
Kojto 122:f9eeca106725 5604 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5605 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
Kojto 122:f9eeca106725 5606 #define DMA_CCR_PINC_Pos (6U)
Kojto 122:f9eeca106725 5607 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5608 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
Kojto 122:f9eeca106725 5609 #define DMA_CCR_MINC_Pos (7U)
Kojto 122:f9eeca106725 5610 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5611 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
Kojto 122:f9eeca106725 5612
Kojto 122:f9eeca106725 5613 #define DMA_CCR_PSIZE_Pos (8U)
Kojto 122:f9eeca106725 5614 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 5615 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 122:f9eeca106725 5616 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5617 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5618
Kojto 122:f9eeca106725 5619 #define DMA_CCR_MSIZE_Pos (10U)
Kojto 122:f9eeca106725 5620 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 5621 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
Kojto 122:f9eeca106725 5622 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5623 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5624
Kojto 122:f9eeca106725 5625 #define DMA_CCR_PL_Pos (12U)
Kojto 122:f9eeca106725 5626 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 5627 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 122:f9eeca106725 5628 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5629 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5630
Kojto 122:f9eeca106725 5631 #define DMA_CCR_MEM2MEM_Pos (14U)
Kojto 122:f9eeca106725 5632 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5633 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
Kojto 90:cb3d968589d8 5634
Kojto 90:cb3d968589d8 5635 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 122:f9eeca106725 5636 #define DMA_CNDTR_NDT_Pos (0U)
Kojto 122:f9eeca106725 5637 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 5638 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 5639
Kojto 90:cb3d968589d8 5640 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 122:f9eeca106725 5641 #define DMA_CPAR_PA_Pos (0U)
Kojto 122:f9eeca106725 5642 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5643 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
Kojto 90:cb3d968589d8 5644
Kojto 90:cb3d968589d8 5645 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 122:f9eeca106725 5646 #define DMA_CMAR_MA_Pos (0U)
Kojto 122:f9eeca106725 5647 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5648 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
Kojto 90:cb3d968589d8 5649
Kojto 93:e188a91d3eaa 5650 /****************** Bit definition for DMA1_CSELR register ********************/
Kojto 122:f9eeca106725 5651 #define DMA_CSELR_C1S_Pos (0U)
Kojto 122:f9eeca106725 5652 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 5653 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
Kojto 122:f9eeca106725 5654 #define DMA_CSELR_C2S_Pos (4U)
Kojto 122:f9eeca106725 5655 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 5656 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
Kojto 122:f9eeca106725 5657 #define DMA_CSELR_C3S_Pos (8U)
Kojto 122:f9eeca106725 5658 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 5659 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
Kojto 122:f9eeca106725 5660 #define DMA_CSELR_C4S_Pos (12U)
Kojto 122:f9eeca106725 5661 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 5662 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
Kojto 122:f9eeca106725 5663 #define DMA_CSELR_C5S_Pos (16U)
Kojto 122:f9eeca106725 5664 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 5665 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
Kojto 122:f9eeca106725 5666 #define DMA_CSELR_C6S_Pos (20U)
Kojto 122:f9eeca106725 5667 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 5668 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
Kojto 122:f9eeca106725 5669 #define DMA_CSELR_C7S_Pos (24U)
Kojto 122:f9eeca106725 5670 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 5671 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
Kojto 122:f9eeca106725 5672
Kojto 122:f9eeca106725 5673 #define DMA1_CSELR_DEFAULT (0x00000000U) /*!< Default remap position for DMA1 */
Kojto 122:f9eeca106725 5674 #define DMA1_CSELR_CH1_ADC_Pos (0U)
Kojto 122:f9eeca106725 5675 #define DMA1_CSELR_CH1_ADC_Msk (0x1U << DMA1_CSELR_CH1_ADC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5676 #define DMA1_CSELR_CH1_ADC DMA1_CSELR_CH1_ADC_Msk /*!< Remap ADC on DMA1 Channel 1*/
Kojto 122:f9eeca106725 5677 #define DMA1_CSELR_CH1_TIM17_CH1_Pos (0U)
Kojto 122:f9eeca106725 5678 #define DMA1_CSELR_CH1_TIM17_CH1_Msk (0x7U << DMA1_CSELR_CH1_TIM17_CH1_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 5679 #define DMA1_CSELR_CH1_TIM17_CH1 DMA1_CSELR_CH1_TIM17_CH1_Msk /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
Kojto 122:f9eeca106725 5680 #define DMA1_CSELR_CH1_TIM17_UP_Pos (0U)
Kojto 122:f9eeca106725 5681 #define DMA1_CSELR_CH1_TIM17_UP_Msk (0x7U << DMA1_CSELR_CH1_TIM17_UP_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 5682 #define DMA1_CSELR_CH1_TIM17_UP DMA1_CSELR_CH1_TIM17_UP_Msk /*!< Remap TIM17 up on DMA1 channel 1 */
Kojto 122:f9eeca106725 5683 #define DMA1_CSELR_CH1_USART1_RX_Pos (3U)
Kojto 122:f9eeca106725 5684 #define DMA1_CSELR_CH1_USART1_RX_Msk (0x1U << DMA1_CSELR_CH1_USART1_RX_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5685 #define DMA1_CSELR_CH1_USART1_RX DMA1_CSELR_CH1_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5686 #define DMA1_CSELR_CH1_USART2_RX_Pos (0U)
Kojto 122:f9eeca106725 5687 #define DMA1_CSELR_CH1_USART2_RX_Msk (0x9U << DMA1_CSELR_CH1_USART2_RX_Pos) /*!< 0x00000009 */
Kojto 122:f9eeca106725 5688 #define DMA1_CSELR_CH1_USART2_RX DMA1_CSELR_CH1_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5689 #define DMA1_CSELR_CH1_USART3_RX_Pos (1U)
Kojto 122:f9eeca106725 5690 #define DMA1_CSELR_CH1_USART3_RX_Msk (0x5U << DMA1_CSELR_CH1_USART3_RX_Pos) /*!< 0x0000000A */
Kojto 122:f9eeca106725 5691 #define DMA1_CSELR_CH1_USART3_RX DMA1_CSELR_CH1_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5692 #define DMA1_CSELR_CH1_USART4_RX_Pos (0U)
Kojto 122:f9eeca106725 5693 #define DMA1_CSELR_CH1_USART4_RX_Msk (0xBU << DMA1_CSELR_CH1_USART4_RX_Pos) /*!< 0x0000000B */
Kojto 122:f9eeca106725 5694 #define DMA1_CSELR_CH1_USART4_RX DMA1_CSELR_CH1_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5695 #define DMA1_CSELR_CH1_USART5_RX_Pos (2U)
Kojto 122:f9eeca106725 5696 #define DMA1_CSELR_CH1_USART5_RX_Msk (0x3U << DMA1_CSELR_CH1_USART5_RX_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 5697 #define DMA1_CSELR_CH1_USART5_RX DMA1_CSELR_CH1_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5698 #define DMA1_CSELR_CH1_USART6_RX_Pos (0U)
Kojto 122:f9eeca106725 5699 #define DMA1_CSELR_CH1_USART6_RX_Msk (0xDU << DMA1_CSELR_CH1_USART6_RX_Pos) /*!< 0x0000000D */
Kojto 122:f9eeca106725 5700 #define DMA1_CSELR_CH1_USART6_RX DMA1_CSELR_CH1_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5701 #define DMA1_CSELR_CH1_USART7_RX_Pos (1U)
Kojto 122:f9eeca106725 5702 #define DMA1_CSELR_CH1_USART7_RX_Msk (0x7U << DMA1_CSELR_CH1_USART7_RX_Pos) /*!< 0x0000000E */
Kojto 122:f9eeca106725 5703 #define DMA1_CSELR_CH1_USART7_RX DMA1_CSELR_CH1_USART7_RX_Msk /*!< Remap USART7 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5704 #define DMA1_CSELR_CH1_USART8_RX_Pos (0U)
Kojto 122:f9eeca106725 5705 #define DMA1_CSELR_CH1_USART8_RX_Msk (0xFU << DMA1_CSELR_CH1_USART8_RX_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 5706 #define DMA1_CSELR_CH1_USART8_RX DMA1_CSELR_CH1_USART8_RX_Msk /*!< Remap USART8 Rx on DMA1 channel 1 */
Kojto 122:f9eeca106725 5707 #define DMA1_CSELR_CH2_ADC_Pos (4U)
Kojto 122:f9eeca106725 5708 #define DMA1_CSELR_CH2_ADC_Msk (0x1U << DMA1_CSELR_CH2_ADC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5709 #define DMA1_CSELR_CH2_ADC DMA1_CSELR_CH2_ADC_Msk /*!< Remap ADC on DMA1 channel 2 */
Kojto 122:f9eeca106725 5710 #define DMA1_CSELR_CH2_I2C1_TX_Pos (5U)
Kojto 122:f9eeca106725 5711 #define DMA1_CSELR_CH2_I2C1_TX_Msk (0x1U << DMA1_CSELR_CH2_I2C1_TX_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5712 #define DMA1_CSELR_CH2_I2C1_TX DMA1_CSELR_CH2_I2C1_TX_Msk /*!< Remap I2C1 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5713 #define DMA1_CSELR_CH2_SPI1_RX_Pos (4U)
Kojto 122:f9eeca106725 5714 #define DMA1_CSELR_CH2_SPI1_RX_Msk (0x3U << DMA1_CSELR_CH2_SPI1_RX_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 5715 #define DMA1_CSELR_CH2_SPI1_RX DMA1_CSELR_CH2_SPI1_RX_Msk /*!< Remap SPI1 Rx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5716 #define DMA1_CSELR_CH2_TIM1_CH1_Pos (6U)
Kojto 122:f9eeca106725 5717 #define DMA1_CSELR_CH2_TIM1_CH1_Msk (0x1U << DMA1_CSELR_CH2_TIM1_CH1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5718 #define DMA1_CSELR_CH2_TIM1_CH1 DMA1_CSELR_CH2_TIM1_CH1_Msk /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
Kojto 122:f9eeca106725 5719 #define DMA1_CSELR_CH2_TIM17_CH1_Pos (4U)
Kojto 122:f9eeca106725 5720 #define DMA1_CSELR_CH2_TIM17_CH1_Msk (0x7U << DMA1_CSELR_CH2_TIM17_CH1_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 5721 #define DMA1_CSELR_CH2_TIM17_CH1 DMA1_CSELR_CH2_TIM17_CH1_Msk /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
Kojto 122:f9eeca106725 5722 #define DMA1_CSELR_CH2_TIM17_UP_Pos (4U)
Kojto 122:f9eeca106725 5723 #define DMA1_CSELR_CH2_TIM17_UP_Msk (0x7U << DMA1_CSELR_CH2_TIM17_UP_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 5724 #define DMA1_CSELR_CH2_TIM17_UP DMA1_CSELR_CH2_TIM17_UP_Msk /*!< Remap TIM17 up on DMA1 channel 2 */
Kojto 122:f9eeca106725 5725 #define DMA1_CSELR_CH2_USART1_TX_Pos (7U)
Kojto 122:f9eeca106725 5726 #define DMA1_CSELR_CH2_USART1_TX_Msk (0x1U << DMA1_CSELR_CH2_USART1_TX_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5727 #define DMA1_CSELR_CH2_USART1_TX DMA1_CSELR_CH2_USART1_TX_Msk /*!< Remap USART1 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5728 #define DMA1_CSELR_CH2_USART2_TX_Pos (4U)
Kojto 122:f9eeca106725 5729 #define DMA1_CSELR_CH2_USART2_TX_Msk (0x9U << DMA1_CSELR_CH2_USART2_TX_Pos) /*!< 0x00000090 */
Kojto 122:f9eeca106725 5730 #define DMA1_CSELR_CH2_USART2_TX DMA1_CSELR_CH2_USART2_TX_Msk /*!< Remap USART2 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5731 #define DMA1_CSELR_CH2_USART3_TX_Pos (5U)
Kojto 122:f9eeca106725 5732 #define DMA1_CSELR_CH2_USART3_TX_Msk (0x5U << DMA1_CSELR_CH2_USART3_TX_Pos) /*!< 0x000000A0 */
Kojto 122:f9eeca106725 5733 #define DMA1_CSELR_CH2_USART3_TX DMA1_CSELR_CH2_USART3_TX_Msk /*!< Remap USART3 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5734 #define DMA1_CSELR_CH2_USART4_TX_Pos (4U)
Kojto 122:f9eeca106725 5735 #define DMA1_CSELR_CH2_USART4_TX_Msk (0xBU << DMA1_CSELR_CH2_USART4_TX_Pos) /*!< 0x000000B0 */
Kojto 122:f9eeca106725 5736 #define DMA1_CSELR_CH2_USART4_TX DMA1_CSELR_CH2_USART4_TX_Msk /*!< Remap USART4 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5737 #define DMA1_CSELR_CH2_USART5_TX_Pos (6U)
Kojto 122:f9eeca106725 5738 #define DMA1_CSELR_CH2_USART5_TX_Msk (0x3U << DMA1_CSELR_CH2_USART5_TX_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 5739 #define DMA1_CSELR_CH2_USART5_TX DMA1_CSELR_CH2_USART5_TX_Msk /*!< Remap USART5 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5740 #define DMA1_CSELR_CH2_USART6_TX_Pos (4U)
Kojto 122:f9eeca106725 5741 #define DMA1_CSELR_CH2_USART6_TX_Msk (0xDU << DMA1_CSELR_CH2_USART6_TX_Pos) /*!< 0x000000D0 */
Kojto 122:f9eeca106725 5742 #define DMA1_CSELR_CH2_USART6_TX DMA1_CSELR_CH2_USART6_TX_Msk /*!< Remap USART6 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5743 #define DMA1_CSELR_CH2_USART7_TX_Pos (5U)
Kojto 122:f9eeca106725 5744 #define DMA1_CSELR_CH2_USART7_TX_Msk (0x7U << DMA1_CSELR_CH2_USART7_TX_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 5745 #define DMA1_CSELR_CH2_USART7_TX DMA1_CSELR_CH2_USART7_TX_Msk /*!< Remap USART7 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5746 #define DMA1_CSELR_CH2_USART8_TX_Pos (4U)
Kojto 122:f9eeca106725 5747 #define DMA1_CSELR_CH2_USART8_TX_Msk (0xFU << DMA1_CSELR_CH2_USART8_TX_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 5748 #define DMA1_CSELR_CH2_USART8_TX DMA1_CSELR_CH2_USART8_TX_Msk /*!< Remap USART8 Tx on DMA1 channel 2 */
Kojto 122:f9eeca106725 5749 #define DMA1_CSELR_CH3_TIM6_UP_Pos (8U)
Kojto 122:f9eeca106725 5750 #define DMA1_CSELR_CH3_TIM6_UP_Msk (0x1U << DMA1_CSELR_CH3_TIM6_UP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5751 #define DMA1_CSELR_CH3_TIM6_UP DMA1_CSELR_CH3_TIM6_UP_Msk /*!< Remap TIM6 up on DMA1 channel 3 */
Kojto 122:f9eeca106725 5752 #define DMA1_CSELR_CH3_DAC_CH1_Pos (8U)
Kojto 122:f9eeca106725 5753 #define DMA1_CSELR_CH3_DAC_CH1_Msk (0x1U << DMA1_CSELR_CH3_DAC_CH1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5754 #define DMA1_CSELR_CH3_DAC_CH1 DMA1_CSELR_CH3_DAC_CH1_Msk /*!< Remap DAC Channel 1on DMA1 channel 3 */
Kojto 122:f9eeca106725 5755 #define DMA1_CSELR_CH3_I2C1_RX_Pos (9U)
Kojto 122:f9eeca106725 5756 #define DMA1_CSELR_CH3_I2C1_RX_Msk (0x1U << DMA1_CSELR_CH3_I2C1_RX_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5757 #define DMA1_CSELR_CH3_I2C1_RX DMA1_CSELR_CH3_I2C1_RX_Msk /*!< Remap I2C1 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5758 #define DMA1_CSELR_CH3_SPI1_TX_Pos (8U)
Kojto 122:f9eeca106725 5759 #define DMA1_CSELR_CH3_SPI1_TX_Msk (0x3U << DMA1_CSELR_CH3_SPI1_TX_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 5760 #define DMA1_CSELR_CH3_SPI1_TX DMA1_CSELR_CH3_SPI1_TX_Msk /*!< Remap SPI1 Tx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5761 #define DMA1_CSELR_CH3_TIM1_CH2_Pos (10U)
Kojto 122:f9eeca106725 5762 #define DMA1_CSELR_CH3_TIM1_CH2_Msk (0x1U << DMA1_CSELR_CH3_TIM1_CH2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5763 #define DMA1_CSELR_CH3_TIM1_CH2 DMA1_CSELR_CH3_TIM1_CH2_Msk /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
Kojto 122:f9eeca106725 5764 #define DMA1_CSELR_CH3_TIM2_CH2_Pos (8U)
Kojto 122:f9eeca106725 5765 #define DMA1_CSELR_CH3_TIM2_CH2_Msk (0x5U << DMA1_CSELR_CH3_TIM2_CH2_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 5766 #define DMA1_CSELR_CH3_TIM2_CH2 DMA1_CSELR_CH3_TIM2_CH2_Msk /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
Kojto 122:f9eeca106725 5767 #define DMA1_CSELR_CH3_TIM16_CH1_Pos (8U)
Kojto 122:f9eeca106725 5768 #define DMA1_CSELR_CH3_TIM16_CH1_Msk (0x7U << DMA1_CSELR_CH3_TIM16_CH1_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 5769 #define DMA1_CSELR_CH3_TIM16_CH1 DMA1_CSELR_CH3_TIM16_CH1_Msk /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
Kojto 122:f9eeca106725 5770 #define DMA1_CSELR_CH3_TIM16_UP_Pos (8U)
Kojto 122:f9eeca106725 5771 #define DMA1_CSELR_CH3_TIM16_UP_Msk (0x7U << DMA1_CSELR_CH3_TIM16_UP_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 5772 #define DMA1_CSELR_CH3_TIM16_UP DMA1_CSELR_CH3_TIM16_UP_Msk /*!< Remap TIM16 up on DMA1 channel 3 */
Kojto 122:f9eeca106725 5773 #define DMA1_CSELR_CH3_USART1_RX_Pos (11U)
Kojto 122:f9eeca106725 5774 #define DMA1_CSELR_CH3_USART1_RX_Msk (0x1U << DMA1_CSELR_CH3_USART1_RX_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5775 #define DMA1_CSELR_CH3_USART1_RX DMA1_CSELR_CH3_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5776 #define DMA1_CSELR_CH3_USART2_RX_Pos (8U)
Kojto 122:f9eeca106725 5777 #define DMA1_CSELR_CH3_USART2_RX_Msk (0x9U << DMA1_CSELR_CH3_USART2_RX_Pos) /*!< 0x00000900 */
Kojto 122:f9eeca106725 5778 #define DMA1_CSELR_CH3_USART2_RX DMA1_CSELR_CH3_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5779 #define DMA1_CSELR_CH3_USART3_RX_Pos (9U)
Kojto 122:f9eeca106725 5780 #define DMA1_CSELR_CH3_USART3_RX_Msk (0x5U << DMA1_CSELR_CH3_USART3_RX_Pos) /*!< 0x00000A00 */
Kojto 122:f9eeca106725 5781 #define DMA1_CSELR_CH3_USART3_RX DMA1_CSELR_CH3_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5782 #define DMA1_CSELR_CH3_USART4_RX_Pos (8U)
Kojto 122:f9eeca106725 5783 #define DMA1_CSELR_CH3_USART4_RX_Msk (0xBU << DMA1_CSELR_CH3_USART4_RX_Pos) /*!< 0x00000B00 */
Kojto 122:f9eeca106725 5784 #define DMA1_CSELR_CH3_USART4_RX DMA1_CSELR_CH3_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5785 #define DMA1_CSELR_CH3_USART5_RX_Pos (10U)
Kojto 122:f9eeca106725 5786 #define DMA1_CSELR_CH3_USART5_RX_Msk (0x3U << DMA1_CSELR_CH3_USART5_RX_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 5787 #define DMA1_CSELR_CH3_USART5_RX DMA1_CSELR_CH3_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5788 #define DMA1_CSELR_CH3_USART6_RX_Pos (8U)
Kojto 122:f9eeca106725 5789 #define DMA1_CSELR_CH3_USART6_RX_Msk (0xDU << DMA1_CSELR_CH3_USART6_RX_Pos) /*!< 0x00000D00 */
Kojto 122:f9eeca106725 5790 #define DMA1_CSELR_CH3_USART6_RX DMA1_CSELR_CH3_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5791 #define DMA1_CSELR_CH3_USART7_RX_Pos (9U)
Kojto 122:f9eeca106725 5792 #define DMA1_CSELR_CH3_USART7_RX_Msk (0x7U << DMA1_CSELR_CH3_USART7_RX_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 5793 #define DMA1_CSELR_CH3_USART7_RX DMA1_CSELR_CH3_USART7_RX_Msk /*!< Remap USART7 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5794 #define DMA1_CSELR_CH3_USART8_RX_Pos (8U)
Kojto 122:f9eeca106725 5795 #define DMA1_CSELR_CH3_USART8_RX_Msk (0xFU << DMA1_CSELR_CH3_USART8_RX_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 5796 #define DMA1_CSELR_CH3_USART8_RX DMA1_CSELR_CH3_USART8_RX_Msk /*!< Remap USART8 Rx on DMA1 channel 3 */
Kojto 122:f9eeca106725 5797 #define DMA1_CSELR_CH4_TIM7_UP_Pos (12U)
Kojto 122:f9eeca106725 5798 #define DMA1_CSELR_CH4_TIM7_UP_Msk (0x1U << DMA1_CSELR_CH4_TIM7_UP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5799 #define DMA1_CSELR_CH4_TIM7_UP DMA1_CSELR_CH4_TIM7_UP_Msk /*!< Remap TIM7 up on DMA1 channel 4 */
Kojto 122:f9eeca106725 5800 #define DMA1_CSELR_CH4_DAC_CH2_Pos (12U)
Kojto 122:f9eeca106725 5801 #define DMA1_CSELR_CH4_DAC_CH2_Msk (0x1U << DMA1_CSELR_CH4_DAC_CH2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5802 #define DMA1_CSELR_CH4_DAC_CH2 DMA1_CSELR_CH4_DAC_CH2_Msk /*!< Remap DAC Channel 2 on DMA1 channel 4 */
Kojto 122:f9eeca106725 5803 #define DMA1_CSELR_CH4_I2C2_TX_Pos (13U)
Kojto 122:f9eeca106725 5804 #define DMA1_CSELR_CH4_I2C2_TX_Msk (0x1U << DMA1_CSELR_CH4_I2C2_TX_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5805 #define DMA1_CSELR_CH4_I2C2_TX DMA1_CSELR_CH4_I2C2_TX_Msk /*!< Remap I2C2 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5806 #define DMA1_CSELR_CH4_SPI2_RX_Pos (12U)
Kojto 122:f9eeca106725 5807 #define DMA1_CSELR_CH4_SPI2_RX_Msk (0x3U << DMA1_CSELR_CH4_SPI2_RX_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 5808 #define DMA1_CSELR_CH4_SPI2_RX DMA1_CSELR_CH4_SPI2_RX_Msk /*!< Remap SPI2 Rx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5809 #define DMA1_CSELR_CH4_TIM2_CH4_Pos (12U)
Kojto 122:f9eeca106725 5810 #define DMA1_CSELR_CH4_TIM2_CH4_Msk (0x5U << DMA1_CSELR_CH4_TIM2_CH4_Pos) /*!< 0x00005000 */
Kojto 122:f9eeca106725 5811 #define DMA1_CSELR_CH4_TIM2_CH4 DMA1_CSELR_CH4_TIM2_CH4_Msk /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
Kojto 122:f9eeca106725 5812 #define DMA1_CSELR_CH4_TIM3_CH1_Pos (13U)
Kojto 122:f9eeca106725 5813 #define DMA1_CSELR_CH4_TIM3_CH1_Msk (0x3U << DMA1_CSELR_CH4_TIM3_CH1_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 5814 #define DMA1_CSELR_CH4_TIM3_CH1 DMA1_CSELR_CH4_TIM3_CH1_Msk /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
Kojto 122:f9eeca106725 5815 #define DMA1_CSELR_CH4_TIM3_TRIG_Pos (13U)
Kojto 122:f9eeca106725 5816 #define DMA1_CSELR_CH4_TIM3_TRIG_Msk (0x3U << DMA1_CSELR_CH4_TIM3_TRIG_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 5817 #define DMA1_CSELR_CH4_TIM3_TRIG DMA1_CSELR_CH4_TIM3_TRIG_Msk /*!< Remap TIM3 Trig on DMA1 channel 4 */
Kojto 122:f9eeca106725 5818 #define DMA1_CSELR_CH4_TIM16_CH1_Pos (12U)
Kojto 122:f9eeca106725 5819 #define DMA1_CSELR_CH4_TIM16_CH1_Msk (0x7U << DMA1_CSELR_CH4_TIM16_CH1_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 5820 #define DMA1_CSELR_CH4_TIM16_CH1 DMA1_CSELR_CH4_TIM16_CH1_Msk /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
Kojto 122:f9eeca106725 5821 #define DMA1_CSELR_CH4_TIM16_UP_Pos (12U)
Kojto 122:f9eeca106725 5822 #define DMA1_CSELR_CH4_TIM16_UP_Msk (0x7U << DMA1_CSELR_CH4_TIM16_UP_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 5823 #define DMA1_CSELR_CH4_TIM16_UP DMA1_CSELR_CH4_TIM16_UP_Msk /*!< Remap TIM16 up on DMA1 channel 4 */
Kojto 122:f9eeca106725 5824 #define DMA1_CSELR_CH4_USART1_TX_Pos (15U)
Kojto 122:f9eeca106725 5825 #define DMA1_CSELR_CH4_USART1_TX_Msk (0x1U << DMA1_CSELR_CH4_USART1_TX_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5826 #define DMA1_CSELR_CH4_USART1_TX DMA1_CSELR_CH4_USART1_TX_Msk /*!< Remap USART1 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5827 #define DMA1_CSELR_CH4_USART2_TX_Pos (12U)
Kojto 122:f9eeca106725 5828 #define DMA1_CSELR_CH4_USART2_TX_Msk (0x9U << DMA1_CSELR_CH4_USART2_TX_Pos) /*!< 0x00009000 */
Kojto 122:f9eeca106725 5829 #define DMA1_CSELR_CH4_USART2_TX DMA1_CSELR_CH4_USART2_TX_Msk /*!< Remap USART2 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5830 #define DMA1_CSELR_CH4_USART3_TX_Pos (13U)
Kojto 122:f9eeca106725 5831 #define DMA1_CSELR_CH4_USART3_TX_Msk (0x5U << DMA1_CSELR_CH4_USART3_TX_Pos) /*!< 0x0000A000 */
Kojto 122:f9eeca106725 5832 #define DMA1_CSELR_CH4_USART3_TX DMA1_CSELR_CH4_USART3_TX_Msk /*!< Remap USART3 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5833 #define DMA1_CSELR_CH4_USART4_TX_Pos (12U)
Kojto 122:f9eeca106725 5834 #define DMA1_CSELR_CH4_USART4_TX_Msk (0xBU << DMA1_CSELR_CH4_USART4_TX_Pos) /*!< 0x0000B000 */
Kojto 122:f9eeca106725 5835 #define DMA1_CSELR_CH4_USART4_TX DMA1_CSELR_CH4_USART4_TX_Msk /*!< Remap USART4 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5836 #define DMA1_CSELR_CH4_USART5_TX_Pos (14U)
Kojto 122:f9eeca106725 5837 #define DMA1_CSELR_CH4_USART5_TX_Msk (0x3U << DMA1_CSELR_CH4_USART5_TX_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 5838 #define DMA1_CSELR_CH4_USART5_TX DMA1_CSELR_CH4_USART5_TX_Msk /*!< Remap USART5 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5839 #define DMA1_CSELR_CH4_USART6_TX_Pos (12U)
Kojto 122:f9eeca106725 5840 #define DMA1_CSELR_CH4_USART6_TX_Msk (0xDU << DMA1_CSELR_CH4_USART6_TX_Pos) /*!< 0x0000D000 */
Kojto 122:f9eeca106725 5841 #define DMA1_CSELR_CH4_USART6_TX DMA1_CSELR_CH4_USART6_TX_Msk /*!< Remap USART6 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5842 #define DMA1_CSELR_CH4_USART7_TX_Pos (13U)
Kojto 122:f9eeca106725 5843 #define DMA1_CSELR_CH4_USART7_TX_Msk (0x7U << DMA1_CSELR_CH4_USART7_TX_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 5844 #define DMA1_CSELR_CH4_USART7_TX DMA1_CSELR_CH4_USART7_TX_Msk /*!< Remap USART7 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5845 #define DMA1_CSELR_CH4_USART8_TX_Pos (12U)
Kojto 122:f9eeca106725 5846 #define DMA1_CSELR_CH4_USART8_TX_Msk (0xFU << DMA1_CSELR_CH4_USART8_TX_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 5847 #define DMA1_CSELR_CH4_USART8_TX DMA1_CSELR_CH4_USART8_TX_Msk /*!< Remap USART8 Tx on DMA1 channel 4 */
Kojto 122:f9eeca106725 5848 #define DMA1_CSELR_CH5_I2C2_RX_Pos (17U)
Kojto 122:f9eeca106725 5849 #define DMA1_CSELR_CH5_I2C2_RX_Msk (0x1U << DMA1_CSELR_CH5_I2C2_RX_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5850 #define DMA1_CSELR_CH5_I2C2_RX DMA1_CSELR_CH5_I2C2_RX_Msk /*!< Remap I2C2 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5851 #define DMA1_CSELR_CH5_SPI2_TX_Pos (16U)
Kojto 122:f9eeca106725 5852 #define DMA1_CSELR_CH5_SPI2_TX_Msk (0x3U << DMA1_CSELR_CH5_SPI2_TX_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 5853 #define DMA1_CSELR_CH5_SPI2_TX DMA1_CSELR_CH5_SPI2_TX_Msk /*!< Remap SPI1 Tx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5854 #define DMA1_CSELR_CH5_TIM1_CH3_Pos (18U)
Kojto 122:f9eeca106725 5855 #define DMA1_CSELR_CH5_TIM1_CH3_Msk (0x1U << DMA1_CSELR_CH5_TIM1_CH3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5856 #define DMA1_CSELR_CH5_TIM1_CH3 DMA1_CSELR_CH5_TIM1_CH3_Msk /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
Kojto 122:f9eeca106725 5857 #define DMA1_CSELR_CH5_USART1_RX_Pos (19U)
Kojto 122:f9eeca106725 5858 #define DMA1_CSELR_CH5_USART1_RX_Msk (0x1U << DMA1_CSELR_CH5_USART1_RX_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5859 #define DMA1_CSELR_CH5_USART1_RX DMA1_CSELR_CH5_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5860 #define DMA1_CSELR_CH5_USART2_RX_Pos (16U)
Kojto 122:f9eeca106725 5861 #define DMA1_CSELR_CH5_USART2_RX_Msk (0x9U << DMA1_CSELR_CH5_USART2_RX_Pos) /*!< 0x00090000 */
Kojto 122:f9eeca106725 5862 #define DMA1_CSELR_CH5_USART2_RX DMA1_CSELR_CH5_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5863 #define DMA1_CSELR_CH5_USART3_RX_Pos (17U)
Kojto 122:f9eeca106725 5864 #define DMA1_CSELR_CH5_USART3_RX_Msk (0x5U << DMA1_CSELR_CH5_USART3_RX_Pos) /*!< 0x000A0000 */
Kojto 122:f9eeca106725 5865 #define DMA1_CSELR_CH5_USART3_RX DMA1_CSELR_CH5_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5866 #define DMA1_CSELR_CH5_USART4_RX_Pos (16U)
Kojto 122:f9eeca106725 5867 #define DMA1_CSELR_CH5_USART4_RX_Msk (0xBU << DMA1_CSELR_CH5_USART4_RX_Pos) /*!< 0x000B0000 */
Kojto 122:f9eeca106725 5868 #define DMA1_CSELR_CH5_USART4_RX DMA1_CSELR_CH5_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5869 #define DMA1_CSELR_CH5_USART5_RX_Pos (18U)
Kojto 122:f9eeca106725 5870 #define DMA1_CSELR_CH5_USART5_RX_Msk (0x3U << DMA1_CSELR_CH5_USART5_RX_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 5871 #define DMA1_CSELR_CH5_USART5_RX DMA1_CSELR_CH5_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5872 #define DMA1_CSELR_CH5_USART6_RX_Pos (16U)
Kojto 122:f9eeca106725 5873 #define DMA1_CSELR_CH5_USART6_RX_Msk (0xDU << DMA1_CSELR_CH5_USART6_RX_Pos) /*!< 0x000D0000 */
Kojto 122:f9eeca106725 5874 #define DMA1_CSELR_CH5_USART6_RX DMA1_CSELR_CH5_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5875 #define DMA1_CSELR_CH5_USART7_RX_Pos (17U)
Kojto 122:f9eeca106725 5876 #define DMA1_CSELR_CH5_USART7_RX_Msk (0x7U << DMA1_CSELR_CH5_USART7_RX_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 5877 #define DMA1_CSELR_CH5_USART7_RX DMA1_CSELR_CH5_USART7_RX_Msk /*!< Remap USART7 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5878 #define DMA1_CSELR_CH5_USART8_RX_Pos (16U)
Kojto 122:f9eeca106725 5879 #define DMA1_CSELR_CH5_USART8_RX_Msk (0xFU << DMA1_CSELR_CH5_USART8_RX_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 5880 #define DMA1_CSELR_CH5_USART8_RX DMA1_CSELR_CH5_USART8_RX_Msk /*!< Remap USART8 Rx on DMA1 channel 5 */
Kojto 122:f9eeca106725 5881 #define DMA1_CSELR_CH6_I2C1_TX_Pos (21U)
Kojto 122:f9eeca106725 5882 #define DMA1_CSELR_CH6_I2C1_TX_Msk (0x1U << DMA1_CSELR_CH6_I2C1_TX_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5883 #define DMA1_CSELR_CH6_I2C1_TX DMA1_CSELR_CH6_I2C1_TX_Msk /*!< Remap I2C1 Tx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5884 #define DMA1_CSELR_CH6_SPI2_RX_Pos (20U)
Kojto 122:f9eeca106725 5885 #define DMA1_CSELR_CH6_SPI2_RX_Msk (0x3U << DMA1_CSELR_CH6_SPI2_RX_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 5886 #define DMA1_CSELR_CH6_SPI2_RX DMA1_CSELR_CH6_SPI2_RX_Msk /*!< Remap SPI2 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5887 #define DMA1_CSELR_CH6_TIM1_CH1_Pos (22U)
Kojto 122:f9eeca106725 5888 #define DMA1_CSELR_CH6_TIM1_CH1_Msk (0x1U << DMA1_CSELR_CH6_TIM1_CH1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5889 #define DMA1_CSELR_CH6_TIM1_CH1 DMA1_CSELR_CH6_TIM1_CH1_Msk /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
Kojto 122:f9eeca106725 5890 #define DMA1_CSELR_CH6_TIM1_CH2_Pos (22U)
Kojto 122:f9eeca106725 5891 #define DMA1_CSELR_CH6_TIM1_CH2_Msk (0x1U << DMA1_CSELR_CH6_TIM1_CH2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5892 #define DMA1_CSELR_CH6_TIM1_CH2 DMA1_CSELR_CH6_TIM1_CH2_Msk /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
Kojto 122:f9eeca106725 5893 #define DMA1_CSELR_CH6_TIM1_CH3_Pos (22U)
Kojto 122:f9eeca106725 5894 #define DMA1_CSELR_CH6_TIM1_CH3_Msk (0x1U << DMA1_CSELR_CH6_TIM1_CH3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5895 #define DMA1_CSELR_CH6_TIM1_CH3 DMA1_CSELR_CH6_TIM1_CH3_Msk /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
Kojto 122:f9eeca106725 5896 #define DMA1_CSELR_CH6_TIM3_CH1_Pos (21U)
Kojto 122:f9eeca106725 5897 #define DMA1_CSELR_CH6_TIM3_CH1_Msk (0x3U << DMA1_CSELR_CH6_TIM3_CH1_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 5898 #define DMA1_CSELR_CH6_TIM3_CH1 DMA1_CSELR_CH6_TIM3_CH1_Msk /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
Kojto 122:f9eeca106725 5899 #define DMA1_CSELR_CH6_TIM3_TRIG_Pos (21U)
Kojto 122:f9eeca106725 5900 #define DMA1_CSELR_CH6_TIM3_TRIG_Msk (0x3U << DMA1_CSELR_CH6_TIM3_TRIG_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 5901 #define DMA1_CSELR_CH6_TIM3_TRIG DMA1_CSELR_CH6_TIM3_TRIG_Msk /*!< Remap TIM3 Trig on DMA1 channel 6 */
Kojto 122:f9eeca106725 5902 #define DMA1_CSELR_CH6_TIM16_CH1_Pos (20U)
Kojto 122:f9eeca106725 5903 #define DMA1_CSELR_CH6_TIM16_CH1_Msk (0x7U << DMA1_CSELR_CH6_TIM16_CH1_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 5904 #define DMA1_CSELR_CH6_TIM16_CH1 DMA1_CSELR_CH6_TIM16_CH1_Msk /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
Kojto 122:f9eeca106725 5905 #define DMA1_CSELR_CH6_TIM16_UP_Pos (20U)
Kojto 122:f9eeca106725 5906 #define DMA1_CSELR_CH6_TIM16_UP_Msk (0x7U << DMA1_CSELR_CH6_TIM16_UP_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 5907 #define DMA1_CSELR_CH6_TIM16_UP DMA1_CSELR_CH6_TIM16_UP_Msk /*!< Remap TIM16 up on DMA1 channel 6 */
Kojto 122:f9eeca106725 5908 #define DMA1_CSELR_CH6_USART1_RX_Pos (23U)
Kojto 122:f9eeca106725 5909 #define DMA1_CSELR_CH6_USART1_RX_Msk (0x1U << DMA1_CSELR_CH6_USART1_RX_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5910 #define DMA1_CSELR_CH6_USART1_RX DMA1_CSELR_CH6_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5911 #define DMA1_CSELR_CH6_USART2_RX_Pos (20U)
Kojto 122:f9eeca106725 5912 #define DMA1_CSELR_CH6_USART2_RX_Msk (0x9U << DMA1_CSELR_CH6_USART2_RX_Pos) /*!< 0x00900000 */
Kojto 122:f9eeca106725 5913 #define DMA1_CSELR_CH6_USART2_RX DMA1_CSELR_CH6_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5914 #define DMA1_CSELR_CH6_USART3_RX_Pos (21U)
Kojto 122:f9eeca106725 5915 #define DMA1_CSELR_CH6_USART3_RX_Msk (0x5U << DMA1_CSELR_CH6_USART3_RX_Pos) /*!< 0x00A00000 */
Kojto 122:f9eeca106725 5916 #define DMA1_CSELR_CH6_USART3_RX DMA1_CSELR_CH6_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5917 #define DMA1_CSELR_CH6_USART4_RX_Pos (20U)
Kojto 122:f9eeca106725 5918 #define DMA1_CSELR_CH6_USART4_RX_Msk (0xBU << DMA1_CSELR_CH6_USART4_RX_Pos) /*!< 0x00B00000 */
Kojto 122:f9eeca106725 5919 #define DMA1_CSELR_CH6_USART4_RX DMA1_CSELR_CH6_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5920 #define DMA1_CSELR_CH6_USART5_RX_Pos (22U)
Kojto 122:f9eeca106725 5921 #define DMA1_CSELR_CH6_USART5_RX_Msk (0x3U << DMA1_CSELR_CH6_USART5_RX_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 5922 #define DMA1_CSELR_CH6_USART5_RX DMA1_CSELR_CH6_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5923 #define DMA1_CSELR_CH6_USART6_RX_Pos (20U)
Kojto 122:f9eeca106725 5924 #define DMA1_CSELR_CH6_USART6_RX_Msk (0xDU << DMA1_CSELR_CH6_USART6_RX_Pos) /*!< 0x00D00000 */
Kojto 122:f9eeca106725 5925 #define DMA1_CSELR_CH6_USART6_RX DMA1_CSELR_CH6_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5926 #define DMA1_CSELR_CH6_USART7_RX_Pos (21U)
Kojto 122:f9eeca106725 5927 #define DMA1_CSELR_CH6_USART7_RX_Msk (0x7U << DMA1_CSELR_CH6_USART7_RX_Pos) /*!< 0x00E00000 */
Kojto 122:f9eeca106725 5928 #define DMA1_CSELR_CH6_USART7_RX DMA1_CSELR_CH6_USART7_RX_Msk /*!< Remap USART7 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5929 #define DMA1_CSELR_CH6_USART8_RX_Pos (20U)
Kojto 122:f9eeca106725 5930 #define DMA1_CSELR_CH6_USART8_RX_Msk (0xFU << DMA1_CSELR_CH6_USART8_RX_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 5931 #define DMA1_CSELR_CH6_USART8_RX DMA1_CSELR_CH6_USART8_RX_Msk /*!< Remap USART8 Rx on DMA1 channel 6 */
Kojto 122:f9eeca106725 5932 #define DMA1_CSELR_CH7_I2C1_RX_Pos (25U)
Kojto 122:f9eeca106725 5933 #define DMA1_CSELR_CH7_I2C1_RX_Msk (0x1U << DMA1_CSELR_CH7_I2C1_RX_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5934 #define DMA1_CSELR_CH7_I2C1_RX DMA1_CSELR_CH7_I2C1_RX_Msk /*!< Remap I2C1 Rx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5935 #define DMA1_CSELR_CH7_SPI2_TX_Pos (24U)
Kojto 122:f9eeca106725 5936 #define DMA1_CSELR_CH7_SPI2_TX_Msk (0x3U << DMA1_CSELR_CH7_SPI2_TX_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 5937 #define DMA1_CSELR_CH7_SPI2_TX DMA1_CSELR_CH7_SPI2_TX_Msk /*!< Remap SPI2 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5938 #define DMA1_CSELR_CH7_TIM2_CH2_Pos (24U)
Kojto 122:f9eeca106725 5939 #define DMA1_CSELR_CH7_TIM2_CH2_Msk (0x5U << DMA1_CSELR_CH7_TIM2_CH2_Pos) /*!< 0x05000000 */
Kojto 122:f9eeca106725 5940 #define DMA1_CSELR_CH7_TIM2_CH2 DMA1_CSELR_CH7_TIM2_CH2_Msk /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
Kojto 122:f9eeca106725 5941 #define DMA1_CSELR_CH7_TIM2_CH4_Pos (24U)
Kojto 122:f9eeca106725 5942 #define DMA1_CSELR_CH7_TIM2_CH4_Msk (0x5U << DMA1_CSELR_CH7_TIM2_CH4_Pos) /*!< 0x05000000 */
Kojto 122:f9eeca106725 5943 #define DMA1_CSELR_CH7_TIM2_CH4 DMA1_CSELR_CH7_TIM2_CH4_Msk /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
Kojto 122:f9eeca106725 5944 #define DMA1_CSELR_CH7_TIM17_CH1_Pos (24U)
Kojto 122:f9eeca106725 5945 #define DMA1_CSELR_CH7_TIM17_CH1_Msk (0x7U << DMA1_CSELR_CH7_TIM17_CH1_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 5946 #define DMA1_CSELR_CH7_TIM17_CH1 DMA1_CSELR_CH7_TIM17_CH1_Msk /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
Kojto 122:f9eeca106725 5947 #define DMA1_CSELR_CH7_TIM17_UP_Pos (24U)
Kojto 122:f9eeca106725 5948 #define DMA1_CSELR_CH7_TIM17_UP_Msk (0x7U << DMA1_CSELR_CH7_TIM17_UP_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 5949 #define DMA1_CSELR_CH7_TIM17_UP DMA1_CSELR_CH7_TIM17_UP_Msk /*!< Remap TIM17 up on DMA1 channel 7 */
Kojto 122:f9eeca106725 5950 #define DMA1_CSELR_CH7_USART1_TX_Pos (27U)
Kojto 122:f9eeca106725 5951 #define DMA1_CSELR_CH7_USART1_TX_Msk (0x1U << DMA1_CSELR_CH7_USART1_TX_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5952 #define DMA1_CSELR_CH7_USART1_TX DMA1_CSELR_CH7_USART1_TX_Msk /*!< Remap USART1 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5953 #define DMA1_CSELR_CH7_USART2_TX_Pos (24U)
Kojto 122:f9eeca106725 5954 #define DMA1_CSELR_CH7_USART2_TX_Msk (0x9U << DMA1_CSELR_CH7_USART2_TX_Pos) /*!< 0x09000000 */
Kojto 122:f9eeca106725 5955 #define DMA1_CSELR_CH7_USART2_TX DMA1_CSELR_CH7_USART2_TX_Msk /*!< Remap USART2 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5956 #define DMA1_CSELR_CH7_USART3_TX_Pos (25U)
Kojto 122:f9eeca106725 5957 #define DMA1_CSELR_CH7_USART3_TX_Msk (0x5U << DMA1_CSELR_CH7_USART3_TX_Pos) /*!< 0x0A000000 */
Kojto 122:f9eeca106725 5958 #define DMA1_CSELR_CH7_USART3_TX DMA1_CSELR_CH7_USART3_TX_Msk /*!< Remap USART3 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5959 #define DMA1_CSELR_CH7_USART4_TX_Pos (24U)
Kojto 122:f9eeca106725 5960 #define DMA1_CSELR_CH7_USART4_TX_Msk (0xBU << DMA1_CSELR_CH7_USART4_TX_Pos) /*!< 0x0B000000 */
Kojto 122:f9eeca106725 5961 #define DMA1_CSELR_CH7_USART4_TX DMA1_CSELR_CH7_USART4_TX_Msk /*!< Remap USART4 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5962 #define DMA1_CSELR_CH7_USART5_TX_Pos (26U)
Kojto 122:f9eeca106725 5963 #define DMA1_CSELR_CH7_USART5_TX_Msk (0x3U << DMA1_CSELR_CH7_USART5_TX_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 5964 #define DMA1_CSELR_CH7_USART5_TX DMA1_CSELR_CH7_USART5_TX_Msk /*!< Remap USART5 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5965 #define DMA1_CSELR_CH7_USART6_TX_Pos (24U)
Kojto 122:f9eeca106725 5966 #define DMA1_CSELR_CH7_USART6_TX_Msk (0xDU << DMA1_CSELR_CH7_USART6_TX_Pos) /*!< 0x0D000000 */
Kojto 122:f9eeca106725 5967 #define DMA1_CSELR_CH7_USART6_TX DMA1_CSELR_CH7_USART6_TX_Msk /*!< Remap USART6 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5968 #define DMA1_CSELR_CH7_USART7_TX_Pos (25U)
Kojto 122:f9eeca106725 5969 #define DMA1_CSELR_CH7_USART7_TX_Msk (0x7U << DMA1_CSELR_CH7_USART7_TX_Pos) /*!< 0x0E000000 */
Kojto 122:f9eeca106725 5970 #define DMA1_CSELR_CH7_USART7_TX DMA1_CSELR_CH7_USART7_TX_Msk /*!< Remap USART7 Tx on DMA1 channel 7 */
Kojto 122:f9eeca106725 5971 #define DMA1_CSELR_CH7_USART8_TX_Pos (24U)
Kojto 122:f9eeca106725 5972 #define DMA1_CSELR_CH7_USART8_TX_Msk (0xFU << DMA1_CSELR_CH7_USART8_TX_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 5973 #define DMA1_CSELR_CH7_USART8_TX DMA1_CSELR_CH7_USART8_TX_Msk /*!< Remap USART8 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 5974
Kojto 93:e188a91d3eaa 5975 /****************** Bit definition for DMA2_CSELR register ********************/
Kojto 122:f9eeca106725 5976 #define DMA2_CSELR_DEFAULT (0x00000000U) /*!< Default remap position for DMA2 */
Kojto 122:f9eeca106725 5977 #define DMA2_CSELR_CH1_I2C2_TX_Pos (1U)
Kojto 122:f9eeca106725 5978 #define DMA2_CSELR_CH1_I2C2_TX_Msk (0x1U << DMA2_CSELR_CH1_I2C2_TX_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5979 #define DMA2_CSELR_CH1_I2C2_TX DMA2_CSELR_CH1_I2C2_TX_Msk /*!< Remap I2C2 TX on DMA2 channel 1 */
Kojto 122:f9eeca106725 5980 #define DMA2_CSELR_CH1_USART1_TX_Pos (3U)
Kojto 122:f9eeca106725 5981 #define DMA2_CSELR_CH1_USART1_TX_Msk (0x1U << DMA2_CSELR_CH1_USART1_TX_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5982 #define DMA2_CSELR_CH1_USART1_TX DMA2_CSELR_CH1_USART1_TX_Msk /*!< Remap USART1 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5983 #define DMA2_CSELR_CH1_USART2_TX_Pos (0U)
Kojto 122:f9eeca106725 5984 #define DMA2_CSELR_CH1_USART2_TX_Msk (0x9U << DMA2_CSELR_CH1_USART2_TX_Pos) /*!< 0x00000009 */
Kojto 122:f9eeca106725 5985 #define DMA2_CSELR_CH1_USART2_TX DMA2_CSELR_CH1_USART2_TX_Msk /*!< Remap USART2 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5986 #define DMA2_CSELR_CH1_USART3_TX_Pos (1U)
Kojto 122:f9eeca106725 5987 #define DMA2_CSELR_CH1_USART3_TX_Msk (0x5U << DMA2_CSELR_CH1_USART3_TX_Pos) /*!< 0x0000000A */
Kojto 122:f9eeca106725 5988 #define DMA2_CSELR_CH1_USART3_TX DMA2_CSELR_CH1_USART3_TX_Msk /*!< Remap USART3 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5989 #define DMA2_CSELR_CH1_USART4_TX_Pos (0U)
Kojto 122:f9eeca106725 5990 #define DMA2_CSELR_CH1_USART4_TX_Msk (0xBU << DMA2_CSELR_CH1_USART4_TX_Pos) /*!< 0x0000000B */
Kojto 122:f9eeca106725 5991 #define DMA2_CSELR_CH1_USART4_TX DMA2_CSELR_CH1_USART4_TX_Msk /*!< Remap USART4 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5992 #define DMA2_CSELR_CH1_USART5_TX_Pos (2U)
Kojto 122:f9eeca106725 5993 #define DMA2_CSELR_CH1_USART5_TX_Msk (0x3U << DMA2_CSELR_CH1_USART5_TX_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 5994 #define DMA2_CSELR_CH1_USART5_TX DMA2_CSELR_CH1_USART5_TX_Msk /*!< Remap USART5 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5995 #define DMA2_CSELR_CH1_USART6_TX_Pos (0U)
Kojto 122:f9eeca106725 5996 #define DMA2_CSELR_CH1_USART6_TX_Msk (0xDU << DMA2_CSELR_CH1_USART6_TX_Pos) /*!< 0x0000000D */
Kojto 122:f9eeca106725 5997 #define DMA2_CSELR_CH1_USART6_TX DMA2_CSELR_CH1_USART6_TX_Msk /*!< Remap USART6 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 5998 #define DMA2_CSELR_CH1_USART7_TX_Pos (1U)
Kojto 122:f9eeca106725 5999 #define DMA2_CSELR_CH1_USART7_TX_Msk (0x7U << DMA2_CSELR_CH1_USART7_TX_Pos) /*!< 0x0000000E */
Kojto 122:f9eeca106725 6000 #define DMA2_CSELR_CH1_USART7_TX DMA2_CSELR_CH1_USART7_TX_Msk /*!< Remap USART7 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 6001 #define DMA2_CSELR_CH1_USART8_TX_Pos (0U)
Kojto 122:f9eeca106725 6002 #define DMA2_CSELR_CH1_USART8_TX_Msk (0xFU << DMA2_CSELR_CH1_USART8_TX_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 6003 #define DMA2_CSELR_CH1_USART8_TX DMA2_CSELR_CH1_USART8_TX_Msk /*!< Remap USART8 Tx on DMA2 channel 1 */
Kojto 122:f9eeca106725 6004 #define DMA2_CSELR_CH2_I2C2_RX_Pos (5U)
Kojto 122:f9eeca106725 6005 #define DMA2_CSELR_CH2_I2C2_RX_Msk (0x1U << DMA2_CSELR_CH2_I2C2_RX_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6006 #define DMA2_CSELR_CH2_I2C2_RX DMA2_CSELR_CH2_I2C2_RX_Msk /*!< Remap I2C2 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6007 #define DMA2_CSELR_CH2_USART1_RX_Pos (7U)
Kojto 122:f9eeca106725 6008 #define DMA2_CSELR_CH2_USART1_RX_Msk (0x1U << DMA2_CSELR_CH2_USART1_RX_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6009 #define DMA2_CSELR_CH2_USART1_RX DMA2_CSELR_CH2_USART1_RX_Msk /*!< Remap USART1 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6010 #define DMA2_CSELR_CH2_USART2_RX_Pos (4U)
Kojto 122:f9eeca106725 6011 #define DMA2_CSELR_CH2_USART2_RX_Msk (0x9U << DMA2_CSELR_CH2_USART2_RX_Pos) /*!< 0x00000090 */
Kojto 122:f9eeca106725 6012 #define DMA2_CSELR_CH2_USART2_RX DMA2_CSELR_CH2_USART2_RX_Msk /*!< Remap USART2 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6013 #define DMA2_CSELR_CH2_USART3_RX_Pos (5U)
Kojto 122:f9eeca106725 6014 #define DMA2_CSELR_CH2_USART3_RX_Msk (0x5U << DMA2_CSELR_CH2_USART3_RX_Pos) /*!< 0x000000A0 */
Kojto 122:f9eeca106725 6015 #define DMA2_CSELR_CH2_USART3_RX DMA2_CSELR_CH2_USART3_RX_Msk /*!< Remap USART3 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6016 #define DMA2_CSELR_CH2_USART4_RX_Pos (4U)
Kojto 122:f9eeca106725 6017 #define DMA2_CSELR_CH2_USART4_RX_Msk (0xBU << DMA2_CSELR_CH2_USART4_RX_Pos) /*!< 0x000000B0 */
Kojto 122:f9eeca106725 6018 #define DMA2_CSELR_CH2_USART4_RX DMA2_CSELR_CH2_USART4_RX_Msk /*!< Remap USART4 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6019 #define DMA2_CSELR_CH2_USART5_RX_Pos (6U)
Kojto 122:f9eeca106725 6020 #define DMA2_CSELR_CH2_USART5_RX_Msk (0x3U << DMA2_CSELR_CH2_USART5_RX_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 6021 #define DMA2_CSELR_CH2_USART5_RX DMA2_CSELR_CH2_USART5_RX_Msk /*!< Remap USART5 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6022 #define DMA2_CSELR_CH2_USART6_RX_Pos (4U)
Kojto 122:f9eeca106725 6023 #define DMA2_CSELR_CH2_USART6_RX_Msk (0xDU << DMA2_CSELR_CH2_USART6_RX_Pos) /*!< 0x000000D0 */
Kojto 122:f9eeca106725 6024 #define DMA2_CSELR_CH2_USART6_RX DMA2_CSELR_CH2_USART6_RX_Msk /*!< Remap USART6 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6025 #define DMA2_CSELR_CH2_USART7_RX_Pos (5U)
Kojto 122:f9eeca106725 6026 #define DMA2_CSELR_CH2_USART7_RX_Msk (0x7U << DMA2_CSELR_CH2_USART7_RX_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 6027 #define DMA2_CSELR_CH2_USART7_RX DMA2_CSELR_CH2_USART7_RX_Msk /*!< Remap USART7 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6028 #define DMA2_CSELR_CH2_USART8_RX_Pos (4U)
Kojto 122:f9eeca106725 6029 #define DMA2_CSELR_CH2_USART8_RX_Msk (0xFU << DMA2_CSELR_CH2_USART8_RX_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 6030 #define DMA2_CSELR_CH2_USART8_RX DMA2_CSELR_CH2_USART8_RX_Msk /*!< Remap USART8 Rx on DMA2 channel 2 */
Kojto 122:f9eeca106725 6031 #define DMA2_CSELR_CH3_TIM6_UP_Pos (8U)
Kojto 122:f9eeca106725 6032 #define DMA2_CSELR_CH3_TIM6_UP_Msk (0x1U << DMA2_CSELR_CH3_TIM6_UP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6033 #define DMA2_CSELR_CH3_TIM6_UP DMA2_CSELR_CH3_TIM6_UP_Msk /*!< Remap TIM6 up on DMA2 channel 3 */
Kojto 122:f9eeca106725 6034 #define DMA2_CSELR_CH3_DAC_CH1_Pos (8U)
Kojto 122:f9eeca106725 6035 #define DMA2_CSELR_CH3_DAC_CH1_Msk (0x1U << DMA2_CSELR_CH3_DAC_CH1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6036 #define DMA2_CSELR_CH3_DAC_CH1 DMA2_CSELR_CH3_DAC_CH1_Msk /*!< Remap DAC channel 1 on DMA2 channel 3 */
Kojto 122:f9eeca106725 6037 #define DMA2_CSELR_CH3_SPI1_RX_Pos (8U)
Kojto 122:f9eeca106725 6038 #define DMA2_CSELR_CH3_SPI1_RX_Msk (0x3U << DMA2_CSELR_CH3_SPI1_RX_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 6039 #define DMA2_CSELR_CH3_SPI1_RX DMA2_CSELR_CH3_SPI1_RX_Msk /*!< Remap SPI1 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6040 #define DMA2_CSELR_CH3_USART1_RX_Pos (11U)
Kojto 122:f9eeca106725 6041 #define DMA2_CSELR_CH3_USART1_RX_Msk (0x1U << DMA2_CSELR_CH3_USART1_RX_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6042 #define DMA2_CSELR_CH3_USART1_RX DMA2_CSELR_CH3_USART1_RX_Msk /*!< Remap USART1 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6043 #define DMA2_CSELR_CH3_USART2_RX_Pos (8U)
Kojto 122:f9eeca106725 6044 #define DMA2_CSELR_CH3_USART2_RX_Msk (0x9U << DMA2_CSELR_CH3_USART2_RX_Pos) /*!< 0x00000900 */
Kojto 122:f9eeca106725 6045 #define DMA2_CSELR_CH3_USART2_RX DMA2_CSELR_CH3_USART2_RX_Msk /*!< Remap USART2 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6046 #define DMA2_CSELR_CH3_USART3_RX_Pos (9U)
Kojto 122:f9eeca106725 6047 #define DMA2_CSELR_CH3_USART3_RX_Msk (0x5U << DMA2_CSELR_CH3_USART3_RX_Pos) /*!< 0x00000A00 */
Kojto 122:f9eeca106725 6048 #define DMA2_CSELR_CH3_USART3_RX DMA2_CSELR_CH3_USART3_RX_Msk /*!< Remap USART3 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6049 #define DMA2_CSELR_CH3_USART4_RX_Pos (8U)
Kojto 122:f9eeca106725 6050 #define DMA2_CSELR_CH3_USART4_RX_Msk (0xBU << DMA2_CSELR_CH3_USART4_RX_Pos) /*!< 0x00000B00 */
Kojto 122:f9eeca106725 6051 #define DMA2_CSELR_CH3_USART4_RX DMA2_CSELR_CH3_USART4_RX_Msk /*!< Remap USART4 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6052 #define DMA2_CSELR_CH3_USART5_RX_Pos (10U)
Kojto 122:f9eeca106725 6053 #define DMA2_CSELR_CH3_USART5_RX_Msk (0x3U << DMA2_CSELR_CH3_USART5_RX_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 6054 #define DMA2_CSELR_CH3_USART5_RX DMA2_CSELR_CH3_USART5_RX_Msk /*!< Remap USART5 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6055 #define DMA2_CSELR_CH3_USART6_RX_Pos (8U)
Kojto 122:f9eeca106725 6056 #define DMA2_CSELR_CH3_USART6_RX_Msk (0xDU << DMA2_CSELR_CH3_USART6_RX_Pos) /*!< 0x00000D00 */
Kojto 122:f9eeca106725 6057 #define DMA2_CSELR_CH3_USART6_RX DMA2_CSELR_CH3_USART6_RX_Msk /*!< Remap USART6 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6058 #define DMA2_CSELR_CH3_USART7_RX_Pos (9U)
Kojto 122:f9eeca106725 6059 #define DMA2_CSELR_CH3_USART7_RX_Msk (0x7U << DMA2_CSELR_CH3_USART7_RX_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 6060 #define DMA2_CSELR_CH3_USART7_RX DMA2_CSELR_CH3_USART7_RX_Msk /*!< Remap USART7 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6061 #define DMA2_CSELR_CH3_USART8_RX_Pos (8U)
Kojto 122:f9eeca106725 6062 #define DMA2_CSELR_CH3_USART8_RX_Msk (0xFU << DMA2_CSELR_CH3_USART8_RX_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 6063 #define DMA2_CSELR_CH3_USART8_RX DMA2_CSELR_CH3_USART8_RX_Msk /*!< Remap USART8 Rx on DMA2 channel 3 */
Kojto 122:f9eeca106725 6064 #define DMA2_CSELR_CH4_TIM7_UP_Pos (12U)
Kojto 122:f9eeca106725 6065 #define DMA2_CSELR_CH4_TIM7_UP_Msk (0x1U << DMA2_CSELR_CH4_TIM7_UP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6066 #define DMA2_CSELR_CH4_TIM7_UP DMA2_CSELR_CH4_TIM7_UP_Msk /*!< Remap TIM7 up on DMA2 channel 4 */
Kojto 122:f9eeca106725 6067 #define DMA2_CSELR_CH4_DAC_CH2_Pos (12U)
Kojto 122:f9eeca106725 6068 #define DMA2_CSELR_CH4_DAC_CH2_Msk (0x1U << DMA2_CSELR_CH4_DAC_CH2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6069 #define DMA2_CSELR_CH4_DAC_CH2 DMA2_CSELR_CH4_DAC_CH2_Msk /*!< Remap DAC channel 2 on DMA2 channel 4 */
Kojto 122:f9eeca106725 6070 #define DMA2_CSELR_CH4_SPI1_TX_Pos (12U)
Kojto 122:f9eeca106725 6071 #define DMA2_CSELR_CH4_SPI1_TX_Msk (0x3U << DMA2_CSELR_CH4_SPI1_TX_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 6072 #define DMA2_CSELR_CH4_SPI1_TX DMA2_CSELR_CH4_SPI1_TX_Msk /*!< Remap SPI1 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6073 #define DMA2_CSELR_CH4_USART1_TX_Pos (15U)
Kojto 122:f9eeca106725 6074 #define DMA2_CSELR_CH4_USART1_TX_Msk (0x1U << DMA2_CSELR_CH4_USART1_TX_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6075 #define DMA2_CSELR_CH4_USART1_TX DMA2_CSELR_CH4_USART1_TX_Msk /*!< Remap USART1 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6076 #define DMA2_CSELR_CH4_USART2_TX_Pos (12U)
Kojto 122:f9eeca106725 6077 #define DMA2_CSELR_CH4_USART2_TX_Msk (0x9U << DMA2_CSELR_CH4_USART2_TX_Pos) /*!< 0x00009000 */
Kojto 122:f9eeca106725 6078 #define DMA2_CSELR_CH4_USART2_TX DMA2_CSELR_CH4_USART2_TX_Msk /*!< Remap USART2 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6079 #define DMA2_CSELR_CH4_USART3_TX_Pos (13U)
Kojto 122:f9eeca106725 6080 #define DMA2_CSELR_CH4_USART3_TX_Msk (0x5U << DMA2_CSELR_CH4_USART3_TX_Pos) /*!< 0x0000A000 */
Kojto 122:f9eeca106725 6081 #define DMA2_CSELR_CH4_USART3_TX DMA2_CSELR_CH4_USART3_TX_Msk /*!< Remap USART3 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6082 #define DMA2_CSELR_CH4_USART4_TX_Pos (12U)
Kojto 122:f9eeca106725 6083 #define DMA2_CSELR_CH4_USART4_TX_Msk (0xBU << DMA2_CSELR_CH4_USART4_TX_Pos) /*!< 0x0000B000 */
Kojto 122:f9eeca106725 6084 #define DMA2_CSELR_CH4_USART4_TX DMA2_CSELR_CH4_USART4_TX_Msk /*!< Remap USART4 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6085 #define DMA2_CSELR_CH4_USART5_TX_Pos (14U)
Kojto 122:f9eeca106725 6086 #define DMA2_CSELR_CH4_USART5_TX_Msk (0x3U << DMA2_CSELR_CH4_USART5_TX_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 6087 #define DMA2_CSELR_CH4_USART5_TX DMA2_CSELR_CH4_USART5_TX_Msk /*!< Remap USART5 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6088 #define DMA2_CSELR_CH4_USART6_TX_Pos (12U)
Kojto 122:f9eeca106725 6089 #define DMA2_CSELR_CH4_USART6_TX_Msk (0xDU << DMA2_CSELR_CH4_USART6_TX_Pos) /*!< 0x0000D000 */
Kojto 122:f9eeca106725 6090 #define DMA2_CSELR_CH4_USART6_TX DMA2_CSELR_CH4_USART6_TX_Msk /*!< Remap USART6 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6091 #define DMA2_CSELR_CH4_USART7_TX_Pos (13U)
Kojto 122:f9eeca106725 6092 #define DMA2_CSELR_CH4_USART7_TX_Msk (0x7U << DMA2_CSELR_CH4_USART7_TX_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 6093 #define DMA2_CSELR_CH4_USART7_TX DMA2_CSELR_CH4_USART7_TX_Msk /*!< Remap USART7 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6094 #define DMA2_CSELR_CH4_USART8_TX_Pos (12U)
Kojto 122:f9eeca106725 6095 #define DMA2_CSELR_CH4_USART8_TX_Msk (0xFU << DMA2_CSELR_CH4_USART8_TX_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 6096 #define DMA2_CSELR_CH4_USART8_TX DMA2_CSELR_CH4_USART8_TX_Msk /*!< Remap USART8 Tx on DMA2 channel 4 */
Kojto 122:f9eeca106725 6097 #define DMA2_CSELR_CH5_ADC_Pos (16U)
Kojto 122:f9eeca106725 6098 #define DMA2_CSELR_CH5_ADC_Msk (0x1U << DMA2_CSELR_CH5_ADC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6099 #define DMA2_CSELR_CH5_ADC DMA2_CSELR_CH5_ADC_Msk /*!< Remap ADC on DMA2 channel 5 */
Kojto 122:f9eeca106725 6100 #define DMA2_CSELR_CH5_USART1_TX_Pos (19U)
Kojto 122:f9eeca106725 6101 #define DMA2_CSELR_CH5_USART1_TX_Msk (0x1U << DMA2_CSELR_CH5_USART1_TX_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6102 #define DMA2_CSELR_CH5_USART1_TX DMA2_CSELR_CH5_USART1_TX_Msk /*!< Remap USART1 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6103 #define DMA2_CSELR_CH5_USART2_TX_Pos (16U)
Kojto 122:f9eeca106725 6104 #define DMA2_CSELR_CH5_USART2_TX_Msk (0x9U << DMA2_CSELR_CH5_USART2_TX_Pos) /*!< 0x00090000 */
Kojto 122:f9eeca106725 6105 #define DMA2_CSELR_CH5_USART2_TX DMA2_CSELR_CH5_USART2_TX_Msk /*!< Remap USART2 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6106 #define DMA2_CSELR_CH5_USART3_TX_Pos (17U)
Kojto 122:f9eeca106725 6107 #define DMA2_CSELR_CH5_USART3_TX_Msk (0x5U << DMA2_CSELR_CH5_USART3_TX_Pos) /*!< 0x000A0000 */
Kojto 122:f9eeca106725 6108 #define DMA2_CSELR_CH5_USART3_TX DMA2_CSELR_CH5_USART3_TX_Msk /*!< Remap USART3 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6109 #define DMA2_CSELR_CH5_USART4_TX_Pos (16U)
Kojto 122:f9eeca106725 6110 #define DMA2_CSELR_CH5_USART4_TX_Msk (0xBU << DMA2_CSELR_CH5_USART4_TX_Pos) /*!< 0x000B0000 */
Kojto 122:f9eeca106725 6111 #define DMA2_CSELR_CH5_USART4_TX DMA2_CSELR_CH5_USART4_TX_Msk /*!< Remap USART4 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6112 #define DMA2_CSELR_CH5_USART5_TX_Pos (18U)
Kojto 122:f9eeca106725 6113 #define DMA2_CSELR_CH5_USART5_TX_Msk (0x3U << DMA2_CSELR_CH5_USART5_TX_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 6114 #define DMA2_CSELR_CH5_USART5_TX DMA2_CSELR_CH5_USART5_TX_Msk /*!< Remap USART5 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6115 #define DMA2_CSELR_CH5_USART6_TX_Pos (16U)
Kojto 122:f9eeca106725 6116 #define DMA2_CSELR_CH5_USART6_TX_Msk (0xDU << DMA2_CSELR_CH5_USART6_TX_Pos) /*!< 0x000D0000 */
Kojto 122:f9eeca106725 6117 #define DMA2_CSELR_CH5_USART6_TX DMA2_CSELR_CH5_USART6_TX_Msk /*!< Remap USART6 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6118 #define DMA2_CSELR_CH5_USART7_TX_Pos (17U)
Kojto 122:f9eeca106725 6119 #define DMA2_CSELR_CH5_USART7_TX_Msk (0x7U << DMA2_CSELR_CH5_USART7_TX_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 6120 #define DMA2_CSELR_CH5_USART7_TX DMA2_CSELR_CH5_USART7_TX_Msk /*!< Remap USART7 Tx on DMA2 channel 5 */
Kojto 122:f9eeca106725 6121 #define DMA2_CSELR_CH5_USART8_TX_Pos (16U)
Kojto 122:f9eeca106725 6122 #define DMA2_CSELR_CH5_USART8_TX_Msk (0xFU << DMA2_CSELR_CH5_USART8_TX_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 6123 #define DMA2_CSELR_CH5_USART8_TX DMA2_CSELR_CH5_USART8_TX_Msk /*!< Remap USART8 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 6124
Kojto 90:cb3d968589d8 6125 /******************************************************************************/
Kojto 90:cb3d968589d8 6126 /* */
Kojto 90:cb3d968589d8 6127 /* External Interrupt/Event Controller (EXTI) */
Kojto 90:cb3d968589d8 6128 /* */
Kojto 90:cb3d968589d8 6129 /******************************************************************************/
Kojto 90:cb3d968589d8 6130 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 6131 #define EXTI_IMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 6132 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6133 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 6134 #define EXTI_IMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 6135 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6136 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 6137 #define EXTI_IMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 6138 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6139 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 6140 #define EXTI_IMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 6141 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6142 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 6143 #define EXTI_IMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 6144 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6145 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 6146 #define EXTI_IMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 6147 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6148 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 6149 #define EXTI_IMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 6150 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6151 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 6152 #define EXTI_IMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 6153 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6154 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 6155 #define EXTI_IMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 6156 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6157 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 6158 #define EXTI_IMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 6159 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6160 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 6161 #define EXTI_IMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 6162 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6163 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 6164 #define EXTI_IMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 6165 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6166 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 6167 #define EXTI_IMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 6168 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6169 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 6170 #define EXTI_IMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 6171 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6172 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 6173 #define EXTI_IMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 6174 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6175 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 6176 #define EXTI_IMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 6177 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6178 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 6179 #define EXTI_IMR_MR16_Pos (16U)
Kojto 122:f9eeca106725 6180 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6181 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 6182 #define EXTI_IMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 6183 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6184 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 6185 #define EXTI_IMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 6186 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6187 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 6188 #define EXTI_IMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 6189 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6190 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 6191 #define EXTI_IMR_MR20_Pos (20U)
Kojto 122:f9eeca106725 6192 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6193 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 6194 #define EXTI_IMR_MR21_Pos (21U)
Kojto 122:f9eeca106725 6195 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6196 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 6197 #define EXTI_IMR_MR22_Pos (22U)
Kojto 122:f9eeca106725 6198 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6199 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
Kojto 122:f9eeca106725 6200 #define EXTI_IMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 6201 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6202 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 6203 #define EXTI_IMR_MR25_Pos (25U)
Kojto 122:f9eeca106725 6204 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6205 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
Kojto 122:f9eeca106725 6206 #define EXTI_IMR_MR26_Pos (26U)
Kojto 122:f9eeca106725 6207 #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6208 #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
Kojto 122:f9eeca106725 6209 #define EXTI_IMR_MR27_Pos (27U)
Kojto 122:f9eeca106725 6210 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6211 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
Kojto 122:f9eeca106725 6212 #define EXTI_IMR_MR28_Pos (28U)
Kojto 122:f9eeca106725 6213 #define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6214 #define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
Kojto 122:f9eeca106725 6215 #define EXTI_IMR_MR31_Pos (31U)
Kojto 122:f9eeca106725 6216 #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6217 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
Kojto 122:f9eeca106725 6218
Kojto 122:f9eeca106725 6219 /* References Defines */
Kojto 122:f9eeca106725 6220 #define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto 122:f9eeca106725 6221 #define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto 122:f9eeca106725 6222 #define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto 122:f9eeca106725 6223 #define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto 122:f9eeca106725 6224 #define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto 122:f9eeca106725 6225 #define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto 122:f9eeca106725 6226 #define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto 122:f9eeca106725 6227 #define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto 122:f9eeca106725 6228 #define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto 122:f9eeca106725 6229 #define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto 122:f9eeca106725 6230 #define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto 122:f9eeca106725 6231 #define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto 122:f9eeca106725 6232 #define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto 122:f9eeca106725 6233 #define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto 122:f9eeca106725 6234 #define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto 122:f9eeca106725 6235 #define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto 122:f9eeca106725 6236 #define EXTI_IMR_IM16 EXTI_IMR_MR16
Kojto 122:f9eeca106725 6237 #define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto 122:f9eeca106725 6238 #define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto 122:f9eeca106725 6239 #define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto 122:f9eeca106725 6240 #define EXTI_IMR_IM20 EXTI_IMR_MR20
Kojto 122:f9eeca106725 6241 #define EXTI_IMR_IM21 EXTI_IMR_MR21
Kojto 122:f9eeca106725 6242 #define EXTI_IMR_IM22 EXTI_IMR_MR22
Kojto 122:f9eeca106725 6243 #define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto 122:f9eeca106725 6244 #define EXTI_IMR_IM25 EXTI_IMR_MR25
Kojto 122:f9eeca106725 6245 #define EXTI_IMR_IM26 EXTI_IMR_MR26
Kojto 122:f9eeca106725 6246 #define EXTI_IMR_IM27 EXTI_IMR_MR27
Kojto 122:f9eeca106725 6247 #define EXTI_IMR_IM28 EXTI_IMR_MR28
Kojto 122:f9eeca106725 6248 #define EXTI_IMR_IM31 EXTI_IMR_MR31
Kojto 122:f9eeca106725 6249
Kojto 122:f9eeca106725 6250 #define EXTI_IMR_IM_Pos (0U)
Kojto 122:f9eeca106725 6251 #define EXTI_IMR_IM_Msk (0x9EFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x9EFFFFFF */
Kojto 122:f9eeca106725 6252 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
Kojto 122:f9eeca106725 6253
Kojto 90:cb3d968589d8 6254
Kojto 90:cb3d968589d8 6255 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 122:f9eeca106725 6256 #define EXTI_EMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 6257 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6258 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 6259 #define EXTI_EMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 6260 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6261 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 6262 #define EXTI_EMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 6263 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6264 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 6265 #define EXTI_EMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 6266 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6267 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 6268 #define EXTI_EMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 6269 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6270 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 6271 #define EXTI_EMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 6272 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6273 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 6274 #define EXTI_EMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 6275 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6276 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 6277 #define EXTI_EMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 6278 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6279 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 6280 #define EXTI_EMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 6281 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6282 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 6283 #define EXTI_EMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 6284 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6285 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 6286 #define EXTI_EMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 6287 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6288 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 6289 #define EXTI_EMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 6290 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6291 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 6292 #define EXTI_EMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 6293 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6294 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 6295 #define EXTI_EMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 6296 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6297 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 6298 #define EXTI_EMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 6299 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6300 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 6301 #define EXTI_EMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 6302 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6303 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 6304 #define EXTI_EMR_MR16_Pos (16U)
Kojto 122:f9eeca106725 6305 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6306 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 6307 #define EXTI_EMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 6308 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6309 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 6310 #define EXTI_EMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 6311 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6312 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 6313 #define EXTI_EMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 6314 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6315 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 6316 #define EXTI_EMR_MR20_Pos (20U)
Kojto 122:f9eeca106725 6317 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6318 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 6319 #define EXTI_EMR_MR21_Pos (21U)
Kojto 122:f9eeca106725 6320 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6321 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 6322 #define EXTI_EMR_MR22_Pos (22U)
Kojto 122:f9eeca106725 6323 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6324 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
Kojto 122:f9eeca106725 6325 #define EXTI_EMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 6326 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6327 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 6328 #define EXTI_EMR_MR25_Pos (25U)
Kojto 122:f9eeca106725 6329 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6330 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
Kojto 122:f9eeca106725 6331 #define EXTI_EMR_MR26_Pos (26U)
Kojto 122:f9eeca106725 6332 #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6333 #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
Kojto 122:f9eeca106725 6334 #define EXTI_EMR_MR27_Pos (27U)
Kojto 122:f9eeca106725 6335 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6336 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
Kojto 122:f9eeca106725 6337 #define EXTI_EMR_MR28_Pos (28U)
Kojto 122:f9eeca106725 6338 #define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6339 #define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
Kojto 122:f9eeca106725 6340 #define EXTI_EMR_MR31_Pos (31U)
Kojto 122:f9eeca106725 6341 #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6342 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
Kojto 122:f9eeca106725 6343
Kojto 122:f9eeca106725 6344 /* References Defines */
Kojto 122:f9eeca106725 6345 #define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto 122:f9eeca106725 6346 #define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto 122:f9eeca106725 6347 #define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto 122:f9eeca106725 6348 #define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto 122:f9eeca106725 6349 #define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto 122:f9eeca106725 6350 #define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto 122:f9eeca106725 6351 #define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto 122:f9eeca106725 6352 #define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto 122:f9eeca106725 6353 #define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto 122:f9eeca106725 6354 #define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto 122:f9eeca106725 6355 #define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto 122:f9eeca106725 6356 #define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto 122:f9eeca106725 6357 #define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto 122:f9eeca106725 6358 #define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto 122:f9eeca106725 6359 #define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto 122:f9eeca106725 6360 #define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto 122:f9eeca106725 6361 #define EXTI_EMR_EM16 EXTI_EMR_MR16
Kojto 122:f9eeca106725 6362 #define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto 122:f9eeca106725 6363 #define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto 122:f9eeca106725 6364 #define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto 122:f9eeca106725 6365 #define EXTI_EMR_EM20 EXTI_EMR_MR20
Kojto 122:f9eeca106725 6366 #define EXTI_EMR_EM21 EXTI_EMR_MR21
Kojto 122:f9eeca106725 6367 #define EXTI_EMR_EM22 EXTI_EMR_MR22
Kojto 122:f9eeca106725 6368 #define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto 122:f9eeca106725 6369 #define EXTI_EMR_EM25 EXTI_EMR_MR25
Kojto 122:f9eeca106725 6370 #define EXTI_EMR_EM26 EXTI_EMR_MR26
Kojto 122:f9eeca106725 6371 #define EXTI_EMR_EM27 EXTI_EMR_MR27
Kojto 122:f9eeca106725 6372 #define EXTI_EMR_EM28 EXTI_EMR_MR28
Kojto 122:f9eeca106725 6373 #define EXTI_EMR_EM31 EXTI_EMR_MR31
Kojto 90:cb3d968589d8 6374
Kojto 90:cb3d968589d8 6375 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 122:f9eeca106725 6376 #define EXTI_RTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 6377 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6378 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6379 #define EXTI_RTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 6380 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6381 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6382 #define EXTI_RTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 6383 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6384 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6385 #define EXTI_RTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 6386 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6387 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6388 #define EXTI_RTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 6389 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6390 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6391 #define EXTI_RTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 6392 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6393 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6394 #define EXTI_RTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 6395 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6396 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6397 #define EXTI_RTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 6398 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6399 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6400 #define EXTI_RTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 6401 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6402 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6403 #define EXTI_RTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 6404 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6405 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6406 #define EXTI_RTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 6407 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6408 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6409 #define EXTI_RTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 6410 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6411 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6412 #define EXTI_RTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 6413 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6414 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6415 #define EXTI_RTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 6416 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6417 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 6418 #define EXTI_RTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 6419 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6420 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 6421 #define EXTI_RTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 6422 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6423 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 6424 #define EXTI_RTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 6425 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6426 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 6427 #define EXTI_RTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 6428 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6429 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 6430 #define EXTI_RTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 6431 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6432 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 6433 #define EXTI_RTSR_TR20_Pos (20U)
Kojto 122:f9eeca106725 6434 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6435 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 6436 #define EXTI_RTSR_TR21_Pos (21U)
Kojto 122:f9eeca106725 6437 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6438 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 6439 #define EXTI_RTSR_TR22_Pos (22U)
Kojto 122:f9eeca106725 6440 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6441 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 6442 #define EXTI_RTSR_TR31_Pos (31U)
Kojto 122:f9eeca106725 6443 #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6444 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
Kojto 122:f9eeca106725 6445
Kojto 122:f9eeca106725 6446 /* References Defines */
Kojto 122:f9eeca106725 6447 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
Kojto 122:f9eeca106725 6448 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
Kojto 122:f9eeca106725 6449 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
Kojto 122:f9eeca106725 6450 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
Kojto 122:f9eeca106725 6451 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
Kojto 122:f9eeca106725 6452 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
Kojto 122:f9eeca106725 6453 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
Kojto 122:f9eeca106725 6454 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
Kojto 122:f9eeca106725 6455 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
Kojto 122:f9eeca106725 6456 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
Kojto 122:f9eeca106725 6457 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
Kojto 122:f9eeca106725 6458 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
Kojto 122:f9eeca106725 6459 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
Kojto 122:f9eeca106725 6460 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
Kojto 122:f9eeca106725 6461 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
Kojto 122:f9eeca106725 6462 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
Kojto 122:f9eeca106725 6463 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
Kojto 122:f9eeca106725 6464 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
Kojto 122:f9eeca106725 6465 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
Kojto 122:f9eeca106725 6466 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
Kojto 122:f9eeca106725 6467 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
Kojto 122:f9eeca106725 6468 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
Kojto 122:f9eeca106725 6469 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
Kojto 90:cb3d968589d8 6470
Kojto 90:cb3d968589d8 6471 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 6472 #define EXTI_FTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 6473 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6474 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6475 #define EXTI_FTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 6476 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6477 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6478 #define EXTI_FTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 6479 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6480 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6481 #define EXTI_FTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 6482 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6483 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6484 #define EXTI_FTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 6485 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6486 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6487 #define EXTI_FTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 6488 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6489 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6490 #define EXTI_FTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 6491 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6492 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6493 #define EXTI_FTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 6494 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6495 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6496 #define EXTI_FTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 6497 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6498 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6499 #define EXTI_FTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 6500 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6501 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6502 #define EXTI_FTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 6503 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6504 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6505 #define EXTI_FTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 6506 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6507 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6508 #define EXTI_FTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 6509 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6510 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6511 #define EXTI_FTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 6512 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6513 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 6514 #define EXTI_FTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 6515 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6516 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 6517 #define EXTI_FTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 6518 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6519 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 6520 #define EXTI_FTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 6521 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6522 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 6523 #define EXTI_FTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 6524 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6525 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 6526 #define EXTI_FTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 6527 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6528 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 6529 #define EXTI_FTSR_TR20_Pos (20U)
Kojto 122:f9eeca106725 6530 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6531 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 6532 #define EXTI_FTSR_TR21_Pos (21U)
Kojto 122:f9eeca106725 6533 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6534 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 6535 #define EXTI_FTSR_TR22_Pos (22U)
Kojto 122:f9eeca106725 6536 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6537 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 6538 #define EXTI_FTSR_TR31_Pos (31U)
Kojto 122:f9eeca106725 6539 #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6540 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
Kojto 122:f9eeca106725 6541
Kojto 122:f9eeca106725 6542 /* References Defines */
Kojto 122:f9eeca106725 6543 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
Kojto 122:f9eeca106725 6544 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
Kojto 122:f9eeca106725 6545 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
Kojto 122:f9eeca106725 6546 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
Kojto 122:f9eeca106725 6547 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
Kojto 122:f9eeca106725 6548 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
Kojto 122:f9eeca106725 6549 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
Kojto 122:f9eeca106725 6550 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
Kojto 122:f9eeca106725 6551 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
Kojto 122:f9eeca106725 6552 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
Kojto 122:f9eeca106725 6553 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
Kojto 122:f9eeca106725 6554 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
Kojto 122:f9eeca106725 6555 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
Kojto 122:f9eeca106725 6556 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
Kojto 122:f9eeca106725 6557 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
Kojto 122:f9eeca106725 6558 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
Kojto 122:f9eeca106725 6559 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
Kojto 122:f9eeca106725 6560 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
Kojto 122:f9eeca106725 6561 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
Kojto 122:f9eeca106725 6562 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
Kojto 122:f9eeca106725 6563 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
Kojto 122:f9eeca106725 6564 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
Kojto 122:f9eeca106725 6565 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
Kojto 90:cb3d968589d8 6566
Kojto 90:cb3d968589d8 6567 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 122:f9eeca106725 6568 #define EXTI_SWIER_SWIER0_Pos (0U)
Kojto 122:f9eeca106725 6569 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6570 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 6571 #define EXTI_SWIER_SWIER1_Pos (1U)
Kojto 122:f9eeca106725 6572 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6573 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 6574 #define EXTI_SWIER_SWIER2_Pos (2U)
Kojto 122:f9eeca106725 6575 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6576 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 6577 #define EXTI_SWIER_SWIER3_Pos (3U)
Kojto 122:f9eeca106725 6578 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6579 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 6580 #define EXTI_SWIER_SWIER4_Pos (4U)
Kojto 122:f9eeca106725 6581 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6582 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 6583 #define EXTI_SWIER_SWIER5_Pos (5U)
Kojto 122:f9eeca106725 6584 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6585 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 6586 #define EXTI_SWIER_SWIER6_Pos (6U)
Kojto 122:f9eeca106725 6587 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6588 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 6589 #define EXTI_SWIER_SWIER7_Pos (7U)
Kojto 122:f9eeca106725 6590 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6591 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 6592 #define EXTI_SWIER_SWIER8_Pos (8U)
Kojto 122:f9eeca106725 6593 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6594 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 6595 #define EXTI_SWIER_SWIER9_Pos (9U)
Kojto 122:f9eeca106725 6596 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6597 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 6598 #define EXTI_SWIER_SWIER10_Pos (10U)
Kojto 122:f9eeca106725 6599 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6600 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 6601 #define EXTI_SWIER_SWIER11_Pos (11U)
Kojto 122:f9eeca106725 6602 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6603 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 6604 #define EXTI_SWIER_SWIER12_Pos (12U)
Kojto 122:f9eeca106725 6605 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6606 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 6607 #define EXTI_SWIER_SWIER13_Pos (13U)
Kojto 122:f9eeca106725 6608 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6609 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 6610 #define EXTI_SWIER_SWIER14_Pos (14U)
Kojto 122:f9eeca106725 6611 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6612 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 6613 #define EXTI_SWIER_SWIER15_Pos (15U)
Kojto 122:f9eeca106725 6614 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6615 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 6616 #define EXTI_SWIER_SWIER16_Pos (16U)
Kojto 122:f9eeca106725 6617 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6618 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 6619 #define EXTI_SWIER_SWIER17_Pos (17U)
Kojto 122:f9eeca106725 6620 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6621 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 6622 #define EXTI_SWIER_SWIER19_Pos (19U)
Kojto 122:f9eeca106725 6623 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6624 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 6625 #define EXTI_SWIER_SWIER20_Pos (20U)
Kojto 122:f9eeca106725 6626 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6627 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 6628 #define EXTI_SWIER_SWIER21_Pos (21U)
Kojto 122:f9eeca106725 6629 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6630 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 6631 #define EXTI_SWIER_SWIER22_Pos (22U)
Kojto 122:f9eeca106725 6632 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6633 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
Kojto 122:f9eeca106725 6634 #define EXTI_SWIER_SWIER31_Pos (31U)
Kojto 122:f9eeca106725 6635 #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6636 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
Kojto 122:f9eeca106725 6637
Kojto 122:f9eeca106725 6638 /* References Defines */
Kojto 122:f9eeca106725 6639 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
Kojto 122:f9eeca106725 6640 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
Kojto 122:f9eeca106725 6641 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
Kojto 122:f9eeca106725 6642 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
Kojto 122:f9eeca106725 6643 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
Kojto 122:f9eeca106725 6644 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
Kojto 122:f9eeca106725 6645 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
Kojto 122:f9eeca106725 6646 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
Kojto 122:f9eeca106725 6647 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
Kojto 122:f9eeca106725 6648 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
Kojto 122:f9eeca106725 6649 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
Kojto 122:f9eeca106725 6650 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
Kojto 122:f9eeca106725 6651 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
Kojto 122:f9eeca106725 6652 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
Kojto 122:f9eeca106725 6653 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
Kojto 122:f9eeca106725 6654 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
Kojto 122:f9eeca106725 6655 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
Kojto 122:f9eeca106725 6656 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
Kojto 122:f9eeca106725 6657 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
Kojto 122:f9eeca106725 6658 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
Kojto 122:f9eeca106725 6659 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
Kojto 122:f9eeca106725 6660 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
Kojto 122:f9eeca106725 6661 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
Kojto 90:cb3d968589d8 6662
Kojto 90:cb3d968589d8 6663 /****************** Bit definition for EXTI_PR register *********************/
Kojto 122:f9eeca106725 6664 #define EXTI_PR_PR0_Pos (0U)
Kojto 122:f9eeca106725 6665 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6666 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
Kojto 122:f9eeca106725 6667 #define EXTI_PR_PR1_Pos (1U)
Kojto 122:f9eeca106725 6668 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6669 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
Kojto 122:f9eeca106725 6670 #define EXTI_PR_PR2_Pos (2U)
Kojto 122:f9eeca106725 6671 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6672 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
Kojto 122:f9eeca106725 6673 #define EXTI_PR_PR3_Pos (3U)
Kojto 122:f9eeca106725 6674 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6675 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
Kojto 122:f9eeca106725 6676 #define EXTI_PR_PR4_Pos (4U)
Kojto 122:f9eeca106725 6677 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6678 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
Kojto 122:f9eeca106725 6679 #define EXTI_PR_PR5_Pos (5U)
Kojto 122:f9eeca106725 6680 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6681 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
Kojto 122:f9eeca106725 6682 #define EXTI_PR_PR6_Pos (6U)
Kojto 122:f9eeca106725 6683 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6684 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
Kojto 122:f9eeca106725 6685 #define EXTI_PR_PR7_Pos (7U)
Kojto 122:f9eeca106725 6686 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6687 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
Kojto 122:f9eeca106725 6688 #define EXTI_PR_PR8_Pos (8U)
Kojto 122:f9eeca106725 6689 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6690 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
Kojto 122:f9eeca106725 6691 #define EXTI_PR_PR9_Pos (9U)
Kojto 122:f9eeca106725 6692 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6693 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
Kojto 122:f9eeca106725 6694 #define EXTI_PR_PR10_Pos (10U)
Kojto 122:f9eeca106725 6695 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6696 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
Kojto 122:f9eeca106725 6697 #define EXTI_PR_PR11_Pos (11U)
Kojto 122:f9eeca106725 6698 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6699 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
Kojto 122:f9eeca106725 6700 #define EXTI_PR_PR12_Pos (12U)
Kojto 122:f9eeca106725 6701 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6702 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
Kojto 122:f9eeca106725 6703 #define EXTI_PR_PR13_Pos (13U)
Kojto 122:f9eeca106725 6704 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6705 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
Kojto 122:f9eeca106725 6706 #define EXTI_PR_PR14_Pos (14U)
Kojto 122:f9eeca106725 6707 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6708 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
Kojto 122:f9eeca106725 6709 #define EXTI_PR_PR15_Pos (15U)
Kojto 122:f9eeca106725 6710 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6711 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
Kojto 122:f9eeca106725 6712 #define EXTI_PR_PR16_Pos (16U)
Kojto 122:f9eeca106725 6713 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6714 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
Kojto 122:f9eeca106725 6715 #define EXTI_PR_PR17_Pos (17U)
Kojto 122:f9eeca106725 6716 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6717 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
Kojto 122:f9eeca106725 6718 #define EXTI_PR_PR19_Pos (19U)
Kojto 122:f9eeca106725 6719 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6720 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
Kojto 122:f9eeca106725 6721 #define EXTI_PR_PR20_Pos (20U)
Kojto 122:f9eeca106725 6722 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6723 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit 20 */
Kojto 122:f9eeca106725 6724 #define EXTI_PR_PR21_Pos (21U)
Kojto 122:f9eeca106725 6725 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6726 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */
Kojto 122:f9eeca106725 6727 #define EXTI_PR_PR22_Pos (22U)
Kojto 122:f9eeca106725 6728 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6729 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */
Kojto 122:f9eeca106725 6730 #define EXTI_PR_PR31_Pos (31U)
Kojto 122:f9eeca106725 6731 #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6732 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit 31 */
Kojto 122:f9eeca106725 6733
Kojto 122:f9eeca106725 6734 /* References Defines */
Kojto 122:f9eeca106725 6735 #define EXTI_PR_PIF0 EXTI_PR_PR0
Kojto 122:f9eeca106725 6736 #define EXTI_PR_PIF1 EXTI_PR_PR1
Kojto 122:f9eeca106725 6737 #define EXTI_PR_PIF2 EXTI_PR_PR2
Kojto 122:f9eeca106725 6738 #define EXTI_PR_PIF3 EXTI_PR_PR3
Kojto 122:f9eeca106725 6739 #define EXTI_PR_PIF4 EXTI_PR_PR4
Kojto 122:f9eeca106725 6740 #define EXTI_PR_PIF5 EXTI_PR_PR5
Kojto 122:f9eeca106725 6741 #define EXTI_PR_PIF6 EXTI_PR_PR6
Kojto 122:f9eeca106725 6742 #define EXTI_PR_PIF7 EXTI_PR_PR7
Kojto 122:f9eeca106725 6743 #define EXTI_PR_PIF8 EXTI_PR_PR8
Kojto 122:f9eeca106725 6744 #define EXTI_PR_PIF9 EXTI_PR_PR9
Kojto 122:f9eeca106725 6745 #define EXTI_PR_PIF10 EXTI_PR_PR10
Kojto 122:f9eeca106725 6746 #define EXTI_PR_PIF11 EXTI_PR_PR11
Kojto 122:f9eeca106725 6747 #define EXTI_PR_PIF12 EXTI_PR_PR12
Kojto 122:f9eeca106725 6748 #define EXTI_PR_PIF13 EXTI_PR_PR13
Kojto 122:f9eeca106725 6749 #define EXTI_PR_PIF14 EXTI_PR_PR14
Kojto 122:f9eeca106725 6750 #define EXTI_PR_PIF15 EXTI_PR_PR15
Kojto 122:f9eeca106725 6751 #define EXTI_PR_PIF16 EXTI_PR_PR16
Kojto 122:f9eeca106725 6752 #define EXTI_PR_PIF17 EXTI_PR_PR17
Kojto 122:f9eeca106725 6753 #define EXTI_PR_PIF19 EXTI_PR_PR19
Kojto 122:f9eeca106725 6754 #define EXTI_PR_PIF20 EXTI_PR_PR20
Kojto 122:f9eeca106725 6755 #define EXTI_PR_PIF21 EXTI_PR_PR21
Kojto 122:f9eeca106725 6756 #define EXTI_PR_PIF22 EXTI_PR_PR22
Kojto 122:f9eeca106725 6757 #define EXTI_PR_PIF31 EXTI_PR_PR31
Kojto 90:cb3d968589d8 6758
Kojto 90:cb3d968589d8 6759 /******************************************************************************/
Kojto 90:cb3d968589d8 6760 /* */
Kojto 90:cb3d968589d8 6761 /* FLASH and Option Bytes Registers */
Kojto 90:cb3d968589d8 6762 /* */
Kojto 90:cb3d968589d8 6763 /******************************************************************************/
Kojto 90:cb3d968589d8 6764
Kojto 90:cb3d968589d8 6765 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 122:f9eeca106725 6766 #define FLASH_ACR_LATENCY_Pos (0U)
Kojto 122:f9eeca106725 6767 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6768 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
Kojto 122:f9eeca106725 6769
Kojto 122:f9eeca106725 6770 #define FLASH_ACR_PRFTBE_Pos (4U)
Kojto 122:f9eeca106725 6771 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6772 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
Kojto 122:f9eeca106725 6773 #define FLASH_ACR_PRFTBS_Pos (5U)
Kojto 122:f9eeca106725 6774 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6775 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
Kojto 90:cb3d968589d8 6776
Kojto 90:cb3d968589d8 6777 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 122:f9eeca106725 6778 #define FLASH_KEYR_FKEYR_Pos (0U)
Kojto 122:f9eeca106725 6779 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6780 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
Kojto 90:cb3d968589d8 6781
Kojto 90:cb3d968589d8 6782 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 122:f9eeca106725 6783 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
Kojto 122:f9eeca106725 6784 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6785 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
Kojto 90:cb3d968589d8 6786
Kojto 90:cb3d968589d8 6787 /****************** FLASH Keys **********************************************/
Kojto 122:f9eeca106725 6788 #define FLASH_KEY1_Pos (0U)
Kojto 122:f9eeca106725 6789 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
Kojto 122:f9eeca106725 6790 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
Kojto 122:f9eeca106725 6791 #define FLASH_KEY2_Pos (0U)
Kojto 122:f9eeca106725 6792 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
Kojto 122:f9eeca106725 6793 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 90:cb3d968589d8 6794 to unlock the write access to the FPEC. */
Kojto 90:cb3d968589d8 6795
Kojto 122:f9eeca106725 6796 #define FLASH_OPTKEY1_Pos (0U)
Kojto 122:f9eeca106725 6797 #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
Kojto 122:f9eeca106725 6798 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
Kojto 122:f9eeca106725 6799 #define FLASH_OPTKEY2_Pos (0U)
Kojto 122:f9eeca106725 6800 #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
Kojto 122:f9eeca106725 6801 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 90:cb3d968589d8 6802 unlock the write access to the option byte block */
Kojto 90:cb3d968589d8 6803
Kojto 90:cb3d968589d8 6804 /****************** Bit definition for FLASH_SR register *******************/
Kojto 122:f9eeca106725 6805 #define FLASH_SR_BSY_Pos (0U)
Kojto 122:f9eeca106725 6806 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6807 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
Kojto 122:f9eeca106725 6808 #define FLASH_SR_PGERR_Pos (2U)
Kojto 122:f9eeca106725 6809 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6810 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
Kojto 122:f9eeca106725 6811 #define FLASH_SR_WRPRTERR_Pos (4U)
Kojto 122:f9eeca106725 6812 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6813 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
Kojto 122:f9eeca106725 6814 #define FLASH_SR_EOP_Pos (5U)
Kojto 122:f9eeca106725 6815 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6816 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
Kojto 90:cb3d968589d8 6817 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 90:cb3d968589d8 6818
Kojto 90:cb3d968589d8 6819 /******************* Bit definition for FLASH_CR register *******************/
Kojto 122:f9eeca106725 6820 #define FLASH_CR_PG_Pos (0U)
Kojto 122:f9eeca106725 6821 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6822 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
Kojto 122:f9eeca106725 6823 #define FLASH_CR_PER_Pos (1U)
Kojto 122:f9eeca106725 6824 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6825 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
Kojto 122:f9eeca106725 6826 #define FLASH_CR_MER_Pos (2U)
Kojto 122:f9eeca106725 6827 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6828 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
Kojto 122:f9eeca106725 6829 #define FLASH_CR_OPTPG_Pos (4U)
Kojto 122:f9eeca106725 6830 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6831 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
Kojto 122:f9eeca106725 6832 #define FLASH_CR_OPTER_Pos (5U)
Kojto 122:f9eeca106725 6833 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6834 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
Kojto 122:f9eeca106725 6835 #define FLASH_CR_STRT_Pos (6U)
Kojto 122:f9eeca106725 6836 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6837 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
Kojto 122:f9eeca106725 6838 #define FLASH_CR_LOCK_Pos (7U)
Kojto 122:f9eeca106725 6839 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6840 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
Kojto 122:f9eeca106725 6841 #define FLASH_CR_OPTWRE_Pos (9U)
Kojto 122:f9eeca106725 6842 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6843 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
Kojto 122:f9eeca106725 6844 #define FLASH_CR_ERRIE_Pos (10U)
Kojto 122:f9eeca106725 6845 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6846 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 6847 #define FLASH_CR_EOPIE_Pos (12U)
Kojto 122:f9eeca106725 6848 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6849 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
Kojto 122:f9eeca106725 6850 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
Kojto 122:f9eeca106725 6851 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6852 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
Kojto 90:cb3d968589d8 6853
Kojto 90:cb3d968589d8 6854 /******************* Bit definition for FLASH_AR register *******************/
Kojto 122:f9eeca106725 6855 #define FLASH_AR_FAR_Pos (0U)
Kojto 122:f9eeca106725 6856 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6857 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
Kojto 90:cb3d968589d8 6858
Kojto 90:cb3d968589d8 6859 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 122:f9eeca106725 6860 #define FLASH_OBR_OPTERR_Pos (0U)
Kojto 122:f9eeca106725 6861 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6862 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
Kojto 122:f9eeca106725 6863 #define FLASH_OBR_RDPRT1_Pos (1U)
Kojto 122:f9eeca106725 6864 #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6865 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
Kojto 122:f9eeca106725 6866 #define FLASH_OBR_RDPRT2_Pos (2U)
Kojto 122:f9eeca106725 6867 #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6868 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
Kojto 122:f9eeca106725 6869
Kojto 122:f9eeca106725 6870 #define FLASH_OBR_USER_Pos (8U)
Kojto 122:f9eeca106725 6871 #define FLASH_OBR_USER_Msk (0xFFU << FLASH_OBR_USER_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 6872 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
Kojto 122:f9eeca106725 6873 #define FLASH_OBR_IWDG_SW_Pos (8U)
Kojto 122:f9eeca106725 6874 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6875 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
Kojto 122:f9eeca106725 6876 #define FLASH_OBR_nRST_STOP_Pos (9U)
Kojto 122:f9eeca106725 6877 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6878 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
Kojto 122:f9eeca106725 6879 #define FLASH_OBR_nRST_STDBY_Pos (10U)
Kojto 122:f9eeca106725 6880 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6881 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
Kojto 122:f9eeca106725 6882 #define FLASH_OBR_nBOOT0_Pos (11U)
Kojto 122:f9eeca106725 6883 #define FLASH_OBR_nBOOT0_Msk (0x1U << FLASH_OBR_nBOOT0_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6884 #define FLASH_OBR_nBOOT0 FLASH_OBR_nBOOT0_Msk /*!< nBOOT0 */
Kojto 122:f9eeca106725 6885 #define FLASH_OBR_nBOOT1_Pos (12U)
Kojto 122:f9eeca106725 6886 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6887 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
Kojto 122:f9eeca106725 6888 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
Kojto 122:f9eeca106725 6889 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6890 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
Kojto 122:f9eeca106725 6891 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
Kojto 122:f9eeca106725 6892 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6893 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
Kojto 122:f9eeca106725 6894 #define FLASH_OBR_BOOT_SEL_Pos (15U)
Kojto 122:f9eeca106725 6895 #define FLASH_OBR_BOOT_SEL_Msk (0x1U << FLASH_OBR_BOOT_SEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6896 #define FLASH_OBR_BOOT_SEL FLASH_OBR_BOOT_SEL_Msk /*!< BOOT selection */
Kojto 122:f9eeca106725 6897 #define FLASH_OBR_DATA0_Pos (16U)
Kojto 122:f9eeca106725 6898 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 6899 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
Kojto 122:f9eeca106725 6900 #define FLASH_OBR_DATA1_Pos (24U)
Kojto 122:f9eeca106725 6901 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 6902 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
Kojto 90:cb3d968589d8 6903
Kojto 90:cb3d968589d8 6904 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 6905 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 90:cb3d968589d8 6906
Kojto 90:cb3d968589d8 6907 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 6908 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 90:cb3d968589d8 6909
Kojto 90:cb3d968589d8 6910 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 122:f9eeca106725 6911 #define FLASH_WRPR_WRP_Pos (0U)
Kojto 122:f9eeca106725 6912 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 6913 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
Kojto 90:cb3d968589d8 6914
Kojto 90:cb3d968589d8 6915 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 6916
Kojto 90:cb3d968589d8 6917 /****************** Bit definition for OB_RDP register **********************/
Kojto 122:f9eeca106725 6918 #define OB_RDP_RDP_Pos (0U)
Kojto 122:f9eeca106725 6919 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6920 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
Kojto 122:f9eeca106725 6921 #define OB_RDP_nRDP_Pos (8U)
Kojto 122:f9eeca106725 6922 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 6923 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
Kojto 90:cb3d968589d8 6924
Kojto 90:cb3d968589d8 6925 /****************** Bit definition for OB_USER register *********************/
Kojto 122:f9eeca106725 6926 #define OB_USER_USER_Pos (16U)
Kojto 122:f9eeca106725 6927 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 6928 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
Kojto 122:f9eeca106725 6929 #define OB_USER_nUSER_Pos (24U)
Kojto 122:f9eeca106725 6930 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 6931 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
Kojto 90:cb3d968589d8 6932
Kojto 90:cb3d968589d8 6933 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 122:f9eeca106725 6934 #define OB_WRP0_WRP0_Pos (0U)
Kojto 122:f9eeca106725 6935 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6936 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 6937 #define OB_WRP0_nWRP0_Pos (8U)
Kojto 122:f9eeca106725 6938 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 6939 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 6940
Kojto 90:cb3d968589d8 6941 /****************** Bit definition for OB_WRP1 register *********************/
Kojto 122:f9eeca106725 6942 #define OB_WRP1_WRP1_Pos (16U)
Kojto 122:f9eeca106725 6943 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 6944 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 6945 #define OB_WRP1_nWRP1_Pos (24U)
Kojto 122:f9eeca106725 6946 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 6947 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 6948
Kojto 90:cb3d968589d8 6949 /****************** Bit definition for OB_WRP2 register *********************/
Kojto 122:f9eeca106725 6950 #define OB_WRP2_WRP2_Pos (0U)
Kojto 122:f9eeca106725 6951 #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6952 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 6953 #define OB_WRP2_nWRP2_Pos (8U)
Kojto 122:f9eeca106725 6954 #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 6955 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 6956
Kojto 90:cb3d968589d8 6957 /****************** Bit definition for OB_WRP3 register *********************/
Kojto 122:f9eeca106725 6958 #define OB_WRP3_WRP3_Pos (16U)
Kojto 122:f9eeca106725 6959 #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 6960 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 6961 #define OB_WRP3_nWRP3_Pos (24U)
Kojto 122:f9eeca106725 6962 #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 6963 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 6964
Kojto 90:cb3d968589d8 6965 /******************************************************************************/
Kojto 90:cb3d968589d8 6966 /* */
Kojto 90:cb3d968589d8 6967 /* General Purpose IOs (GPIO) */
Kojto 90:cb3d968589d8 6968 /* */
Kojto 90:cb3d968589d8 6969 /******************************************************************************/
Kojto 90:cb3d968589d8 6970 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 6971 #define GPIO_MODER_MODER0_Pos (0U)
Kojto 122:f9eeca106725 6972 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 6973 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
Kojto 122:f9eeca106725 6974 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6975 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6976 #define GPIO_MODER_MODER1_Pos (2U)
Kojto 122:f9eeca106725 6977 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 6978 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
Kojto 122:f9eeca106725 6979 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6980 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6981 #define GPIO_MODER_MODER2_Pos (4U)
Kojto 122:f9eeca106725 6982 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 6983 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
Kojto 122:f9eeca106725 6984 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6985 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6986 #define GPIO_MODER_MODER3_Pos (6U)
Kojto 122:f9eeca106725 6987 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 6988 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
Kojto 122:f9eeca106725 6989 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6990 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6991 #define GPIO_MODER_MODER4_Pos (8U)
Kojto 122:f9eeca106725 6992 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 6993 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
Kojto 122:f9eeca106725 6994 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6995 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6996 #define GPIO_MODER_MODER5_Pos (10U)
Kojto 122:f9eeca106725 6997 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 6998 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
Kojto 122:f9eeca106725 6999 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7000 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7001 #define GPIO_MODER_MODER6_Pos (12U)
Kojto 122:f9eeca106725 7002 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7003 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
Kojto 122:f9eeca106725 7004 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7005 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7006 #define GPIO_MODER_MODER7_Pos (14U)
Kojto 122:f9eeca106725 7007 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7008 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
Kojto 122:f9eeca106725 7009 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7010 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7011 #define GPIO_MODER_MODER8_Pos (16U)
Kojto 122:f9eeca106725 7012 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7013 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
Kojto 122:f9eeca106725 7014 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7015 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7016 #define GPIO_MODER_MODER9_Pos (18U)
Kojto 122:f9eeca106725 7017 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7018 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
Kojto 122:f9eeca106725 7019 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7020 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7021 #define GPIO_MODER_MODER10_Pos (20U)
Kojto 122:f9eeca106725 7022 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7023 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
Kojto 122:f9eeca106725 7024 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7025 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7026 #define GPIO_MODER_MODER11_Pos (22U)
Kojto 122:f9eeca106725 7027 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7028 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
Kojto 122:f9eeca106725 7029 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7030 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7031 #define GPIO_MODER_MODER12_Pos (24U)
Kojto 122:f9eeca106725 7032 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7033 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
Kojto 122:f9eeca106725 7034 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7035 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7036 #define GPIO_MODER_MODER13_Pos (26U)
Kojto 122:f9eeca106725 7037 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7038 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
Kojto 122:f9eeca106725 7039 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7040 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7041 #define GPIO_MODER_MODER14_Pos (28U)
Kojto 122:f9eeca106725 7042 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7043 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
Kojto 122:f9eeca106725 7044 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7045 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7046 #define GPIO_MODER_MODER15_Pos (30U)
Kojto 122:f9eeca106725 7047 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7048 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
Kojto 122:f9eeca106725 7049 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7050 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 7051
Kojto 90:cb3d968589d8 7052 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 122:f9eeca106725 7053 #define GPIO_OTYPER_OT_0 (0x00000001U)
Kojto 122:f9eeca106725 7054 #define GPIO_OTYPER_OT_1 (0x00000002U)
Kojto 122:f9eeca106725 7055 #define GPIO_OTYPER_OT_2 (0x00000004U)
Kojto 122:f9eeca106725 7056 #define GPIO_OTYPER_OT_3 (0x00000008U)
Kojto 122:f9eeca106725 7057 #define GPIO_OTYPER_OT_4 (0x00000010U)
Kojto 122:f9eeca106725 7058 #define GPIO_OTYPER_OT_5 (0x00000020U)
Kojto 122:f9eeca106725 7059 #define GPIO_OTYPER_OT_6 (0x00000040U)
Kojto 122:f9eeca106725 7060 #define GPIO_OTYPER_OT_7 (0x00000080U)
Kojto 122:f9eeca106725 7061 #define GPIO_OTYPER_OT_8 (0x00000100U)
Kojto 122:f9eeca106725 7062 #define GPIO_OTYPER_OT_9 (0x00000200U)
Kojto 122:f9eeca106725 7063 #define GPIO_OTYPER_OT_10 (0x00000400U)
Kojto 122:f9eeca106725 7064 #define GPIO_OTYPER_OT_11 (0x00000800U)
Kojto 122:f9eeca106725 7065 #define GPIO_OTYPER_OT_12 (0x00001000U)
Kojto 122:f9eeca106725 7066 #define GPIO_OTYPER_OT_13 (0x00002000U)
Kojto 122:f9eeca106725 7067 #define GPIO_OTYPER_OT_14 (0x00004000U)
Kojto 122:f9eeca106725 7068 #define GPIO_OTYPER_OT_15 (0x00008000U)
Kojto 90:cb3d968589d8 7069
Kojto 90:cb3d968589d8 7070 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 122:f9eeca106725 7071 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
Kojto 122:f9eeca106725 7072 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7073 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
Kojto 122:f9eeca106725 7074 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7075 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7076 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
Kojto 122:f9eeca106725 7077 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7078 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
Kojto 122:f9eeca106725 7079 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7080 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7081 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
Kojto 122:f9eeca106725 7082 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7083 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
Kojto 122:f9eeca106725 7084 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7085 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7086 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
Kojto 122:f9eeca106725 7087 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7088 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
Kojto 122:f9eeca106725 7089 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7090 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7091 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
Kojto 122:f9eeca106725 7092 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7093 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
Kojto 122:f9eeca106725 7094 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7095 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7096 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
Kojto 122:f9eeca106725 7097 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7098 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
Kojto 122:f9eeca106725 7099 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7100 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7101 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
Kojto 122:f9eeca106725 7102 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7103 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
Kojto 122:f9eeca106725 7104 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7105 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7106 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
Kojto 122:f9eeca106725 7107 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7108 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
Kojto 122:f9eeca106725 7109 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7110 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7111 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
Kojto 122:f9eeca106725 7112 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7113 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
Kojto 122:f9eeca106725 7114 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7115 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7116 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
Kojto 122:f9eeca106725 7117 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7118 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
Kojto 122:f9eeca106725 7119 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7120 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7121 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
Kojto 122:f9eeca106725 7122 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7123 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
Kojto 122:f9eeca106725 7124 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7125 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7126 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
Kojto 122:f9eeca106725 7127 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7128 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
Kojto 122:f9eeca106725 7129 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7130 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7131 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
Kojto 122:f9eeca106725 7132 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7133 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
Kojto 122:f9eeca106725 7134 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7135 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7136 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
Kojto 122:f9eeca106725 7137 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7138 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
Kojto 122:f9eeca106725 7139 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7140 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7141 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
Kojto 122:f9eeca106725 7142 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7143 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
Kojto 122:f9eeca106725 7144 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7145 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7146 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
Kojto 122:f9eeca106725 7147 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7148 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
Kojto 122:f9eeca106725 7149 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7150 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 7151
Kojto 90:cb3d968589d8 7152 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 90:cb3d968589d8 7153 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 90:cb3d968589d8 7154 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 90:cb3d968589d8 7155 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 90:cb3d968589d8 7156 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 90:cb3d968589d8 7157 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 90:cb3d968589d8 7158 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 90:cb3d968589d8 7159 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 90:cb3d968589d8 7160 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 90:cb3d968589d8 7161 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 90:cb3d968589d8 7162 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 90:cb3d968589d8 7163 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 90:cb3d968589d8 7164 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 90:cb3d968589d8 7165 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 90:cb3d968589d8 7166 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 90:cb3d968589d8 7167 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 90:cb3d968589d8 7168 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 90:cb3d968589d8 7169 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 90:cb3d968589d8 7170 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 90:cb3d968589d8 7171 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 90:cb3d968589d8 7172 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 90:cb3d968589d8 7173 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 90:cb3d968589d8 7174 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 90:cb3d968589d8 7175 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 90:cb3d968589d8 7176 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 90:cb3d968589d8 7177 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 90:cb3d968589d8 7178 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 90:cb3d968589d8 7179 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 90:cb3d968589d8 7180 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 90:cb3d968589d8 7181 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 90:cb3d968589d8 7182 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 90:cb3d968589d8 7183 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 90:cb3d968589d8 7184 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 90:cb3d968589d8 7185 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 90:cb3d968589d8 7186 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 90:cb3d968589d8 7187 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 90:cb3d968589d8 7188 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 90:cb3d968589d8 7189 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 90:cb3d968589d8 7190 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 90:cb3d968589d8 7191 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 90:cb3d968589d8 7192 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 90:cb3d968589d8 7193 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 90:cb3d968589d8 7194 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 90:cb3d968589d8 7195 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 90:cb3d968589d8 7196 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 90:cb3d968589d8 7197 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 90:cb3d968589d8 7198 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 90:cb3d968589d8 7199 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 90:cb3d968589d8 7200 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 90:cb3d968589d8 7201
Kojto 90:cb3d968589d8 7202 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 122:f9eeca106725 7203 #define GPIO_PUPDR_PUPDR0_Pos (0U)
Kojto 122:f9eeca106725 7204 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7205 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
Kojto 122:f9eeca106725 7206 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7207 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7208 #define GPIO_PUPDR_PUPDR1_Pos (2U)
Kojto 122:f9eeca106725 7209 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7210 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
Kojto 122:f9eeca106725 7211 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7212 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7213 #define GPIO_PUPDR_PUPDR2_Pos (4U)
Kojto 122:f9eeca106725 7214 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7215 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
Kojto 122:f9eeca106725 7216 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7217 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7218 #define GPIO_PUPDR_PUPDR3_Pos (6U)
Kojto 122:f9eeca106725 7219 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7220 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
Kojto 122:f9eeca106725 7221 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7222 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7223 #define GPIO_PUPDR_PUPDR4_Pos (8U)
Kojto 122:f9eeca106725 7224 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7225 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
Kojto 122:f9eeca106725 7226 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7227 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7228 #define GPIO_PUPDR_PUPDR5_Pos (10U)
Kojto 122:f9eeca106725 7229 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7230 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
Kojto 122:f9eeca106725 7231 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7232 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7233 #define GPIO_PUPDR_PUPDR6_Pos (12U)
Kojto 122:f9eeca106725 7234 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7235 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
Kojto 122:f9eeca106725 7236 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7237 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7238 #define GPIO_PUPDR_PUPDR7_Pos (14U)
Kojto 122:f9eeca106725 7239 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7240 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
Kojto 122:f9eeca106725 7241 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7242 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7243 #define GPIO_PUPDR_PUPDR8_Pos (16U)
Kojto 122:f9eeca106725 7244 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7245 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
Kojto 122:f9eeca106725 7246 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7247 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7248 #define GPIO_PUPDR_PUPDR9_Pos (18U)
Kojto 122:f9eeca106725 7249 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7250 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
Kojto 122:f9eeca106725 7251 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7252 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7253 #define GPIO_PUPDR_PUPDR10_Pos (20U)
Kojto 122:f9eeca106725 7254 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7255 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
Kojto 122:f9eeca106725 7256 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7257 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7258 #define GPIO_PUPDR_PUPDR11_Pos (22U)
Kojto 122:f9eeca106725 7259 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7260 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
Kojto 122:f9eeca106725 7261 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7262 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7263 #define GPIO_PUPDR_PUPDR12_Pos (24U)
Kojto 122:f9eeca106725 7264 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7265 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
Kojto 122:f9eeca106725 7266 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7267 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7268 #define GPIO_PUPDR_PUPDR13_Pos (26U)
Kojto 122:f9eeca106725 7269 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7270 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
Kojto 122:f9eeca106725 7271 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7272 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7273 #define GPIO_PUPDR_PUPDR14_Pos (28U)
Kojto 122:f9eeca106725 7274 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7275 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
Kojto 122:f9eeca106725 7276 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7277 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7278 #define GPIO_PUPDR_PUPDR15_Pos (30U)
Kojto 122:f9eeca106725 7279 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7280 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
Kojto 122:f9eeca106725 7281 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7282 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 7283
Kojto 90:cb3d968589d8 7284 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 7285 #define GPIO_IDR_0 (0x00000001U)
Kojto 122:f9eeca106725 7286 #define GPIO_IDR_1 (0x00000002U)
Kojto 122:f9eeca106725 7287 #define GPIO_IDR_2 (0x00000004U)
Kojto 122:f9eeca106725 7288 #define GPIO_IDR_3 (0x00000008U)
Kojto 122:f9eeca106725 7289 #define GPIO_IDR_4 (0x00000010U)
Kojto 122:f9eeca106725 7290 #define GPIO_IDR_5 (0x00000020U)
Kojto 122:f9eeca106725 7291 #define GPIO_IDR_6 (0x00000040U)
Kojto 122:f9eeca106725 7292 #define GPIO_IDR_7 (0x00000080U)
Kojto 122:f9eeca106725 7293 #define GPIO_IDR_8 (0x00000100U)
Kojto 122:f9eeca106725 7294 #define GPIO_IDR_9 (0x00000200U)
Kojto 122:f9eeca106725 7295 #define GPIO_IDR_10 (0x00000400U)
Kojto 122:f9eeca106725 7296 #define GPIO_IDR_11 (0x00000800U)
Kojto 122:f9eeca106725 7297 #define GPIO_IDR_12 (0x00001000U)
Kojto 122:f9eeca106725 7298 #define GPIO_IDR_13 (0x00002000U)
Kojto 122:f9eeca106725 7299 #define GPIO_IDR_14 (0x00004000U)
Kojto 122:f9eeca106725 7300 #define GPIO_IDR_15 (0x00008000U)
Kojto 90:cb3d968589d8 7301
Kojto 90:cb3d968589d8 7302 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 122:f9eeca106725 7303 #define GPIO_ODR_0 (0x00000001U)
Kojto 122:f9eeca106725 7304 #define GPIO_ODR_1 (0x00000002U)
Kojto 122:f9eeca106725 7305 #define GPIO_ODR_2 (0x00000004U)
Kojto 122:f9eeca106725 7306 #define GPIO_ODR_3 (0x00000008U)
Kojto 122:f9eeca106725 7307 #define GPIO_ODR_4 (0x00000010U)
Kojto 122:f9eeca106725 7308 #define GPIO_ODR_5 (0x00000020U)
Kojto 122:f9eeca106725 7309 #define GPIO_ODR_6 (0x00000040U)
Kojto 122:f9eeca106725 7310 #define GPIO_ODR_7 (0x00000080U)
Kojto 122:f9eeca106725 7311 #define GPIO_ODR_8 (0x00000100U)
Kojto 122:f9eeca106725 7312 #define GPIO_ODR_9 (0x00000200U)
Kojto 122:f9eeca106725 7313 #define GPIO_ODR_10 (0x00000400U)
Kojto 122:f9eeca106725 7314 #define GPIO_ODR_11 (0x00000800U)
Kojto 122:f9eeca106725 7315 #define GPIO_ODR_12 (0x00001000U)
Kojto 122:f9eeca106725 7316 #define GPIO_ODR_13 (0x00002000U)
Kojto 122:f9eeca106725 7317 #define GPIO_ODR_14 (0x00004000U)
Kojto 122:f9eeca106725 7318 #define GPIO_ODR_15 (0x00008000U)
Kojto 90:cb3d968589d8 7319
Kojto 90:cb3d968589d8 7320 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 122:f9eeca106725 7321 #define GPIO_BSRR_BS_0 (0x00000001U)
Kojto 122:f9eeca106725 7322 #define GPIO_BSRR_BS_1 (0x00000002U)
Kojto 122:f9eeca106725 7323 #define GPIO_BSRR_BS_2 (0x00000004U)
Kojto 122:f9eeca106725 7324 #define GPIO_BSRR_BS_3 (0x00000008U)
Kojto 122:f9eeca106725 7325 #define GPIO_BSRR_BS_4 (0x00000010U)
Kojto 122:f9eeca106725 7326 #define GPIO_BSRR_BS_5 (0x00000020U)
Kojto 122:f9eeca106725 7327 #define GPIO_BSRR_BS_6 (0x00000040U)
Kojto 122:f9eeca106725 7328 #define GPIO_BSRR_BS_7 (0x00000080U)
Kojto 122:f9eeca106725 7329 #define GPIO_BSRR_BS_8 (0x00000100U)
Kojto 122:f9eeca106725 7330 #define GPIO_BSRR_BS_9 (0x00000200U)
Kojto 122:f9eeca106725 7331 #define GPIO_BSRR_BS_10 (0x00000400U)
Kojto 122:f9eeca106725 7332 #define GPIO_BSRR_BS_11 (0x00000800U)
Kojto 122:f9eeca106725 7333 #define GPIO_BSRR_BS_12 (0x00001000U)
Kojto 122:f9eeca106725 7334 #define GPIO_BSRR_BS_13 (0x00002000U)
Kojto 122:f9eeca106725 7335 #define GPIO_BSRR_BS_14 (0x00004000U)
Kojto 122:f9eeca106725 7336 #define GPIO_BSRR_BS_15 (0x00008000U)
Kojto 122:f9eeca106725 7337 #define GPIO_BSRR_BR_0 (0x00010000U)
Kojto 122:f9eeca106725 7338 #define GPIO_BSRR_BR_1 (0x00020000U)
Kojto 122:f9eeca106725 7339 #define GPIO_BSRR_BR_2 (0x00040000U)
Kojto 122:f9eeca106725 7340 #define GPIO_BSRR_BR_3 (0x00080000U)
Kojto 122:f9eeca106725 7341 #define GPIO_BSRR_BR_4 (0x00100000U)
Kojto 122:f9eeca106725 7342 #define GPIO_BSRR_BR_5 (0x00200000U)
Kojto 122:f9eeca106725 7343 #define GPIO_BSRR_BR_6 (0x00400000U)
Kojto 122:f9eeca106725 7344 #define GPIO_BSRR_BR_7 (0x00800000U)
Kojto 122:f9eeca106725 7345 #define GPIO_BSRR_BR_8 (0x01000000U)
Kojto 122:f9eeca106725 7346 #define GPIO_BSRR_BR_9 (0x02000000U)
Kojto 122:f9eeca106725 7347 #define GPIO_BSRR_BR_10 (0x04000000U)
Kojto 122:f9eeca106725 7348 #define GPIO_BSRR_BR_11 (0x08000000U)
Kojto 122:f9eeca106725 7349 #define GPIO_BSRR_BR_12 (0x10000000U)
Kojto 122:f9eeca106725 7350 #define GPIO_BSRR_BR_13 (0x20000000U)
Kojto 122:f9eeca106725 7351 #define GPIO_BSRR_BR_14 (0x40000000U)
Kojto 122:f9eeca106725 7352 #define GPIO_BSRR_BR_15 (0x80000000U)
Kojto 90:cb3d968589d8 7353
Kojto 90:cb3d968589d8 7354 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 122:f9eeca106725 7355 #define GPIO_LCKR_LCK0_Pos (0U)
Kojto 122:f9eeca106725 7356 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7357 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
Kojto 122:f9eeca106725 7358 #define GPIO_LCKR_LCK1_Pos (1U)
Kojto 122:f9eeca106725 7359 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7360 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
Kojto 122:f9eeca106725 7361 #define GPIO_LCKR_LCK2_Pos (2U)
Kojto 122:f9eeca106725 7362 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7363 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
Kojto 122:f9eeca106725 7364 #define GPIO_LCKR_LCK3_Pos (3U)
Kojto 122:f9eeca106725 7365 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7366 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
Kojto 122:f9eeca106725 7367 #define GPIO_LCKR_LCK4_Pos (4U)
Kojto 122:f9eeca106725 7368 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7369 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
Kojto 122:f9eeca106725 7370 #define GPIO_LCKR_LCK5_Pos (5U)
Kojto 122:f9eeca106725 7371 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7372 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
Kojto 122:f9eeca106725 7373 #define GPIO_LCKR_LCK6_Pos (6U)
Kojto 122:f9eeca106725 7374 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7375 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
Kojto 122:f9eeca106725 7376 #define GPIO_LCKR_LCK7_Pos (7U)
Kojto 122:f9eeca106725 7377 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7378 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
Kojto 122:f9eeca106725 7379 #define GPIO_LCKR_LCK8_Pos (8U)
Kojto 122:f9eeca106725 7380 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7381 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
Kojto 122:f9eeca106725 7382 #define GPIO_LCKR_LCK9_Pos (9U)
Kojto 122:f9eeca106725 7383 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7384 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
Kojto 122:f9eeca106725 7385 #define GPIO_LCKR_LCK10_Pos (10U)
Kojto 122:f9eeca106725 7386 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7387 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
Kojto 122:f9eeca106725 7388 #define GPIO_LCKR_LCK11_Pos (11U)
Kojto 122:f9eeca106725 7389 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7390 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
Kojto 122:f9eeca106725 7391 #define GPIO_LCKR_LCK12_Pos (12U)
Kojto 122:f9eeca106725 7392 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7393 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
Kojto 122:f9eeca106725 7394 #define GPIO_LCKR_LCK13_Pos (13U)
Kojto 122:f9eeca106725 7395 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7396 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
Kojto 122:f9eeca106725 7397 #define GPIO_LCKR_LCK14_Pos (14U)
Kojto 122:f9eeca106725 7398 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7399 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
Kojto 122:f9eeca106725 7400 #define GPIO_LCKR_LCK15_Pos (15U)
Kojto 122:f9eeca106725 7401 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7402 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
Kojto 122:f9eeca106725 7403 #define GPIO_LCKR_LCKK_Pos (16U)
Kojto 122:f9eeca106725 7404 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7405 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
Kojto 90:cb3d968589d8 7406
Kojto 90:cb3d968589d8 7407 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 122:f9eeca106725 7408 #define GPIO_AFRL_AFRL0_Pos (0U)
Kojto 122:f9eeca106725 7409 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7410 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
Kojto 122:f9eeca106725 7411 #define GPIO_AFRL_AFRL1_Pos (4U)
Kojto 122:f9eeca106725 7412 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7413 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
Kojto 122:f9eeca106725 7414 #define GPIO_AFRL_AFRL2_Pos (8U)
Kojto 122:f9eeca106725 7415 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7416 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
Kojto 122:f9eeca106725 7417 #define GPIO_AFRL_AFRL3_Pos (12U)
Kojto 122:f9eeca106725 7418 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 7419 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
Kojto 122:f9eeca106725 7420 #define GPIO_AFRL_AFRL4_Pos (16U)
Kojto 122:f9eeca106725 7421 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7422 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
Kojto 122:f9eeca106725 7423 #define GPIO_AFRL_AFRL5_Pos (20U)
Kojto 122:f9eeca106725 7424 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 7425 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
Kojto 122:f9eeca106725 7426 #define GPIO_AFRL_AFRL6_Pos (24U)
Kojto 122:f9eeca106725 7427 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 7428 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
Kojto 122:f9eeca106725 7429 #define GPIO_AFRL_AFRL7_Pos (28U)
Kojto 122:f9eeca106725 7430 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 7431 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
Kojto 90:cb3d968589d8 7432
Kojto 90:cb3d968589d8 7433 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 122:f9eeca106725 7434 #define GPIO_AFRH_AFRH0_Pos (0U)
Kojto 122:f9eeca106725 7435 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7436 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
Kojto 122:f9eeca106725 7437 #define GPIO_AFRH_AFRH1_Pos (4U)
Kojto 122:f9eeca106725 7438 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7439 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
Kojto 122:f9eeca106725 7440 #define GPIO_AFRH_AFRH2_Pos (8U)
Kojto 122:f9eeca106725 7441 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7442 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
Kojto 122:f9eeca106725 7443 #define GPIO_AFRH_AFRH3_Pos (12U)
Kojto 122:f9eeca106725 7444 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 7445 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
Kojto 122:f9eeca106725 7446 #define GPIO_AFRH_AFRH4_Pos (16U)
Kojto 122:f9eeca106725 7447 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7448 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
Kojto 122:f9eeca106725 7449 #define GPIO_AFRH_AFRH5_Pos (20U)
Kojto 122:f9eeca106725 7450 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 7451 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
Kojto 122:f9eeca106725 7452 #define GPIO_AFRH_AFRH6_Pos (24U)
Kojto 122:f9eeca106725 7453 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 7454 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
Kojto 122:f9eeca106725 7455 #define GPIO_AFRH_AFRH7_Pos (28U)
Kojto 122:f9eeca106725 7456 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 7457 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
Kojto 90:cb3d968589d8 7458
Kojto 90:cb3d968589d8 7459 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 122:f9eeca106725 7460 #define GPIO_BRR_BR_0 (0x00000001U)
Kojto 122:f9eeca106725 7461 #define GPIO_BRR_BR_1 (0x00000002U)
Kojto 122:f9eeca106725 7462 #define GPIO_BRR_BR_2 (0x00000004U)
Kojto 122:f9eeca106725 7463 #define GPIO_BRR_BR_3 (0x00000008U)
Kojto 122:f9eeca106725 7464 #define GPIO_BRR_BR_4 (0x00000010U)
Kojto 122:f9eeca106725 7465 #define GPIO_BRR_BR_5 (0x00000020U)
Kojto 122:f9eeca106725 7466 #define GPIO_BRR_BR_6 (0x00000040U)
Kojto 122:f9eeca106725 7467 #define GPIO_BRR_BR_7 (0x00000080U)
Kojto 122:f9eeca106725 7468 #define GPIO_BRR_BR_8 (0x00000100U)
Kojto 122:f9eeca106725 7469 #define GPIO_BRR_BR_9 (0x00000200U)
Kojto 122:f9eeca106725 7470 #define GPIO_BRR_BR_10 (0x00000400U)
Kojto 122:f9eeca106725 7471 #define GPIO_BRR_BR_11 (0x00000800U)
Kojto 122:f9eeca106725 7472 #define GPIO_BRR_BR_12 (0x00001000U)
Kojto 122:f9eeca106725 7473 #define GPIO_BRR_BR_13 (0x00002000U)
Kojto 122:f9eeca106725 7474 #define GPIO_BRR_BR_14 (0x00004000U)
Kojto 122:f9eeca106725 7475 #define GPIO_BRR_BR_15 (0x00008000U)
Kojto 90:cb3d968589d8 7476
Kojto 90:cb3d968589d8 7477 /******************************************************************************/
Kojto 90:cb3d968589d8 7478 /* */
Kojto 90:cb3d968589d8 7479 /* Inter-integrated Circuit Interface (I2C) */
Kojto 90:cb3d968589d8 7480 /* */
Kojto 90:cb3d968589d8 7481 /******************************************************************************/
Kojto 90:cb3d968589d8 7482
Kojto 90:cb3d968589d8 7483 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 7484 #define I2C_CR1_PE_Pos (0U)
Kojto 122:f9eeca106725 7485 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7486 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
Kojto 122:f9eeca106725 7487 #define I2C_CR1_TXIE_Pos (1U)
Kojto 122:f9eeca106725 7488 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7489 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
Kojto 122:f9eeca106725 7490 #define I2C_CR1_RXIE_Pos (2U)
Kojto 122:f9eeca106725 7491 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7492 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
Kojto 122:f9eeca106725 7493 #define I2C_CR1_ADDRIE_Pos (3U)
Kojto 122:f9eeca106725 7494 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7495 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 7496 #define I2C_CR1_NACKIE_Pos (4U)
Kojto 122:f9eeca106725 7497 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7498 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 7499 #define I2C_CR1_STOPIE_Pos (5U)
Kojto 122:f9eeca106725 7500 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7501 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 7502 #define I2C_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 7503 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7504 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 7505 #define I2C_CR1_ERRIE_Pos (7U)
Kojto 122:f9eeca106725 7506 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7507 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 7508 #define I2C_CR1_DNF_Pos (8U)
Kojto 122:f9eeca106725 7509 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7510 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
Kojto 122:f9eeca106725 7511 #define I2C_CR1_ANFOFF_Pos (12U)
Kojto 122:f9eeca106725 7512 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7513 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 7514 #define I2C_CR1_SWRST_Pos (13U)
Kojto 122:f9eeca106725 7515 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7516 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
Kojto 122:f9eeca106725 7517 #define I2C_CR1_TXDMAEN_Pos (14U)
Kojto 122:f9eeca106725 7518 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7519 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 7520 #define I2C_CR1_RXDMAEN_Pos (15U)
Kojto 122:f9eeca106725 7521 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7522 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 7523 #define I2C_CR1_SBC_Pos (16U)
Kojto 122:f9eeca106725 7524 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7525 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
Kojto 122:f9eeca106725 7526 #define I2C_CR1_NOSTRETCH_Pos (17U)
Kojto 122:f9eeca106725 7527 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7528 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
Kojto 122:f9eeca106725 7529 #define I2C_CR1_WUPEN_Pos (18U)
Kojto 122:f9eeca106725 7530 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7531 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
Kojto 122:f9eeca106725 7532 #define I2C_CR1_GCEN_Pos (19U)
Kojto 122:f9eeca106725 7533 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7534 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
Kojto 122:f9eeca106725 7535 #define I2C_CR1_SMBHEN_Pos (20U)
Kojto 122:f9eeca106725 7536 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7537 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
Kojto 122:f9eeca106725 7538 #define I2C_CR1_SMBDEN_Pos (21U)
Kojto 122:f9eeca106725 7539 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7540 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 7541 #define I2C_CR1_ALERTEN_Pos (22U)
Kojto 122:f9eeca106725 7542 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7543 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
Kojto 122:f9eeca106725 7544 #define I2C_CR1_PECEN_Pos (23U)
Kojto 122:f9eeca106725 7545 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7546 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
Kojto 90:cb3d968589d8 7547
Kojto 90:cb3d968589d8 7548 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 7549 #define I2C_CR2_SADD_Pos (0U)
Kojto 122:f9eeca106725 7550 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 7551 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 7552 #define I2C_CR2_RD_WRN_Pos (10U)
Kojto 122:f9eeca106725 7553 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7554 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 7555 #define I2C_CR2_ADD10_Pos (11U)
Kojto 122:f9eeca106725 7556 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7557 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 7558 #define I2C_CR2_HEAD10R_Pos (12U)
Kojto 122:f9eeca106725 7559 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7560 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 7561 #define I2C_CR2_START_Pos (13U)
Kojto 122:f9eeca106725 7562 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7563 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
Kojto 122:f9eeca106725 7564 #define I2C_CR2_STOP_Pos (14U)
Kojto 122:f9eeca106725 7565 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7566 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 7567 #define I2C_CR2_NACK_Pos (15U)
Kojto 122:f9eeca106725 7568 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7569 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 7570 #define I2C_CR2_NBYTES_Pos (16U)
Kojto 122:f9eeca106725 7571 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7572 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
Kojto 122:f9eeca106725 7573 #define I2C_CR2_RELOAD_Pos (24U)
Kojto 122:f9eeca106725 7574 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7575 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 7576 #define I2C_CR2_AUTOEND_Pos (25U)
Kojto 122:f9eeca106725 7577 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7578 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 7579 #define I2C_CR2_PECBYTE_Pos (26U)
Kojto 122:f9eeca106725 7580 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7581 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
Kojto 90:cb3d968589d8 7582
Kojto 90:cb3d968589d8 7583 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 7584 #define I2C_OAR1_OA1_Pos (0U)
Kojto 122:f9eeca106725 7585 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 7586 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
Kojto 122:f9eeca106725 7587 #define I2C_OAR1_OA1MODE_Pos (10U)
Kojto 122:f9eeca106725 7588 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7589 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 7590 #define I2C_OAR1_OA1EN_Pos (15U)
Kojto 122:f9eeca106725 7591 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7592 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
Kojto 90:cb3d968589d8 7593
Kojto 90:cb3d968589d8 7594 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 122:f9eeca106725 7595 #define I2C_OAR2_OA2_Pos (1U)
Kojto 122:f9eeca106725 7596 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
Kojto 122:f9eeca106725 7597 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
Kojto 122:f9eeca106725 7598 #define I2C_OAR2_OA2MSK_Pos (8U)
Kojto 122:f9eeca106725 7599 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 7600 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
Kojto 122:f9eeca106725 7601 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
Kojto 122:f9eeca106725 7602 #define I2C_OAR2_OA2MASK01_Pos (8U)
Kojto 122:f9eeca106725 7603 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7604 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 122:f9eeca106725 7605 #define I2C_OAR2_OA2MASK02_Pos (9U)
Kojto 122:f9eeca106725 7606 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7607 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 122:f9eeca106725 7608 #define I2C_OAR2_OA2MASK03_Pos (8U)
Kojto 122:f9eeca106725 7609 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7610 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 122:f9eeca106725 7611 #define I2C_OAR2_OA2MASK04_Pos (10U)
Kojto 122:f9eeca106725 7612 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7613 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 122:f9eeca106725 7614 #define I2C_OAR2_OA2MASK05_Pos (8U)
Kojto 122:f9eeca106725 7615 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 7616 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 122:f9eeca106725 7617 #define I2C_OAR2_OA2MASK06_Pos (9U)
Kojto 122:f9eeca106725 7618 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 7619 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 122:f9eeca106725 7620 #define I2C_OAR2_OA2MASK07_Pos (8U)
Kojto 122:f9eeca106725 7621 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 7622 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
Kojto 122:f9eeca106725 7623 #define I2C_OAR2_OA2EN_Pos (15U)
Kojto 122:f9eeca106725 7624 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7625 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
Kojto 90:cb3d968589d8 7626
Kojto 90:cb3d968589d8 7627 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 122:f9eeca106725 7628 #define I2C_TIMINGR_SCLL_Pos (0U)
Kojto 122:f9eeca106725 7629 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7630 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 7631 #define I2C_TIMINGR_SCLH_Pos (8U)
Kojto 122:f9eeca106725 7632 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 7633 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 7634 #define I2C_TIMINGR_SDADEL_Pos (16U)
Kojto 122:f9eeca106725 7635 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7636 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
Kojto 122:f9eeca106725 7637 #define I2C_TIMINGR_SCLDEL_Pos (20U)
Kojto 122:f9eeca106725 7638 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 7639 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
Kojto 122:f9eeca106725 7640 #define I2C_TIMINGR_PRESC_Pos (28U)
Kojto 122:f9eeca106725 7641 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 7642 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
Kojto 90:cb3d968589d8 7643
Kojto 90:cb3d968589d8 7644 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 122:f9eeca106725 7645 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
Kojto 122:f9eeca106725 7646 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 7647 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
Kojto 122:f9eeca106725 7648 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
Kojto 122:f9eeca106725 7649 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7650 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 7651 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
Kojto 122:f9eeca106725 7652 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7653 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
Kojto 122:f9eeca106725 7654 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
Kojto 122:f9eeca106725 7655 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 7656 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
Kojto 122:f9eeca106725 7657 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
Kojto 122:f9eeca106725 7658 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7659 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
Kojto 90:cb3d968589d8 7660
Kojto 90:cb3d968589d8 7661 /****************** Bit definition for I2C_ISR register ********************/
Kojto 122:f9eeca106725 7662 #define I2C_ISR_TXE_Pos (0U)
Kojto 122:f9eeca106725 7663 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7664 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
Kojto 122:f9eeca106725 7665 #define I2C_ISR_TXIS_Pos (1U)
Kojto 122:f9eeca106725 7666 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7667 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 7668 #define I2C_ISR_RXNE_Pos (2U)
Kojto 122:f9eeca106725 7669 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7670 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
Kojto 122:f9eeca106725 7671 #define I2C_ISR_ADDR_Pos (3U)
Kojto 122:f9eeca106725 7672 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7673 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
Kojto 122:f9eeca106725 7674 #define I2C_ISR_NACKF_Pos (4U)
Kojto 122:f9eeca106725 7675 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7676 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
Kojto 122:f9eeca106725 7677 #define I2C_ISR_STOPF_Pos (5U)
Kojto 122:f9eeca106725 7678 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7679 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
Kojto 122:f9eeca106725 7680 #define I2C_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 7681 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7682 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 7683 #define I2C_ISR_TCR_Pos (7U)
Kojto 122:f9eeca106725 7684 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7685 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
Kojto 122:f9eeca106725 7686 #define I2C_ISR_BERR_Pos (8U)
Kojto 122:f9eeca106725 7687 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7688 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
Kojto 122:f9eeca106725 7689 #define I2C_ISR_ARLO_Pos (9U)
Kojto 122:f9eeca106725 7690 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7691 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
Kojto 122:f9eeca106725 7692 #define I2C_ISR_OVR_Pos (10U)
Kojto 122:f9eeca106725 7693 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7694 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 7695 #define I2C_ISR_PECERR_Pos (11U)
Kojto 122:f9eeca106725 7696 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7697 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
Kojto 122:f9eeca106725 7698 #define I2C_ISR_TIMEOUT_Pos (12U)
Kojto 122:f9eeca106725 7699 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7700 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 7701 #define I2C_ISR_ALERT_Pos (13U)
Kojto 122:f9eeca106725 7702 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7703 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
Kojto 122:f9eeca106725 7704 #define I2C_ISR_BUSY_Pos (15U)
Kojto 122:f9eeca106725 7705 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7706 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
Kojto 122:f9eeca106725 7707 #define I2C_ISR_DIR_Pos (16U)
Kojto 122:f9eeca106725 7708 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7709 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 7710 #define I2C_ISR_ADDCODE_Pos (17U)
Kojto 122:f9eeca106725 7711 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 7712 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
Kojto 90:cb3d968589d8 7713
Kojto 90:cb3d968589d8 7714 /****************** Bit definition for I2C_ICR register ********************/
Kojto 122:f9eeca106725 7715 #define I2C_ICR_ADDRCF_Pos (3U)
Kojto 122:f9eeca106725 7716 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7717 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
Kojto 122:f9eeca106725 7718 #define I2C_ICR_NACKCF_Pos (4U)
Kojto 122:f9eeca106725 7719 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7720 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
Kojto 122:f9eeca106725 7721 #define I2C_ICR_STOPCF_Pos (5U)
Kojto 122:f9eeca106725 7722 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7723 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 7724 #define I2C_ICR_BERRCF_Pos (8U)
Kojto 122:f9eeca106725 7725 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7726 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
Kojto 122:f9eeca106725 7727 #define I2C_ICR_ARLOCF_Pos (9U)
Kojto 122:f9eeca106725 7728 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7729 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 7730 #define I2C_ICR_OVRCF_Pos (10U)
Kojto 122:f9eeca106725 7731 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7732 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 7733 #define I2C_ICR_PECCF_Pos (11U)
Kojto 122:f9eeca106725 7734 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7735 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
Kojto 122:f9eeca106725 7736 #define I2C_ICR_TIMOUTCF_Pos (12U)
Kojto 122:f9eeca106725 7737 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7738 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
Kojto 122:f9eeca106725 7739 #define I2C_ICR_ALERTCF_Pos (13U)
Kojto 122:f9eeca106725 7740 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7741 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
Kojto 90:cb3d968589d8 7742
Kojto 90:cb3d968589d8 7743 /****************** Bit definition for I2C_PECR register *******************/
Kojto 122:f9eeca106725 7744 #define I2C_PECR_PEC_Pos (0U)
Kojto 122:f9eeca106725 7745 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7746 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
Kojto 90:cb3d968589d8 7747
Kojto 90:cb3d968589d8 7748 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 7749 #define I2C_RXDR_RXDATA_Pos (0U)
Kojto 122:f9eeca106725 7750 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7751 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
Kojto 90:cb3d968589d8 7752
Kojto 90:cb3d968589d8 7753 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 122:f9eeca106725 7754 #define I2C_TXDR_TXDATA_Pos (0U)
Kojto 122:f9eeca106725 7755 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7756 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
Kojto 90:cb3d968589d8 7757
Kojto 90:cb3d968589d8 7758 /*****************************************************************************/
Kojto 90:cb3d968589d8 7759 /* */
Kojto 90:cb3d968589d8 7760 /* Independent WATCHDOG (IWDG) */
Kojto 90:cb3d968589d8 7761 /* */
Kojto 90:cb3d968589d8 7762 /*****************************************************************************/
Kojto 90:cb3d968589d8 7763 /******************* Bit definition for IWDG_KR register *******************/
Kojto 122:f9eeca106725 7764 #define IWDG_KR_KEY_Pos (0U)
Kojto 122:f9eeca106725 7765 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 7766 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
Kojto 90:cb3d968589d8 7767
Kojto 90:cb3d968589d8 7768 /******************* Bit definition for IWDG_PR register *******************/
Kojto 122:f9eeca106725 7769 #define IWDG_PR_PR_Pos (0U)
Kojto 122:f9eeca106725 7770 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 7771 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 7772 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
Kojto 122:f9eeca106725 7773 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
Kojto 122:f9eeca106725 7774 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
Kojto 90:cb3d968589d8 7775
Kojto 90:cb3d968589d8 7776 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 122:f9eeca106725 7777 #define IWDG_RLR_RL_Pos (0U)
Kojto 122:f9eeca106725 7778 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 7779 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
Kojto 90:cb3d968589d8 7780
Kojto 90:cb3d968589d8 7781 /******************* Bit definition for IWDG_SR register *******************/
Kojto 122:f9eeca106725 7782 #define IWDG_SR_PVU_Pos (0U)
Kojto 122:f9eeca106725 7783 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7784 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 7785 #define IWDG_SR_RVU_Pos (1U)
Kojto 122:f9eeca106725 7786 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7787 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
Kojto 122:f9eeca106725 7788 #define IWDG_SR_WVU_Pos (2U)
Kojto 122:f9eeca106725 7789 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7790 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
Kojto 90:cb3d968589d8 7791
Kojto 90:cb3d968589d8 7792 /******************* Bit definition for IWDG_KR register *******************/
Kojto 122:f9eeca106725 7793 #define IWDG_WINR_WIN_Pos (0U)
Kojto 122:f9eeca106725 7794 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 7795 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
Kojto 90:cb3d968589d8 7796
Kojto 90:cb3d968589d8 7797 /*****************************************************************************/
Kojto 90:cb3d968589d8 7798 /* */
Kojto 90:cb3d968589d8 7799 /* Power Control (PWR) */
Kojto 90:cb3d968589d8 7800 /* */
Kojto 90:cb3d968589d8 7801 /*****************************************************************************/
Kojto 90:cb3d968589d8 7802
Kojto 122:f9eeca106725 7803 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
Kojto 122:f9eeca106725 7804
Kojto 122:f9eeca106725 7805
Kojto 90:cb3d968589d8 7806 /******************** Bit definition for PWR_CR register *******************/
Kojto 122:f9eeca106725 7807 #define PWR_CR_LPDS_Pos (0U)
Kojto 122:f9eeca106725 7808 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7809 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
Kojto 122:f9eeca106725 7810 #define PWR_CR_PDDS_Pos (1U)
Kojto 122:f9eeca106725 7811 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7812 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 7813 #define PWR_CR_CWUF_Pos (2U)
Kojto 122:f9eeca106725 7814 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7815 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 7816 #define PWR_CR_CSBF_Pos (3U)
Kojto 122:f9eeca106725 7817 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7818 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 7819 #define PWR_CR_PVDE_Pos (4U)
Kojto 122:f9eeca106725 7820 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7821 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 7822
Kojto 122:f9eeca106725 7823 #define PWR_CR_PLS_Pos (5U)
Kojto 122:f9eeca106725 7824 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 7825 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 7826 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7827 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7828 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
Kojto 90:cb3d968589d8 7829
Kojto 90:cb3d968589d8 7830 /*!< PVD level configuration */
Kojto 122:f9eeca106725 7831 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
Kojto 122:f9eeca106725 7832 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
Kojto 122:f9eeca106725 7833 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
Kojto 122:f9eeca106725 7834 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
Kojto 122:f9eeca106725 7835 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
Kojto 122:f9eeca106725 7836 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
Kojto 122:f9eeca106725 7837 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
Kojto 122:f9eeca106725 7838 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
Kojto 122:f9eeca106725 7839
Kojto 122:f9eeca106725 7840 #define PWR_CR_DBP_Pos (8U)
Kojto 122:f9eeca106725 7841 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7842 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
Kojto 90:cb3d968589d8 7843
Kojto 90:cb3d968589d8 7844 /******************* Bit definition for PWR_CSR register *******************/
Kojto 122:f9eeca106725 7845 #define PWR_CSR_WUF_Pos (0U)
Kojto 122:f9eeca106725 7846 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7847 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
Kojto 122:f9eeca106725 7848 #define PWR_CSR_SBF_Pos (1U)
Kojto 122:f9eeca106725 7849 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7850 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
Kojto 122:f9eeca106725 7851 #define PWR_CSR_PVDO_Pos (2U)
Kojto 122:f9eeca106725 7852 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7853 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
Kojto 122:f9eeca106725 7854 #define PWR_CSR_VREFINTRDYF_Pos (3U)
Kojto 122:f9eeca106725 7855 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7856 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 122:f9eeca106725 7857
Kojto 122:f9eeca106725 7858 #define PWR_CSR_EWUP1_Pos (8U)
Kojto 122:f9eeca106725 7859 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7860 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
Kojto 122:f9eeca106725 7861 #define PWR_CSR_EWUP2_Pos (9U)
Kojto 122:f9eeca106725 7862 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7863 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
Kojto 122:f9eeca106725 7864 #define PWR_CSR_EWUP3_Pos (10U)
Kojto 122:f9eeca106725 7865 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7866 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
Kojto 122:f9eeca106725 7867 #define PWR_CSR_EWUP4_Pos (11U)
Kojto 122:f9eeca106725 7868 #define PWR_CSR_EWUP4_Msk (0x1U << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7869 #define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */
Kojto 122:f9eeca106725 7870 #define PWR_CSR_EWUP5_Pos (12U)
Kojto 122:f9eeca106725 7871 #define PWR_CSR_EWUP5_Msk (0x1U << PWR_CSR_EWUP5_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7872 #define PWR_CSR_EWUP5 PWR_CSR_EWUP5_Msk /*!< Enable WKUP pin 5 */
Kojto 122:f9eeca106725 7873 #define PWR_CSR_EWUP6_Pos (13U)
Kojto 122:f9eeca106725 7874 #define PWR_CSR_EWUP6_Msk (0x1U << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7875 #define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */
Kojto 122:f9eeca106725 7876 #define PWR_CSR_EWUP7_Pos (14U)
Kojto 122:f9eeca106725 7877 #define PWR_CSR_EWUP7_Msk (0x1U << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7878 #define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */
Kojto 122:f9eeca106725 7879 #define PWR_CSR_EWUP8_Pos (15U)
Kojto 122:f9eeca106725 7880 #define PWR_CSR_EWUP8_Msk (0x1U << PWR_CSR_EWUP8_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7881 #define PWR_CSR_EWUP8 PWR_CSR_EWUP8_Msk /*!< Enable WKUP pin 8 */
Kojto 90:cb3d968589d8 7882
Kojto 90:cb3d968589d8 7883 /*****************************************************************************/
Kojto 90:cb3d968589d8 7884 /* */
Kojto 90:cb3d968589d8 7885 /* Reset and Clock Control */
Kojto 90:cb3d968589d8 7886 /* */
Kojto 90:cb3d968589d8 7887 /*****************************************************************************/
Kojto 122:f9eeca106725 7888 /*
Kojto 122:f9eeca106725 7889 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 7890 */
Kojto 122:f9eeca106725 7891 #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
Kojto 122:f9eeca106725 7892 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */
Kojto 90:cb3d968589d8 7893
Kojto 90:cb3d968589d8 7894 /******************** Bit definition for RCC_CR register *******************/
Kojto 122:f9eeca106725 7895 #define RCC_CR_HSION_Pos (0U)
Kojto 122:f9eeca106725 7896 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7897 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
Kojto 122:f9eeca106725 7898 #define RCC_CR_HSIRDY_Pos (1U)
Kojto 122:f9eeca106725 7899 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7900 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
Kojto 122:f9eeca106725 7901
Kojto 122:f9eeca106725 7902 #define RCC_CR_HSITRIM_Pos (3U)
Kojto 122:f9eeca106725 7903 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
Kojto 122:f9eeca106725 7904 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
Kojto 122:f9eeca106725 7905 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7906 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7907 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7908 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7909 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7910
Kojto 122:f9eeca106725 7911 #define RCC_CR_HSICAL_Pos (8U)
Kojto 122:f9eeca106725 7912 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 7913 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
Kojto 122:f9eeca106725 7914 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7915 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7916 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7917 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7918 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7919 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7920 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7921 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7922
Kojto 122:f9eeca106725 7923 #define RCC_CR_HSEON_Pos (16U)
Kojto 122:f9eeca106725 7924 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7925 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
Kojto 122:f9eeca106725 7926 #define RCC_CR_HSERDY_Pos (17U)
Kojto 122:f9eeca106725 7927 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7928 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
Kojto 122:f9eeca106725 7929 #define RCC_CR_HSEBYP_Pos (18U)
Kojto 122:f9eeca106725 7930 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7931 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
Kojto 122:f9eeca106725 7932 #define RCC_CR_CSSON_Pos (19U)
Kojto 122:f9eeca106725 7933 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7934 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
Kojto 122:f9eeca106725 7935 #define RCC_CR_PLLON_Pos (24U)
Kojto 122:f9eeca106725 7936 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7937 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
Kojto 122:f9eeca106725 7938 #define RCC_CR_PLLRDY_Pos (25U)
Kojto 122:f9eeca106725 7939 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7940 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
Kojto 90:cb3d968589d8 7941
Kojto 90:cb3d968589d8 7942 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 90:cb3d968589d8 7943 /*!< SW configuration */
Kojto 122:f9eeca106725 7944 #define RCC_CFGR_SW_Pos (0U)
Kojto 122:f9eeca106725 7945 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7946 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 7947 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7948 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7949
Kojto 122:f9eeca106725 7950 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 7951 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 7952 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
Kojto 122:f9eeca106725 7953 #define RCC_CFGR_SW_HSI48 (0x00000003U) /*!< HSI48 selected as system clock */
Kojto 90:cb3d968589d8 7954
Kojto 90:cb3d968589d8 7955 /*!< SWS configuration */
Kojto 122:f9eeca106725 7956 #define RCC_CFGR_SWS_Pos (2U)
Kojto 122:f9eeca106725 7957 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7958 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 7959 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7960 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7961
Kojto 122:f9eeca106725 7962 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 7963 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 7964 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
Kojto 122:f9eeca106725 7965 #define RCC_CFGR_SWS_HSI48 (0x0000000CU) /*!< HSI48 oscillator used as system clock */
Kojto 90:cb3d968589d8 7966
Kojto 90:cb3d968589d8 7967 /*!< HPRE configuration */
Kojto 122:f9eeca106725 7968 #define RCC_CFGR_HPRE_Pos (4U)
Kojto 122:f9eeca106725 7969 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7970 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 7971 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7972 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7973 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7974 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7975
Kojto 122:f9eeca106725 7976 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 7977 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 7978 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 7979 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 7980 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 7981 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 7982 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 7983 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 7984 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
Kojto 90:cb3d968589d8 7985
Kojto 90:cb3d968589d8 7986 /*!< PPRE configuration */
Kojto 122:f9eeca106725 7987 #define RCC_CFGR_PPRE_Pos (8U)
Kojto 122:f9eeca106725 7988 #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 7989 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
Kojto 122:f9eeca106725 7990 #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7991 #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7992 #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7993
Kojto 122:f9eeca106725 7994 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 7995 #define RCC_CFGR_PPRE_DIV2_Pos (10U)
Kojto 122:f9eeca106725 7996 #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7997 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 7998 #define RCC_CFGR_PPRE_DIV4_Pos (8U)
Kojto 122:f9eeca106725 7999 #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 8000 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 8001 #define RCC_CFGR_PPRE_DIV8_Pos (9U)
Kojto 122:f9eeca106725 8002 #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 8003 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 8004 #define RCC_CFGR_PPRE_DIV16_Pos (8U)
Kojto 122:f9eeca106725 8005 #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 8006 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 8007
Kojto 122:f9eeca106725 8008 #define RCC_CFGR_PLLSRC_Pos (15U)
Kojto 122:f9eeca106725 8009 #define RCC_CFGR_PLLSRC_Msk (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
Kojto 122:f9eeca106725 8010 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
Kojto 122:f9eeca106725 8011 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 122:f9eeca106725 8012 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 8013 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 8014 #define RCC_CFGR_PLLSRC_HSI48_PREDIV (0x00018000U) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 8015
Kojto 122:f9eeca106725 8016 #define RCC_CFGR_PLLXTPRE_Pos (17U)
Kojto 122:f9eeca106725 8017 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8018 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
Kojto 122:f9eeca106725 8019 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 122:f9eeca106725 8020 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 90:cb3d968589d8 8021
Kojto 90:cb3d968589d8 8022 /*!< PLLMUL configuration */
Kojto 122:f9eeca106725 8023 #define RCC_CFGR_PLLMUL_Pos (18U)
Kojto 122:f9eeca106725 8024 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
Kojto 122:f9eeca106725 8025 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 122:f9eeca106725 8026 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8027 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8028 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8029 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8030
Kojto 122:f9eeca106725 8031 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
Kojto 122:f9eeca106725 8032 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
Kojto 122:f9eeca106725 8033 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
Kojto 122:f9eeca106725 8034 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
Kojto 122:f9eeca106725 8035 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
Kojto 122:f9eeca106725 8036 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
Kojto 122:f9eeca106725 8037 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
Kojto 122:f9eeca106725 8038 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
Kojto 122:f9eeca106725 8039 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
Kojto 122:f9eeca106725 8040 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
Kojto 122:f9eeca106725 8041 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
Kojto 122:f9eeca106725 8042 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
Kojto 122:f9eeca106725 8043 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
Kojto 122:f9eeca106725 8044 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
Kojto 122:f9eeca106725 8045 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
Kojto 90:cb3d968589d8 8046
Kojto 90:cb3d968589d8 8047 /*!< MCO configuration */
Kojto 122:f9eeca106725 8048 #define RCC_CFGR_MCO_Pos (24U)
Kojto 122:f9eeca106725 8049 #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 8050 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 122:f9eeca106725 8051 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8052 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8053 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8054 #define RCC_CFGR_MCO_3 (0x08000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 8055
Kojto 122:f9eeca106725 8056 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 8057 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
Kojto 122:f9eeca106725 8058 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
Kojto 122:f9eeca106725 8059 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
Kojto 122:f9eeca106725 8060 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
Kojto 122:f9eeca106725 8061 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
Kojto 122:f9eeca106725 8062 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
Kojto 122:f9eeca106725 8063 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 122:f9eeca106725 8064 #define RCC_CFGR_MCO_HSI48 (0x08000000U) /*!< HSI48 clock selected as MCO source */
Kojto 122:f9eeca106725 8065
Kojto 122:f9eeca106725 8066 #define RCC_CFGR_MCOPRE_Pos (28U)
Kojto 122:f9eeca106725 8067 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
Kojto 122:f9eeca106725 8068 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
Kojto 122:f9eeca106725 8069 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
Kojto 122:f9eeca106725 8070 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
Kojto 122:f9eeca106725 8071 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
Kojto 122:f9eeca106725 8072 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
Kojto 122:f9eeca106725 8073 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
Kojto 122:f9eeca106725 8074 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
Kojto 122:f9eeca106725 8075 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
Kojto 122:f9eeca106725 8076 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
Kojto 122:f9eeca106725 8077
Kojto 122:f9eeca106725 8078 #define RCC_CFGR_PLLNODIV_Pos (31U)
Kojto 122:f9eeca106725 8079 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8080 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */
Kojto 122:f9eeca106725 8081
Kojto 122:f9eeca106725 8082 /* Reference defines */
Kojto 122:f9eeca106725 8083 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
Kojto 122:f9eeca106725 8084 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
Kojto 122:f9eeca106725 8085 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
Kojto 122:f9eeca106725 8086 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
Kojto 122:f9eeca106725 8087 #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
Kojto 122:f9eeca106725 8088 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 122:f9eeca106725 8089 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
Kojto 122:f9eeca106725 8090 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
Kojto 122:f9eeca106725 8091 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
Kojto 122:f9eeca106725 8092 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 122:f9eeca106725 8093 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
Kojto 122:f9eeca106725 8094 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
Kojto 122:f9eeca106725 8095 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
Kojto 122:f9eeca106725 8096 #define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCO_HSI48
Kojto 90:cb3d968589d8 8097
Kojto 90:cb3d968589d8 8098 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 122:f9eeca106725 8099 #define RCC_CIR_LSIRDYF_Pos (0U)
Kojto 122:f9eeca106725 8100 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8101 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 8102 #define RCC_CIR_LSERDYF_Pos (1U)
Kojto 122:f9eeca106725 8103 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8104 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 8105 #define RCC_CIR_HSIRDYF_Pos (2U)
Kojto 122:f9eeca106725 8106 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8107 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
Kojto 122:f9eeca106725 8108 #define RCC_CIR_HSERDYF_Pos (3U)
Kojto 122:f9eeca106725 8109 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8110 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 8111 #define RCC_CIR_PLLRDYF_Pos (4U)
Kojto 122:f9eeca106725 8112 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8113 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 8114 #define RCC_CIR_HSI14RDYF_Pos (5U)
Kojto 122:f9eeca106725 8115 #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8116 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
Kojto 122:f9eeca106725 8117 #define RCC_CIR_HSI48RDYF_Pos (6U)
Kojto 122:f9eeca106725 8118 #define RCC_CIR_HSI48RDYF_Msk (0x1U << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8119 #define RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
Kojto 122:f9eeca106725 8120 #define RCC_CIR_CSSF_Pos (7U)
Kojto 122:f9eeca106725 8121 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8122 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 8123 #define RCC_CIR_LSIRDYIE_Pos (8U)
Kojto 122:f9eeca106725 8124 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8125 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 8126 #define RCC_CIR_LSERDYIE_Pos (9U)
Kojto 122:f9eeca106725 8127 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8128 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 8129 #define RCC_CIR_HSIRDYIE_Pos (10U)
Kojto 122:f9eeca106725 8130 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8131 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 8132 #define RCC_CIR_HSERDYIE_Pos (11U)
Kojto 122:f9eeca106725 8133 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8134 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 8135 #define RCC_CIR_PLLRDYIE_Pos (12U)
Kojto 122:f9eeca106725 8136 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8137 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
Kojto 122:f9eeca106725 8138 #define RCC_CIR_HSI14RDYIE_Pos (13U)
Kojto 122:f9eeca106725 8139 #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8140 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
Kojto 122:f9eeca106725 8141 #define RCC_CIR_HSI48RDYIE_Pos (14U)
Kojto 122:f9eeca106725 8142 #define RCC_CIR_HSI48RDYIE_Msk (0x1U << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8143 #define RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
Kojto 122:f9eeca106725 8144 #define RCC_CIR_LSIRDYC_Pos (16U)
Kojto 122:f9eeca106725 8145 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8146 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 8147 #define RCC_CIR_LSERDYC_Pos (17U)
Kojto 122:f9eeca106725 8148 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8149 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 8150 #define RCC_CIR_HSIRDYC_Pos (18U)
Kojto 122:f9eeca106725 8151 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8152 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 8153 #define RCC_CIR_HSERDYC_Pos (19U)
Kojto 122:f9eeca106725 8154 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8155 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 8156 #define RCC_CIR_PLLRDYC_Pos (20U)
Kojto 122:f9eeca106725 8157 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8158 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
Kojto 122:f9eeca106725 8159 #define RCC_CIR_HSI14RDYC_Pos (21U)
Kojto 122:f9eeca106725 8160 #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8161 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
Kojto 122:f9eeca106725 8162 #define RCC_CIR_HSI48RDYC_Pos (22U)
Kojto 122:f9eeca106725 8163 #define RCC_CIR_HSI48RDYC_Msk (0x1U << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8164 #define RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
Kojto 122:f9eeca106725 8165 #define RCC_CIR_CSSC_Pos (23U)
Kojto 122:f9eeca106725 8166 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8167 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
Kojto 90:cb3d968589d8 8168
Kojto 90:cb3d968589d8 8169 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 122:f9eeca106725 8170 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
Kojto 122:f9eeca106725 8171 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8172 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
Kojto 122:f9eeca106725 8173 #define RCC_APB2RSTR_USART6RST_Pos (5U)
Kojto 122:f9eeca106725 8174 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8175 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 clock reset */
Kojto 122:f9eeca106725 8176 #define RCC_APB2RSTR_USART7RST_Pos (6U)
Kojto 122:f9eeca106725 8177 #define RCC_APB2RSTR_USART7RST_Msk (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8178 #define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 clock reset */
Kojto 122:f9eeca106725 8179 #define RCC_APB2RSTR_USART8RST_Pos (7U)
Kojto 122:f9eeca106725 8180 #define RCC_APB2RSTR_USART8RST_Msk (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8181 #define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 clock reset */
Kojto 122:f9eeca106725 8182 #define RCC_APB2RSTR_ADCRST_Pos (9U)
Kojto 122:f9eeca106725 8183 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8184 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */
Kojto 122:f9eeca106725 8185 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
Kojto 122:f9eeca106725 8186 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8187 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */
Kojto 122:f9eeca106725 8188 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
Kojto 122:f9eeca106725 8189 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8190 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
Kojto 122:f9eeca106725 8191 #define RCC_APB2RSTR_USART1RST_Pos (14U)
Kojto 122:f9eeca106725 8192 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8193 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
Kojto 122:f9eeca106725 8194 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
Kojto 122:f9eeca106725 8195 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8196 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */
Kojto 122:f9eeca106725 8197 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
Kojto 122:f9eeca106725 8198 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8199 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */
Kojto 122:f9eeca106725 8200 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
Kojto 122:f9eeca106725 8201 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8202 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */
Kojto 122:f9eeca106725 8203 #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
Kojto 122:f9eeca106725 8204 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8205 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */
Kojto 90:cb3d968589d8 8206
Kojto 90:cb3d968589d8 8207 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 8208 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 90:cb3d968589d8 8209
Kojto 90:cb3d968589d8 8210 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 122:f9eeca106725 8211 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
Kojto 122:f9eeca106725 8212 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8213 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
Kojto 122:f9eeca106725 8214 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
Kojto 122:f9eeca106725 8215 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8216 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
Kojto 122:f9eeca106725 8217 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
Kojto 122:f9eeca106725 8218 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8219 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
Kojto 122:f9eeca106725 8220 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
Kojto 122:f9eeca106725 8221 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8222 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */
Kojto 122:f9eeca106725 8223 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
Kojto 122:f9eeca106725 8224 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8225 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */
Kojto 122:f9eeca106725 8226 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
Kojto 122:f9eeca106725 8227 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8228 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
Kojto 122:f9eeca106725 8229 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
Kojto 122:f9eeca106725 8230 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8231 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
Kojto 122:f9eeca106725 8232 #define RCC_APB1RSTR_USART2RST_Pos (17U)
Kojto 122:f9eeca106725 8233 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8234 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
Kojto 122:f9eeca106725 8235 #define RCC_APB1RSTR_USART3RST_Pos (18U)
Kojto 122:f9eeca106725 8236 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8237 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */
Kojto 122:f9eeca106725 8238 #define RCC_APB1RSTR_USART4RST_Pos (19U)
Kojto 122:f9eeca106725 8239 #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8240 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */
Kojto 122:f9eeca106725 8241 #define RCC_APB1RSTR_USART5RST_Pos (20U)
Kojto 122:f9eeca106725 8242 #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8243 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 clock reset */
Kojto 122:f9eeca106725 8244 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
Kojto 122:f9eeca106725 8245 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8246 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
Kojto 122:f9eeca106725 8247 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
Kojto 122:f9eeca106725 8248 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8249 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
Kojto 122:f9eeca106725 8250 #define RCC_APB1RSTR_CANRST_Pos (25U)
Kojto 122:f9eeca106725 8251 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8252 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */
Kojto 122:f9eeca106725 8253 #define RCC_APB1RSTR_CRSRST_Pos (27U)
Kojto 122:f9eeca106725 8254 #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8255 #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */
Kojto 122:f9eeca106725 8256 #define RCC_APB1RSTR_PWRRST_Pos (28U)
Kojto 122:f9eeca106725 8257 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8258 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
Kojto 122:f9eeca106725 8259 #define RCC_APB1RSTR_DACRST_Pos (29U)
Kojto 122:f9eeca106725 8260 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8261 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
Kojto 122:f9eeca106725 8262 #define RCC_APB1RSTR_CECRST_Pos (30U)
Kojto 122:f9eeca106725 8263 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8264 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */
Kojto 90:cb3d968589d8 8265
Kojto 90:cb3d968589d8 8266 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 122:f9eeca106725 8267 #define RCC_AHBENR_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 8268 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8269 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
Kojto 122:f9eeca106725 8270 #define RCC_AHBENR_DMA2EN_Pos (1U)
Kojto 122:f9eeca106725 8271 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8272 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
Kojto 122:f9eeca106725 8273 #define RCC_AHBENR_SRAMEN_Pos (2U)
Kojto 122:f9eeca106725 8274 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8275 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
Kojto 122:f9eeca106725 8276 #define RCC_AHBENR_FLITFEN_Pos (4U)
Kojto 122:f9eeca106725 8277 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8278 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
Kojto 122:f9eeca106725 8279 #define RCC_AHBENR_CRCEN_Pos (6U)
Kojto 122:f9eeca106725 8280 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8281 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
Kojto 122:f9eeca106725 8282 #define RCC_AHBENR_GPIOAEN_Pos (17U)
Kojto 122:f9eeca106725 8283 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8284 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
Kojto 122:f9eeca106725 8285 #define RCC_AHBENR_GPIOBEN_Pos (18U)
Kojto 122:f9eeca106725 8286 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8287 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
Kojto 122:f9eeca106725 8288 #define RCC_AHBENR_GPIOCEN_Pos (19U)
Kojto 122:f9eeca106725 8289 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8290 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
Kojto 122:f9eeca106725 8291 #define RCC_AHBENR_GPIODEN_Pos (20U)
Kojto 122:f9eeca106725 8292 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8293 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
Kojto 122:f9eeca106725 8294 #define RCC_AHBENR_GPIOEEN_Pos (21U)
Kojto 122:f9eeca106725 8295 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8296 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIOE clock enable */
Kojto 122:f9eeca106725 8297 #define RCC_AHBENR_GPIOFEN_Pos (22U)
Kojto 122:f9eeca106725 8298 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8299 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
Kojto 122:f9eeca106725 8300 #define RCC_AHBENR_TSCEN_Pos (24U)
Kojto 122:f9eeca106725 8301 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8302 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller clock enable */
Kojto 90:cb3d968589d8 8303
Kojto 90:cb3d968589d8 8304 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 8305 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 90:cb3d968589d8 8306 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Kojto 90:cb3d968589d8 8307
Kojto 90:cb3d968589d8 8308 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 122:f9eeca106725 8309 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
Kojto 122:f9eeca106725 8310 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8311 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
Kojto 122:f9eeca106725 8312 #define RCC_APB2ENR_USART6EN_Pos (5U)
Kojto 122:f9eeca106725 8313 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8314 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 clock enable */
Kojto 122:f9eeca106725 8315 #define RCC_APB2ENR_USART7EN_Pos (6U)
Kojto 122:f9eeca106725 8316 #define RCC_APB2ENR_USART7EN_Msk (0x1U << RCC_APB2ENR_USART7EN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8317 #define RCC_APB2ENR_USART7EN RCC_APB2ENR_USART7EN_Msk /*!< USART7 clock enable */
Kojto 122:f9eeca106725 8318 #define RCC_APB2ENR_USART8EN_Pos (7U)
Kojto 122:f9eeca106725 8319 #define RCC_APB2ENR_USART8EN_Msk (0x1U << RCC_APB2ENR_USART8EN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8320 #define RCC_APB2ENR_USART8EN RCC_APB2ENR_USART8EN_Msk /*!< USART8 clock enable */
Kojto 122:f9eeca106725 8321 #define RCC_APB2ENR_ADCEN_Pos (9U)
Kojto 122:f9eeca106725 8322 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8323 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
Kojto 122:f9eeca106725 8324 #define RCC_APB2ENR_TIM1EN_Pos (11U)
Kojto 122:f9eeca106725 8325 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8326 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
Kojto 122:f9eeca106725 8327 #define RCC_APB2ENR_SPI1EN_Pos (12U)
Kojto 122:f9eeca106725 8328 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8329 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
Kojto 122:f9eeca106725 8330 #define RCC_APB2ENR_USART1EN_Pos (14U)
Kojto 122:f9eeca106725 8331 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8332 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
Kojto 122:f9eeca106725 8333 #define RCC_APB2ENR_TIM15EN_Pos (16U)
Kojto 122:f9eeca106725 8334 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8335 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
Kojto 122:f9eeca106725 8336 #define RCC_APB2ENR_TIM16EN_Pos (17U)
Kojto 122:f9eeca106725 8337 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8338 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
Kojto 122:f9eeca106725 8339 #define RCC_APB2ENR_TIM17EN_Pos (18U)
Kojto 122:f9eeca106725 8340 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8341 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
Kojto 122:f9eeca106725 8342 #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
Kojto 122:f9eeca106725 8343 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8344 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
Kojto 90:cb3d968589d8 8345
Kojto 90:cb3d968589d8 8346 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 8347 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 90:cb3d968589d8 8348 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 90:cb3d968589d8 8349
Kojto 90:cb3d968589d8 8350 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 122:f9eeca106725 8351 #define RCC_APB1ENR_TIM2EN_Pos (0U)
Kojto 122:f9eeca106725 8352 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8353 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
Kojto 122:f9eeca106725 8354 #define RCC_APB1ENR_TIM3EN_Pos (1U)
Kojto 122:f9eeca106725 8355 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8356 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
Kojto 122:f9eeca106725 8357 #define RCC_APB1ENR_TIM6EN_Pos (4U)
Kojto 122:f9eeca106725 8358 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8359 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
Kojto 122:f9eeca106725 8360 #define RCC_APB1ENR_TIM7EN_Pos (5U)
Kojto 122:f9eeca106725 8361 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8362 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
Kojto 122:f9eeca106725 8363 #define RCC_APB1ENR_TIM14EN_Pos (8U)
Kojto 122:f9eeca106725 8364 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8365 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
Kojto 122:f9eeca106725 8366 #define RCC_APB1ENR_WWDGEN_Pos (11U)
Kojto 122:f9eeca106725 8367 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8368 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
Kojto 122:f9eeca106725 8369 #define RCC_APB1ENR_SPI2EN_Pos (14U)
Kojto 122:f9eeca106725 8370 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8371 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
Kojto 122:f9eeca106725 8372 #define RCC_APB1ENR_USART2EN_Pos (17U)
Kojto 122:f9eeca106725 8373 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8374 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
Kojto 122:f9eeca106725 8375 #define RCC_APB1ENR_USART3EN_Pos (18U)
Kojto 122:f9eeca106725 8376 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8377 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART3 clock enable */
Kojto 122:f9eeca106725 8378 #define RCC_APB1ENR_USART4EN_Pos (19U)
Kojto 122:f9eeca106725 8379 #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8380 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
Kojto 122:f9eeca106725 8381 #define RCC_APB1ENR_USART5EN_Pos (20U)
Kojto 122:f9eeca106725 8382 #define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8383 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
Kojto 122:f9eeca106725 8384 #define RCC_APB1ENR_I2C1EN_Pos (21U)
Kojto 122:f9eeca106725 8385 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8386 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
Kojto 122:f9eeca106725 8387 #define RCC_APB1ENR_I2C2EN_Pos (22U)
Kojto 122:f9eeca106725 8388 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8389 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
Kojto 122:f9eeca106725 8390 #define RCC_APB1ENR_CANEN_Pos (25U)
Kojto 122:f9eeca106725 8391 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8392 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
Kojto 122:f9eeca106725 8393 #define RCC_APB1ENR_CRSEN_Pos (27U)
Kojto 122:f9eeca106725 8394 #define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8395 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
Kojto 122:f9eeca106725 8396 #define RCC_APB1ENR_PWREN_Pos (28U)
Kojto 122:f9eeca106725 8397 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8398 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
Kojto 122:f9eeca106725 8399 #define RCC_APB1ENR_DACEN_Pos (29U)
Kojto 122:f9eeca106725 8400 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8401 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
Kojto 122:f9eeca106725 8402 #define RCC_APB1ENR_CECEN_Pos (30U)
Kojto 122:f9eeca106725 8403 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8404 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enable */
Kojto 90:cb3d968589d8 8405
Kojto 90:cb3d968589d8 8406 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 8407 #define RCC_BDCR_LSEON_Pos (0U)
Kojto 122:f9eeca106725 8408 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8409 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
Kojto 122:f9eeca106725 8410 #define RCC_BDCR_LSERDY_Pos (1U)
Kojto 122:f9eeca106725 8411 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8412 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
Kojto 122:f9eeca106725 8413 #define RCC_BDCR_LSEBYP_Pos (2U)
Kojto 122:f9eeca106725 8414 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8415 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
Kojto 122:f9eeca106725 8416
Kojto 122:f9eeca106725 8417 #define RCC_BDCR_LSEDRV_Pos (3U)
Kojto 122:f9eeca106725 8418 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 8419 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 122:f9eeca106725 8420 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8421 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8422
Kojto 122:f9eeca106725 8423 #define RCC_BDCR_RTCSEL_Pos (8U)
Kojto 122:f9eeca106725 8424 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 8425 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 122:f9eeca106725 8426 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8427 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
Kojto 90:cb3d968589d8 8428
Kojto 90:cb3d968589d8 8429 /*!< RTC configuration */
Kojto 122:f9eeca106725 8430 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 8431 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 8432 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 8433 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 122:f9eeca106725 8434
Kojto 122:f9eeca106725 8435 #define RCC_BDCR_RTCEN_Pos (15U)
Kojto 122:f9eeca106725 8436 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8437 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
Kojto 122:f9eeca106725 8438 #define RCC_BDCR_BDRST_Pos (16U)
Kojto 122:f9eeca106725 8439 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8440 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
Kojto 90:cb3d968589d8 8441
Kojto 90:cb3d968589d8 8442 /******************* Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 8443 #define RCC_CSR_LSION_Pos (0U)
Kojto 122:f9eeca106725 8444 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8445 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
Kojto 122:f9eeca106725 8446 #define RCC_CSR_LSIRDY_Pos (1U)
Kojto 122:f9eeca106725 8447 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8448 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
Kojto 122:f9eeca106725 8449 #define RCC_CSR_V18PWRRSTF_Pos (23U)
Kojto 122:f9eeca106725 8450 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8451 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
Kojto 122:f9eeca106725 8452 #define RCC_CSR_RMVF_Pos (24U)
Kojto 122:f9eeca106725 8453 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8454 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
Kojto 122:f9eeca106725 8455 #define RCC_CSR_OBLRSTF_Pos (25U)
Kojto 122:f9eeca106725 8456 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8457 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
Kojto 122:f9eeca106725 8458 #define RCC_CSR_PINRSTF_Pos (26U)
Kojto 122:f9eeca106725 8459 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8460 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
Kojto 122:f9eeca106725 8461 #define RCC_CSR_PORRSTF_Pos (27U)
Kojto 122:f9eeca106725 8462 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8463 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
Kojto 122:f9eeca106725 8464 #define RCC_CSR_SFTRSTF_Pos (28U)
Kojto 122:f9eeca106725 8465 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8466 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
Kojto 122:f9eeca106725 8467 #define RCC_CSR_IWDGRSTF_Pos (29U)
Kojto 122:f9eeca106725 8468 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8469 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 8470 #define RCC_CSR_WWDGRSTF_Pos (30U)
Kojto 122:f9eeca106725 8471 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8472 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 8473 #define RCC_CSR_LPWRRSTF_Pos (31U)
Kojto 122:f9eeca106725 8474 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8475 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
Kojto 90:cb3d968589d8 8476
Kojto 90:cb3d968589d8 8477 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 8478 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 90:cb3d968589d8 8479
Kojto 90:cb3d968589d8 8480 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 122:f9eeca106725 8481 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
Kojto 122:f9eeca106725 8482 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8483 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */
Kojto 122:f9eeca106725 8484 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
Kojto 122:f9eeca106725 8485 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8486 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */
Kojto 122:f9eeca106725 8487 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
Kojto 122:f9eeca106725 8488 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8489 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */
Kojto 122:f9eeca106725 8490 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
Kojto 122:f9eeca106725 8491 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8492 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */
Kojto 122:f9eeca106725 8493 #define RCC_AHBRSTR_GPIOERST_Pos (21U)
Kojto 122:f9eeca106725 8494 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8495 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */
Kojto 122:f9eeca106725 8496 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
Kojto 122:f9eeca106725 8497 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8498 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */
Kojto 122:f9eeca106725 8499 #define RCC_AHBRSTR_TSCRST_Pos (24U)
Kojto 122:f9eeca106725 8500 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8501 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */
Kojto 90:cb3d968589d8 8502
Kojto 90:cb3d968589d8 8503 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 8504 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
Kojto 90:cb3d968589d8 8505
Kojto 90:cb3d968589d8 8506 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 90:cb3d968589d8 8507 /*!< PREDIV configuration */
Kojto 122:f9eeca106725 8508 #define RCC_CFGR2_PREDIV_Pos (0U)
Kojto 122:f9eeca106725 8509 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8510 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
Kojto 122:f9eeca106725 8511 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8512 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8513 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8514 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8515
Kojto 122:f9eeca106725 8516 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
Kojto 122:f9eeca106725 8517 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
Kojto 122:f9eeca106725 8518 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
Kojto 122:f9eeca106725 8519 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
Kojto 122:f9eeca106725 8520 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
Kojto 122:f9eeca106725 8521 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
Kojto 122:f9eeca106725 8522 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
Kojto 122:f9eeca106725 8523 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
Kojto 122:f9eeca106725 8524 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
Kojto 122:f9eeca106725 8525 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
Kojto 122:f9eeca106725 8526 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
Kojto 122:f9eeca106725 8527 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
Kojto 122:f9eeca106725 8528 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
Kojto 122:f9eeca106725 8529 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
Kojto 122:f9eeca106725 8530 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
Kojto 122:f9eeca106725 8531 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
Kojto 90:cb3d968589d8 8532
Kojto 90:cb3d968589d8 8533 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 90:cb3d968589d8 8534 /*!< USART1 Clock source selection */
Kojto 122:f9eeca106725 8535 #define RCC_CFGR3_USART1SW_Pos (0U)
Kojto 122:f9eeca106725 8536 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 8537 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
Kojto 122:f9eeca106725 8538 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8539 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8540
Kojto 122:f9eeca106725 8541 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
Kojto 122:f9eeca106725 8542 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
Kojto 122:f9eeca106725 8543 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 122:f9eeca106725 8544 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 90:cb3d968589d8 8545
Kojto 90:cb3d968589d8 8546 /*!< I2C1 Clock source selection */
Kojto 122:f9eeca106725 8547 #define RCC_CFGR3_I2C1SW_Pos (4U)
Kojto 122:f9eeca106725 8548 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8549 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
Kojto 122:f9eeca106725 8550
Kojto 122:f9eeca106725 8551 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 122:f9eeca106725 8552 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
Kojto 122:f9eeca106725 8553 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8554 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
Kojto 90:cb3d968589d8 8555
Kojto 90:cb3d968589d8 8556 /*!< CEC Clock source selection */
Kojto 122:f9eeca106725 8557 #define RCC_CFGR3_CECSW_Pos (6U)
Kojto 122:f9eeca106725 8558 #define RCC_CFGR3_CECSW_Msk (0x1U << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8559 #define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /*!< CECSW bits */
Kojto 122:f9eeca106725 8560
Kojto 122:f9eeca106725 8561 #define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
Kojto 122:f9eeca106725 8562 #define RCC_CFGR3_CECSW_LSE_Pos (6U)
Kojto 122:f9eeca106725 8563 #define RCC_CFGR3_CECSW_LSE_Msk (0x1U << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8564 #define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /*!< LSE clock selected as HDMI CEC entry clock source */
Kojto 90:cb3d968589d8 8565
Kojto 90:cb3d968589d8 8566 /*!< USART2 Clock source selection */
Kojto 122:f9eeca106725 8567 #define RCC_CFGR3_USART2SW_Pos (16U)
Kojto 122:f9eeca106725 8568 #define RCC_CFGR3_USART2SW_Msk (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 8569 #define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk /*!< USART2SW[1:0] bits */
Kojto 122:f9eeca106725 8570 #define RCC_CFGR3_USART2SW_0 (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8571 #define RCC_CFGR3_USART2SW_1 (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8572
Kojto 122:f9eeca106725 8573 #define RCC_CFGR3_USART2SW_PCLK (0x00000000U) /*!< PCLK clock used as USART2 clock source */
Kojto 122:f9eeca106725 8574 #define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U) /*!< System clock selected as USART2 clock source */
Kojto 122:f9eeca106725 8575 #define RCC_CFGR3_USART2SW_LSE (0x00020000U) /*!< LSE oscillator clock used as USART2 clock source */
Kojto 122:f9eeca106725 8576 #define RCC_CFGR3_USART2SW_HSI (0x00030000U) /*!< HSI oscillator clock used as USART2 clock source */
Kojto 90:cb3d968589d8 8577
Kojto 90:cb3d968589d8 8578 /*!< USART3 Clock source selection */
Kojto 122:f9eeca106725 8579 #define RCC_CFGR3_USART3SW_Pos (18U)
Kojto 122:f9eeca106725 8580 #define RCC_CFGR3_USART3SW_Msk (0x3U << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 8581 #define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk /*!< USART3SW[1:0] bits */
Kojto 122:f9eeca106725 8582 #define RCC_CFGR3_USART3SW_0 (0x1U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8583 #define RCC_CFGR3_USART3SW_1 (0x2U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8584
Kojto 122:f9eeca106725 8585 #define RCC_CFGR3_USART3SW_PCLK (0x00000000U) /*!< PCLK clock used as USART3 clock source */
Kojto 122:f9eeca106725 8586 #define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U) /*!< System clock selected as USART3 clock source */
Kojto 122:f9eeca106725 8587 #define RCC_CFGR3_USART3SW_LSE (0x00080000U) /*!< LSE oscillator clock used as USART3 clock source */
Kojto 122:f9eeca106725 8588 #define RCC_CFGR3_USART3SW_HSI (0x000C0000U) /*!< HSI oscillator clock used as USART3 clock source */
Kojto 90:cb3d968589d8 8589
Kojto 90:cb3d968589d8 8590 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 122:f9eeca106725 8591 #define RCC_CR2_HSI14ON_Pos (0U)
Kojto 122:f9eeca106725 8592 #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8593 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
Kojto 122:f9eeca106725 8594 #define RCC_CR2_HSI14RDY_Pos (1U)
Kojto 122:f9eeca106725 8595 #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8596 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
Kojto 122:f9eeca106725 8597 #define RCC_CR2_HSI14DIS_Pos (2U)
Kojto 122:f9eeca106725 8598 #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8599 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
Kojto 122:f9eeca106725 8600 #define RCC_CR2_HSI14TRIM_Pos (3U)
Kojto 122:f9eeca106725 8601 #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
Kojto 122:f9eeca106725 8602 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
Kojto 122:f9eeca106725 8603 #define RCC_CR2_HSI14CAL_Pos (8U)
Kojto 122:f9eeca106725 8604 #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 8605 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
Kojto 122:f9eeca106725 8606 #define RCC_CR2_HSI48ON_Pos (16U)
Kojto 122:f9eeca106725 8607 #define RCC_CR2_HSI48ON_Msk (0x1U << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8608 #define RCC_CR2_HSI48ON RCC_CR2_HSI48ON_Msk /*!< Internal High Speed 48MHz clock enable */
Kojto 122:f9eeca106725 8609 #define RCC_CR2_HSI48RDY_Pos (17U)
Kojto 122:f9eeca106725 8610 #define RCC_CR2_HSI48RDY_Msk (0x1U << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8611 #define RCC_CR2_HSI48RDY RCC_CR2_HSI48RDY_Msk /*!< Internal High Speed 48MHz clock ready flag */
Kojto 122:f9eeca106725 8612 #define RCC_CR2_HSI48CAL_Pos (24U)
Kojto 122:f9eeca106725 8613 #define RCC_CR2_HSI48CAL_Msk (0xFFU << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 8614 #define RCC_CR2_HSI48CAL RCC_CR2_HSI48CAL_Msk /*!< Internal High Speed 48MHz clock Calibration */
Kojto 90:cb3d968589d8 8615
Kojto 90:cb3d968589d8 8616 /*****************************************************************************/
Kojto 90:cb3d968589d8 8617 /* */
Kojto 90:cb3d968589d8 8618 /* Real-Time Clock (RTC) */
Kojto 90:cb3d968589d8 8619 /* */
Kojto 90:cb3d968589d8 8620 /*****************************************************************************/
Kojto 122:f9eeca106725 8621 /*
Kojto 122:f9eeca106725 8622 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 8623 */
Kojto 122:f9eeca106725 8624 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
Kojto 122:f9eeca106725 8625 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Kojto 122:f9eeca106725 8626 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
Kojto 122:f9eeca106725 8627 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
Kojto 122:f9eeca106725 8628 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
Kojto 122:f9eeca106725 8629
Kojto 90:cb3d968589d8 8630 /******************** Bits definition for RTC_TR register ******************/
Kojto 122:f9eeca106725 8631 #define RTC_TR_PM_Pos (22U)
Kojto 122:f9eeca106725 8632 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8633 #define RTC_TR_PM RTC_TR_PM_Msk
Kojto 122:f9eeca106725 8634 #define RTC_TR_HT_Pos (20U)
Kojto 122:f9eeca106725 8635 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 8636 #define RTC_TR_HT RTC_TR_HT_Msk
Kojto 122:f9eeca106725 8637 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8638 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8639 #define RTC_TR_HU_Pos (16U)
Kojto 122:f9eeca106725 8640 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8641 #define RTC_TR_HU RTC_TR_HU_Msk
Kojto 122:f9eeca106725 8642 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8643 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8644 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8645 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8646 #define RTC_TR_MNT_Pos (12U)
Kojto 122:f9eeca106725 8647 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 8648 #define RTC_TR_MNT RTC_TR_MNT_Msk
Kojto 122:f9eeca106725 8649 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8650 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8651 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8652 #define RTC_TR_MNU_Pos (8U)
Kojto 122:f9eeca106725 8653 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8654 #define RTC_TR_MNU RTC_TR_MNU_Msk
Kojto 122:f9eeca106725 8655 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8656 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8657 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8658 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8659 #define RTC_TR_ST_Pos (4U)
Kojto 122:f9eeca106725 8660 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 8661 #define RTC_TR_ST RTC_TR_ST_Msk
Kojto 122:f9eeca106725 8662 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8663 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8664 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8665 #define RTC_TR_SU_Pos (0U)
Kojto 122:f9eeca106725 8666 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8667 #define RTC_TR_SU RTC_TR_SU_Msk
Kojto 122:f9eeca106725 8668 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8669 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8670 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8671 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 8672
Kojto 90:cb3d968589d8 8673 /******************** Bits definition for RTC_DR register ******************/
Kojto 122:f9eeca106725 8674 #define RTC_DR_YT_Pos (20U)
Kojto 122:f9eeca106725 8675 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 8676 #define RTC_DR_YT RTC_DR_YT_Msk
Kojto 122:f9eeca106725 8677 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8678 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8679 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8680 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8681 #define RTC_DR_YU_Pos (16U)
Kojto 122:f9eeca106725 8682 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8683 #define RTC_DR_YU RTC_DR_YU_Msk
Kojto 122:f9eeca106725 8684 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8685 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8686 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8687 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8688 #define RTC_DR_WDU_Pos (13U)
Kojto 122:f9eeca106725 8689 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 8690 #define RTC_DR_WDU RTC_DR_WDU_Msk
Kojto 122:f9eeca106725 8691 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8692 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8693 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8694 #define RTC_DR_MT_Pos (12U)
Kojto 122:f9eeca106725 8695 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8696 #define RTC_DR_MT RTC_DR_MT_Msk
Kojto 122:f9eeca106725 8697 #define RTC_DR_MU_Pos (8U)
Kojto 122:f9eeca106725 8698 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8699 #define RTC_DR_MU RTC_DR_MU_Msk
Kojto 122:f9eeca106725 8700 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8701 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8702 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8703 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8704 #define RTC_DR_DT_Pos (4U)
Kojto 122:f9eeca106725 8705 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 8706 #define RTC_DR_DT RTC_DR_DT_Msk
Kojto 122:f9eeca106725 8707 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8708 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8709 #define RTC_DR_DU_Pos (0U)
Kojto 122:f9eeca106725 8710 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8711 #define RTC_DR_DU RTC_DR_DU_Msk
Kojto 122:f9eeca106725 8712 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8713 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8714 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8715 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 8716
Kojto 90:cb3d968589d8 8717 /******************** Bits definition for RTC_CR register ******************/
Kojto 122:f9eeca106725 8718 #define RTC_CR_COE_Pos (23U)
Kojto 122:f9eeca106725 8719 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8720 #define RTC_CR_COE RTC_CR_COE_Msk
Kojto 122:f9eeca106725 8721 #define RTC_CR_OSEL_Pos (21U)
Kojto 122:f9eeca106725 8722 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 8723 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
Kojto 122:f9eeca106725 8724 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8725 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8726 #define RTC_CR_POL_Pos (20U)
Kojto 122:f9eeca106725 8727 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8728 #define RTC_CR_POL RTC_CR_POL_Msk
Kojto 122:f9eeca106725 8729 #define RTC_CR_COSEL_Pos (19U)
Kojto 122:f9eeca106725 8730 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8731 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
Kojto 122:f9eeca106725 8732 #define RTC_CR_BCK_Pos (18U)
Kojto 122:f9eeca106725 8733 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8734 #define RTC_CR_BCK RTC_CR_BCK_Msk
Kojto 122:f9eeca106725 8735 #define RTC_CR_SUB1H_Pos (17U)
Kojto 122:f9eeca106725 8736 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8737 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
Kojto 122:f9eeca106725 8738 #define RTC_CR_ADD1H_Pos (16U)
Kojto 122:f9eeca106725 8739 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8740 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
Kojto 122:f9eeca106725 8741 #define RTC_CR_TSIE_Pos (15U)
Kojto 122:f9eeca106725 8742 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8743 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
Kojto 122:f9eeca106725 8744 #define RTC_CR_WUTIE_Pos (14U)
Kojto 122:f9eeca106725 8745 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8746 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
Kojto 122:f9eeca106725 8747 #define RTC_CR_ALRAIE_Pos (12U)
Kojto 122:f9eeca106725 8748 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8749 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
Kojto 122:f9eeca106725 8750 #define RTC_CR_TSE_Pos (11U)
Kojto 122:f9eeca106725 8751 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8752 #define RTC_CR_TSE RTC_CR_TSE_Msk
Kojto 122:f9eeca106725 8753 #define RTC_CR_WUTE_Pos (10U)
Kojto 122:f9eeca106725 8754 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8755 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
Kojto 122:f9eeca106725 8756 #define RTC_CR_ALRAE_Pos (8U)
Kojto 122:f9eeca106725 8757 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8758 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
Kojto 122:f9eeca106725 8759 #define RTC_CR_FMT_Pos (6U)
Kojto 122:f9eeca106725 8760 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8761 #define RTC_CR_FMT RTC_CR_FMT_Msk
Kojto 122:f9eeca106725 8762 #define RTC_CR_BYPSHAD_Pos (5U)
Kojto 122:f9eeca106725 8763 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8764 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
Kojto 122:f9eeca106725 8765 #define RTC_CR_REFCKON_Pos (4U)
Kojto 122:f9eeca106725 8766 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8767 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
Kojto 122:f9eeca106725 8768 #define RTC_CR_TSEDGE_Pos (3U)
Kojto 122:f9eeca106725 8769 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8770 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
Kojto 122:f9eeca106725 8771 #define RTC_CR_WUCKSEL_Pos (0U)
Kojto 122:f9eeca106725 8772 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 8773 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
Kojto 122:f9eeca106725 8774 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8775 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8776 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
Kojto 90:cb3d968589d8 8777
Kojto 90:cb3d968589d8 8778 /******************** Bits definition for RTC_ISR register *****************/
Kojto 122:f9eeca106725 8779 #define RTC_ISR_RECALPF_Pos (16U)
Kojto 122:f9eeca106725 8780 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8781 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
Kojto 122:f9eeca106725 8782 #define RTC_ISR_TAMP3F_Pos (15U)
Kojto 122:f9eeca106725 8783 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8784 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
Kojto 122:f9eeca106725 8785 #define RTC_ISR_TAMP2F_Pos (14U)
Kojto 122:f9eeca106725 8786 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8787 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
Kojto 122:f9eeca106725 8788 #define RTC_ISR_TAMP1F_Pos (13U)
Kojto 122:f9eeca106725 8789 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8790 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
Kojto 122:f9eeca106725 8791 #define RTC_ISR_TSOVF_Pos (12U)
Kojto 122:f9eeca106725 8792 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8793 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
Kojto 122:f9eeca106725 8794 #define RTC_ISR_TSF_Pos (11U)
Kojto 122:f9eeca106725 8795 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8796 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
Kojto 122:f9eeca106725 8797 #define RTC_ISR_WUTF_Pos (10U)
Kojto 122:f9eeca106725 8798 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8799 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
Kojto 122:f9eeca106725 8800 #define RTC_ISR_ALRAF_Pos (8U)
Kojto 122:f9eeca106725 8801 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8802 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
Kojto 122:f9eeca106725 8803 #define RTC_ISR_INIT_Pos (7U)
Kojto 122:f9eeca106725 8804 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8805 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
Kojto 122:f9eeca106725 8806 #define RTC_ISR_INITF_Pos (6U)
Kojto 122:f9eeca106725 8807 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8808 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
Kojto 122:f9eeca106725 8809 #define RTC_ISR_RSF_Pos (5U)
Kojto 122:f9eeca106725 8810 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8811 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
Kojto 122:f9eeca106725 8812 #define RTC_ISR_INITS_Pos (4U)
Kojto 122:f9eeca106725 8813 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8814 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
Kojto 122:f9eeca106725 8815 #define RTC_ISR_SHPF_Pos (3U)
Kojto 122:f9eeca106725 8816 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8817 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
Kojto 122:f9eeca106725 8818 #define RTC_ISR_WUTWF_Pos (2U)
Kojto 122:f9eeca106725 8819 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8820 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
Kojto 122:f9eeca106725 8821 #define RTC_ISR_ALRAWF_Pos (0U)
Kojto 122:f9eeca106725 8822 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8823 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
Kojto 90:cb3d968589d8 8824
Kojto 90:cb3d968589d8 8825 /******************** Bits definition for RTC_PRER register ****************/
Kojto 122:f9eeca106725 8826 #define RTC_PRER_PREDIV_A_Pos (16U)
Kojto 122:f9eeca106725 8827 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 8828 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
Kojto 122:f9eeca106725 8829 #define RTC_PRER_PREDIV_S_Pos (0U)
Kojto 122:f9eeca106725 8830 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 8831 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
Kojto 90:cb3d968589d8 8832
Kojto 90:cb3d968589d8 8833 /******************** Bits definition for RTC_WUTR register ****************/
Kojto 122:f9eeca106725 8834 #define RTC_WUTR_WUT_Pos (0U)
Kojto 122:f9eeca106725 8835 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 8836 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
Kojto 90:cb3d968589d8 8837
Kojto 90:cb3d968589d8 8838 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 122:f9eeca106725 8839 #define RTC_ALRMAR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 8840 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8841 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
Kojto 122:f9eeca106725 8842 #define RTC_ALRMAR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 8843 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8844 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
Kojto 122:f9eeca106725 8845 #define RTC_ALRMAR_DT_Pos (28U)
Kojto 122:f9eeca106725 8846 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 8847 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
Kojto 122:f9eeca106725 8848 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8849 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8850 #define RTC_ALRMAR_DU_Pos (24U)
Kojto 122:f9eeca106725 8851 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 8852 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
Kojto 122:f9eeca106725 8853 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8854 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8855 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8856 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8857 #define RTC_ALRMAR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 8858 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8859 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
Kojto 122:f9eeca106725 8860 #define RTC_ALRMAR_PM_Pos (22U)
Kojto 122:f9eeca106725 8861 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8862 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
Kojto 122:f9eeca106725 8863 #define RTC_ALRMAR_HT_Pos (20U)
Kojto 122:f9eeca106725 8864 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 8865 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
Kojto 122:f9eeca106725 8866 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8867 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8868 #define RTC_ALRMAR_HU_Pos (16U)
Kojto 122:f9eeca106725 8869 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8870 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
Kojto 122:f9eeca106725 8871 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8872 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8873 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8874 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8875 #define RTC_ALRMAR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 8876 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8877 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
Kojto 122:f9eeca106725 8878 #define RTC_ALRMAR_MNT_Pos (12U)
Kojto 122:f9eeca106725 8879 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 8880 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
Kojto 122:f9eeca106725 8881 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8882 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8883 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8884 #define RTC_ALRMAR_MNU_Pos (8U)
Kojto 122:f9eeca106725 8885 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8886 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
Kojto 122:f9eeca106725 8887 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8888 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8889 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8890 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8891 #define RTC_ALRMAR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 8892 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8893 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
Kojto 122:f9eeca106725 8894 #define RTC_ALRMAR_ST_Pos (4U)
Kojto 122:f9eeca106725 8895 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 8896 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
Kojto 122:f9eeca106725 8897 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8898 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8899 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8900 #define RTC_ALRMAR_SU_Pos (0U)
Kojto 122:f9eeca106725 8901 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8902 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
Kojto 122:f9eeca106725 8903 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8904 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8905 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8906 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 8907
Kojto 90:cb3d968589d8 8908 /******************** Bits definition for RTC_WPR register *****************/
Kojto 122:f9eeca106725 8909 #define RTC_WPR_KEY_Pos (0U)
Kojto 122:f9eeca106725 8910 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8911 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
Kojto 90:cb3d968589d8 8912
Kojto 90:cb3d968589d8 8913 /******************** Bits definition for RTC_SSR register *****************/
Kojto 122:f9eeca106725 8914 #define RTC_SSR_SS_Pos (0U)
Kojto 122:f9eeca106725 8915 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 8916 #define RTC_SSR_SS RTC_SSR_SS_Msk
Kojto 90:cb3d968589d8 8917
Kojto 90:cb3d968589d8 8918 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 122:f9eeca106725 8919 #define RTC_SHIFTR_SUBFS_Pos (0U)
Kojto 122:f9eeca106725 8920 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 8921 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
Kojto 122:f9eeca106725 8922 #define RTC_SHIFTR_ADD1S_Pos (31U)
Kojto 122:f9eeca106725 8923 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8924 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
Kojto 90:cb3d968589d8 8925
Kojto 90:cb3d968589d8 8926 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 122:f9eeca106725 8927 #define RTC_TSTR_PM_Pos (22U)
Kojto 122:f9eeca106725 8928 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8929 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
Kojto 122:f9eeca106725 8930 #define RTC_TSTR_HT_Pos (20U)
Kojto 122:f9eeca106725 8931 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 8932 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
Kojto 122:f9eeca106725 8933 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8934 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8935 #define RTC_TSTR_HU_Pos (16U)
Kojto 122:f9eeca106725 8936 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8937 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
Kojto 122:f9eeca106725 8938 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8939 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8940 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8941 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8942 #define RTC_TSTR_MNT_Pos (12U)
Kojto 122:f9eeca106725 8943 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 8944 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
Kojto 122:f9eeca106725 8945 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8946 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8947 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8948 #define RTC_TSTR_MNU_Pos (8U)
Kojto 122:f9eeca106725 8949 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8950 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
Kojto 122:f9eeca106725 8951 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8952 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8953 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8954 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8955 #define RTC_TSTR_ST_Pos (4U)
Kojto 122:f9eeca106725 8956 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 8957 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
Kojto 122:f9eeca106725 8958 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8959 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8960 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8961 #define RTC_TSTR_SU_Pos (0U)
Kojto 122:f9eeca106725 8962 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8963 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
Kojto 122:f9eeca106725 8964 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8965 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8966 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8967 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 8968
Kojto 90:cb3d968589d8 8969 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 122:f9eeca106725 8970 #define RTC_TSDR_WDU_Pos (13U)
Kojto 122:f9eeca106725 8971 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 8972 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
Kojto 122:f9eeca106725 8973 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8974 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8975 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8976 #define RTC_TSDR_MT_Pos (12U)
Kojto 122:f9eeca106725 8977 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8978 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
Kojto 122:f9eeca106725 8979 #define RTC_TSDR_MU_Pos (8U)
Kojto 122:f9eeca106725 8980 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8981 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
Kojto 122:f9eeca106725 8982 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8983 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8984 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8985 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8986 #define RTC_TSDR_DT_Pos (4U)
Kojto 122:f9eeca106725 8987 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 8988 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
Kojto 122:f9eeca106725 8989 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8990 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8991 #define RTC_TSDR_DU_Pos (0U)
Kojto 122:f9eeca106725 8992 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 8993 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
Kojto 122:f9eeca106725 8994 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8995 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8996 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8997 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 8998
Kojto 90:cb3d968589d8 8999 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 122:f9eeca106725 9000 #define RTC_TSSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 9001 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 9002 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
Kojto 90:cb3d968589d8 9003
Kojto 90:cb3d968589d8 9004 /******************** Bits definition for RTC_CALR register ****************/
Kojto 122:f9eeca106725 9005 #define RTC_CALR_CALP_Pos (15U)
Kojto 122:f9eeca106725 9006 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9007 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
Kojto 122:f9eeca106725 9008 #define RTC_CALR_CALW8_Pos (14U)
Kojto 122:f9eeca106725 9009 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9010 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
Kojto 122:f9eeca106725 9011 #define RTC_CALR_CALW16_Pos (13U)
Kojto 122:f9eeca106725 9012 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9013 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
Kojto 122:f9eeca106725 9014 #define RTC_CALR_CALM_Pos (0U)
Kojto 122:f9eeca106725 9015 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 9016 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
Kojto 122:f9eeca106725 9017 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9018 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9019 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9020 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9021 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9022 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9023 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9024 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9025 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
Kojto 90:cb3d968589d8 9026
Kojto 90:cb3d968589d8 9027 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 122:f9eeca106725 9028 #define RTC_TAFCR_PC15MODE_Pos (23U)
Kojto 122:f9eeca106725 9029 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9030 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
Kojto 122:f9eeca106725 9031 #define RTC_TAFCR_PC15VALUE_Pos (22U)
Kojto 122:f9eeca106725 9032 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9033 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
Kojto 122:f9eeca106725 9034 #define RTC_TAFCR_PC14MODE_Pos (21U)
Kojto 122:f9eeca106725 9035 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9036 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
Kojto 122:f9eeca106725 9037 #define RTC_TAFCR_PC14VALUE_Pos (20U)
Kojto 122:f9eeca106725 9038 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9039 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
Kojto 122:f9eeca106725 9040 #define RTC_TAFCR_PC13MODE_Pos (19U)
Kojto 122:f9eeca106725 9041 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9042 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
Kojto 122:f9eeca106725 9043 #define RTC_TAFCR_PC13VALUE_Pos (18U)
Kojto 122:f9eeca106725 9044 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9045 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
Kojto 122:f9eeca106725 9046 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
Kojto 122:f9eeca106725 9047 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9048 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
Kojto 122:f9eeca106725 9049 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
Kojto 122:f9eeca106725 9050 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 9051 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
Kojto 122:f9eeca106725 9052 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9053 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9054 #define RTC_TAFCR_TAMPFLT_Pos (11U)
Kojto 122:f9eeca106725 9055 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 9056 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
Kojto 122:f9eeca106725 9057 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9058 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9059 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
Kojto 122:f9eeca106725 9060 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 9061 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
Kojto 122:f9eeca106725 9062 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9063 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9064 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9065 #define RTC_TAFCR_TAMPTS_Pos (7U)
Kojto 122:f9eeca106725 9066 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9067 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
Kojto 122:f9eeca106725 9068 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
Kojto 122:f9eeca106725 9069 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9070 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
Kojto 122:f9eeca106725 9071 #define RTC_TAFCR_TAMP3E_Pos (5U)
Kojto 122:f9eeca106725 9072 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9073 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
Kojto 122:f9eeca106725 9074 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
Kojto 122:f9eeca106725 9075 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9076 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
Kojto 122:f9eeca106725 9077 #define RTC_TAFCR_TAMP2E_Pos (3U)
Kojto 122:f9eeca106725 9078 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9079 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
Kojto 122:f9eeca106725 9080 #define RTC_TAFCR_TAMPIE_Pos (2U)
Kojto 122:f9eeca106725 9081 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9082 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
Kojto 122:f9eeca106725 9083 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
Kojto 122:f9eeca106725 9084 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9085 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
Kojto 122:f9eeca106725 9086 #define RTC_TAFCR_TAMP1E_Pos (0U)
Kojto 122:f9eeca106725 9087 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9088 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
Kojto 122:f9eeca106725 9089
Kojto 122:f9eeca106725 9090 /* Reference defines */
Kojto 122:f9eeca106725 9091 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
Kojto 90:cb3d968589d8 9092
Kojto 90:cb3d968589d8 9093 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 122:f9eeca106725 9094 #define RTC_ALRMASSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 9095 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 9096 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
Kojto 122:f9eeca106725 9097 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9098 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9099 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9100 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9101 #define RTC_ALRMASSR_SS_Pos (0U)
Kojto 122:f9eeca106725 9102 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 9103 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
Kojto 90:cb3d968589d8 9104
Kojto 90:cb3d968589d8 9105 /******************** Bits definition for RTC_BKP0R register ***************/
Kojto 122:f9eeca106725 9106 #define RTC_BKP0R_Pos (0U)
Kojto 122:f9eeca106725 9107 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9108 #define RTC_BKP0R RTC_BKP0R_Msk
Kojto 90:cb3d968589d8 9109
Kojto 90:cb3d968589d8 9110 /******************** Bits definition for RTC_BKP1R register ***************/
Kojto 122:f9eeca106725 9111 #define RTC_BKP1R_Pos (0U)
Kojto 122:f9eeca106725 9112 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9113 #define RTC_BKP1R RTC_BKP1R_Msk
Kojto 90:cb3d968589d8 9114
Kojto 90:cb3d968589d8 9115 /******************** Bits definition for RTC_BKP2R register ***************/
Kojto 122:f9eeca106725 9116 #define RTC_BKP2R_Pos (0U)
Kojto 122:f9eeca106725 9117 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9118 #define RTC_BKP2R RTC_BKP2R_Msk
Kojto 90:cb3d968589d8 9119
Kojto 90:cb3d968589d8 9120 /******************** Bits definition for RTC_BKP3R register ***************/
Kojto 122:f9eeca106725 9121 #define RTC_BKP3R_Pos (0U)
Kojto 122:f9eeca106725 9122 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9123 #define RTC_BKP3R RTC_BKP3R_Msk
Kojto 90:cb3d968589d8 9124
Kojto 90:cb3d968589d8 9125 /******************** Bits definition for RTC_BKP4R register ***************/
Kojto 122:f9eeca106725 9126 #define RTC_BKP4R_Pos (0U)
Kojto 122:f9eeca106725 9127 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9128 #define RTC_BKP4R RTC_BKP4R_Msk
Kojto 90:cb3d968589d8 9129
Kojto 90:cb3d968589d8 9130 /******************** Number of backup registers ******************************/
Kojto 122:f9eeca106725 9131 #define RTC_BKP_NUMBER 0x00000005U
Kojto 90:cb3d968589d8 9132
Kojto 90:cb3d968589d8 9133 /*****************************************************************************/
Kojto 90:cb3d968589d8 9134 /* */
Kojto 90:cb3d968589d8 9135 /* Serial Peripheral Interface (SPI) */
Kojto 90:cb3d968589d8 9136 /* */
Kojto 90:cb3d968589d8 9137 /*****************************************************************************/
Kojto 122:f9eeca106725 9138
Kojto 122:f9eeca106725 9139 /*
Kojto 122:f9eeca106725 9140 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 9141 */
Kojto 122:f9eeca106725 9142 #define SPI_I2S_SUPPORT /*!< I2S support */
Kojto 122:f9eeca106725 9143
Kojto 90:cb3d968589d8 9144 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 122:f9eeca106725 9145 #define SPI_CR1_CPHA_Pos (0U)
Kojto 122:f9eeca106725 9146 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9147 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 9148 #define SPI_CR1_CPOL_Pos (1U)
Kojto 122:f9eeca106725 9149 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9150 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 9151 #define SPI_CR1_MSTR_Pos (2U)
Kojto 122:f9eeca106725 9152 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9153 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
Kojto 122:f9eeca106725 9154 #define SPI_CR1_BR_Pos (3U)
Kojto 122:f9eeca106725 9155 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 9156 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 9157 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9158 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9159 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9160 #define SPI_CR1_SPE_Pos (6U)
Kojto 122:f9eeca106725 9161 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9162 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Kojto 122:f9eeca106725 9163 #define SPI_CR1_LSBFIRST_Pos (7U)
Kojto 122:f9eeca106725 9164 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9165 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
Kojto 122:f9eeca106725 9166 #define SPI_CR1_SSI_Pos (8U)
Kojto 122:f9eeca106725 9167 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9168 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
Kojto 122:f9eeca106725 9169 #define SPI_CR1_SSM_Pos (9U)
Kojto 122:f9eeca106725 9170 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9171 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
Kojto 122:f9eeca106725 9172 #define SPI_CR1_RXONLY_Pos (10U)
Kojto 122:f9eeca106725 9173 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9174 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
Kojto 122:f9eeca106725 9175 #define SPI_CR1_CRCL_Pos (11U)
Kojto 122:f9eeca106725 9176 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9177 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Kojto 122:f9eeca106725 9178 #define SPI_CR1_CRCNEXT_Pos (12U)
Kojto 122:f9eeca106725 9179 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9180 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
Kojto 122:f9eeca106725 9181 #define SPI_CR1_CRCEN_Pos (13U)
Kojto 122:f9eeca106725 9182 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9183 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
Kojto 122:f9eeca106725 9184 #define SPI_CR1_BIDIOE_Pos (14U)
Kojto 122:f9eeca106725 9185 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9186 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
Kojto 122:f9eeca106725 9187 #define SPI_CR1_BIDIMODE_Pos (15U)
Kojto 122:f9eeca106725 9188 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9189 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
Kojto 90:cb3d968589d8 9190
Kojto 90:cb3d968589d8 9191 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 122:f9eeca106725 9192 #define SPI_CR2_RXDMAEN_Pos (0U)
Kojto 122:f9eeca106725 9193 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9194 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 9195 #define SPI_CR2_TXDMAEN_Pos (1U)
Kojto 122:f9eeca106725 9196 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9197 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 9198 #define SPI_CR2_SSOE_Pos (2U)
Kojto 122:f9eeca106725 9199 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9200 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
Kojto 122:f9eeca106725 9201 #define SPI_CR2_NSSP_Pos (3U)
Kojto 122:f9eeca106725 9202 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9203 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
Kojto 122:f9eeca106725 9204 #define SPI_CR2_FRF_Pos (4U)
Kojto 122:f9eeca106725 9205 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9206 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
Kojto 122:f9eeca106725 9207 #define SPI_CR2_ERRIE_Pos (5U)
Kojto 122:f9eeca106725 9208 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9209 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 9210 #define SPI_CR2_RXNEIE_Pos (6U)
Kojto 122:f9eeca106725 9211 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9212 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 9213 #define SPI_CR2_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 9214 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9215 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
Kojto 122:f9eeca106725 9216 #define SPI_CR2_DS_Pos (8U)
Kojto 122:f9eeca106725 9217 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9218 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
Kojto 122:f9eeca106725 9219 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9220 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9221 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9222 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9223 #define SPI_CR2_FRXTH_Pos (12U)
Kojto 122:f9eeca106725 9224 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9225 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
Kojto 122:f9eeca106725 9226 #define SPI_CR2_LDMARX_Pos (13U)
Kojto 122:f9eeca106725 9227 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9228 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
Kojto 122:f9eeca106725 9229 #define SPI_CR2_LDMATX_Pos (14U)
Kojto 122:f9eeca106725 9230 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9231 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
Kojto 90:cb3d968589d8 9232
Kojto 90:cb3d968589d8 9233 /******************** Bit definition for SPI_SR register *******************/
Kojto 122:f9eeca106725 9234 #define SPI_SR_RXNE_Pos (0U)
Kojto 122:f9eeca106725 9235 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9236 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 9237 #define SPI_SR_TXE_Pos (1U)
Kojto 122:f9eeca106725 9238 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9239 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 9240 #define SPI_SR_CHSIDE_Pos (2U)
Kojto 122:f9eeca106725 9241 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9242 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
Kojto 122:f9eeca106725 9243 #define SPI_SR_UDR_Pos (3U)
Kojto 122:f9eeca106725 9244 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9245 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Kojto 122:f9eeca106725 9246 #define SPI_SR_CRCERR_Pos (4U)
Kojto 122:f9eeca106725 9247 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9248 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
Kojto 122:f9eeca106725 9249 #define SPI_SR_MODF_Pos (5U)
Kojto 122:f9eeca106725 9250 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9251 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
Kojto 122:f9eeca106725 9252 #define SPI_SR_OVR_Pos (6U)
Kojto 122:f9eeca106725 9253 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9254 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
Kojto 122:f9eeca106725 9255 #define SPI_SR_BSY_Pos (7U)
Kojto 122:f9eeca106725 9256 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9257 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
Kojto 122:f9eeca106725 9258 #define SPI_SR_FRE_Pos (8U)
Kojto 122:f9eeca106725 9259 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9260 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
Kojto 122:f9eeca106725 9261 #define SPI_SR_FRLVL_Pos (9U)
Kojto 122:f9eeca106725 9262 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 9263 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
Kojto 122:f9eeca106725 9264 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9265 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9266 #define SPI_SR_FTLVL_Pos (11U)
Kojto 122:f9eeca106725 9267 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 9268 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
Kojto 122:f9eeca106725 9269 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9270 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
Kojto 90:cb3d968589d8 9271
Kojto 90:cb3d968589d8 9272 /******************** Bit definition for SPI_DR register *******************/
Kojto 122:f9eeca106725 9273 #define SPI_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 9274 #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9275 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Kojto 90:cb3d968589d8 9276
Kojto 90:cb3d968589d8 9277 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 122:f9eeca106725 9278 #define SPI_CRCPR_CRCPOLY_Pos (0U)
Kojto 122:f9eeca106725 9279 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9280 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
Kojto 90:cb3d968589d8 9281
Kojto 90:cb3d968589d8 9282 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 122:f9eeca106725 9283 #define SPI_RXCRCR_RXCRC_Pos (0U)
Kojto 122:f9eeca106725 9284 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9285 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
Kojto 90:cb3d968589d8 9286
Kojto 90:cb3d968589d8 9287 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 122:f9eeca106725 9288 #define SPI_TXCRCR_TXCRC_Pos (0U)
Kojto 122:f9eeca106725 9289 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 9290 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
Kojto 90:cb3d968589d8 9291
Kojto 90:cb3d968589d8 9292 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 122:f9eeca106725 9293 #define SPI_I2SCFGR_CHLEN_Pos (0U)
Kojto 122:f9eeca106725 9294 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9295 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 9296 #define SPI_I2SCFGR_DATLEN_Pos (1U)
Kojto 122:f9eeca106725 9297 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 9298 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 9299 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9300 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9301 #define SPI_I2SCFGR_CKPOL_Pos (3U)
Kojto 122:f9eeca106725 9302 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9303 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
Kojto 122:f9eeca106725 9304 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
Kojto 122:f9eeca106725 9305 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 9306 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 9307 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9308 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9309 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
Kojto 122:f9eeca106725 9310 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9311 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 9312 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
Kojto 122:f9eeca106725 9313 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 9314 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 9315 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9316 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9317 #define SPI_I2SCFGR_I2SE_Pos (10U)
Kojto 122:f9eeca106725 9318 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9319 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
Kojto 122:f9eeca106725 9320 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
Kojto 122:f9eeca106725 9321 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9322 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
Kojto 90:cb3d968589d8 9323
Kojto 90:cb3d968589d8 9324 /****************** Bit definition for SPI_I2SPR register ******************/
Kojto 122:f9eeca106725 9325 #define SPI_I2SPR_I2SDIV_Pos (0U)
Kojto 122:f9eeca106725 9326 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 9327 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 9328 #define SPI_I2SPR_ODD_Pos (8U)
Kojto 122:f9eeca106725 9329 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9330 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 9331 #define SPI_I2SPR_MCKOE_Pos (9U)
Kojto 122:f9eeca106725 9332 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9333 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
Kojto 90:cb3d968589d8 9334
Kojto 90:cb3d968589d8 9335 /*****************************************************************************/
Kojto 90:cb3d968589d8 9336 /* */
Kojto 90:cb3d968589d8 9337 /* System Configuration (SYSCFG) */
Kojto 90:cb3d968589d8 9338 /* */
Kojto 90:cb3d968589d8 9339 /*****************************************************************************/
Kojto 90:cb3d968589d8 9340 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 122:f9eeca106725 9341 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
Kojto 122:f9eeca106725 9342 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 9343 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 9344 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9345 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9346 #define SYSCFG_CFGR1_IR_MOD_Pos (6U)
Kojto 122:f9eeca106725 9347 #define SYSCFG_CFGR1_IR_MOD_Msk (0x3U << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 9348 #define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IR_MOD config */
Kojto 122:f9eeca106725 9349 #define SYSCFG_CFGR1_IR_MOD_0 (0x1U << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9350 #define SYSCFG_CFGR1_IR_MOD_1 (0x2U << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9351
Kojto 122:f9eeca106725 9352 /* Alias for legacy purposes */
Kojto 122:f9eeca106725 9353 #define SYSCFG_CFGR1_IRDA_ENV_SEL SYSCFG_CFGR1_IR_MOD
Kojto 122:f9eeca106725 9354 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0 SYSCFG_CFGR1_IR_MOD_0
Kojto 122:f9eeca106725 9355 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1 SYSCFG_CFGR1_IR_MOD_1
Kojto 122:f9eeca106725 9356
Kojto 122:f9eeca106725 9357
Kojto 122:f9eeca106725 9358
Kojto 122:f9eeca106725 9359 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
Kojto 122:f9eeca106725 9360 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9361 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
Kojto 122:f9eeca106725 9362 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
Kojto 122:f9eeca106725 9363 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9364 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
Kojto 122:f9eeca106725 9365 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
Kojto 122:f9eeca106725 9366 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9367 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
Kojto 122:f9eeca106725 9368 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
Kojto 122:f9eeca106725 9369 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9370 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
Kojto 122:f9eeca106725 9371 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U)
Kojto 122:f9eeca106725 9372 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9373 #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Kojto 122:f9eeca106725 9374 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos (21U)
Kojto 122:f9eeca106725 9375 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9376 #define SYSCFG_CFGR1_I2C_FMP_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2_Msk /*!< Enable I2C2 Fast mode plus */
Kojto 122:f9eeca106725 9377 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U)
Kojto 122:f9eeca106725 9378 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9379 #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk /*!< Enable Fast Mode Plus on PA9 */
Kojto 122:f9eeca106725 9380 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U)
Kojto 122:f9eeca106725 9381 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9382 #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk /*!< Enable Fast Mode Plus on PA10 */
Kojto 90:cb3d968589d8 9383
Kojto 90:cb3d968589d8 9384 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 122:f9eeca106725 9385 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
Kojto 122:f9eeca106725 9386 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9387 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
Kojto 122:f9eeca106725 9388 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
Kojto 122:f9eeca106725 9389 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 9390 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
Kojto 122:f9eeca106725 9391 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
Kojto 122:f9eeca106725 9392 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9393 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
Kojto 122:f9eeca106725 9394 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
Kojto 122:f9eeca106725 9395 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 9396 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
Kojto 90:cb3d968589d8 9397
Kojto 90:cb3d968589d8 9398 /**
Kojto 90:cb3d968589d8 9399 * @brief EXTI0 configuration
Kojto 90:cb3d968589d8 9400 */
Kojto 122:f9eeca106725 9401 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
Kojto 122:f9eeca106725 9402 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
Kojto 122:f9eeca106725 9403 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
Kojto 122:f9eeca106725 9404 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
Kojto 122:f9eeca106725 9405 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
Kojto 122:f9eeca106725 9406 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
Kojto 90:cb3d968589d8 9407
Kojto 90:cb3d968589d8 9408 /**
Kojto 90:cb3d968589d8 9409 * @brief EXTI1 configuration
Kojto 90:cb3d968589d8 9410 */
Kojto 122:f9eeca106725 9411 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
Kojto 122:f9eeca106725 9412 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
Kojto 122:f9eeca106725 9413 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
Kojto 122:f9eeca106725 9414 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
Kojto 122:f9eeca106725 9415 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
Kojto 122:f9eeca106725 9416 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
Kojto 90:cb3d968589d8 9417
Kojto 90:cb3d968589d8 9418 /**
Kojto 90:cb3d968589d8 9419 * @brief EXTI2 configuration
Kojto 90:cb3d968589d8 9420 */
Kojto 122:f9eeca106725 9421 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
Kojto 122:f9eeca106725 9422 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
Kojto 122:f9eeca106725 9423 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
Kojto 122:f9eeca106725 9424 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
Kojto 122:f9eeca106725 9425 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
Kojto 122:f9eeca106725 9426 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
Kojto 90:cb3d968589d8 9427
Kojto 90:cb3d968589d8 9428 /**
Kojto 90:cb3d968589d8 9429 * @brief EXTI3 configuration
Kojto 90:cb3d968589d8 9430 */
Kojto 122:f9eeca106725 9431 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
Kojto 122:f9eeca106725 9432 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
Kojto 122:f9eeca106725 9433 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
Kojto 122:f9eeca106725 9434 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
Kojto 122:f9eeca106725 9435 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
Kojto 122:f9eeca106725 9436 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
Kojto 90:cb3d968589d8 9437
Kojto 90:cb3d968589d8 9438 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 122:f9eeca106725 9439 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
Kojto 122:f9eeca106725 9440 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9441 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
Kojto 122:f9eeca106725 9442 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
Kojto 122:f9eeca106725 9443 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 9444 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
Kojto 122:f9eeca106725 9445 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
Kojto 122:f9eeca106725 9446 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9447 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
Kojto 122:f9eeca106725 9448 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
Kojto 122:f9eeca106725 9449 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 9450 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
Kojto 90:cb3d968589d8 9451
Kojto 90:cb3d968589d8 9452 /**
Kojto 90:cb3d968589d8 9453 * @brief EXTI4 configuration
Kojto 90:cb3d968589d8 9454 */
Kojto 122:f9eeca106725 9455 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
Kojto 122:f9eeca106725 9456 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
Kojto 122:f9eeca106725 9457 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
Kojto 122:f9eeca106725 9458 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
Kojto 122:f9eeca106725 9459 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
Kojto 122:f9eeca106725 9460 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
Kojto 90:cb3d968589d8 9461
Kojto 90:cb3d968589d8 9462 /**
Kojto 90:cb3d968589d8 9463 * @brief EXTI5 configuration
Kojto 90:cb3d968589d8 9464 */
Kojto 122:f9eeca106725 9465 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
Kojto 122:f9eeca106725 9466 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
Kojto 122:f9eeca106725 9467 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
Kojto 122:f9eeca106725 9468 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
Kojto 122:f9eeca106725 9469 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
Kojto 122:f9eeca106725 9470 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
Kojto 90:cb3d968589d8 9471
Kojto 90:cb3d968589d8 9472 /**
Kojto 90:cb3d968589d8 9473 * @brief EXTI6 configuration
Kojto 90:cb3d968589d8 9474 */
Kojto 122:f9eeca106725 9475 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
Kojto 122:f9eeca106725 9476 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
Kojto 122:f9eeca106725 9477 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
Kojto 122:f9eeca106725 9478 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
Kojto 122:f9eeca106725 9479 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
Kojto 122:f9eeca106725 9480 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
Kojto 90:cb3d968589d8 9481
Kojto 90:cb3d968589d8 9482 /**
Kojto 90:cb3d968589d8 9483 * @brief EXTI7 configuration
Kojto 90:cb3d968589d8 9484 */
Kojto 122:f9eeca106725 9485 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
Kojto 122:f9eeca106725 9486 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
Kojto 122:f9eeca106725 9487 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
Kojto 122:f9eeca106725 9488 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
Kojto 122:f9eeca106725 9489 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
Kojto 122:f9eeca106725 9490 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
Kojto 90:cb3d968589d8 9491
Kojto 90:cb3d968589d8 9492 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 122:f9eeca106725 9493 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
Kojto 122:f9eeca106725 9494 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9495 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
Kojto 122:f9eeca106725 9496 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
Kojto 122:f9eeca106725 9497 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 9498 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
Kojto 122:f9eeca106725 9499 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
Kojto 122:f9eeca106725 9500 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9501 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
Kojto 122:f9eeca106725 9502 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
Kojto 122:f9eeca106725 9503 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 9504 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
Kojto 90:cb3d968589d8 9505
Kojto 90:cb3d968589d8 9506 /**
Kojto 90:cb3d968589d8 9507 * @brief EXTI8 configuration
Kojto 90:cb3d968589d8 9508 */
Kojto 122:f9eeca106725 9509 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
Kojto 122:f9eeca106725 9510 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
Kojto 122:f9eeca106725 9511 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
Kojto 122:f9eeca106725 9512 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
Kojto 122:f9eeca106725 9513 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
Kojto 122:f9eeca106725 9514
Kojto 90:cb3d968589d8 9515
Kojto 90:cb3d968589d8 9516 /**
Kojto 90:cb3d968589d8 9517 * @brief EXTI9 configuration
Kojto 90:cb3d968589d8 9518 */
Kojto 122:f9eeca106725 9519 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
Kojto 122:f9eeca106725 9520 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
Kojto 122:f9eeca106725 9521 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
Kojto 122:f9eeca106725 9522 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
Kojto 122:f9eeca106725 9523 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
Kojto 122:f9eeca106725 9524 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
Kojto 90:cb3d968589d8 9525
Kojto 90:cb3d968589d8 9526 /**
Kojto 90:cb3d968589d8 9527 * @brief EXTI10 configuration
Kojto 90:cb3d968589d8 9528 */
Kojto 122:f9eeca106725 9529 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
Kojto 122:f9eeca106725 9530 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
Kojto 122:f9eeca106725 9531 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
Kojto 122:f9eeca106725 9532 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
Kojto 122:f9eeca106725 9533 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
Kojto 122:f9eeca106725 9534 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
Kojto 90:cb3d968589d8 9535
Kojto 90:cb3d968589d8 9536 /**
Kojto 90:cb3d968589d8 9537 * @brief EXTI11 configuration
Kojto 90:cb3d968589d8 9538 */
Kojto 122:f9eeca106725 9539 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
Kojto 122:f9eeca106725 9540 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
Kojto 122:f9eeca106725 9541 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
Kojto 122:f9eeca106725 9542 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
Kojto 122:f9eeca106725 9543 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
Kojto 90:cb3d968589d8 9544
Kojto 90:cb3d968589d8 9545 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 122:f9eeca106725 9546 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
Kojto 122:f9eeca106725 9547 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9548 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
Kojto 122:f9eeca106725 9549 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
Kojto 122:f9eeca106725 9550 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 9551 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
Kojto 122:f9eeca106725 9552 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
Kojto 122:f9eeca106725 9553 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9554 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
Kojto 122:f9eeca106725 9555 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
Kojto 122:f9eeca106725 9556 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 9557 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
Kojto 90:cb3d968589d8 9558
Kojto 90:cb3d968589d8 9559 /**
Kojto 90:cb3d968589d8 9560 * @brief EXTI12 configuration
Kojto 90:cb3d968589d8 9561 */
Kojto 122:f9eeca106725 9562 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
Kojto 122:f9eeca106725 9563 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
Kojto 122:f9eeca106725 9564 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
Kojto 122:f9eeca106725 9565 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
Kojto 122:f9eeca106725 9566 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
Kojto 90:cb3d968589d8 9567
Kojto 90:cb3d968589d8 9568 /**
Kojto 90:cb3d968589d8 9569 * @brief EXTI13 configuration
Kojto 90:cb3d968589d8 9570 */
Kojto 122:f9eeca106725 9571 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
Kojto 122:f9eeca106725 9572 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
Kojto 122:f9eeca106725 9573 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
Kojto 122:f9eeca106725 9574 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
Kojto 122:f9eeca106725 9575 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
Kojto 90:cb3d968589d8 9576
Kojto 90:cb3d968589d8 9577 /**
Kojto 90:cb3d968589d8 9578 * @brief EXTI14 configuration
Kojto 90:cb3d968589d8 9579 */
Kojto 122:f9eeca106725 9580 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
Kojto 122:f9eeca106725 9581 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
Kojto 122:f9eeca106725 9582 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
Kojto 122:f9eeca106725 9583 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
Kojto 122:f9eeca106725 9584 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
Kojto 90:cb3d968589d8 9585
Kojto 90:cb3d968589d8 9586 /**
Kojto 90:cb3d968589d8 9587 * @brief EXTI15 configuration
Kojto 90:cb3d968589d8 9588 */
Kojto 122:f9eeca106725 9589 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
Kojto 122:f9eeca106725 9590 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
Kojto 122:f9eeca106725 9591 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
Kojto 122:f9eeca106725 9592 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
Kojto 122:f9eeca106725 9593 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
Kojto 90:cb3d968589d8 9594
Kojto 90:cb3d968589d8 9595 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 122:f9eeca106725 9596 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
Kojto 122:f9eeca106725 9597 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9598 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 122:f9eeca106725 9599 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
Kojto 122:f9eeca106725 9600 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9601 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 122:f9eeca106725 9602 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
Kojto 122:f9eeca106725 9603 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9604 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
Kojto 122:f9eeca106725 9605 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
Kojto 122:f9eeca106725 9606 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9607 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
Kojto 122:f9eeca106725 9608 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 90:cb3d968589d8 9609
Kojto 90:cb3d968589d8 9610 /***************** Bit definition for SYSCFG_xxx ISR Wrapper register ****************/
Kojto 122:f9eeca106725 9611 #define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
Kojto 122:f9eeca106725 9612 #define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1U << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9613 #define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
Kojto 122:f9eeca106725 9614 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos (0U)
Kojto 122:f9eeca106725 9615 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk (0x1U << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9616 #define SYSCFG_ITLINE1_SR_PVDOUT SYSCFG_ITLINE1_SR_PVDOUT_Msk /*!< Power voltage detection -> exti[31] Interrupt */
Kojto 122:f9eeca106725 9617 #define SYSCFG_ITLINE1_SR_VDDIO2_Pos (1U)
Kojto 122:f9eeca106725 9618 #define SYSCFG_ITLINE1_SR_VDDIO2_Msk (0x1U << SYSCFG_ITLINE1_SR_VDDIO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9619 #define SYSCFG_ITLINE1_SR_VDDIO2 SYSCFG_ITLINE1_SR_VDDIO2_Msk /*!< VDDIO2 -> exti[16] Interrupt */
Kojto 122:f9eeca106725 9620 #define SYSCFG_ITLINE2_SR_RTC_ALRA_Pos (0U)
Kojto 122:f9eeca106725 9621 #define SYSCFG_ITLINE2_SR_RTC_ALRA_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_ALRA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9622 #define SYSCFG_ITLINE2_SR_RTC_ALRA SYSCFG_ITLINE2_SR_RTC_ALRA_Msk /*!< RTC Alarm -> exti[17] interrupt .... */
Kojto 122:f9eeca106725 9623 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos (1U)
Kojto 122:f9eeca106725 9624 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9625 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk /*!< RTC Time Stamp -> exti[19] interrupt */
Kojto 122:f9eeca106725 9626 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (2U)
Kojto 122:f9eeca106725 9627 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9628 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC WAKEUP -> exti[20] Interrupt */
Kojto 122:f9eeca106725 9629 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (0U)
Kojto 122:f9eeca106725 9630 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1U << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9631 #define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< Flash ITF Interrupt */
Kojto 122:f9eeca106725 9632 #define SYSCFG_ITLINE4_SR_CRS_Pos (0U)
Kojto 122:f9eeca106725 9633 #define SYSCFG_ITLINE4_SR_CRS_Msk (0x1U << SYSCFG_ITLINE4_SR_CRS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9634 #define SYSCFG_ITLINE4_SR_CRS SYSCFG_ITLINE4_SR_CRS_Msk /*!< CRS interrupt */
Kojto 122:f9eeca106725 9635 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (1U)
Kojto 122:f9eeca106725 9636 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1U << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9637 #define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< CLK CTRL interrupt */
Kojto 122:f9eeca106725 9638 #define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
Kojto 122:f9eeca106725 9639 #define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9640 #define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
Kojto 122:f9eeca106725 9641 #define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
Kojto 122:f9eeca106725 9642 #define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9643 #define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
Kojto 122:f9eeca106725 9644 #define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
Kojto 122:f9eeca106725 9645 #define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9646 #define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
Kojto 122:f9eeca106725 9647 #define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
Kojto 122:f9eeca106725 9648 #define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9649 #define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
Kojto 122:f9eeca106725 9650 #define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
Kojto 122:f9eeca106725 9651 #define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9652 #define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9653 #define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
Kojto 122:f9eeca106725 9654 #define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9655 #define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9656 #define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
Kojto 122:f9eeca106725 9657 #define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9658 #define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9659 #define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
Kojto 122:f9eeca106725 9660 #define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9661 #define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9662 #define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
Kojto 122:f9eeca106725 9663 #define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9664 #define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9665 #define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
Kojto 122:f9eeca106725 9666 #define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9667 #define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9668 #define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
Kojto 122:f9eeca106725 9669 #define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9670 #define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9671 #define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
Kojto 122:f9eeca106725 9672 #define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9673 #define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9674 #define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
Kojto 122:f9eeca106725 9675 #define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9676 #define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9677 #define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
Kojto 122:f9eeca106725 9678 #define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9679 #define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9680 #define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
Kojto 122:f9eeca106725 9681 #define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9682 #define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9683 #define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
Kojto 122:f9eeca106725 9684 #define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9685 #define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 to 4 */
Kojto 122:f9eeca106725 9686 #define SYSCFG_ITLINE8_SR_TSC_EOA_Pos (0U)
Kojto 122:f9eeca106725 9687 #define SYSCFG_ITLINE8_SR_TSC_EOA_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_EOA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9688 #define SYSCFG_ITLINE8_SR_TSC_EOA SYSCFG_ITLINE8_SR_TSC_EOA_Msk /*!< Touch control EOA Interrupt */
Kojto 122:f9eeca106725 9689 #define SYSCFG_ITLINE8_SR_TSC_MCE_Pos (1U)
Kojto 122:f9eeca106725 9690 #define SYSCFG_ITLINE8_SR_TSC_MCE_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_MCE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9691 #define SYSCFG_ITLINE8_SR_TSC_MCE SYSCFG_ITLINE8_SR_TSC_MCE_Msk /*!< Touch control MCE Interrupt */
Kojto 122:f9eeca106725 9692 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
Kojto 122:f9eeca106725 9693 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1U << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9694 #define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
Kojto 122:f9eeca106725 9695 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
Kojto 122:f9eeca106725 9696 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9697 #define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
Kojto 122:f9eeca106725 9698 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
Kojto 122:f9eeca106725 9699 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9700 #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
Kojto 122:f9eeca106725 9701 #define SYSCFG_ITLINE10_SR_DMA2_CH1_Pos (2U)
Kojto 122:f9eeca106725 9702 #define SYSCFG_ITLINE10_SR_DMA2_CH1_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9703 #define SYSCFG_ITLINE10_SR_DMA2_CH1 SYSCFG_ITLINE10_SR_DMA2_CH1_Msk /*!< DMA2 Channel 1 Interrupt */
Kojto 122:f9eeca106725 9704 #define SYSCFG_ITLINE10_SR_DMA2_CH2_Pos (3U)
Kojto 122:f9eeca106725 9705 #define SYSCFG_ITLINE10_SR_DMA2_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH2_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9706 #define SYSCFG_ITLINE10_SR_DMA2_CH2 SYSCFG_ITLINE10_SR_DMA2_CH2_Msk /*!< DMA2 Channel 2 Interrupt */
Kojto 122:f9eeca106725 9707 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (0U)
Kojto 122:f9eeca106725 9708 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9709 #define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
Kojto 122:f9eeca106725 9710 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (1U)
Kojto 122:f9eeca106725 9711 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9712 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
Kojto 122:f9eeca106725 9713 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (2U)
Kojto 122:f9eeca106725 9714 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9715 #define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */
Kojto 122:f9eeca106725 9716 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (3U)
Kojto 122:f9eeca106725 9717 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9718 #define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */
Kojto 122:f9eeca106725 9719 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Pos (4U)
Kojto 122:f9eeca106725 9720 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH3_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9721 #define SYSCFG_ITLINE11_SR_DMA2_CH3 SYSCFG_ITLINE11_SR_DMA2_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
Kojto 122:f9eeca106725 9722 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Pos (5U)
Kojto 122:f9eeca106725 9723 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH4_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9724 #define SYSCFG_ITLINE11_SR_DMA2_CH4 SYSCFG_ITLINE11_SR_DMA2_CH4_Msk /*!< DMA2 Channel 4 Interrupt */
Kojto 122:f9eeca106725 9725 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Pos (6U)
Kojto 122:f9eeca106725 9726 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH5_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9727 #define SYSCFG_ITLINE11_SR_DMA2_CH5 SYSCFG_ITLINE11_SR_DMA2_CH5_Msk /*!< DMA2 Channel 5 Interrupt */
Kojto 122:f9eeca106725 9728 #define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
Kojto 122:f9eeca106725 9729 #define SYSCFG_ITLINE12_SR_ADC_Msk (0x1U << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9730 #define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
Kojto 122:f9eeca106725 9731 #define SYSCFG_ITLINE12_SR_COMP1_Pos (1U)
Kojto 122:f9eeca106725 9732 #define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9733 #define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[21] */
Kojto 122:f9eeca106725 9734 #define SYSCFG_ITLINE12_SR_COMP2_Pos (2U)
Kojto 122:f9eeca106725 9735 #define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9736 #define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[22] */
Kojto 122:f9eeca106725 9737 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (0U)
Kojto 122:f9eeca106725 9738 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9739 #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
Kojto 122:f9eeca106725 9740 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (1U)
Kojto 122:f9eeca106725 9741 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9742 #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
Kojto 122:f9eeca106725 9743 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (2U)
Kojto 122:f9eeca106725 9744 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9745 #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
Kojto 122:f9eeca106725 9746 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (3U)
Kojto 122:f9eeca106725 9747 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9748 #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
Kojto 122:f9eeca106725 9749 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
Kojto 122:f9eeca106725 9750 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1U << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9751 #define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
Kojto 122:f9eeca106725 9752 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U)
Kojto 122:f9eeca106725 9753 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1U << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9754 #define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */
Kojto 122:f9eeca106725 9755 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
Kojto 122:f9eeca106725 9756 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1U << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9757 #define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
Kojto 122:f9eeca106725 9758 #define SYSCFG_ITLINE17_SR_DAC_Pos (0U)
Kojto 122:f9eeca106725 9759 #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1U << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9760 #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */
Kojto 122:f9eeca106725 9761 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (1U)
Kojto 122:f9eeca106725 9762 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1U << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9763 #define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */
Kojto 122:f9eeca106725 9764 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U)
Kojto 122:f9eeca106725 9765 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1U << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9766 #define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */
Kojto 122:f9eeca106725 9767 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
Kojto 122:f9eeca106725 9768 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1U << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9769 #define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
Kojto 122:f9eeca106725 9770 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U)
Kojto 122:f9eeca106725 9771 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1U << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9772 #define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */
Kojto 122:f9eeca106725 9773 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
Kojto 122:f9eeca106725 9774 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1U << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9775 #define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
Kojto 122:f9eeca106725 9776 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
Kojto 122:f9eeca106725 9777 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1U << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9778 #define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
Kojto 122:f9eeca106725 9779 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
Kojto 122:f9eeca106725 9780 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1U << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9781 #define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
Kojto 122:f9eeca106725 9782 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
Kojto 122:f9eeca106725 9783 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1U << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9784 #define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */
Kojto 122:f9eeca106725 9785 #define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
Kojto 122:f9eeca106725 9786 #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1U << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9787 #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
Kojto 122:f9eeca106725 9788 #define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
Kojto 122:f9eeca106725 9789 #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1U << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9790 #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
Kojto 122:f9eeca106725 9791 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
Kojto 122:f9eeca106725 9792 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1U << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9793 #define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
Kojto 122:f9eeca106725 9794 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
Kojto 122:f9eeca106725 9795 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1U << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9796 #define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
Kojto 122:f9eeca106725 9797 #define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U)
Kojto 122:f9eeca106725 9798 #define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9799 #define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt -> exti[28] */
Kojto 122:f9eeca106725 9800 #define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U)
Kojto 122:f9eeca106725 9801 #define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9802 #define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */
Kojto 122:f9eeca106725 9803 #define SYSCFG_ITLINE29_SR_USART5_GLB_Pos (2U)
Kojto 122:f9eeca106725 9804 #define SYSCFG_ITLINE29_SR_USART5_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART5_GLB_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9805 #define SYSCFG_ITLINE29_SR_USART5_GLB SYSCFG_ITLINE29_SR_USART5_GLB_Msk /*!< USART5 GLB Interrupt */
Kojto 122:f9eeca106725 9806 #define SYSCFG_ITLINE29_SR_USART6_GLB_Pos (3U)
Kojto 122:f9eeca106725 9807 #define SYSCFG_ITLINE29_SR_USART6_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART6_GLB_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9808 #define SYSCFG_ITLINE29_SR_USART6_GLB SYSCFG_ITLINE29_SR_USART6_GLB_Msk /*!< USART6 GLB Interrupt */
Kojto 122:f9eeca106725 9809 #define SYSCFG_ITLINE29_SR_USART7_GLB_Pos (4U)
Kojto 122:f9eeca106725 9810 #define SYSCFG_ITLINE29_SR_USART7_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART7_GLB_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9811 #define SYSCFG_ITLINE29_SR_USART7_GLB SYSCFG_ITLINE29_SR_USART7_GLB_Msk /*!< USART7 GLB Interrupt */
Kojto 122:f9eeca106725 9812 #define SYSCFG_ITLINE29_SR_USART8_GLB_Pos (5U)
Kojto 122:f9eeca106725 9813 #define SYSCFG_ITLINE29_SR_USART8_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART8_GLB_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9814 #define SYSCFG_ITLINE29_SR_USART8_GLB SYSCFG_ITLINE29_SR_USART8_GLB_Msk /*!< USART8 GLB Interrupt */
Kojto 122:f9eeca106725 9815 #define SYSCFG_ITLINE30_SR_CAN_Pos (0U)
Kojto 122:f9eeca106725 9816 #define SYSCFG_ITLINE30_SR_CAN_Msk (0x1U << SYSCFG_ITLINE30_SR_CAN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9817 #define SYSCFG_ITLINE30_SR_CAN SYSCFG_ITLINE30_SR_CAN_Msk /*!< CAN Interrupt */
Kojto 122:f9eeca106725 9818 #define SYSCFG_ITLINE30_SR_CEC_Pos (1U)
Kojto 122:f9eeca106725 9819 #define SYSCFG_ITLINE30_SR_CEC_Msk (0x1U << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9820 #define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt */
Kojto 122:f9eeca106725 9821
Kojto 90:cb3d968589d8 9822 /*****************************************************************************/
Kojto 90:cb3d968589d8 9823 /* */
Kojto 90:cb3d968589d8 9824 /* Timers (TIM) */
Kojto 90:cb3d968589d8 9825 /* */
Kojto 90:cb3d968589d8 9826 /*****************************************************************************/
Kojto 90:cb3d968589d8 9827 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 122:f9eeca106725 9828 #define TIM_CR1_CEN_Pos (0U)
Kojto 122:f9eeca106725 9829 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9830 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
Kojto 122:f9eeca106725 9831 #define TIM_CR1_UDIS_Pos (1U)
Kojto 122:f9eeca106725 9832 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9833 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
Kojto 122:f9eeca106725 9834 #define TIM_CR1_URS_Pos (2U)
Kojto 122:f9eeca106725 9835 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9836 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
Kojto 122:f9eeca106725 9837 #define TIM_CR1_OPM_Pos (3U)
Kojto 122:f9eeca106725 9838 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9839 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
Kojto 122:f9eeca106725 9840 #define TIM_CR1_DIR_Pos (4U)
Kojto 122:f9eeca106725 9841 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9842 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
Kojto 122:f9eeca106725 9843
Kojto 122:f9eeca106725 9844 #define TIM_CR1_CMS_Pos (5U)
Kojto 122:f9eeca106725 9845 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 9846 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 9847 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9848 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9849
Kojto 122:f9eeca106725 9850 #define TIM_CR1_ARPE_Pos (7U)
Kojto 122:f9eeca106725 9851 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9852 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 9853
Kojto 122:f9eeca106725 9854 #define TIM_CR1_CKD_Pos (8U)
Kojto 122:f9eeca106725 9855 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 9856 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 9857 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9858 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
Kojto 90:cb3d968589d8 9859
Kojto 90:cb3d968589d8 9860 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 122:f9eeca106725 9861 #define TIM_CR2_CCPC_Pos (0U)
Kojto 122:f9eeca106725 9862 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9863 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 9864 #define TIM_CR2_CCUS_Pos (2U)
Kojto 122:f9eeca106725 9865 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9866 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 9867 #define TIM_CR2_CCDS_Pos (3U)
Kojto 122:f9eeca106725 9868 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9869 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 9870
Kojto 122:f9eeca106725 9871 #define TIM_CR2_MMS_Pos (4U)
Kojto 122:f9eeca106725 9872 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 9873 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 9874 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9875 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9876 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9877
Kojto 122:f9eeca106725 9878 #define TIM_CR2_TI1S_Pos (7U)
Kojto 122:f9eeca106725 9879 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9880 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
Kojto 122:f9eeca106725 9881 #define TIM_CR2_OIS1_Pos (8U)
Kojto 122:f9eeca106725 9882 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9883 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 9884 #define TIM_CR2_OIS1N_Pos (9U)
Kojto 122:f9eeca106725 9885 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9886 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 9887 #define TIM_CR2_OIS2_Pos (10U)
Kojto 122:f9eeca106725 9888 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9889 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 9890 #define TIM_CR2_OIS2N_Pos (11U)
Kojto 122:f9eeca106725 9891 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9892 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 9893 #define TIM_CR2_OIS3_Pos (12U)
Kojto 122:f9eeca106725 9894 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9895 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 9896 #define TIM_CR2_OIS3N_Pos (13U)
Kojto 122:f9eeca106725 9897 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9898 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 9899 #define TIM_CR2_OIS4_Pos (14U)
Kojto 122:f9eeca106725 9900 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9901 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 90:cb3d968589d8 9902
Kojto 90:cb3d968589d8 9903 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 122:f9eeca106725 9904 #define TIM_SMCR_SMS_Pos (0U)
Kojto 122:f9eeca106725 9905 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 9906 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 9907 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9908 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9909 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9910
Kojto 122:f9eeca106725 9911 #define TIM_SMCR_OCCS_Pos (3U)
Kojto 122:f9eeca106725 9912 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9913 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
Kojto 122:f9eeca106725 9914
Kojto 122:f9eeca106725 9915 #define TIM_SMCR_TS_Pos (4U)
Kojto 122:f9eeca106725 9916 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 9917 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 9918 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9919 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9920 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9921
Kojto 122:f9eeca106725 9922 #define TIM_SMCR_MSM_Pos (7U)
Kojto 122:f9eeca106725 9923 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9924 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
Kojto 122:f9eeca106725 9925
Kojto 122:f9eeca106725 9926 #define TIM_SMCR_ETF_Pos (8U)
Kojto 122:f9eeca106725 9927 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9928 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 9929 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9930 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9931 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9932 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9933
Kojto 122:f9eeca106725 9934 #define TIM_SMCR_ETPS_Pos (12U)
Kojto 122:f9eeca106725 9935 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 9936 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 9937 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9938 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9939
Kojto 122:f9eeca106725 9940 #define TIM_SMCR_ECE_Pos (14U)
Kojto 122:f9eeca106725 9941 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9942 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
Kojto 122:f9eeca106725 9943 #define TIM_SMCR_ETP_Pos (15U)
Kojto 122:f9eeca106725 9944 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9945 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
Kojto 90:cb3d968589d8 9946
Kojto 90:cb3d968589d8 9947 /******************* Bit definition for TIM_DIER register ******************/
Kojto 122:f9eeca106725 9948 #define TIM_DIER_UIE_Pos (0U)
Kojto 122:f9eeca106725 9949 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9950 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
Kojto 122:f9eeca106725 9951 #define TIM_DIER_CC1IE_Pos (1U)
Kojto 122:f9eeca106725 9952 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9953 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 9954 #define TIM_DIER_CC2IE_Pos (2U)
Kojto 122:f9eeca106725 9955 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9956 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 9957 #define TIM_DIER_CC3IE_Pos (3U)
Kojto 122:f9eeca106725 9958 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9959 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 9960 #define TIM_DIER_CC4IE_Pos (4U)
Kojto 122:f9eeca106725 9961 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9962 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 9963 #define TIM_DIER_COMIE_Pos (5U)
Kojto 122:f9eeca106725 9964 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9965 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
Kojto 122:f9eeca106725 9966 #define TIM_DIER_TIE_Pos (6U)
Kojto 122:f9eeca106725 9967 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9968 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 9969 #define TIM_DIER_BIE_Pos (7U)
Kojto 122:f9eeca106725 9970 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9971 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
Kojto 122:f9eeca106725 9972 #define TIM_DIER_UDE_Pos (8U)
Kojto 122:f9eeca106725 9973 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9974 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
Kojto 122:f9eeca106725 9975 #define TIM_DIER_CC1DE_Pos (9U)
Kojto 122:f9eeca106725 9976 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9977 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 9978 #define TIM_DIER_CC2DE_Pos (10U)
Kojto 122:f9eeca106725 9979 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9980 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 9981 #define TIM_DIER_CC3DE_Pos (11U)
Kojto 122:f9eeca106725 9982 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9983 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 9984 #define TIM_DIER_CC4DE_Pos (12U)
Kojto 122:f9eeca106725 9985 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9986 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 9987 #define TIM_DIER_COMDE_Pos (13U)
Kojto 122:f9eeca106725 9988 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9989 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
Kojto 122:f9eeca106725 9990 #define TIM_DIER_TDE_Pos (14U)
Kojto 122:f9eeca106725 9991 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9992 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
Kojto 90:cb3d968589d8 9993
Kojto 90:cb3d968589d8 9994 /******************** Bit definition for TIM_SR register *******************/
Kojto 122:f9eeca106725 9995 #define TIM_SR_UIF_Pos (0U)
Kojto 122:f9eeca106725 9996 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9997 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 9998 #define TIM_SR_CC1IF_Pos (1U)
Kojto 122:f9eeca106725 9999 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10000 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 10001 #define TIM_SR_CC2IF_Pos (2U)
Kojto 122:f9eeca106725 10002 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10003 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 10004 #define TIM_SR_CC3IF_Pos (3U)
Kojto 122:f9eeca106725 10005 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10006 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 10007 #define TIM_SR_CC4IF_Pos (4U)
Kojto 122:f9eeca106725 10008 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10009 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 10010 #define TIM_SR_COMIF_Pos (5U)
Kojto 122:f9eeca106725 10011 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10012 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 10013 #define TIM_SR_TIF_Pos (6U)
Kojto 122:f9eeca106725 10014 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10015 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 10016 #define TIM_SR_BIF_Pos (7U)
Kojto 122:f9eeca106725 10017 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10018 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 10019 #define TIM_SR_CC1OF_Pos (9U)
Kojto 122:f9eeca106725 10020 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10021 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 10022 #define TIM_SR_CC2OF_Pos (10U)
Kojto 122:f9eeca106725 10023 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10024 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 10025 #define TIM_SR_CC3OF_Pos (11U)
Kojto 122:f9eeca106725 10026 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10027 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 10028 #define TIM_SR_CC4OF_Pos (12U)
Kojto 122:f9eeca106725 10029 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10030 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
Kojto 90:cb3d968589d8 10031
Kojto 90:cb3d968589d8 10032 /******************* Bit definition for TIM_EGR register *******************/
Kojto 122:f9eeca106725 10033 #define TIM_EGR_UG_Pos (0U)
Kojto 122:f9eeca106725 10034 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10035 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
Kojto 122:f9eeca106725 10036 #define TIM_EGR_CC1G_Pos (1U)
Kojto 122:f9eeca106725 10037 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10038 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 10039 #define TIM_EGR_CC2G_Pos (2U)
Kojto 122:f9eeca106725 10040 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10041 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 10042 #define TIM_EGR_CC3G_Pos (3U)
Kojto 122:f9eeca106725 10043 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10044 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 10045 #define TIM_EGR_CC4G_Pos (4U)
Kojto 122:f9eeca106725 10046 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10047 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 10048 #define TIM_EGR_COMG_Pos (5U)
Kojto 122:f9eeca106725 10049 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10050 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 10051 #define TIM_EGR_TG_Pos (6U)
Kojto 122:f9eeca106725 10052 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10053 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
Kojto 122:f9eeca106725 10054 #define TIM_EGR_BG_Pos (7U)
Kojto 122:f9eeca106725 10055 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10056 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
Kojto 90:cb3d968589d8 10057
Kojto 90:cb3d968589d8 10058 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 122:f9eeca106725 10059 #define TIM_CCMR1_CC1S_Pos (0U)
Kojto 122:f9eeca106725 10060 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10061 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 10062 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10063 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10064
Kojto 122:f9eeca106725 10065 #define TIM_CCMR1_OC1FE_Pos (2U)
Kojto 122:f9eeca106725 10066 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10067 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 10068 #define TIM_CCMR1_OC1PE_Pos (3U)
Kojto 122:f9eeca106725 10069 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10070 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 10071
Kojto 122:f9eeca106725 10072 #define TIM_CCMR1_OC1M_Pos (4U)
Kojto 122:f9eeca106725 10073 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 10074 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 10075 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10076 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10077 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10078
Kojto 122:f9eeca106725 10079 #define TIM_CCMR1_OC1CE_Pos (7U)
Kojto 122:f9eeca106725 10080 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10081 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 10082
Kojto 122:f9eeca106725 10083 #define TIM_CCMR1_CC2S_Pos (8U)
Kojto 122:f9eeca106725 10084 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 10085 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 10086 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10087 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10088
Kojto 122:f9eeca106725 10089 #define TIM_CCMR1_OC2FE_Pos (10U)
Kojto 122:f9eeca106725 10090 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10091 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 10092 #define TIM_CCMR1_OC2PE_Pos (11U)
Kojto 122:f9eeca106725 10093 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10094 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 10095
Kojto 122:f9eeca106725 10096 #define TIM_CCMR1_OC2M_Pos (12U)
Kojto 122:f9eeca106725 10097 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10098 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 10099 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10100 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10101 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10102
Kojto 122:f9eeca106725 10103 #define TIM_CCMR1_OC2CE_Pos (15U)
Kojto 122:f9eeca106725 10104 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10105 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
Kojto 90:cb3d968589d8 10106
Kojto 90:cb3d968589d8 10107 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 10108
Kojto 122:f9eeca106725 10109 #define TIM_CCMR1_IC1PSC_Pos (2U)
Kojto 122:f9eeca106725 10110 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 10111 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 10112 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10113 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10114
Kojto 122:f9eeca106725 10115 #define TIM_CCMR1_IC1F_Pos (4U)
Kojto 122:f9eeca106725 10116 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 10117 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 10118 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10119 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10120 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10121 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10122
Kojto 122:f9eeca106725 10123 #define TIM_CCMR1_IC2PSC_Pos (10U)
Kojto 122:f9eeca106725 10124 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 10125 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 10126 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10127 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10128
Kojto 122:f9eeca106725 10129 #define TIM_CCMR1_IC2F_Pos (12U)
Kojto 122:f9eeca106725 10130 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 10131 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 10132 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10133 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10134 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10135 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
Kojto 90:cb3d968589d8 10136
Kojto 90:cb3d968589d8 10137 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 122:f9eeca106725 10138 #define TIM_CCMR2_CC3S_Pos (0U)
Kojto 122:f9eeca106725 10139 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10140 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 10141 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10142 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10143
Kojto 122:f9eeca106725 10144 #define TIM_CCMR2_OC3FE_Pos (2U)
Kojto 122:f9eeca106725 10145 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10146 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 10147 #define TIM_CCMR2_OC3PE_Pos (3U)
Kojto 122:f9eeca106725 10148 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10149 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 10150
Kojto 122:f9eeca106725 10151 #define TIM_CCMR2_OC3M_Pos (4U)
Kojto 122:f9eeca106725 10152 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 10153 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 10154 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10155 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10156 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10157
Kojto 122:f9eeca106725 10158 #define TIM_CCMR2_OC3CE_Pos (7U)
Kojto 122:f9eeca106725 10159 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10160 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 10161
Kojto 122:f9eeca106725 10162 #define TIM_CCMR2_CC4S_Pos (8U)
Kojto 122:f9eeca106725 10163 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 10164 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 10165 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10166 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10167
Kojto 122:f9eeca106725 10168 #define TIM_CCMR2_OC4FE_Pos (10U)
Kojto 122:f9eeca106725 10169 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10170 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 10171 #define TIM_CCMR2_OC4PE_Pos (11U)
Kojto 122:f9eeca106725 10172 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10173 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 10174
Kojto 122:f9eeca106725 10175 #define TIM_CCMR2_OC4M_Pos (12U)
Kojto 122:f9eeca106725 10176 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10177 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 10178 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10179 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10180 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10181
Kojto 122:f9eeca106725 10182 #define TIM_CCMR2_OC4CE_Pos (15U)
Kojto 122:f9eeca106725 10183 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10184 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
Kojto 90:cb3d968589d8 10185
Kojto 90:cb3d968589d8 10186 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 10187
Kojto 122:f9eeca106725 10188 #define TIM_CCMR2_IC3PSC_Pos (2U)
Kojto 122:f9eeca106725 10189 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 10190 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 10191 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10192 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10193
Kojto 122:f9eeca106725 10194 #define TIM_CCMR2_IC3F_Pos (4U)
Kojto 122:f9eeca106725 10195 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 10196 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 10197 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10198 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10199 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10200 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10201
Kojto 122:f9eeca106725 10202 #define TIM_CCMR2_IC4PSC_Pos (10U)
Kojto 122:f9eeca106725 10203 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 10204 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 10205 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10206 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10207
Kojto 122:f9eeca106725 10208 #define TIM_CCMR2_IC4F_Pos (12U)
Kojto 122:f9eeca106725 10209 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 10210 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 10211 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10212 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10213 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10214 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
Kojto 90:cb3d968589d8 10215
Kojto 90:cb3d968589d8 10216 /******************* Bit definition for TIM_CCER register ******************/
Kojto 122:f9eeca106725 10217 #define TIM_CCER_CC1E_Pos (0U)
Kojto 122:f9eeca106725 10218 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10219 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 10220 #define TIM_CCER_CC1P_Pos (1U)
Kojto 122:f9eeca106725 10221 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10222 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 10223 #define TIM_CCER_CC1NE_Pos (2U)
Kojto 122:f9eeca106725 10224 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10225 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 10226 #define TIM_CCER_CC1NP_Pos (3U)
Kojto 122:f9eeca106725 10227 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10228 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 10229 #define TIM_CCER_CC2E_Pos (4U)
Kojto 122:f9eeca106725 10230 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10231 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 10232 #define TIM_CCER_CC2P_Pos (5U)
Kojto 122:f9eeca106725 10233 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10234 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 10235 #define TIM_CCER_CC2NE_Pos (6U)
Kojto 122:f9eeca106725 10236 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10237 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 10238 #define TIM_CCER_CC2NP_Pos (7U)
Kojto 122:f9eeca106725 10239 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10240 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 10241 #define TIM_CCER_CC3E_Pos (8U)
Kojto 122:f9eeca106725 10242 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10243 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 10244 #define TIM_CCER_CC3P_Pos (9U)
Kojto 122:f9eeca106725 10245 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10246 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 10247 #define TIM_CCER_CC3NE_Pos (10U)
Kojto 122:f9eeca106725 10248 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10249 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 10250 #define TIM_CCER_CC3NP_Pos (11U)
Kojto 122:f9eeca106725 10251 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10252 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 10253 #define TIM_CCER_CC4E_Pos (12U)
Kojto 122:f9eeca106725 10254 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10255 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 10256 #define TIM_CCER_CC4P_Pos (13U)
Kojto 122:f9eeca106725 10257 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10258 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 10259 #define TIM_CCER_CC4NP_Pos (15U)
Kojto 122:f9eeca106725 10260 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10261 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 90:cb3d968589d8 10262
Kojto 90:cb3d968589d8 10263 /******************* Bit definition for TIM_CNT register *******************/
Kojto 122:f9eeca106725 10264 #define TIM_CNT_CNT_Pos (0U)
Kojto 122:f9eeca106725 10265 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10266 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
Kojto 90:cb3d968589d8 10267
Kojto 90:cb3d968589d8 10268 /******************* Bit definition for TIM_PSC register *******************/
Kojto 122:f9eeca106725 10269 #define TIM_PSC_PSC_Pos (0U)
Kojto 122:f9eeca106725 10270 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10271 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
Kojto 90:cb3d968589d8 10272
Kojto 90:cb3d968589d8 10273 /******************* Bit definition for TIM_ARR register *******************/
Kojto 122:f9eeca106725 10274 #define TIM_ARR_ARR_Pos (0U)
Kojto 122:f9eeca106725 10275 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10276 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
Kojto 90:cb3d968589d8 10277
Kojto 90:cb3d968589d8 10278 /******************* Bit definition for TIM_RCR register *******************/
Kojto 122:f9eeca106725 10279 #define TIM_RCR_REP_Pos (0U)
Kojto 122:f9eeca106725 10280 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 10281 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
Kojto 90:cb3d968589d8 10282
Kojto 90:cb3d968589d8 10283 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 122:f9eeca106725 10284 #define TIM_CCR1_CCR1_Pos (0U)
Kojto 122:f9eeca106725 10285 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10286 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
Kojto 90:cb3d968589d8 10287
Kojto 90:cb3d968589d8 10288 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 122:f9eeca106725 10289 #define TIM_CCR2_CCR2_Pos (0U)
Kojto 122:f9eeca106725 10290 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10291 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
Kojto 90:cb3d968589d8 10292
Kojto 90:cb3d968589d8 10293 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 122:f9eeca106725 10294 #define TIM_CCR3_CCR3_Pos (0U)
Kojto 122:f9eeca106725 10295 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10296 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
Kojto 90:cb3d968589d8 10297
Kojto 90:cb3d968589d8 10298 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 122:f9eeca106725 10299 #define TIM_CCR4_CCR4_Pos (0U)
Kojto 122:f9eeca106725 10300 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10301 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
Kojto 90:cb3d968589d8 10302
Kojto 90:cb3d968589d8 10303 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 122:f9eeca106725 10304 #define TIM_BDTR_DTG_Pos (0U)
Kojto 122:f9eeca106725 10305 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 10306 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 10307 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10308 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10309 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10310 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10311 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10312 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10313 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10314 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10315
Kojto 122:f9eeca106725 10316 #define TIM_BDTR_LOCK_Pos (8U)
Kojto 122:f9eeca106725 10317 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 10318 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 10319 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10320 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10321
Kojto 122:f9eeca106725 10322 #define TIM_BDTR_OSSI_Pos (10U)
Kojto 122:f9eeca106725 10323 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10324 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 10325 #define TIM_BDTR_OSSR_Pos (11U)
Kojto 122:f9eeca106725 10326 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10327 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 10328 #define TIM_BDTR_BKE_Pos (12U)
Kojto 122:f9eeca106725 10329 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10330 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
Kojto 122:f9eeca106725 10331 #define TIM_BDTR_BKP_Pos (13U)
Kojto 122:f9eeca106725 10332 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10333 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
Kojto 122:f9eeca106725 10334 #define TIM_BDTR_AOE_Pos (14U)
Kojto 122:f9eeca106725 10335 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10336 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
Kojto 122:f9eeca106725 10337 #define TIM_BDTR_MOE_Pos (15U)
Kojto 122:f9eeca106725 10338 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10339 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
Kojto 90:cb3d968589d8 10340
Kojto 90:cb3d968589d8 10341 /******************* Bit definition for TIM_DCR register *******************/
Kojto 122:f9eeca106725 10342 #define TIM_DCR_DBA_Pos (0U)
Kojto 122:f9eeca106725 10343 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 10344 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 10345 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10346 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10347 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10348 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10349 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10350
Kojto 122:f9eeca106725 10351 #define TIM_DCR_DBL_Pos (8U)
Kojto 122:f9eeca106725 10352 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 10353 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 10354 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10355 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10356 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10357 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10358 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
Kojto 90:cb3d968589d8 10359
Kojto 90:cb3d968589d8 10360 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 122:f9eeca106725 10361 #define TIM_DMAR_DMAB_Pos (0U)
Kojto 122:f9eeca106725 10362 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10363 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
Kojto 90:cb3d968589d8 10364
Kojto 90:cb3d968589d8 10365 /******************* Bit definition for TIM14_OR register ********************/
Kojto 122:f9eeca106725 10366 #define TIM14_OR_TI1_RMP_Pos (0U)
Kojto 122:f9eeca106725 10367 #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10368 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 122:f9eeca106725 10369 #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10370 #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
Kojto 90:cb3d968589d8 10371
Kojto 90:cb3d968589d8 10372 /******************************************************************************/
Kojto 90:cb3d968589d8 10373 /* */
Kojto 90:cb3d968589d8 10374 /* Touch Sensing Controller (TSC) */
Kojto 90:cb3d968589d8 10375 /* */
Kojto 90:cb3d968589d8 10376 /******************************************************************************/
Kojto 90:cb3d968589d8 10377 /******************* Bit definition for TSC_CR register *********************/
Kojto 122:f9eeca106725 10378 #define TSC_CR_TSCE_Pos (0U)
Kojto 122:f9eeca106725 10379 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10380 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
Kojto 122:f9eeca106725 10381 #define TSC_CR_START_Pos (1U)
Kojto 122:f9eeca106725 10382 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10383 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
Kojto 122:f9eeca106725 10384 #define TSC_CR_AM_Pos (2U)
Kojto 122:f9eeca106725 10385 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10386 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
Kojto 122:f9eeca106725 10387 #define TSC_CR_SYNCPOL_Pos (3U)
Kojto 122:f9eeca106725 10388 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10389 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
Kojto 122:f9eeca106725 10390 #define TSC_CR_IODEF_Pos (4U)
Kojto 122:f9eeca106725 10391 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10392 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
Kojto 122:f9eeca106725 10393
Kojto 122:f9eeca106725 10394 #define TSC_CR_MCV_Pos (5U)
Kojto 122:f9eeca106725 10395 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 10396 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
Kojto 122:f9eeca106725 10397 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10398 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10399 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10400
Kojto 122:f9eeca106725 10401 #define TSC_CR_PGPSC_Pos (12U)
Kojto 122:f9eeca106725 10402 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10403 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 122:f9eeca106725 10404 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10405 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10406 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10407
Kojto 122:f9eeca106725 10408 #define TSC_CR_SSPSC_Pos (15U)
Kojto 122:f9eeca106725 10409 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10410 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
Kojto 122:f9eeca106725 10411 #define TSC_CR_SSE_Pos (16U)
Kojto 122:f9eeca106725 10412 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10413 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
Kojto 122:f9eeca106725 10414
Kojto 122:f9eeca106725 10415 #define TSC_CR_SSD_Pos (17U)
Kojto 122:f9eeca106725 10416 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 10417 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 122:f9eeca106725 10418 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10419 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10420 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10421 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10422 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10423 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10424 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10425
Kojto 122:f9eeca106725 10426 #define TSC_CR_CTPL_Pos (24U)
Kojto 122:f9eeca106725 10427 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10428 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 122:f9eeca106725 10429 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10430 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10431 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10432 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10433
Kojto 122:f9eeca106725 10434 #define TSC_CR_CTPH_Pos (28U)
Kojto 122:f9eeca106725 10435 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 10436 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 122:f9eeca106725 10437 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10438 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10439 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10440 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 10441
Kojto 90:cb3d968589d8 10442 /******************* Bit definition for TSC_IER register ********************/
Kojto 122:f9eeca106725 10443 #define TSC_IER_EOAIE_Pos (0U)
Kojto 122:f9eeca106725 10444 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10445 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
Kojto 122:f9eeca106725 10446 #define TSC_IER_MCEIE_Pos (1U)
Kojto 122:f9eeca106725 10447 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10448 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
Kojto 90:cb3d968589d8 10449
Kojto 90:cb3d968589d8 10450 /******************* Bit definition for TSC_ICR register ********************/
Kojto 122:f9eeca106725 10451 #define TSC_ICR_EOAIC_Pos (0U)
Kojto 122:f9eeca106725 10452 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10453 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
Kojto 122:f9eeca106725 10454 #define TSC_ICR_MCEIC_Pos (1U)
Kojto 122:f9eeca106725 10455 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10456 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
Kojto 90:cb3d968589d8 10457
Kojto 90:cb3d968589d8 10458 /******************* Bit definition for TSC_ISR register ********************/
Kojto 122:f9eeca106725 10459 #define TSC_ISR_EOAF_Pos (0U)
Kojto 122:f9eeca106725 10460 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10461 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
Kojto 122:f9eeca106725 10462 #define TSC_ISR_MCEF_Pos (1U)
Kojto 122:f9eeca106725 10463 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10464 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
Kojto 90:cb3d968589d8 10465
Kojto 90:cb3d968589d8 10466 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 122:f9eeca106725 10467 #define TSC_IOHCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 10468 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10469 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10470 #define TSC_IOHCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 10471 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10472 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10473 #define TSC_IOHCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 10474 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10475 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10476 #define TSC_IOHCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 10477 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10478 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10479 #define TSC_IOHCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 10480 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10481 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10482 #define TSC_IOHCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 10483 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10484 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10485 #define TSC_IOHCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 10486 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10487 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10488 #define TSC_IOHCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 10489 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10490 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10491 #define TSC_IOHCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 10492 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10493 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10494 #define TSC_IOHCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 10495 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10496 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10497 #define TSC_IOHCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 10498 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10499 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10500 #define TSC_IOHCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 10501 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10502 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10503 #define TSC_IOHCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 10504 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10505 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10506 #define TSC_IOHCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 10507 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10508 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10509 #define TSC_IOHCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 10510 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10511 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10512 #define TSC_IOHCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 10513 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10514 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10515 #define TSC_IOHCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 10516 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10517 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10518 #define TSC_IOHCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 10519 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10520 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10521 #define TSC_IOHCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 10522 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10523 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10524 #define TSC_IOHCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 10525 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10526 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10527 #define TSC_IOHCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 10528 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10529 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10530 #define TSC_IOHCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 10531 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10532 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10533 #define TSC_IOHCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 10534 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10535 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10536 #define TSC_IOHCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 10537 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10538 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10539 #define TSC_IOHCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 10540 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10541 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10542 #define TSC_IOHCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 10543 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10544 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10545 #define TSC_IOHCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 10546 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10547 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10548 #define TSC_IOHCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 10549 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10550 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10551 #define TSC_IOHCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 10552 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10553 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10554 #define TSC_IOHCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 10555 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10556 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10557 #define TSC_IOHCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 10558 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10559 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 10560 #define TSC_IOHCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 10561 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10562 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 10563
Kojto 90:cb3d968589d8 10564 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 122:f9eeca106725 10565 #define TSC_IOASCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 10566 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10567 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
Kojto 122:f9eeca106725 10568 #define TSC_IOASCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 10569 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10570 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
Kojto 122:f9eeca106725 10571 #define TSC_IOASCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 10572 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10573 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
Kojto 122:f9eeca106725 10574 #define TSC_IOASCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 10575 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10576 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
Kojto 122:f9eeca106725 10577 #define TSC_IOASCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 10578 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10579 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
Kojto 122:f9eeca106725 10580 #define TSC_IOASCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 10581 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10582 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
Kojto 122:f9eeca106725 10583 #define TSC_IOASCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 10584 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10585 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
Kojto 122:f9eeca106725 10586 #define TSC_IOASCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 10587 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10588 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
Kojto 122:f9eeca106725 10589 #define TSC_IOASCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 10590 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10591 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
Kojto 122:f9eeca106725 10592 #define TSC_IOASCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 10593 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10594 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
Kojto 122:f9eeca106725 10595 #define TSC_IOASCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 10596 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10597 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
Kojto 122:f9eeca106725 10598 #define TSC_IOASCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 10599 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10600 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
Kojto 122:f9eeca106725 10601 #define TSC_IOASCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 10602 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10603 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
Kojto 122:f9eeca106725 10604 #define TSC_IOASCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 10605 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10606 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
Kojto 122:f9eeca106725 10607 #define TSC_IOASCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 10608 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10609 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
Kojto 122:f9eeca106725 10610 #define TSC_IOASCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 10611 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10612 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
Kojto 122:f9eeca106725 10613 #define TSC_IOASCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 10614 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10615 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
Kojto 122:f9eeca106725 10616 #define TSC_IOASCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 10617 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10618 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
Kojto 122:f9eeca106725 10619 #define TSC_IOASCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 10620 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10621 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
Kojto 122:f9eeca106725 10622 #define TSC_IOASCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 10623 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10624 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
Kojto 122:f9eeca106725 10625 #define TSC_IOASCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 10626 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10627 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
Kojto 122:f9eeca106725 10628 #define TSC_IOASCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 10629 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10630 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
Kojto 122:f9eeca106725 10631 #define TSC_IOASCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 10632 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10633 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
Kojto 122:f9eeca106725 10634 #define TSC_IOASCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 10635 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10636 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
Kojto 122:f9eeca106725 10637 #define TSC_IOASCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 10638 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10639 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
Kojto 122:f9eeca106725 10640 #define TSC_IOASCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 10641 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10642 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
Kojto 122:f9eeca106725 10643 #define TSC_IOASCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 10644 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10645 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
Kojto 122:f9eeca106725 10646 #define TSC_IOASCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 10647 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10648 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
Kojto 122:f9eeca106725 10649 #define TSC_IOASCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 10650 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10651 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
Kojto 122:f9eeca106725 10652 #define TSC_IOASCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 10653 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10654 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
Kojto 122:f9eeca106725 10655 #define TSC_IOASCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 10656 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10657 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
Kojto 122:f9eeca106725 10658 #define TSC_IOASCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 10659 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10660 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
Kojto 90:cb3d968589d8 10661
Kojto 90:cb3d968589d8 10662 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 122:f9eeca106725 10663 #define TSC_IOSCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 10664 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10665 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
Kojto 122:f9eeca106725 10666 #define TSC_IOSCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 10667 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10668 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
Kojto 122:f9eeca106725 10669 #define TSC_IOSCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 10670 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10671 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
Kojto 122:f9eeca106725 10672 #define TSC_IOSCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 10673 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10674 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
Kojto 122:f9eeca106725 10675 #define TSC_IOSCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 10676 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10677 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
Kojto 122:f9eeca106725 10678 #define TSC_IOSCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 10679 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10680 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
Kojto 122:f9eeca106725 10681 #define TSC_IOSCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 10682 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10683 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
Kojto 122:f9eeca106725 10684 #define TSC_IOSCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 10685 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10686 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
Kojto 122:f9eeca106725 10687 #define TSC_IOSCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 10688 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10689 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
Kojto 122:f9eeca106725 10690 #define TSC_IOSCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 10691 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10692 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
Kojto 122:f9eeca106725 10693 #define TSC_IOSCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 10694 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10695 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
Kojto 122:f9eeca106725 10696 #define TSC_IOSCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 10697 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10698 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
Kojto 122:f9eeca106725 10699 #define TSC_IOSCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 10700 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10701 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
Kojto 122:f9eeca106725 10702 #define TSC_IOSCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 10703 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10704 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
Kojto 122:f9eeca106725 10705 #define TSC_IOSCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 10706 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10707 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
Kojto 122:f9eeca106725 10708 #define TSC_IOSCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 10709 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10710 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
Kojto 122:f9eeca106725 10711 #define TSC_IOSCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 10712 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10713 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
Kojto 122:f9eeca106725 10714 #define TSC_IOSCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 10715 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10716 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
Kojto 122:f9eeca106725 10717 #define TSC_IOSCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 10718 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10719 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
Kojto 122:f9eeca106725 10720 #define TSC_IOSCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 10721 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10722 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
Kojto 122:f9eeca106725 10723 #define TSC_IOSCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 10724 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10725 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
Kojto 122:f9eeca106725 10726 #define TSC_IOSCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 10727 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10728 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
Kojto 122:f9eeca106725 10729 #define TSC_IOSCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 10730 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10731 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
Kojto 122:f9eeca106725 10732 #define TSC_IOSCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 10733 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10734 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
Kojto 122:f9eeca106725 10735 #define TSC_IOSCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 10736 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10737 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
Kojto 122:f9eeca106725 10738 #define TSC_IOSCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 10739 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10740 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
Kojto 122:f9eeca106725 10741 #define TSC_IOSCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 10742 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10743 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
Kojto 122:f9eeca106725 10744 #define TSC_IOSCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 10745 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10746 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
Kojto 122:f9eeca106725 10747 #define TSC_IOSCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 10748 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10749 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
Kojto 122:f9eeca106725 10750 #define TSC_IOSCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 10751 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10752 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
Kojto 122:f9eeca106725 10753 #define TSC_IOSCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 10754 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10755 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
Kojto 122:f9eeca106725 10756 #define TSC_IOSCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 10757 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10758 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
Kojto 90:cb3d968589d8 10759
Kojto 90:cb3d968589d8 10760 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 122:f9eeca106725 10761 #define TSC_IOCCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 10762 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10763 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
Kojto 122:f9eeca106725 10764 #define TSC_IOCCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 10765 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10766 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
Kojto 122:f9eeca106725 10767 #define TSC_IOCCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 10768 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10769 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
Kojto 122:f9eeca106725 10770 #define TSC_IOCCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 10771 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10772 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
Kojto 122:f9eeca106725 10773 #define TSC_IOCCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 10774 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10775 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
Kojto 122:f9eeca106725 10776 #define TSC_IOCCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 10777 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10778 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
Kojto 122:f9eeca106725 10779 #define TSC_IOCCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 10780 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10781 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
Kojto 122:f9eeca106725 10782 #define TSC_IOCCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 10783 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10784 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
Kojto 122:f9eeca106725 10785 #define TSC_IOCCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 10786 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10787 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
Kojto 122:f9eeca106725 10788 #define TSC_IOCCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 10789 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10790 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
Kojto 122:f9eeca106725 10791 #define TSC_IOCCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 10792 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10793 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
Kojto 122:f9eeca106725 10794 #define TSC_IOCCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 10795 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10796 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
Kojto 122:f9eeca106725 10797 #define TSC_IOCCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 10798 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10799 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
Kojto 122:f9eeca106725 10800 #define TSC_IOCCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 10801 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10802 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
Kojto 122:f9eeca106725 10803 #define TSC_IOCCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 10804 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10805 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
Kojto 122:f9eeca106725 10806 #define TSC_IOCCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 10807 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10808 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
Kojto 122:f9eeca106725 10809 #define TSC_IOCCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 10810 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10811 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
Kojto 122:f9eeca106725 10812 #define TSC_IOCCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 10813 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10814 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
Kojto 122:f9eeca106725 10815 #define TSC_IOCCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 10816 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10817 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
Kojto 122:f9eeca106725 10818 #define TSC_IOCCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 10819 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10820 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
Kojto 122:f9eeca106725 10821 #define TSC_IOCCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 10822 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10823 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
Kojto 122:f9eeca106725 10824 #define TSC_IOCCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 10825 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10826 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
Kojto 122:f9eeca106725 10827 #define TSC_IOCCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 10828 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10829 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
Kojto 122:f9eeca106725 10830 #define TSC_IOCCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 10831 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10832 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
Kojto 122:f9eeca106725 10833 #define TSC_IOCCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 10834 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10835 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
Kojto 122:f9eeca106725 10836 #define TSC_IOCCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 10837 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10838 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
Kojto 122:f9eeca106725 10839 #define TSC_IOCCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 10840 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10841 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
Kojto 122:f9eeca106725 10842 #define TSC_IOCCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 10843 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10844 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
Kojto 122:f9eeca106725 10845 #define TSC_IOCCR_G8_IO1_Pos (28U)
Kojto 122:f9eeca106725 10846 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10847 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
Kojto 122:f9eeca106725 10848 #define TSC_IOCCR_G8_IO2_Pos (29U)
Kojto 122:f9eeca106725 10849 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10850 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
Kojto 122:f9eeca106725 10851 #define TSC_IOCCR_G8_IO3_Pos (30U)
Kojto 122:f9eeca106725 10852 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10853 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
Kojto 122:f9eeca106725 10854 #define TSC_IOCCR_G8_IO4_Pos (31U)
Kojto 122:f9eeca106725 10855 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10856 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
Kojto 90:cb3d968589d8 10857
Kojto 90:cb3d968589d8 10858 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 122:f9eeca106725 10859 #define TSC_IOGCSR_G1E_Pos (0U)
Kojto 122:f9eeca106725 10860 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10861 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
Kojto 122:f9eeca106725 10862 #define TSC_IOGCSR_G2E_Pos (1U)
Kojto 122:f9eeca106725 10863 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10864 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
Kojto 122:f9eeca106725 10865 #define TSC_IOGCSR_G3E_Pos (2U)
Kojto 122:f9eeca106725 10866 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10867 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
Kojto 122:f9eeca106725 10868 #define TSC_IOGCSR_G4E_Pos (3U)
Kojto 122:f9eeca106725 10869 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10870 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
Kojto 122:f9eeca106725 10871 #define TSC_IOGCSR_G5E_Pos (4U)
Kojto 122:f9eeca106725 10872 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10873 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
Kojto 122:f9eeca106725 10874 #define TSC_IOGCSR_G6E_Pos (5U)
Kojto 122:f9eeca106725 10875 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10876 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
Kojto 122:f9eeca106725 10877 #define TSC_IOGCSR_G7E_Pos (6U)
Kojto 122:f9eeca106725 10878 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10879 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
Kojto 122:f9eeca106725 10880 #define TSC_IOGCSR_G8E_Pos (7U)
Kojto 122:f9eeca106725 10881 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10882 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
Kojto 122:f9eeca106725 10883 #define TSC_IOGCSR_G1S_Pos (16U)
Kojto 122:f9eeca106725 10884 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10885 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
Kojto 122:f9eeca106725 10886 #define TSC_IOGCSR_G2S_Pos (17U)
Kojto 122:f9eeca106725 10887 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10888 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
Kojto 122:f9eeca106725 10889 #define TSC_IOGCSR_G3S_Pos (18U)
Kojto 122:f9eeca106725 10890 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10891 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
Kojto 122:f9eeca106725 10892 #define TSC_IOGCSR_G4S_Pos (19U)
Kojto 122:f9eeca106725 10893 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10894 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
Kojto 122:f9eeca106725 10895 #define TSC_IOGCSR_G5S_Pos (20U)
Kojto 122:f9eeca106725 10896 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10897 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
Kojto 122:f9eeca106725 10898 #define TSC_IOGCSR_G6S_Pos (21U)
Kojto 122:f9eeca106725 10899 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10900 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
Kojto 122:f9eeca106725 10901 #define TSC_IOGCSR_G7S_Pos (22U)
Kojto 122:f9eeca106725 10902 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10903 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
Kojto 122:f9eeca106725 10904 #define TSC_IOGCSR_G8S_Pos (23U)
Kojto 122:f9eeca106725 10905 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10906 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
Kojto 90:cb3d968589d8 10907
Kojto 90:cb3d968589d8 10908 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 122:f9eeca106725 10909 #define TSC_IOGXCR_CNT_Pos (0U)
Kojto 122:f9eeca106725 10910 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 10911 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
Kojto 90:cb3d968589d8 10912
Kojto 90:cb3d968589d8 10913 /******************************************************************************/
Kojto 90:cb3d968589d8 10914 /* */
Kojto 90:cb3d968589d8 10915 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 90:cb3d968589d8 10916 /* */
Kojto 90:cb3d968589d8 10917 /******************************************************************************/
Kojto 122:f9eeca106725 10918
Kojto 122:f9eeca106725 10919 /*
Kojto 122:f9eeca106725 10920 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 10921 */
Kojto 122:f9eeca106725 10922
Kojto 122:f9eeca106725 10923 /* Support of 7 bits data length feature */
Kojto 122:f9eeca106725 10924 #define USART_7BITS_SUPPORT
Kojto 122:f9eeca106725 10925
Kojto 122:f9eeca106725 10926 /* Support of LIN feature */
Kojto 122:f9eeca106725 10927 #define USART_LIN_SUPPORT
Kojto 122:f9eeca106725 10928
Kojto 122:f9eeca106725 10929 /* Support of Smartcard feature */
Kojto 122:f9eeca106725 10930 #define USART_SMARTCARD_SUPPORT
Kojto 122:f9eeca106725 10931
Kojto 122:f9eeca106725 10932 /* Support of Irda feature */
Kojto 122:f9eeca106725 10933 #define USART_IRDA_SUPPORT
Kojto 122:f9eeca106725 10934
Kojto 122:f9eeca106725 10935 /* Support of Wake Up from Stop Mode feature */
Kojto 122:f9eeca106725 10936 #define USART_WUSM_SUPPORT
Kojto 122:f9eeca106725 10937
Kojto 122:f9eeca106725 10938 /* Support of Full Auto Baud rate feature (4 modes) activation */
Kojto 122:f9eeca106725 10939 #define USART_FABR_SUPPORT
Kojto 122:f9eeca106725 10940
Kojto 90:cb3d968589d8 10941 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 10942 #define USART_CR1_UE_Pos (0U)
Kojto 122:f9eeca106725 10943 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10944 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
Kojto 122:f9eeca106725 10945 #define USART_CR1_UESM_Pos (1U)
Kojto 122:f9eeca106725 10946 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10947 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
Kojto 122:f9eeca106725 10948 #define USART_CR1_RE_Pos (2U)
Kojto 122:f9eeca106725 10949 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10950 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
Kojto 122:f9eeca106725 10951 #define USART_CR1_TE_Pos (3U)
Kojto 122:f9eeca106725 10952 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10953 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
Kojto 122:f9eeca106725 10954 #define USART_CR1_IDLEIE_Pos (4U)
Kojto 122:f9eeca106725 10955 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10956 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 10957 #define USART_CR1_RXNEIE_Pos (5U)
Kojto 122:f9eeca106725 10958 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10959 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 10960 #define USART_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 10961 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10962 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 10963 #define USART_CR1_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 10964 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10965 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
Kojto 122:f9eeca106725 10966 #define USART_CR1_PEIE_Pos (8U)
Kojto 122:f9eeca106725 10967 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10968 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 10969 #define USART_CR1_PS_Pos (9U)
Kojto 122:f9eeca106725 10970 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10971 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
Kojto 122:f9eeca106725 10972 #define USART_CR1_PCE_Pos (10U)
Kojto 122:f9eeca106725 10973 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10974 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
Kojto 122:f9eeca106725 10975 #define USART_CR1_WAKE_Pos (11U)
Kojto 122:f9eeca106725 10976 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10977 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
Kojto 122:f9eeca106725 10978 #define USART_CR1_M0_Pos (12U)
Kojto 122:f9eeca106725 10979 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10980 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
Kojto 122:f9eeca106725 10981 #define USART_CR1_MME_Pos (13U)
Kojto 122:f9eeca106725 10982 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10983 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
Kojto 122:f9eeca106725 10984 #define USART_CR1_CMIE_Pos (14U)
Kojto 122:f9eeca106725 10985 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10986 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
Kojto 122:f9eeca106725 10987 #define USART_CR1_OVER8_Pos (15U)
Kojto 122:f9eeca106725 10988 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10989 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 122:f9eeca106725 10990 #define USART_CR1_DEDT_Pos (16U)
Kojto 122:f9eeca106725 10991 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 10992 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 122:f9eeca106725 10993 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10994 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10995 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10996 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10997 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10998 #define USART_CR1_DEAT_Pos (21U)
Kojto 122:f9eeca106725 10999 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
Kojto 122:f9eeca106725 11000 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 122:f9eeca106725 11001 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11002 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11003 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11004 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11005 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11006 #define USART_CR1_RTOIE_Pos (26U)
Kojto 122:f9eeca106725 11007 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11008 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
Kojto 122:f9eeca106725 11009 #define USART_CR1_EOBIE_Pos (27U)
Kojto 122:f9eeca106725 11010 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 11011 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
Kojto 122:f9eeca106725 11012 #define USART_CR1_M1_Pos (28U)
Kojto 122:f9eeca106725 11013 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11014 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
Kojto 122:f9eeca106725 11015 #define USART_CR1_M_Pos (12U)
Kojto 122:f9eeca106725 11016 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
Kojto 122:f9eeca106725 11017 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
Kojto 90:cb3d968589d8 11018
Kojto 90:cb3d968589d8 11019 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 11020 #define USART_CR2_ADDM7_Pos (4U)
Kojto 122:f9eeca106725 11021 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11022 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
Kojto 122:f9eeca106725 11023 #define USART_CR2_LBDL_Pos (5U)
Kojto 122:f9eeca106725 11024 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11025 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
Kojto 122:f9eeca106725 11026 #define USART_CR2_LBDIE_Pos (6U)
Kojto 122:f9eeca106725 11027 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11028 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 11029 #define USART_CR2_LBCL_Pos (8U)
Kojto 122:f9eeca106725 11030 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11031 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 11032 #define USART_CR2_CPHA_Pos (9U)
Kojto 122:f9eeca106725 11033 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11034 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 11035 #define USART_CR2_CPOL_Pos (10U)
Kojto 122:f9eeca106725 11036 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11037 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 11038 #define USART_CR2_CLKEN_Pos (11U)
Kojto 122:f9eeca106725 11039 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11040 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
Kojto 122:f9eeca106725 11041 #define USART_CR2_STOP_Pos (12U)
Kojto 122:f9eeca106725 11042 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 11043 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 11044 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11045 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11046 #define USART_CR2_LINEN_Pos (14U)
Kojto 122:f9eeca106725 11047 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11048 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
Kojto 122:f9eeca106725 11049 #define USART_CR2_SWAP_Pos (15U)
Kojto 122:f9eeca106725 11050 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11051 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
Kojto 122:f9eeca106725 11052 #define USART_CR2_RXINV_Pos (16U)
Kojto 122:f9eeca106725 11053 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11054 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
Kojto 122:f9eeca106725 11055 #define USART_CR2_TXINV_Pos (17U)
Kojto 122:f9eeca106725 11056 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11057 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
Kojto 122:f9eeca106725 11058 #define USART_CR2_DATAINV_Pos (18U)
Kojto 122:f9eeca106725 11059 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11060 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
Kojto 122:f9eeca106725 11061 #define USART_CR2_MSBFIRST_Pos (19U)
Kojto 122:f9eeca106725 11062 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11063 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
Kojto 122:f9eeca106725 11064 #define USART_CR2_ABREN_Pos (20U)
Kojto 122:f9eeca106725 11065 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11066 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
Kojto 122:f9eeca106725 11067 #define USART_CR2_ABRMODE_Pos (21U)
Kojto 122:f9eeca106725 11068 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 11069 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 122:f9eeca106725 11070 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11071 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11072 #define USART_CR2_RTOEN_Pos (23U)
Kojto 122:f9eeca106725 11073 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11074 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
Kojto 122:f9eeca106725 11075 #define USART_CR2_ADD_Pos (24U)
Kojto 122:f9eeca106725 11076 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 11077 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
Kojto 90:cb3d968589d8 11078
Kojto 90:cb3d968589d8 11079 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 11080 #define USART_CR3_EIE_Pos (0U)
Kojto 122:f9eeca106725 11081 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11082 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 11083 #define USART_CR3_IREN_Pos (1U)
Kojto 122:f9eeca106725 11084 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11085 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
Kojto 122:f9eeca106725 11086 #define USART_CR3_IRLP_Pos (2U)
Kojto 122:f9eeca106725 11087 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11088 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
Kojto 122:f9eeca106725 11089 #define USART_CR3_HDSEL_Pos (3U)
Kojto 122:f9eeca106725 11090 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11091 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 11092 #define USART_CR3_NACK_Pos (4U)
Kojto 122:f9eeca106725 11093 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11094 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
Kojto 122:f9eeca106725 11095 #define USART_CR3_SCEN_Pos (5U)
Kojto 122:f9eeca106725 11096 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11097 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
Kojto 122:f9eeca106725 11098 #define USART_CR3_DMAR_Pos (6U)
Kojto 122:f9eeca106725 11099 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11100 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 11101 #define USART_CR3_DMAT_Pos (7U)
Kojto 122:f9eeca106725 11102 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11103 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 11104 #define USART_CR3_RTSE_Pos (8U)
Kojto 122:f9eeca106725 11105 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11106 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
Kojto 122:f9eeca106725 11107 #define USART_CR3_CTSE_Pos (9U)
Kojto 122:f9eeca106725 11108 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11109 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
Kojto 122:f9eeca106725 11110 #define USART_CR3_CTSIE_Pos (10U)
Kojto 122:f9eeca106725 11111 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11112 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 11113 #define USART_CR3_ONEBIT_Pos (11U)
Kojto 122:f9eeca106725 11114 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11115 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
Kojto 122:f9eeca106725 11116 #define USART_CR3_OVRDIS_Pos (12U)
Kojto 122:f9eeca106725 11117 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11118 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
Kojto 122:f9eeca106725 11119 #define USART_CR3_DDRE_Pos (13U)
Kojto 122:f9eeca106725 11120 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11121 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
Kojto 122:f9eeca106725 11122 #define USART_CR3_DEM_Pos (14U)
Kojto 122:f9eeca106725 11123 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11124 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
Kojto 122:f9eeca106725 11125 #define USART_CR3_DEP_Pos (15U)
Kojto 122:f9eeca106725 11126 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11127 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
Kojto 122:f9eeca106725 11128 #define USART_CR3_SCARCNT_Pos (17U)
Kojto 122:f9eeca106725 11129 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 11130 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 122:f9eeca106725 11131 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11132 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11133 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11134 #define USART_CR3_WUS_Pos (20U)
Kojto 122:f9eeca106725 11135 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 11136 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 122:f9eeca106725 11137 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11138 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11139 #define USART_CR3_WUFIE_Pos (22U)
Kojto 122:f9eeca106725 11140 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11141 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
Kojto 90:cb3d968589d8 11142
Kojto 90:cb3d968589d8 11143 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 11144 #define USART_BRR_DIV_FRACTION_Pos (0U)
Kojto 122:f9eeca106725 11145 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 11146 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 11147 #define USART_BRR_DIV_MANTISSA_Pos (4U)
Kojto 122:f9eeca106725 11148 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 11149 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
Kojto 90:cb3d968589d8 11150
Kojto 90:cb3d968589d8 11151 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 11152 #define USART_GTPR_PSC_Pos (0U)
Kojto 122:f9eeca106725 11153 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11154 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 11155 #define USART_GTPR_GT_Pos (8U)
Kojto 122:f9eeca106725 11156 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 11157 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
Kojto 90:cb3d968589d8 11158
Kojto 90:cb3d968589d8 11159
Kojto 90:cb3d968589d8 11160 /******************* Bit definition for USART_RTOR register *****************/
Kojto 122:f9eeca106725 11161 #define USART_RTOR_RTO_Pos (0U)
Kojto 122:f9eeca106725 11162 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
Kojto 122:f9eeca106725 11163 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
Kojto 122:f9eeca106725 11164 #define USART_RTOR_BLEN_Pos (24U)
Kojto 122:f9eeca106725 11165 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 11166 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
Kojto 90:cb3d968589d8 11167
Kojto 90:cb3d968589d8 11168 /******************* Bit definition for USART_RQR register ******************/
Kojto 122:f9eeca106725 11169 #define USART_RQR_ABRRQ_Pos (0U)
Kojto 122:f9eeca106725 11170 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11171 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
Kojto 122:f9eeca106725 11172 #define USART_RQR_SBKRQ_Pos (1U)
Kojto 122:f9eeca106725 11173 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11174 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
Kojto 122:f9eeca106725 11175 #define USART_RQR_MMRQ_Pos (2U)
Kojto 122:f9eeca106725 11176 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11177 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
Kojto 122:f9eeca106725 11178 #define USART_RQR_RXFRQ_Pos (3U)
Kojto 122:f9eeca106725 11179 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11180 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
Kojto 122:f9eeca106725 11181 #define USART_RQR_TXFRQ_Pos (4U)
Kojto 122:f9eeca106725 11182 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11183 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
Kojto 90:cb3d968589d8 11184
Kojto 90:cb3d968589d8 11185 /******************* Bit definition for USART_ISR register ******************/
Kojto 122:f9eeca106725 11186 #define USART_ISR_PE_Pos (0U)
Kojto 122:f9eeca106725 11187 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11188 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
Kojto 122:f9eeca106725 11189 #define USART_ISR_FE_Pos (1U)
Kojto 122:f9eeca106725 11190 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11191 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
Kojto 122:f9eeca106725 11192 #define USART_ISR_NE_Pos (2U)
Kojto 122:f9eeca106725 11193 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11194 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
Kojto 122:f9eeca106725 11195 #define USART_ISR_ORE_Pos (3U)
Kojto 122:f9eeca106725 11196 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11197 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
Kojto 122:f9eeca106725 11198 #define USART_ISR_IDLE_Pos (4U)
Kojto 122:f9eeca106725 11199 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11200 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
Kojto 122:f9eeca106725 11201 #define USART_ISR_RXNE_Pos (5U)
Kojto 122:f9eeca106725 11202 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11203 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 11204 #define USART_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 11205 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11206 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
Kojto 122:f9eeca106725 11207 #define USART_ISR_TXE_Pos (7U)
Kojto 122:f9eeca106725 11208 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11209 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 11210 #define USART_ISR_LBDF_Pos (8U)
Kojto 122:f9eeca106725 11211 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11212 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
Kojto 122:f9eeca106725 11213 #define USART_ISR_CTSIF_Pos (9U)
Kojto 122:f9eeca106725 11214 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11215 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
Kojto 122:f9eeca106725 11216 #define USART_ISR_CTS_Pos (10U)
Kojto 122:f9eeca106725 11217 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11218 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
Kojto 122:f9eeca106725 11219 #define USART_ISR_RTOF_Pos (11U)
Kojto 122:f9eeca106725 11220 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11221 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
Kojto 122:f9eeca106725 11222 #define USART_ISR_EOBF_Pos (12U)
Kojto 122:f9eeca106725 11223 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11224 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
Kojto 122:f9eeca106725 11225 #define USART_ISR_ABRE_Pos (14U)
Kojto 122:f9eeca106725 11226 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11227 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
Kojto 122:f9eeca106725 11228 #define USART_ISR_ABRF_Pos (15U)
Kojto 122:f9eeca106725 11229 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11230 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
Kojto 122:f9eeca106725 11231 #define USART_ISR_BUSY_Pos (16U)
Kojto 122:f9eeca106725 11232 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11233 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
Kojto 122:f9eeca106725 11234 #define USART_ISR_CMF_Pos (17U)
Kojto 122:f9eeca106725 11235 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11236 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
Kojto 122:f9eeca106725 11237 #define USART_ISR_SBKF_Pos (18U)
Kojto 122:f9eeca106725 11238 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11239 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
Kojto 122:f9eeca106725 11240 #define USART_ISR_RWU_Pos (19U)
Kojto 122:f9eeca106725 11241 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11242 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
Kojto 122:f9eeca106725 11243 #define USART_ISR_WUF_Pos (20U)
Kojto 122:f9eeca106725 11244 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11245 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
Kojto 122:f9eeca106725 11246 #define USART_ISR_TEACK_Pos (21U)
Kojto 122:f9eeca106725 11247 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11248 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
Kojto 122:f9eeca106725 11249 #define USART_ISR_REACK_Pos (22U)
Kojto 122:f9eeca106725 11250 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11251 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
Kojto 90:cb3d968589d8 11252
Kojto 90:cb3d968589d8 11253 /******************* Bit definition for USART_ICR register ******************/
Kojto 122:f9eeca106725 11254 #define USART_ICR_PECF_Pos (0U)
Kojto 122:f9eeca106725 11255 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11256 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
Kojto 122:f9eeca106725 11257 #define USART_ICR_FECF_Pos (1U)
Kojto 122:f9eeca106725 11258 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11259 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
Kojto 122:f9eeca106725 11260 #define USART_ICR_NCF_Pos (2U)
Kojto 122:f9eeca106725 11261 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11262 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
Kojto 122:f9eeca106725 11263 #define USART_ICR_ORECF_Pos (3U)
Kojto 122:f9eeca106725 11264 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11265 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
Kojto 122:f9eeca106725 11266 #define USART_ICR_IDLECF_Pos (4U)
Kojto 122:f9eeca106725 11267 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11268 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
Kojto 122:f9eeca106725 11269 #define USART_ICR_TCCF_Pos (6U)
Kojto 122:f9eeca106725 11270 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11271 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
Kojto 122:f9eeca106725 11272 #define USART_ICR_LBDCF_Pos (8U)
Kojto 122:f9eeca106725 11273 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11274 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
Kojto 122:f9eeca106725 11275 #define USART_ICR_CTSCF_Pos (9U)
Kojto 122:f9eeca106725 11276 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11277 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
Kojto 122:f9eeca106725 11278 #define USART_ICR_RTOCF_Pos (11U)
Kojto 122:f9eeca106725 11279 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11280 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
Kojto 122:f9eeca106725 11281 #define USART_ICR_EOBCF_Pos (12U)
Kojto 122:f9eeca106725 11282 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11283 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
Kojto 122:f9eeca106725 11284 #define USART_ICR_CMCF_Pos (17U)
Kojto 122:f9eeca106725 11285 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11286 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
Kojto 122:f9eeca106725 11287 #define USART_ICR_WUCF_Pos (20U)
Kojto 122:f9eeca106725 11288 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11289 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
Kojto 90:cb3d968589d8 11290
Kojto 90:cb3d968589d8 11291 /******************* Bit definition for USART_RDR register ******************/
Kojto 122:f9eeca106725 11292 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 90:cb3d968589d8 11293
Kojto 90:cb3d968589d8 11294 /******************* Bit definition for USART_TDR register ******************/
Kojto 122:f9eeca106725 11295 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 90:cb3d968589d8 11296
Kojto 90:cb3d968589d8 11297 /******************************************************************************/
Kojto 90:cb3d968589d8 11298 /* */
Kojto 90:cb3d968589d8 11299 /* Window WATCHDOG (WWDG) */
Kojto 90:cb3d968589d8 11300 /* */
Kojto 90:cb3d968589d8 11301 /******************************************************************************/
Kojto 122:f9eeca106725 11302
Kojto 90:cb3d968589d8 11303 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 11304 #define WWDG_CR_T_Pos (0U)
Kojto 122:f9eeca106725 11305 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 11306 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 11307 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11308 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11309 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11310 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11311 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11312 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11313 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11314
Kojto 122:f9eeca106725 11315 /* Legacy defines */
Kojto 122:f9eeca106725 11316 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 11317 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 11318 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 11319 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 11320 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 11321 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 11322 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 11323
Kojto 122:f9eeca106725 11324 #define WWDG_CR_WDGA_Pos (7U)
Kojto 122:f9eeca106725 11325 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11326 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
Kojto 90:cb3d968589d8 11327
Kojto 90:cb3d968589d8 11328 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 11329 #define WWDG_CFR_W_Pos (0U)
Kojto 122:f9eeca106725 11330 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 11331 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 11332 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11333 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11334 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11335 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11336 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11337 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11338 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11339
Kojto 122:f9eeca106725 11340 /* Legacy defines */
Kojto 122:f9eeca106725 11341 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 11342 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 11343 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 11344 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 11345 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 11346 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 11347 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 11348
Kojto 122:f9eeca106725 11349 #define WWDG_CFR_WDGTB_Pos (7U)
Kojto 122:f9eeca106725 11350 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
Kojto 122:f9eeca106725 11351 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 11352 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11353 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11354
Kojto 122:f9eeca106725 11355 /* Legacy defines */
Kojto 122:f9eeca106725 11356 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 11357 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 11358
Kojto 122:f9eeca106725 11359 #define WWDG_CFR_EWI_Pos (9U)
Kojto 122:f9eeca106725 11360 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11361 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
Kojto 90:cb3d968589d8 11362
Kojto 90:cb3d968589d8 11363 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 11364 #define WWDG_SR_EWIF_Pos (0U)
Kojto 122:f9eeca106725 11365 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11366 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
Kojto 90:cb3d968589d8 11367
Kojto 90:cb3d968589d8 11368 /**
Kojto 90:cb3d968589d8 11369 * @}
Kojto 90:cb3d968589d8 11370 */
Kojto 90:cb3d968589d8 11371
Kojto 90:cb3d968589d8 11372 /**
Kojto 90:cb3d968589d8 11373 * @}
Kojto 90:cb3d968589d8 11374 */
Kojto 90:cb3d968589d8 11375
Kojto 90:cb3d968589d8 11376
Kojto 90:cb3d968589d8 11377 /** @addtogroup Exported_macro
Kojto 90:cb3d968589d8 11378 * @{
Kojto 90:cb3d968589d8 11379 */
Kojto 90:cb3d968589d8 11380
Kojto 90:cb3d968589d8 11381 /****************************** ADC Instances *********************************/
Kojto 90:cb3d968589d8 11382 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 90:cb3d968589d8 11383
Kojto 90:cb3d968589d8 11384 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 90:cb3d968589d8 11385
Kojto 90:cb3d968589d8 11386 /******************************* CAN Instances ********************************/
Kojto 90:cb3d968589d8 11387 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
Kojto 90:cb3d968589d8 11388
Kojto 90:cb3d968589d8 11389 /****************************** COMP Instances *********************************/
Kojto 90:cb3d968589d8 11390 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Kojto 90:cb3d968589d8 11391 ((INSTANCE) == COMP2))
Kojto 90:cb3d968589d8 11392
Kojto 122:f9eeca106725 11393 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
Kojto 122:f9eeca106725 11394
Kojto 90:cb3d968589d8 11395 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
Kojto 90:cb3d968589d8 11396
Kojto 90:cb3d968589d8 11397 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
Kojto 90:cb3d968589d8 11398
Kojto 90:cb3d968589d8 11399 /****************************** CEC Instances *********************************/
Kojto 90:cb3d968589d8 11400 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
Kojto 90:cb3d968589d8 11401
Kojto 90:cb3d968589d8 11402 /****************************** CRC Instances *********************************/
Kojto 90:cb3d968589d8 11403 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 90:cb3d968589d8 11404
Kojto 90:cb3d968589d8 11405 /******************************* DAC Instances ********************************/
Kojto 122:f9eeca106725 11406 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
Kojto 122:f9eeca106725 11407
Kojto 122:f9eeca106725 11408 /******************************* DMA Instances ********************************/
Kojto 90:cb3d968589d8 11409 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 90:cb3d968589d8 11410 ((INSTANCE) == DMA1_Channel2) || \
Kojto 90:cb3d968589d8 11411 ((INSTANCE) == DMA1_Channel3) || \
Kojto 90:cb3d968589d8 11412 ((INSTANCE) == DMA1_Channel4) || \
Kojto 90:cb3d968589d8 11413 ((INSTANCE) == DMA1_Channel5) || \
Kojto 90:cb3d968589d8 11414 ((INSTANCE) == DMA1_Channel6) || \
Kojto 90:cb3d968589d8 11415 ((INSTANCE) == DMA1_Channel7) || \
Kojto 90:cb3d968589d8 11416 ((INSTANCE) == DMA2_Channel1) || \
Kojto 90:cb3d968589d8 11417 ((INSTANCE) == DMA2_Channel2) || \
Kojto 90:cb3d968589d8 11418 ((INSTANCE) == DMA2_Channel3) || \
Kojto 90:cb3d968589d8 11419 ((INSTANCE) == DMA2_Channel4) || \
Kojto 90:cb3d968589d8 11420 ((INSTANCE) == DMA2_Channel5))
Kojto 90:cb3d968589d8 11421
Kojto 90:cb3d968589d8 11422 /****************************** GPIO Instances ********************************/
Kojto 93:e188a91d3eaa 11423 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 11424 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 11425 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 11426 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 11427 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 11428 ((INSTANCE) == GPIOF))
Kojto 122:f9eeca106725 11429
Kojto 122:f9eeca106725 11430 /**************************** GPIO Alternate Function Instances ***************/
Kojto 93:e188a91d3eaa 11431 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 11432 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 11433 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 11434 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 11435 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 11436 ((INSTANCE) == GPIOF))
Kojto 93:e188a91d3eaa 11437
Kojto 122:f9eeca106725 11438 /****************************** GPIO Lock Instances ***************************/
Kojto 90:cb3d968589d8 11439 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 90:cb3d968589d8 11440 ((INSTANCE) == GPIOB))
Kojto 90:cb3d968589d8 11441
Kojto 90:cb3d968589d8 11442 /****************************** I2C Instances *********************************/
Kojto 90:cb3d968589d8 11443 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 90:cb3d968589d8 11444 ((INSTANCE) == I2C2))
Kojto 90:cb3d968589d8 11445
Kojto 122:f9eeca106725 11446 /****************** I2C Instances : wakeup capability from stop modes *********/
Kojto 122:f9eeca106725 11447 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 122:f9eeca106725 11448
Kojto 90:cb3d968589d8 11449 /****************************** I2S Instances *********************************/
Kojto 90:cb3d968589d8 11450 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 11451 ((INSTANCE) == SPI2))
Kojto 90:cb3d968589d8 11452
Kojto 90:cb3d968589d8 11453 /****************************** IWDG Instances ********************************/
Kojto 90:cb3d968589d8 11454 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 90:cb3d968589d8 11455
Kojto 90:cb3d968589d8 11456 /****************************** RTC Instances *********************************/
Kojto 90:cb3d968589d8 11457 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 90:cb3d968589d8 11458
Kojto 90:cb3d968589d8 11459 /****************************** SMBUS Instances *********************************/
Kojto 90:cb3d968589d8 11460 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 90:cb3d968589d8 11461
Kojto 90:cb3d968589d8 11462 /****************************** SPI Instances *********************************/
Kojto 90:cb3d968589d8 11463 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 11464 ((INSTANCE) == SPI2))
Kojto 90:cb3d968589d8 11465
Kojto 90:cb3d968589d8 11466 /****************************** TIM Instances *********************************/
Kojto 90:cb3d968589d8 11467 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11468 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11469 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11470 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11471 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 11472 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 11473 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 11474 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11475 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11476 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11477
Kojto 90:cb3d968589d8 11478 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11479 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11480 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11481 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11482 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 11483 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11484 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11485 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11486
Kojto 90:cb3d968589d8 11487 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11488 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11489 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11490 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11491 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 11492
Kojto 90:cb3d968589d8 11493 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11494 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11495 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11496 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11497
Kojto 90:cb3d968589d8 11498 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11499 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11500 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11501 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11502
Kojto 90:cb3d968589d8 11503 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11504 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11505 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11506 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11507
Kojto 90:cb3d968589d8 11508 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11509 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11510 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11511 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11512
Kojto 90:cb3d968589d8 11513 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11514 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11515 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11516 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11517 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 11518
Kojto 90:cb3d968589d8 11519 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11520 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11521 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11522 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11523 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 11524
Kojto 90:cb3d968589d8 11525 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11526 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11527 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11528 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11529
Kojto 90:cb3d968589d8 11530 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11531 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11532 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11533 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11534
Kojto 90:cb3d968589d8 11535 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11536 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 11537
Kojto 122:f9eeca106725 11538 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
Kojto 122:f9eeca106725 11539 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 11540
Kojto 122:f9eeca106725 11541 #define IS_TIM_ETR_INSTANCE(INSTANCE)\
Kojto 122:f9eeca106725 11542 (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 11543 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 11544 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11545
Kojto 90:cb3d968589d8 11546 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11547 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11548 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11549 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11550
Kojto 90:cb3d968589d8 11551 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11552 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11553 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11554 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11555 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 11556 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 11557 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 11558
Kojto 90:cb3d968589d8 11559 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11560 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11561 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11562 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11563 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 11564
Kojto 90:cb3d968589d8 11565 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11566 ((INSTANCE) == TIM2)
Kojto 90:cb3d968589d8 11567
Kojto 90:cb3d968589d8 11568 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11569 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11570 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11571 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11572 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11573 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11574 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11575
Kojto 90:cb3d968589d8 11576 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11577 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11578 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11579 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11580 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11581
Kojto 90:cb3d968589d8 11582 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 11583 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 11584 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 11585 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 11586 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 11587 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 11588 || \
Kojto 90:cb3d968589d8 11589 (((INSTANCE) == TIM2) && \
Kojto 90:cb3d968589d8 11590 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 11591 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 11592 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 11593 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 11594 || \
Kojto 90:cb3d968589d8 11595 (((INSTANCE) == TIM3) && \
Kojto 90:cb3d968589d8 11596 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 11597 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 11598 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 11599 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 11600 || \
Kojto 90:cb3d968589d8 11601 (((INSTANCE) == TIM14) && \
Kojto 90:cb3d968589d8 11602 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 11603 || \
Kojto 90:cb3d968589d8 11604 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 11605 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 11606 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 90:cb3d968589d8 11607 || \
Kojto 90:cb3d968589d8 11608 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 11609 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 11610 || \
Kojto 90:cb3d968589d8 11611 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 11612 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 90:cb3d968589d8 11613
Kojto 90:cb3d968589d8 11614 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 11615 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 11616 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 11617 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 11618 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 90:cb3d968589d8 11619 || \
Kojto 90:cb3d968589d8 11620 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 11621 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 11622 || \
Kojto 90:cb3d968589d8 11623 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 11624 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 11625 || \
Kojto 90:cb3d968589d8 11626 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 11627 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 90:cb3d968589d8 11628
Kojto 90:cb3d968589d8 11629 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11630 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11631 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11632 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 11633
Kojto 90:cb3d968589d8 11634 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11635 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11636 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11637 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11638 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11639
Kojto 90:cb3d968589d8 11640 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11641 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11642 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11643 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11644 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 11645 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11646 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11647 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11648
Kojto 90:cb3d968589d8 11649 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11650 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11651 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11652 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11653 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 11654 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 11655 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11656 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11657 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11658
Kojto 90:cb3d968589d8 11659 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11660 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11661 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 11662 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 11663 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11664 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11665 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11666
Kojto 90:cb3d968589d8 11667 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11668 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 11669 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 11670 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 11671 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 11672
Kojto 90:cb3d968589d8 11673 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 11674 ((INSTANCE) == TIM14)
Kojto 90:cb3d968589d8 11675
Kojto 90:cb3d968589d8 11676 /****************************** TSC Instances *********************************/
Kojto 90:cb3d968589d8 11677 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Kojto 90:cb3d968589d8 11678
Kojto 90:cb3d968589d8 11679 /*********************** UART Instances : IRDA mode ***************************/
Kojto 90:cb3d968589d8 11680 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11681 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11682 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 11683
Kojto 90:cb3d968589d8 11684 /********************* UART Instances : Smard card mode ***********************/
Kojto 90:cb3d968589d8 11685 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11686 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11687 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 11688
Kojto 90:cb3d968589d8 11689 /******************** USART Instances : Synchronous mode **********************/
Kojto 90:cb3d968589d8 11690 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11691 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11692 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 11693 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 11694 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 11695 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 11696 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 11697 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 11698
Kojto 90:cb3d968589d8 11699 /******************** USART Instances : auto Baud rate detection **************/
Kojto 90:cb3d968589d8 11700 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11701 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11702 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 11703
Kojto 90:cb3d968589d8 11704 /******************** UART Instances : Asynchronous mode **********************/
Kojto 90:cb3d968589d8 11705 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11706 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11707 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 11708 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 11709 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 11710 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 11711 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 11712 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 11713
Kojto 90:cb3d968589d8 11714 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 90:cb3d968589d8 11715 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11716 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11717 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 11718 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 11719 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 11720 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 11721 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 11722 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 11723
Kojto 90:cb3d968589d8 11724 /****************** UART Instances : Hardware Flow control ********************/
Kojto 90:cb3d968589d8 11725 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11726 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11727 ((INSTANCE) == USART3) || \
Kojto 122:f9eeca106725 11728 ((INSTANCE) == USART4))
Kojto 90:cb3d968589d8 11729
Kojto 90:cb3d968589d8 11730 /****************** UART Instances : LIN mode ********************/
Kojto 90:cb3d968589d8 11731 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11732 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11733 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 11734
Kojto 90:cb3d968589d8 11735 /****************** UART Instances : wakeup from stop mode ********************/
Kojto 122:f9eeca106725 11736 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 11737 ((INSTANCE) == USART2) || \
Kojto 122:f9eeca106725 11738 ((INSTANCE) == USART3))
Kojto 122:f9eeca106725 11739 /* Old macro definition maintained for legacy purpose */
Kojto 122:f9eeca106725 11740 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
Kojto 90:cb3d968589d8 11741
Kojto 90:cb3d968589d8 11742 /****************** UART Instances : Driver enable detection ********************/
Kojto 90:cb3d968589d8 11743 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 11744 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 11745 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 11746 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 11747 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 11748 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 11749 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 11750 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 11751
Kojto 90:cb3d968589d8 11752 /****************************** WWDG Instances ********************************/
Kojto 90:cb3d968589d8 11753 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 90:cb3d968589d8 11754
Kojto 90:cb3d968589d8 11755 /**
Kojto 90:cb3d968589d8 11756 * @}
Kojto 90:cb3d968589d8 11757 */
Kojto 90:cb3d968589d8 11758
Kojto 108:34e6b704fe68 11759
Kojto 90:cb3d968589d8 11760 /******************************************************************************/
Kojto 122:f9eeca106725 11761 /* For a painless codes migration between the STM32F0xx device product */
Kojto 90:cb3d968589d8 11762 /* lines, the aliases defined below are put in place to overcome the */
Kojto 90:cb3d968589d8 11763 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 122:f9eeca106725 11764 /* No need to update developed interrupt code when moving across */
Kojto 122:f9eeca106725 11765 /* product lines within the same STM32F0 Family */
Kojto 90:cb3d968589d8 11766 /******************************************************************************/
Kojto 90:cb3d968589d8 11767
Kojto 90:cb3d968589d8 11768 /* Aliases for __IRQn */
Kojto 122:f9eeca106725 11769 #define ADC1_IRQn ADC1_COMP_IRQn
Kojto 122:f9eeca106725 11770 #define DMA1_Channel1_IRQn DMA1_Ch1_IRQn
Kojto 122:f9eeca106725 11771 #define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn
Kojto 122:f9eeca106725 11772 #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
Kojto 122:f9eeca106725 11773 #define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
Kojto 122:f9eeca106725 11774 #define PVD_IRQn PVD_VDDIO2_IRQn
Kojto 122:f9eeca106725 11775 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
Kojto 122:f9eeca106725 11776 #define RCC_IRQn RCC_CRS_IRQn
Kojto 122:f9eeca106725 11777 #define TIM6_IRQn TIM6_DAC_IRQn
Kojto 122:f9eeca106725 11778 #define USART3_4_IRQn USART3_8_IRQn
Kojto 122:f9eeca106725 11779 #define USART3_6_IRQn USART3_8_IRQn
Kojto 122:f9eeca106725 11780
Kojto 90:cb3d968589d8 11781
Kojto 90:cb3d968589d8 11782 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 11783 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
Kojto 122:f9eeca106725 11784 #define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler
Kojto 122:f9eeca106725 11785 #define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
Kojto 122:f9eeca106725 11786 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
Kojto 122:f9eeca106725 11787 #define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
Kojto 90:cb3d968589d8 11788 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 90:cb3d968589d8 11789 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 90:cb3d968589d8 11790 #define RCC_IRQHandler RCC_CRS_IRQHandler
Kojto 90:cb3d968589d8 11791 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
Kojto 90:cb3d968589d8 11792 #define USART3_4_IRQHandler USART3_8_IRQHandler
Kojto 122:f9eeca106725 11793 #define USART3_6_IRQHandler USART3_8_IRQHandler
Kojto 122:f9eeca106725 11794
Kojto 90:cb3d968589d8 11795
Kojto 90:cb3d968589d8 11796 #ifdef __cplusplus
Kojto 90:cb3d968589d8 11797 }
Kojto 90:cb3d968589d8 11798 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 11799
Kojto 90:cb3d968589d8 11800 #endif /* __STM32F091xC_H */
Kojto 90:cb3d968589d8 11801
Kojto 90:cb3d968589d8 11802 /**
Kojto 90:cb3d968589d8 11803 * @}
Kojto 90:cb3d968589d8 11804 */
Kojto 90:cb3d968589d8 11805
Kojto 90:cb3d968589d8 11806 /**
Kojto 90:cb3d968589d8 11807 * @}
Kojto 90:cb3d968589d8 11808 */
Kojto 90:cb3d968589d8 11809
Kojto 90:cb3d968589d8 11810 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/