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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F070RB/stm32f0xx_hal_dma.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
108:34e6b704fe68 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f0xx_hal_dma.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.4.0
Kojto 122:f9eeca106725 6 * @date 27-May-2016
Kojto 93:e188a91d3eaa 7 * @brief Header file of DMA HAL module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F0xx_HAL_DMA_H
Kojto 93:e188a91d3eaa 40 #define __STM32F0xx_HAL_DMA_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f0xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 93:e188a91d3eaa 52
Kojto 93:e188a91d3eaa 53 /** @addtogroup DMA
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 93:e188a91d3eaa 56
Kojto 93:e188a91d3eaa 57 /* Exported types ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 58
Kojto 93:e188a91d3eaa 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 93:e188a91d3eaa 60 * @{
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62
Kojto 93:e188a91d3eaa 63 /**
Kojto 93:e188a91d3eaa 64 * @brief DMA Configuration Structure definition
Kojto 93:e188a91d3eaa 65 */
Kojto 93:e188a91d3eaa 66 typedef struct
Kojto 93:e188a91d3eaa 67 {
Kojto 93:e188a91d3eaa 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 93:e188a91d3eaa 69 from memory to memory or from peripheral to memory.
Kojto 93:e188a91d3eaa 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 93:e188a91d3eaa 71
Kojto 93:e188a91d3eaa 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 93:e188a91d3eaa 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 93:e188a91d3eaa 74
Kojto 93:e188a91d3eaa 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 93:e188a91d3eaa 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 93:e188a91d3eaa 77
Kojto 93:e188a91d3eaa 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 93:e188a91d3eaa 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 93:e188a91d3eaa 80
Kojto 93:e188a91d3eaa 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 93:e188a91d3eaa 82 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 93:e188a91d3eaa 83
Kojto 93:e188a91d3eaa 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
Kojto 93:e188a91d3eaa 85 This parameter can be a value of @ref DMA_mode
Kojto 93:e188a91d3eaa 86 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 93:e188a91d3eaa 87 data transfer is configured on the selected Channel */
Kojto 93:e188a91d3eaa 88
Kojto 93:e188a91d3eaa 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
Kojto 93:e188a91d3eaa 90 This parameter can be a value of @ref DMA_Priority_level */
Kojto 93:e188a91d3eaa 91 } DMA_InitTypeDef;
Kojto 93:e188a91d3eaa 92
Kojto 93:e188a91d3eaa 93 /**
Kojto 93:e188a91d3eaa 94 * @brief DMA Configuration enumeration values definition
Kojto 93:e188a91d3eaa 95 */
Kojto 93:e188a91d3eaa 96 typedef enum
Kojto 93:e188a91d3eaa 97 {
Kojto 93:e188a91d3eaa 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
Kojto 93:e188a91d3eaa 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
Kojto 93:e188a91d3eaa 100
Kojto 93:e188a91d3eaa 101 } DMA_ControlTypeDef;
Kojto 93:e188a91d3eaa 102
Kojto 93:e188a91d3eaa 103 /**
Kojto 93:e188a91d3eaa 104 * @brief HAL DMA State structures definition
Kojto 93:e188a91d3eaa 105 */
Kojto 93:e188a91d3eaa 106 typedef enum
Kojto 93:e188a91d3eaa 107 {
Kojto 93:e188a91d3eaa 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 108:34e6b704fe68 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
Kojto 93:e188a91d3eaa 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
Kojto 93:e188a91d3eaa 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
Kojto 93:e188a91d3eaa 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
Kojto 108:34e6b704fe68 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
Kojto 93:e188a91d3eaa 114 }HAL_DMA_StateTypeDef;
Kojto 93:e188a91d3eaa 115
Kojto 93:e188a91d3eaa 116 /**
Kojto 93:e188a91d3eaa 117 * @brief HAL DMA Error Code structure definition
Kojto 93:e188a91d3eaa 118 */
Kojto 93:e188a91d3eaa 119 typedef enum
Kojto 93:e188a91d3eaa 120 {
Kojto 93:e188a91d3eaa 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
Kojto 93:e188a91d3eaa 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
Kojto 108:34e6b704fe68 123 }HAL_DMA_LevelCompleteTypeDef;
Kojto 93:e188a91d3eaa 124
Kojto 93:e188a91d3eaa 125 /**
Kojto 93:e188a91d3eaa 126 * @brief DMA handle Structure definition
Kojto 93:e188a91d3eaa 127 */
Kojto 93:e188a91d3eaa 128 typedef struct __DMA_HandleTypeDef
Kojto 93:e188a91d3eaa 129 {
Kojto 93:e188a91d3eaa 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
Kojto 93:e188a91d3eaa 131
Kojto 93:e188a91d3eaa 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 93:e188a91d3eaa 133
Kojto 93:e188a91d3eaa 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 93:e188a91d3eaa 135
Kojto 108:34e6b704fe68 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 93:e188a91d3eaa 137
Kojto 93:e188a91d3eaa 138 void *Parent; /*!< Parent object state */
Kojto 93:e188a91d3eaa 139
Kojto 93:e188a91d3eaa 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 93:e188a91d3eaa 141
Kojto 93:e188a91d3eaa 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 93:e188a91d3eaa 143
Kojto 93:e188a91d3eaa 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 93:e188a91d3eaa 145
Kojto 122:f9eeca106725 146 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
Kojto 122:f9eeca106725 147
Kojto 93:e188a91d3eaa 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 93:e188a91d3eaa 149 } DMA_HandleTypeDef;
Kojto 108:34e6b704fe68 150
Kojto 93:e188a91d3eaa 151 /**
Kojto 93:e188a91d3eaa 152 * @}
Kojto 93:e188a91d3eaa 153 */
Kojto 93:e188a91d3eaa 154
Kojto 93:e188a91d3eaa 155 /* Exported constants --------------------------------------------------------*/
Kojto 108:34e6b704fe68 156
Kojto 93:e188a91d3eaa 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 93:e188a91d3eaa 158 * @{
Kojto 93:e188a91d3eaa 159 */
Kojto 93:e188a91d3eaa 160
Kojto 93:e188a91d3eaa 161 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 93:e188a91d3eaa 162 * @{
Kojto 93:e188a91d3eaa 163 */
Kojto 122:f9eeca106725 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 122:f9eeca106725 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 122:f9eeca106725 166 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
Kojto 122:f9eeca106725 167 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
Kojto 93:e188a91d3eaa 168 /**
Kojto 93:e188a91d3eaa 169 * @}
Kojto 93:e188a91d3eaa 170 */
Kojto 93:e188a91d3eaa 171
Kojto 93:e188a91d3eaa 172 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 93:e188a91d3eaa 173 * @{
Kojto 93:e188a91d3eaa 174 */
Kojto 93:e188a91d3eaa 175 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
Kojto 93:e188a91d3eaa 176 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
Kojto 93:e188a91d3eaa 177 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
Kojto 93:e188a91d3eaa 178
Kojto 93:e188a91d3eaa 179 /**
Kojto 93:e188a91d3eaa 180 * @}
Kojto 93:e188a91d3eaa 181 */
Kojto 108:34e6b704fe68 182
Kojto 93:e188a91d3eaa 183 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 93:e188a91d3eaa 184 * @{
Kojto 93:e188a91d3eaa 185 */
Kojto 93:e188a91d3eaa 186 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
Kojto 93:e188a91d3eaa 187 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
Kojto 93:e188a91d3eaa 188 /**
Kojto 93:e188a91d3eaa 189 * @}
Kojto 93:e188a91d3eaa 190 */
Kojto 93:e188a91d3eaa 191
Kojto 93:e188a91d3eaa 192 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 93:e188a91d3eaa 193 * @{
Kojto 93:e188a91d3eaa 194 */
Kojto 93:e188a91d3eaa 195 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
Kojto 93:e188a91d3eaa 196 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
Kojto 93:e188a91d3eaa 197 /**
Kojto 93:e188a91d3eaa 198 * @}
Kojto 93:e188a91d3eaa 199 */
Kojto 93:e188a91d3eaa 200
Kojto 93:e188a91d3eaa 201 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 93:e188a91d3eaa 202 * @{
Kojto 93:e188a91d3eaa 203 */
Kojto 93:e188a91d3eaa 204 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
Kojto 93:e188a91d3eaa 205 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
Kojto 93:e188a91d3eaa 206 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
Kojto 93:e188a91d3eaa 207 /**
Kojto 93:e188a91d3eaa 208 * @}
Kojto 93:e188a91d3eaa 209 */
Kojto 93:e188a91d3eaa 210
Kojto 93:e188a91d3eaa 211 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 93:e188a91d3eaa 212 * @{
Kojto 93:e188a91d3eaa 213 */
Kojto 93:e188a91d3eaa 214 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
Kojto 93:e188a91d3eaa 215 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
Kojto 93:e188a91d3eaa 216 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
Kojto 93:e188a91d3eaa 217 /**
Kojto 93:e188a91d3eaa 218 * @}
Kojto 93:e188a91d3eaa 219 */
Kojto 93:e188a91d3eaa 220
Kojto 93:e188a91d3eaa 221 /** @defgroup DMA_mode DMA mode
Kojto 93:e188a91d3eaa 222 * @{
Kojto 93:e188a91d3eaa 223 */
Kojto 93:e188a91d3eaa 224 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
Kojto 93:e188a91d3eaa 225 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
Kojto 93:e188a91d3eaa 226 /**
Kojto 93:e188a91d3eaa 227 * @}
Kojto 93:e188a91d3eaa 228 */
Kojto 93:e188a91d3eaa 229
Kojto 93:e188a91d3eaa 230 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 93:e188a91d3eaa 231 * @{
Kojto 93:e188a91d3eaa 232 */
Kojto 93:e188a91d3eaa 233 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
Kojto 93:e188a91d3eaa 234 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
Kojto 93:e188a91d3eaa 235 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
Kojto 93:e188a91d3eaa 236 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
Kojto 93:e188a91d3eaa 237 /**
Kojto 93:e188a91d3eaa 238 * @}
Kojto 93:e188a91d3eaa 239 */
Kojto 93:e188a91d3eaa 240
Kojto 93:e188a91d3eaa 241
Kojto 93:e188a91d3eaa 242 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 93:e188a91d3eaa 243 * @{
Kojto 93:e188a91d3eaa 244 */
Kojto 93:e188a91d3eaa 245 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
Kojto 93:e188a91d3eaa 246 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
Kojto 93:e188a91d3eaa 247 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
Kojto 93:e188a91d3eaa 248 /**
Kojto 93:e188a91d3eaa 249 * @}
Kojto 93:e188a91d3eaa 250 */
Kojto 93:e188a91d3eaa 251
Kojto 93:e188a91d3eaa 252 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 93:e188a91d3eaa 253 * @{
Kojto 93:e188a91d3eaa 254 */
Kojto 93:e188a91d3eaa 255
Kojto 93:e188a91d3eaa 256 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
Kojto 93:e188a91d3eaa 257 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
Kojto 93:e188a91d3eaa 258 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
Kojto 93:e188a91d3eaa 259 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
Kojto 93:e188a91d3eaa 260 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
Kojto 93:e188a91d3eaa 261 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
Kojto 93:e188a91d3eaa 262 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
Kojto 93:e188a91d3eaa 263 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
Kojto 93:e188a91d3eaa 264 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
Kojto 93:e188a91d3eaa 265 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
Kojto 93:e188a91d3eaa 266 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
Kojto 93:e188a91d3eaa 267 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
Kojto 93:e188a91d3eaa 268 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
Kojto 93:e188a91d3eaa 269 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
Kojto 93:e188a91d3eaa 270 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
Kojto 93:e188a91d3eaa 271 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
Kojto 93:e188a91d3eaa 272 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
Kojto 93:e188a91d3eaa 273 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
Kojto 93:e188a91d3eaa 274 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
Kojto 93:e188a91d3eaa 275 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
Kojto 93:e188a91d3eaa 276 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
Kojto 93:e188a91d3eaa 277 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
Kojto 93:e188a91d3eaa 278 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
Kojto 93:e188a91d3eaa 279 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
Kojto 93:e188a91d3eaa 280 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
Kojto 93:e188a91d3eaa 281 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
Kojto 93:e188a91d3eaa 282 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
Kojto 93:e188a91d3eaa 283 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
Kojto 93:e188a91d3eaa 284
Kojto 108:34e6b704fe68 285 /**
Kojto 108:34e6b704fe68 286 * @}
Kojto 108:34e6b704fe68 287 */
Kojto 108:34e6b704fe68 288
Kojto 108:34e6b704fe68 289 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 108:34e6b704fe68 290 /** @defgroup HAL_DMA_remapping HAL DMA remapping
Kojto 108:34e6b704fe68 291 * Elements values convention: 0xYYYYYYYY
Kojto 108:34e6b704fe68 292 * - YYYYYYYY : Position in the SYSCFG register CFGR1
Kojto 108:34e6b704fe68 293 * @{
Kojto 108:34e6b704fe68 294 */
Kojto 108:34e6b704fe68 295 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
Kojto 108:34e6b704fe68 296 0: No remap (ADC DMA requests mapped on DMA channel 1
Kojto 108:34e6b704fe68 297 1: Remap (ADC DMA requests mapped on DMA channel 2 */
Kojto 108:34e6b704fe68 298 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
Kojto 108:34e6b704fe68 299 0: No remap (USART1_TX DMA request mapped on DMA channel 2
Kojto 108:34e6b704fe68 300 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
Kojto 108:34e6b704fe68 301 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
Kojto 108:34e6b704fe68 302 0: No remap (USART1_RX DMA request mapped on DMA channel 3
Kojto 108:34e6b704fe68 303 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
Kojto 108:34e6b704fe68 304 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
Kojto 108:34e6b704fe68 305 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
Kojto 108:34e6b704fe68 306 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
Kojto 108:34e6b704fe68 307 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
Kojto 108:34e6b704fe68 308 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
Kojto 108:34e6b704fe68 309 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
Kojto 108:34e6b704fe68 310 #if defined (STM32F070xB)
Kojto 108:34e6b704fe68 311 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
Kojto 108:34e6b704fe68 312 0: Disabled, need to remap before use
Kojto 108:34e6b704fe68 313 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto 108:34e6b704fe68 314
Kojto 108:34e6b704fe68 315 #endif
Kojto 108:34e6b704fe68 316
Kojto 108:34e6b704fe68 317 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
Kojto 108:34e6b704fe68 318 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto 108:34e6b704fe68 319 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
Kojto 108:34e6b704fe68 320 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
Kojto 108:34e6b704fe68 321 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto 108:34e6b704fe68 322 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
Kojto 108:34e6b704fe68 323 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
Kojto 108:34e6b704fe68 324 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 325 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
Kojto 108:34e6b704fe68 326 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto 108:34e6b704fe68 327 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 328 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
Kojto 108:34e6b704fe68 329 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto 108:34e6b704fe68 330 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 331 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
Kojto 108:34e6b704fe68 332 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto 108:34e6b704fe68 333 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 334 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
Kojto 108:34e6b704fe68 335 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
Kojto 108:34e6b704fe68 336 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 337 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
Kojto 108:34e6b704fe68 338 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
Kojto 108:34e6b704fe68 339 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 340 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
Kojto 108:34e6b704fe68 341 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
Kojto 108:34e6b704fe68 342 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 108:34e6b704fe68 343 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
Kojto 108:34e6b704fe68 344 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
Kojto 108:34e6b704fe68 345 #endif
Kojto 93:e188a91d3eaa 346
Kojto 93:e188a91d3eaa 347 /**
Kojto 93:e188a91d3eaa 348 * @}
Kojto 93:e188a91d3eaa 349 */
Kojto 93:e188a91d3eaa 350
Kojto 108:34e6b704fe68 351 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 93:e188a91d3eaa 352 /**
Kojto 93:e188a91d3eaa 353 * @}
Kojto 93:e188a91d3eaa 354 */
Kojto 93:e188a91d3eaa 355
Kojto 108:34e6b704fe68 356 /* Exported macro ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 357 /** @defgroup DMA_Exported_Macros DMA Exported Macros
Kojto 93:e188a91d3eaa 358 * @{
Kojto 93:e188a91d3eaa 359 */
Kojto 93:e188a91d3eaa 360
Kojto 93:e188a91d3eaa 361 /** @brief Reset DMA handle state
Kojto 93:e188a91d3eaa 362 * @param __HANDLE__: DMA handle.
Kojto 93:e188a91d3eaa 363 * @retval None
Kojto 93:e188a91d3eaa 364 */
Kojto 93:e188a91d3eaa 365 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 93:e188a91d3eaa 366
Kojto 93:e188a91d3eaa 367 /**
Kojto 93:e188a91d3eaa 368 * @brief Enable the specified DMA Channel.
Kojto 93:e188a91d3eaa 369 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 370 * @retval None
Kojto 93:e188a91d3eaa 371 */
Kojto 93:e188a91d3eaa 372 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 93:e188a91d3eaa 373
Kojto 93:e188a91d3eaa 374 /**
Kojto 93:e188a91d3eaa 375 * @brief Disable the specified DMA Channel.
Kojto 93:e188a91d3eaa 376 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 377 * @retval None
Kojto 93:e188a91d3eaa 378 */
Kojto 93:e188a91d3eaa 379 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 93:e188a91d3eaa 380
Kojto 93:e188a91d3eaa 381
Kojto 93:e188a91d3eaa 382 /* Interrupt & Flag management */
Kojto 93:e188a91d3eaa 383
Kojto 93:e188a91d3eaa 384 /**
Kojto 93:e188a91d3eaa 385 * @brief Enables the specified DMA Channel interrupts.
Kojto 93:e188a91d3eaa 386 * @param __HANDLE__: DMA handle
Kojto 93:e188a91d3eaa 387 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 93:e188a91d3eaa 388 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 389 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 93:e188a91d3eaa 390 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 93:e188a91d3eaa 391 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 93:e188a91d3eaa 392 * @retval None
Kojto 93:e188a91d3eaa 393 */
Kojto 93:e188a91d3eaa 394 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
Kojto 93:e188a91d3eaa 395
Kojto 93:e188a91d3eaa 396 /**
Kojto 93:e188a91d3eaa 397 * @brief Disables the specified DMA Channel interrupts.
Kojto 93:e188a91d3eaa 398 * @param __HANDLE__: DMA handle
Kojto 93:e188a91d3eaa 399 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 93:e188a91d3eaa 400 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 401 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 93:e188a91d3eaa 402 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 93:e188a91d3eaa 403 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 93:e188a91d3eaa 404 * @retval None
Kojto 93:e188a91d3eaa 405 */
Kojto 93:e188a91d3eaa 406 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
Kojto 93:e188a91d3eaa 407
Kojto 93:e188a91d3eaa 408 /**
Kojto 108:34e6b704fe68 409 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
Kojto 93:e188a91d3eaa 410 * @param __HANDLE__: DMA handle
Kojto 93:e188a91d3eaa 411 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 93:e188a91d3eaa 412 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 413 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 93:e188a91d3eaa 414 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 93:e188a91d3eaa 415 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 93:e188a91d3eaa 416 * @retval The state of DMA_IT (SET or RESET).
Kojto 93:e188a91d3eaa 417 */
Kojto 93:e188a91d3eaa 418 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto 93:e188a91d3eaa 419
Kojto 122:f9eeca106725 420 /**
Kojto 122:f9eeca106725 421 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
Kojto 122:f9eeca106725 422 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 423 *
Kojto 122:f9eeca106725 424 * @retval The number of remaining data units in the current DMA Channel transfer.
Kojto 122:f9eeca106725 425 */
Kojto 122:f9eeca106725 426 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Kojto 122:f9eeca106725 427
Kojto 108:34e6b704fe68 428 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 108:34e6b704fe68 429 /** @brief DMA remapping enable/disable macros
Kojto 108:34e6b704fe68 430 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
Kojto 108:34e6b704fe68 431 */
Kojto 108:34e6b704fe68 432 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto 108:34e6b704fe68 433 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
Kojto 108:34e6b704fe68 434 }while(0)
Kojto 108:34e6b704fe68 435 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto 108:34e6b704fe68 436 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
Kojto 108:34e6b704fe68 437 }while(0)
Kojto 108:34e6b704fe68 438 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 108:34e6b704fe68 439
Kojto 93:e188a91d3eaa 440 /**
Kojto 93:e188a91d3eaa 441 * @}
Kojto 93:e188a91d3eaa 442 */
Kojto 93:e188a91d3eaa 443
Kojto 93:e188a91d3eaa 444 /* Include DMA HAL Extension module */
Kojto 93:e188a91d3eaa 445 #include "stm32f0xx_hal_dma_ex.h"
Kojto 93:e188a91d3eaa 446
Kojto 93:e188a91d3eaa 447 /* Exported functions --------------------------------------------------------*/
Kojto 108:34e6b704fe68 448 /** @addtogroup DMA_Exported_Functions
Kojto 93:e188a91d3eaa 449 * @{
Kojto 93:e188a91d3eaa 450 */
Kojto 108:34e6b704fe68 451
Kojto 93:e188a91d3eaa 452 /** @addtogroup DMA_Exported_Functions_Group1
Kojto 93:e188a91d3eaa 453 * @{
Kojto 93:e188a91d3eaa 454 */
Kojto 93:e188a91d3eaa 455 /* Initialization and de-initialization functions *****************************/
Kojto 93:e188a91d3eaa 456 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 457 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 458 /**
Kojto 93:e188a91d3eaa 459 * @}
Kojto 93:e188a91d3eaa 460 */
Kojto 93:e188a91d3eaa 461
Kojto 93:e188a91d3eaa 462 /** @addtogroup DMA_Exported_Functions_Group2
Kojto 93:e188a91d3eaa 463 * @{
Kojto 93:e188a91d3eaa 464 */
Kojto 108:34e6b704fe68 465 /* Input and Output operation functions *****************************************************/
Kojto 93:e188a91d3eaa 466 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 93:e188a91d3eaa 467 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 93:e188a91d3eaa 468 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 469 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 470 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
Kojto 93:e188a91d3eaa 471 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 472 /**
Kojto 93:e188a91d3eaa 473 * @}
Kojto 93:e188a91d3eaa 474 */
Kojto 93:e188a91d3eaa 475
Kojto 93:e188a91d3eaa 476 /** @addtogroup DMA_Exported_Functions_Group3
Kojto 93:e188a91d3eaa 477 * @{
Kojto 93:e188a91d3eaa 478 */
Kojto 108:34e6b704fe68 479 /* Peripheral State and Error functions ***************************************/
Kojto 93:e188a91d3eaa 480 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 481 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 93:e188a91d3eaa 482 /**
Kojto 93:e188a91d3eaa 483 * @}
Kojto 108:34e6b704fe68 484 */
Kojto 108:34e6b704fe68 485
Kojto 108:34e6b704fe68 486 /**
Kojto 108:34e6b704fe68 487 * @}
Kojto 108:34e6b704fe68 488 */
Kojto 108:34e6b704fe68 489
Kojto 108:34e6b704fe68 490 /** @addtogroup DMA_Private_Macros
Kojto 108:34e6b704fe68 491 * @{
Kojto 93:e188a91d3eaa 492 */
Kojto 108:34e6b704fe68 493 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 108:34e6b704fe68 494 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 108:34e6b704fe68 495 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 108:34e6b704fe68 496 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 108:34e6b704fe68 497 ((STATE) == DMA_PINC_DISABLE))
Kojto 108:34e6b704fe68 498
Kojto 108:34e6b704fe68 499 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 108:34e6b704fe68 500 ((STATE) == DMA_MINC_DISABLE))
Kojto 108:34e6b704fe68 501
Kojto 108:34e6b704fe68 502 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 108:34e6b704fe68 503 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 108:34e6b704fe68 504 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 108:34e6b704fe68 505
Kojto 108:34e6b704fe68 506 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 108:34e6b704fe68 507 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 108:34e6b704fe68 508 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 108:34e6b704fe68 509
Kojto 108:34e6b704fe68 510 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 108:34e6b704fe68 511 ((MODE) == DMA_CIRCULAR))
Kojto 108:34e6b704fe68 512 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 108:34e6b704fe68 513 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 108:34e6b704fe68 514 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 108:34e6b704fe68 515 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 108:34e6b704fe68 516 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 108:34e6b704fe68 517
Kojto 108:34e6b704fe68 518 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 108:34e6b704fe68 519
Kojto 108:34e6b704fe68 520 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
Kojto 108:34e6b704fe68 521 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 108:34e6b704fe68 522 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 108:34e6b704fe68 523 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 108:34e6b704fe68 524 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 108:34e6b704fe68 525 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
Kojto 108:34e6b704fe68 526 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
Kojto 108:34e6b704fe68 527 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
Kojto 108:34e6b704fe68 528 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
Kojto 108:34e6b704fe68 529 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
Kojto 108:34e6b704fe68 530 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
Kojto 108:34e6b704fe68 531 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
Kojto 108:34e6b704fe68 532 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
Kojto 108:34e6b704fe68 533 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
Kojto 108:34e6b704fe68 534 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
Kojto 108:34e6b704fe68 535 #elif defined (STM32F070xB)
Kojto 108:34e6b704fe68 536 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
Kojto 108:34e6b704fe68 537 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 108:34e6b704fe68 538 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 108:34e6b704fe68 539 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 108:34e6b704fe68 540 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 108:34e6b704fe68 541 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto 108:34e6b704fe68 542 #else
Kojto 108:34e6b704fe68 543 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 108:34e6b704fe68 544 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 108:34e6b704fe68 545 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 108:34e6b704fe68 546 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 108:34e6b704fe68 547 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto 108:34e6b704fe68 548 #endif
Kojto 108:34e6b704fe68 549
Kojto 108:34e6b704fe68 550 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 108:34e6b704fe68 551
Kojto 108:34e6b704fe68 552
Kojto 108:34e6b704fe68 553 /**
Kojto 108:34e6b704fe68 554 * @}
Kojto 108:34e6b704fe68 555 */
Kojto 93:e188a91d3eaa 556
Kojto 93:e188a91d3eaa 557 /**
Kojto 93:e188a91d3eaa 558 * @}
Kojto 93:e188a91d3eaa 559 */
Kojto 93:e188a91d3eaa 560
Kojto 93:e188a91d3eaa 561 /**
Kojto 93:e188a91d3eaa 562 * @}
Kojto 93:e188a91d3eaa 563 */
Kojto 93:e188a91d3eaa 564
Kojto 93:e188a91d3eaa 565 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 566 }
Kojto 93:e188a91d3eaa 567 #endif
Kojto 93:e188a91d3eaa 568
Kojto 93:e188a91d3eaa 569 #endif /* __STM32F0xx_HAL_DMA_H */
Kojto 93:e188a91d3eaa 570
Kojto 93:e188a91d3eaa 571 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 93:e188a91d3eaa 572