mbed official / mbed

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
108:34e6b704fe68
Release 122 of the mbed library

Changes:
- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4
- Thread safety addition - mbed API should contain a statement about thread safety
- critical section API addition
- CAS API (core_util_atomic_incr/decr)
- DEVICE_ are generated from targets.json file, device.h deprecated
- Callback replaces FunctionPointer to provide std like interface
- mbed HAL API docs improvements
- toolchain - prexif attributes with MBED_
- add new attributes - packed, weak, forcedinline, align
- target.json - contains targets definitions
- ST - L1XX - Cube update to 1.5
- SPI clock selection fix (clock from APB domain)
- F7 - Cube update v1.4.0
- L0 - baudrate init fix
- L1 - Cube update v1.5
- F3 - baudrate init fix, 3 targets CAN support
- F4 - Cube update v1.12.0, 3 targets CAN support
- L4XX - Cube update v1.5.1
- F0 - update Cube to v1.5.0
- L4 - 2 targets (L476RG/VG) CAN support
- NXP - pwm clock fix for KSDK2 MCU
- LPC2368 - remove ARM toolchain support - due to regression
- KSDK2 - fix SPI , I2C address and repeat start
- Silabs - some fixes backported from mbed 3
- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**
Kojto 108:34e6b704fe68 2 ******************************************************************************
Kojto 108:34e6b704fe68 3 * @file stm32_hal_legacy.h
Kojto 108:34e6b704fe68 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.4.0
Kojto 122:f9eeca106725 6 * @date 27-May-2016
Kojto 108:34e6b704fe68 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto 108:34e6b704fe68 8 * macros and functions maintained for legacy purpose.
Kojto 108:34e6b704fe68 9 ******************************************************************************
Kojto 108:34e6b704fe68 10 * @attention
Kojto 108:34e6b704fe68 11 *
Kojto 122:f9eeca106725 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 108:34e6b704fe68 13 *
Kojto 108:34e6b704fe68 14 * Redistribution and use in source and binary forms, with or without modification,
Kojto 108:34e6b704fe68 15 * are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 16 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 108:34e6b704fe68 17 * this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 108:34e6b704fe68 19 * this list of conditions and the following disclaimer in the documentation
Kojto 108:34e6b704fe68 20 * and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 108:34e6b704fe68 22 * may be used to endorse or promote products derived from this software
Kojto 108:34e6b704fe68 23 * without specific prior written permission.
Kojto 108:34e6b704fe68 24 *
Kojto 108:34e6b704fe68 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 108:34e6b704fe68 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 108:34e6b704fe68 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 108:34e6b704fe68 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 108:34e6b704fe68 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 108:34e6b704fe68 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 108:34e6b704fe68 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 108:34e6b704fe68 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 35 *
Kojto 108:34e6b704fe68 36 ******************************************************************************
Kojto 108:34e6b704fe68 37 */
Kojto 108:34e6b704fe68 38
Kojto 108:34e6b704fe68 39 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 108:34e6b704fe68 40 #ifndef __STM32_HAL_LEGACY
Kojto 108:34e6b704fe68 41 #define __STM32_HAL_LEGACY
Kojto 108:34e6b704fe68 42
Kojto 108:34e6b704fe68 43 #ifdef __cplusplus
Kojto 108:34e6b704fe68 44 extern "C" {
Kojto 108:34e6b704fe68 45 #endif
Kojto 108:34e6b704fe68 46
Kojto 108:34e6b704fe68 47 /* Includes ------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 48 /* Exported types ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 49 /* Exported constants --------------------------------------------------------*/
Kojto 108:34e6b704fe68 50
Kojto 108:34e6b704fe68 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 52 * @{
Kojto 108:34e6b704fe68 53 */
Kojto 108:34e6b704fe68 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto 108:34e6b704fe68 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto 108:34e6b704fe68 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto 108:34e6b704fe68 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto 108:34e6b704fe68 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto 108:34e6b704fe68 59
Kojto 108:34e6b704fe68 60 /**
Kojto 108:34e6b704fe68 61 * @}
Kojto 108:34e6b704fe68 62 */
Kojto 108:34e6b704fe68 63
Kojto 108:34e6b704fe68 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 65 * @{
Kojto 108:34e6b704fe68 66 */
Kojto 108:34e6b704fe68 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto 108:34e6b704fe68 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto 108:34e6b704fe68 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto 108:34e6b704fe68 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto 108:34e6b704fe68 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto 108:34e6b704fe68 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto 108:34e6b704fe68 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto 108:34e6b704fe68 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto 108:34e6b704fe68 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto 108:34e6b704fe68 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto 108:34e6b704fe68 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto 108:34e6b704fe68 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto 108:34e6b704fe68 79 #define AWD_EVENT ADC_AWD_EVENT
Kojto 108:34e6b704fe68 80 #define AWD1_EVENT ADC_AWD1_EVENT
Kojto 108:34e6b704fe68 81 #define AWD2_EVENT ADC_AWD2_EVENT
Kojto 108:34e6b704fe68 82 #define AWD3_EVENT ADC_AWD3_EVENT
Kojto 108:34e6b704fe68 83 #define OVR_EVENT ADC_OVR_EVENT
Kojto 108:34e6b704fe68 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto 108:34e6b704fe68 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto 108:34e6b704fe68 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto 108:34e6b704fe68 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto 108:34e6b704fe68 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto 108:34e6b704fe68 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto 108:34e6b704fe68 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto 108:34e6b704fe68 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto 108:34e6b704fe68 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto 108:34e6b704fe68 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
Kojto 108:34e6b704fe68 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
Kojto 108:34e6b704fe68 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto 108:34e6b704fe68 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto 108:34e6b704fe68 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto 108:34e6b704fe68 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto 108:34e6b704fe68 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto 108:34e6b704fe68 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto 108:34e6b704fe68 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto 108:34e6b704fe68 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto 108:34e6b704fe68 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto 108:34e6b704fe68 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto 122:f9eeca106725 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto 122:f9eeca106725 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
Kojto 122:f9eeca106725 107
Kojto 122:f9eeca106725 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
Kojto 122:f9eeca106725 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
Kojto 122:f9eeca106725 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
Kojto 122:f9eeca106725 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
Kojto 122:f9eeca106725 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
Kojto 122:f9eeca106725 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
Kojto 122:f9eeca106725 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
Kojto 108:34e6b704fe68 115 /**
Kojto 108:34e6b704fe68 116 * @}
Kojto 108:34e6b704fe68 117 */
Kojto 108:34e6b704fe68 118
Kojto 108:34e6b704fe68 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 120 * @{
Kojto 108:34e6b704fe68 121 */
Kojto 108:34e6b704fe68 122
Kojto 108:34e6b704fe68 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto 108:34e6b704fe68 124
Kojto 108:34e6b704fe68 125 /**
Kojto 108:34e6b704fe68 126 * @}
Kojto 108:34e6b704fe68 127 */
Kojto 108:34e6b704fe68 128
Kojto 108:34e6b704fe68 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 130 * @{
Kojto 108:34e6b704fe68 131 */
Kojto 122:f9eeca106725 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto 122:f9eeca106725 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto 122:f9eeca106725 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto 122:f9eeca106725 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto 122:f9eeca106725 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
Kojto 122:f9eeca106725 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
Kojto 122:f9eeca106725 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
Kojto 122:f9eeca106725 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
Kojto 122:f9eeca106725 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
Kojto 122:f9eeca106725 141 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
Kojto 122:f9eeca106725 142 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 143 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
Kojto 122:f9eeca106725 144 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
Kojto 122:f9eeca106725 145 #endif /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 146
Kojto 122:f9eeca106725 147 #if defined(STM32L0) || defined(STM32L4)
Kojto 122:f9eeca106725 148 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Kojto 108:34e6b704fe68 149
Kojto 122:f9eeca106725 150 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
Kojto 122:f9eeca106725 151 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
Kojto 122:f9eeca106725 152 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
Kojto 122:f9eeca106725 153 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
Kojto 122:f9eeca106725 154 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
Kojto 122:f9eeca106725 155 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
Kojto 122:f9eeca106725 156
Kojto 122:f9eeca106725 157 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
Kojto 122:f9eeca106725 158 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
Kojto 122:f9eeca106725 159 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
Kojto 122:f9eeca106725 160 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
Kojto 122:f9eeca106725 161 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
Kojto 122:f9eeca106725 162 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
Kojto 122:f9eeca106725 163 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
Kojto 122:f9eeca106725 164 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
Kojto 122:f9eeca106725 165 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
Kojto 122:f9eeca106725 166 #if defined(STM32L0)
Kojto 122:f9eeca106725 167 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
Kojto 122:f9eeca106725 168 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
Kojto 122:f9eeca106725 169 /* to the second dedicated IO (only for COMP2). */
Kojto 122:f9eeca106725 170 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
Kojto 122:f9eeca106725 171 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
Kojto 122:f9eeca106725 172 #else
Kojto 122:f9eeca106725 173 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
Kojto 122:f9eeca106725 174 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
Kojto 122:f9eeca106725 175 #endif
Kojto 122:f9eeca106725 176 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
Kojto 122:f9eeca106725 177 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
Kojto 122:f9eeca106725 178
Kojto 122:f9eeca106725 179 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
Kojto 122:f9eeca106725 180 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
Kojto 122:f9eeca106725 181
Kojto 122:f9eeca106725 182 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
Kojto 122:f9eeca106725 183 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
Kojto 122:f9eeca106725 184 #if defined(COMP_CSR_LOCK)
Kojto 122:f9eeca106725 185 #define COMP_FLAG_LOCK COMP_CSR_LOCK
Kojto 122:f9eeca106725 186 #elif defined(COMP_CSR_COMP1LOCK)
Kojto 122:f9eeca106725 187 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
Kojto 122:f9eeca106725 188 #elif defined(COMP_CSR_COMPxLOCK)
Kojto 122:f9eeca106725 189 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
Kojto 122:f9eeca106725 190 #endif
Kojto 122:f9eeca106725 191
Kojto 122:f9eeca106725 192 #if defined(STM32L4)
Kojto 122:f9eeca106725 193 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
Kojto 122:f9eeca106725 194 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
Kojto 122:f9eeca106725 195 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
Kojto 122:f9eeca106725 196 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
Kojto 122:f9eeca106725 197 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
Kojto 122:f9eeca106725 198 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
Kojto 122:f9eeca106725 199 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
Kojto 122:f9eeca106725 200 #endif
Kojto 122:f9eeca106725 201
Kojto 122:f9eeca106725 202 #if defined(STM32L0)
Kojto 122:f9eeca106725 203 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto 122:f9eeca106725 204 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
Kojto 122:f9eeca106725 205 #else
Kojto 122:f9eeca106725 206 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
Kojto 122:f9eeca106725 207 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto 122:f9eeca106725 208 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
Kojto 122:f9eeca106725 209 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
Kojto 122:f9eeca106725 210 #endif
Kojto 122:f9eeca106725 211
Kojto 122:f9eeca106725 212 #endif
Kojto 122:f9eeca106725 213 /**
Kojto 122:f9eeca106725 214 * @}
Kojto 122:f9eeca106725 215 */
Kojto 122:f9eeca106725 216
Kojto 122:f9eeca106725 217 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
Kojto 122:f9eeca106725 218 * @{
Kojto 122:f9eeca106725 219 */
Kojto 122:f9eeca106725 220 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
Kojto 108:34e6b704fe68 221 /**
Kojto 108:34e6b704fe68 222 * @}
Kojto 108:34e6b704fe68 223 */
Kojto 108:34e6b704fe68 224
Kojto 108:34e6b704fe68 225 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 226 * @{
Kojto 108:34e6b704fe68 227 */
Kojto 108:34e6b704fe68 228
Kojto 108:34e6b704fe68 229 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto 108:34e6b704fe68 230 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto 108:34e6b704fe68 231
Kojto 108:34e6b704fe68 232 /**
Kojto 108:34e6b704fe68 233 * @}
Kojto 108:34e6b704fe68 234 */
Kojto 108:34e6b704fe68 235
Kojto 108:34e6b704fe68 236 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 237 * @{
Kojto 108:34e6b704fe68 238 */
Kojto 108:34e6b704fe68 239
Kojto 108:34e6b704fe68 240 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto 108:34e6b704fe68 241 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto 108:34e6b704fe68 242 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto 122:f9eeca106725 243 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
Kojto 108:34e6b704fe68 244 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto 108:34e6b704fe68 245 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto 108:34e6b704fe68 246 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto 108:34e6b704fe68 247 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto 108:34e6b704fe68 248 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto 108:34e6b704fe68 249
Kojto 108:34e6b704fe68 250 /**
Kojto 108:34e6b704fe68 251 * @}
Kojto 108:34e6b704fe68 252 */
Kojto 108:34e6b704fe68 253
Kojto 108:34e6b704fe68 254 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 255 * @{
Kojto 108:34e6b704fe68 256 */
Kojto 108:34e6b704fe68 257 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto 108:34e6b704fe68 258 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto 108:34e6b704fe68 259 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto 108:34e6b704fe68 260 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto 108:34e6b704fe68 261 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto 108:34e6b704fe68 262 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 108:34e6b704fe68 263 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto 108:34e6b704fe68 264 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto 108:34e6b704fe68 265 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto 108:34e6b704fe68 266 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto 108:34e6b704fe68 267 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 108:34e6b704fe68 268 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto 108:34e6b704fe68 269 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto 108:34e6b704fe68 270 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto 108:34e6b704fe68 271 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto 108:34e6b704fe68 272
Kojto 108:34e6b704fe68 273 #define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto 108:34e6b704fe68 274 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto 108:34e6b704fe68 275 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto 108:34e6b704fe68 276
Kojto 108:34e6b704fe68 277
Kojto 108:34e6b704fe68 278
Kojto 108:34e6b704fe68 279 /**
Kojto 108:34e6b704fe68 280 * @}
Kojto 108:34e6b704fe68 281 */
Kojto 108:34e6b704fe68 282
Kojto 108:34e6b704fe68 283 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 284 * @{
Kojto 108:34e6b704fe68 285 */
Kojto 108:34e6b704fe68 286
Kojto 108:34e6b704fe68 287 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto 108:34e6b704fe68 288 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 108:34e6b704fe68 289 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto 108:34e6b704fe68 290 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto 108:34e6b704fe68 291 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto 108:34e6b704fe68 292 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto 108:34e6b704fe68 293 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto 108:34e6b704fe68 294 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto 108:34e6b704fe68 295 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto 108:34e6b704fe68 296 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto 108:34e6b704fe68 297 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto 108:34e6b704fe68 298 #define OBEX_PCROP OPTIONBYTE_PCROP
Kojto 108:34e6b704fe68 299 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto 108:34e6b704fe68 300 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto 108:34e6b704fe68 301 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto 108:34e6b704fe68 302 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto 108:34e6b704fe68 303 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto 108:34e6b704fe68 304 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto 108:34e6b704fe68 305 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto 108:34e6b704fe68 306 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto 108:34e6b704fe68 307 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto 108:34e6b704fe68 308 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto 108:34e6b704fe68 309 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto 108:34e6b704fe68 310 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto 108:34e6b704fe68 311 #define PAGESIZE FLASH_PAGE_SIZE
Kojto 108:34e6b704fe68 312 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto 108:34e6b704fe68 313 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 108:34e6b704fe68 314 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto 108:34e6b704fe68 315 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto 108:34e6b704fe68 316 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto 108:34e6b704fe68 317 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto 108:34e6b704fe68 318 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto 108:34e6b704fe68 319 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto 108:34e6b704fe68 320 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto 108:34e6b704fe68 321 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto 108:34e6b704fe68 322 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto 108:34e6b704fe68 323 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto 108:34e6b704fe68 324 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto 108:34e6b704fe68 325 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto 108:34e6b704fe68 326 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto 108:34e6b704fe68 327 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto 108:34e6b704fe68 328 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto 108:34e6b704fe68 329 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto 108:34e6b704fe68 330 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto 108:34e6b704fe68 331 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto 108:34e6b704fe68 332 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto 108:34e6b704fe68 333 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto 108:34e6b704fe68 334 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto 108:34e6b704fe68 335 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto 108:34e6b704fe68 336 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto 108:34e6b704fe68 337 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto 108:34e6b704fe68 338 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto 108:34e6b704fe68 339 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto 108:34e6b704fe68 340 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto 108:34e6b704fe68 341 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto 108:34e6b704fe68 342 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto 108:34e6b704fe68 343 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto 108:34e6b704fe68 344 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto 108:34e6b704fe68 345 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto 108:34e6b704fe68 346 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto 108:34e6b704fe68 347 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto 108:34e6b704fe68 348 #define OB_WDG_SW OB_IWDG_SW
Kojto 108:34e6b704fe68 349 #define OB_WDG_HW OB_IWDG_HW
Kojto 122:f9eeca106725 350 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
Kojto 122:f9eeca106725 351 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
Kojto 122:f9eeca106725 352 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
Kojto 122:f9eeca106725 353 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
Kojto 122:f9eeca106725 354 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
Kojto 122:f9eeca106725 355 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
Kojto 122:f9eeca106725 356 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
Kojto 122:f9eeca106725 357 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
Kojto 108:34e6b704fe68 358 /**
Kojto 108:34e6b704fe68 359 * @}
Kojto 108:34e6b704fe68 360 */
Kojto 108:34e6b704fe68 361
Kojto 108:34e6b704fe68 362 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 363 * @{
Kojto 108:34e6b704fe68 364 */
Kojto 108:34e6b704fe68 365
Kojto 122:f9eeca106725 366 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
Kojto 122:f9eeca106725 367 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
Kojto 122:f9eeca106725 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto 122:f9eeca106725 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto 122:f9eeca106725 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto 122:f9eeca106725 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto 122:f9eeca106725 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto 122:f9eeca106725 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto 122:f9eeca106725 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto 108:34e6b704fe68 375 /**
Kojto 108:34e6b704fe68 376 * @}
Kojto 108:34e6b704fe68 377 */
Kojto 108:34e6b704fe68 378
Kojto 108:34e6b704fe68 379
Kojto 108:34e6b704fe68 380 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto 108:34e6b704fe68 381 * @{
Kojto 108:34e6b704fe68 382 */
Kojto 108:34e6b704fe68 383 #if defined(STM32L4) || defined(STM32F7)
Kojto 108:34e6b704fe68 384 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto 108:34e6b704fe68 385 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto 108:34e6b704fe68 386 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto 108:34e6b704fe68 387 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto 108:34e6b704fe68 388 #else
Kojto 108:34e6b704fe68 389 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto 108:34e6b704fe68 390 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto 108:34e6b704fe68 391 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto 108:34e6b704fe68 392 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto 108:34e6b704fe68 393 #endif
Kojto 108:34e6b704fe68 394 /**
Kojto 108:34e6b704fe68 395 * @}
Kojto 108:34e6b704fe68 396 */
Kojto 108:34e6b704fe68 397
Kojto 108:34e6b704fe68 398 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 399 * @{
Kojto 108:34e6b704fe68 400 */
Kojto 108:34e6b704fe68 401
Kojto 108:34e6b704fe68 402 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto 108:34e6b704fe68 403 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 108:34e6b704fe68 404 /**
Kojto 108:34e6b704fe68 405 * @}
Kojto 108:34e6b704fe68 406 */
Kojto 108:34e6b704fe68 407
Kojto 108:34e6b704fe68 408 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 409 * @{
Kojto 108:34e6b704fe68 410 */
Kojto 108:34e6b704fe68 411 #define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto 108:34e6b704fe68 412 #define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto 108:34e6b704fe68 413
Kojto 108:34e6b704fe68 414 #if defined(STM32F4)
Kojto 108:34e6b704fe68 415 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto 108:34e6b704fe68 416 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto 108:34e6b704fe68 417 #endif
Kojto 108:34e6b704fe68 418
Kojto 108:34e6b704fe68 419 #if defined(STM32F7)
Kojto 108:34e6b704fe68 420 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 108:34e6b704fe68 421 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 108:34e6b704fe68 422 #endif
Kojto 108:34e6b704fe68 423
Kojto 108:34e6b704fe68 424 #if defined(STM32L4)
Kojto 108:34e6b704fe68 425 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 108:34e6b704fe68 426 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 108:34e6b704fe68 427 #endif
Kojto 108:34e6b704fe68 428
Kojto 108:34e6b704fe68 429 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto 108:34e6b704fe68 430 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto 108:34e6b704fe68 431 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto 108:34e6b704fe68 432
Kojto 122:f9eeca106725 433 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
Kojto 122:f9eeca106725 434 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 122:f9eeca106725 435 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 122:f9eeca106725 436 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
Kojto 122:f9eeca106725 437 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 122:f9eeca106725 438 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
Kojto 122:f9eeca106725 439
Kojto 122:f9eeca106725 440 #if defined(STM32L1)
Kojto 122:f9eeca106725 441 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
Kojto 122:f9eeca106725 442 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
Kojto 122:f9eeca106725 443 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
Kojto 122:f9eeca106725 444 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 122:f9eeca106725 445 #endif /* STM32L1 */
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
Kojto 122:f9eeca106725 448 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 122:f9eeca106725 449 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 122:f9eeca106725 450 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
Kojto 122:f9eeca106725 451 #endif /* STM32F0 || STM32F3 || STM32F1 */
Kojto 122:f9eeca106725 452
Kojto 122:f9eeca106725 453 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
Kojto 108:34e6b704fe68 454 /**
Kojto 108:34e6b704fe68 455 * @}
Kojto 108:34e6b704fe68 456 */
Kojto 108:34e6b704fe68 457
Kojto 108:34e6b704fe68 458 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 459 * @{
Kojto 108:34e6b704fe68 460 */
Kojto 108:34e6b704fe68 461 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto 108:34e6b704fe68 462 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto 108:34e6b704fe68 463 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto 108:34e6b704fe68 464 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto 108:34e6b704fe68 465 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto 108:34e6b704fe68 466 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto 108:34e6b704fe68 467 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto 108:34e6b704fe68 468 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto 108:34e6b704fe68 469 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto 122:f9eeca106725 470
Kojto 122:f9eeca106725 471 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
Kojto 122:f9eeca106725 472 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
Kojto 122:f9eeca106725 473 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
Kojto 122:f9eeca106725 474 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
Kojto 122:f9eeca106725 475 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
Kojto 122:f9eeca106725 476 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
Kojto 122:f9eeca106725 477 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
Kojto 122:f9eeca106725 478 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
Kojto 108:34e6b704fe68 479 /**
Kojto 108:34e6b704fe68 480 * @}
Kojto 108:34e6b704fe68 481 */
Kojto 108:34e6b704fe68 482
Kojto 108:34e6b704fe68 483 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 484 * @{
Kojto 108:34e6b704fe68 485 */
Kojto 108:34e6b704fe68 486 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto 108:34e6b704fe68 487 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto 108:34e6b704fe68 488 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto 108:34e6b704fe68 489 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto 108:34e6b704fe68 490 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto 108:34e6b704fe68 491 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto 108:34e6b704fe68 492 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto 108:34e6b704fe68 493 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto 122:f9eeca106725 494 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
Kojto 122:f9eeca106725 495 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 122:f9eeca106725 496 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 122:f9eeca106725 497 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 122:f9eeca106725 498 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 122:f9eeca106725 499 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 122:f9eeca106725 500 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 122:f9eeca106725 501 #endif
Kojto 108:34e6b704fe68 502 /**
Kojto 108:34e6b704fe68 503 * @}
Kojto 108:34e6b704fe68 504 */
Kojto 108:34e6b704fe68 505
Kojto 108:34e6b704fe68 506 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 507 * @{
Kojto 108:34e6b704fe68 508 */
Kojto 108:34e6b704fe68 509 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 510 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 511
Kojto 108:34e6b704fe68 512 /**
Kojto 108:34e6b704fe68 513 * @}
Kojto 108:34e6b704fe68 514 */
Kojto 108:34e6b704fe68 515
Kojto 108:34e6b704fe68 516 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 517 * @{
Kojto 108:34e6b704fe68 518 */
Kojto 108:34e6b704fe68 519 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto 108:34e6b704fe68 520 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto 108:34e6b704fe68 521 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto 108:34e6b704fe68 522 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto 108:34e6b704fe68 523 /**
Kojto 108:34e6b704fe68 524 * @}
Kojto 108:34e6b704fe68 525 */
Kojto 108:34e6b704fe68 526
Kojto 108:34e6b704fe68 527 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 528 * @{
Kojto 108:34e6b704fe68 529 */
Kojto 108:34e6b704fe68 530
Kojto 108:34e6b704fe68 531 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto 108:34e6b704fe68 532 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto 108:34e6b704fe68 533 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto 108:34e6b704fe68 534 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto 108:34e6b704fe68 535
Kojto 108:34e6b704fe68 536 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto 108:34e6b704fe68 537 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto 108:34e6b704fe68 538 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto 108:34e6b704fe68 539
Kojto 122:f9eeca106725 540 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
Kojto 122:f9eeca106725 541 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 122:f9eeca106725 542 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 122:f9eeca106725 543 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 122:f9eeca106725 544
Kojto 122:f9eeca106725 545 /* The following 3 definition have also been present in a temporary version of lptim.h */
Kojto 122:f9eeca106725 546 /* They need to be renamed also to the right name, just in case */
Kojto 122:f9eeca106725 547 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 122:f9eeca106725 548 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 122:f9eeca106725 549 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 108:34e6b704fe68 550
Kojto 108:34e6b704fe68 551 /**
Kojto 108:34e6b704fe68 552 * @}
Kojto 108:34e6b704fe68 553 */
Kojto 108:34e6b704fe68 554
Kojto 108:34e6b704fe68 555 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 556 * @{
Kojto 108:34e6b704fe68 557 */
Kojto 122:f9eeca106725 558 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
Kojto 122:f9eeca106725 559 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
Kojto 122:f9eeca106725 560 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
Kojto 122:f9eeca106725 561 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
Kojto 122:f9eeca106725 562
Kojto 108:34e6b704fe68 563 #define NAND_AddressTypedef NAND_AddressTypeDef
Kojto 108:34e6b704fe68 564
Kojto 108:34e6b704fe68 565 #define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto 108:34e6b704fe68 566 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto 108:34e6b704fe68 567 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto 108:34e6b704fe68 568 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto 108:34e6b704fe68 569 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto 108:34e6b704fe68 570 /**
Kojto 108:34e6b704fe68 571 * @}
Kojto 108:34e6b704fe68 572 */
Kojto 108:34e6b704fe68 573
Kojto 108:34e6b704fe68 574 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 575 * @{
Kojto 108:34e6b704fe68 576 */
Kojto 108:34e6b704fe68 577 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto 108:34e6b704fe68 578 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto 108:34e6b704fe68 579 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto 108:34e6b704fe68 580 #define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto 108:34e6b704fe68 581 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto 108:34e6b704fe68 582
Kojto 108:34e6b704fe68 583 #define __NOR_WRITE NOR_WRITE
Kojto 108:34e6b704fe68 584 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto 108:34e6b704fe68 585 /**
Kojto 108:34e6b704fe68 586 * @}
Kojto 108:34e6b704fe68 587 */
Kojto 108:34e6b704fe68 588
Kojto 108:34e6b704fe68 589 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 590 * @{
Kojto 108:34e6b704fe68 591 */
Kojto 108:34e6b704fe68 592
Kojto 108:34e6b704fe68 593 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 594 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 595 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto 108:34e6b704fe68 596 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto 108:34e6b704fe68 597
Kojto 108:34e6b704fe68 598 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 599 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 600 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto 108:34e6b704fe68 601 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto 108:34e6b704fe68 602
Kojto 108:34e6b704fe68 603 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 604 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 605
Kojto 108:34e6b704fe68 606 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 607 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 608
Kojto 108:34e6b704fe68 609 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 610 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 611
Kojto 108:34e6b704fe68 612 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 613
Kojto 108:34e6b704fe68 614 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto 108:34e6b704fe68 615 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto 108:34e6b704fe68 616 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto 108:34e6b704fe68 617
Kojto 108:34e6b704fe68 618 /**
Kojto 108:34e6b704fe68 619 * @}
Kojto 108:34e6b704fe68 620 */
Kojto 108:34e6b704fe68 621
Kojto 108:34e6b704fe68 622 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 623 * @{
Kojto 108:34e6b704fe68 624 */
Kojto 108:34e6b704fe68 625 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto 122:f9eeca106725 626 #if defined(STM32F7)
Kojto 122:f9eeca106725 627 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
Kojto 122:f9eeca106725 628 #endif
Kojto 108:34e6b704fe68 629 /**
Kojto 108:34e6b704fe68 630 * @}
Kojto 108:34e6b704fe68 631 */
Kojto 108:34e6b704fe68 632
Kojto 108:34e6b704fe68 633 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 634 * @{
Kojto 108:34e6b704fe68 635 */
Kojto 108:34e6b704fe68 636
Kojto 108:34e6b704fe68 637 /* Compact Flash-ATA registers description */
Kojto 108:34e6b704fe68 638 #define CF_DATA ATA_DATA
Kojto 108:34e6b704fe68 639 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto 108:34e6b704fe68 640 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto 108:34e6b704fe68 641 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto 108:34e6b704fe68 642 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto 108:34e6b704fe68 643 #define CF_CARD_HEAD ATA_CARD_HEAD
Kojto 108:34e6b704fe68 644 #define CF_STATUS_CMD ATA_STATUS_CMD
Kojto 108:34e6b704fe68 645 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto 108:34e6b704fe68 646 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto 108:34e6b704fe68 647
Kojto 108:34e6b704fe68 648 /* Compact Flash-ATA commands */
Kojto 108:34e6b704fe68 649 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto 108:34e6b704fe68 650 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto 108:34e6b704fe68 651 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto 108:34e6b704fe68 652 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto 108:34e6b704fe68 653
Kojto 108:34e6b704fe68 654 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto 108:34e6b704fe68 655 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto 108:34e6b704fe68 656 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto 108:34e6b704fe68 657 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto 108:34e6b704fe68 658 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto 108:34e6b704fe68 659 /**
Kojto 108:34e6b704fe68 660 * @}
Kojto 108:34e6b704fe68 661 */
Kojto 108:34e6b704fe68 662
Kojto 108:34e6b704fe68 663 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 664 * @{
Kojto 108:34e6b704fe68 665 */
Kojto 108:34e6b704fe68 666
Kojto 108:34e6b704fe68 667 #define FORMAT_BIN RTC_FORMAT_BIN
Kojto 108:34e6b704fe68 668 #define FORMAT_BCD RTC_FORMAT_BCD
Kojto 108:34e6b704fe68 669
Kojto 108:34e6b704fe68 670 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto 108:34e6b704fe68 671 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 108:34e6b704fe68 672 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 108:34e6b704fe68 673 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 108:34e6b704fe68 674 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 108:34e6b704fe68 675
Kojto 108:34e6b704fe68 676 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 108:34e6b704fe68 677 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 108:34e6b704fe68 678 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 108:34e6b704fe68 679 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 108:34e6b704fe68 680 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 108:34e6b704fe68 681 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 108:34e6b704fe68 682 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 108:34e6b704fe68 683 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 108:34e6b704fe68 684
Kojto 108:34e6b704fe68 685 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto 122:f9eeca106725 686 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Kojto 122:f9eeca106725 687 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Kojto 122:f9eeca106725 688 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Kojto 108:34e6b704fe68 689
Kojto 108:34e6b704fe68 690 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto 108:34e6b704fe68 691 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto 122:f9eeca106725 692 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Kojto 122:f9eeca106725 693
Kojto 122:f9eeca106725 694 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Kojto 122:f9eeca106725 695 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Kojto 122:f9eeca106725 696 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
Kojto 108:34e6b704fe68 697
Kojto 108:34e6b704fe68 698 /**
Kojto 108:34e6b704fe68 699 * @}
Kojto 108:34e6b704fe68 700 */
Kojto 108:34e6b704fe68 701
Kojto 108:34e6b704fe68 702
Kojto 108:34e6b704fe68 703 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 704 * @{
Kojto 108:34e6b704fe68 705 */
Kojto 108:34e6b704fe68 706 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto 108:34e6b704fe68 707 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto 108:34e6b704fe68 708
Kojto 108:34e6b704fe68 709 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 710 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 711 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 712 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 713
Kojto 108:34e6b704fe68 714 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto 108:34e6b704fe68 715 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto 108:34e6b704fe68 716
Kojto 108:34e6b704fe68 717 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto 108:34e6b704fe68 718 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto 108:34e6b704fe68 719 /**
Kojto 108:34e6b704fe68 720 * @}
Kojto 108:34e6b704fe68 721 */
Kojto 108:34e6b704fe68 722
Kojto 108:34e6b704fe68 723
Kojto 122:f9eeca106725 724 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 725 * @{
Kojto 108:34e6b704fe68 726 */
Kojto 108:34e6b704fe68 727 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto 108:34e6b704fe68 728 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto 108:34e6b704fe68 729 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto 108:34e6b704fe68 730 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto 108:34e6b704fe68 731 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto 108:34e6b704fe68 732 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto 108:34e6b704fe68 733 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto 108:34e6b704fe68 734 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto 108:34e6b704fe68 735 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto 108:34e6b704fe68 736 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto 108:34e6b704fe68 737 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto 108:34e6b704fe68 738 /**
Kojto 108:34e6b704fe68 739 * @}
Kojto 108:34e6b704fe68 740 */
Kojto 108:34e6b704fe68 741
Kojto 122:f9eeca106725 742 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 743 * @{
Kojto 108:34e6b704fe68 744 */
Kojto 108:34e6b704fe68 745 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto 108:34e6b704fe68 746 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto 108:34e6b704fe68 747
Kojto 108:34e6b704fe68 748 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto 108:34e6b704fe68 749 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto 108:34e6b704fe68 750
Kojto 108:34e6b704fe68 751 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto 108:34e6b704fe68 752 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto 108:34e6b704fe68 753
Kojto 108:34e6b704fe68 754 /**
Kojto 108:34e6b704fe68 755 * @}
Kojto 108:34e6b704fe68 756 */
Kojto 108:34e6b704fe68 757
Kojto 108:34e6b704fe68 758 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 759 * @{
Kojto 108:34e6b704fe68 760 */
Kojto 108:34e6b704fe68 761 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto 108:34e6b704fe68 762 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto 108:34e6b704fe68 763
Kojto 108:34e6b704fe68 764 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto 108:34e6b704fe68 765 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto 108:34e6b704fe68 766 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto 108:34e6b704fe68 767 #define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto 108:34e6b704fe68 768 #define TIM_DMABase_SR TIM_DMABASE_SR
Kojto 108:34e6b704fe68 769 #define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto 108:34e6b704fe68 770 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto 108:34e6b704fe68 771 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto 108:34e6b704fe68 772 #define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto 108:34e6b704fe68 773 #define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto 108:34e6b704fe68 774 #define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto 108:34e6b704fe68 775 #define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto 108:34e6b704fe68 776 #define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto 108:34e6b704fe68 777 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto 108:34e6b704fe68 778 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto 108:34e6b704fe68 779 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto 108:34e6b704fe68 780 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto 108:34e6b704fe68 781 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto 108:34e6b704fe68 782 #define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto 108:34e6b704fe68 783 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto 108:34e6b704fe68 784 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto 108:34e6b704fe68 785 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto 108:34e6b704fe68 786 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto 108:34e6b704fe68 787 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto 108:34e6b704fe68 788 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto 108:34e6b704fe68 789 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto 108:34e6b704fe68 790 #define TIM_DMABase_OR TIM_DMABASE_OR
Kojto 108:34e6b704fe68 791
Kojto 108:34e6b704fe68 792 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto 108:34e6b704fe68 793 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto 108:34e6b704fe68 794 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto 108:34e6b704fe68 795 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto 108:34e6b704fe68 796 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto 108:34e6b704fe68 797 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto 108:34e6b704fe68 798 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto 108:34e6b704fe68 799 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto 108:34e6b704fe68 800 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto 108:34e6b704fe68 801
Kojto 108:34e6b704fe68 802 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto 108:34e6b704fe68 803 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto 108:34e6b704fe68 804 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto 108:34e6b704fe68 805 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto 108:34e6b704fe68 806 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto 108:34e6b704fe68 807 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto 108:34e6b704fe68 808 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto 108:34e6b704fe68 809 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto 108:34e6b704fe68 810 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto 108:34e6b704fe68 811 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto 108:34e6b704fe68 812 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto 108:34e6b704fe68 813 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto 108:34e6b704fe68 814 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto 108:34e6b704fe68 815 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto 108:34e6b704fe68 816 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto 108:34e6b704fe68 817 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto 108:34e6b704fe68 818 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto 108:34e6b704fe68 819 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto 108:34e6b704fe68 820
Kojto 108:34e6b704fe68 821 /**
Kojto 108:34e6b704fe68 822 * @}
Kojto 108:34e6b704fe68 823 */
Kojto 108:34e6b704fe68 824
Kojto 108:34e6b704fe68 825 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 826 * @{
Kojto 108:34e6b704fe68 827 */
Kojto 108:34e6b704fe68 828 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto 108:34e6b704fe68 829 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto 108:34e6b704fe68 830 /**
Kojto 108:34e6b704fe68 831 * @}
Kojto 108:34e6b704fe68 832 */
Kojto 108:34e6b704fe68 833
Kojto 108:34e6b704fe68 834 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 835 * @{
Kojto 108:34e6b704fe68 836 */
Kojto 108:34e6b704fe68 837 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 838 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 839 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 840 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 841
Kojto 108:34e6b704fe68 842 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto 108:34e6b704fe68 843 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto 108:34e6b704fe68 844
Kojto 108:34e6b704fe68 845 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto 108:34e6b704fe68 846 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto 108:34e6b704fe68 847 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto 108:34e6b704fe68 848 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto 108:34e6b704fe68 849
Kojto 108:34e6b704fe68 850 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto 108:34e6b704fe68 851 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto 108:34e6b704fe68 852 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto 108:34e6b704fe68 853 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto 108:34e6b704fe68 854
Kojto 108:34e6b704fe68 855 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto 108:34e6b704fe68 856 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto 108:34e6b704fe68 857
Kojto 108:34e6b704fe68 858 /**
Kojto 108:34e6b704fe68 859 * @}
Kojto 108:34e6b704fe68 860 */
Kojto 108:34e6b704fe68 861
Kojto 108:34e6b704fe68 862
Kojto 108:34e6b704fe68 863 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 864 * @{
Kojto 108:34e6b704fe68 865 */
Kojto 108:34e6b704fe68 866
Kojto 108:34e6b704fe68 867 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto 108:34e6b704fe68 868 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto 108:34e6b704fe68 869
Kojto 108:34e6b704fe68 870 #define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto 108:34e6b704fe68 871 #define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto 108:34e6b704fe68 872 /**
Kojto 108:34e6b704fe68 873 * @}
Kojto 108:34e6b704fe68 874 */
Kojto 108:34e6b704fe68 875
Kojto 108:34e6b704fe68 876 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 877 * @{
Kojto 108:34e6b704fe68 878 */
Kojto 108:34e6b704fe68 879 #define CFR_BASE WWDG_CFR_BASE
Kojto 108:34e6b704fe68 880
Kojto 108:34e6b704fe68 881 /**
Kojto 108:34e6b704fe68 882 * @}
Kojto 108:34e6b704fe68 883 */
Kojto 108:34e6b704fe68 884
Kojto 108:34e6b704fe68 885 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 886 * @{
Kojto 108:34e6b704fe68 887 */
Kojto 108:34e6b704fe68 888 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto 108:34e6b704fe68 889 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto 108:34e6b704fe68 890 #define CAN_IT_RQCP0 CAN_IT_TME
Kojto 108:34e6b704fe68 891 #define CAN_IT_RQCP1 CAN_IT_TME
Kojto 108:34e6b704fe68 892 #define CAN_IT_RQCP2 CAN_IT_TME
Kojto 108:34e6b704fe68 893 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 108:34e6b704fe68 894 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 122:f9eeca106725 895 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
Kojto 122:f9eeca106725 896 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
Kojto 122:f9eeca106725 897 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
Kojto 108:34e6b704fe68 898
Kojto 108:34e6b704fe68 899 /**
Kojto 108:34e6b704fe68 900 * @}
Kojto 108:34e6b704fe68 901 */
Kojto 108:34e6b704fe68 902
Kojto 108:34e6b704fe68 903 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 904 * @{
Kojto 108:34e6b704fe68 905 */
Kojto 108:34e6b704fe68 906
Kojto 108:34e6b704fe68 907 #define VLAN_TAG ETH_VLAN_TAG
Kojto 108:34e6b704fe68 908 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto 108:34e6b704fe68 909 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto 108:34e6b704fe68 910 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto 108:34e6b704fe68 911 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto 108:34e6b704fe68 912 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto 108:34e6b704fe68 913 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto 108:34e6b704fe68 914 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto 108:34e6b704fe68 915
Kojto 122:f9eeca106725 916 #define ETH_MMCCR ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 917 #define ETH_MMCRIR ((uint32_t)0x00000104U)
Kojto 122:f9eeca106725 918 #define ETH_MMCTIR ((uint32_t)0x00000108U)
Kojto 122:f9eeca106725 919 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
Kojto 122:f9eeca106725 920 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
Kojto 122:f9eeca106725 921 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
Kojto 122:f9eeca106725 922 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
Kojto 122:f9eeca106725 923 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
Kojto 122:f9eeca106725 924 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
Kojto 122:f9eeca106725 925 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
Kojto 122:f9eeca106725 926 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
Kojto 122:f9eeca106725 927
Kojto 122:f9eeca106725 928 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto 122:f9eeca106725 929 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto 122:f9eeca106725 930 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto 122:f9eeca106725 931 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto 122:f9eeca106725 932 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto 122:f9eeca106725 933 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto 122:f9eeca106725 934 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto 122:f9eeca106725 935 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto 122:f9eeca106725 936 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto 122:f9eeca106725 937 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto 122:f9eeca106725 938 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto 122:f9eeca106725 939 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto 122:f9eeca106725 940 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto 122:f9eeca106725 941 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto 122:f9eeca106725 942 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto 122:f9eeca106725 943 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto 122:f9eeca106725 944 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto 122:f9eeca106725 945 #if defined(STM32F1)
Kojto 122:f9eeca106725 946 #else
Kojto 122:f9eeca106725 947 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto 122:f9eeca106725 948 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto 122:f9eeca106725 949 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto 122:f9eeca106725 950 #endif
Kojto 122:f9eeca106725 951 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto 122:f9eeca106725 952 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto 122:f9eeca106725 953 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto 122:f9eeca106725 954 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto 122:f9eeca106725 955 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto 122:f9eeca106725 956 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto 122:f9eeca106725 957 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto 108:34e6b704fe68 958
Kojto 108:34e6b704fe68 959 /**
Kojto 108:34e6b704fe68 960 * @}
Kojto 108:34e6b704fe68 961 */
Kojto 122:f9eeca106725 962
Kojto 122:f9eeca106725 963 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
Kojto 122:f9eeca106725 964 * @{
Kojto 122:f9eeca106725 965 */
Kojto 122:f9eeca106725 966 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
Kojto 122:f9eeca106725 967 #define DCMI_IT_OVF DCMI_IT_OVR
Kojto 122:f9eeca106725 968 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
Kojto 122:f9eeca106725 969 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
Kojto 122:f9eeca106725 970
Kojto 122:f9eeca106725 971 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
Kojto 122:f9eeca106725 972 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
Kojto 122:f9eeca106725 973 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
Kojto 122:f9eeca106725 974
Kojto 122:f9eeca106725 975 /**
Kojto 122:f9eeca106725 976 * @}
Kojto 122:f9eeca106725 977 */
Kojto 122:f9eeca106725 978
Kojto 122:f9eeca106725 979 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
Kojto 122:f9eeca106725 980 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 122:f9eeca106725 981 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
Kojto 122:f9eeca106725 982 * @{
Kojto 122:f9eeca106725 983 */
Kojto 122:f9eeca106725 984 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
Kojto 122:f9eeca106725 985 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
Kojto 122:f9eeca106725 986 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
Kojto 122:f9eeca106725 987 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
Kojto 122:f9eeca106725 988 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
Kojto 122:f9eeca106725 989
Kojto 122:f9eeca106725 990 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
Kojto 122:f9eeca106725 991 #define CM_RGB888 DMA2D_INPUT_RGB888
Kojto 122:f9eeca106725 992 #define CM_RGB565 DMA2D_INPUT_RGB565
Kojto 122:f9eeca106725 993 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
Kojto 122:f9eeca106725 994 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
Kojto 122:f9eeca106725 995 #define CM_L8 DMA2D_INPUT_L8
Kojto 122:f9eeca106725 996 #define CM_AL44 DMA2D_INPUT_AL44
Kojto 122:f9eeca106725 997 #define CM_AL88 DMA2D_INPUT_AL88
Kojto 122:f9eeca106725 998 #define CM_L4 DMA2D_INPUT_L4
Kojto 122:f9eeca106725 999 #define CM_A8 DMA2D_INPUT_A8
Kojto 122:f9eeca106725 1000 #define CM_A4 DMA2D_INPUT_A4
Kojto 122:f9eeca106725 1001 /**
Kojto 122:f9eeca106725 1002 * @}
Kojto 122:f9eeca106725 1003 */
Kojto 122:f9eeca106725 1004 #endif /* STM32L4xx || STM32F7*/
Kojto 108:34e6b704fe68 1005
Kojto 108:34e6b704fe68 1006 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto 108:34e6b704fe68 1007 * @{
Kojto 108:34e6b704fe68 1008 */
Kojto 108:34e6b704fe68 1009
Kojto 108:34e6b704fe68 1010 /**
Kojto 108:34e6b704fe68 1011 * @}
Kojto 108:34e6b704fe68 1012 */
Kojto 108:34e6b704fe68 1013
Kojto 108:34e6b704fe68 1014 /* Exported functions --------------------------------------------------------*/
Kojto 108:34e6b704fe68 1015
Kojto 108:34e6b704fe68 1016 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1017 * @{
Kojto 108:34e6b704fe68 1018 */
Kojto 108:34e6b704fe68 1019 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto 108:34e6b704fe68 1020 /**
Kojto 108:34e6b704fe68 1021 * @}
Kojto 108:34e6b704fe68 1022 */
Kojto 108:34e6b704fe68 1023
Kojto 108:34e6b704fe68 1024 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1025 * @{
Kojto 108:34e6b704fe68 1026 */
Kojto 122:f9eeca106725 1027 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
Kojto 122:f9eeca106725 1028 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
Kojto 108:34e6b704fe68 1029 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto 108:34e6b704fe68 1030 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto 108:34e6b704fe68 1031 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto 108:34e6b704fe68 1032 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto 108:34e6b704fe68 1033
Kojto 108:34e6b704fe68 1034 /*HASH Algorithm Selection*/
Kojto 108:34e6b704fe68 1035
Kojto 108:34e6b704fe68 1036 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto 108:34e6b704fe68 1037 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto 108:34e6b704fe68 1038 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto 108:34e6b704fe68 1039 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto 108:34e6b704fe68 1040
Kojto 108:34e6b704fe68 1041 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto 108:34e6b704fe68 1042 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto 108:34e6b704fe68 1043
Kojto 108:34e6b704fe68 1044 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto 108:34e6b704fe68 1045 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto 108:34e6b704fe68 1046 /**
Kojto 108:34e6b704fe68 1047 * @}
Kojto 108:34e6b704fe68 1048 */
Kojto 108:34e6b704fe68 1049
Kojto 108:34e6b704fe68 1050 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1051 * @{
Kojto 108:34e6b704fe68 1052 */
Kojto 108:34e6b704fe68 1053 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto 108:34e6b704fe68 1054 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto 108:34e6b704fe68 1055 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto 108:34e6b704fe68 1056 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto 108:34e6b704fe68 1057 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto 108:34e6b704fe68 1058 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto 108:34e6b704fe68 1059 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto 108:34e6b704fe68 1060 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto 108:34e6b704fe68 1061 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto 122:f9eeca106725 1062 #if defined(STM32L0)
Kojto 122:f9eeca106725 1063 #else
Kojto 108:34e6b704fe68 1064 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto 122:f9eeca106725 1065 #endif
Kojto 108:34e6b704fe68 1066 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto 108:34e6b704fe68 1067 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto 108:34e6b704fe68 1068 /**
Kojto 108:34e6b704fe68 1069 * @}
Kojto 108:34e6b704fe68 1070 */
Kojto 108:34e6b704fe68 1071
Kojto 108:34e6b704fe68 1072 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1073 * @{
Kojto 108:34e6b704fe68 1074 */
Kojto 108:34e6b704fe68 1075 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto 108:34e6b704fe68 1076 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto 108:34e6b704fe68 1077 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto 108:34e6b704fe68 1078 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto 108:34e6b704fe68 1079 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto 108:34e6b704fe68 1080 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto 108:34e6b704fe68 1081 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto 108:34e6b704fe68 1082
Kojto 108:34e6b704fe68 1083 /**
Kojto 108:34e6b704fe68 1084 * @}
Kojto 108:34e6b704fe68 1085 */
Kojto 108:34e6b704fe68 1086
Kojto 108:34e6b704fe68 1087 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1088 * @{
Kojto 108:34e6b704fe68 1089 */
Kojto 122:f9eeca106725 1090 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto 122:f9eeca106725 1091 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto 122:f9eeca106725 1092 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
Kojto 122:f9eeca106725 1093 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
Kojto 108:34e6b704fe68 1094
Kojto 108:34e6b704fe68 1095 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto 108:34e6b704fe68 1096 /**
Kojto 108:34e6b704fe68 1097 * @}
Kojto 108:34e6b704fe68 1098 */
Kojto 108:34e6b704fe68 1099
Kojto 108:34e6b704fe68 1100 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto 108:34e6b704fe68 1101 * @{
Kojto 108:34e6b704fe68 1102 */
Kojto 108:34e6b704fe68 1103 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto 108:34e6b704fe68 1104 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto 108:34e6b704fe68 1105 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto 108:34e6b704fe68 1106 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto 108:34e6b704fe68 1107 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto 108:34e6b704fe68 1108 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto 108:34e6b704fe68 1109 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto 108:34e6b704fe68 1110 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto 108:34e6b704fe68 1111 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto 108:34e6b704fe68 1112 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto 108:34e6b704fe68 1113 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto 108:34e6b704fe68 1114 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto 108:34e6b704fe68 1115 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto 108:34e6b704fe68 1116 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto 108:34e6b704fe68 1117 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto 108:34e6b704fe68 1118 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto 108:34e6b704fe68 1119
Kojto 108:34e6b704fe68 1120 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto 108:34e6b704fe68 1121 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto 108:34e6b704fe68 1122 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto 108:34e6b704fe68 1123 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto 108:34e6b704fe68 1124 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto 108:34e6b704fe68 1125 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto 108:34e6b704fe68 1126 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto 108:34e6b704fe68 1127
Kojto 108:34e6b704fe68 1128 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto 108:34e6b704fe68 1129 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto 108:34e6b704fe68 1130
Kojto 108:34e6b704fe68 1131 #define DBP_BitNumber DBP_BIT_NUMBER
Kojto 108:34e6b704fe68 1132 #define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto 108:34e6b704fe68 1133 #define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto 108:34e6b704fe68 1134 #define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto 108:34e6b704fe68 1135 #define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto 108:34e6b704fe68 1136 #define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto 108:34e6b704fe68 1137 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto 108:34e6b704fe68 1138 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto 108:34e6b704fe68 1139 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto 108:34e6b704fe68 1140 #define BRE_BitNumber BRE_BIT_NUMBER
Kojto 108:34e6b704fe68 1141
Kojto 108:34e6b704fe68 1142 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto 108:34e6b704fe68 1143
Kojto 108:34e6b704fe68 1144 /**
Kojto 108:34e6b704fe68 1145 * @}
Kojto 108:34e6b704fe68 1146 */
Kojto 108:34e6b704fe68 1147
Kojto 108:34e6b704fe68 1148 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1149 * @{
Kojto 108:34e6b704fe68 1150 */
Kojto 108:34e6b704fe68 1151 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto 108:34e6b704fe68 1152 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto 108:34e6b704fe68 1153 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto 108:34e6b704fe68 1154 /**
Kojto 108:34e6b704fe68 1155 * @}
Kojto 108:34e6b704fe68 1156 */
Kojto 108:34e6b704fe68 1157
Kojto 108:34e6b704fe68 1158 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1159 * @{
Kojto 108:34e6b704fe68 1160 */
Kojto 108:34e6b704fe68 1161 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto 108:34e6b704fe68 1162 /**
Kojto 108:34e6b704fe68 1163 * @}
Kojto 108:34e6b704fe68 1164 */
Kojto 108:34e6b704fe68 1165
Kojto 108:34e6b704fe68 1166 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1167 * @{
Kojto 108:34e6b704fe68 1168 */
Kojto 108:34e6b704fe68 1169 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto 108:34e6b704fe68 1170 #define HAL_TIM_DMAError TIM_DMAError
Kojto 108:34e6b704fe68 1171 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto 108:34e6b704fe68 1172 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto 108:34e6b704fe68 1173 /**
Kojto 108:34e6b704fe68 1174 * @}
Kojto 108:34e6b704fe68 1175 */
Kojto 108:34e6b704fe68 1176
Kojto 108:34e6b704fe68 1177 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1178 * @{
Kojto 108:34e6b704fe68 1179 */
Kojto 108:34e6b704fe68 1180 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto 108:34e6b704fe68 1181 /**
Kojto 108:34e6b704fe68 1182 * @}
Kojto 108:34e6b704fe68 1183 */
Kojto 108:34e6b704fe68 1184
Kojto 108:34e6b704fe68 1185 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1186 * @{
Kojto 108:34e6b704fe68 1187 */
Kojto 108:34e6b704fe68 1188 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto 108:34e6b704fe68 1189 /**
Kojto 108:34e6b704fe68 1190 * @}
Kojto 108:34e6b704fe68 1191 */
Kojto 108:34e6b704fe68 1192
Kojto 108:34e6b704fe68 1193
Kojto 122:f9eeca106725 1194 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto 108:34e6b704fe68 1195 * @{
Kojto 108:34e6b704fe68 1196 */
Kojto 108:34e6b704fe68 1197
Kojto 108:34e6b704fe68 1198 /**
Kojto 108:34e6b704fe68 1199 * @}
Kojto 108:34e6b704fe68 1200 */
Kojto 108:34e6b704fe68 1201
Kojto 108:34e6b704fe68 1202 /* Exported macros ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 1203
Kojto 108:34e6b704fe68 1204 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1205 * @{
Kojto 108:34e6b704fe68 1206 */
Kojto 108:34e6b704fe68 1207 #define AES_IT_CC CRYP_IT_CC
Kojto 108:34e6b704fe68 1208 #define AES_IT_ERR CRYP_IT_ERR
Kojto 108:34e6b704fe68 1209 #define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto 108:34e6b704fe68 1210 /**
Kojto 108:34e6b704fe68 1211 * @}
Kojto 108:34e6b704fe68 1212 */
Kojto 108:34e6b704fe68 1213
Kojto 108:34e6b704fe68 1214 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1215 * @{
Kojto 108:34e6b704fe68 1216 */
Kojto 108:34e6b704fe68 1217 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto 108:34e6b704fe68 1218 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto 108:34e6b704fe68 1219 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto 108:34e6b704fe68 1220 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto 108:34e6b704fe68 1221 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto 108:34e6b704fe68 1222 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto 108:34e6b704fe68 1223 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto 108:34e6b704fe68 1224 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto 108:34e6b704fe68 1225 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto 108:34e6b704fe68 1226 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto 108:34e6b704fe68 1227 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto 108:34e6b704fe68 1228 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto 108:34e6b704fe68 1229 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto 108:34e6b704fe68 1230
Kojto 108:34e6b704fe68 1231 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto 108:34e6b704fe68 1232 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto 108:34e6b704fe68 1233 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto 108:34e6b704fe68 1234 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto 108:34e6b704fe68 1235 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto 108:34e6b704fe68 1236
Kojto 108:34e6b704fe68 1237 /**
Kojto 108:34e6b704fe68 1238 * @}
Kojto 108:34e6b704fe68 1239 */
Kojto 108:34e6b704fe68 1240
Kojto 108:34e6b704fe68 1241
Kojto 108:34e6b704fe68 1242 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1243 * @{
Kojto 108:34e6b704fe68 1244 */
Kojto 108:34e6b704fe68 1245 #define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto 108:34e6b704fe68 1246 #define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto 108:34e6b704fe68 1247 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto 108:34e6b704fe68 1248 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto 108:34e6b704fe68 1249 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 108:34e6b704fe68 1250 #define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 108:34e6b704fe68 1251 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto 108:34e6b704fe68 1252 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto 108:34e6b704fe68 1253 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto 108:34e6b704fe68 1254 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto 108:34e6b704fe68 1255 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto 108:34e6b704fe68 1256 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto 108:34e6b704fe68 1257 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto 108:34e6b704fe68 1258
Kojto 108:34e6b704fe68 1259 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 108:34e6b704fe68 1260 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto 108:34e6b704fe68 1261 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto 108:34e6b704fe68 1262 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto 108:34e6b704fe68 1263 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto 108:34e6b704fe68 1264 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto 108:34e6b704fe68 1265 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto 108:34e6b704fe68 1266 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto 108:34e6b704fe68 1267 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto 108:34e6b704fe68 1268 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto 108:34e6b704fe68 1269 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto 108:34e6b704fe68 1270 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto 108:34e6b704fe68 1271 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto 108:34e6b704fe68 1272 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto 108:34e6b704fe68 1273 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto 108:34e6b704fe68 1274 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto 108:34e6b704fe68 1275 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto 108:34e6b704fe68 1276 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto 108:34e6b704fe68 1277 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto 108:34e6b704fe68 1278 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto 108:34e6b704fe68 1279
Kojto 108:34e6b704fe68 1280 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto 108:34e6b704fe68 1281 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto 108:34e6b704fe68 1282 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto 108:34e6b704fe68 1283 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto 108:34e6b704fe68 1284 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto 108:34e6b704fe68 1285 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 108:34e6b704fe68 1286 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 108:34e6b704fe68 1287 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto 108:34e6b704fe68 1288 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto 108:34e6b704fe68 1289 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto 108:34e6b704fe68 1290
Kojto 108:34e6b704fe68 1291 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto 108:34e6b704fe68 1292 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto 108:34e6b704fe68 1293 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto 108:34e6b704fe68 1294 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto 108:34e6b704fe68 1295 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto 108:34e6b704fe68 1296 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto 108:34e6b704fe68 1297 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto 108:34e6b704fe68 1298 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto 108:34e6b704fe68 1299
Kojto 108:34e6b704fe68 1300 #define __HAL_ADC_SQR1 ADC_SQR1
Kojto 108:34e6b704fe68 1301 #define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto 108:34e6b704fe68 1302 #define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto 108:34e6b704fe68 1303 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto 108:34e6b704fe68 1304 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto 108:34e6b704fe68 1305 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto 108:34e6b704fe68 1306 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto 108:34e6b704fe68 1307 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto 108:34e6b704fe68 1308 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto 108:34e6b704fe68 1309 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto 108:34e6b704fe68 1310 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto 108:34e6b704fe68 1311 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 108:34e6b704fe68 1312 #define __HAL_ADC_JSQR ADC_JSQR
Kojto 108:34e6b704fe68 1313
Kojto 108:34e6b704fe68 1314 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto 108:34e6b704fe68 1315 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto 108:34e6b704fe68 1316 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto 108:34e6b704fe68 1317 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto 108:34e6b704fe68 1318 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto 108:34e6b704fe68 1319 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto 108:34e6b704fe68 1320 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto 108:34e6b704fe68 1321 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto 108:34e6b704fe68 1322
Kojto 108:34e6b704fe68 1323 /**
Kojto 108:34e6b704fe68 1324 * @}
Kojto 108:34e6b704fe68 1325 */
Kojto 108:34e6b704fe68 1326
Kojto 108:34e6b704fe68 1327 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1328 * @{
Kojto 108:34e6b704fe68 1329 */
Kojto 108:34e6b704fe68 1330 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto 108:34e6b704fe68 1331 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto 108:34e6b704fe68 1332 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto 108:34e6b704fe68 1333 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto 108:34e6b704fe68 1334
Kojto 108:34e6b704fe68 1335 /**
Kojto 108:34e6b704fe68 1336 * @}
Kojto 108:34e6b704fe68 1337 */
Kojto 108:34e6b704fe68 1338
Kojto 108:34e6b704fe68 1339 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1340 * @{
Kojto 108:34e6b704fe68 1341 */
Kojto 108:34e6b704fe68 1342 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto 108:34e6b704fe68 1343 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto 108:34e6b704fe68 1344 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto 108:34e6b704fe68 1345 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto 108:34e6b704fe68 1346 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto 108:34e6b704fe68 1347 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto 108:34e6b704fe68 1348 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto 108:34e6b704fe68 1349 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto 108:34e6b704fe68 1350 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto 108:34e6b704fe68 1351 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto 108:34e6b704fe68 1352 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto 108:34e6b704fe68 1353 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto 108:34e6b704fe68 1354 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto 108:34e6b704fe68 1355 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto 108:34e6b704fe68 1356 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto 108:34e6b704fe68 1357 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto 108:34e6b704fe68 1358
Kojto 108:34e6b704fe68 1359 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto 108:34e6b704fe68 1360 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto 108:34e6b704fe68 1361 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto 108:34e6b704fe68 1362 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto 108:34e6b704fe68 1363 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto 108:34e6b704fe68 1364 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto 108:34e6b704fe68 1365 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto 108:34e6b704fe68 1366 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto 108:34e6b704fe68 1367 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto 108:34e6b704fe68 1368 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto 108:34e6b704fe68 1369 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto 108:34e6b704fe68 1370 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto 108:34e6b704fe68 1371 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto 108:34e6b704fe68 1372 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto 108:34e6b704fe68 1373
Kojto 108:34e6b704fe68 1374
Kojto 108:34e6b704fe68 1375 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto 108:34e6b704fe68 1376 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto 108:34e6b704fe68 1377 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto 108:34e6b704fe68 1378 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto 108:34e6b704fe68 1379 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto 108:34e6b704fe68 1380 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto 108:34e6b704fe68 1381 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto 108:34e6b704fe68 1382 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto 108:34e6b704fe68 1383 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto 108:34e6b704fe68 1384 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto 108:34e6b704fe68 1385 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto 108:34e6b704fe68 1386 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto 108:34e6b704fe68 1387 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto 108:34e6b704fe68 1388 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto 108:34e6b704fe68 1389 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto 108:34e6b704fe68 1390 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto 108:34e6b704fe68 1391 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto 108:34e6b704fe68 1392 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto 108:34e6b704fe68 1393 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto 108:34e6b704fe68 1394 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto 108:34e6b704fe68 1395 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto 108:34e6b704fe68 1396 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto 108:34e6b704fe68 1397 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto 108:34e6b704fe68 1398 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto 108:34e6b704fe68 1399
Kojto 108:34e6b704fe68 1400 /**
Kojto 108:34e6b704fe68 1401 * @}
Kojto 108:34e6b704fe68 1402 */
Kojto 108:34e6b704fe68 1403
Kojto 108:34e6b704fe68 1404 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1405 * @{
Kojto 108:34e6b704fe68 1406 */
Kojto 122:f9eeca106725 1407 #if defined(STM32F3)
Kojto 122:f9eeca106725 1408 #define COMP_START __HAL_COMP_ENABLE
Kojto 122:f9eeca106725 1409 #define COMP_STOP __HAL_COMP_DISABLE
Kojto 122:f9eeca106725 1410 #define COMP_LOCK __HAL_COMP_LOCK
Kojto 122:f9eeca106725 1411
Kojto 122:f9eeca106725 1412 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 1413 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1414 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1415 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1416 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1417 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1418 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1419 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1420 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1421 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1422 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1423 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1424 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1425 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1426 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1427 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 122:f9eeca106725 1428 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1429 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1430 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 122:f9eeca106725 1431 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1432 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1433 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 122:f9eeca106725 1434 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1435 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1436 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 122:f9eeca106725 1437 # endif
Kojto 122:f9eeca106725 1438 # if defined(STM32F302xE) || defined(STM32F302xC)
Kojto 122:f9eeca106725 1439 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1440 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1441 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1442 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1443 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1444 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1445 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1446 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1447 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1448 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1449 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1450 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1451 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1452 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1453 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1454 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1455 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1456 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1457 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1458 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 122:f9eeca106725 1459 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1460 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1461 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1462 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 122:f9eeca106725 1463 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1464 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1465 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1466 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 122:f9eeca106725 1467 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1468 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1469 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1470 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 122:f9eeca106725 1471 # endif
Kojto 122:f9eeca106725 1472 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 1473 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1474 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1475 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1476 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1477 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1479 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1480 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1482 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1483 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1484 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1486 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1487 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1489 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1490 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1491 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1493 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1494 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1496 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1497 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1498 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1500 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1501 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1503 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1504 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1505 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1506 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1507 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
Kojto 122:f9eeca106725 1508 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1509 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1510 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1511 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1512 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1513 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1514 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
Kojto 122:f9eeca106725 1515 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1516 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1517 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1518 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1519 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1520 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1521 __HAL_COMP_COMP7_EXTI_GET_FLAG())
Kojto 122:f9eeca106725 1522 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1523 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1524 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1525 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1526 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1527 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1528 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
Kojto 122:f9eeca106725 1529 # endif
Kojto 122:f9eeca106725 1530 # if defined(STM32F373xC) ||defined(STM32F378xx)
Kojto 108:34e6b704fe68 1531 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 108:34e6b704fe68 1532 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1533 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 108:34e6b704fe68 1534 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 108:34e6b704fe68 1535 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 108:34e6b704fe68 1536 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1537 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 108:34e6b704fe68 1538 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1539 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 108:34e6b704fe68 1540 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 122:f9eeca106725 1541 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 108:34e6b704fe68 1542 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 122:f9eeca106725 1543 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 108:34e6b704fe68 1544 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 122:f9eeca106725 1545 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 108:34e6b704fe68 1546 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 122:f9eeca106725 1547 # endif
Kojto 122:f9eeca106725 1548 #else
Kojto 122:f9eeca106725 1549 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1550 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1551 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 122:f9eeca106725 1552 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 122:f9eeca106725 1553 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1554 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1555 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 122:f9eeca106725 1556 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 122:f9eeca106725 1557 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 122:f9eeca106725 1558 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 122:f9eeca106725 1559 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 122:f9eeca106725 1560 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 122:f9eeca106725 1561 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 122:f9eeca106725 1562 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 122:f9eeca106725 1563 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 122:f9eeca106725 1564 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 122:f9eeca106725 1565 #endif
Kojto 122:f9eeca106725 1566
Kojto 108:34e6b704fe68 1567 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto 108:34e6b704fe68 1568
Kojto 122:f9eeca106725 1569 #if defined(STM32L0) || defined(STM32L4)
Kojto 122:f9eeca106725 1570 /* Note: On these STM32 families, the only argument of this macro */
Kojto 122:f9eeca106725 1571 /* is COMP_FLAG_LOCK. */
Kojto 122:f9eeca106725 1572 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
Kojto 122:f9eeca106725 1573 /* argument. */
Kojto 122:f9eeca106725 1574 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
Kojto 122:f9eeca106725 1575 #endif
Kojto 108:34e6b704fe68 1576 /**
Kojto 108:34e6b704fe68 1577 * @}
Kojto 108:34e6b704fe68 1578 */
Kojto 108:34e6b704fe68 1579
Kojto 122:f9eeca106725 1580 #if defined(STM32L0) || defined(STM32L4)
Kojto 122:f9eeca106725 1581 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
Kojto 122:f9eeca106725 1582 * @{
Kojto 122:f9eeca106725 1583 */
Kojto 122:f9eeca106725 1584 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto 122:f9eeca106725 1585 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto 122:f9eeca106725 1586 /**
Kojto 122:f9eeca106725 1587 * @}
Kojto 122:f9eeca106725 1588 */
Kojto 122:f9eeca106725 1589 #endif
Kojto 122:f9eeca106725 1590
Kojto 108:34e6b704fe68 1591 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1592 * @{
Kojto 108:34e6b704fe68 1593 */
Kojto 108:34e6b704fe68 1594
Kojto 108:34e6b704fe68 1595 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
Kojto 108:34e6b704fe68 1596 ((WAVE) == DAC_WAVE_NOISE)|| \
Kojto 108:34e6b704fe68 1597 ((WAVE) == DAC_WAVE_TRIANGLE))
Kojto 108:34e6b704fe68 1598
Kojto 108:34e6b704fe68 1599 /**
Kojto 108:34e6b704fe68 1600 * @}
Kojto 108:34e6b704fe68 1601 */
Kojto 108:34e6b704fe68 1602
Kojto 108:34e6b704fe68 1603 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1604 * @{
Kojto 108:34e6b704fe68 1605 */
Kojto 108:34e6b704fe68 1606
Kojto 108:34e6b704fe68 1607 #define IS_WRPAREA IS_OB_WRPAREA
Kojto 108:34e6b704fe68 1608 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto 108:34e6b704fe68 1609 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto 108:34e6b704fe68 1610 #define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto 108:34e6b704fe68 1611 #define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto 108:34e6b704fe68 1612 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto 108:34e6b704fe68 1613
Kojto 108:34e6b704fe68 1614 /**
Kojto 108:34e6b704fe68 1615 * @}
Kojto 108:34e6b704fe68 1616 */
Kojto 108:34e6b704fe68 1617
Kojto 108:34e6b704fe68 1618 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1619 * @{
Kojto 108:34e6b704fe68 1620 */
Kojto 108:34e6b704fe68 1621
Kojto 108:34e6b704fe68 1622 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto 108:34e6b704fe68 1623 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto 108:34e6b704fe68 1624 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto 108:34e6b704fe68 1625 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto 108:34e6b704fe68 1626 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto 108:34e6b704fe68 1627 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto 108:34e6b704fe68 1628 #define __HAL_I2C_SPEED I2C_SPEED
Kojto 108:34e6b704fe68 1629 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto 108:34e6b704fe68 1630 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto 108:34e6b704fe68 1631 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto 108:34e6b704fe68 1632 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto 108:34e6b704fe68 1633 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto 108:34e6b704fe68 1634 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto 108:34e6b704fe68 1635 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto 108:34e6b704fe68 1636 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto 108:34e6b704fe68 1637 /**
Kojto 108:34e6b704fe68 1638 * @}
Kojto 108:34e6b704fe68 1639 */
Kojto 108:34e6b704fe68 1640
Kojto 108:34e6b704fe68 1641 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1642 * @{
Kojto 108:34e6b704fe68 1643 */
Kojto 108:34e6b704fe68 1644
Kojto 108:34e6b704fe68 1645 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto 108:34e6b704fe68 1646 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto 108:34e6b704fe68 1647
Kojto 108:34e6b704fe68 1648 /**
Kojto 108:34e6b704fe68 1649 * @}
Kojto 108:34e6b704fe68 1650 */
Kojto 108:34e6b704fe68 1651
Kojto 108:34e6b704fe68 1652 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1653 * @{
Kojto 108:34e6b704fe68 1654 */
Kojto 108:34e6b704fe68 1655
Kojto 108:34e6b704fe68 1656 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto 108:34e6b704fe68 1657 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto 108:34e6b704fe68 1658
Kojto 108:34e6b704fe68 1659 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 1660 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 108:34e6b704fe68 1661 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 1662 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 108:34e6b704fe68 1663
Kojto 108:34e6b704fe68 1664 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto 108:34e6b704fe68 1665
Kojto 108:34e6b704fe68 1666
Kojto 108:34e6b704fe68 1667 /**
Kojto 108:34e6b704fe68 1668 * @}
Kojto 108:34e6b704fe68 1669 */
Kojto 108:34e6b704fe68 1670
Kojto 108:34e6b704fe68 1671
Kojto 108:34e6b704fe68 1672 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1673 * @{
Kojto 108:34e6b704fe68 1674 */
Kojto 108:34e6b704fe68 1675 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto 108:34e6b704fe68 1676 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto 108:34e6b704fe68 1677 /**
Kojto 108:34e6b704fe68 1678 * @}
Kojto 108:34e6b704fe68 1679 */
Kojto 108:34e6b704fe68 1680
Kojto 108:34e6b704fe68 1681
Kojto 108:34e6b704fe68 1682 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1683 * @{
Kojto 108:34e6b704fe68 1684 */
Kojto 108:34e6b704fe68 1685
Kojto 108:34e6b704fe68 1686 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto 108:34e6b704fe68 1687 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto 108:34e6b704fe68 1688 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto 108:34e6b704fe68 1689
Kojto 108:34e6b704fe68 1690 /**
Kojto 108:34e6b704fe68 1691 * @}
Kojto 108:34e6b704fe68 1692 */
Kojto 108:34e6b704fe68 1693
Kojto 108:34e6b704fe68 1694
Kojto 108:34e6b704fe68 1695 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1696 * @{
Kojto 108:34e6b704fe68 1697 */
Kojto 108:34e6b704fe68 1698 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto 108:34e6b704fe68 1699 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto 108:34e6b704fe68 1700 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto 108:34e6b704fe68 1701 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto 108:34e6b704fe68 1702 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto 108:34e6b704fe68 1703 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto 108:34e6b704fe68 1704 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto 108:34e6b704fe68 1705 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto 108:34e6b704fe68 1706 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto 108:34e6b704fe68 1707 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto 108:34e6b704fe68 1708 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto 108:34e6b704fe68 1709 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto 108:34e6b704fe68 1710 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto 108:34e6b704fe68 1711
Kojto 108:34e6b704fe68 1712 /**
Kojto 108:34e6b704fe68 1713 * @}
Kojto 108:34e6b704fe68 1714 */
Kojto 108:34e6b704fe68 1715
Kojto 108:34e6b704fe68 1716
Kojto 108:34e6b704fe68 1717 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 1718 * @{
Kojto 108:34e6b704fe68 1719 */
Kojto 108:34e6b704fe68 1720 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 108:34e6b704fe68 1721 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 108:34e6b704fe68 1722 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1723 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1724 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 108:34e6b704fe68 1725 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 108:34e6b704fe68 1726 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto 108:34e6b704fe68 1727 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto 108:34e6b704fe68 1728 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto 108:34e6b704fe68 1729 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto 108:34e6b704fe68 1730 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto 108:34e6b704fe68 1731 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto 108:34e6b704fe68 1732 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto 108:34e6b704fe68 1733 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto 108:34e6b704fe68 1734 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto 108:34e6b704fe68 1735 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto 122:f9eeca106725 1736 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
Kojto 108:34e6b704fe68 1737 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 108:34e6b704fe68 1738 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 108:34e6b704fe68 1739 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1740 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1741 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 108:34e6b704fe68 1742 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 108:34e6b704fe68 1743 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1744 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 122:f9eeca106725 1745 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
Kojto 122:f9eeca106725 1746 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
Kojto 108:34e6b704fe68 1747 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto 108:34e6b704fe68 1748 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto 108:34e6b704fe68 1749 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto 108:34e6b704fe68 1750 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto 108:34e6b704fe68 1751 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1752 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 1753 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto 108:34e6b704fe68 1754 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto 108:34e6b704fe68 1755
Kojto 108:34e6b704fe68 1756 #if defined (STM32F4)
Kojto 108:34e6b704fe68 1757 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto 108:34e6b704fe68 1758 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto 108:34e6b704fe68 1759 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto 108:34e6b704fe68 1760 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto 108:34e6b704fe68 1761 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto 108:34e6b704fe68 1762 #else
Kojto 108:34e6b704fe68 1763 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 1764 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 1765 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 1766 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto 108:34e6b704fe68 1767 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto 108:34e6b704fe68 1768 #endif /* STM32F4 */
Kojto 108:34e6b704fe68 1769 /**
Kojto 108:34e6b704fe68 1770 * @}
Kojto 108:34e6b704fe68 1771 */
Kojto 108:34e6b704fe68 1772
Kojto 108:34e6b704fe68 1773
Kojto 108:34e6b704fe68 1774 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto 108:34e6b704fe68 1775 * @{
Kojto 108:34e6b704fe68 1776 */
Kojto 108:34e6b704fe68 1777
Kojto 108:34e6b704fe68 1778 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto 108:34e6b704fe68 1779 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto 108:34e6b704fe68 1780
Kojto 108:34e6b704fe68 1781 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto 108:34e6b704fe68 1782 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto 108:34e6b704fe68 1783
Kojto 108:34e6b704fe68 1784 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto 108:34e6b704fe68 1785 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto 108:34e6b704fe68 1786 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1787 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1788 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto 108:34e6b704fe68 1789 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto 108:34e6b704fe68 1790 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto 108:34e6b704fe68 1791 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto 108:34e6b704fe68 1792 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto 108:34e6b704fe68 1793 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto 108:34e6b704fe68 1794 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1795 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1796 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto 108:34e6b704fe68 1797 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto 108:34e6b704fe68 1798 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto 108:34e6b704fe68 1799 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto 108:34e6b704fe68 1800 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto 108:34e6b704fe68 1801 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto 108:34e6b704fe68 1802 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto 108:34e6b704fe68 1803 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto 108:34e6b704fe68 1804 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto 108:34e6b704fe68 1805 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto 108:34e6b704fe68 1806 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1807 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1808 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto 108:34e6b704fe68 1809 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto 108:34e6b704fe68 1810 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1811 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1812 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto 108:34e6b704fe68 1813 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto 108:34e6b704fe68 1814 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 108:34e6b704fe68 1815 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto 108:34e6b704fe68 1816 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto 108:34e6b704fe68 1817 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto 108:34e6b704fe68 1818 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto 108:34e6b704fe68 1819 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto 108:34e6b704fe68 1820 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto 108:34e6b704fe68 1821 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto 108:34e6b704fe68 1822 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto 108:34e6b704fe68 1823 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto 108:34e6b704fe68 1824 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto 108:34e6b704fe68 1825 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto 108:34e6b704fe68 1826 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto 108:34e6b704fe68 1827 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto 108:34e6b704fe68 1828 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto 108:34e6b704fe68 1829 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto 108:34e6b704fe68 1830 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto 108:34e6b704fe68 1831 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto 108:34e6b704fe68 1832 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto 108:34e6b704fe68 1833 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto 108:34e6b704fe68 1834 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto 108:34e6b704fe68 1835 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto 108:34e6b704fe68 1836 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 108:34e6b704fe68 1837 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 108:34e6b704fe68 1838 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1839 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1840 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 108:34e6b704fe68 1841 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 108:34e6b704fe68 1842 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 108:34e6b704fe68 1843 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 108:34e6b704fe68 1844 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 108:34e6b704fe68 1845 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 108:34e6b704fe68 1846 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto 108:34e6b704fe68 1847 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto 108:34e6b704fe68 1848 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto 108:34e6b704fe68 1849 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto 108:34e6b704fe68 1850 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto 108:34e6b704fe68 1851 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto 108:34e6b704fe68 1852 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto 108:34e6b704fe68 1853 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto 108:34e6b704fe68 1854 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto 108:34e6b704fe68 1855 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto 108:34e6b704fe68 1856 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1857 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1858 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto 108:34e6b704fe68 1859 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto 108:34e6b704fe68 1860 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto 108:34e6b704fe68 1861 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto 108:34e6b704fe68 1862 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1863 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1864 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto 108:34e6b704fe68 1865 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto 108:34e6b704fe68 1866 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto 108:34e6b704fe68 1867 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto 108:34e6b704fe68 1868 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto 108:34e6b704fe68 1869 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto 108:34e6b704fe68 1870 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto 108:34e6b704fe68 1871 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto 108:34e6b704fe68 1872 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1873 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1874 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto 108:34e6b704fe68 1875 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto 108:34e6b704fe68 1876 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto 108:34e6b704fe68 1877 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto 108:34e6b704fe68 1878 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto 108:34e6b704fe68 1879 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto 108:34e6b704fe68 1880 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto 108:34e6b704fe68 1881 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto 108:34e6b704fe68 1882 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1883 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1884 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto 108:34e6b704fe68 1885 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto 108:34e6b704fe68 1886 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto 108:34e6b704fe68 1887 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto 108:34e6b704fe68 1888 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1889 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1890 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto 108:34e6b704fe68 1891 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto 108:34e6b704fe68 1892 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto 108:34e6b704fe68 1893 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto 108:34e6b704fe68 1894 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1895 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1896 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto 108:34e6b704fe68 1897 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto 108:34e6b704fe68 1898 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto 108:34e6b704fe68 1899 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto 108:34e6b704fe68 1900 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto 108:34e6b704fe68 1901 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto 108:34e6b704fe68 1902 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto 108:34e6b704fe68 1903 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto 108:34e6b704fe68 1904 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto 108:34e6b704fe68 1905 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto 108:34e6b704fe68 1906 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto 108:34e6b704fe68 1907 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto 108:34e6b704fe68 1908 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto 108:34e6b704fe68 1909 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto 108:34e6b704fe68 1910 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1911 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1912 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto 108:34e6b704fe68 1913 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto 108:34e6b704fe68 1914 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto 108:34e6b704fe68 1915 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto 108:34e6b704fe68 1916 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto 108:34e6b704fe68 1917 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto 108:34e6b704fe68 1918 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1919 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1920 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto 108:34e6b704fe68 1921 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto 108:34e6b704fe68 1922 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1923 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1924 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto 108:34e6b704fe68 1925 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto 108:34e6b704fe68 1926 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto 108:34e6b704fe68 1927 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto 108:34e6b704fe68 1928 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto 108:34e6b704fe68 1929 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto 108:34e6b704fe68 1930 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1931 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1932 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto 108:34e6b704fe68 1933 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto 108:34e6b704fe68 1934 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto 108:34e6b704fe68 1935 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto 108:34e6b704fe68 1936 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1937 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1938 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto 108:34e6b704fe68 1939 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto 108:34e6b704fe68 1940 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto 108:34e6b704fe68 1941 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto 108:34e6b704fe68 1942 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1943 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1944 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto 108:34e6b704fe68 1945 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto 108:34e6b704fe68 1946 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto 108:34e6b704fe68 1947 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto 108:34e6b704fe68 1948 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1949 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1950 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto 108:34e6b704fe68 1951 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto 108:34e6b704fe68 1952 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto 108:34e6b704fe68 1953 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto 108:34e6b704fe68 1954 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1955 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1956 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto 108:34e6b704fe68 1957 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto 108:34e6b704fe68 1958 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto 108:34e6b704fe68 1959 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto 108:34e6b704fe68 1960 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1961 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1962 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto 108:34e6b704fe68 1963 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto 108:34e6b704fe68 1964 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto 108:34e6b704fe68 1965 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto 108:34e6b704fe68 1966 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1967 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1968 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto 108:34e6b704fe68 1969 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto 108:34e6b704fe68 1970 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto 108:34e6b704fe68 1971 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto 108:34e6b704fe68 1972 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1973 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1974 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto 108:34e6b704fe68 1975 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto 108:34e6b704fe68 1976 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto 108:34e6b704fe68 1977 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto 108:34e6b704fe68 1978 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1979 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1980 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto 108:34e6b704fe68 1981 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto 108:34e6b704fe68 1982 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto 108:34e6b704fe68 1983 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto 108:34e6b704fe68 1984 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1985 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1986 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto 108:34e6b704fe68 1987 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto 108:34e6b704fe68 1988 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto 108:34e6b704fe68 1989 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto 108:34e6b704fe68 1990 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1991 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1992 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto 108:34e6b704fe68 1993 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto 108:34e6b704fe68 1994 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto 108:34e6b704fe68 1995 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto 108:34e6b704fe68 1996 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 1997 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 1998 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto 108:34e6b704fe68 1999 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto 108:34e6b704fe68 2000 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto 108:34e6b704fe68 2001 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto 108:34e6b704fe68 2002 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2003 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2004 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto 108:34e6b704fe68 2005 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto 108:34e6b704fe68 2006 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto 108:34e6b704fe68 2007 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto 108:34e6b704fe68 2008 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2009 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2010 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto 108:34e6b704fe68 2011 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto 108:34e6b704fe68 2012 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto 108:34e6b704fe68 2013 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto 108:34e6b704fe68 2014 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2015 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2016 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto 108:34e6b704fe68 2017 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto 108:34e6b704fe68 2018 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto 108:34e6b704fe68 2019 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto 108:34e6b704fe68 2020 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2021 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2022 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto 108:34e6b704fe68 2023 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto 108:34e6b704fe68 2024 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto 108:34e6b704fe68 2025 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto 108:34e6b704fe68 2026 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2027 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2028 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto 108:34e6b704fe68 2029 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto 108:34e6b704fe68 2030 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto 108:34e6b704fe68 2031 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto 108:34e6b704fe68 2032 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2033 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2034 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto 108:34e6b704fe68 2035 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto 108:34e6b704fe68 2036 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto 108:34e6b704fe68 2037 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto 108:34e6b704fe68 2038 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2039 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2040 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto 108:34e6b704fe68 2041 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto 108:34e6b704fe68 2042 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto 108:34e6b704fe68 2043 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto 108:34e6b704fe68 2044 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2045 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2046 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto 108:34e6b704fe68 2047 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto 108:34e6b704fe68 2048 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto 108:34e6b704fe68 2049 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto 108:34e6b704fe68 2050 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2051 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2052 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto 108:34e6b704fe68 2053 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto 108:34e6b704fe68 2054 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto 108:34e6b704fe68 2055 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto 108:34e6b704fe68 2056 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2057 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2058 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto 108:34e6b704fe68 2059 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto 108:34e6b704fe68 2060 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 108:34e6b704fe68 2061 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 108:34e6b704fe68 2062 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto 108:34e6b704fe68 2063 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto 108:34e6b704fe68 2064 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2065 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2066 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto 108:34e6b704fe68 2067 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto 108:34e6b704fe68 2068 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto 108:34e6b704fe68 2069 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto 108:34e6b704fe68 2070 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2071 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2072 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto 108:34e6b704fe68 2073 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto 108:34e6b704fe68 2074 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto 108:34e6b704fe68 2075 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto 108:34e6b704fe68 2076 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2077 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2078 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto 108:34e6b704fe68 2079 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto 108:34e6b704fe68 2080 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto 108:34e6b704fe68 2081 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto 108:34e6b704fe68 2082 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2083 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2084 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto 108:34e6b704fe68 2085 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto 108:34e6b704fe68 2086 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto 108:34e6b704fe68 2087 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto 108:34e6b704fe68 2088 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2089 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2090 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2091 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2092 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto 108:34e6b704fe68 2093 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto 108:34e6b704fe68 2094 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2095 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2096 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto 108:34e6b704fe68 2097 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto 108:34e6b704fe68 2098 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto 108:34e6b704fe68 2099 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto 108:34e6b704fe68 2100 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2101 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2102 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto 108:34e6b704fe68 2103 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto 108:34e6b704fe68 2104 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto 108:34e6b704fe68 2105 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto 108:34e6b704fe68 2106 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2107 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2108 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto 108:34e6b704fe68 2109 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto 108:34e6b704fe68 2110 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto 108:34e6b704fe68 2111 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto 108:34e6b704fe68 2112 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto 108:34e6b704fe68 2113 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto 108:34e6b704fe68 2114 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto 108:34e6b704fe68 2115 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto 108:34e6b704fe68 2116 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto 108:34e6b704fe68 2117 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto 108:34e6b704fe68 2118 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto 108:34e6b704fe68 2119 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto 108:34e6b704fe68 2120 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto 108:34e6b704fe68 2121 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto 108:34e6b704fe68 2122 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto 108:34e6b704fe68 2123 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto 108:34e6b704fe68 2124 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto 108:34e6b704fe68 2125 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto 108:34e6b704fe68 2126 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto 108:34e6b704fe68 2127 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto 108:34e6b704fe68 2128 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto 108:34e6b704fe68 2129 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto 108:34e6b704fe68 2130 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto 108:34e6b704fe68 2131 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto 108:34e6b704fe68 2132 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2133 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2134 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto 108:34e6b704fe68 2135 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto 108:34e6b704fe68 2136 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto 108:34e6b704fe68 2137 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto 108:34e6b704fe68 2138 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2139 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2140 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto 108:34e6b704fe68 2141 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto 108:34e6b704fe68 2142 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto 108:34e6b704fe68 2143 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto 108:34e6b704fe68 2144 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2145 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2146 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto 108:34e6b704fe68 2147 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto 108:34e6b704fe68 2148 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto 108:34e6b704fe68 2149 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto 108:34e6b704fe68 2150 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2151 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2152 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto 108:34e6b704fe68 2153 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto 108:34e6b704fe68 2154 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto 108:34e6b704fe68 2155 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto 108:34e6b704fe68 2156 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2157 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2158 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto 108:34e6b704fe68 2159 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto 108:34e6b704fe68 2160 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto 108:34e6b704fe68 2161 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto 108:34e6b704fe68 2162 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2163 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2164 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto 108:34e6b704fe68 2165 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto 108:34e6b704fe68 2166 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto 108:34e6b704fe68 2167 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto 108:34e6b704fe68 2168 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2169 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2170 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto 108:34e6b704fe68 2171 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto 108:34e6b704fe68 2172 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto 108:34e6b704fe68 2173 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto 108:34e6b704fe68 2174 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2175 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2176 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto 108:34e6b704fe68 2177 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto 108:34e6b704fe68 2178 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto 108:34e6b704fe68 2179 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto 108:34e6b704fe68 2180 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2181 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2182 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto 108:34e6b704fe68 2183 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto 108:34e6b704fe68 2184 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto 108:34e6b704fe68 2185 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto 108:34e6b704fe68 2186 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2187 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2188 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto 108:34e6b704fe68 2189 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto 108:34e6b704fe68 2190 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto 108:34e6b704fe68 2191 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto 108:34e6b704fe68 2192 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto 108:34e6b704fe68 2193 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto 108:34e6b704fe68 2194 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto 108:34e6b704fe68 2195 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto 108:34e6b704fe68 2196 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2197 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2198 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto 108:34e6b704fe68 2199 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto 108:34e6b704fe68 2200 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto 108:34e6b704fe68 2201 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto 108:34e6b704fe68 2202 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2203 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2204 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto 108:34e6b704fe68 2205 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto 108:34e6b704fe68 2206 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto 108:34e6b704fe68 2207 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto 108:34e6b704fe68 2208 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2209 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2210 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto 108:34e6b704fe68 2211 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto 108:34e6b704fe68 2212 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto 108:34e6b704fe68 2213 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto 108:34e6b704fe68 2214 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2215 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2216 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto 108:34e6b704fe68 2217 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto 108:34e6b704fe68 2218 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto 108:34e6b704fe68 2219 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto 108:34e6b704fe68 2220 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2221 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2222 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto 108:34e6b704fe68 2223 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto 108:34e6b704fe68 2224 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto 108:34e6b704fe68 2225 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto 108:34e6b704fe68 2226 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2227 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2228 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto 108:34e6b704fe68 2229 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto 108:34e6b704fe68 2230 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto 108:34e6b704fe68 2231 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto 108:34e6b704fe68 2232 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2233 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2234 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto 108:34e6b704fe68 2235 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto 108:34e6b704fe68 2236 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto 108:34e6b704fe68 2237 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto 108:34e6b704fe68 2238 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2239 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2240 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto 108:34e6b704fe68 2241 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto 108:34e6b704fe68 2242 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto 108:34e6b704fe68 2243 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto 108:34e6b704fe68 2244 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto 108:34e6b704fe68 2245 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto 108:34e6b704fe68 2246 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto 108:34e6b704fe68 2247 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto 108:34e6b704fe68 2248 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto 108:34e6b704fe68 2249 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto 108:34e6b704fe68 2250 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto 108:34e6b704fe68 2251 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto 108:34e6b704fe68 2252 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto 108:34e6b704fe68 2253 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2254 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2255 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto 108:34e6b704fe68 2256 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto 108:34e6b704fe68 2257 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto 108:34e6b704fe68 2258 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto 108:34e6b704fe68 2259 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto 108:34e6b704fe68 2260 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2261 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2262 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto 108:34e6b704fe68 2263 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto 108:34e6b704fe68 2264 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto 108:34e6b704fe68 2265 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto 108:34e6b704fe68 2266 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto 108:34e6b704fe68 2267 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto 108:34e6b704fe68 2268 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2269 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2270 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto 108:34e6b704fe68 2271 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto 108:34e6b704fe68 2272 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto 108:34e6b704fe68 2273 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto 108:34e6b704fe68 2274 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2275 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2276 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto 108:34e6b704fe68 2277 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto 108:34e6b704fe68 2278 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2279 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2280 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto 108:34e6b704fe68 2281 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto 108:34e6b704fe68 2282 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto 108:34e6b704fe68 2283 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto 108:34e6b704fe68 2284
Kojto 108:34e6b704fe68 2285 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 108:34e6b704fe68 2286 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 108:34e6b704fe68 2287 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2288 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2289 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto 108:34e6b704fe68 2290 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto 108:34e6b704fe68 2291 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto 108:34e6b704fe68 2292 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto 108:34e6b704fe68 2293 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2294 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2295 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2296 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2297 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2298 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2299 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2300 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2301 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto 108:34e6b704fe68 2302 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto 108:34e6b704fe68 2303 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto 108:34e6b704fe68 2304 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto 108:34e6b704fe68 2305 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto 108:34e6b704fe68 2306 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2307 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2308 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto 108:34e6b704fe68 2309 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto 108:34e6b704fe68 2310 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto 108:34e6b704fe68 2311 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto 108:34e6b704fe68 2312 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto 108:34e6b704fe68 2313 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2314 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2315 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto 108:34e6b704fe68 2316 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto 108:34e6b704fe68 2317 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto 108:34e6b704fe68 2318 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto 108:34e6b704fe68 2319 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2320 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2321 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto 108:34e6b704fe68 2322 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto 108:34e6b704fe68 2323 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto 108:34e6b704fe68 2324 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto 108:34e6b704fe68 2325 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2326 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2327 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2328 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2329 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2330 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2331 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2332 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2333 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2334 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2335 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2336 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2337 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2338 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto 108:34e6b704fe68 2339 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto 108:34e6b704fe68 2340 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2341 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2342 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto 108:34e6b704fe68 2343 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto 108:34e6b704fe68 2344 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto 108:34e6b704fe68 2345 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto 108:34e6b704fe68 2346 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto 108:34e6b704fe68 2347 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto 108:34e6b704fe68 2348 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2349 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2350 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto 108:34e6b704fe68 2351 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto 108:34e6b704fe68 2352 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto 108:34e6b704fe68 2353 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto 108:34e6b704fe68 2354 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2355 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2356 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto 108:34e6b704fe68 2357 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto 108:34e6b704fe68 2358 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto 108:34e6b704fe68 2359 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto 108:34e6b704fe68 2360 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2361 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2362 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto 108:34e6b704fe68 2363 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto 108:34e6b704fe68 2364 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto 108:34e6b704fe68 2365 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto 108:34e6b704fe68 2366 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2367 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2368 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto 108:34e6b704fe68 2369 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto 108:34e6b704fe68 2370 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto 108:34e6b704fe68 2371 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2372 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2373 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto 108:34e6b704fe68 2374 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto 108:34e6b704fe68 2375 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto 108:34e6b704fe68 2376 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto 108:34e6b704fe68 2377 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto 108:34e6b704fe68 2378 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto 108:34e6b704fe68 2379 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2380 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2381 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto 108:34e6b704fe68 2382 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto 108:34e6b704fe68 2383 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto 108:34e6b704fe68 2384 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto 108:34e6b704fe68 2385 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2386 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2387 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto 108:34e6b704fe68 2388 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto 108:34e6b704fe68 2389 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto 108:34e6b704fe68 2390 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto 108:34e6b704fe68 2391 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2392 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2393 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2394 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2395 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 108:34e6b704fe68 2396 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 108:34e6b704fe68 2397 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2398 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2399 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2400 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2401 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto 108:34e6b704fe68 2402 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto 108:34e6b704fe68 2403 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 108:34e6b704fe68 2404 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 122:f9eeca106725 2405 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2406 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2407 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto 108:34e6b704fe68 2408 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto 122:f9eeca106725 2409 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 122:f9eeca106725 2410 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2411 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2412 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2413 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2414 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2415 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2416 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2417 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2418 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2419 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto 122:f9eeca106725 2420 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto 122:f9eeca106725 2421 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2422 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2423 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 122:f9eeca106725 2424 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 122:f9eeca106725 2425 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2426 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2427 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto 122:f9eeca106725 2428 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto 122:f9eeca106725 2429 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto 108:34e6b704fe68 2430 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto 122:f9eeca106725 2431 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2432 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2433
Kojto 108:34e6b704fe68 2434 /* alias define maintained for legacy */
Kojto 108:34e6b704fe68 2435 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 108:34e6b704fe68 2436 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 108:34e6b704fe68 2437
Kojto 122:f9eeca106725 2438 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 122:f9eeca106725 2439 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 122:f9eeca106725 2440 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
Kojto 122:f9eeca106725 2441 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
Kojto 122:f9eeca106725 2442 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 122:f9eeca106725 2443 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 122:f9eeca106725 2444 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
Kojto 122:f9eeca106725 2445 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
Kojto 122:f9eeca106725 2446 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
Kojto 122:f9eeca106725 2447 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
Kojto 122:f9eeca106725 2448 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
Kojto 122:f9eeca106725 2449 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
Kojto 122:f9eeca106725 2450 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
Kojto 122:f9eeca106725 2451 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
Kojto 122:f9eeca106725 2452 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
Kojto 122:f9eeca106725 2453 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
Kojto 122:f9eeca106725 2454 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
Kojto 122:f9eeca106725 2455 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
Kojto 122:f9eeca106725 2456 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
Kojto 122:f9eeca106725 2457 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
Kojto 122:f9eeca106725 2458 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
Kojto 122:f9eeca106725 2459 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
Kojto 122:f9eeca106725 2460
Kojto 122:f9eeca106725 2461 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 122:f9eeca106725 2462 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 122:f9eeca106725 2463 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
Kojto 122:f9eeca106725 2464 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
Kojto 122:f9eeca106725 2465 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 122:f9eeca106725 2466 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 122:f9eeca106725 2467 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
Kojto 122:f9eeca106725 2468 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
Kojto 122:f9eeca106725 2469 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
Kojto 122:f9eeca106725 2470 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
Kojto 122:f9eeca106725 2471 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
Kojto 122:f9eeca106725 2472 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
Kojto 122:f9eeca106725 2473 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
Kojto 122:f9eeca106725 2474 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
Kojto 122:f9eeca106725 2475 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
Kojto 122:f9eeca106725 2476 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
Kojto 122:f9eeca106725 2477 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
Kojto 122:f9eeca106725 2478 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
Kojto 122:f9eeca106725 2479 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
Kojto 122:f9eeca106725 2480 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
Kojto 122:f9eeca106725 2481 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
Kojto 122:f9eeca106725 2482 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
Kojto 122:f9eeca106725 2483
Kojto 122:f9eeca106725 2484 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2485 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2486 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2487 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2488 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2489 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2490 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2491 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2492 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2493 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2494 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2495 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2496 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2497 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2498 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2499 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2500 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2501 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2502 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2503 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2504 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2505 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2506 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2507 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2508 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2509 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2510 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2511 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2512 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2513 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2514 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2515 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2516 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2517 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2518 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2519 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2520 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2521 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2522 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2523 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2524 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2525 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2526 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2527 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2528 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2529 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2530 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2531 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2532 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2533 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2534 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2535 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2536 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2537 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2538 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2539 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2540 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2541 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2542 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2543 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2544 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2545 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2546 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2547 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2548 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2549 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2550 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2551 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2552 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2553 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2554 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2555 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2556 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2557 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2558 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2559 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2560 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2561 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2562 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2563 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2564 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2565 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2566 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2567 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2568 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2569 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2570 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2571 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2572 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2573 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2574 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2575 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2576 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2577 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2578 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2579 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2580 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2581 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2582 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2583 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2584 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2585 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2586 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2587 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2588 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2589 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2590 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2591 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2592 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2593 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2594 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2595 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2596 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2597 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2598 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2599 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2600
Kojto 108:34e6b704fe68 2601 #if defined(STM32F4)
Kojto 108:34e6b704fe68 2602 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 108:34e6b704fe68 2603 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 108:34e6b704fe68 2604 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2605 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2606 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 108:34e6b704fe68 2607 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 122:f9eeca106725 2608 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2609 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
Kojto 108:34e6b704fe68 2610 #define Sdmmc1ClockSelection SdioClockSelection
Kojto 108:34e6b704fe68 2611 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto 108:34e6b704fe68 2612 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto 108:34e6b704fe68 2613 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto 108:34e6b704fe68 2614 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto 108:34e6b704fe68 2615 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto 108:34e6b704fe68 2616 #endif
Kojto 108:34e6b704fe68 2617
Kojto 108:34e6b704fe68 2618 #if defined(STM32F7) || defined(STM32L4)
Kojto 108:34e6b704fe68 2619 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto 108:34e6b704fe68 2620 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto 108:34e6b704fe68 2621 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto 108:34e6b704fe68 2622 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto 108:34e6b704fe68 2623 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto 108:34e6b704fe68 2624 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto 122:f9eeca106725 2625 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2626 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
Kojto 108:34e6b704fe68 2627 #define SdioClockSelection Sdmmc1ClockSelection
Kojto 108:34e6b704fe68 2628 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto 108:34e6b704fe68 2629 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto 108:34e6b704fe68 2630 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto 108:34e6b704fe68 2631 #endif
Kojto 108:34e6b704fe68 2632
Kojto 108:34e6b704fe68 2633 #if defined(STM32F7)
Kojto 122:f9eeca106725 2634 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto 108:34e6b704fe68 2635 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto 108:34e6b704fe68 2636 #endif
Kojto 108:34e6b704fe68 2637
Kojto 108:34e6b704fe68 2638 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto 108:34e6b704fe68 2639 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto 108:34e6b704fe68 2640
Kojto 122:f9eeca106725 2641 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto 122:f9eeca106725 2642
Kojto 122:f9eeca106725 2643 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto 122:f9eeca106725 2644 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto 122:f9eeca106725 2645 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto 122:f9eeca106725 2646 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto 122:f9eeca106725 2647 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
Kojto 122:f9eeca106725 2648
Kojto 122:f9eeca106725 2649 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
Kojto 122:f9eeca106725 2650
Kojto 122:f9eeca106725 2651 #if defined(STM32L0)
Kojto 122:f9eeca106725 2652 #define RCC_IT_LSECSS RCC_IT_CSSLSE
Kojto 122:f9eeca106725 2653 #define RCC_IT_CSS RCC_IT_CSSHSE
Kojto 122:f9eeca106725 2654 #endif
Kojto 108:34e6b704fe68 2655
Kojto 122:f9eeca106725 2656 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto 122:f9eeca106725 2657 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
Kojto 122:f9eeca106725 2658 #define RCC_MCO_NODIV RCC_MCODIV_1
Kojto 122:f9eeca106725 2659 #define RCC_MCO_DIV1 RCC_MCODIV_1
Kojto 122:f9eeca106725 2660 #define RCC_MCO_DIV2 RCC_MCODIV_2
Kojto 122:f9eeca106725 2661 #define RCC_MCO_DIV4 RCC_MCODIV_4
Kojto 122:f9eeca106725 2662 #define RCC_MCO_DIV8 RCC_MCODIV_8
Kojto 122:f9eeca106725 2663 #define RCC_MCO_DIV16 RCC_MCODIV_16
Kojto 122:f9eeca106725 2664 #define RCC_MCO_DIV32 RCC_MCODIV_32
Kojto 122:f9eeca106725 2665 #define RCC_MCO_DIV64 RCC_MCODIV_64
Kojto 122:f9eeca106725 2666 #define RCC_MCO_DIV128 RCC_MCODIV_128
Kojto 122:f9eeca106725 2667 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
Kojto 122:f9eeca106725 2668 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
Kojto 122:f9eeca106725 2669 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
Kojto 122:f9eeca106725 2670 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
Kojto 122:f9eeca106725 2671 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
Kojto 122:f9eeca106725 2672 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
Kojto 122:f9eeca106725 2673 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
Kojto 122:f9eeca106725 2674 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
Kojto 122:f9eeca106725 2675 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
Kojto 122:f9eeca106725 2676 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
Kojto 122:f9eeca106725 2677 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
Kojto 108:34e6b704fe68 2678
Kojto 122:f9eeca106725 2679 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto 122:f9eeca106725 2680
Kojto 122:f9eeca106725 2681 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
Kojto 122:f9eeca106725 2682 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
Kojto 122:f9eeca106725 2683 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
Kojto 122:f9eeca106725 2684 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
Kojto 122:f9eeca106725 2685 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
Kojto 122:f9eeca106725 2686 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
Kojto 122:f9eeca106725 2687 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
Kojto 122:f9eeca106725 2688 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
Kojto 108:34e6b704fe68 2689
Kojto 108:34e6b704fe68 2690 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto 122:f9eeca106725 2691 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
Kojto 122:f9eeca106725 2692 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
Kojto 122:f9eeca106725 2693 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
Kojto 122:f9eeca106725 2694 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
Kojto 108:34e6b704fe68 2695 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto 122:f9eeca106725 2696 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
Kojto 108:34e6b704fe68 2697 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto 122:f9eeca106725 2698 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
Kojto 108:34e6b704fe68 2699 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto 108:34e6b704fe68 2700 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto 108:34e6b704fe68 2701 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto 122:f9eeca106725 2702 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
Kojto 108:34e6b704fe68 2703 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto 122:f9eeca106725 2704 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
Kojto 122:f9eeca106725 2705 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
Kojto 108:34e6b704fe68 2706 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto 122:f9eeca106725 2707 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
Kojto 122:f9eeca106725 2708 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
Kojto 122:f9eeca106725 2709 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
Kojto 122:f9eeca106725 2710 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
Kojto 108:34e6b704fe68 2711 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto 108:34e6b704fe68 2712 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto 122:f9eeca106725 2713 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
Kojto 122:f9eeca106725 2714 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
Kojto 122:f9eeca106725 2715 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
Kojto 108:34e6b704fe68 2716 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto 108:34e6b704fe68 2717 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto 108:34e6b704fe68 2718 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto 108:34e6b704fe68 2719 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto 108:34e6b704fe68 2720 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto 108:34e6b704fe68 2721 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto 108:34e6b704fe68 2722
Kojto 108:34e6b704fe68 2723 #define CR_HSION_BB RCC_CR_HSION_BB
Kojto 108:34e6b704fe68 2724 #define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto 108:34e6b704fe68 2725 #define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto 108:34e6b704fe68 2726 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto 108:34e6b704fe68 2727 #define CR_MSION_BB RCC_CR_MSION_BB
Kojto 108:34e6b704fe68 2728 #define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto 108:34e6b704fe68 2729 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto 108:34e6b704fe68 2730 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto 108:34e6b704fe68 2731 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto 108:34e6b704fe68 2732 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto 108:34e6b704fe68 2733 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto 108:34e6b704fe68 2734 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto 108:34e6b704fe68 2735 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto 122:f9eeca106725 2736 #define CR_HSEON_BB RCC_CR_HSEON_BB
Kojto 122:f9eeca106725 2737 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
Kojto 108:34e6b704fe68 2738 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto 108:34e6b704fe68 2739 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto 108:34e6b704fe68 2740
Kojto 122:f9eeca106725 2741 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
Kojto 122:f9eeca106725 2742 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
Kojto 122:f9eeca106725 2743 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
Kojto 122:f9eeca106725 2744 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
Kojto 122:f9eeca106725 2745 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
Kojto 122:f9eeca106725 2746
Kojto 122:f9eeca106725 2747 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
Kojto 122:f9eeca106725 2748
Kojto 122:f9eeca106725 2749 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
Kojto 122:f9eeca106725 2750 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
Kojto 122:f9eeca106725 2751
Kojto 122:f9eeca106725 2752 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
Kojto 122:f9eeca106725 2753 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
Kojto 122:f9eeca106725 2754 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
Kojto 122:f9eeca106725 2755 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
Kojto 122:f9eeca106725 2756 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
Kojto 122:f9eeca106725 2757 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
Kojto 122:f9eeca106725 2758
Kojto 122:f9eeca106725 2759 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
Kojto 122:f9eeca106725 2760 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
Kojto 122:f9eeca106725 2761 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
Kojto 122:f9eeca106725 2762 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
Kojto 122:f9eeca106725 2763 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
Kojto 122:f9eeca106725 2764 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
Kojto 122:f9eeca106725 2765 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
Kojto 122:f9eeca106725 2766 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
Kojto 122:f9eeca106725 2767 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
Kojto 122:f9eeca106725 2768 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
Kojto 122:f9eeca106725 2769 #define DfsdmClockSelection Dfsdm1ClockSelection
Kojto 122:f9eeca106725 2770 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
Kojto 122:f9eeca106725 2771 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
Kojto 122:f9eeca106725 2772 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
Kojto 122:f9eeca106725 2773 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
Kojto 122:f9eeca106725 2774 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
Kojto 122:f9eeca106725 2775
Kojto 108:34e6b704fe68 2776 /**
Kojto 108:34e6b704fe68 2777 * @}
Kojto 108:34e6b704fe68 2778 */
Kojto 108:34e6b704fe68 2779
Kojto 108:34e6b704fe68 2780 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2781 * @{
Kojto 108:34e6b704fe68 2782 */
Kojto 108:34e6b704fe68 2783 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto 108:34e6b704fe68 2784
Kojto 108:34e6b704fe68 2785 /**
Kojto 108:34e6b704fe68 2786 * @}
Kojto 108:34e6b704fe68 2787 */
Kojto 108:34e6b704fe68 2788
Kojto 108:34e6b704fe68 2789 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2790 * @{
Kojto 108:34e6b704fe68 2791 */
Kojto 108:34e6b704fe68 2792
Kojto 108:34e6b704fe68 2793 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 2794 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 2795 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 2796
Kojto 108:34e6b704fe68 2797 #if defined (STM32F1)
Kojto 108:34e6b704fe68 2798 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto 108:34e6b704fe68 2799
Kojto 108:34e6b704fe68 2800 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto 108:34e6b704fe68 2801
Kojto 108:34e6b704fe68 2802 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto 108:34e6b704fe68 2803
Kojto 108:34e6b704fe68 2804 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto 108:34e6b704fe68 2805
Kojto 108:34e6b704fe68 2806 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto 108:34e6b704fe68 2807 #else
Kojto 108:34e6b704fe68 2808 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto 108:34e6b704fe68 2809 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto 108:34e6b704fe68 2810 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto 108:34e6b704fe68 2811 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto 108:34e6b704fe68 2812 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto 108:34e6b704fe68 2813 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto 108:34e6b704fe68 2814 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto 108:34e6b704fe68 2815 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto 108:34e6b704fe68 2816 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto 108:34e6b704fe68 2817 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto 108:34e6b704fe68 2818 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto 108:34e6b704fe68 2819 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto 108:34e6b704fe68 2820 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto 108:34e6b704fe68 2821 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto 108:34e6b704fe68 2822 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto 108:34e6b704fe68 2823 #endif /* STM32F1 */
Kojto 108:34e6b704fe68 2824
Kojto 108:34e6b704fe68 2825 #define IS_ALARM IS_RTC_ALARM
Kojto 108:34e6b704fe68 2826 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto 108:34e6b704fe68 2827 #define IS_TAMPER IS_RTC_TAMPER
Kojto 108:34e6b704fe68 2828 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto 108:34e6b704fe68 2829 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto 108:34e6b704fe68 2830 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto 108:34e6b704fe68 2831 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto 108:34e6b704fe68 2832 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto 108:34e6b704fe68 2833 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto 108:34e6b704fe68 2834 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto 108:34e6b704fe68 2835 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto 108:34e6b704fe68 2836 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto 108:34e6b704fe68 2837 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto 108:34e6b704fe68 2838 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto 108:34e6b704fe68 2839
Kojto 108:34e6b704fe68 2840 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto 108:34e6b704fe68 2841 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto 108:34e6b704fe68 2842
Kojto 108:34e6b704fe68 2843 /**
Kojto 108:34e6b704fe68 2844 * @}
Kojto 108:34e6b704fe68 2845 */
Kojto 108:34e6b704fe68 2846
Kojto 108:34e6b704fe68 2847 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2848 * @{
Kojto 108:34e6b704fe68 2849 */
Kojto 108:34e6b704fe68 2850
Kojto 108:34e6b704fe68 2851 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto 108:34e6b704fe68 2852 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto 108:34e6b704fe68 2853
Kojto 108:34e6b704fe68 2854 #if defined(STM32F4)
Kojto 108:34e6b704fe68 2855 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto 108:34e6b704fe68 2856 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto 108:34e6b704fe68 2857 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto 108:34e6b704fe68 2858 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto 108:34e6b704fe68 2859 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto 108:34e6b704fe68 2860 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto 108:34e6b704fe68 2861 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto 108:34e6b704fe68 2862 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto 108:34e6b704fe68 2863 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto 108:34e6b704fe68 2864 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto 108:34e6b704fe68 2865 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto 108:34e6b704fe68 2866 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto 108:34e6b704fe68 2867 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto 108:34e6b704fe68 2868 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto 108:34e6b704fe68 2869 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto 108:34e6b704fe68 2870 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto 108:34e6b704fe68 2871 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto 108:34e6b704fe68 2872 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto 108:34e6b704fe68 2873 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto 108:34e6b704fe68 2874 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto 108:34e6b704fe68 2875 /* alias CMSIS */
Kojto 108:34e6b704fe68 2876 #define SDMMC1_IRQn SDIO_IRQn
Kojto 108:34e6b704fe68 2877 #define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto 108:34e6b704fe68 2878 #endif
Kojto 108:34e6b704fe68 2879
Kojto 108:34e6b704fe68 2880 #if defined(STM32F7) || defined(STM32L4)
Kojto 108:34e6b704fe68 2881 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto 108:34e6b704fe68 2882 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto 108:34e6b704fe68 2883 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto 108:34e6b704fe68 2884 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto 108:34e6b704fe68 2885 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto 108:34e6b704fe68 2886 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto 108:34e6b704fe68 2887 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto 108:34e6b704fe68 2888 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto 108:34e6b704fe68 2889 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto 108:34e6b704fe68 2890 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto 108:34e6b704fe68 2891 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto 108:34e6b704fe68 2892 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto 108:34e6b704fe68 2893 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto 108:34e6b704fe68 2894 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto 108:34e6b704fe68 2895 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto 108:34e6b704fe68 2896 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto 108:34e6b704fe68 2897 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto 108:34e6b704fe68 2898 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto 108:34e6b704fe68 2899 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto 108:34e6b704fe68 2900 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto 108:34e6b704fe68 2901 /* alias CMSIS for compatibilities */
Kojto 108:34e6b704fe68 2902 #define SDIO_IRQn SDMMC1_IRQn
Kojto 108:34e6b704fe68 2903 #define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto 108:34e6b704fe68 2904 #endif
Kojto 108:34e6b704fe68 2905 /**
Kojto 108:34e6b704fe68 2906 * @}
Kojto 108:34e6b704fe68 2907 */
Kojto 108:34e6b704fe68 2908
Kojto 108:34e6b704fe68 2909 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2910 * @{
Kojto 108:34e6b704fe68 2911 */
Kojto 108:34e6b704fe68 2912
Kojto 108:34e6b704fe68 2913 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto 108:34e6b704fe68 2914 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto 108:34e6b704fe68 2915 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto 108:34e6b704fe68 2916 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto 108:34e6b704fe68 2917 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto 108:34e6b704fe68 2918 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto 108:34e6b704fe68 2919
Kojto 108:34e6b704fe68 2920 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2921 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2922
Kojto 108:34e6b704fe68 2923 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto 108:34e6b704fe68 2924
Kojto 108:34e6b704fe68 2925 /**
Kojto 108:34e6b704fe68 2926 * @}
Kojto 108:34e6b704fe68 2927 */
Kojto 108:34e6b704fe68 2928
Kojto 108:34e6b704fe68 2929 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2930 * @{
Kojto 108:34e6b704fe68 2931 */
Kojto 108:34e6b704fe68 2932 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto 108:34e6b704fe68 2933 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto 108:34e6b704fe68 2934 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto 108:34e6b704fe68 2935 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto 108:34e6b704fe68 2936 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto 108:34e6b704fe68 2937 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto 108:34e6b704fe68 2938 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto 108:34e6b704fe68 2939 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto 108:34e6b704fe68 2940 /**
Kojto 108:34e6b704fe68 2941 * @}
Kojto 108:34e6b704fe68 2942 */
Kojto 108:34e6b704fe68 2943
Kojto 108:34e6b704fe68 2944 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2945 * @{
Kojto 108:34e6b704fe68 2946 */
Kojto 108:34e6b704fe68 2947
Kojto 108:34e6b704fe68 2948 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto 108:34e6b704fe68 2949 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto 108:34e6b704fe68 2950 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto 108:34e6b704fe68 2951
Kojto 108:34e6b704fe68 2952 /**
Kojto 108:34e6b704fe68 2953 * @}
Kojto 108:34e6b704fe68 2954 */
Kojto 108:34e6b704fe68 2955
Kojto 108:34e6b704fe68 2956 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2957 * @{
Kojto 108:34e6b704fe68 2958 */
Kojto 108:34e6b704fe68 2959
Kojto 108:34e6b704fe68 2960 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2961 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 108:34e6b704fe68 2962 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2963 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 108:34e6b704fe68 2964
Kojto 108:34e6b704fe68 2965 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto 108:34e6b704fe68 2966
Kojto 108:34e6b704fe68 2967 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto 108:34e6b704fe68 2968 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto 108:34e6b704fe68 2969
Kojto 108:34e6b704fe68 2970 /**
Kojto 108:34e6b704fe68 2971 * @}
Kojto 108:34e6b704fe68 2972 */
Kojto 108:34e6b704fe68 2973
Kojto 108:34e6b704fe68 2974
Kojto 108:34e6b704fe68 2975 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2976 * @{
Kojto 108:34e6b704fe68 2977 */
Kojto 108:34e6b704fe68 2978
Kojto 108:34e6b704fe68 2979 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto 108:34e6b704fe68 2980 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto 108:34e6b704fe68 2981 #define __USART_ENABLE __HAL_USART_ENABLE
Kojto 108:34e6b704fe68 2982 #define __USART_DISABLE __HAL_USART_DISABLE
Kojto 108:34e6b704fe68 2983
Kojto 108:34e6b704fe68 2984 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2985 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 108:34e6b704fe68 2986
Kojto 108:34e6b704fe68 2987 /**
Kojto 108:34e6b704fe68 2988 * @}
Kojto 108:34e6b704fe68 2989 */
Kojto 108:34e6b704fe68 2990
Kojto 108:34e6b704fe68 2991 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 2992 * @{
Kojto 108:34e6b704fe68 2993 */
Kojto 108:34e6b704fe68 2994 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto 108:34e6b704fe68 2995
Kojto 108:34e6b704fe68 2996 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto 108:34e6b704fe68 2997 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto 108:34e6b704fe68 2998 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 108:34e6b704fe68 2999 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto 108:34e6b704fe68 3000
Kojto 108:34e6b704fe68 3001 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto 108:34e6b704fe68 3002 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto 108:34e6b704fe68 3003 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 108:34e6b704fe68 3004 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto 108:34e6b704fe68 3005
Kojto 108:34e6b704fe68 3006 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 3007 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 3008 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto 108:34e6b704fe68 3009 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 3010 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 108:34e6b704fe68 3011 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 3012 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 108:34e6b704fe68 3013
Kojto 108:34e6b704fe68 3014 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 3015 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 3016 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto 108:34e6b704fe68 3017 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 3018 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 108:34e6b704fe68 3019 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 3020 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 108:34e6b704fe68 3021 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 108:34e6b704fe68 3022
Kojto 108:34e6b704fe68 3023 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 3024 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 3025 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto 108:34e6b704fe68 3026 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 3027 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 108:34e6b704fe68 3028 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 108:34e6b704fe68 3029 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 108:34e6b704fe68 3030 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 108:34e6b704fe68 3031
Kojto 108:34e6b704fe68 3032 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto 108:34e6b704fe68 3033 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto 108:34e6b704fe68 3034
Kojto 108:34e6b704fe68 3035 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto 108:34e6b704fe68 3036 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto 108:34e6b704fe68 3037 /**
Kojto 108:34e6b704fe68 3038 * @}
Kojto 108:34e6b704fe68 3039 */
Kojto 108:34e6b704fe68 3040
Kojto 108:34e6b704fe68 3041 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 3042 * @{
Kojto 108:34e6b704fe68 3043 */
Kojto 108:34e6b704fe68 3044 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto 108:34e6b704fe68 3045 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto 108:34e6b704fe68 3046
Kojto 108:34e6b704fe68 3047 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 108:34e6b704fe68 3048 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto 108:34e6b704fe68 3049
Kojto 108:34e6b704fe68 3050 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 108:34e6b704fe68 3051
Kojto 108:34e6b704fe68 3052 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto 108:34e6b704fe68 3053 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto 108:34e6b704fe68 3054 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto 108:34e6b704fe68 3055 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto 108:34e6b704fe68 3056 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto 108:34e6b704fe68 3057 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto 108:34e6b704fe68 3058 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto 108:34e6b704fe68 3059 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto 108:34e6b704fe68 3060 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto 108:34e6b704fe68 3061 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto 108:34e6b704fe68 3062 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto 108:34e6b704fe68 3063 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto 108:34e6b704fe68 3064
Kojto 122:f9eeca106725 3065 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
Kojto 108:34e6b704fe68 3066 /**
Kojto 108:34e6b704fe68 3067 * @}
Kojto 108:34e6b704fe68 3068 */
Kojto 108:34e6b704fe68 3069
Kojto 108:34e6b704fe68 3070 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 3071 * @{
Kojto 108:34e6b704fe68 3072 */
Kojto 108:34e6b704fe68 3073
Kojto 108:34e6b704fe68 3074 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto 108:34e6b704fe68 3075 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto 108:34e6b704fe68 3076 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto 108:34e6b704fe68 3077 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto 108:34e6b704fe68 3078 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto 108:34e6b704fe68 3079 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto 108:34e6b704fe68 3080 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto 108:34e6b704fe68 3081
Kojto 108:34e6b704fe68 3082 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto 108:34e6b704fe68 3083 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto 108:34e6b704fe68 3084 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto 108:34e6b704fe68 3085 /**
Kojto 108:34e6b704fe68 3086 * @}
Kojto 108:34e6b704fe68 3087 */
Kojto 108:34e6b704fe68 3088
Kojto 108:34e6b704fe68 3089 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 3090 * @{
Kojto 108:34e6b704fe68 3091 */
Kojto 108:34e6b704fe68 3092 #define __HAL_LTDC_LAYER LTDC_LAYER
Kojto 108:34e6b704fe68 3093 /**
Kojto 108:34e6b704fe68 3094 * @}
Kojto 108:34e6b704fe68 3095 */
Kojto 108:34e6b704fe68 3096
Kojto 108:34e6b704fe68 3097 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 3098 * @{
Kojto 108:34e6b704fe68 3099 */
Kojto 108:34e6b704fe68 3100 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto 108:34e6b704fe68 3101 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto 108:34e6b704fe68 3102 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto 108:34e6b704fe68 3103 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto 108:34e6b704fe68 3104 #define SAI_STREOMODE SAI_STEREOMODE
Kojto 122:f9eeca106725 3105 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto 122:f9eeca106725 3106 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto 122:f9eeca106725 3107 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto 122:f9eeca106725 3108 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto 122:f9eeca106725 3109 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto 122:f9eeca106725 3110 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto 122:f9eeca106725 3111 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto 122:f9eeca106725 3112 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
Kojto 122:f9eeca106725 3113 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
Kojto 108:34e6b704fe68 3114 /**
Kojto 108:34e6b704fe68 3115 * @}
Kojto 108:34e6b704fe68 3116 */
Kojto 108:34e6b704fe68 3117
Kojto 108:34e6b704fe68 3118
Kojto 108:34e6b704fe68 3119 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto 108:34e6b704fe68 3120 * @{
Kojto 108:34e6b704fe68 3121 */
Kojto 108:34e6b704fe68 3122
Kojto 108:34e6b704fe68 3123 /**
Kojto 108:34e6b704fe68 3124 * @}
Kojto 108:34e6b704fe68 3125 */
Kojto 108:34e6b704fe68 3126
Kojto 108:34e6b704fe68 3127 #ifdef __cplusplus
Kojto 108:34e6b704fe68 3128 }
Kojto 108:34e6b704fe68 3129 #endif
Kojto 108:34e6b704fe68 3130
Kojto 108:34e6b704fe68 3131 #endif /* ___STM32_HAL_LEGACY */
Kojto 108:34e6b704fe68 3132
Kojto 108:34e6b704fe68 3133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 108:34e6b704fe68 3134