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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_MTS_MDOT_F411RE/stm32f411xe.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
106:ba1f97679dad 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f411xe.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.5.0
Kojto 122:f9eeca106725 6 * @date 22-April-2016
Kojto 93:e188a91d3eaa 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
Kojto 93:e188a91d3eaa 8 *
Kojto 93:e188a91d3eaa 9 * This file contains:
Kojto 93:e188a91d3eaa 10 * - Data structures and the address mapping for all peripherals
Kojto 122:f9eeca106725 11 * - peripherals registers declarations and bits definition
Kojto 122:f9eeca106725 12 * - Macros to access peripheral's registers hardware
Kojto 93:e188a91d3eaa 13 *
Kojto 93:e188a91d3eaa 14 ******************************************************************************
Kojto 93:e188a91d3eaa 15 * @attention
Kojto 93:e188a91d3eaa 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 18 *
Kojto 93:e188a91d3eaa 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 20 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 22 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 24 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 25 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 27 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 28 * without specific prior written permission.
Kojto 93:e188a91d3eaa 29 *
Kojto 93:e188a91d3eaa 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 40 *
Kojto 93:e188a91d3eaa 41 ******************************************************************************
Kojto 93:e188a91d3eaa 42 */
Kojto 93:e188a91d3eaa 43
Kojto 93:e188a91d3eaa 44 /** @addtogroup CMSIS
Kojto 93:e188a91d3eaa 45 * @{
Kojto 93:e188a91d3eaa 46 */
Kojto 93:e188a91d3eaa 47
Kojto 122:f9eeca106725 48 /** @addtogroup stm32f411xe
Kojto 93:e188a91d3eaa 49 * @{
Kojto 93:e188a91d3eaa 50 */
Kojto 93:e188a91d3eaa 51
Kojto 122:f9eeca106725 52 #ifndef __STM32F411xE_H
Kojto 122:f9eeca106725 53 #define __STM32F411xE_H
Kojto 93:e188a91d3eaa 54
Kojto 93:e188a91d3eaa 55 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 56 extern "C" {
Kojto 93:e188a91d3eaa 57 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59
Kojto 93:e188a91d3eaa 60 /** @addtogroup Configuration_section_for_CMSIS
Kojto 93:e188a91d3eaa 61 * @{
Kojto 93:e188a91d3eaa 62 */
Kojto 93:e188a91d3eaa 63
Kojto 93:e188a91d3eaa 64 /**
Kojto 93:e188a91d3eaa 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 93:e188a91d3eaa 66 */
Kojto 122:f9eeca106725 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
Kojto 122:f9eeca106725 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
Kojto 122:f9eeca106725 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 71 #ifndef __FPU_PRESENT
Kojto 122:f9eeca106725 72 #define __FPU_PRESENT 1U /*!< FPU present */
Kojto 122:f9eeca106725 73 #endif /* __FPU_PRESENT */
Kojto 93:e188a91d3eaa 74
Kojto 93:e188a91d3eaa 75 /**
Kojto 93:e188a91d3eaa 76 * @}
Kojto 93:e188a91d3eaa 77 */
Kojto 93:e188a91d3eaa 78
Kojto 93:e188a91d3eaa 79 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 93:e188a91d3eaa 80 * @{
Kojto 93:e188a91d3eaa 81 */
Kojto 93:e188a91d3eaa 82
Kojto 93:e188a91d3eaa 83 /**
Kojto 93:e188a91d3eaa 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 93:e188a91d3eaa 85 * in @ref Library_configuration_section
Kojto 93:e188a91d3eaa 86 */
Kojto 93:e188a91d3eaa 87 typedef enum
Kojto 93:e188a91d3eaa 88 {
Kojto 93:e188a91d3eaa 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 93:e188a91d3eaa 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 93:e188a91d3eaa 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 93:e188a91d3eaa 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 93:e188a91d3eaa 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 93:e188a91d3eaa 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 93:e188a91d3eaa 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 93:e188a91d3eaa 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 93:e188a91d3eaa 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 93:e188a91d3eaa 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 93:e188a91d3eaa 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 93:e188a91d3eaa 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 93:e188a91d3eaa 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 93:e188a91d3eaa 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 93:e188a91d3eaa 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 93:e188a91d3eaa 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 93:e188a91d3eaa 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 93:e188a91d3eaa 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 93:e188a91d3eaa 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 93:e188a91d3eaa 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 93:e188a91d3eaa 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 93:e188a91d3eaa 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 93:e188a91d3eaa 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 93:e188a91d3eaa 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 93:e188a91d3eaa 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 93:e188a91d3eaa 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 93:e188a91d3eaa 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 93:e188a91d3eaa 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 93:e188a91d3eaa 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 93:e188a91d3eaa 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 93:e188a91d3eaa 119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 93:e188a91d3eaa 120 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 93:e188a91d3eaa 121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 93:e188a91d3eaa 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 93:e188a91d3eaa 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 93:e188a91d3eaa 124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 93:e188a91d3eaa 125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 93:e188a91d3eaa 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 93:e188a91d3eaa 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 93:e188a91d3eaa 128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 93:e188a91d3eaa 129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 93:e188a91d3eaa 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 93:e188a91d3eaa 131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 93:e188a91d3eaa 132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 93:e188a91d3eaa 133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 93:e188a91d3eaa 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 93:e188a91d3eaa 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 93:e188a91d3eaa 136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 93:e188a91d3eaa 137 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 93:e188a91d3eaa 138 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 93:e188a91d3eaa 139 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 93:e188a91d3eaa 140 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 93:e188a91d3eaa 141 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 93:e188a91d3eaa 142 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 93:e188a91d3eaa 143 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 93:e188a91d3eaa 144 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 93:e188a91d3eaa 145 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 93:e188a91d3eaa 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 93:e188a91d3eaa 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 93:e188a91d3eaa 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 93:e188a91d3eaa 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 93:e188a91d3eaa 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 93:e188a91d3eaa 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 93:e188a91d3eaa 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 93:e188a91d3eaa 153 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 93:e188a91d3eaa 154 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 93:e188a91d3eaa 155 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
Kojto 93:e188a91d3eaa 156 } IRQn_Type;
Kojto 93:e188a91d3eaa 157
Kojto 93:e188a91d3eaa 158 /**
Kojto 93:e188a91d3eaa 159 * @}
Kojto 93:e188a91d3eaa 160 */
Kojto 93:e188a91d3eaa 161
Kojto 93:e188a91d3eaa 162 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 93:e188a91d3eaa 163 #include "system_stm32f4xx.h"
Kojto 93:e188a91d3eaa 164 #include <stdint.h>
Kojto 93:e188a91d3eaa 165
Kojto 93:e188a91d3eaa 166 /** @addtogroup Peripheral_registers_structures
Kojto 93:e188a91d3eaa 167 * @{
Kojto 93:e188a91d3eaa 168 */
Kojto 93:e188a91d3eaa 169
Kojto 93:e188a91d3eaa 170 /**
Kojto 93:e188a91d3eaa 171 * @brief Analog to Digital Converter
Kojto 93:e188a91d3eaa 172 */
Kojto 93:e188a91d3eaa 173
Kojto 93:e188a91d3eaa 174 typedef struct
Kojto 93:e188a91d3eaa 175 {
Kojto 93:e188a91d3eaa 176 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 178 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 179 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 180 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 181 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 182 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 183 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 184 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 185 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 186 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 187 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 188 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 189 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 190 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 93:e188a91d3eaa 191 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 192 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 193 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 194 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 195 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 196 } ADC_TypeDef;
Kojto 93:e188a91d3eaa 197
Kojto 93:e188a91d3eaa 198 typedef struct
Kojto 93:e188a91d3eaa 199 {
Kojto 93:e188a91d3eaa 200 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 93:e188a91d3eaa 201 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 93:e188a91d3eaa 202 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 93:e188a91d3eaa 203 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 93:e188a91d3eaa 204 } ADC_Common_TypeDef;
Kojto 93:e188a91d3eaa 205
Kojto 93:e188a91d3eaa 206 /**
Kojto 93:e188a91d3eaa 207 * @brief CRC calculation unit
Kojto 93:e188a91d3eaa 208 */
Kojto 93:e188a91d3eaa 209
Kojto 93:e188a91d3eaa 210 typedef struct
Kojto 93:e188a91d3eaa 211 {
Kojto 93:e188a91d3eaa 212 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 213 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 214 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 93:e188a91d3eaa 215 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 93:e188a91d3eaa 216 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 217 } CRC_TypeDef;
Kojto 93:e188a91d3eaa 218
Kojto 93:e188a91d3eaa 219 /**
Kojto 93:e188a91d3eaa 220 * @brief Debug MCU
Kojto 93:e188a91d3eaa 221 */
Kojto 93:e188a91d3eaa 222
Kojto 93:e188a91d3eaa 223 typedef struct
Kojto 93:e188a91d3eaa 224 {
Kojto 93:e188a91d3eaa 225 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 226 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 227 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 228 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 229 }DBGMCU_TypeDef;
Kojto 93:e188a91d3eaa 230
Kojto 93:e188a91d3eaa 231
Kojto 93:e188a91d3eaa 232 /**
Kojto 93:e188a91d3eaa 233 * @brief DMA Controller
Kojto 93:e188a91d3eaa 234 */
Kojto 93:e188a91d3eaa 235
Kojto 93:e188a91d3eaa 236 typedef struct
Kojto 93:e188a91d3eaa 237 {
Kojto 93:e188a91d3eaa 238 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 93:e188a91d3eaa 239 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 93:e188a91d3eaa 240 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 93:e188a91d3eaa 241 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 93:e188a91d3eaa 242 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 93:e188a91d3eaa 243 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 93:e188a91d3eaa 244 } DMA_Stream_TypeDef;
Kojto 93:e188a91d3eaa 245
Kojto 93:e188a91d3eaa 246 typedef struct
Kojto 93:e188a91d3eaa 247 {
Kojto 93:e188a91d3eaa 248 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 249 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 250 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 251 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 252 } DMA_TypeDef;
Kojto 93:e188a91d3eaa 253
Kojto 93:e188a91d3eaa 254
Kojto 93:e188a91d3eaa 255 /**
Kojto 93:e188a91d3eaa 256 * @brief External Interrupt/Event Controller
Kojto 93:e188a91d3eaa 257 */
Kojto 93:e188a91d3eaa 258
Kojto 93:e188a91d3eaa 259 typedef struct
Kojto 93:e188a91d3eaa 260 {
Kojto 93:e188a91d3eaa 261 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 262 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 263 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 264 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 265 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 266 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 267 } EXTI_TypeDef;
Kojto 93:e188a91d3eaa 268
Kojto 93:e188a91d3eaa 269 /**
Kojto 93:e188a91d3eaa 270 * @brief FLASH Registers
Kojto 93:e188a91d3eaa 271 */
Kojto 93:e188a91d3eaa 272
Kojto 93:e188a91d3eaa 273 typedef struct
Kojto 93:e188a91d3eaa 274 {
Kojto 93:e188a91d3eaa 275 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 276 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 277 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 278 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 279 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 280 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 93:e188a91d3eaa 281 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 282 } FLASH_TypeDef;
Kojto 93:e188a91d3eaa 283
Kojto 93:e188a91d3eaa 284 /**
Kojto 93:e188a91d3eaa 285 * @brief General Purpose I/O
Kojto 93:e188a91d3eaa 286 */
Kojto 93:e188a91d3eaa 287
Kojto 93:e188a91d3eaa 288 typedef struct
Kojto 93:e188a91d3eaa 289 {
Kojto 93:e188a91d3eaa 290 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 291 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 292 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 293 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 294 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 295 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 296 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 297 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 298 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 93:e188a91d3eaa 299 } GPIO_TypeDef;
Kojto 93:e188a91d3eaa 300
Kojto 93:e188a91d3eaa 301 /**
Kojto 93:e188a91d3eaa 302 * @brief System configuration controller
Kojto 93:e188a91d3eaa 303 */
Kojto 93:e188a91d3eaa 304
Kojto 93:e188a91d3eaa 305 typedef struct
Kojto 93:e188a91d3eaa 306 {
Kojto 93:e188a91d3eaa 307 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 308 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 309 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 93:e188a91d3eaa 310 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 93:e188a91d3eaa 311 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 312 } SYSCFG_TypeDef;
Kojto 93:e188a91d3eaa 313
Kojto 93:e188a91d3eaa 314 /**
Kojto 93:e188a91d3eaa 315 * @brief Inter-integrated Circuit Interface
Kojto 93:e188a91d3eaa 316 */
Kojto 93:e188a91d3eaa 317
Kojto 93:e188a91d3eaa 318 typedef struct
Kojto 93:e188a91d3eaa 319 {
Kojto 93:e188a91d3eaa 320 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 321 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 322 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 323 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 324 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 325 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 326 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 327 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 328 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 329 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 330 } I2C_TypeDef;
Kojto 93:e188a91d3eaa 331
Kojto 93:e188a91d3eaa 332 /**
Kojto 93:e188a91d3eaa 333 * @brief Independent WATCHDOG
Kojto 93:e188a91d3eaa 334 */
Kojto 93:e188a91d3eaa 335
Kojto 93:e188a91d3eaa 336 typedef struct
Kojto 93:e188a91d3eaa 337 {
Kojto 93:e188a91d3eaa 338 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 339 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 340 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 341 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 342 } IWDG_TypeDef;
Kojto 93:e188a91d3eaa 343
Kojto 93:e188a91d3eaa 344 /**
Kojto 93:e188a91d3eaa 345 * @brief Power Control
Kojto 93:e188a91d3eaa 346 */
Kojto 93:e188a91d3eaa 347
Kojto 93:e188a91d3eaa 348 typedef struct
Kojto 93:e188a91d3eaa 349 {
Kojto 93:e188a91d3eaa 350 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 351 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 352 } PWR_TypeDef;
Kojto 93:e188a91d3eaa 353
Kojto 93:e188a91d3eaa 354 /**
Kojto 93:e188a91d3eaa 355 * @brief Reset and Clock Control
Kojto 93:e188a91d3eaa 356 */
Kojto 93:e188a91d3eaa 357
Kojto 93:e188a91d3eaa 358 typedef struct
Kojto 93:e188a91d3eaa 359 {
Kojto 93:e188a91d3eaa 360 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 361 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 362 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 363 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 364 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 365 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 366 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 367 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 93:e188a91d3eaa 368 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 369 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 370 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 93:e188a91d3eaa 371 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 372 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 373 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 374 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 93:e188a91d3eaa 375 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 376 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 377 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 93:e188a91d3eaa 378 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 379 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 93:e188a91d3eaa 380 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 93:e188a91d3eaa 381 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 93:e188a91d3eaa 382 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 93:e188a91d3eaa 383 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 93:e188a91d3eaa 384 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 93:e188a91d3eaa 385 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 93:e188a91d3eaa 386 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 93:e188a91d3eaa 387 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 93:e188a91d3eaa 388 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 389 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 122:f9eeca106725 390 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
Kojto 122:f9eeca106725 391 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
Kojto 93:e188a91d3eaa 392 } RCC_TypeDef;
Kojto 93:e188a91d3eaa 393
Kojto 93:e188a91d3eaa 394 /**
Kojto 93:e188a91d3eaa 395 * @brief Real-Time Clock
Kojto 93:e188a91d3eaa 396 */
Kojto 93:e188a91d3eaa 397
Kojto 93:e188a91d3eaa 398 typedef struct
Kojto 93:e188a91d3eaa 399 {
Kojto 93:e188a91d3eaa 400 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 401 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 402 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 403 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 404 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 405 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 406 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 407 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 408 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 409 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 410 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 411 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 412 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 413 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 414 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 415 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 416 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 417 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 418 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 419 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 93:e188a91d3eaa 420 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 421 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 93:e188a91d3eaa 422 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 93:e188a91d3eaa 423 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 93:e188a91d3eaa 424 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 93:e188a91d3eaa 425 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 93:e188a91d3eaa 426 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 93:e188a91d3eaa 427 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 93:e188a91d3eaa 428 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 93:e188a91d3eaa 429 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 93:e188a91d3eaa 430 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 93:e188a91d3eaa 431 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 93:e188a91d3eaa 432 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 433 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 93:e188a91d3eaa 434 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 93:e188a91d3eaa 435 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 93:e188a91d3eaa 436 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 93:e188a91d3eaa 437 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 93:e188a91d3eaa 438 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 93:e188a91d3eaa 439 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 93:e188a91d3eaa 440 } RTC_TypeDef;
Kojto 93:e188a91d3eaa 441
Kojto 93:e188a91d3eaa 442
Kojto 93:e188a91d3eaa 443 /**
Kojto 93:e188a91d3eaa 444 * @brief SD host Interface
Kojto 93:e188a91d3eaa 445 */
Kojto 93:e188a91d3eaa 446
Kojto 93:e188a91d3eaa 447 typedef struct
Kojto 93:e188a91d3eaa 448 {
Kojto 93:e188a91d3eaa 449 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 450 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 451 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 452 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 453 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 454 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 455 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 456 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 457 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 458 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 459 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 460 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 461 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 462 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 463 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 464 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 465 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 93:e188a91d3eaa 466 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 467 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 93:e188a91d3eaa 468 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 469 } SDIO_TypeDef;
Kojto 93:e188a91d3eaa 470
Kojto 93:e188a91d3eaa 471 /**
Kojto 93:e188a91d3eaa 472 * @brief Serial Peripheral Interface
Kojto 93:e188a91d3eaa 473 */
Kojto 93:e188a91d3eaa 474
Kojto 93:e188a91d3eaa 475 typedef struct
Kojto 93:e188a91d3eaa 476 {
Kojto 93:e188a91d3eaa 477 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 93:e188a91d3eaa 478 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 479 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 480 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 481 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 93:e188a91d3eaa 482 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 93:e188a91d3eaa 483 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 93:e188a91d3eaa 484 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 485 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 486 } SPI_TypeDef;
Kojto 93:e188a91d3eaa 487
Kojto 93:e188a91d3eaa 488 /**
Kojto 93:e188a91d3eaa 489 * @brief TIM
Kojto 93:e188a91d3eaa 490 */
Kojto 93:e188a91d3eaa 491
Kojto 93:e188a91d3eaa 492 typedef struct
Kojto 93:e188a91d3eaa 493 {
Kojto 93:e188a91d3eaa 494 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 495 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 496 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 497 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 498 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 499 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 500 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 501 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 502 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 503 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 504 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 505 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 506 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 507 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 508 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 509 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 510 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 511 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 512 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 513 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 514 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 515 } TIM_TypeDef;
Kojto 93:e188a91d3eaa 516
Kojto 93:e188a91d3eaa 517 /**
Kojto 93:e188a91d3eaa 518 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 93:e188a91d3eaa 519 */
Kojto 93:e188a91d3eaa 520
Kojto 93:e188a91d3eaa 521 typedef struct
Kojto 93:e188a91d3eaa 522 {
Kojto 93:e188a91d3eaa 523 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 524 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 525 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 526 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 527 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 528 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 529 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 530 } USART_TypeDef;
Kojto 93:e188a91d3eaa 531
Kojto 93:e188a91d3eaa 532 /**
Kojto 93:e188a91d3eaa 533 * @brief Window WATCHDOG
Kojto 93:e188a91d3eaa 534 */
Kojto 93:e188a91d3eaa 535
Kojto 93:e188a91d3eaa 536 typedef struct
Kojto 93:e188a91d3eaa 537 {
Kojto 93:e188a91d3eaa 538 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 539 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 540 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 541 } WWDG_TypeDef;
Kojto 93:e188a91d3eaa 542
Kojto 93:e188a91d3eaa 543
Kojto 93:e188a91d3eaa 544 /**
Kojto 93:e188a91d3eaa 545 * @brief __USB_OTG_Core_register
Kojto 93:e188a91d3eaa 546 */
Kojto 93:e188a91d3eaa 547 typedef struct
Kojto 93:e188a91d3eaa 548 {
Kojto 93:e188a91d3eaa 549 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
Kojto 93:e188a91d3eaa 550 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
Kojto 93:e188a91d3eaa 551 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
Kojto 93:e188a91d3eaa 552 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
Kojto 93:e188a91d3eaa 553 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
Kojto 93:e188a91d3eaa 554 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
Kojto 93:e188a91d3eaa 555 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
Kojto 93:e188a91d3eaa 556 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
Kojto 93:e188a91d3eaa 557 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
Kojto 93:e188a91d3eaa 558 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
Kojto 93:e188a91d3eaa 559 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
Kojto 93:e188a91d3eaa 560 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
Kojto 93:e188a91d3eaa 561 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
Kojto 93:e188a91d3eaa 562 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
Kojto 93:e188a91d3eaa 563 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
Kojto 93:e188a91d3eaa 564 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
Kojto 93:e188a91d3eaa 565 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
Kojto 93:e188a91d3eaa 566 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 93:e188a91d3eaa 567 }
Kojto 93:e188a91d3eaa 568 USB_OTG_GlobalTypeDef;
Kojto 93:e188a91d3eaa 569
Kojto 93:e188a91d3eaa 570
Kojto 93:e188a91d3eaa 571
Kojto 93:e188a91d3eaa 572 /**
Kojto 93:e188a91d3eaa 573 * @brief __device_Registers
Kojto 93:e188a91d3eaa 574 */
Kojto 93:e188a91d3eaa 575 typedef struct
Kojto 93:e188a91d3eaa 576 {
Kojto 93:e188a91d3eaa 577 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
Kojto 93:e188a91d3eaa 578 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
Kojto 93:e188a91d3eaa 579 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
Kojto 93:e188a91d3eaa 580 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
Kojto 93:e188a91d3eaa 581 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
Kojto 93:e188a91d3eaa 582 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
Kojto 93:e188a91d3eaa 583 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
Kojto 93:e188a91d3eaa 584 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
Kojto 93:e188a91d3eaa 585 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
Kojto 93:e188a91d3eaa 586 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
Kojto 93:e188a91d3eaa 587 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
Kojto 93:e188a91d3eaa 588 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
Kojto 93:e188a91d3eaa 589 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
Kojto 93:e188a91d3eaa 590 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
Kojto 93:e188a91d3eaa 591 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
Kojto 93:e188a91d3eaa 592 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
Kojto 93:e188a91d3eaa 593 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
Kojto 93:e188a91d3eaa 594 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
Kojto 93:e188a91d3eaa 595 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
Kojto 93:e188a91d3eaa 596 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
Kojto 93:e188a91d3eaa 597 }
Kojto 93:e188a91d3eaa 598 USB_OTG_DeviceTypeDef;
Kojto 93:e188a91d3eaa 599
Kojto 93:e188a91d3eaa 600
Kojto 93:e188a91d3eaa 601 /**
Kojto 93:e188a91d3eaa 602 * @brief __IN_Endpoint-Specific_Register
Kojto 93:e188a91d3eaa 603 */
Kojto 93:e188a91d3eaa 604 typedef struct
Kojto 93:e188a91d3eaa 605 {
Kojto 93:e188a91d3eaa 606 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 93:e188a91d3eaa 607 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
Kojto 93:e188a91d3eaa 608 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 93:e188a91d3eaa 609 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 93:e188a91d3eaa 610 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 93:e188a91d3eaa 611 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 93:e188a91d3eaa 612 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 93:e188a91d3eaa 613 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 93:e188a91d3eaa 614 }
Kojto 93:e188a91d3eaa 615 USB_OTG_INEndpointTypeDef;
Kojto 93:e188a91d3eaa 616
Kojto 93:e188a91d3eaa 617
Kojto 93:e188a91d3eaa 618 /**
Kojto 93:e188a91d3eaa 619 * @brief __OUT_Endpoint-Specific_Registers
Kojto 93:e188a91d3eaa 620 */
Kojto 93:e188a91d3eaa 621 typedef struct
Kojto 93:e188a91d3eaa 622 {
Kojto 93:e188a91d3eaa 623 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Kojto 93:e188a91d3eaa 624 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Kojto 93:e188a91d3eaa 625 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Kojto 93:e188a91d3eaa 626 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Kojto 93:e188a91d3eaa 627 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Kojto 93:e188a91d3eaa 628 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
Kojto 93:e188a91d3eaa 629 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
Kojto 93:e188a91d3eaa 630 }
Kojto 93:e188a91d3eaa 631 USB_OTG_OUTEndpointTypeDef;
Kojto 93:e188a91d3eaa 632
Kojto 93:e188a91d3eaa 633
Kojto 93:e188a91d3eaa 634 /**
Kojto 93:e188a91d3eaa 635 * @brief __Host_Mode_Register_Structures
Kojto 93:e188a91d3eaa 636 */
Kojto 93:e188a91d3eaa 637 typedef struct
Kojto 93:e188a91d3eaa 638 {
Kojto 93:e188a91d3eaa 639 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Kojto 93:e188a91d3eaa 640 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Kojto 93:e188a91d3eaa 641 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Kojto 93:e188a91d3eaa 642 uint32_t Reserved40C; /* Reserved 40Ch*/
Kojto 93:e188a91d3eaa 643 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Kojto 93:e188a91d3eaa 644 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Kojto 93:e188a91d3eaa 645 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Kojto 93:e188a91d3eaa 646 }
Kojto 93:e188a91d3eaa 647 USB_OTG_HostTypeDef;
Kojto 93:e188a91d3eaa 648
Kojto 93:e188a91d3eaa 649
Kojto 93:e188a91d3eaa 650 /**
Kojto 93:e188a91d3eaa 651 * @brief __Host_Channel_Specific_Registers
Kojto 93:e188a91d3eaa 652 */
Kojto 93:e188a91d3eaa 653 typedef struct
Kojto 93:e188a91d3eaa 654 {
Kojto 93:e188a91d3eaa 655 __IO uint32_t HCCHAR;
Kojto 93:e188a91d3eaa 656 __IO uint32_t HCSPLT;
Kojto 93:e188a91d3eaa 657 __IO uint32_t HCINT;
Kojto 93:e188a91d3eaa 658 __IO uint32_t HCINTMSK;
Kojto 93:e188a91d3eaa 659 __IO uint32_t HCTSIZ;
Kojto 93:e188a91d3eaa 660 __IO uint32_t HCDMA;
Kojto 93:e188a91d3eaa 661 uint32_t Reserved[2];
Kojto 93:e188a91d3eaa 662 }
Kojto 93:e188a91d3eaa 663 USB_OTG_HostChannelTypeDef;
Kojto 93:e188a91d3eaa 664
Kojto 93:e188a91d3eaa 665
Kojto 93:e188a91d3eaa 666 /**
Kojto 93:e188a91d3eaa 667 * @brief Peripheral_memory_map
Kojto 93:e188a91d3eaa 668 */
Kojto 122:f9eeca106725 669 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 122:f9eeca106725 670 #define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
Kojto 122:f9eeca106725 671 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
Kojto 122:f9eeca106725 672 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 122:f9eeca106725 673 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 674 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
Kojto 122:f9eeca106725 675 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 676 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
Kojto 93:e188a91d3eaa 677
Kojto 93:e188a91d3eaa 678 /* Legacy defines */
Kojto 93:e188a91d3eaa 679 #define SRAM_BASE SRAM1_BASE
Kojto 93:e188a91d3eaa 680 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 93:e188a91d3eaa 681
Kojto 93:e188a91d3eaa 682
Kojto 93:e188a91d3eaa 683 /*!< Peripheral memory map */
Kojto 93:e188a91d3eaa 684 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 685 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 686 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 687 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
Kojto 93:e188a91d3eaa 688
Kojto 93:e188a91d3eaa 689 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 690 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 691 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 692 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 693 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 694 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 695 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 696 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 697 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 698 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 699 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 700 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 701 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 702 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 703 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 704 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 705 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto 93:e188a91d3eaa 706
Kojto 93:e188a91d3eaa 707 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 708 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 709 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 710 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 711 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 712 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto 122:f9eeca106725 713 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 714 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 715 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 716 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 717 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 718 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 719 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 720 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 721 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
Kojto 93:e188a91d3eaa 722
Kojto 93:e188a91d3eaa 723 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 724 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 725 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 726 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 727 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 728 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 729 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 730 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 731 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 732 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 733 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 734 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto 122:f9eeca106725 735 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto 122:f9eeca106725 736 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto 122:f9eeca106725 737 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto 122:f9eeca106725 738 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto 122:f9eeca106725 739 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto 122:f9eeca106725 740 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto 122:f9eeca106725 741 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto 122:f9eeca106725 742 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 743 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto 122:f9eeca106725 744 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto 122:f9eeca106725 745 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto 122:f9eeca106725 746 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto 122:f9eeca106725 747 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto 122:f9eeca106725 748 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto 122:f9eeca106725 749 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto 122:f9eeca106725 750 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
Kojto 93:e188a91d3eaa 751
Kojto 93:e188a91d3eaa 752 /* Debug MCU registers base address */
Kojto 122:f9eeca106725 753 #define DBGMCU_BASE 0xE0042000U
Kojto 93:e188a91d3eaa 754
Kojto 93:e188a91d3eaa 755 /*!< USB registers base address */
Kojto 122:f9eeca106725 756 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto 122:f9eeca106725 757
Kojto 122:f9eeca106725 758 #define USB_OTG_GLOBAL_BASE 0x000U
Kojto 122:f9eeca106725 759 #define USB_OTG_DEVICE_BASE 0x800U
Kojto 122:f9eeca106725 760 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto 122:f9eeca106725 761 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto 122:f9eeca106725 762 #define USB_OTG_EP_REG_SIZE 0x20U
Kojto 122:f9eeca106725 763 #define USB_OTG_HOST_BASE 0x400U
Kojto 122:f9eeca106725 764 #define USB_OTG_HOST_PORT_BASE 0x440U
Kojto 122:f9eeca106725 765 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto 122:f9eeca106725 766 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto 122:f9eeca106725 767 #define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto 122:f9eeca106725 768 #define USB_OTG_FIFO_BASE 0x1000U
Kojto 122:f9eeca106725 769 #define USB_OTG_FIFO_SIZE 0x1000U
Kojto 93:e188a91d3eaa 770
Kojto 93:e188a91d3eaa 771 /**
Kojto 93:e188a91d3eaa 772 * @}
Kojto 93:e188a91d3eaa 773 */
Kojto 93:e188a91d3eaa 774
Kojto 93:e188a91d3eaa 775 /** @addtogroup Peripheral_declaration
Kojto 93:e188a91d3eaa 776 * @{
Kojto 93:e188a91d3eaa 777 */
Kojto 93:e188a91d3eaa 778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 93:e188a91d3eaa 779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 93:e188a91d3eaa 780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 93:e188a91d3eaa 781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 93:e188a91d3eaa 782 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 93:e188a91d3eaa 783 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 93:e188a91d3eaa 784 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 93:e188a91d3eaa 785 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
Kojto 93:e188a91d3eaa 786 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 93:e188a91d3eaa 787 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 93:e188a91d3eaa 788 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
Kojto 93:e188a91d3eaa 789 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 93:e188a91d3eaa 790 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 93:e188a91d3eaa 791 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 93:e188a91d3eaa 792 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 93:e188a91d3eaa 793 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 93:e188a91d3eaa 794 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 93:e188a91d3eaa 795 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 93:e188a91d3eaa 796 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 93:e188a91d3eaa 797 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 93:e188a91d3eaa 798 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 93:e188a91d3eaa 799 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 93:e188a91d3eaa 800 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 93:e188a91d3eaa 801 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 93:e188a91d3eaa 802 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 93:e188a91d3eaa 803 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 93:e188a91d3eaa 804 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 93:e188a91d3eaa 805 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 93:e188a91d3eaa 806 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 93:e188a91d3eaa 807 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 93:e188a91d3eaa 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 93:e188a91d3eaa 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 93:e188a91d3eaa 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 93:e188a91d3eaa 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 93:e188a91d3eaa 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 93:e188a91d3eaa 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 93:e188a91d3eaa 814 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 93:e188a91d3eaa 815 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 93:e188a91d3eaa 816 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 93:e188a91d3eaa 817 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 93:e188a91d3eaa 818 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 93:e188a91d3eaa 819 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 93:e188a91d3eaa 820 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 93:e188a91d3eaa 821 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 93:e188a91d3eaa 822 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 93:e188a91d3eaa 823 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 93:e188a91d3eaa 824 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 93:e188a91d3eaa 825 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 93:e188a91d3eaa 826 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 93:e188a91d3eaa 827 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 93:e188a91d3eaa 828 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 93:e188a91d3eaa 829 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 93:e188a91d3eaa 830 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 93:e188a91d3eaa 831 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 93:e188a91d3eaa 832 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 93:e188a91d3eaa 833 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 93:e188a91d3eaa 834 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 93:e188a91d3eaa 835
Kojto 93:e188a91d3eaa 836 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 93:e188a91d3eaa 837
Kojto 93:e188a91d3eaa 838 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 93:e188a91d3eaa 839
Kojto 93:e188a91d3eaa 840 /**
Kojto 93:e188a91d3eaa 841 * @}
Kojto 93:e188a91d3eaa 842 */
Kojto 93:e188a91d3eaa 843
Kojto 93:e188a91d3eaa 844 /** @addtogroup Exported_constants
Kojto 93:e188a91d3eaa 845 * @{
Kojto 93:e188a91d3eaa 846 */
Kojto 93:e188a91d3eaa 847
Kojto 93:e188a91d3eaa 848 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 93:e188a91d3eaa 849 * @{
Kojto 93:e188a91d3eaa 850 */
Kojto 93:e188a91d3eaa 851
Kojto 93:e188a91d3eaa 852 /******************************************************************************/
Kojto 93:e188a91d3eaa 853 /* Peripheral Registers_Bits_Definition */
Kojto 93:e188a91d3eaa 854 /******************************************************************************/
Kojto 93:e188a91d3eaa 855
Kojto 93:e188a91d3eaa 856 /******************************************************************************/
Kojto 93:e188a91d3eaa 857 /* */
Kojto 93:e188a91d3eaa 858 /* Analog to Digital Converter */
Kojto 93:e188a91d3eaa 859 /* */
Kojto 93:e188a91d3eaa 860 /******************************************************************************/
Kojto 93:e188a91d3eaa 861 /******************** Bit definition for ADC_SR register ********************/
Kojto 122:f9eeca106725 862 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
Kojto 122:f9eeca106725 863 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
Kojto 122:f9eeca106725 864 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
Kojto 122:f9eeca106725 865 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
Kojto 122:f9eeca106725 866 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
Kojto 122:f9eeca106725 867 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
Kojto 93:e188a91d3eaa 868
Kojto 93:e188a91d3eaa 869 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 122:f9eeca106725 870 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 122:f9eeca106725 871 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 872 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 873 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 874 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 875 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 876 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
Kojto 122:f9eeca106725 877 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
Kojto 122:f9eeca106725 878 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
Kojto 122:f9eeca106725 879 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
Kojto 122:f9eeca106725 880 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
Kojto 122:f9eeca106725 881 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
Kojto 122:f9eeca106725 882 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
Kojto 122:f9eeca106725 883 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
Kojto 122:f9eeca106725 884 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 122:f9eeca106725 885 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 886 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 887 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 888 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
Kojto 122:f9eeca106725 889 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
Kojto 122:f9eeca106725 890 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
Kojto 122:f9eeca106725 891 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 892 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 893 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
Kojto 93:e188a91d3eaa 894
Kojto 93:e188a91d3eaa 895 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 122:f9eeca106725 896 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
Kojto 122:f9eeca106725 897 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
Kojto 122:f9eeca106725 898 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
Kojto 122:f9eeca106725 899 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
Kojto 122:f9eeca106725 900 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
Kojto 122:f9eeca106725 901 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
Kojto 122:f9eeca106725 902 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 122:f9eeca106725 903 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 904 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 905 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 906 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 907 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 122:f9eeca106725 908 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 909 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 910 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
Kojto 122:f9eeca106725 911 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 122:f9eeca106725 912 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 913 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 914 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 915 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 916 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 122:f9eeca106725 917 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 918 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 919 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
Kojto 93:e188a91d3eaa 920
Kojto 93:e188a91d3eaa 921 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 122:f9eeca106725 922 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 122:f9eeca106725 923 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 924 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 925 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 926 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 122:f9eeca106725 927 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 928 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 929 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 930 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 122:f9eeca106725 931 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 932 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 933 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 934 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 122:f9eeca106725 935 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 936 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 937 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 938 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 122:f9eeca106725 939 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 940 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 941 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 942 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 122:f9eeca106725 943 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 944 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 945 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 946 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 122:f9eeca106725 947 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 948 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 949 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 950 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 122:f9eeca106725 951 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 952 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 953 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 954 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 122:f9eeca106725 955 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 956 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 957 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
Kojto 93:e188a91d3eaa 958
Kojto 93:e188a91d3eaa 959 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 122:f9eeca106725 960 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 122:f9eeca106725 961 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 962 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 963 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 964 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 122:f9eeca106725 965 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 966 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 967 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 968 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 122:f9eeca106725 969 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 970 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 971 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 972 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 122:f9eeca106725 973 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 974 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 975 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 976 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 122:f9eeca106725 977 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 978 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 979 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 980 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 122:f9eeca106725 981 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 982 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 983 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 984 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 122:f9eeca106725 985 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 986 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 987 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 988 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 122:f9eeca106725 989 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 990 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 991 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 992 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 122:f9eeca106725 993 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 994 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 995 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 996 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 122:f9eeca106725 997 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 998 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 999 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1000
Kojto 93:e188a91d3eaa 1001 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 122:f9eeca106725 1002 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
Kojto 93:e188a91d3eaa 1003
Kojto 93:e188a91d3eaa 1004 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 122:f9eeca106725 1005 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
Kojto 93:e188a91d3eaa 1006
Kojto 93:e188a91d3eaa 1007 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 122:f9eeca106725 1008 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
Kojto 93:e188a91d3eaa 1009
Kojto 93:e188a91d3eaa 1010 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 122:f9eeca106725 1011 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
Kojto 93:e188a91d3eaa 1012
Kojto 93:e188a91d3eaa 1013 /******************* Bit definition for ADC_HTR register ********************/
Kojto 122:f9eeca106725 1014 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
Kojto 93:e188a91d3eaa 1015
Kojto 93:e188a91d3eaa 1016 /******************* Bit definition for ADC_LTR register ********************/
Kojto 122:f9eeca106725 1017 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
Kojto 93:e188a91d3eaa 1018
Kojto 93:e188a91d3eaa 1019 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 122:f9eeca106725 1020 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 122:f9eeca106725 1021 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1022 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1023 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1024 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1025 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1026 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 122:f9eeca106725 1027 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1028 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1029 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1030 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1031 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1032 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 122:f9eeca106725 1033 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1034 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1035 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1036 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1037 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1038 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 122:f9eeca106725 1039 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1040 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1041 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1042 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1043 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1044 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 122:f9eeca106725 1045 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1046 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1047 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1048 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1049
Kojto 93:e188a91d3eaa 1050 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 122:f9eeca106725 1051 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 122:f9eeca106725 1052 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1053 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1054 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1055 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1056 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1057 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 122:f9eeca106725 1058 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1059 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1060 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1061 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1062 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1063 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 122:f9eeca106725 1064 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1065 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1066 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1067 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1068 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1069 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 122:f9eeca106725 1070 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1071 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1072 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1073 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1074 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1075 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 122:f9eeca106725 1076 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1077 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1078 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1079 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1080 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1081 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 122:f9eeca106725 1082 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1083 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1084 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1085 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1086 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1087
Kojto 93:e188a91d3eaa 1088 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 122:f9eeca106725 1089 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 122:f9eeca106725 1090 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1091 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1092 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1093 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1094 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1095 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 122:f9eeca106725 1096 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1097 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1098 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1099 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1100 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1101 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 122:f9eeca106725 1102 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1103 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1104 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1105 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1106 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1107 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 122:f9eeca106725 1108 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1109 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1110 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1111 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1112 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1113 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 122:f9eeca106725 1114 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1115 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1116 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1117 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1118 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1119 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 122:f9eeca106725 1120 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1121 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1122 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1123 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1124 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1125
Kojto 93:e188a91d3eaa 1126 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 122:f9eeca106725 1127 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 122:f9eeca106725 1128 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1129 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1130 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1131 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1132 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1133 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 122:f9eeca106725 1134 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1135 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1136 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1137 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1138 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1139 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 122:f9eeca106725 1140 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1141 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1142 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1143 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1144 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1145 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 122:f9eeca106725 1146 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1147 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1148 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1149 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1150 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1151 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 122:f9eeca106725 1152 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1153 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1154
Kojto 93:e188a91d3eaa 1155 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 122:f9eeca106725 1156 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
Kojto 93:e188a91d3eaa 1157
Kojto 93:e188a91d3eaa 1158 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 122:f9eeca106725 1159 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
Kojto 93:e188a91d3eaa 1160
Kojto 93:e188a91d3eaa 1161 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 122:f9eeca106725 1162 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
Kojto 93:e188a91d3eaa 1163
Kojto 93:e188a91d3eaa 1164 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 122:f9eeca106725 1165 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
Kojto 93:e188a91d3eaa 1166
Kojto 93:e188a91d3eaa 1167 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1168 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
Kojto 122:f9eeca106725 1169 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
Kojto 93:e188a91d3eaa 1170
Kojto 93:e188a91d3eaa 1171 /******************* Bit definition for ADC_CSR register ********************/
Kojto 122:f9eeca106725 1172 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
Kojto 122:f9eeca106725 1173 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
Kojto 122:f9eeca106725 1174 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
Kojto 122:f9eeca106725 1175 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
Kojto 122:f9eeca106725 1176 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
Kojto 122:f9eeca106725 1177 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
Kojto 122:f9eeca106725 1178 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
Kojto 122:f9eeca106725 1179 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
Kojto 122:f9eeca106725 1180 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
Kojto 122:f9eeca106725 1181 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
Kojto 122:f9eeca106725 1182 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
Kojto 122:f9eeca106725 1183 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
Kojto 122:f9eeca106725 1184 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
Kojto 122:f9eeca106725 1185 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
Kojto 122:f9eeca106725 1186 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
Kojto 122:f9eeca106725 1187 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
Kojto 122:f9eeca106725 1188 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
Kojto 122:f9eeca106725 1189 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
Kojto 122:f9eeca106725 1190
Kojto 122:f9eeca106725 1191 /* Legacy defines */
Kojto 122:f9eeca106725 1192 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto 122:f9eeca106725 1193 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto 122:f9eeca106725 1194 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
Kojto 93:e188a91d3eaa 1195
Kojto 93:e188a91d3eaa 1196 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1197 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 122:f9eeca106725 1198 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1199 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1200 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1201 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1202 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1203 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 122:f9eeca106725 1204 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 1205 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 1206 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 1207 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 1208 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
Kojto 122:f9eeca106725 1209 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 122:f9eeca106725 1210 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1211 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1212 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 122:f9eeca106725 1213 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1214 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1215 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
Kojto 122:f9eeca106725 1216 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
Kojto 93:e188a91d3eaa 1217
Kojto 93:e188a91d3eaa 1218 /******************* Bit definition for ADC_CDR register ********************/
Kojto 122:f9eeca106725 1219 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
Kojto 122:f9eeca106725 1220 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
Kojto 93:e188a91d3eaa 1221
Kojto 93:e188a91d3eaa 1222 /******************************************************************************/
Kojto 93:e188a91d3eaa 1223 /* */
Kojto 93:e188a91d3eaa 1224 /* CRC calculation unit */
Kojto 93:e188a91d3eaa 1225 /* */
Kojto 93:e188a91d3eaa 1226 /******************************************************************************/
Kojto 93:e188a91d3eaa 1227 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 1228 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
Kojto 93:e188a91d3eaa 1229
Kojto 93:e188a91d3eaa 1230
Kojto 93:e188a91d3eaa 1231 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 1232 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
Kojto 93:e188a91d3eaa 1233
Kojto 93:e188a91d3eaa 1234
Kojto 93:e188a91d3eaa 1235 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 1236 #define CRC_CR_RESET 0x01U /*!< RESET bit */
Kojto 93:e188a91d3eaa 1237
Kojto 93:e188a91d3eaa 1238 /******************************************************************************/
Kojto 93:e188a91d3eaa 1239 /* */
Kojto 93:e188a91d3eaa 1240 /* Debug MCU */
Kojto 93:e188a91d3eaa 1241 /* */
Kojto 93:e188a91d3eaa 1242 /******************************************************************************/
Kojto 93:e188a91d3eaa 1243
Kojto 93:e188a91d3eaa 1244 /******************************************************************************/
Kojto 93:e188a91d3eaa 1245 /* */
Kojto 93:e188a91d3eaa 1246 /* DMA Controller */
Kojto 93:e188a91d3eaa 1247 /* */
Kojto 93:e188a91d3eaa 1248 /******************************************************************************/
Kojto 122:f9eeca106725 1249 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 122:f9eeca106725 1250 #define DMA_SxCR_CHSEL 0x0E000000U
Kojto 122:f9eeca106725 1251 #define DMA_SxCR_CHSEL_0 0x02000000U
Kojto 122:f9eeca106725 1252 #define DMA_SxCR_CHSEL_1 0x04000000U
Kojto 122:f9eeca106725 1253 #define DMA_SxCR_CHSEL_2 0x08000000U
Kojto 122:f9eeca106725 1254 #define DMA_SxCR_MBURST 0x01800000U
Kojto 122:f9eeca106725 1255 #define DMA_SxCR_MBURST_0 0x00800000U
Kojto 122:f9eeca106725 1256 #define DMA_SxCR_MBURST_1 0x01000000U
Kojto 122:f9eeca106725 1257 #define DMA_SxCR_PBURST 0x00600000U
Kojto 122:f9eeca106725 1258 #define DMA_SxCR_PBURST_0 0x00200000U
Kojto 122:f9eeca106725 1259 #define DMA_SxCR_PBURST_1 0x00400000U
Kojto 122:f9eeca106725 1260 #define DMA_SxCR_CT 0x00080000U
Kojto 122:f9eeca106725 1261 #define DMA_SxCR_DBM 0x00040000U
Kojto 122:f9eeca106725 1262 #define DMA_SxCR_PL 0x00030000U
Kojto 122:f9eeca106725 1263 #define DMA_SxCR_PL_0 0x00010000U
Kojto 122:f9eeca106725 1264 #define DMA_SxCR_PL_1 0x00020000U
Kojto 122:f9eeca106725 1265 #define DMA_SxCR_PINCOS 0x00008000U
Kojto 122:f9eeca106725 1266 #define DMA_SxCR_MSIZE 0x00006000U
Kojto 122:f9eeca106725 1267 #define DMA_SxCR_MSIZE_0 0x00002000U
Kojto 122:f9eeca106725 1268 #define DMA_SxCR_MSIZE_1 0x00004000U
Kojto 122:f9eeca106725 1269 #define DMA_SxCR_PSIZE 0x00001800U
Kojto 122:f9eeca106725 1270 #define DMA_SxCR_PSIZE_0 0x00000800U
Kojto 122:f9eeca106725 1271 #define DMA_SxCR_PSIZE_1 0x00001000U
Kojto 122:f9eeca106725 1272 #define DMA_SxCR_MINC 0x00000400U
Kojto 122:f9eeca106725 1273 #define DMA_SxCR_PINC 0x00000200U
Kojto 122:f9eeca106725 1274 #define DMA_SxCR_CIRC 0x00000100U
Kojto 122:f9eeca106725 1275 #define DMA_SxCR_DIR 0x000000C0U
Kojto 122:f9eeca106725 1276 #define DMA_SxCR_DIR_0 0x00000040U
Kojto 122:f9eeca106725 1277 #define DMA_SxCR_DIR_1 0x00000080U
Kojto 122:f9eeca106725 1278 #define DMA_SxCR_PFCTRL 0x00000020U
Kojto 122:f9eeca106725 1279 #define DMA_SxCR_TCIE 0x00000010U
Kojto 122:f9eeca106725 1280 #define DMA_SxCR_HTIE 0x00000008U
Kojto 122:f9eeca106725 1281 #define DMA_SxCR_TEIE 0x00000004U
Kojto 122:f9eeca106725 1282 #define DMA_SxCR_DMEIE 0x00000002U
Kojto 122:f9eeca106725 1283 #define DMA_SxCR_EN 0x00000001U
Kojto 122:f9eeca106725 1284
Kojto 122:f9eeca106725 1285 /* Legacy defines */
Kojto 122:f9eeca106725 1286 #define DMA_SxCR_ACK 0x00100000U
Kojto 93:e188a91d3eaa 1287
Kojto 93:e188a91d3eaa 1288 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 122:f9eeca106725 1289 #define DMA_SxNDT 0x0000FFFFU
Kojto 122:f9eeca106725 1290 #define DMA_SxNDT_0 0x00000001U
Kojto 122:f9eeca106725 1291 #define DMA_SxNDT_1 0x00000002U
Kojto 122:f9eeca106725 1292 #define DMA_SxNDT_2 0x00000004U
Kojto 122:f9eeca106725 1293 #define DMA_SxNDT_3 0x00000008U
Kojto 122:f9eeca106725 1294 #define DMA_SxNDT_4 0x00000010U
Kojto 122:f9eeca106725 1295 #define DMA_SxNDT_5 0x00000020U
Kojto 122:f9eeca106725 1296 #define DMA_SxNDT_6 0x00000040U
Kojto 122:f9eeca106725 1297 #define DMA_SxNDT_7 0x00000080U
Kojto 122:f9eeca106725 1298 #define DMA_SxNDT_8 0x00000100U
Kojto 122:f9eeca106725 1299 #define DMA_SxNDT_9 0x00000200U
Kojto 122:f9eeca106725 1300 #define DMA_SxNDT_10 0x00000400U
Kojto 122:f9eeca106725 1301 #define DMA_SxNDT_11 0x00000800U
Kojto 122:f9eeca106725 1302 #define DMA_SxNDT_12 0x00001000U
Kojto 122:f9eeca106725 1303 #define DMA_SxNDT_13 0x00002000U
Kojto 122:f9eeca106725 1304 #define DMA_SxNDT_14 0x00004000U
Kojto 122:f9eeca106725 1305 #define DMA_SxNDT_15 0x00008000U
Kojto 93:e188a91d3eaa 1306
Kojto 93:e188a91d3eaa 1307 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 122:f9eeca106725 1308 #define DMA_SxFCR_FEIE 0x00000080U
Kojto 122:f9eeca106725 1309 #define DMA_SxFCR_FS 0x00000038U
Kojto 122:f9eeca106725 1310 #define DMA_SxFCR_FS_0 0x00000008U
Kojto 122:f9eeca106725 1311 #define DMA_SxFCR_FS_1 0x00000010U
Kojto 122:f9eeca106725 1312 #define DMA_SxFCR_FS_2 0x00000020U
Kojto 122:f9eeca106725 1313 #define DMA_SxFCR_DMDIS 0x00000004U
Kojto 122:f9eeca106725 1314 #define DMA_SxFCR_FTH 0x00000003U
Kojto 122:f9eeca106725 1315 #define DMA_SxFCR_FTH_0 0x00000001U
Kojto 122:f9eeca106725 1316 #define DMA_SxFCR_FTH_1 0x00000002U
Kojto 93:e188a91d3eaa 1317
Kojto 93:e188a91d3eaa 1318 /******************** Bits definition for DMA_LISR register *****************/
Kojto 122:f9eeca106725 1319 #define DMA_LISR_TCIF3 0x08000000U
Kojto 122:f9eeca106725 1320 #define DMA_LISR_HTIF3 0x04000000U
Kojto 122:f9eeca106725 1321 #define DMA_LISR_TEIF3 0x02000000U
Kojto 122:f9eeca106725 1322 #define DMA_LISR_DMEIF3 0x01000000U
Kojto 122:f9eeca106725 1323 #define DMA_LISR_FEIF3 0x00400000U
Kojto 122:f9eeca106725 1324 #define DMA_LISR_TCIF2 0x00200000U
Kojto 122:f9eeca106725 1325 #define DMA_LISR_HTIF2 0x00100000U
Kojto 122:f9eeca106725 1326 #define DMA_LISR_TEIF2 0x00080000U
Kojto 122:f9eeca106725 1327 #define DMA_LISR_DMEIF2 0x00040000U
Kojto 122:f9eeca106725 1328 #define DMA_LISR_FEIF2 0x00010000U
Kojto 122:f9eeca106725 1329 #define DMA_LISR_TCIF1 0x00000800U
Kojto 122:f9eeca106725 1330 #define DMA_LISR_HTIF1 0x00000400U
Kojto 122:f9eeca106725 1331 #define DMA_LISR_TEIF1 0x00000200U
Kojto 122:f9eeca106725 1332 #define DMA_LISR_DMEIF1 0x00000100U
Kojto 122:f9eeca106725 1333 #define DMA_LISR_FEIF1 0x00000040U
Kojto 122:f9eeca106725 1334 #define DMA_LISR_TCIF0 0x00000020U
Kojto 122:f9eeca106725 1335 #define DMA_LISR_HTIF0 0x00000010U
Kojto 122:f9eeca106725 1336 #define DMA_LISR_TEIF0 0x00000008U
Kojto 122:f9eeca106725 1337 #define DMA_LISR_DMEIF0 0x00000004U
Kojto 122:f9eeca106725 1338 #define DMA_LISR_FEIF0 0x00000001U
Kojto 93:e188a91d3eaa 1339
Kojto 93:e188a91d3eaa 1340 /******************** Bits definition for DMA_HISR register *****************/
Kojto 122:f9eeca106725 1341 #define DMA_HISR_TCIF7 0x08000000U
Kojto 122:f9eeca106725 1342 #define DMA_HISR_HTIF7 0x04000000U
Kojto 122:f9eeca106725 1343 #define DMA_HISR_TEIF7 0x02000000U
Kojto 122:f9eeca106725 1344 #define DMA_HISR_DMEIF7 0x01000000U
Kojto 122:f9eeca106725 1345 #define DMA_HISR_FEIF7 0x00400000U
Kojto 122:f9eeca106725 1346 #define DMA_HISR_TCIF6 0x00200000U
Kojto 122:f9eeca106725 1347 #define DMA_HISR_HTIF6 0x00100000U
Kojto 122:f9eeca106725 1348 #define DMA_HISR_TEIF6 0x00080000U
Kojto 122:f9eeca106725 1349 #define DMA_HISR_DMEIF6 0x00040000U
Kojto 122:f9eeca106725 1350 #define DMA_HISR_FEIF6 0x00010000U
Kojto 122:f9eeca106725 1351 #define DMA_HISR_TCIF5 0x00000800U
Kojto 122:f9eeca106725 1352 #define DMA_HISR_HTIF5 0x00000400U
Kojto 122:f9eeca106725 1353 #define DMA_HISR_TEIF5 0x00000200U
Kojto 122:f9eeca106725 1354 #define DMA_HISR_DMEIF5 0x00000100U
Kojto 122:f9eeca106725 1355 #define DMA_HISR_FEIF5 0x00000040U
Kojto 122:f9eeca106725 1356 #define DMA_HISR_TCIF4 0x00000020U
Kojto 122:f9eeca106725 1357 #define DMA_HISR_HTIF4 0x00000010U
Kojto 122:f9eeca106725 1358 #define DMA_HISR_TEIF4 0x00000008U
Kojto 122:f9eeca106725 1359 #define DMA_HISR_DMEIF4 0x00000004U
Kojto 122:f9eeca106725 1360 #define DMA_HISR_FEIF4 0x00000001U
Kojto 93:e188a91d3eaa 1361
Kojto 93:e188a91d3eaa 1362 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 122:f9eeca106725 1363 #define DMA_LIFCR_CTCIF3 0x08000000U
Kojto 122:f9eeca106725 1364 #define DMA_LIFCR_CHTIF3 0x04000000U
Kojto 122:f9eeca106725 1365 #define DMA_LIFCR_CTEIF3 0x02000000U
Kojto 122:f9eeca106725 1366 #define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto 122:f9eeca106725 1367 #define DMA_LIFCR_CFEIF3 0x00400000U
Kojto 122:f9eeca106725 1368 #define DMA_LIFCR_CTCIF2 0x00200000U
Kojto 122:f9eeca106725 1369 #define DMA_LIFCR_CHTIF2 0x00100000U
Kojto 122:f9eeca106725 1370 #define DMA_LIFCR_CTEIF2 0x00080000U
Kojto 122:f9eeca106725 1371 #define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto 122:f9eeca106725 1372 #define DMA_LIFCR_CFEIF2 0x00010000U
Kojto 122:f9eeca106725 1373 #define DMA_LIFCR_CTCIF1 0x00000800U
Kojto 122:f9eeca106725 1374 #define DMA_LIFCR_CHTIF1 0x00000400U
Kojto 122:f9eeca106725 1375 #define DMA_LIFCR_CTEIF1 0x00000200U
Kojto 122:f9eeca106725 1376 #define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto 122:f9eeca106725 1377 #define DMA_LIFCR_CFEIF1 0x00000040U
Kojto 122:f9eeca106725 1378 #define DMA_LIFCR_CTCIF0 0x00000020U
Kojto 122:f9eeca106725 1379 #define DMA_LIFCR_CHTIF0 0x00000010U
Kojto 122:f9eeca106725 1380 #define DMA_LIFCR_CTEIF0 0x00000008U
Kojto 122:f9eeca106725 1381 #define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto 122:f9eeca106725 1382 #define DMA_LIFCR_CFEIF0 0x00000001U
Kojto 93:e188a91d3eaa 1383
Kojto 93:e188a91d3eaa 1384 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 122:f9eeca106725 1385 #define DMA_HIFCR_CTCIF7 0x08000000U
Kojto 122:f9eeca106725 1386 #define DMA_HIFCR_CHTIF7 0x04000000U
Kojto 122:f9eeca106725 1387 #define DMA_HIFCR_CTEIF7 0x02000000U
Kojto 122:f9eeca106725 1388 #define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto 122:f9eeca106725 1389 #define DMA_HIFCR_CFEIF7 0x00400000U
Kojto 122:f9eeca106725 1390 #define DMA_HIFCR_CTCIF6 0x00200000U
Kojto 122:f9eeca106725 1391 #define DMA_HIFCR_CHTIF6 0x00100000U
Kojto 122:f9eeca106725 1392 #define DMA_HIFCR_CTEIF6 0x00080000U
Kojto 122:f9eeca106725 1393 #define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto 122:f9eeca106725 1394 #define DMA_HIFCR_CFEIF6 0x00010000U
Kojto 122:f9eeca106725 1395 #define DMA_HIFCR_CTCIF5 0x00000800U
Kojto 122:f9eeca106725 1396 #define DMA_HIFCR_CHTIF5 0x00000400U
Kojto 122:f9eeca106725 1397 #define DMA_HIFCR_CTEIF5 0x00000200U
Kojto 122:f9eeca106725 1398 #define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto 122:f9eeca106725 1399 #define DMA_HIFCR_CFEIF5 0x00000040U
Kojto 122:f9eeca106725 1400 #define DMA_HIFCR_CTCIF4 0x00000020U
Kojto 122:f9eeca106725 1401 #define DMA_HIFCR_CHTIF4 0x00000010U
Kojto 122:f9eeca106725 1402 #define DMA_HIFCR_CTEIF4 0x00000008U
Kojto 122:f9eeca106725 1403 #define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto 122:f9eeca106725 1404 #define DMA_HIFCR_CFEIF4 0x00000001U
Kojto 93:e188a91d3eaa 1405
Kojto 93:e188a91d3eaa 1406
Kojto 93:e188a91d3eaa 1407 /******************************************************************************/
Kojto 93:e188a91d3eaa 1408 /* */
Kojto 93:e188a91d3eaa 1409 /* External Interrupt/Event Controller */
Kojto 93:e188a91d3eaa 1410 /* */
Kojto 93:e188a91d3eaa 1411 /******************************************************************************/
Kojto 93:e188a91d3eaa 1412 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 1413 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 1414 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 1415 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 1416 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 1417 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 1418 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 1419 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 1420 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 1421 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 1422 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 1423 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 1424 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 1425 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 1426 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 1427 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 1428 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 1429 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 1430 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 1431 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 1432 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 1433 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 1434 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 1435 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
Kojto 93:e188a91d3eaa 1436
Kojto 93:e188a91d3eaa 1437 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 1438 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 1439 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 1440 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 1441 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 1442 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 1443 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 1444 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 1445 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 1446 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 1447 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 1448 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 1449 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 1450 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 1451 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 1452 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 1453 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 1454 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 1455 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 1456 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 1457 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 1458 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 1459 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 1460 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
Kojto 93:e188a91d3eaa 1461
Kojto 93:e188a91d3eaa 1462 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 1463 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1464 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1465 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1466 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1467 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1468 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1469 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1470 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1471 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1472 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1473 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1474 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1475 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1476 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1477 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1478 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1479 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1480 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1481 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 1482 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1483 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 1484 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 1485 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 1486
Kojto 93:e188a91d3eaa 1487 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 1488 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1489 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1490 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1491 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1492 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1493 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1494 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1495 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1496 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1497 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1498 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1499 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1500 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1501 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1502 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1503 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1504 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1505 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1506 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 1507 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1508 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 1509 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 1510 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 1511
Kojto 93:e188a91d3eaa 1512 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 1513 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 1514 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 1515 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 1516 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 1517 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 1518 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 1519 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 1520 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 1521 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 1522 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 1523 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 1524 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 1525 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 1526 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 1527 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 1528 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 1529 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 1530 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 1531 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 1532 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 1533 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 1534 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 1535 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
Kojto 93:e188a91d3eaa 1536
Kojto 93:e188a91d3eaa 1537 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 1538 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 1539 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 1540 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 1541 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 1542 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 1543 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 1544 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 1545 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 1546 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 1547 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 1548 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 1549 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 1550 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 1551 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 1552 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 1553 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 1554 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 1555 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 1556 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 1557 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 1558 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 1559 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 1560 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
Kojto 93:e188a91d3eaa 1561
Kojto 93:e188a91d3eaa 1562 /******************************************************************************/
Kojto 93:e188a91d3eaa 1563 /* */
Kojto 93:e188a91d3eaa 1564 /* FLASH */
Kojto 93:e188a91d3eaa 1565 /* */
Kojto 93:e188a91d3eaa 1566 /******************************************************************************/
Kojto 93:e188a91d3eaa 1567 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 122:f9eeca106725 1568 #define FLASH_ACR_LATENCY 0x0000000FU
Kojto 122:f9eeca106725 1569 #define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto 122:f9eeca106725 1570 #define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto 122:f9eeca106725 1571 #define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto 122:f9eeca106725 1572 #define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto 122:f9eeca106725 1573 #define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto 122:f9eeca106725 1574 #define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto 122:f9eeca106725 1575 #define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto 122:f9eeca106725 1576 #define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto 122:f9eeca106725 1577
Kojto 122:f9eeca106725 1578 #define FLASH_ACR_PRFTEN 0x00000100U
Kojto 122:f9eeca106725 1579 #define FLASH_ACR_ICEN 0x00000200U
Kojto 122:f9eeca106725 1580 #define FLASH_ACR_DCEN 0x00000400U
Kojto 122:f9eeca106725 1581 #define FLASH_ACR_ICRST 0x00000800U
Kojto 122:f9eeca106725 1582 #define FLASH_ACR_DCRST 0x00001000U
Kojto 122:f9eeca106725 1583 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
Kojto 122:f9eeca106725 1584 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
Kojto 93:e188a91d3eaa 1585
Kojto 93:e188a91d3eaa 1586 /******************* Bits definition for FLASH_SR register ******************/
Kojto 122:f9eeca106725 1587 #define FLASH_SR_EOP 0x00000001U
Kojto 122:f9eeca106725 1588 #define FLASH_SR_SOP 0x00000002U
Kojto 122:f9eeca106725 1589 #define FLASH_SR_WRPERR 0x00000010U
Kojto 122:f9eeca106725 1590 #define FLASH_SR_PGAERR 0x00000020U
Kojto 122:f9eeca106725 1591 #define FLASH_SR_PGPERR 0x00000040U
Kojto 122:f9eeca106725 1592 #define FLASH_SR_PGSERR 0x00000080U
Kojto 122:f9eeca106725 1593 #define FLASH_SR_BSY 0x00010000U
Kojto 93:e188a91d3eaa 1594
Kojto 93:e188a91d3eaa 1595 /******************* Bits definition for FLASH_CR register ******************/
Kojto 122:f9eeca106725 1596 #define FLASH_CR_PG 0x00000001U
Kojto 122:f9eeca106725 1597 #define FLASH_CR_SER 0x00000002U
Kojto 122:f9eeca106725 1598 #define FLASH_CR_MER 0x00000004U
Kojto 122:f9eeca106725 1599 #define FLASH_CR_SNB 0x000000F8U
Kojto 122:f9eeca106725 1600 #define FLASH_CR_SNB_0 0x00000008U
Kojto 122:f9eeca106725 1601 #define FLASH_CR_SNB_1 0x00000010U
Kojto 122:f9eeca106725 1602 #define FLASH_CR_SNB_2 0x00000020U
Kojto 122:f9eeca106725 1603 #define FLASH_CR_SNB_3 0x00000040U
Kojto 122:f9eeca106725 1604 #define FLASH_CR_SNB_4 0x00000080U
Kojto 122:f9eeca106725 1605 #define FLASH_CR_PSIZE 0x00000300U
Kojto 122:f9eeca106725 1606 #define FLASH_CR_PSIZE_0 0x00000100U
Kojto 122:f9eeca106725 1607 #define FLASH_CR_PSIZE_1 0x00000200U
Kojto 122:f9eeca106725 1608 #define FLASH_CR_STRT 0x00010000U
Kojto 122:f9eeca106725 1609 #define FLASH_CR_EOPIE 0x01000000U
Kojto 122:f9eeca106725 1610 #define FLASH_CR_LOCK 0x80000000U
Kojto 93:e188a91d3eaa 1611
Kojto 93:e188a91d3eaa 1612 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 122:f9eeca106725 1613 #define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto 122:f9eeca106725 1614 #define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto 122:f9eeca106725 1615 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto 122:f9eeca106725 1616 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto 122:f9eeca106725 1617 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto 122:f9eeca106725 1618
Kojto 122:f9eeca106725 1619 #define FLASH_OPTCR_WDG_SW 0x00000020U
Kojto 122:f9eeca106725 1620 #define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto 122:f9eeca106725 1621 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto 122:f9eeca106725 1622 #define FLASH_OPTCR_RDP 0x0000FF00U
Kojto 122:f9eeca106725 1623 #define FLASH_OPTCR_RDP_0 0x00000100U
Kojto 122:f9eeca106725 1624 #define FLASH_OPTCR_RDP_1 0x00000200U
Kojto 122:f9eeca106725 1625 #define FLASH_OPTCR_RDP_2 0x00000400U
Kojto 122:f9eeca106725 1626 #define FLASH_OPTCR_RDP_3 0x00000800U
Kojto 122:f9eeca106725 1627 #define FLASH_OPTCR_RDP_4 0x00001000U
Kojto 122:f9eeca106725 1628 #define FLASH_OPTCR_RDP_5 0x00002000U
Kojto 122:f9eeca106725 1629 #define FLASH_OPTCR_RDP_6 0x00004000U
Kojto 122:f9eeca106725 1630 #define FLASH_OPTCR_RDP_7 0x00008000U
Kojto 122:f9eeca106725 1631 #define FLASH_OPTCR_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 1632 #define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 1633 #define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 1634 #define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 1635 #define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 1636 #define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 1637 #define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 1638 #define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 1639 #define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 1640 #define FLASH_OPTCR_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 1641 #define FLASH_OPTCR_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 1642 #define FLASH_OPTCR_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 1643 #define FLASH_OPTCR_nWRP_11 0x08000000U
Kojto 93:e188a91d3eaa 1644
Kojto 93:e188a91d3eaa 1645 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 122:f9eeca106725 1646 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 1647 #define FLASH_OPTCR1_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 1648 #define FLASH_OPTCR1_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 1649 #define FLASH_OPTCR1_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 1650 #define FLASH_OPTCR1_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 1651 #define FLASH_OPTCR1_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 1652 #define FLASH_OPTCR1_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 1653 #define FLASH_OPTCR1_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 1654 #define FLASH_OPTCR1_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 1655 #define FLASH_OPTCR1_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 1656 #define FLASH_OPTCR1_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 1657 #define FLASH_OPTCR1_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 1658 #define FLASH_OPTCR1_nWRP_11 0x08000000U
Kojto 93:e188a91d3eaa 1659
Kojto 93:e188a91d3eaa 1660 /******************************************************************************/
Kojto 93:e188a91d3eaa 1661 /* */
Kojto 93:e188a91d3eaa 1662 /* General Purpose I/O */
Kojto 93:e188a91d3eaa 1663 /* */
Kojto 93:e188a91d3eaa 1664 /******************************************************************************/
Kojto 93:e188a91d3eaa 1665 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 1666 #define GPIO_MODER_MODER0 0x00000003U
Kojto 122:f9eeca106725 1667 #define GPIO_MODER_MODER0_0 0x00000001U
Kojto 122:f9eeca106725 1668 #define GPIO_MODER_MODER0_1 0x00000002U
Kojto 122:f9eeca106725 1669
Kojto 122:f9eeca106725 1670 #define GPIO_MODER_MODER1 0x0000000CU
Kojto 122:f9eeca106725 1671 #define GPIO_MODER_MODER1_0 0x00000004U
Kojto 122:f9eeca106725 1672 #define GPIO_MODER_MODER1_1 0x00000008U
Kojto 122:f9eeca106725 1673
Kojto 122:f9eeca106725 1674 #define GPIO_MODER_MODER2 0x00000030U
Kojto 122:f9eeca106725 1675 #define GPIO_MODER_MODER2_0 0x00000010U
Kojto 122:f9eeca106725 1676 #define GPIO_MODER_MODER2_1 0x00000020U
Kojto 122:f9eeca106725 1677
Kojto 122:f9eeca106725 1678 #define GPIO_MODER_MODER3 0x000000C0U
Kojto 122:f9eeca106725 1679 #define GPIO_MODER_MODER3_0 0x00000040U
Kojto 122:f9eeca106725 1680 #define GPIO_MODER_MODER3_1 0x00000080U
Kojto 122:f9eeca106725 1681
Kojto 122:f9eeca106725 1682 #define GPIO_MODER_MODER4 0x00000300U
Kojto 122:f9eeca106725 1683 #define GPIO_MODER_MODER4_0 0x00000100U
Kojto 122:f9eeca106725 1684 #define GPIO_MODER_MODER4_1 0x00000200U
Kojto 122:f9eeca106725 1685
Kojto 122:f9eeca106725 1686 #define GPIO_MODER_MODER5 0x00000C00U
Kojto 122:f9eeca106725 1687 #define GPIO_MODER_MODER5_0 0x00000400U
Kojto 122:f9eeca106725 1688 #define GPIO_MODER_MODER5_1 0x00000800U
Kojto 122:f9eeca106725 1689
Kojto 122:f9eeca106725 1690 #define GPIO_MODER_MODER6 0x00003000U
Kojto 122:f9eeca106725 1691 #define GPIO_MODER_MODER6_0 0x00001000U
Kojto 122:f9eeca106725 1692 #define GPIO_MODER_MODER6_1 0x00002000U
Kojto 122:f9eeca106725 1693
Kojto 122:f9eeca106725 1694 #define GPIO_MODER_MODER7 0x0000C000U
Kojto 122:f9eeca106725 1695 #define GPIO_MODER_MODER7_0 0x00004000U
Kojto 122:f9eeca106725 1696 #define GPIO_MODER_MODER7_1 0x00008000U
Kojto 122:f9eeca106725 1697
Kojto 122:f9eeca106725 1698 #define GPIO_MODER_MODER8 0x00030000U
Kojto 122:f9eeca106725 1699 #define GPIO_MODER_MODER8_0 0x00010000U
Kojto 122:f9eeca106725 1700 #define GPIO_MODER_MODER8_1 0x00020000U
Kojto 122:f9eeca106725 1701
Kojto 122:f9eeca106725 1702 #define GPIO_MODER_MODER9 0x000C0000U
Kojto 122:f9eeca106725 1703 #define GPIO_MODER_MODER9_0 0x00040000U
Kojto 122:f9eeca106725 1704 #define GPIO_MODER_MODER9_1 0x00080000U
Kojto 122:f9eeca106725 1705
Kojto 122:f9eeca106725 1706 #define GPIO_MODER_MODER10 0x00300000U
Kojto 122:f9eeca106725 1707 #define GPIO_MODER_MODER10_0 0x00100000U
Kojto 122:f9eeca106725 1708 #define GPIO_MODER_MODER10_1 0x00200000U
Kojto 122:f9eeca106725 1709
Kojto 122:f9eeca106725 1710 #define GPIO_MODER_MODER11 0x00C00000U
Kojto 122:f9eeca106725 1711 #define GPIO_MODER_MODER11_0 0x00400000U
Kojto 122:f9eeca106725 1712 #define GPIO_MODER_MODER11_1 0x00800000U
Kojto 122:f9eeca106725 1713
Kojto 122:f9eeca106725 1714 #define GPIO_MODER_MODER12 0x03000000U
Kojto 122:f9eeca106725 1715 #define GPIO_MODER_MODER12_0 0x01000000U
Kojto 122:f9eeca106725 1716 #define GPIO_MODER_MODER12_1 0x02000000U
Kojto 122:f9eeca106725 1717
Kojto 122:f9eeca106725 1718 #define GPIO_MODER_MODER13 0x0C000000U
Kojto 122:f9eeca106725 1719 #define GPIO_MODER_MODER13_0 0x04000000U
Kojto 122:f9eeca106725 1720 #define GPIO_MODER_MODER13_1 0x08000000U
Kojto 122:f9eeca106725 1721
Kojto 122:f9eeca106725 1722 #define GPIO_MODER_MODER14 0x30000000U
Kojto 122:f9eeca106725 1723 #define GPIO_MODER_MODER14_0 0x10000000U
Kojto 122:f9eeca106725 1724 #define GPIO_MODER_MODER14_1 0x20000000U
Kojto 122:f9eeca106725 1725
Kojto 122:f9eeca106725 1726 #define GPIO_MODER_MODER15 0xC0000000U
Kojto 122:f9eeca106725 1727 #define GPIO_MODER_MODER15_0 0x40000000U
Kojto 122:f9eeca106725 1728 #define GPIO_MODER_MODER15_1 0x80000000U
Kojto 93:e188a91d3eaa 1729
Kojto 93:e188a91d3eaa 1730 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 1731 #define GPIO_OTYPER_OT_0 0x00000001U
Kojto 122:f9eeca106725 1732 #define GPIO_OTYPER_OT_1 0x00000002U
Kojto 122:f9eeca106725 1733 #define GPIO_OTYPER_OT_2 0x00000004U
Kojto 122:f9eeca106725 1734 #define GPIO_OTYPER_OT_3 0x00000008U
Kojto 122:f9eeca106725 1735 #define GPIO_OTYPER_OT_4 0x00000010U
Kojto 122:f9eeca106725 1736 #define GPIO_OTYPER_OT_5 0x00000020U
Kojto 122:f9eeca106725 1737 #define GPIO_OTYPER_OT_6 0x00000040U
Kojto 122:f9eeca106725 1738 #define GPIO_OTYPER_OT_7 0x00000080U
Kojto 122:f9eeca106725 1739 #define GPIO_OTYPER_OT_8 0x00000100U
Kojto 122:f9eeca106725 1740 #define GPIO_OTYPER_OT_9 0x00000200U
Kojto 122:f9eeca106725 1741 #define GPIO_OTYPER_OT_10 0x00000400U
Kojto 122:f9eeca106725 1742 #define GPIO_OTYPER_OT_11 0x00000800U
Kojto 122:f9eeca106725 1743 #define GPIO_OTYPER_OT_12 0x00001000U
Kojto 122:f9eeca106725 1744 #define GPIO_OTYPER_OT_13 0x00002000U
Kojto 122:f9eeca106725 1745 #define GPIO_OTYPER_OT_14 0x00004000U
Kojto 122:f9eeca106725 1746 #define GPIO_OTYPER_OT_15 0x00008000U
Kojto 93:e188a91d3eaa 1747
Kojto 93:e188a91d3eaa 1748 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 1749 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto 122:f9eeca106725 1750 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto 122:f9eeca106725 1751 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto 122:f9eeca106725 1752
Kojto 122:f9eeca106725 1753 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto 122:f9eeca106725 1754 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto 122:f9eeca106725 1755 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto 122:f9eeca106725 1756
Kojto 122:f9eeca106725 1757 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto 122:f9eeca106725 1758 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto 122:f9eeca106725 1759 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto 122:f9eeca106725 1760
Kojto 122:f9eeca106725 1761 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto 122:f9eeca106725 1762 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto 122:f9eeca106725 1763 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto 122:f9eeca106725 1764
Kojto 122:f9eeca106725 1765 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto 122:f9eeca106725 1766 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto 122:f9eeca106725 1767 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto 122:f9eeca106725 1768
Kojto 122:f9eeca106725 1769 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto 122:f9eeca106725 1770 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto 122:f9eeca106725 1771 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto 122:f9eeca106725 1772
Kojto 122:f9eeca106725 1773 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto 122:f9eeca106725 1774 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto 122:f9eeca106725 1775 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto 122:f9eeca106725 1776
Kojto 122:f9eeca106725 1777 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto 122:f9eeca106725 1778 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto 122:f9eeca106725 1779 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto 122:f9eeca106725 1780
Kojto 122:f9eeca106725 1781 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto 122:f9eeca106725 1782 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto 122:f9eeca106725 1783 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto 122:f9eeca106725 1784
Kojto 122:f9eeca106725 1785 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto 122:f9eeca106725 1786 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto 122:f9eeca106725 1787 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto 122:f9eeca106725 1788
Kojto 122:f9eeca106725 1789 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto 122:f9eeca106725 1790 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto 122:f9eeca106725 1791 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto 122:f9eeca106725 1792
Kojto 122:f9eeca106725 1793 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto 122:f9eeca106725 1794 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto 122:f9eeca106725 1795 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto 122:f9eeca106725 1796
Kojto 122:f9eeca106725 1797 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto 122:f9eeca106725 1798 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto 122:f9eeca106725 1799 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto 122:f9eeca106725 1800
Kojto 122:f9eeca106725 1801 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto 122:f9eeca106725 1802 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto 122:f9eeca106725 1803 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto 122:f9eeca106725 1804
Kojto 122:f9eeca106725 1805 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto 122:f9eeca106725 1806 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto 122:f9eeca106725 1807 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto 122:f9eeca106725 1808
Kojto 122:f9eeca106725 1809 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto 122:f9eeca106725 1810 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto 122:f9eeca106725 1811 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
Kojto 93:e188a91d3eaa 1812
Kojto 93:e188a91d3eaa 1813 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 1814 #define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto 122:f9eeca106725 1815 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto 122:f9eeca106725 1816 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto 122:f9eeca106725 1817
Kojto 122:f9eeca106725 1818 #define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto 122:f9eeca106725 1819 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto 122:f9eeca106725 1820 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto 122:f9eeca106725 1821
Kojto 122:f9eeca106725 1822 #define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto 122:f9eeca106725 1823 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto 122:f9eeca106725 1824 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto 122:f9eeca106725 1825
Kojto 122:f9eeca106725 1826 #define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto 122:f9eeca106725 1827 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto 122:f9eeca106725 1828 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto 122:f9eeca106725 1829
Kojto 122:f9eeca106725 1830 #define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto 122:f9eeca106725 1831 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto 122:f9eeca106725 1832 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto 122:f9eeca106725 1833
Kojto 122:f9eeca106725 1834 #define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto 122:f9eeca106725 1835 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto 122:f9eeca106725 1836 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto 122:f9eeca106725 1837
Kojto 122:f9eeca106725 1838 #define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto 122:f9eeca106725 1839 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto 122:f9eeca106725 1840 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto 122:f9eeca106725 1841
Kojto 122:f9eeca106725 1842 #define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto 122:f9eeca106725 1843 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto 122:f9eeca106725 1844 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto 122:f9eeca106725 1845
Kojto 122:f9eeca106725 1846 #define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto 122:f9eeca106725 1847 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto 122:f9eeca106725 1848 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto 122:f9eeca106725 1849
Kojto 122:f9eeca106725 1850 #define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto 122:f9eeca106725 1851 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto 122:f9eeca106725 1852 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto 122:f9eeca106725 1853
Kojto 122:f9eeca106725 1854 #define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto 122:f9eeca106725 1855 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto 122:f9eeca106725 1856 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto 122:f9eeca106725 1857
Kojto 122:f9eeca106725 1858 #define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto 122:f9eeca106725 1859 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto 122:f9eeca106725 1860 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto 122:f9eeca106725 1861
Kojto 122:f9eeca106725 1862 #define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto 122:f9eeca106725 1863 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto 122:f9eeca106725 1864 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto 122:f9eeca106725 1865
Kojto 122:f9eeca106725 1866 #define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto 122:f9eeca106725 1867 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto 122:f9eeca106725 1868 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto 122:f9eeca106725 1869
Kojto 122:f9eeca106725 1870 #define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto 122:f9eeca106725 1871 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto 122:f9eeca106725 1872 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto 122:f9eeca106725 1873
Kojto 122:f9eeca106725 1874 #define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto 122:f9eeca106725 1875 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto 122:f9eeca106725 1876 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
Kojto 93:e188a91d3eaa 1877
Kojto 93:e188a91d3eaa 1878 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 1879 #define GPIO_IDR_IDR_0 0x00000001U
Kojto 122:f9eeca106725 1880 #define GPIO_IDR_IDR_1 0x00000002U
Kojto 122:f9eeca106725 1881 #define GPIO_IDR_IDR_2 0x00000004U
Kojto 122:f9eeca106725 1882 #define GPIO_IDR_IDR_3 0x00000008U
Kojto 122:f9eeca106725 1883 #define GPIO_IDR_IDR_4 0x00000010U
Kojto 122:f9eeca106725 1884 #define GPIO_IDR_IDR_5 0x00000020U
Kojto 122:f9eeca106725 1885 #define GPIO_IDR_IDR_6 0x00000040U
Kojto 122:f9eeca106725 1886 #define GPIO_IDR_IDR_7 0x00000080U
Kojto 122:f9eeca106725 1887 #define GPIO_IDR_IDR_8 0x00000100U
Kojto 122:f9eeca106725 1888 #define GPIO_IDR_IDR_9 0x00000200U
Kojto 122:f9eeca106725 1889 #define GPIO_IDR_IDR_10 0x00000400U
Kojto 122:f9eeca106725 1890 #define GPIO_IDR_IDR_11 0x00000800U
Kojto 122:f9eeca106725 1891 #define GPIO_IDR_IDR_12 0x00001000U
Kojto 122:f9eeca106725 1892 #define GPIO_IDR_IDR_13 0x00002000U
Kojto 122:f9eeca106725 1893 #define GPIO_IDR_IDR_14 0x00004000U
Kojto 122:f9eeca106725 1894 #define GPIO_IDR_IDR_15 0x00008000U
Kojto 93:e188a91d3eaa 1895 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1896 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 93:e188a91d3eaa 1897 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 93:e188a91d3eaa 1898 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 93:e188a91d3eaa 1899 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 93:e188a91d3eaa 1900 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 93:e188a91d3eaa 1901 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 93:e188a91d3eaa 1902 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 93:e188a91d3eaa 1903 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 93:e188a91d3eaa 1904 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 93:e188a91d3eaa 1905 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 93:e188a91d3eaa 1906 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 93:e188a91d3eaa 1907 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 93:e188a91d3eaa 1908 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 93:e188a91d3eaa 1909 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 93:e188a91d3eaa 1910 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 93:e188a91d3eaa 1911 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 93:e188a91d3eaa 1912
Kojto 93:e188a91d3eaa 1913 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 1914 #define GPIO_ODR_ODR_0 0x00000001U
Kojto 122:f9eeca106725 1915 #define GPIO_ODR_ODR_1 0x00000002U
Kojto 122:f9eeca106725 1916 #define GPIO_ODR_ODR_2 0x00000004U
Kojto 122:f9eeca106725 1917 #define GPIO_ODR_ODR_3 0x00000008U
Kojto 122:f9eeca106725 1918 #define GPIO_ODR_ODR_4 0x00000010U
Kojto 122:f9eeca106725 1919 #define GPIO_ODR_ODR_5 0x00000020U
Kojto 122:f9eeca106725 1920 #define GPIO_ODR_ODR_6 0x00000040U
Kojto 122:f9eeca106725 1921 #define GPIO_ODR_ODR_7 0x00000080U
Kojto 122:f9eeca106725 1922 #define GPIO_ODR_ODR_8 0x00000100U
Kojto 122:f9eeca106725 1923 #define GPIO_ODR_ODR_9 0x00000200U
Kojto 122:f9eeca106725 1924 #define GPIO_ODR_ODR_10 0x00000400U
Kojto 122:f9eeca106725 1925 #define GPIO_ODR_ODR_11 0x00000800U
Kojto 122:f9eeca106725 1926 #define GPIO_ODR_ODR_12 0x00001000U
Kojto 122:f9eeca106725 1927 #define GPIO_ODR_ODR_13 0x00002000U
Kojto 122:f9eeca106725 1928 #define GPIO_ODR_ODR_14 0x00004000U
Kojto 122:f9eeca106725 1929 #define GPIO_ODR_ODR_15 0x00008000U
Kojto 93:e188a91d3eaa 1930 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1931 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 93:e188a91d3eaa 1932 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 93:e188a91d3eaa 1933 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 93:e188a91d3eaa 1934 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 93:e188a91d3eaa 1935 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 93:e188a91d3eaa 1936 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 93:e188a91d3eaa 1937 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 93:e188a91d3eaa 1938 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 93:e188a91d3eaa 1939 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 93:e188a91d3eaa 1940 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 93:e188a91d3eaa 1941 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 93:e188a91d3eaa 1942 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 93:e188a91d3eaa 1943 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 93:e188a91d3eaa 1944 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 93:e188a91d3eaa 1945 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 93:e188a91d3eaa 1946 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 93:e188a91d3eaa 1947
Kojto 93:e188a91d3eaa 1948 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 1949 #define GPIO_BSRR_BS_0 0x00000001U
Kojto 122:f9eeca106725 1950 #define GPIO_BSRR_BS_1 0x00000002U
Kojto 122:f9eeca106725 1951 #define GPIO_BSRR_BS_2 0x00000004U
Kojto 122:f9eeca106725 1952 #define GPIO_BSRR_BS_3 0x00000008U
Kojto 122:f9eeca106725 1953 #define GPIO_BSRR_BS_4 0x00000010U
Kojto 122:f9eeca106725 1954 #define GPIO_BSRR_BS_5 0x00000020U
Kojto 122:f9eeca106725 1955 #define GPIO_BSRR_BS_6 0x00000040U
Kojto 122:f9eeca106725 1956 #define GPIO_BSRR_BS_7 0x00000080U
Kojto 122:f9eeca106725 1957 #define GPIO_BSRR_BS_8 0x00000100U
Kojto 122:f9eeca106725 1958 #define GPIO_BSRR_BS_9 0x00000200U
Kojto 122:f9eeca106725 1959 #define GPIO_BSRR_BS_10 0x00000400U
Kojto 122:f9eeca106725 1960 #define GPIO_BSRR_BS_11 0x00000800U
Kojto 122:f9eeca106725 1961 #define GPIO_BSRR_BS_12 0x00001000U
Kojto 122:f9eeca106725 1962 #define GPIO_BSRR_BS_13 0x00002000U
Kojto 122:f9eeca106725 1963 #define GPIO_BSRR_BS_14 0x00004000U
Kojto 122:f9eeca106725 1964 #define GPIO_BSRR_BS_15 0x00008000U
Kojto 122:f9eeca106725 1965 #define GPIO_BSRR_BR_0 0x00010000U
Kojto 122:f9eeca106725 1966 #define GPIO_BSRR_BR_1 0x00020000U
Kojto 122:f9eeca106725 1967 #define GPIO_BSRR_BR_2 0x00040000U
Kojto 122:f9eeca106725 1968 #define GPIO_BSRR_BR_3 0x00080000U
Kojto 122:f9eeca106725 1969 #define GPIO_BSRR_BR_4 0x00100000U
Kojto 122:f9eeca106725 1970 #define GPIO_BSRR_BR_5 0x00200000U
Kojto 122:f9eeca106725 1971 #define GPIO_BSRR_BR_6 0x00400000U
Kojto 122:f9eeca106725 1972 #define GPIO_BSRR_BR_7 0x00800000U
Kojto 122:f9eeca106725 1973 #define GPIO_BSRR_BR_8 0x01000000U
Kojto 122:f9eeca106725 1974 #define GPIO_BSRR_BR_9 0x02000000U
Kojto 122:f9eeca106725 1975 #define GPIO_BSRR_BR_10 0x04000000U
Kojto 122:f9eeca106725 1976 #define GPIO_BSRR_BR_11 0x08000000U
Kojto 122:f9eeca106725 1977 #define GPIO_BSRR_BR_12 0x10000000U
Kojto 122:f9eeca106725 1978 #define GPIO_BSRR_BR_13 0x20000000U
Kojto 122:f9eeca106725 1979 #define GPIO_BSRR_BR_14 0x40000000U
Kojto 122:f9eeca106725 1980 #define GPIO_BSRR_BR_15 0x80000000U
Kojto 93:e188a91d3eaa 1981
Kojto 93:e188a91d3eaa 1982 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 122:f9eeca106725 1983 #define GPIO_LCKR_LCK0 0x00000001U
Kojto 122:f9eeca106725 1984 #define GPIO_LCKR_LCK1 0x00000002U
Kojto 122:f9eeca106725 1985 #define GPIO_LCKR_LCK2 0x00000004U
Kojto 122:f9eeca106725 1986 #define GPIO_LCKR_LCK3 0x00000008U
Kojto 122:f9eeca106725 1987 #define GPIO_LCKR_LCK4 0x00000010U
Kojto 122:f9eeca106725 1988 #define GPIO_LCKR_LCK5 0x00000020U
Kojto 122:f9eeca106725 1989 #define GPIO_LCKR_LCK6 0x00000040U
Kojto 122:f9eeca106725 1990 #define GPIO_LCKR_LCK7 0x00000080U
Kojto 122:f9eeca106725 1991 #define GPIO_LCKR_LCK8 0x00000100U
Kojto 122:f9eeca106725 1992 #define GPIO_LCKR_LCK9 0x00000200U
Kojto 122:f9eeca106725 1993 #define GPIO_LCKR_LCK10 0x00000400U
Kojto 122:f9eeca106725 1994 #define GPIO_LCKR_LCK11 0x00000800U
Kojto 122:f9eeca106725 1995 #define GPIO_LCKR_LCK12 0x00001000U
Kojto 122:f9eeca106725 1996 #define GPIO_LCKR_LCK13 0x00002000U
Kojto 122:f9eeca106725 1997 #define GPIO_LCKR_LCK14 0x00004000U
Kojto 122:f9eeca106725 1998 #define GPIO_LCKR_LCK15 0x00008000U
Kojto 122:f9eeca106725 1999 #define GPIO_LCKR_LCKK 0x00010000U
Kojto 93:e188a91d3eaa 2000
Kojto 93:e188a91d3eaa 2001 /******************************************************************************/
Kojto 93:e188a91d3eaa 2002 /* */
Kojto 93:e188a91d3eaa 2003 /* Inter-integrated Circuit Interface */
Kojto 93:e188a91d3eaa 2004 /* */
Kojto 93:e188a91d3eaa 2005 /******************************************************************************/
Kojto 93:e188a91d3eaa 2006 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 122:f9eeca106725 2007 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
Kojto 122:f9eeca106725 2008 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
Kojto 122:f9eeca106725 2009 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
Kojto 122:f9eeca106725 2010 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
Kojto 122:f9eeca106725 2011 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
Kojto 122:f9eeca106725 2012 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
Kojto 122:f9eeca106725 2013 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
Kojto 122:f9eeca106725 2014 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
Kojto 122:f9eeca106725 2015 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
Kojto 122:f9eeca106725 2016 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
Kojto 122:f9eeca106725 2017 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
Kojto 122:f9eeca106725 2018 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
Kojto 122:f9eeca106725 2019 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
Kojto 122:f9eeca106725 2020 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
Kojto 93:e188a91d3eaa 2021
Kojto 93:e188a91d3eaa 2022 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 2023 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 122:f9eeca106725 2024 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 2025 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 2026 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 2027 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 2028 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 2029 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 2030
Kojto 122:f9eeca106725 2031 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 2032 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
Kojto 122:f9eeca106725 2033 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
Kojto 122:f9eeca106725 2034 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
Kojto 122:f9eeca106725 2035 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
Kojto 93:e188a91d3eaa 2036
Kojto 93:e188a91d3eaa 2037 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 122:f9eeca106725 2038 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
Kojto 122:f9eeca106725 2039 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
Kojto 122:f9eeca106725 2040
Kojto 122:f9eeca106725 2041 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 2042 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 2043 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 2044 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 2045 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 2046 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 2047 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 2048 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 2049 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
Kojto 122:f9eeca106725 2050 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
Kojto 122:f9eeca106725 2051
Kojto 122:f9eeca106725 2052 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
Kojto 93:e188a91d3eaa 2053
Kojto 93:e188a91d3eaa 2054 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 122:f9eeca106725 2055 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
Kojto 122:f9eeca106725 2056 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
Kojto 93:e188a91d3eaa 2057
Kojto 93:e188a91d3eaa 2058 /******************** Bit definition for I2C_DR register ********************/
Kojto 122:f9eeca106725 2059 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
Kojto 93:e188a91d3eaa 2060
Kojto 93:e188a91d3eaa 2061 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 122:f9eeca106725 2062 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
Kojto 122:f9eeca106725 2063 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
Kojto 122:f9eeca106725 2064 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
Kojto 122:f9eeca106725 2065 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
Kojto 122:f9eeca106725 2066 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
Kojto 122:f9eeca106725 2067 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
Kojto 122:f9eeca106725 2068 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
Kojto 122:f9eeca106725 2069 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
Kojto 122:f9eeca106725 2070 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
Kojto 122:f9eeca106725 2071 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
Kojto 122:f9eeca106725 2072 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
Kojto 122:f9eeca106725 2073 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
Kojto 122:f9eeca106725 2074 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
Kojto 122:f9eeca106725 2075 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
Kojto 93:e188a91d3eaa 2076
Kojto 93:e188a91d3eaa 2077 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 122:f9eeca106725 2078 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
Kojto 122:f9eeca106725 2079 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
Kojto 122:f9eeca106725 2080 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
Kojto 122:f9eeca106725 2081 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
Kojto 122:f9eeca106725 2082 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
Kojto 122:f9eeca106725 2083 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
Kojto 122:f9eeca106725 2084 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
Kojto 122:f9eeca106725 2085 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
Kojto 93:e188a91d3eaa 2086
Kojto 93:e188a91d3eaa 2087 /******************* Bit definition for I2C_CCR register ********************/
Kojto 122:f9eeca106725 2088 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 122:f9eeca106725 2089 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
Kojto 122:f9eeca106725 2090 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
Kojto 93:e188a91d3eaa 2091
Kojto 93:e188a91d3eaa 2092 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 122:f9eeca106725 2093 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 93:e188a91d3eaa 2094
Kojto 93:e188a91d3eaa 2095 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 122:f9eeca106725 2096 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
Kojto 122:f9eeca106725 2097 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
Kojto 93:e188a91d3eaa 2098
Kojto 93:e188a91d3eaa 2099 /******************************************************************************/
Kojto 93:e188a91d3eaa 2100 /* */
Kojto 93:e188a91d3eaa 2101 /* Independent WATCHDOG */
Kojto 93:e188a91d3eaa 2102 /* */
Kojto 93:e188a91d3eaa 2103 /******************************************************************************/
Kojto 93:e188a91d3eaa 2104 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 2105 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
Kojto 93:e188a91d3eaa 2106
Kojto 93:e188a91d3eaa 2107 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 2108 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 2109 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 2110 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 2111 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2112
Kojto 93:e188a91d3eaa 2113 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 2114 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
Kojto 93:e188a91d3eaa 2115
Kojto 93:e188a91d3eaa 2116 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 2117 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
Kojto 122:f9eeca106725 2118 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
Kojto 93:e188a91d3eaa 2119
Kojto 93:e188a91d3eaa 2120
Kojto 93:e188a91d3eaa 2121 /******************************************************************************/
Kojto 93:e188a91d3eaa 2122 /* */
Kojto 93:e188a91d3eaa 2123 /* Power Control */
Kojto 93:e188a91d3eaa 2124 /* */
Kojto 93:e188a91d3eaa 2125 /******************************************************************************/
Kojto 93:e188a91d3eaa 2126 /******************** Bit definition for PWR_CR register ********************/
Kojto 122:f9eeca106725 2127 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
Kojto 122:f9eeca106725 2128 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 2129 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 2130 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 2131 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 2132
Kojto 122:f9eeca106725 2133 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 2134 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
Kojto 122:f9eeca106725 2135 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
Kojto 122:f9eeca106725 2136 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2137
Kojto 93:e188a91d3eaa 2138 /*!< PVD level configuration */
Kojto 122:f9eeca106725 2139 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
Kojto 122:f9eeca106725 2140 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
Kojto 122:f9eeca106725 2141 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
Kojto 122:f9eeca106725 2142 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
Kojto 122:f9eeca106725 2143 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
Kojto 122:f9eeca106725 2144 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
Kojto 122:f9eeca106725 2145 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
Kojto 122:f9eeca106725 2146 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
Kojto 122:f9eeca106725 2147
Kojto 122:f9eeca106725 2148 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
Kojto 122:f9eeca106725 2149 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
Kojto 122:f9eeca106725 2150 #define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
Kojto 122:f9eeca106725 2151 #define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
Kojto 122:f9eeca106725 2152 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 2153
Kojto 122:f9eeca106725 2154 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 122:f9eeca106725 2155 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
Kojto 122:f9eeca106725 2156 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
Kojto 122:f9eeca106725 2157
Kojto 122:f9eeca106725 2158 #define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
Kojto 122:f9eeca106725 2159 #define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
Kojto 93:e188a91d3eaa 2160 /* Legacy define */
Kojto 93:e188a91d3eaa 2161 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 93:e188a91d3eaa 2162
Kojto 93:e188a91d3eaa 2163 /******************* Bit definition for PWR_CSR register ********************/
Kojto 122:f9eeca106725 2164 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
Kojto 122:f9eeca106725 2165 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
Kojto 122:f9eeca106725 2166 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
Kojto 122:f9eeca106725 2167 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
Kojto 122:f9eeca106725 2168 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
Kojto 122:f9eeca106725 2169 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
Kojto 122:f9eeca106725 2170 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
Kojto 93:e188a91d3eaa 2171
Kojto 93:e188a91d3eaa 2172 /* Legacy define */
Kojto 93:e188a91d3eaa 2173 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 93:e188a91d3eaa 2174
Kojto 93:e188a91d3eaa 2175 /******************************************************************************/
Kojto 93:e188a91d3eaa 2176 /* */
Kojto 93:e188a91d3eaa 2177 /* Reset and Clock Control */
Kojto 93:e188a91d3eaa 2178 /* */
Kojto 93:e188a91d3eaa 2179 /******************************************************************************/
Kojto 93:e188a91d3eaa 2180 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 2181 #define RCC_CR_HSION 0x00000001U
Kojto 122:f9eeca106725 2182 #define RCC_CR_HSIRDY 0x00000002U
Kojto 122:f9eeca106725 2183
Kojto 122:f9eeca106725 2184 #define RCC_CR_HSITRIM 0x000000F8U
Kojto 122:f9eeca106725 2185 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
Kojto 122:f9eeca106725 2186 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
Kojto 122:f9eeca106725 2187 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
Kojto 122:f9eeca106725 2188 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
Kojto 122:f9eeca106725 2189 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
Kojto 122:f9eeca106725 2190
Kojto 122:f9eeca106725 2191 #define RCC_CR_HSICAL 0x0000FF00U
Kojto 122:f9eeca106725 2192 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
Kojto 122:f9eeca106725 2193 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
Kojto 122:f9eeca106725 2194 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
Kojto 122:f9eeca106725 2195 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
Kojto 122:f9eeca106725 2196 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
Kojto 122:f9eeca106725 2197 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
Kojto 122:f9eeca106725 2198 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
Kojto 122:f9eeca106725 2199 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
Kojto 122:f9eeca106725 2200
Kojto 122:f9eeca106725 2201 #define RCC_CR_HSEON 0x00010000U
Kojto 122:f9eeca106725 2202 #define RCC_CR_HSERDY 0x00020000U
Kojto 122:f9eeca106725 2203 #define RCC_CR_HSEBYP 0x00040000U
Kojto 122:f9eeca106725 2204 #define RCC_CR_CSSON 0x00080000U
Kojto 122:f9eeca106725 2205 #define RCC_CR_PLLON 0x01000000U
Kojto 122:f9eeca106725 2206 #define RCC_CR_PLLRDY 0x02000000U
Kojto 122:f9eeca106725 2207 #define RCC_CR_PLLI2SON 0x04000000U
Kojto 122:f9eeca106725 2208 #define RCC_CR_PLLI2SRDY 0x08000000U
Kojto 93:e188a91d3eaa 2209
Kojto 93:e188a91d3eaa 2210 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 122:f9eeca106725 2211 #define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto 122:f9eeca106725 2212 #define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto 122:f9eeca106725 2213 #define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto 122:f9eeca106725 2214 #define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto 122:f9eeca106725 2215 #define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto 122:f9eeca106725 2216 #define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto 122:f9eeca106725 2217 #define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 #define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto 122:f9eeca106725 2220 #define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto 122:f9eeca106725 2221 #define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto 122:f9eeca106725 2222 #define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto 122:f9eeca106725 2223 #define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto 122:f9eeca106725 2224 #define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto 122:f9eeca106725 2225 #define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto 122:f9eeca106725 2226 #define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto 122:f9eeca106725 2227 #define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto 122:f9eeca106725 2228 #define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto 122:f9eeca106725 2229
Kojto 122:f9eeca106725 2230 #define RCC_PLLCFGR_PLLP 0x00030000U
Kojto 122:f9eeca106725 2231 #define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto 122:f9eeca106725 2232 #define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto 122:f9eeca106725 2233
Kojto 122:f9eeca106725 2234 #define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto 122:f9eeca106725 2235 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto 122:f9eeca106725 2236 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto 122:f9eeca106725 2237
Kojto 122:f9eeca106725 2238 #define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto 122:f9eeca106725 2239 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto 122:f9eeca106725 2240 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto 122:f9eeca106725 2241 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto 122:f9eeca106725 2242 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
Kojto 93:e188a91d3eaa 2243
Kojto 93:e188a91d3eaa 2244 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 93:e188a91d3eaa 2245 /*!< SW configuration */
Kojto 122:f9eeca106725 2246 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 2247 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 2248 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 2249
Kojto 122:f9eeca106725 2250 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 2251 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 2252 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
Kojto 93:e188a91d3eaa 2253
Kojto 93:e188a91d3eaa 2254 /*!< SWS configuration */
Kojto 122:f9eeca106725 2255 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 2256 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
Kojto 122:f9eeca106725 2257 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
Kojto 122:f9eeca106725 2258
Kojto 122:f9eeca106725 2259 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 2260 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 2261 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
Kojto 93:e188a91d3eaa 2262
Kojto 93:e188a91d3eaa 2263 /*!< HPRE configuration */
Kojto 122:f9eeca106725 2264 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 2265 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
Kojto 122:f9eeca106725 2266 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
Kojto 122:f9eeca106725 2267 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
Kojto 122:f9eeca106725 2268 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
Kojto 122:f9eeca106725 2269
Kojto 122:f9eeca106725 2270 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 2271 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 2272 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 2273 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 2274 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 2275 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 2276 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 2277 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 2278 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
Kojto 93:e188a91d3eaa 2279
Kojto 93:e188a91d3eaa 2280 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 2281 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 2282 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 2283 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 2284 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
Kojto 122:f9eeca106725 2285
Kojto 122:f9eeca106725 2286 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 2287 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 2288 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 2289 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 2290 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
Kojto 93:e188a91d3eaa 2291
Kojto 93:e188a91d3eaa 2292 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 2293 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 2294 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
Kojto 122:f9eeca106725 2295 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
Kojto 122:f9eeca106725 2296 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
Kojto 122:f9eeca106725 2297
Kojto 122:f9eeca106725 2298 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 2299 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 2300 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 2301 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 2302 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
Kojto 93:e188a91d3eaa 2303
Kojto 93:e188a91d3eaa 2304 /*!< RTCPRE configuration */
Kojto 122:f9eeca106725 2305 #define RCC_CFGR_RTCPRE 0x001F0000U
Kojto 122:f9eeca106725 2306 #define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto 122:f9eeca106725 2307 #define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto 122:f9eeca106725 2308 #define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto 122:f9eeca106725 2309 #define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto 122:f9eeca106725 2310 #define RCC_CFGR_RTCPRE_4 0x00100000U
Kojto 93:e188a91d3eaa 2311
Kojto 93:e188a91d3eaa 2312 /*!< MCO1 configuration */
Kojto 122:f9eeca106725 2313 #define RCC_CFGR_MCO1 0x00600000U
Kojto 122:f9eeca106725 2314 #define RCC_CFGR_MCO1_0 0x00200000U
Kojto 122:f9eeca106725 2315 #define RCC_CFGR_MCO1_1 0x00400000U
Kojto 122:f9eeca106725 2316
Kojto 122:f9eeca106725 2317 #define RCC_CFGR_I2SSRC 0x00800000U
Kojto 122:f9eeca106725 2318
Kojto 122:f9eeca106725 2319 #define RCC_CFGR_MCO1PRE 0x07000000U
Kojto 122:f9eeca106725 2320 #define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto 122:f9eeca106725 2321 #define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto 122:f9eeca106725 2322 #define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto 122:f9eeca106725 2323
Kojto 122:f9eeca106725 2324 #define RCC_CFGR_MCO2PRE 0x38000000U
Kojto 122:f9eeca106725 2325 #define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto 122:f9eeca106725 2326 #define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto 122:f9eeca106725 2327 #define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto 122:f9eeca106725 2328
Kojto 122:f9eeca106725 2329 #define RCC_CFGR_MCO2 0xC0000000U
Kojto 122:f9eeca106725 2330 #define RCC_CFGR_MCO2_0 0x40000000U
Kojto 122:f9eeca106725 2331 #define RCC_CFGR_MCO2_1 0x80000000U
Kojto 93:e188a91d3eaa 2332
Kojto 93:e188a91d3eaa 2333 /******************** Bit definition for RCC_CIR register *******************/
Kojto 122:f9eeca106725 2334 #define RCC_CIR_LSIRDYF 0x00000001U
Kojto 122:f9eeca106725 2335 #define RCC_CIR_LSERDYF 0x00000002U
Kojto 122:f9eeca106725 2336 #define RCC_CIR_HSIRDYF 0x00000004U
Kojto 122:f9eeca106725 2337 #define RCC_CIR_HSERDYF 0x00000008U
Kojto 122:f9eeca106725 2338 #define RCC_CIR_PLLRDYF 0x00000010U
Kojto 122:f9eeca106725 2339 #define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto 122:f9eeca106725 2340
Kojto 122:f9eeca106725 2341 #define RCC_CIR_CSSF 0x00000080U
Kojto 122:f9eeca106725 2342 #define RCC_CIR_LSIRDYIE 0x00000100U
Kojto 122:f9eeca106725 2343 #define RCC_CIR_LSERDYIE 0x00000200U
Kojto 122:f9eeca106725 2344 #define RCC_CIR_HSIRDYIE 0x00000400U
Kojto 122:f9eeca106725 2345 #define RCC_CIR_HSERDYIE 0x00000800U
Kojto 122:f9eeca106725 2346 #define RCC_CIR_PLLRDYIE 0x00001000U
Kojto 122:f9eeca106725 2347 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto 122:f9eeca106725 2348
Kojto 122:f9eeca106725 2349 #define RCC_CIR_LSIRDYC 0x00010000U
Kojto 122:f9eeca106725 2350 #define RCC_CIR_LSERDYC 0x00020000U
Kojto 122:f9eeca106725 2351 #define RCC_CIR_HSIRDYC 0x00040000U
Kojto 122:f9eeca106725 2352 #define RCC_CIR_HSERDYC 0x00080000U
Kojto 122:f9eeca106725 2353 #define RCC_CIR_PLLRDYC 0x00100000U
Kojto 122:f9eeca106725 2354 #define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto 122:f9eeca106725 2355
Kojto 122:f9eeca106725 2356 #define RCC_CIR_CSSC 0x00800000U
Kojto 93:e188a91d3eaa 2357
Kojto 93:e188a91d3eaa 2358 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 122:f9eeca106725 2359 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto 122:f9eeca106725 2360 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto 122:f9eeca106725 2361 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto 122:f9eeca106725 2362 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto 122:f9eeca106725 2363 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto 122:f9eeca106725 2364 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto 122:f9eeca106725 2365 #define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto 122:f9eeca106725 2366 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto 122:f9eeca106725 2367 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto 93:e188a91d3eaa 2368
Kojto 93:e188a91d3eaa 2369 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 122:f9eeca106725 2370 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
Kojto 93:e188a91d3eaa 2371
Kojto 93:e188a91d3eaa 2372 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 93:e188a91d3eaa 2373
Kojto 93:e188a91d3eaa 2374 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 122:f9eeca106725 2375 #define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto 122:f9eeca106725 2376 #define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto 122:f9eeca106725 2377 #define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto 122:f9eeca106725 2378 #define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto 122:f9eeca106725 2379 #define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto 122:f9eeca106725 2380 #define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto 122:f9eeca106725 2381 #define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto 122:f9eeca106725 2382 #define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto 122:f9eeca106725 2383 #define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto 122:f9eeca106725 2384 #define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto 122:f9eeca106725 2385 #define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto 122:f9eeca106725 2386 #define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto 93:e188a91d3eaa 2387
Kojto 93:e188a91d3eaa 2388 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 122:f9eeca106725 2389 #define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto 122:f9eeca106725 2390 #define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto 122:f9eeca106725 2391 #define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto 122:f9eeca106725 2392 #define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto 122:f9eeca106725 2393 #define RCC_APB2RSTR_SDIORST 0x00000800U
Kojto 122:f9eeca106725 2394 #define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto 122:f9eeca106725 2395 #define RCC_APB2RSTR_SPI4RST 0x00002000U
Kojto 122:f9eeca106725 2396 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto 122:f9eeca106725 2397 #define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto 122:f9eeca106725 2398 #define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto 122:f9eeca106725 2399 #define RCC_APB2RSTR_TIM11RST 0x00040000U
Kojto 122:f9eeca106725 2400 #define RCC_APB2RSTR_SPI5RST 0x00100000U
Kojto 93:e188a91d3eaa 2401
Kojto 93:e188a91d3eaa 2402 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 2403 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 93:e188a91d3eaa 2404
Kojto 93:e188a91d3eaa 2405 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 122:f9eeca106725 2406 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto 122:f9eeca106725 2407 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto 122:f9eeca106725 2408 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto 122:f9eeca106725 2409 #define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto 122:f9eeca106725 2410 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto 122:f9eeca106725 2411 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto 122:f9eeca106725 2412 #define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto 122:f9eeca106725 2413 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto 122:f9eeca106725 2414 #define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto 122:f9eeca106725 2415 #define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto 93:e188a91d3eaa 2416
Kojto 93:e188a91d3eaa 2417 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 122:f9eeca106725 2418 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
Kojto 93:e188a91d3eaa 2419
Kojto 93:e188a91d3eaa 2420 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 93:e188a91d3eaa 2421
Kojto 93:e188a91d3eaa 2422 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 122:f9eeca106725 2423 #define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto 122:f9eeca106725 2424 #define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto 122:f9eeca106725 2425 #define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto 122:f9eeca106725 2426 #define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto 122:f9eeca106725 2427 #define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto 122:f9eeca106725 2428 #define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto 122:f9eeca106725 2429 #define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto 122:f9eeca106725 2430 #define RCC_APB1ENR_USART2EN 0x00020000U
Kojto 122:f9eeca106725 2431 #define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto 122:f9eeca106725 2432 #define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto 122:f9eeca106725 2433 #define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto 122:f9eeca106725 2434 #define RCC_APB1ENR_PWREN 0x10000000U
Kojto 93:e188a91d3eaa 2435
Kojto 93:e188a91d3eaa 2436 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 122:f9eeca106725 2437 #define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto 122:f9eeca106725 2438 #define RCC_APB2ENR_USART1EN 0x00000010U
Kojto 122:f9eeca106725 2439 #define RCC_APB2ENR_USART6EN 0x00000020U
Kojto 122:f9eeca106725 2440 #define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto 122:f9eeca106725 2441 #define RCC_APB2ENR_SDIOEN 0x00000800U
Kojto 122:f9eeca106725 2442 #define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto 122:f9eeca106725 2443 #define RCC_APB2ENR_SPI4EN 0x00002000U
Kojto 122:f9eeca106725 2444 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto 122:f9eeca106725 2445 #define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto 122:f9eeca106725 2446 #define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto 122:f9eeca106725 2447 #define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto 122:f9eeca106725 2448 #define RCC_APB2ENR_SPI5EN 0x00100000U
Kojto 93:e188a91d3eaa 2449
Kojto 93:e188a91d3eaa 2450 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 122:f9eeca106725 2451 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto 122:f9eeca106725 2452 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto 122:f9eeca106725 2453 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto 122:f9eeca106725 2454 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto 122:f9eeca106725 2455 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto 122:f9eeca106725 2456 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto 122:f9eeca106725 2457 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto 122:f9eeca106725 2458 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto 122:f9eeca106725 2459 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto 122:f9eeca106725 2460 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto 122:f9eeca106725 2461 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto 122:f9eeca106725 2462 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto 122:f9eeca106725 2463 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto 93:e188a91d3eaa 2464
Kojto 93:e188a91d3eaa 2465 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 122:f9eeca106725 2466 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
Kojto 93:e188a91d3eaa 2467
Kojto 93:e188a91d3eaa 2468 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 93:e188a91d3eaa 2469
Kojto 93:e188a91d3eaa 2470 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 122:f9eeca106725 2471 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto 122:f9eeca106725 2472 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto 122:f9eeca106725 2473 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto 122:f9eeca106725 2474 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto 122:f9eeca106725 2475 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto 122:f9eeca106725 2476 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto 122:f9eeca106725 2477 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto 122:f9eeca106725 2478 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto 122:f9eeca106725 2479 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto 122:f9eeca106725 2480 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto 122:f9eeca106725 2481 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto 122:f9eeca106725 2482 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto 122:f9eeca106725 2483 #define RCC_APB1LPENR_DACLPEN 0x20000000U
Kojto 93:e188a91d3eaa 2484
Kojto 93:e188a91d3eaa 2485 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 122:f9eeca106725 2486 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto 122:f9eeca106725 2487 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto 122:f9eeca106725 2488 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto 122:f9eeca106725 2489 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto 122:f9eeca106725 2490 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
Kojto 122:f9eeca106725 2491 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto 122:f9eeca106725 2492 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
Kojto 122:f9eeca106725 2493 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto 122:f9eeca106725 2494 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto 122:f9eeca106725 2495 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto 122:f9eeca106725 2496 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
Kojto 122:f9eeca106725 2497 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
Kojto 93:e188a91d3eaa 2498
Kojto 93:e188a91d3eaa 2499 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 2500 #define RCC_BDCR_LSEON 0x00000001U
Kojto 122:f9eeca106725 2501 #define RCC_BDCR_LSERDY 0x00000002U
Kojto 122:f9eeca106725 2502 #define RCC_BDCR_LSEBYP 0x00000004U
Kojto 122:f9eeca106725 2503 #define RCC_BDCR_LSEMOD 0x00000008U
Kojto 122:f9eeca106725 2504
Kojto 122:f9eeca106725 2505 #define RCC_BDCR_RTCSEL 0x00000300U
Kojto 122:f9eeca106725 2506 #define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto 122:f9eeca106725 2507 #define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto 122:f9eeca106725 2508
Kojto 122:f9eeca106725 2509 #define RCC_BDCR_RTCEN 0x00008000U
Kojto 122:f9eeca106725 2510 #define RCC_BDCR_BDRST 0x00010000U
Kojto 93:e188a91d3eaa 2511
Kojto 93:e188a91d3eaa 2512 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 2513 #define RCC_CSR_LSION 0x00000001U
Kojto 122:f9eeca106725 2514 #define RCC_CSR_LSIRDY 0x00000002U
Kojto 122:f9eeca106725 2515 #define RCC_CSR_RMVF 0x01000000U
Kojto 122:f9eeca106725 2516 #define RCC_CSR_BORRSTF 0x02000000U
Kojto 122:f9eeca106725 2517 #define RCC_CSR_PADRSTF 0x04000000U
Kojto 122:f9eeca106725 2518 #define RCC_CSR_PORRSTF 0x08000000U
Kojto 122:f9eeca106725 2519 #define RCC_CSR_SFTRSTF 0x10000000U
Kojto 122:f9eeca106725 2520 #define RCC_CSR_WDGRSTF 0x20000000U
Kojto 122:f9eeca106725 2521 #define RCC_CSR_WWDGRSTF 0x40000000U
Kojto 122:f9eeca106725 2522 #define RCC_CSR_LPWRRSTF 0x80000000U
Kojto 93:e188a91d3eaa 2523
Kojto 93:e188a91d3eaa 2524 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 122:f9eeca106725 2525 #define RCC_SSCGR_MODPER 0x00001FFFU
Kojto 122:f9eeca106725 2526 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto 122:f9eeca106725 2527 #define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto 122:f9eeca106725 2528 #define RCC_SSCGR_SSCGEN 0x80000000U
Kojto 93:e188a91d3eaa 2529
Kojto 93:e188a91d3eaa 2530 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 122:f9eeca106725 2531 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
Kojto 122:f9eeca106725 2532 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
Kojto 122:f9eeca106725 2533 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
Kojto 122:f9eeca106725 2534 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
Kojto 122:f9eeca106725 2535 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
Kojto 122:f9eeca106725 2536 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
Kojto 122:f9eeca106725 2537 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
Kojto 122:f9eeca106725 2538
Kojto 122:f9eeca106725 2539 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto 122:f9eeca106725 2540 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto 122:f9eeca106725 2541 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto 122:f9eeca106725 2542 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto 122:f9eeca106725 2543 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto 122:f9eeca106725 2544 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto 122:f9eeca106725 2545 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto 122:f9eeca106725 2546 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto 122:f9eeca106725 2547 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto 122:f9eeca106725 2548 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto 122:f9eeca106725 2549
Kojto 122:f9eeca106725 2550 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto 122:f9eeca106725 2551 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto 122:f9eeca106725 2552 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto 122:f9eeca106725 2553 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
Kojto 122:f9eeca106725 2554
Kojto 122:f9eeca106725 2555 /******************** Bit definition for RCC_DCKCFGR register ***************/
Kojto 122:f9eeca106725 2556 #define RCC_DCKCFGR_TIMPRE 0x01000000U
Kojto 93:e188a91d3eaa 2557
Kojto 93:e188a91d3eaa 2558 /******************************************************************************/
Kojto 93:e188a91d3eaa 2559 /* */
Kojto 93:e188a91d3eaa 2560 /* Real-Time Clock (RTC) */
Kojto 93:e188a91d3eaa 2561 /* */
Kojto 93:e188a91d3eaa 2562 /******************************************************************************/
Kojto 93:e188a91d3eaa 2563 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 2564 #define RTC_TR_PM 0x00400000U
Kojto 122:f9eeca106725 2565 #define RTC_TR_HT 0x00300000U
Kojto 122:f9eeca106725 2566 #define RTC_TR_HT_0 0x00100000U
Kojto 122:f9eeca106725 2567 #define RTC_TR_HT_1 0x00200000U
Kojto 122:f9eeca106725 2568 #define RTC_TR_HU 0x000F0000U
Kojto 122:f9eeca106725 2569 #define RTC_TR_HU_0 0x00010000U
Kojto 122:f9eeca106725 2570 #define RTC_TR_HU_1 0x00020000U
Kojto 122:f9eeca106725 2571 #define RTC_TR_HU_2 0x00040000U
Kojto 122:f9eeca106725 2572 #define RTC_TR_HU_3 0x00080000U
Kojto 122:f9eeca106725 2573 #define RTC_TR_MNT 0x00007000U
Kojto 122:f9eeca106725 2574 #define RTC_TR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 2575 #define RTC_TR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 2576 #define RTC_TR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 2577 #define RTC_TR_MNU 0x00000F00U
Kojto 122:f9eeca106725 2578 #define RTC_TR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 2579 #define RTC_TR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 2580 #define RTC_TR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 2581 #define RTC_TR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 2582 #define RTC_TR_ST 0x00000070U
Kojto 122:f9eeca106725 2583 #define RTC_TR_ST_0 0x00000010U
Kojto 122:f9eeca106725 2584 #define RTC_TR_ST_1 0x00000020U
Kojto 122:f9eeca106725 2585 #define RTC_TR_ST_2 0x00000040U
Kojto 122:f9eeca106725 2586 #define RTC_TR_SU 0x0000000FU
Kojto 122:f9eeca106725 2587 #define RTC_TR_SU_0 0x00000001U
Kojto 122:f9eeca106725 2588 #define RTC_TR_SU_1 0x00000002U
Kojto 122:f9eeca106725 2589 #define RTC_TR_SU_2 0x00000004U
Kojto 122:f9eeca106725 2590 #define RTC_TR_SU_3 0x00000008U
Kojto 93:e188a91d3eaa 2591
Kojto 93:e188a91d3eaa 2592 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 2593 #define RTC_DR_YT 0x00F00000U
Kojto 122:f9eeca106725 2594 #define RTC_DR_YT_0 0x00100000U
Kojto 122:f9eeca106725 2595 #define RTC_DR_YT_1 0x00200000U
Kojto 122:f9eeca106725 2596 #define RTC_DR_YT_2 0x00400000U
Kojto 122:f9eeca106725 2597 #define RTC_DR_YT_3 0x00800000U
Kojto 122:f9eeca106725 2598 #define RTC_DR_YU 0x000F0000U
Kojto 122:f9eeca106725 2599 #define RTC_DR_YU_0 0x00010000U
Kojto 122:f9eeca106725 2600 #define RTC_DR_YU_1 0x00020000U
Kojto 122:f9eeca106725 2601 #define RTC_DR_YU_2 0x00040000U
Kojto 122:f9eeca106725 2602 #define RTC_DR_YU_3 0x00080000U
Kojto 122:f9eeca106725 2603 #define RTC_DR_WDU 0x0000E000U
Kojto 122:f9eeca106725 2604 #define RTC_DR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 2605 #define RTC_DR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 2606 #define RTC_DR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 2607 #define RTC_DR_MT 0x00001000U
Kojto 122:f9eeca106725 2608 #define RTC_DR_MU 0x00000F00U
Kojto 122:f9eeca106725 2609 #define RTC_DR_MU_0 0x00000100U
Kojto 122:f9eeca106725 2610 #define RTC_DR_MU_1 0x00000200U
Kojto 122:f9eeca106725 2611 #define RTC_DR_MU_2 0x00000400U
Kojto 122:f9eeca106725 2612 #define RTC_DR_MU_3 0x00000800U
Kojto 122:f9eeca106725 2613 #define RTC_DR_DT 0x00000030U
Kojto 122:f9eeca106725 2614 #define RTC_DR_DT_0 0x00000010U
Kojto 122:f9eeca106725 2615 #define RTC_DR_DT_1 0x00000020U
Kojto 122:f9eeca106725 2616 #define RTC_DR_DU 0x0000000FU
Kojto 122:f9eeca106725 2617 #define RTC_DR_DU_0 0x00000001U
Kojto 122:f9eeca106725 2618 #define RTC_DR_DU_1 0x00000002U
Kojto 122:f9eeca106725 2619 #define RTC_DR_DU_2 0x00000004U
Kojto 122:f9eeca106725 2620 #define RTC_DR_DU_3 0x00000008U
Kojto 93:e188a91d3eaa 2621
Kojto 93:e188a91d3eaa 2622 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 2623 #define RTC_CR_COE 0x00800000U
Kojto 122:f9eeca106725 2624 #define RTC_CR_OSEL 0x00600000U
Kojto 122:f9eeca106725 2625 #define RTC_CR_OSEL_0 0x00200000U
Kojto 122:f9eeca106725 2626 #define RTC_CR_OSEL_1 0x00400000U
Kojto 122:f9eeca106725 2627 #define RTC_CR_POL 0x00100000U
Kojto 122:f9eeca106725 2628 #define RTC_CR_COSEL 0x00080000U
Kojto 122:f9eeca106725 2629 #define RTC_CR_BCK 0x00040000U
Kojto 122:f9eeca106725 2630 #define RTC_CR_SUB1H 0x00020000U
Kojto 122:f9eeca106725 2631 #define RTC_CR_ADD1H 0x00010000U
Kojto 122:f9eeca106725 2632 #define RTC_CR_TSIE 0x00008000U
Kojto 122:f9eeca106725 2633 #define RTC_CR_WUTIE 0x00004000U
Kojto 122:f9eeca106725 2634 #define RTC_CR_ALRBIE 0x00002000U
Kojto 122:f9eeca106725 2635 #define RTC_CR_ALRAIE 0x00001000U
Kojto 122:f9eeca106725 2636 #define RTC_CR_TSE 0x00000800U
Kojto 122:f9eeca106725 2637 #define RTC_CR_WUTE 0x00000400U
Kojto 122:f9eeca106725 2638 #define RTC_CR_ALRBE 0x00000200U
Kojto 122:f9eeca106725 2639 #define RTC_CR_ALRAE 0x00000100U
Kojto 122:f9eeca106725 2640 #define RTC_CR_DCE 0x00000080U
Kojto 122:f9eeca106725 2641 #define RTC_CR_FMT 0x00000040U
Kojto 122:f9eeca106725 2642 #define RTC_CR_BYPSHAD 0x00000020U
Kojto 122:f9eeca106725 2643 #define RTC_CR_REFCKON 0x00000010U
Kojto 122:f9eeca106725 2644 #define RTC_CR_TSEDGE 0x00000008U
Kojto 122:f9eeca106725 2645 #define RTC_CR_WUCKSEL 0x00000007U
Kojto 122:f9eeca106725 2646 #define RTC_CR_WUCKSEL_0 0x00000001U
Kojto 122:f9eeca106725 2647 #define RTC_CR_WUCKSEL_1 0x00000002U
Kojto 122:f9eeca106725 2648 #define RTC_CR_WUCKSEL_2 0x00000004U
Kojto 93:e188a91d3eaa 2649
Kojto 93:e188a91d3eaa 2650 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 2651 #define RTC_ISR_RECALPF 0x00010000U
Kojto 122:f9eeca106725 2652 #define RTC_ISR_TAMP1F 0x00002000U
Kojto 122:f9eeca106725 2653 #define RTC_ISR_TAMP2F 0x00004000U
Kojto 122:f9eeca106725 2654 #define RTC_ISR_TSOVF 0x00001000U
Kojto 122:f9eeca106725 2655 #define RTC_ISR_TSF 0x00000800U
Kojto 122:f9eeca106725 2656 #define RTC_ISR_WUTF 0x00000400U
Kojto 122:f9eeca106725 2657 #define RTC_ISR_ALRBF 0x00000200U
Kojto 122:f9eeca106725 2658 #define RTC_ISR_ALRAF 0x00000100U
Kojto 122:f9eeca106725 2659 #define RTC_ISR_INIT 0x00000080U
Kojto 122:f9eeca106725 2660 #define RTC_ISR_INITF 0x00000040U
Kojto 122:f9eeca106725 2661 #define RTC_ISR_RSF 0x00000020U
Kojto 122:f9eeca106725 2662 #define RTC_ISR_INITS 0x00000010U
Kojto 122:f9eeca106725 2663 #define RTC_ISR_SHPF 0x00000008U
Kojto 122:f9eeca106725 2664 #define RTC_ISR_WUTWF 0x00000004U
Kojto 122:f9eeca106725 2665 #define RTC_ISR_ALRBWF 0x00000002U
Kojto 122:f9eeca106725 2666 #define RTC_ISR_ALRAWF 0x00000001U
Kojto 93:e188a91d3eaa 2667
Kojto 93:e188a91d3eaa 2668 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 2669 #define RTC_PRER_PREDIV_A 0x007F0000U
Kojto 122:f9eeca106725 2670 #define RTC_PRER_PREDIV_S 0x00007FFFU
Kojto 93:e188a91d3eaa 2671
Kojto 93:e188a91d3eaa 2672 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 2673 #define RTC_WUTR_WUT 0x0000FFFFU
Kojto 93:e188a91d3eaa 2674
Kojto 93:e188a91d3eaa 2675 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 122:f9eeca106725 2676 #define RTC_CALIBR_DCS 0x00000080U
Kojto 122:f9eeca106725 2677 #define RTC_CALIBR_DC 0x0000001FU
Kojto 93:e188a91d3eaa 2678
Kojto 93:e188a91d3eaa 2679 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 2680 #define RTC_ALRMAR_MSK4 0x80000000U
Kojto 122:f9eeca106725 2681 #define RTC_ALRMAR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 2682 #define RTC_ALRMAR_DT 0x30000000U
Kojto 122:f9eeca106725 2683 #define RTC_ALRMAR_DT_0 0x10000000U
Kojto 122:f9eeca106725 2684 #define RTC_ALRMAR_DT_1 0x20000000U
Kojto 122:f9eeca106725 2685 #define RTC_ALRMAR_DU 0x0F000000U
Kojto 122:f9eeca106725 2686 #define RTC_ALRMAR_DU_0 0x01000000U
Kojto 122:f9eeca106725 2687 #define RTC_ALRMAR_DU_1 0x02000000U
Kojto 122:f9eeca106725 2688 #define RTC_ALRMAR_DU_2 0x04000000U
Kojto 122:f9eeca106725 2689 #define RTC_ALRMAR_DU_3 0x08000000U
Kojto 122:f9eeca106725 2690 #define RTC_ALRMAR_MSK3 0x00800000U
Kojto 122:f9eeca106725 2691 #define RTC_ALRMAR_PM 0x00400000U
Kojto 122:f9eeca106725 2692 #define RTC_ALRMAR_HT 0x00300000U
Kojto 122:f9eeca106725 2693 #define RTC_ALRMAR_HT_0 0x00100000U
Kojto 122:f9eeca106725 2694 #define RTC_ALRMAR_HT_1 0x00200000U
Kojto 122:f9eeca106725 2695 #define RTC_ALRMAR_HU 0x000F0000U
Kojto 122:f9eeca106725 2696 #define RTC_ALRMAR_HU_0 0x00010000U
Kojto 122:f9eeca106725 2697 #define RTC_ALRMAR_HU_1 0x00020000U
Kojto 122:f9eeca106725 2698 #define RTC_ALRMAR_HU_2 0x00040000U
Kojto 122:f9eeca106725 2699 #define RTC_ALRMAR_HU_3 0x00080000U
Kojto 122:f9eeca106725 2700 #define RTC_ALRMAR_MSK2 0x00008000U
Kojto 122:f9eeca106725 2701 #define RTC_ALRMAR_MNT 0x00007000U
Kojto 122:f9eeca106725 2702 #define RTC_ALRMAR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 2703 #define RTC_ALRMAR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 2704 #define RTC_ALRMAR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 2705 #define RTC_ALRMAR_MNU 0x00000F00U
Kojto 122:f9eeca106725 2706 #define RTC_ALRMAR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 2707 #define RTC_ALRMAR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 2708 #define RTC_ALRMAR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 2709 #define RTC_ALRMAR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 2710 #define RTC_ALRMAR_MSK1 0x00000080U
Kojto 122:f9eeca106725 2711 #define RTC_ALRMAR_ST 0x00000070U
Kojto 122:f9eeca106725 2712 #define RTC_ALRMAR_ST_0 0x00000010U
Kojto 122:f9eeca106725 2713 #define RTC_ALRMAR_ST_1 0x00000020U
Kojto 122:f9eeca106725 2714 #define RTC_ALRMAR_ST_2 0x00000040U
Kojto 122:f9eeca106725 2715 #define RTC_ALRMAR_SU 0x0000000FU
Kojto 122:f9eeca106725 2716 #define RTC_ALRMAR_SU_0 0x00000001U
Kojto 122:f9eeca106725 2717 #define RTC_ALRMAR_SU_1 0x00000002U
Kojto 122:f9eeca106725 2718 #define RTC_ALRMAR_SU_2 0x00000004U
Kojto 122:f9eeca106725 2719 #define RTC_ALRMAR_SU_3 0x00000008U
Kojto 93:e188a91d3eaa 2720
Kojto 93:e188a91d3eaa 2721 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 2722 #define RTC_ALRMBR_MSK4 0x80000000U
Kojto 122:f9eeca106725 2723 #define RTC_ALRMBR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 2724 #define RTC_ALRMBR_DT 0x30000000U
Kojto 122:f9eeca106725 2725 #define RTC_ALRMBR_DT_0 0x10000000U
Kojto 122:f9eeca106725 2726 #define RTC_ALRMBR_DT_1 0x20000000U
Kojto 122:f9eeca106725 2727 #define RTC_ALRMBR_DU 0x0F000000U
Kojto 122:f9eeca106725 2728 #define RTC_ALRMBR_DU_0 0x01000000U
Kojto 122:f9eeca106725 2729 #define RTC_ALRMBR_DU_1 0x02000000U
Kojto 122:f9eeca106725 2730 #define RTC_ALRMBR_DU_2 0x04000000U
Kojto 122:f9eeca106725 2731 #define RTC_ALRMBR_DU_3 0x08000000U
Kojto 122:f9eeca106725 2732 #define RTC_ALRMBR_MSK3 0x00800000U
Kojto 122:f9eeca106725 2733 #define RTC_ALRMBR_PM 0x00400000U
Kojto 122:f9eeca106725 2734 #define RTC_ALRMBR_HT 0x00300000U
Kojto 122:f9eeca106725 2735 #define RTC_ALRMBR_HT_0 0x00100000U
Kojto 122:f9eeca106725 2736 #define RTC_ALRMBR_HT_1 0x00200000U
Kojto 122:f9eeca106725 2737 #define RTC_ALRMBR_HU 0x000F0000U
Kojto 122:f9eeca106725 2738 #define RTC_ALRMBR_HU_0 0x00010000U
Kojto 122:f9eeca106725 2739 #define RTC_ALRMBR_HU_1 0x00020000U
Kojto 122:f9eeca106725 2740 #define RTC_ALRMBR_HU_2 0x00040000U
Kojto 122:f9eeca106725 2741 #define RTC_ALRMBR_HU_3 0x00080000U
Kojto 122:f9eeca106725 2742 #define RTC_ALRMBR_MSK2 0x00008000U
Kojto 122:f9eeca106725 2743 #define RTC_ALRMBR_MNT 0x00007000U
Kojto 122:f9eeca106725 2744 #define RTC_ALRMBR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 2745 #define RTC_ALRMBR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 2746 #define RTC_ALRMBR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 2747 #define RTC_ALRMBR_MNU 0x00000F00U
Kojto 122:f9eeca106725 2748 #define RTC_ALRMBR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 2749 #define RTC_ALRMBR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 2750 #define RTC_ALRMBR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 2751 #define RTC_ALRMBR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 2752 #define RTC_ALRMBR_MSK1 0x00000080U
Kojto 122:f9eeca106725 2753 #define RTC_ALRMBR_ST 0x00000070U
Kojto 122:f9eeca106725 2754 #define RTC_ALRMBR_ST_0 0x00000010U
Kojto 122:f9eeca106725 2755 #define RTC_ALRMBR_ST_1 0x00000020U
Kojto 122:f9eeca106725 2756 #define RTC_ALRMBR_ST_2 0x00000040U
Kojto 122:f9eeca106725 2757 #define RTC_ALRMBR_SU 0x0000000FU
Kojto 122:f9eeca106725 2758 #define RTC_ALRMBR_SU_0 0x00000001U
Kojto 122:f9eeca106725 2759 #define RTC_ALRMBR_SU_1 0x00000002U
Kojto 122:f9eeca106725 2760 #define RTC_ALRMBR_SU_2 0x00000004U
Kojto 122:f9eeca106725 2761 #define RTC_ALRMBR_SU_3 0x00000008U
Kojto 93:e188a91d3eaa 2762
Kojto 93:e188a91d3eaa 2763 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 2764 #define RTC_WPR_KEY 0x000000FFU
Kojto 93:e188a91d3eaa 2765
Kojto 93:e188a91d3eaa 2766 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 2767 #define RTC_SSR_SS 0x0000FFFFU
Kojto 93:e188a91d3eaa 2768
Kojto 93:e188a91d3eaa 2769 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 2770 #define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto 122:f9eeca106725 2771 #define RTC_SHIFTR_ADD1S 0x80000000U
Kojto 93:e188a91d3eaa 2772
Kojto 93:e188a91d3eaa 2773 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 2774 #define RTC_TSTR_PM 0x00400000U
Kojto 122:f9eeca106725 2775 #define RTC_TSTR_HT 0x00300000U
Kojto 122:f9eeca106725 2776 #define RTC_TSTR_HT_0 0x00100000U
Kojto 122:f9eeca106725 2777 #define RTC_TSTR_HT_1 0x00200000U
Kojto 122:f9eeca106725 2778 #define RTC_TSTR_HU 0x000F0000U
Kojto 122:f9eeca106725 2779 #define RTC_TSTR_HU_0 0x00010000U
Kojto 122:f9eeca106725 2780 #define RTC_TSTR_HU_1 0x00020000U
Kojto 122:f9eeca106725 2781 #define RTC_TSTR_HU_2 0x00040000U
Kojto 122:f9eeca106725 2782 #define RTC_TSTR_HU_3 0x00080000U
Kojto 122:f9eeca106725 2783 #define RTC_TSTR_MNT 0x00007000U
Kojto 122:f9eeca106725 2784 #define RTC_TSTR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 2785 #define RTC_TSTR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 2786 #define RTC_TSTR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 2787 #define RTC_TSTR_MNU 0x00000F00U
Kojto 122:f9eeca106725 2788 #define RTC_TSTR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 2789 #define RTC_TSTR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 2790 #define RTC_TSTR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 2791 #define RTC_TSTR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 2792 #define RTC_TSTR_ST 0x00000070U
Kojto 122:f9eeca106725 2793 #define RTC_TSTR_ST_0 0x00000010U
Kojto 122:f9eeca106725 2794 #define RTC_TSTR_ST_1 0x00000020U
Kojto 122:f9eeca106725 2795 #define RTC_TSTR_ST_2 0x00000040U
Kojto 122:f9eeca106725 2796 #define RTC_TSTR_SU 0x0000000FU
Kojto 122:f9eeca106725 2797 #define RTC_TSTR_SU_0 0x00000001U
Kojto 122:f9eeca106725 2798 #define RTC_TSTR_SU_1 0x00000002U
Kojto 122:f9eeca106725 2799 #define RTC_TSTR_SU_2 0x00000004U
Kojto 122:f9eeca106725 2800 #define RTC_TSTR_SU_3 0x00000008U
Kojto 93:e188a91d3eaa 2801
Kojto 93:e188a91d3eaa 2802 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 2803 #define RTC_TSDR_WDU 0x0000E000U
Kojto 122:f9eeca106725 2804 #define RTC_TSDR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 2805 #define RTC_TSDR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 2806 #define RTC_TSDR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 2807 #define RTC_TSDR_MT 0x00001000U
Kojto 122:f9eeca106725 2808 #define RTC_TSDR_MU 0x00000F00U
Kojto 122:f9eeca106725 2809 #define RTC_TSDR_MU_0 0x00000100U
Kojto 122:f9eeca106725 2810 #define RTC_TSDR_MU_1 0x00000200U
Kojto 122:f9eeca106725 2811 #define RTC_TSDR_MU_2 0x00000400U
Kojto 122:f9eeca106725 2812 #define RTC_TSDR_MU_3 0x00000800U
Kojto 122:f9eeca106725 2813 #define RTC_TSDR_DT 0x00000030U
Kojto 122:f9eeca106725 2814 #define RTC_TSDR_DT_0 0x00000010U
Kojto 122:f9eeca106725 2815 #define RTC_TSDR_DT_1 0x00000020U
Kojto 122:f9eeca106725 2816 #define RTC_TSDR_DU 0x0000000FU
Kojto 122:f9eeca106725 2817 #define RTC_TSDR_DU_0 0x00000001U
Kojto 122:f9eeca106725 2818 #define RTC_TSDR_DU_1 0x00000002U
Kojto 122:f9eeca106725 2819 #define RTC_TSDR_DU_2 0x00000004U
Kojto 122:f9eeca106725 2820 #define RTC_TSDR_DU_3 0x00000008U
Kojto 93:e188a91d3eaa 2821
Kojto 93:e188a91d3eaa 2822 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 2823 #define RTC_TSSSR_SS 0x0000FFFFU
Kojto 93:e188a91d3eaa 2824
Kojto 93:e188a91d3eaa 2825 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 2826 #define RTC_CALR_CALP 0x00008000U
Kojto 122:f9eeca106725 2827 #define RTC_CALR_CALW8 0x00004000U
Kojto 122:f9eeca106725 2828 #define RTC_CALR_CALW16 0x00002000U
Kojto 122:f9eeca106725 2829 #define RTC_CALR_CALM 0x000001FFU
Kojto 122:f9eeca106725 2830 #define RTC_CALR_CALM_0 0x00000001U
Kojto 122:f9eeca106725 2831 #define RTC_CALR_CALM_1 0x00000002U
Kojto 122:f9eeca106725 2832 #define RTC_CALR_CALM_2 0x00000004U
Kojto 122:f9eeca106725 2833 #define RTC_CALR_CALM_3 0x00000008U
Kojto 122:f9eeca106725 2834 #define RTC_CALR_CALM_4 0x00000010U
Kojto 122:f9eeca106725 2835 #define RTC_CALR_CALM_5 0x00000020U
Kojto 122:f9eeca106725 2836 #define RTC_CALR_CALM_6 0x00000040U
Kojto 122:f9eeca106725 2837 #define RTC_CALR_CALM_7 0x00000080U
Kojto 122:f9eeca106725 2838 #define RTC_CALR_CALM_8 0x00000100U
Kojto 93:e188a91d3eaa 2839
Kojto 93:e188a91d3eaa 2840 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 122:f9eeca106725 2841 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
Kojto 122:f9eeca106725 2842 #define RTC_TAFCR_TSINSEL 0x00020000U
Kojto 122:f9eeca106725 2843 #define RTC_TAFCR_TAMPINSEL 0x00010000U
Kojto 122:f9eeca106725 2844 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
Kojto 122:f9eeca106725 2845 #define RTC_TAFCR_TAMPPRCH 0x00006000U
Kojto 122:f9eeca106725 2846 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
Kojto 122:f9eeca106725 2847 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
Kojto 122:f9eeca106725 2848 #define RTC_TAFCR_TAMPFLT 0x00001800U
Kojto 122:f9eeca106725 2849 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
Kojto 122:f9eeca106725 2850 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
Kojto 122:f9eeca106725 2851 #define RTC_TAFCR_TAMPFREQ 0x00000700U
Kojto 122:f9eeca106725 2852 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
Kojto 122:f9eeca106725 2853 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
Kojto 122:f9eeca106725 2854 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
Kojto 122:f9eeca106725 2855 #define RTC_TAFCR_TAMPTS 0x00000080U
Kojto 122:f9eeca106725 2856 #define RTC_TAFCR_TAMP2TRG 0x00000010U
Kojto 122:f9eeca106725 2857 #define RTC_TAFCR_TAMP2E 0x00000008U
Kojto 122:f9eeca106725 2858 #define RTC_TAFCR_TAMPIE 0x00000004U
Kojto 122:f9eeca106725 2859 #define RTC_TAFCR_TAMP1TRG 0x00000002U
Kojto 122:f9eeca106725 2860 #define RTC_TAFCR_TAMP1E 0x00000001U
Kojto 93:e188a91d3eaa 2861
Kojto 93:e188a91d3eaa 2862 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 2863 #define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 2864 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 2865 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 2866 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 2867 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 2868 #define RTC_ALRMASSR_SS 0x00007FFFU
Kojto 93:e188a91d3eaa 2869
Kojto 93:e188a91d3eaa 2870 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 2871 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 2872 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 2873 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 2874 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 2875 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 2876 #define RTC_ALRMBSSR_SS 0x00007FFFU
Kojto 93:e188a91d3eaa 2877
Kojto 93:e188a91d3eaa 2878 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 2879 #define RTC_BKP0R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2880
Kojto 93:e188a91d3eaa 2881 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 2882 #define RTC_BKP1R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2883
Kojto 93:e188a91d3eaa 2884 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 2885 #define RTC_BKP2R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2886
Kojto 93:e188a91d3eaa 2887 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 2888 #define RTC_BKP3R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2889
Kojto 93:e188a91d3eaa 2890 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 2891 #define RTC_BKP4R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2892
Kojto 93:e188a91d3eaa 2893 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 2894 #define RTC_BKP5R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2895
Kojto 93:e188a91d3eaa 2896 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 2897 #define RTC_BKP6R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2898
Kojto 93:e188a91d3eaa 2899 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 2900 #define RTC_BKP7R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2901
Kojto 93:e188a91d3eaa 2902 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 2903 #define RTC_BKP8R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2904
Kojto 93:e188a91d3eaa 2905 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 2906 #define RTC_BKP9R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2907
Kojto 93:e188a91d3eaa 2908 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 2909 #define RTC_BKP10R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2910
Kojto 93:e188a91d3eaa 2911 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 2912 #define RTC_BKP11R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2913
Kojto 93:e188a91d3eaa 2914 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 2915 #define RTC_BKP12R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2916
Kojto 93:e188a91d3eaa 2917 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 2918 #define RTC_BKP13R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2919
Kojto 93:e188a91d3eaa 2920 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 2921 #define RTC_BKP14R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2922
Kojto 93:e188a91d3eaa 2923 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 2924 #define RTC_BKP15R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2925
Kojto 93:e188a91d3eaa 2926 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 2927 #define RTC_BKP16R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2928
Kojto 93:e188a91d3eaa 2929 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 2930 #define RTC_BKP17R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2931
Kojto 93:e188a91d3eaa 2932 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 2933 #define RTC_BKP18R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2934
Kojto 93:e188a91d3eaa 2935 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 2936 #define RTC_BKP19R 0xFFFFFFFFU
Kojto 93:e188a91d3eaa 2937
Kojto 93:e188a91d3eaa 2938
Kojto 93:e188a91d3eaa 2939
Kojto 93:e188a91d3eaa 2940 /******************************************************************************/
Kojto 93:e188a91d3eaa 2941 /* */
Kojto 93:e188a91d3eaa 2942 /* SD host Interface */
Kojto 93:e188a91d3eaa 2943 /* */
Kojto 93:e188a91d3eaa 2944 /******************************************************************************/
Kojto 93:e188a91d3eaa 2945 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 122:f9eeca106725 2946 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 122:f9eeca106725 2947 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 2948 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2949
Kojto 93:e188a91d3eaa 2950 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 122:f9eeca106725 2951 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
Kojto 122:f9eeca106725 2952 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
Kojto 122:f9eeca106725 2953 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
Kojto 122:f9eeca106725 2954 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
Kojto 122:f9eeca106725 2955
Kojto 122:f9eeca106725 2956 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 122:f9eeca106725 2957 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
Kojto 122:f9eeca106725 2958 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2959
Kojto 122:f9eeca106725 2960 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
Kojto 122:f9eeca106725 2961 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
Kojto 93:e188a91d3eaa 2962
Kojto 93:e188a91d3eaa 2963 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 122:f9eeca106725 2964 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
Kojto 93:e188a91d3eaa 2965
Kojto 93:e188a91d3eaa 2966 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 122:f9eeca106725 2967 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
Kojto 122:f9eeca106725 2968
Kojto 122:f9eeca106725 2969 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 122:f9eeca106725 2970 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
Kojto 122:f9eeca106725 2971 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
Kojto 122:f9eeca106725 2972
Kojto 122:f9eeca106725 2973 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
Kojto 122:f9eeca106725 2974 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 122:f9eeca106725 2975 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
Kojto 122:f9eeca106725 2976 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
Kojto 122:f9eeca106725 2977 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
Kojto 122:f9eeca106725 2978 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
Kojto 122:f9eeca106725 2979 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
Kojto 93:e188a91d3eaa 2980
Kojto 93:e188a91d3eaa 2981 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 122:f9eeca106725 2982 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
Kojto 93:e188a91d3eaa 2983
Kojto 93:e188a91d3eaa 2984 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 122:f9eeca106725 2985 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
Kojto 93:e188a91d3eaa 2986
Kojto 93:e188a91d3eaa 2987 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 122:f9eeca106725 2988 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
Kojto 93:e188a91d3eaa 2989
Kojto 93:e188a91d3eaa 2990 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 122:f9eeca106725 2991 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
Kojto 93:e188a91d3eaa 2992
Kojto 93:e188a91d3eaa 2993 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 122:f9eeca106725 2994 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
Kojto 93:e188a91d3eaa 2995
Kojto 93:e188a91d3eaa 2996 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 122:f9eeca106725 2997 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
Kojto 93:e188a91d3eaa 2998
Kojto 93:e188a91d3eaa 2999 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 122:f9eeca106725 3000 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
Kojto 93:e188a91d3eaa 3001
Kojto 93:e188a91d3eaa 3002 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 122:f9eeca106725 3003 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
Kojto 93:e188a91d3eaa 3004
Kojto 93:e188a91d3eaa 3005 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 122:f9eeca106725 3006 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
Kojto 122:f9eeca106725 3007 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
Kojto 122:f9eeca106725 3008 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
Kojto 122:f9eeca106725 3009 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
Kojto 122:f9eeca106725 3010
Kojto 122:f9eeca106725 3011 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 122:f9eeca106725 3012 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3013 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3014 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3015 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3016
Kojto 122:f9eeca106725 3017 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
Kojto 122:f9eeca106725 3018 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
Kojto 122:f9eeca106725 3019 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
Kojto 122:f9eeca106725 3020 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
Kojto 93:e188a91d3eaa 3021
Kojto 93:e188a91d3eaa 3022 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 122:f9eeca106725 3023 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
Kojto 93:e188a91d3eaa 3024
Kojto 93:e188a91d3eaa 3025 /****************** Bit definition for SDIO_STA register ********************/
Kojto 122:f9eeca106725 3026 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
Kojto 122:f9eeca106725 3027 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
Kojto 122:f9eeca106725 3028 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
Kojto 122:f9eeca106725 3029 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
Kojto 122:f9eeca106725 3030 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
Kojto 122:f9eeca106725 3031 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
Kojto 122:f9eeca106725 3032 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
Kojto 122:f9eeca106725 3033 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
Kojto 122:f9eeca106725 3034 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 122:f9eeca106725 3035 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
Kojto 122:f9eeca106725 3036 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
Kojto 122:f9eeca106725 3037 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
Kojto 122:f9eeca106725 3038 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
Kojto 122:f9eeca106725 3039 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
Kojto 122:f9eeca106725 3040 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 122:f9eeca106725 3041 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 122:f9eeca106725 3042 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
Kojto 122:f9eeca106725 3043 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
Kojto 122:f9eeca106725 3044 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
Kojto 122:f9eeca106725 3045 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
Kojto 122:f9eeca106725 3046 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
Kojto 122:f9eeca106725 3047 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
Kojto 122:f9eeca106725 3048 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
Kojto 122:f9eeca106725 3049 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
Kojto 93:e188a91d3eaa 3050
Kojto 93:e188a91d3eaa 3051 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 122:f9eeca106725 3052 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 3053 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 3054 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 3055 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 3056 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
Kojto 122:f9eeca106725 3057 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
Kojto 122:f9eeca106725 3058 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
Kojto 122:f9eeca106725 3059 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
Kojto 122:f9eeca106725 3060 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
Kojto 122:f9eeca106725 3061 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
Kojto 122:f9eeca106725 3062 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
Kojto 122:f9eeca106725 3063 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
Kojto 122:f9eeca106725 3064 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
Kojto 93:e188a91d3eaa 3065
Kojto 93:e188a91d3eaa 3066 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 122:f9eeca106725 3067 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 3068 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 3069 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 3070 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 3071 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 122:f9eeca106725 3072 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 122:f9eeca106725 3073 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
Kojto 122:f9eeca106725 3074 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
Kojto 122:f9eeca106725 3075 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
Kojto 122:f9eeca106725 3076 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
Kojto 122:f9eeca106725 3077 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
Kojto 122:f9eeca106725 3078 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
Kojto 122:f9eeca106725 3079 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
Kojto 122:f9eeca106725 3080 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
Kojto 122:f9eeca106725 3081 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 122:f9eeca106725 3082 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
Kojto 122:f9eeca106725 3083 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 3084 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 3085 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 3086 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 3087 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
Kojto 122:f9eeca106725 3088 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
Kojto 122:f9eeca106725 3089 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 122:f9eeca106725 3090 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
Kojto 93:e188a91d3eaa 3091
Kojto 93:e188a91d3eaa 3092 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 122:f9eeca106725 3093 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 93:e188a91d3eaa 3094
Kojto 93:e188a91d3eaa 3095 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 122:f9eeca106725 3096 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
Kojto 93:e188a91d3eaa 3097
Kojto 93:e188a91d3eaa 3098 /******************************************************************************/
Kojto 93:e188a91d3eaa 3099 /* */
Kojto 93:e188a91d3eaa 3100 /* Serial Peripheral Interface */
Kojto 93:e188a91d3eaa 3101 /* */
Kojto 93:e188a91d3eaa 3102 /******************************************************************************/
Kojto 93:e188a91d3eaa 3103 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 3104 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
Kojto 122:f9eeca106725 3105 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
Kojto 122:f9eeca106725 3106 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
Kojto 122:f9eeca106725 3107
Kojto 122:f9eeca106725 3108 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 3109 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 3110 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 3111 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 3112
Kojto 122:f9eeca106725 3113 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
Kojto 122:f9eeca106725 3114 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
Kojto 122:f9eeca106725 3115 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
Kojto 122:f9eeca106725 3116 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
Kojto 122:f9eeca106725 3117 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
Kojto 122:f9eeca106725 3118 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
Kojto 122:f9eeca106725 3119 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
Kojto 122:f9eeca106725 3120 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
Kojto 122:f9eeca106725 3121 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
Kojto 122:f9eeca106725 3122 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
Kojto 93:e188a91d3eaa 3123
Kojto 93:e188a91d3eaa 3124 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 3125 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 3126 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 3127 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
Kojto 122:f9eeca106725 3128 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
Kojto 122:f9eeca106725 3129 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 3130 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 3131 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
Kojto 93:e188a91d3eaa 3132
Kojto 93:e188a91d3eaa 3133 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 3134 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
Kojto 122:f9eeca106725 3135 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
Kojto 122:f9eeca106725 3136 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
Kojto 122:f9eeca106725 3137 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
Kojto 122:f9eeca106725 3138 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
Kojto 122:f9eeca106725 3139 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
Kojto 122:f9eeca106725 3140 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
Kojto 122:f9eeca106725 3141 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
Kojto 122:f9eeca106725 3142 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
Kojto 93:e188a91d3eaa 3143
Kojto 93:e188a91d3eaa 3144 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 3145 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
Kojto 93:e188a91d3eaa 3146
Kojto 93:e188a91d3eaa 3147 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 3148 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
Kojto 93:e188a91d3eaa 3149
Kojto 93:e188a91d3eaa 3150 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 3151 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
Kojto 93:e188a91d3eaa 3152
Kojto 93:e188a91d3eaa 3153 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 3154 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
Kojto 93:e188a91d3eaa 3155
Kojto 93:e188a91d3eaa 3156 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 122:f9eeca106725 3157 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 3158
Kojto 122:f9eeca106725 3159 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 3160 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 3161 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 3162
Kojto 122:f9eeca106725 3163 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
Kojto 122:f9eeca106725 3164
Kojto 122:f9eeca106725 3165 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 3166 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3167 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3168
Kojto 122:f9eeca106725 3169 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 3170
Kojto 122:f9eeca106725 3171 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 3172 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3173 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3174
Kojto 122:f9eeca106725 3175 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
Kojto 122:f9eeca106725 3176 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
Kojto 93:e188a91d3eaa 3177
Kojto 93:e188a91d3eaa 3178 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 122:f9eeca106725 3179 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 3180 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 3181 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
Kojto 93:e188a91d3eaa 3182
Kojto 93:e188a91d3eaa 3183 /******************************************************************************/
Kojto 93:e188a91d3eaa 3184 /* */
Kojto 93:e188a91d3eaa 3185 /* SYSCFG */
Kojto 93:e188a91d3eaa 3186 /* */
Kojto 93:e188a91d3eaa 3187 /******************************************************************************/
Kojto 93:e188a91d3eaa 3188 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 122:f9eeca106725 3189 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 3190 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
Kojto 122:f9eeca106725 3191 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
Kojto 122:f9eeca106725 3192 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
Kojto 93:e188a91d3eaa 3193
Kojto 93:e188a91d3eaa 3194 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 122:f9eeca106725 3195 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
Kojto 93:e188a91d3eaa 3196
Kojto 93:e188a91d3eaa 3197 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 3198 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
Kojto 122:f9eeca106725 3199 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
Kojto 122:f9eeca106725 3200 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
Kojto 122:f9eeca106725 3201 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
Kojto 93:e188a91d3eaa 3202 /**
Kojto 93:e188a91d3eaa 3203 * @brief EXTI0 configuration
Kojto 93:e188a91d3eaa 3204 */
Kojto 122:f9eeca106725 3205 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
Kojto 122:f9eeca106725 3206 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
Kojto 122:f9eeca106725 3207 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
Kojto 122:f9eeca106725 3208 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
Kojto 122:f9eeca106725 3209 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
Kojto 122:f9eeca106725 3210 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
Kojto 93:e188a91d3eaa 3211
Kojto 93:e188a91d3eaa 3212 /**
Kojto 93:e188a91d3eaa 3213 * @brief EXTI1 configuration
Kojto 93:e188a91d3eaa 3214 */
Kojto 122:f9eeca106725 3215 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
Kojto 122:f9eeca106725 3216 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
Kojto 122:f9eeca106725 3217 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
Kojto 122:f9eeca106725 3218 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
Kojto 122:f9eeca106725 3219 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
Kojto 122:f9eeca106725 3220 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
Kojto 93:e188a91d3eaa 3221
Kojto 93:e188a91d3eaa 3222 /**
Kojto 93:e188a91d3eaa 3223 * @brief EXTI2 configuration
Kojto 93:e188a91d3eaa 3224 */
Kojto 122:f9eeca106725 3225 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
Kojto 122:f9eeca106725 3226 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
Kojto 122:f9eeca106725 3227 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
Kojto 122:f9eeca106725 3228 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
Kojto 122:f9eeca106725 3229 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
Kojto 122:f9eeca106725 3230 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
Kojto 93:e188a91d3eaa 3231
Kojto 93:e188a91d3eaa 3232 /**
Kojto 93:e188a91d3eaa 3233 * @brief EXTI3 configuration
Kojto 93:e188a91d3eaa 3234 */
Kojto 122:f9eeca106725 3235 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
Kojto 122:f9eeca106725 3236 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
Kojto 122:f9eeca106725 3237 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
Kojto 122:f9eeca106725 3238 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
Kojto 122:f9eeca106725 3239 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
Kojto 122:f9eeca106725 3240 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
Kojto 93:e188a91d3eaa 3241
Kojto 93:e188a91d3eaa 3242 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 3243 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
Kojto 122:f9eeca106725 3244 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
Kojto 122:f9eeca106725 3245 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
Kojto 122:f9eeca106725 3246 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
Kojto 93:e188a91d3eaa 3247 /**
Kojto 93:e188a91d3eaa 3248 * @brief EXTI4 configuration
Kojto 93:e188a91d3eaa 3249 */
Kojto 122:f9eeca106725 3250 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
Kojto 122:f9eeca106725 3251 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
Kojto 122:f9eeca106725 3252 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
Kojto 122:f9eeca106725 3253 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
Kojto 122:f9eeca106725 3254 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
Kojto 122:f9eeca106725 3255 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
Kojto 93:e188a91d3eaa 3256
Kojto 93:e188a91d3eaa 3257 /**
Kojto 93:e188a91d3eaa 3258 * @brief EXTI5 configuration
Kojto 93:e188a91d3eaa 3259 */
Kojto 122:f9eeca106725 3260 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
Kojto 122:f9eeca106725 3261 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
Kojto 122:f9eeca106725 3262 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
Kojto 122:f9eeca106725 3263 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
Kojto 122:f9eeca106725 3264 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
Kojto 122:f9eeca106725 3265 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
Kojto 93:e188a91d3eaa 3266
Kojto 93:e188a91d3eaa 3267 /**
Kojto 93:e188a91d3eaa 3268 * @brief EXTI6 configuration
Kojto 93:e188a91d3eaa 3269 */
Kojto 122:f9eeca106725 3270 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
Kojto 122:f9eeca106725 3271 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
Kojto 122:f9eeca106725 3272 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
Kojto 122:f9eeca106725 3273 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
Kojto 122:f9eeca106725 3274 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
Kojto 122:f9eeca106725 3275 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
Kojto 93:e188a91d3eaa 3276
Kojto 93:e188a91d3eaa 3277 /**
Kojto 93:e188a91d3eaa 3278 * @brief EXTI7 configuration
Kojto 93:e188a91d3eaa 3279 */
Kojto 122:f9eeca106725 3280 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
Kojto 122:f9eeca106725 3281 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
Kojto 122:f9eeca106725 3282 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
Kojto 122:f9eeca106725 3283 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
Kojto 122:f9eeca106725 3284 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
Kojto 122:f9eeca106725 3285 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
Kojto 93:e188a91d3eaa 3286
Kojto 93:e188a91d3eaa 3287
Kojto 93:e188a91d3eaa 3288 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 3289 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
Kojto 122:f9eeca106725 3290 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
Kojto 122:f9eeca106725 3291 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
Kojto 122:f9eeca106725 3292 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
Kojto 93:e188a91d3eaa 3293
Kojto 93:e188a91d3eaa 3294 /**
Kojto 93:e188a91d3eaa 3295 * @brief EXTI8 configuration
Kojto 93:e188a91d3eaa 3296 */
Kojto 122:f9eeca106725 3297 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
Kojto 122:f9eeca106725 3298 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
Kojto 122:f9eeca106725 3299 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
Kojto 122:f9eeca106725 3300 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
Kojto 122:f9eeca106725 3301 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
Kojto 122:f9eeca106725 3302 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
Kojto 93:e188a91d3eaa 3303
Kojto 93:e188a91d3eaa 3304 /**
Kojto 93:e188a91d3eaa 3305 * @brief EXTI9 configuration
Kojto 93:e188a91d3eaa 3306 */
Kojto 122:f9eeca106725 3307 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
Kojto 122:f9eeca106725 3308 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
Kojto 122:f9eeca106725 3309 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
Kojto 122:f9eeca106725 3310 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
Kojto 122:f9eeca106725 3311 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
Kojto 122:f9eeca106725 3312 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
Kojto 93:e188a91d3eaa 3313
Kojto 93:e188a91d3eaa 3314 /**
Kojto 93:e188a91d3eaa 3315 * @brief EXTI10 configuration
Kojto 93:e188a91d3eaa 3316 */
Kojto 122:f9eeca106725 3317 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
Kojto 122:f9eeca106725 3318 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
Kojto 122:f9eeca106725 3319 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
Kojto 122:f9eeca106725 3320 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
Kojto 122:f9eeca106725 3321 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
Kojto 122:f9eeca106725 3322 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
Kojto 93:e188a91d3eaa 3323
Kojto 93:e188a91d3eaa 3324 /**
Kojto 93:e188a91d3eaa 3325 * @brief EXTI11 configuration
Kojto 93:e188a91d3eaa 3326 */
Kojto 122:f9eeca106725 3327 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
Kojto 122:f9eeca106725 3328 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
Kojto 122:f9eeca106725 3329 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
Kojto 122:f9eeca106725 3330 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
Kojto 122:f9eeca106725 3331 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
Kojto 122:f9eeca106725 3332 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
Kojto 93:e188a91d3eaa 3333
Kojto 93:e188a91d3eaa 3334 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 122:f9eeca106725 3335 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
Kojto 122:f9eeca106725 3336 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
Kojto 122:f9eeca106725 3337 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
Kojto 122:f9eeca106725 3338 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
Kojto 93:e188a91d3eaa 3339 /**
Kojto 93:e188a91d3eaa 3340 * @brief EXTI12 configuration
Kojto 93:e188a91d3eaa 3341 */
Kojto 122:f9eeca106725 3342 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
Kojto 122:f9eeca106725 3343 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
Kojto 122:f9eeca106725 3344 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
Kojto 122:f9eeca106725 3345 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
Kojto 122:f9eeca106725 3346 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
Kojto 122:f9eeca106725 3347 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
Kojto 93:e188a91d3eaa 3348
Kojto 93:e188a91d3eaa 3349 /**
Kojto 93:e188a91d3eaa 3350 * @brief EXTI13 configuration
Kojto 93:e188a91d3eaa 3351 */
Kojto 122:f9eeca106725 3352 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
Kojto 122:f9eeca106725 3353 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
Kojto 122:f9eeca106725 3354 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
Kojto 122:f9eeca106725 3355 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
Kojto 122:f9eeca106725 3356 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
Kojto 122:f9eeca106725 3357 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
Kojto 93:e188a91d3eaa 3358
Kojto 93:e188a91d3eaa 3359 /**
Kojto 93:e188a91d3eaa 3360 * @brief EXTI14 configuration
Kojto 93:e188a91d3eaa 3361 */
Kojto 122:f9eeca106725 3362 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
Kojto 122:f9eeca106725 3363 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
Kojto 122:f9eeca106725 3364 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
Kojto 122:f9eeca106725 3365 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
Kojto 122:f9eeca106725 3366 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
Kojto 122:f9eeca106725 3367 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
Kojto 93:e188a91d3eaa 3368
Kojto 93:e188a91d3eaa 3369 /**
Kojto 93:e188a91d3eaa 3370 * @brief EXTI15 configuration
Kojto 93:e188a91d3eaa 3371 */
Kojto 122:f9eeca106725 3372 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
Kojto 122:f9eeca106725 3373 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
Kojto 122:f9eeca106725 3374 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
Kojto 122:f9eeca106725 3375 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
Kojto 122:f9eeca106725 3376 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
Kojto 122:f9eeca106725 3377 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
Kojto 93:e188a91d3eaa 3378
Kojto 93:e188a91d3eaa 3379 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 122:f9eeca106725 3380 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
Kojto 122:f9eeca106725 3381 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
Kojto 93:e188a91d3eaa 3382
Kojto 93:e188a91d3eaa 3383 /******************************************************************************/
Kojto 93:e188a91d3eaa 3384 /* */
Kojto 93:e188a91d3eaa 3385 /* TIM */
Kojto 93:e188a91d3eaa 3386 /* */
Kojto 93:e188a91d3eaa 3387 /******************************************************************************/
Kojto 93:e188a91d3eaa 3388 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 3389 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
Kojto 122:f9eeca106725 3390 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
Kojto 122:f9eeca106725 3391 #define TIM_CR1_URS 0x0004U /*!<Update request source */
Kojto 122:f9eeca106725 3392 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
Kojto 122:f9eeca106725 3393 #define TIM_CR1_DIR 0x0010U /*!<Direction */
Kojto 122:f9eeca106725 3394
Kojto 122:f9eeca106725 3395 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 3396 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
Kojto 122:f9eeca106725 3397 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
Kojto 122:f9eeca106725 3398
Kojto 122:f9eeca106725 3399 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 3400
Kojto 122:f9eeca106725 3401 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 3402 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3403 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3404
Kojto 93:e188a91d3eaa 3405 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 3406 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 3407 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 3408 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 3409
Kojto 122:f9eeca106725 3410 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 3411 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3412 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3413 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3414
Kojto 122:f9eeca106725 3415 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
Kojto 122:f9eeca106725 3416 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 3417 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 3418 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 3419 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 3420 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 3421 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 3422 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
Kojto 93:e188a91d3eaa 3423
Kojto 93:e188a91d3eaa 3424 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 3425 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 3426 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3427 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3428 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3429
Kojto 122:f9eeca106725 3430 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 3431 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3432 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3433 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3434
Kojto 122:f9eeca106725 3435 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
Kojto 122:f9eeca106725 3436
Kojto 122:f9eeca106725 3437 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 3438 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3439 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3440 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3441 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3442
Kojto 122:f9eeca106725 3443 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 3444 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3445 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3446
Kojto 122:f9eeca106725 3447 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
Kojto 122:f9eeca106725 3448 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
Kojto 93:e188a91d3eaa 3449
Kojto 93:e188a91d3eaa 3450 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 3451 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
Kojto 122:f9eeca106725 3452 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 3453 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 3454 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 3455 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 3456 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
Kojto 122:f9eeca106725 3457 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 3458 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
Kojto 122:f9eeca106725 3459 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
Kojto 122:f9eeca106725 3460 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 3461 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 3462 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 3463 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 3464 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
Kojto 122:f9eeca106725 3465 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
Kojto 93:e188a91d3eaa 3466
Kojto 93:e188a91d3eaa 3467 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 3468 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 3469 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 3470 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 3471 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 3472 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 3473 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 3474 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 3475 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 3476 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 3477 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 3478 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 3479 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
Kojto 93:e188a91d3eaa 3480
Kojto 93:e188a91d3eaa 3481 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 3482 #define TIM_EGR_UG 0x01U /*!<Update Generation */
Kojto 122:f9eeca106725 3483 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 3484 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 3485 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 3486 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 3487 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 3488 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
Kojto 122:f9eeca106725 3489 #define TIM_EGR_BG 0x80U /*!<Break Generation */
Kojto 93:e188a91d3eaa 3490
Kojto 93:e188a91d3eaa 3491 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 3492 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 3493 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3494 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3495
Kojto 122:f9eeca106725 3496 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 3497 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 3498
Kojto 122:f9eeca106725 3499 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 3500 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3501 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3502 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3503
Kojto 122:f9eeca106725 3504 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 3505
Kojto 122:f9eeca106725 3506 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 3507 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3508 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3509
Kojto 122:f9eeca106725 3510 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 3511 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 3512
Kojto 122:f9eeca106725 3513 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 3514 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3515 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3516 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3517
Kojto 122:f9eeca106725 3518 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
Kojto 93:e188a91d3eaa 3519
Kojto 93:e188a91d3eaa 3520 /*----------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 3521
Kojto 122:f9eeca106725 3522 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 3523 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3524 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3525
Kojto 122:f9eeca106725 3526 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 3527 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3528 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3529 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3530 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3531
Kojto 122:f9eeca106725 3532 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 3533 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 3534 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 3535
Kojto 122:f9eeca106725 3536 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 3537 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3538 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3539 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3540 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3541
Kojto 93:e188a91d3eaa 3542 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 3543 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 3544 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3545 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3546
Kojto 122:f9eeca106725 3547 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 3548 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 3549
Kojto 122:f9eeca106725 3550 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 3551 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3552 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3553 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3554
Kojto 122:f9eeca106725 3555 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 3556
Kojto 122:f9eeca106725 3557 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 3558 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3559 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3560
Kojto 122:f9eeca106725 3561 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 3562 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 3563
Kojto 122:f9eeca106725 3564 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 3565 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3566 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3567 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3568
Kojto 122:f9eeca106725 3569 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
Kojto 93:e188a91d3eaa 3570
Kojto 93:e188a91d3eaa 3571 /*----------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 3572
Kojto 122:f9eeca106725 3573 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 3574 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3575 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3576
Kojto 122:f9eeca106725 3577 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 3578 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3579 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3580 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3581 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3582
Kojto 122:f9eeca106725 3583 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 3584 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 3585 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 3586
Kojto 122:f9eeca106725 3587 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 3588 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3589 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3590 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3591 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3592
Kojto 93:e188a91d3eaa 3593 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 3594 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 3595 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 3596 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 3597 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 3598 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 3599 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 3600 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 3601 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 3602 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 3603 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 3604 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 3605 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 3606 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 3607 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 3608 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 93:e188a91d3eaa 3609
Kojto 93:e188a91d3eaa 3610 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 3611 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
Kojto 93:e188a91d3eaa 3612
Kojto 93:e188a91d3eaa 3613 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 3614 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
Kojto 93:e188a91d3eaa 3615
Kojto 93:e188a91d3eaa 3616 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 3617 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
Kojto 93:e188a91d3eaa 3618
Kojto 93:e188a91d3eaa 3619 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 3620 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
Kojto 93:e188a91d3eaa 3621
Kojto 93:e188a91d3eaa 3622 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 3623 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
Kojto 93:e188a91d3eaa 3624
Kojto 93:e188a91d3eaa 3625 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 3626 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
Kojto 93:e188a91d3eaa 3627
Kojto 93:e188a91d3eaa 3628 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 3629 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
Kojto 93:e188a91d3eaa 3630
Kojto 93:e188a91d3eaa 3631 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 3632 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
Kojto 93:e188a91d3eaa 3633
Kojto 93:e188a91d3eaa 3634 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 3635 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 3636 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3637 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3638 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3639 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3640 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3641 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3642 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3643 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3644
Kojto 122:f9eeca106725 3645 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 3646 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3647 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3648
Kojto 122:f9eeca106725 3649 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 3650 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 3651 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
Kojto 122:f9eeca106725 3652 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
Kojto 122:f9eeca106725 3653 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
Kojto 122:f9eeca106725 3654 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
Kojto 93:e188a91d3eaa 3655
Kojto 93:e188a91d3eaa 3656 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 3657 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 3658 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3659 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3660 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3661 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3662 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3663
Kojto 122:f9eeca106725 3664 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 3665 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3666 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3667 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3668 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3669 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3670
Kojto 93:e188a91d3eaa 3671 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 3672 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
Kojto 93:e188a91d3eaa 3673
Kojto 93:e188a91d3eaa 3674 /******************* Bit definition for TIM_OR register *********************/
Kojto 122:f9eeca106725 3675 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 122:f9eeca106725 3676 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
Kojto 122:f9eeca106725 3677 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
Kojto 122:f9eeca106725 3678 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 122:f9eeca106725 3679 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 3680 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3681
Kojto 93:e188a91d3eaa 3682
Kojto 93:e188a91d3eaa 3683 /******************************************************************************/
Kojto 93:e188a91d3eaa 3684 /* */
Kojto 93:e188a91d3eaa 3685 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 93:e188a91d3eaa 3686 /* */
Kojto 93:e188a91d3eaa 3687 /******************************************************************************/
Kojto 93:e188a91d3eaa 3688 /******************* Bit definition for USART_SR register *******************/
Kojto 122:f9eeca106725 3689 #define USART_SR_PE 0x0001U /*!<Parity Error */
Kojto 122:f9eeca106725 3690 #define USART_SR_FE 0x0002U /*!<Framing Error */
Kojto 122:f9eeca106725 3691 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
Kojto 122:f9eeca106725 3692 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
Kojto 122:f9eeca106725 3693 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
Kojto 122:f9eeca106725 3694 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
Kojto 122:f9eeca106725 3695 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
Kojto 122:f9eeca106725 3696 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
Kojto 122:f9eeca106725 3697 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
Kojto 122:f9eeca106725 3698 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
Kojto 93:e188a91d3eaa 3699
Kojto 93:e188a91d3eaa 3700 /******************* Bit definition for USART_DR register *******************/
Kojto 122:f9eeca106725 3701 #define USART_DR_DR 0x01FFU /*!<Data value */
Kojto 93:e188a91d3eaa 3702
Kojto 93:e188a91d3eaa 3703 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 3704 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
Kojto 122:f9eeca106725 3705 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
Kojto 93:e188a91d3eaa 3706
Kojto 93:e188a91d3eaa 3707 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 3708 #define USART_CR1_SBK 0x0001U /*!<Send Break */
Kojto 122:f9eeca106725 3709 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
Kojto 122:f9eeca106725 3710 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
Kojto 122:f9eeca106725 3711 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
Kojto 122:f9eeca106725 3712 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
Kojto 122:f9eeca106725 3713 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
Kojto 122:f9eeca106725 3714 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 3715 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 3716 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 3717 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
Kojto 122:f9eeca106725 3718 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
Kojto 122:f9eeca106725 3719 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
Kojto 122:f9eeca106725 3720 #define USART_CR1_M 0x1000U /*!<Word length */
Kojto 122:f9eeca106725 3721 #define USART_CR1_UE 0x2000U /*!<USART Enable */
Kojto 122:f9eeca106725 3722 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
Kojto 93:e188a91d3eaa 3723
Kojto 93:e188a91d3eaa 3724 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 3725 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
Kojto 122:f9eeca106725 3726 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
Kojto 122:f9eeca106725 3727 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 3728 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
Kojto 122:f9eeca106725 3729 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
Kojto 122:f9eeca106725 3730 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
Kojto 122:f9eeca106725 3731 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
Kojto 122:f9eeca106725 3732
Kojto 122:f9eeca106725 3733 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 3734 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3735 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3736
Kojto 122:f9eeca106725 3737 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
Kojto 93:e188a91d3eaa 3738
Kojto 93:e188a91d3eaa 3739 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 3740 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 3741 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
Kojto 122:f9eeca106725 3742 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
Kojto 122:f9eeca106725 3743 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
Kojto 122:f9eeca106725 3744 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
Kojto 122:f9eeca106725 3745 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
Kojto 122:f9eeca106725 3746 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
Kojto 122:f9eeca106725 3747 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
Kojto 122:f9eeca106725 3748 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
Kojto 122:f9eeca106725 3749 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
Kojto 122:f9eeca106725 3750 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
Kojto 122:f9eeca106725 3751 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
Kojto 93:e188a91d3eaa 3752
Kojto 93:e188a91d3eaa 3753 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 3754 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 3755 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3756 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3757 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3758 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3759 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3760 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3761 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3762 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3763
Kojto 122:f9eeca106725 3764 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
Kojto 93:e188a91d3eaa 3765
Kojto 93:e188a91d3eaa 3766 /******************************************************************************/
Kojto 93:e188a91d3eaa 3767 /* */
Kojto 93:e188a91d3eaa 3768 /* Window WATCHDOG */
Kojto 93:e188a91d3eaa 3769 /* */
Kojto 93:e188a91d3eaa 3770 /******************************************************************************/
Kojto 93:e188a91d3eaa 3771 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 3772 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 3773 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 3774 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 3775 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
Kojto 122:f9eeca106725 3776 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
Kojto 122:f9eeca106725 3777 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
Kojto 122:f9eeca106725 3778 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
Kojto 122:f9eeca106725 3779 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
Kojto 122:f9eeca106725 3780 /* Legacy defines */
Kojto 122:f9eeca106725 3781 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 3782 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 3783 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 3784 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 3785 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 3786 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 3787 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 3788
Kojto 122:f9eeca106725 3789 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
Kojto 93:e188a91d3eaa 3790
Kojto 93:e188a91d3eaa 3791 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 3792 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 3793 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3794 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3795 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3796 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3797 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3798 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3799 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3800 /* Legacy defines */
Kojto 122:f9eeca106725 3801 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 3802 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 3803 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 3804 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 3805 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 3806 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 3807 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 3808
Kojto 122:f9eeca106725 3809 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 3810 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
Kojto 122:f9eeca106725 3811 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
Kojto 122:f9eeca106725 3812 /* Legacy defines */
Kojto 122:f9eeca106725 3813 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 3814 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 3815
Kojto 122:f9eeca106725 3816 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
Kojto 93:e188a91d3eaa 3817
Kojto 93:e188a91d3eaa 3818 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 3819 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
Kojto 93:e188a91d3eaa 3820
Kojto 93:e188a91d3eaa 3821
Kojto 93:e188a91d3eaa 3822 /******************************************************************************/
Kojto 93:e188a91d3eaa 3823 /* */
Kojto 93:e188a91d3eaa 3824 /* DBG */
Kojto 93:e188a91d3eaa 3825 /* */
Kojto 93:e188a91d3eaa 3826 /******************************************************************************/
Kojto 93:e188a91d3eaa 3827 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 3828 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto 122:f9eeca106725 3829 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
Kojto 93:e188a91d3eaa 3830
Kojto 93:e188a91d3eaa 3831 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 3832 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto 122:f9eeca106725 3833 #define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto 122:f9eeca106725 3834 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto 122:f9eeca106725 3835 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto 122:f9eeca106725 3836
Kojto 122:f9eeca106725 3837 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto 122:f9eeca106725 3838 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
Kojto 122:f9eeca106725 3839 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
Kojto 93:e188a91d3eaa 3840
Kojto 93:e188a91d3eaa 3841 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 122:f9eeca106725 3842 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto 122:f9eeca106725 3843 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto 122:f9eeca106725 3844 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto 122:f9eeca106725 3845 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto 122:f9eeca106725 3846 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto 122:f9eeca106725 3847 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto 122:f9eeca106725 3848 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto 122:f9eeca106725 3849 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto 122:f9eeca106725 3850 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto 122:f9eeca106725 3851 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto 122:f9eeca106725 3852 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto 122:f9eeca106725 3853 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto 122:f9eeca106725 3854 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto 122:f9eeca106725 3855 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto 122:f9eeca106725 3856 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto 122:f9eeca106725 3857 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto 122:f9eeca106725 3858 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
Kojto 93:e188a91d3eaa 3859 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 3860 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 93:e188a91d3eaa 3861
Kojto 93:e188a91d3eaa 3862 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 122:f9eeca106725 3863 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto 122:f9eeca106725 3864 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto 122:f9eeca106725 3865 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto 122:f9eeca106725 3866 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto 122:f9eeca106725 3867 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
Kojto 93:e188a91d3eaa 3868
Kojto 93:e188a91d3eaa 3869 /******************************************************************************/
Kojto 93:e188a91d3eaa 3870 /* */
Kojto 93:e188a91d3eaa 3871 /* USB_OTG */
Kojto 93:e188a91d3eaa 3872 /* */
Kojto 93:e188a91d3eaa 3873 /******************************************************************************/
Kojto 93:e188a91d3eaa 3874 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 122:f9eeca106725 3875 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
Kojto 122:f9eeca106725 3876 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
Kojto 122:f9eeca106725 3877 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
Kojto 122:f9eeca106725 3878 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
Kojto 122:f9eeca106725 3879 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 3880 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
Kojto 122:f9eeca106725 3881 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
Kojto 122:f9eeca106725 3882 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
Kojto 122:f9eeca106725 3883 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
Kojto 122:f9eeca106725 3884 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
Kojto 93:e188a91d3eaa 3885
Kojto 93:e188a91d3eaa 3886 /******************** Bit definition forUSB_OTG_HCFG register ********************/
Kojto 93:e188a91d3eaa 3887
Kojto 122:f9eeca106725 3888 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
Kojto 122:f9eeca106725 3889 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3890 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3891 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
Kojto 93:e188a91d3eaa 3892
Kojto 93:e188a91d3eaa 3893 /******************** Bit definition forUSB_OTG_DCFG register ********************/
Kojto 93:e188a91d3eaa 3894
Kojto 122:f9eeca106725 3895 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
Kojto 122:f9eeca106725 3896 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3897 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3898 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
Kojto 122:f9eeca106725 3899
Kojto 122:f9eeca106725 3900 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
Kojto 122:f9eeca106725 3901 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3902 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3903 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3904 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3905 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
Kojto 122:f9eeca106725 3906 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
Kojto 122:f9eeca106725 3907 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
Kojto 122:f9eeca106725 3908
Kojto 122:f9eeca106725 3909 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
Kojto 122:f9eeca106725 3910 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 3911 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3912
Kojto 122:f9eeca106725 3913 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
Kojto 122:f9eeca106725 3914 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3915 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3916
Kojto 93:e188a91d3eaa 3917 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 122:f9eeca106725 3918 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
Kojto 122:f9eeca106725 3919 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
Kojto 122:f9eeca106725 3920 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
Kojto 93:e188a91d3eaa 3921
Kojto 93:e188a91d3eaa 3922 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 122:f9eeca106725 3923 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
Kojto 122:f9eeca106725 3924 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
Kojto 122:f9eeca106725 3925 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
Kojto 122:f9eeca106725 3926 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
Kojto 122:f9eeca106725 3927 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
Kojto 122:f9eeca106725 3928 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
Kojto 93:e188a91d3eaa 3929
Kojto 93:e188a91d3eaa 3930 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 122:f9eeca106725 3931 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
Kojto 122:f9eeca106725 3932 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
Kojto 122:f9eeca106725 3933 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
Kojto 122:f9eeca106725 3934 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
Kojto 122:f9eeca106725 3935
Kojto 122:f9eeca106725 3936 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
Kojto 122:f9eeca106725 3937 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3938 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3939 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3940 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
Kojto 122:f9eeca106725 3941 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
Kojto 122:f9eeca106725 3942 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
Kojto 122:f9eeca106725 3943 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
Kojto 122:f9eeca106725 3944 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
Kojto 93:e188a91d3eaa 3945
Kojto 93:e188a91d3eaa 3946 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 122:f9eeca106725 3947 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
Kojto 93:e188a91d3eaa 3948
Kojto 93:e188a91d3eaa 3949 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 122:f9eeca106725 3950 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
Kojto 122:f9eeca106725 3951 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
Kojto 93:e188a91d3eaa 3952
Kojto 93:e188a91d3eaa 3953 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 122:f9eeca106725 3954 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
Kojto 122:f9eeca106725 3955
Kojto 122:f9eeca106725 3956 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
Kojto 122:f9eeca106725 3957 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 3958 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 3959 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
Kojto 122:f9eeca106725 3960 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
Kojto 93:e188a91d3eaa 3961
Kojto 93:e188a91d3eaa 3962 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 122:f9eeca106725 3963 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
Kojto 122:f9eeca106725 3964
Kojto 122:f9eeca106725 3965 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
Kojto 122:f9eeca106725 3966 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 3967 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 3968 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
Kojto 122:f9eeca106725 3969 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
Kojto 122:f9eeca106725 3970 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
Kojto 122:f9eeca106725 3971 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
Kojto 122:f9eeca106725 3972 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
Kojto 93:e188a91d3eaa 3973
Kojto 93:e188a91d3eaa 3974 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
Kojto 93:e188a91d3eaa 3975
Kojto 122:f9eeca106725 3976 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
Kojto 122:f9eeca106725 3977 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3978 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3979 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3980 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 122:f9eeca106725 3981 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
Kojto 122:f9eeca106725 3982 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
Kojto 122:f9eeca106725 3983
Kojto 122:f9eeca106725 3984 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
Kojto 122:f9eeca106725 3985 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 3986 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 3987 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3988 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3989 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
Kojto 122:f9eeca106725 3990 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
Kojto 122:f9eeca106725 3991 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
Kojto 122:f9eeca106725 3992 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
Kojto 122:f9eeca106725 3993 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
Kojto 122:f9eeca106725 3994 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
Kojto 122:f9eeca106725 3995 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
Kojto 122:f9eeca106725 3996 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
Kojto 122:f9eeca106725 3997 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
Kojto 122:f9eeca106725 3998 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
Kojto 122:f9eeca106725 3999 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
Kojto 122:f9eeca106725 4000 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
Kojto 122:f9eeca106725 4001 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
Kojto 93:e188a91d3eaa 4002
Kojto 93:e188a91d3eaa 4003 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 122:f9eeca106725 4004 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
Kojto 122:f9eeca106725 4005 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
Kojto 122:f9eeca106725 4006 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
Kojto 122:f9eeca106725 4007 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
Kojto 122:f9eeca106725 4008 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
Kojto 122:f9eeca106725 4009
Kojto 122:f9eeca106725 4010 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
Kojto 122:f9eeca106725 4011 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 4012 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 4013 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 4014 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
Kojto 122:f9eeca106725 4015 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
Kojto 122:f9eeca106725 4016 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
Kojto 122:f9eeca106725 4017 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
Kojto 93:e188a91d3eaa 4018
Kojto 93:e188a91d3eaa 4019 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 122:f9eeca106725 4020 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 4021 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 4022 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 4023 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 4024 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 4025 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 4026 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 4027 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4028
Kojto 93:e188a91d3eaa 4029 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 122:f9eeca106725 4030 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
Kojto 122:f9eeca106725 4031
Kojto 122:f9eeca106725 4032 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
Kojto 122:f9eeca106725 4033 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4034 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4035 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4036 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4037 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4038 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4039 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4040 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4041
Kojto 122:f9eeca106725 4042 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
Kojto 122:f9eeca106725 4043 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4044 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4045 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4046 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4047 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4048 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4049 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4050 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4051
Kojto 93:e188a91d3eaa 4052 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 122:f9eeca106725 4053 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
Kojto 93:e188a91d3eaa 4054
Kojto 93:e188a91d3eaa 4055 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 122:f9eeca106725 4056 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 4057 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 4058 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
Kojto 122:f9eeca106725 4059 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
Kojto 122:f9eeca106725 4060 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
Kojto 122:f9eeca106725 4061 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 4062 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4063
Kojto 93:e188a91d3eaa 4064 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 122:f9eeca106725 4065 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
Kojto 122:f9eeca106725 4066 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
Kojto 122:f9eeca106725 4067 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
Kojto 122:f9eeca106725 4068 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
Kojto 122:f9eeca106725 4069 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
Kojto 122:f9eeca106725 4070 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
Kojto 122:f9eeca106725 4071 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
Kojto 122:f9eeca106725 4072 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
Kojto 122:f9eeca106725 4073 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
Kojto 122:f9eeca106725 4074 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
Kojto 122:f9eeca106725 4075 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
Kojto 122:f9eeca106725 4076 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
Kojto 122:f9eeca106725 4077 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
Kojto 122:f9eeca106725 4078 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
Kojto 122:f9eeca106725 4079 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
Kojto 122:f9eeca106725 4080 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
Kojto 122:f9eeca106725 4081 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
Kojto 122:f9eeca106725 4082 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
Kojto 122:f9eeca106725 4083 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
Kojto 122:f9eeca106725 4084 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
Kojto 122:f9eeca106725 4085 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
Kojto 122:f9eeca106725 4086 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
Kojto 122:f9eeca106725 4087 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
Kojto 122:f9eeca106725 4088 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
Kojto 122:f9eeca106725 4089 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
Kojto 122:f9eeca106725 4090 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
Kojto 93:e188a91d3eaa 4091
Kojto 93:e188a91d3eaa 4092 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 122:f9eeca106725 4093 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
Kojto 122:f9eeca106725 4094 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
Kojto 122:f9eeca106725 4095 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
Kojto 122:f9eeca106725 4096 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
Kojto 122:f9eeca106725 4097 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
Kojto 122:f9eeca106725 4098 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
Kojto 122:f9eeca106725 4099 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
Kojto 122:f9eeca106725 4100 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
Kojto 122:f9eeca106725 4101 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
Kojto 122:f9eeca106725 4102 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
Kojto 122:f9eeca106725 4103 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
Kojto 122:f9eeca106725 4104 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 122:f9eeca106725 4105 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
Kojto 122:f9eeca106725 4106 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
Kojto 122:f9eeca106725 4107 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
Kojto 122:f9eeca106725 4108 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
Kojto 122:f9eeca106725 4109 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
Kojto 122:f9eeca106725 4110 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
Kojto 122:f9eeca106725 4111 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
Kojto 122:f9eeca106725 4112 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
Kojto 122:f9eeca106725 4113 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
Kojto 122:f9eeca106725 4114 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
Kojto 122:f9eeca106725 4115 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
Kojto 122:f9eeca106725 4116 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
Kojto 122:f9eeca106725 4117 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
Kojto 122:f9eeca106725 4118 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
Kojto 93:e188a91d3eaa 4119
Kojto 93:e188a91d3eaa 4120 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 122:f9eeca106725 4121 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
Kojto 122:f9eeca106725 4122 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
Kojto 93:e188a91d3eaa 4123
Kojto 93:e188a91d3eaa 4124 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 122:f9eeca106725 4125 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
Kojto 93:e188a91d3eaa 4126
Kojto 93:e188a91d3eaa 4127 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 122:f9eeca106725 4128 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 4129 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 4130 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 4131 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4132
Kojto 93:e188a91d3eaa 4133 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 122:f9eeca106725 4134 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 4135 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4136
Kojto 93:e188a91d3eaa 4137 /******************** Bit definition for OTG register ********************/
Kojto 93:e188a91d3eaa 4138
Kojto 122:f9eeca106725 4139 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 4140 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4141 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4142 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4143 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4144 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 4145
Kojto 122:f9eeca106725 4146 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 4147 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4148 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4149
Kojto 122:f9eeca106725 4150 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 4151 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4152 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4153 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4154 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4155
Kojto 122:f9eeca106725 4156 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 4157 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4158 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4159 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4160 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4161
Kojto 122:f9eeca106725 4162 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 4163 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4164 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4165 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4166 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4167
Kojto 93:e188a91d3eaa 4168 /******************** Bit definition for OTG register ********************/
Kojto 93:e188a91d3eaa 4169
Kojto 122:f9eeca106725 4170 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 4171 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4172 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4173 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4174 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4175 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 4176
Kojto 122:f9eeca106725 4177 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 4178 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4179 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4180
Kojto 122:f9eeca106725 4181 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 4182 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4183 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4184 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4185 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4186
Kojto 122:f9eeca106725 4187 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 4188 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4189 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4190 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4191 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4192
Kojto 122:f9eeca106725 4193 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 4194 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4195 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4196 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4197 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4198
Kojto 93:e188a91d3eaa 4199 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 122:f9eeca106725 4200 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
Kojto 93:e188a91d3eaa 4201
Kojto 93:e188a91d3eaa 4202 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 122:f9eeca106725 4203 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
Kojto 93:e188a91d3eaa 4204
Kojto 93:e188a91d3eaa 4205 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 4206 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
Kojto 122:f9eeca106725 4207 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
Kojto 122:f9eeca106725 4208 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
Kojto 122:f9eeca106725 4209 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
Kojto 93:e188a91d3eaa 4210
Kojto 93:e188a91d3eaa 4211 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 122:f9eeca106725 4212 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
Kojto 93:e188a91d3eaa 4213
Kojto 93:e188a91d3eaa 4214 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 122:f9eeca106725 4215 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
Kojto 122:f9eeca106725 4216
Kojto 122:f9eeca106725 4217 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
Kojto 122:f9eeca106725 4218 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4219 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4220 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4221 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4222 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4223 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4224 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4225 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4226
Kojto 122:f9eeca106725 4227 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
Kojto 122:f9eeca106725 4228 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4229 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4230 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4231 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4232 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4233 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4234 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4235
Kojto 93:e188a91d3eaa 4236 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 122:f9eeca106725 4237 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
Kojto 122:f9eeca106725 4238 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
Kojto 122:f9eeca106725 4239
Kojto 122:f9eeca106725 4240 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
Kojto 122:f9eeca106725 4241 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4242 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4243 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
Kojto 122:f9eeca106725 4244 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
Kojto 122:f9eeca106725 4245 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
Kojto 122:f9eeca106725 4246 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
Kojto 122:f9eeca106725 4247 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
Kojto 122:f9eeca106725 4248 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
Kojto 122:f9eeca106725 4249 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
Kojto 122:f9eeca106725 4250 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
Kojto 122:f9eeca106725 4251
Kojto 122:f9eeca106725 4252 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
Kojto 122:f9eeca106725 4253 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4254 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4255 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4256 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4257 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4258 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4259 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4260 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4261 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
Kojto 122:f9eeca106725 4262 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
Kojto 93:e188a91d3eaa 4263
Kojto 93:e188a91d3eaa 4264 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 122:f9eeca106725 4265 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 93:e188a91d3eaa 4266
Kojto 93:e188a91d3eaa 4267 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 122:f9eeca106725 4268 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
Kojto 122:f9eeca106725 4269 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
Kojto 93:e188a91d3eaa 4270
Kojto 93:e188a91d3eaa 4271 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 122:f9eeca106725 4272 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
Kojto 122:f9eeca106725 4273 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
Kojto 122:f9eeca106725 4274 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
Kojto 122:f9eeca106725 4275 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
Kojto 122:f9eeca106725 4276 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
Kojto 122:f9eeca106725 4277 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
Kojto 93:e188a91d3eaa 4278
Kojto 93:e188a91d3eaa 4279 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 122:f9eeca106725 4280 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
Kojto 122:f9eeca106725 4281 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 93:e188a91d3eaa 4282
Kojto 93:e188a91d3eaa 4283 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 122:f9eeca106725 4284 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
Kojto 93:e188a91d3eaa 4285
Kojto 93:e188a91d3eaa 4286 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 4287 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 4288 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 4289 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 4290 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 4291 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 4292 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 4293 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 4294 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 4295 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 93:e188a91d3eaa 4296
Kojto 93:e188a91d3eaa 4297 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 122:f9eeca106725 4298 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
Kojto 122:f9eeca106725 4299 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
Kojto 122:f9eeca106725 4300 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
Kojto 122:f9eeca106725 4301 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
Kojto 122:f9eeca106725 4302 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
Kojto 122:f9eeca106725 4303 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
Kojto 122:f9eeca106725 4304 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
Kojto 122:f9eeca106725 4305 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
Kojto 122:f9eeca106725 4306 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
Kojto 122:f9eeca106725 4307
Kojto 122:f9eeca106725 4308 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
Kojto 122:f9eeca106725 4309 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 4310 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 4311 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
Kojto 122:f9eeca106725 4312
Kojto 122:f9eeca106725 4313 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
Kojto 122:f9eeca106725 4314 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4315 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4316 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4317 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4318
Kojto 122:f9eeca106725 4319 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
Kojto 122:f9eeca106725 4320 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4321 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4322
Kojto 93:e188a91d3eaa 4323 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 4324 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 4325 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 4326 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
Kojto 122:f9eeca106725 4327 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 4328 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 4329 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 4330 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 4331 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 4332 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
Kojto 122:f9eeca106725 4333 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 4334 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
Kojto 93:e188a91d3eaa 4335
Kojto 93:e188a91d3eaa 4336 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 122:f9eeca106725 4337 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
Kojto 122:f9eeca106725 4338 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
Kojto 93:e188a91d3eaa 4339
Kojto 93:e188a91d3eaa 4340 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 122:f9eeca106725 4341 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 4342 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 4343 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
Kojto 122:f9eeca106725 4344 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 4345
Kojto 122:f9eeca106725 4346 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 4347 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4348 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4349 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 4350
Kojto 122:f9eeca106725 4351 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
Kojto 122:f9eeca106725 4352 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4353 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4354 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4355 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4356 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 4357 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 4358 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 4359 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 4360 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 4361 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 93:e188a91d3eaa 4362
Kojto 93:e188a91d3eaa 4363 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 122:f9eeca106725 4364 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 4365
Kojto 122:f9eeca106725 4366 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
Kojto 122:f9eeca106725 4367 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 4368 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4369 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4370 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4371 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
Kojto 122:f9eeca106725 4372 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
Kojto 122:f9eeca106725 4373
Kojto 122:f9eeca106725 4374 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 4375 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4376 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4377
Kojto 122:f9eeca106725 4378 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
Kojto 122:f9eeca106725 4379 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4380 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4381
Kojto 122:f9eeca106725 4382 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
Kojto 122:f9eeca106725 4383 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4384 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4385 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4386 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4387 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4388 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4389 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4390 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
Kojto 122:f9eeca106725 4391 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
Kojto 122:f9eeca106725 4392 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
Kojto 93:e188a91d3eaa 4393
Kojto 93:e188a91d3eaa 4394 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
Kojto 93:e188a91d3eaa 4395
Kojto 122:f9eeca106725 4396 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
Kojto 122:f9eeca106725 4397 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4398 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4399 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4400 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4401 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4402 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4403 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4404
Kojto 122:f9eeca106725 4405 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
Kojto 122:f9eeca106725 4406 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 4407 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 4408 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 4409 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 4410 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 4411 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4412 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4413
Kojto 122:f9eeca106725 4414 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
Kojto 122:f9eeca106725 4415 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4416 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4417 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
Kojto 122:f9eeca106725 4418 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
Kojto 93:e188a91d3eaa 4419
Kojto 93:e188a91d3eaa 4420 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 122:f9eeca106725 4421 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
Kojto 122:f9eeca106725 4422 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
Kojto 122:f9eeca106725 4423 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 4424 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
Kojto 122:f9eeca106725 4425 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
Kojto 122:f9eeca106725 4426 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
Kojto 122:f9eeca106725 4427 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
Kojto 122:f9eeca106725 4428 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
Kojto 122:f9eeca106725 4429 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
Kojto 122:f9eeca106725 4430 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
Kojto 122:f9eeca106725 4431 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
Kojto 93:e188a91d3eaa 4432
Kojto 93:e188a91d3eaa 4433 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 122:f9eeca106725 4434 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 4435 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 4436 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
Kojto 122:f9eeca106725 4437 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
Kojto 122:f9eeca106725 4438 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
Kojto 122:f9eeca106725 4439 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
Kojto 122:f9eeca106725 4440 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
Kojto 122:f9eeca106725 4441 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
Kojto 122:f9eeca106725 4442 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
Kojto 122:f9eeca106725 4443 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
Kojto 122:f9eeca106725 4444 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
Kojto 93:e188a91d3eaa 4445
Kojto 93:e188a91d3eaa 4446 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 122:f9eeca106725 4447 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
Kojto 122:f9eeca106725 4448 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
Kojto 122:f9eeca106725 4449 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 4450 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
Kojto 122:f9eeca106725 4451 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
Kojto 122:f9eeca106725 4452 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
Kojto 122:f9eeca106725 4453 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
Kojto 122:f9eeca106725 4454 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
Kojto 122:f9eeca106725 4455 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
Kojto 122:f9eeca106725 4456 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
Kojto 122:f9eeca106725 4457 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
Kojto 93:e188a91d3eaa 4458
Kojto 93:e188a91d3eaa 4459 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 93:e188a91d3eaa 4460
Kojto 122:f9eeca106725 4461 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 4462 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 4463 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
Kojto 93:e188a91d3eaa 4464 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 122:f9eeca106725 4465 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 4466 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 4467 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
Kojto 122:f9eeca106725 4468 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
Kojto 122:f9eeca106725 4469 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4470 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4471
Kojto 93:e188a91d3eaa 4472 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 122:f9eeca106725 4473 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 93:e188a91d3eaa 4474
Kojto 93:e188a91d3eaa 4475 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 122:f9eeca106725 4476 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 93:e188a91d3eaa 4477
Kojto 93:e188a91d3eaa 4478 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 122:f9eeca106725 4479 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
Kojto 93:e188a91d3eaa 4480
Kojto 93:e188a91d3eaa 4481 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 122:f9eeca106725 4482 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 122:f9eeca106725 4483 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
Kojto 93:e188a91d3eaa 4484
Kojto 93:e188a91d3eaa 4485 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
Kojto 93:e188a91d3eaa 4486
Kojto 122:f9eeca106725 4487 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 122:f9eeca106725 4488 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 4489 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 4490 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 4491 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 4492 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 4493 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4494 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4495 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
Kojto 122:f9eeca106725 4496 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 4497 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 4498 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 4499 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 4500 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 93:e188a91d3eaa 4501
Kojto 93:e188a91d3eaa 4502 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 122:f9eeca106725 4503 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 4504 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 4505 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
Kojto 122:f9eeca106725 4506 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
Kojto 122:f9eeca106725 4507 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
Kojto 122:f9eeca106725 4508 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
Kojto 93:e188a91d3eaa 4509
Kojto 93:e188a91d3eaa 4510 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
Kojto 93:e188a91d3eaa 4511
Kojto 122:f9eeca106725 4512 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 4513 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 4514
Kojto 122:f9eeca106725 4515 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
Kojto 122:f9eeca106725 4516 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4517 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4518
Kojto 93:e188a91d3eaa 4519 /******************** Bit definition for PCGCCTL register ********************/
Kojto 122:f9eeca106725 4520 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
Kojto 122:f9eeca106725 4521 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 4522 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4523
Kojto 93:e188a91d3eaa 4524 /**
Kojto 93:e188a91d3eaa 4525 * @}
Kojto 93:e188a91d3eaa 4526 */
Kojto 93:e188a91d3eaa 4527
Kojto 93:e188a91d3eaa 4528 /**
Kojto 93:e188a91d3eaa 4529 * @}
Kojto 93:e188a91d3eaa 4530 */
Kojto 93:e188a91d3eaa 4531
Kojto 93:e188a91d3eaa 4532 /** @addtogroup Exported_macros
Kojto 93:e188a91d3eaa 4533 * @{
Kojto 93:e188a91d3eaa 4534 */
Kojto 93:e188a91d3eaa 4535
Kojto 93:e188a91d3eaa 4536 /******************************* ADC Instances ********************************/
Kojto 93:e188a91d3eaa 4537 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 93:e188a91d3eaa 4538
Kojto 93:e188a91d3eaa 4539 /******************************* CRC Instances ********************************/
Kojto 93:e188a91d3eaa 4540 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 93:e188a91d3eaa 4541
Kojto 93:e188a91d3eaa 4542 /******************************** DMA Instances *******************************/
Kojto 93:e188a91d3eaa 4543 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 93:e188a91d3eaa 4544 ((INSTANCE) == DMA1_Stream1) || \
Kojto 93:e188a91d3eaa 4545 ((INSTANCE) == DMA1_Stream2) || \
Kojto 93:e188a91d3eaa 4546 ((INSTANCE) == DMA1_Stream3) || \
Kojto 93:e188a91d3eaa 4547 ((INSTANCE) == DMA1_Stream4) || \
Kojto 93:e188a91d3eaa 4548 ((INSTANCE) == DMA1_Stream5) || \
Kojto 93:e188a91d3eaa 4549 ((INSTANCE) == DMA1_Stream6) || \
Kojto 93:e188a91d3eaa 4550 ((INSTANCE) == DMA1_Stream7) || \
Kojto 93:e188a91d3eaa 4551 ((INSTANCE) == DMA2_Stream0) || \
Kojto 93:e188a91d3eaa 4552 ((INSTANCE) == DMA2_Stream1) || \
Kojto 93:e188a91d3eaa 4553 ((INSTANCE) == DMA2_Stream2) || \
Kojto 93:e188a91d3eaa 4554 ((INSTANCE) == DMA2_Stream3) || \
Kojto 93:e188a91d3eaa 4555 ((INSTANCE) == DMA2_Stream4) || \
Kojto 93:e188a91d3eaa 4556 ((INSTANCE) == DMA2_Stream5) || \
Kojto 93:e188a91d3eaa 4557 ((INSTANCE) == DMA2_Stream6) || \
Kojto 93:e188a91d3eaa 4558 ((INSTANCE) == DMA2_Stream7))
Kojto 93:e188a91d3eaa 4559
Kojto 93:e188a91d3eaa 4560 /******************************* GPIO Instances *******************************/
Kojto 93:e188a91d3eaa 4561 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 4562 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 4563 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 4564 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 4565 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 4566 ((INSTANCE) == GPIOH))
Kojto 93:e188a91d3eaa 4567
Kojto 93:e188a91d3eaa 4568 /******************************** I2C Instances *******************************/
Kojto 93:e188a91d3eaa 4569 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 93:e188a91d3eaa 4570 ((INSTANCE) == I2C2) || \
Kojto 93:e188a91d3eaa 4571 ((INSTANCE) == I2C3))
Kojto 93:e188a91d3eaa 4572
Kojto 93:e188a91d3eaa 4573 /******************************** I2S Instances *******************************/
Kojto 99:dbbf35b96557 4574 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4575 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4576 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4577 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4578 ((INSTANCE) == SPI5))
Kojto 93:e188a91d3eaa 4579
Kojto 93:e188a91d3eaa 4580 /*************************** I2S Extended Instances ***************************/
Kojto 99:dbbf35b96557 4581 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
Kojto 99:dbbf35b96557 4582 ((INSTANCE) == SPI3) || \
Kojto 99:dbbf35b96557 4583 ((INSTANCE) == I2S2ext) || \
Kojto 99:dbbf35b96557 4584 ((INSTANCE) == I2S3ext))
Kojto 93:e188a91d3eaa 4585
Kojto 93:e188a91d3eaa 4586
Kojto 93:e188a91d3eaa 4587 /****************************** RTC Instances *********************************/
Kojto 93:e188a91d3eaa 4588 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 93:e188a91d3eaa 4589
Kojto 93:e188a91d3eaa 4590 /******************************** SPI Instances *******************************/
Kojto 93:e188a91d3eaa 4591 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4592 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4593 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4594 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4595 ((INSTANCE) == SPI5))
Kojto 93:e188a91d3eaa 4596 /*************************** SPI Extended Instances ***************************/
Kojto 93:e188a91d3eaa 4597 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4598 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4599 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4600 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4601 ((INSTANCE) == SPI5) || \
Kojto 93:e188a91d3eaa 4602 ((INSTANCE) == I2S2ext) || \
Kojto 93:e188a91d3eaa 4603 ((INSTANCE) == I2S3ext))
Kojto 93:e188a91d3eaa 4604
Kojto 93:e188a91d3eaa 4605 /****************** TIM Instances : All supported instances *******************/
Kojto 93:e188a91d3eaa 4606 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4607 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4608 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4609 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4610 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4611 ((INSTANCE) == TIM9) || \
Kojto 93:e188a91d3eaa 4612 ((INSTANCE) == TIM10) || \
Kojto 93:e188a91d3eaa 4613 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4614
Kojto 93:e188a91d3eaa 4615 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 93:e188a91d3eaa 4616 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4617 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4618 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4619 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4620 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4621 ((INSTANCE) == TIM9) || \
Kojto 93:e188a91d3eaa 4622 ((INSTANCE) == TIM10) || \
Kojto 93:e188a91d3eaa 4623 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4624
Kojto 93:e188a91d3eaa 4625 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4626 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4627 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4628 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4629 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4630 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4631 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4632
Kojto 93:e188a91d3eaa 4633 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4634 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4635 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4636 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4637 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4638 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4639
Kojto 93:e188a91d3eaa 4640 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4641 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4642 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4643 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4644 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4645 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4646
Kojto 93:e188a91d3eaa 4647 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 93:e188a91d3eaa 4648 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 93:e188a91d3eaa 4649
Kojto 93:e188a91d3eaa 4650 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 93:e188a91d3eaa 4651 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4652 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4653 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4654 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4655 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4656
Kojto 93:e188a91d3eaa 4657 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 93:e188a91d3eaa 4658 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4659 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4660 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4661 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4662 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4663
Kojto 93:e188a91d3eaa 4664 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 93:e188a91d3eaa 4665 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4666 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4667 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4668 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4669 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4670
Kojto 93:e188a91d3eaa 4671 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 93:e188a91d3eaa 4672 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4673 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4674 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4675 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4676 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4677
Kojto 93:e188a91d3eaa 4678 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 93:e188a91d3eaa 4679 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4680 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4681 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4682 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4683 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4684
Kojto 93:e188a91d3eaa 4685 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 93:e188a91d3eaa 4686 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4687 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4688 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4689 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4690 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4691 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4692
Kojto 93:e188a91d3eaa 4693 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 93:e188a91d3eaa 4694 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4695 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4696 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4697 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4698 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4699 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4700
Kojto 93:e188a91d3eaa 4701 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 93:e188a91d3eaa 4702 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4703 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4704
Kojto 93:e188a91d3eaa 4705 /***************** TIM Instances : external trigger input availabe ************/
Kojto 93:e188a91d3eaa 4706 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4707 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4708 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4709 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4710 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4711
Kojto 93:e188a91d3eaa 4712 /****************** TIM Instances : remapping capability **********************/
Kojto 93:e188a91d3eaa 4713 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4714 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4715 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4716
Kojto 93:e188a91d3eaa 4717 /******************* TIM Instances : output(s) available **********************/
Kojto 93:e188a91d3eaa 4718 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 4719 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 4720 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4721 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4722 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4723 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4724 || \
Kojto 93:e188a91d3eaa 4725 (((INSTANCE) == TIM2) && \
Kojto 93:e188a91d3eaa 4726 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4727 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4728 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4729 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4730 || \
Kojto 93:e188a91d3eaa 4731 (((INSTANCE) == TIM3) && \
Kojto 93:e188a91d3eaa 4732 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4733 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4734 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4735 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4736 || \
Kojto 93:e188a91d3eaa 4737 (((INSTANCE) == TIM4) && \
Kojto 93:e188a91d3eaa 4738 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4739 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4740 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4741 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4742 || \
Kojto 93:e188a91d3eaa 4743 (((INSTANCE) == TIM5) && \
Kojto 93:e188a91d3eaa 4744 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4745 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4746 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4747 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4748 || \
Kojto 93:e188a91d3eaa 4749 (((INSTANCE) == TIM9) && \
Kojto 93:e188a91d3eaa 4750 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4751 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 93:e188a91d3eaa 4752 || \
Kojto 93:e188a91d3eaa 4753 (((INSTANCE) == TIM10) && \
Kojto 93:e188a91d3eaa 4754 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 93:e188a91d3eaa 4755 || \
Kojto 93:e188a91d3eaa 4756 (((INSTANCE) == TIM11) && \
Kojto 93:e188a91d3eaa 4757 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 93:e188a91d3eaa 4758
Kojto 93:e188a91d3eaa 4759 /************ TIM Instances : complementary output(s) available ***************/
Kojto 93:e188a91d3eaa 4760 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 4761 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 4762 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4763 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4764 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 93:e188a91d3eaa 4765
Kojto 93:e188a91d3eaa 4766 /******************** USART Instances : Synchronous mode **********************/
Kojto 93:e188a91d3eaa 4767 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4768 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4769 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4770
Kojto 93:e188a91d3eaa 4771 /******************** UART Instances : Asynchronous mode **********************/
Kojto 93:e188a91d3eaa 4772 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4773 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4774 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4775
Kojto 93:e188a91d3eaa 4776 /****************** UART Instances : Hardware Flow control ********************/
Kojto 93:e188a91d3eaa 4777 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4778 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4779 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4780
Kojto 93:e188a91d3eaa 4781 /********************* UART Instances : Smard card mode ***********************/
Kojto 93:e188a91d3eaa 4782 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4783 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4784 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4785
Kojto 93:e188a91d3eaa 4786 /*********************** UART Instances : IRDA mode ***************************/
Kojto 93:e188a91d3eaa 4787 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4788 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4789 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4790
Kojto 122:f9eeca106725 4791 /*********************** PCD Instances ****************************************/
Kojto 122:f9eeca106725 4792 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
Kojto 122:f9eeca106725 4793
Kojto 122:f9eeca106725 4794 /*********************** HCD Instances ****************************************/
Kojto 122:f9eeca106725 4795 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
Kojto 122:f9eeca106725 4796
Kojto 93:e188a91d3eaa 4797 /****************************** IWDG Instances ********************************/
Kojto 93:e188a91d3eaa 4798 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 93:e188a91d3eaa 4799
Kojto 93:e188a91d3eaa 4800 /****************************** WWDG Instances ********************************/
Kojto 93:e188a91d3eaa 4801 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 93:e188a91d3eaa 4802
Kojto 99:dbbf35b96557 4803 /****************************** SDIO Instances ********************************/
Kojto 99:dbbf35b96557 4804 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 99:dbbf35b96557 4805
Kojto 99:dbbf35b96557 4806 /****************************** USB Exported Constants ************************/
Kojto 122:f9eeca106725 4807 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
Kojto 122:f9eeca106725 4808 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
Kojto 122:f9eeca106725 4809 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
Kojto 122:f9eeca106725 4810 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
Kojto 93:e188a91d3eaa 4811
Kojto 93:e188a91d3eaa 4812 /**
Kojto 93:e188a91d3eaa 4813 * @}
Kojto 93:e188a91d3eaa 4814 */
Kojto 93:e188a91d3eaa 4815
Kojto 93:e188a91d3eaa 4816 /**
Kojto 93:e188a91d3eaa 4817 * @}
Kojto 93:e188a91d3eaa 4818 */
Kojto 93:e188a91d3eaa 4819
Kojto 93:e188a91d3eaa 4820 /**
Kojto 93:e188a91d3eaa 4821 * @}
Kojto 93:e188a91d3eaa 4822 */
Kojto 93:e188a91d3eaa 4823
Kojto 93:e188a91d3eaa 4824 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 4825 }
Kojto 93:e188a91d3eaa 4826 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 4827
Kojto 93:e188a91d3eaa 4828 #endif /* __STM32F411xE_H */
Kojto 93:e188a91d3eaa 4829
Kojto 93:e188a91d3eaa 4830
Kojto 93:e188a91d3eaa 4831
Kojto 93:e188a91d3eaa 4832 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/