mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_MTS_MDOT_F405RG/stm32f405xx.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
106:ba1f97679dad 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f405xx.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.5.0
Kojto 122:f9eeca106725 6 * @date 22-April-2016
bogdanm 92:4fc01daae5a5 7 * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 * This file contains:
bogdanm 92:4fc01daae5a5 10 * - Data structures and the address mapping for all peripherals
Kojto 122:f9eeca106725 11 * - peripherals registers declarations and bits definition
Kojto 122:f9eeca106725 12 * - Macros to access peripheral's registers hardware
bogdanm 92:4fc01daae5a5 13 *
bogdanm 92:4fc01daae5a5 14 ******************************************************************************
bogdanm 92:4fc01daae5a5 15 * @attention
bogdanm 92:4fc01daae5a5 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 18 *
bogdanm 92:4fc01daae5a5 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 20 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 22 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 25 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 27 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 28 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 29 *
bogdanm 92:4fc01daae5a5 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 40 *
bogdanm 92:4fc01daae5a5 41 ******************************************************************************
bogdanm 92:4fc01daae5a5 42 */
bogdanm 92:4fc01daae5a5 43
bogdanm 92:4fc01daae5a5 44 /** @addtogroup CMSIS
bogdanm 92:4fc01daae5a5 45 * @{
bogdanm 92:4fc01daae5a5 46 */
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 /** @addtogroup stm32f405xx
bogdanm 92:4fc01daae5a5 49 * @{
bogdanm 92:4fc01daae5a5 50 */
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 #ifndef __STM32F405xx_H
bogdanm 92:4fc01daae5a5 53 #define __STM32F405xx_H
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 56 extern "C" {
bogdanm 92:4fc01daae5a5 57 #endif /* __cplusplus */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 92:4fc01daae5a5 61 * @{
bogdanm 92:4fc01daae5a5 62 */
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 /**
bogdanm 92:4fc01daae5a5 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 92:4fc01daae5a5 66 */
Kojto 122:f9eeca106725 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
Kojto 122:f9eeca106725 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
Kojto 122:f9eeca106725 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 71 #ifndef __FPU_PRESENT
Kojto 122:f9eeca106725 72 #define __FPU_PRESENT 1U /*!< FPU present */
Kojto 122:f9eeca106725 73 #endif /* __FPU_PRESENT */
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 /**
bogdanm 92:4fc01daae5a5 76 * @}
bogdanm 92:4fc01daae5a5 77 */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 92:4fc01daae5a5 80 * @{
bogdanm 92:4fc01daae5a5 81 */
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 /**
bogdanm 92:4fc01daae5a5 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm 92:4fc01daae5a5 85 * in @ref Library_configuration_section
bogdanm 92:4fc01daae5a5 86 */
bogdanm 92:4fc01daae5a5 87 typedef enum
bogdanm 92:4fc01daae5a5 88 {
bogdanm 92:4fc01daae5a5 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 92:4fc01daae5a5 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 92:4fc01daae5a5 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 92:4fc01daae5a5 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 92:4fc01daae5a5 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 92:4fc01daae5a5 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 92:4fc01daae5a5 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 92:4fc01daae5a5 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 92:4fc01daae5a5 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 92:4fc01daae5a5 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 92:4fc01daae5a5 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 92:4fc01daae5a5 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 92:4fc01daae5a5 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
bogdanm 92:4fc01daae5a5 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
bogdanm 92:4fc01daae5a5 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 92:4fc01daae5a5 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 92:4fc01daae5a5 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 92:4fc01daae5a5 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 92:4fc01daae5a5 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 92:4fc01daae5a5 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 92:4fc01daae5a5 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 92:4fc01daae5a5 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
bogdanm 92:4fc01daae5a5 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
bogdanm 92:4fc01daae5a5 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
bogdanm 92:4fc01daae5a5 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
bogdanm 92:4fc01daae5a5 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
bogdanm 92:4fc01daae5a5 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
bogdanm 92:4fc01daae5a5 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
bogdanm 92:4fc01daae5a5 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
bogdanm 92:4fc01daae5a5 118 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
bogdanm 92:4fc01daae5a5 119 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
bogdanm 92:4fc01daae5a5 120 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 92:4fc01daae5a5 121 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 92:4fc01daae5a5 122 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 92:4fc01daae5a5 123 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
bogdanm 92:4fc01daae5a5 124 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
bogdanm 92:4fc01daae5a5 125 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 92:4fc01daae5a5 126 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 92:4fc01daae5a5 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 92:4fc01daae5a5 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 92:4fc01daae5a5 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 92:4fc01daae5a5 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 92:4fc01daae5a5 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 92:4fc01daae5a5 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 92:4fc01daae5a5 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 92:4fc01daae5a5 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 92:4fc01daae5a5 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 92:4fc01daae5a5 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 92:4fc01daae5a5 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 92:4fc01daae5a5 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 92:4fc01daae5a5 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 92:4fc01daae5a5 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 92:4fc01daae5a5 141 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
bogdanm 92:4fc01daae5a5 142 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
bogdanm 92:4fc01daae5a5 143 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
bogdanm 92:4fc01daae5a5 144 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
bogdanm 92:4fc01daae5a5 145 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 92:4fc01daae5a5 146 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
bogdanm 92:4fc01daae5a5 147 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 92:4fc01daae5a5 148 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 92:4fc01daae5a5 149 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 92:4fc01daae5a5 150 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 92:4fc01daae5a5 151 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 92:4fc01daae5a5 152 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 92:4fc01daae5a5 153 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 92:4fc01daae5a5 154 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
bogdanm 92:4fc01daae5a5 155 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
bogdanm 92:4fc01daae5a5 156 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
bogdanm 92:4fc01daae5a5 157 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
bogdanm 92:4fc01daae5a5 158 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
bogdanm 92:4fc01daae5a5 159 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
bogdanm 92:4fc01daae5a5 160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
bogdanm 92:4fc01daae5a5 161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
bogdanm 92:4fc01daae5a5 162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
bogdanm 92:4fc01daae5a5 163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
bogdanm 92:4fc01daae5a5 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
bogdanm 92:4fc01daae5a5 165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
bogdanm 92:4fc01daae5a5 166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
bogdanm 92:4fc01daae5a5 167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
bogdanm 92:4fc01daae5a5 168 USART6_IRQn = 71, /*!< USART6 global interrupt */
bogdanm 92:4fc01daae5a5 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
bogdanm 92:4fc01daae5a5 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
bogdanm 92:4fc01daae5a5 171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
bogdanm 92:4fc01daae5a5 172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
bogdanm 92:4fc01daae5a5 173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
bogdanm 92:4fc01daae5a5 174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
bogdanm 92:4fc01daae5a5 175 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
bogdanm 92:4fc01daae5a5 176 FPU_IRQn = 81 /*!< FPU global interrupt */
bogdanm 92:4fc01daae5a5 177 } IRQn_Type;
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 /**
bogdanm 92:4fc01daae5a5 180 * @}
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 92:4fc01daae5a5 184 #include "system_stm32f4xx.h"
bogdanm 92:4fc01daae5a5 185 #include <stdint.h>
bogdanm 92:4fc01daae5a5 186
bogdanm 92:4fc01daae5a5 187 /** @addtogroup Peripheral_registers_structures
bogdanm 92:4fc01daae5a5 188 * @{
bogdanm 92:4fc01daae5a5 189 */
bogdanm 92:4fc01daae5a5 190
bogdanm 92:4fc01daae5a5 191 /**
bogdanm 92:4fc01daae5a5 192 * @brief Analog to Digital Converter
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 typedef struct
bogdanm 92:4fc01daae5a5 196 {
bogdanm 92:4fc01daae5a5 197 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 198 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 199 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 200 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 201 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 202 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 203 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 204 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 205 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 206 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 207 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 208 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 209 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 210 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 211 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
bogdanm 92:4fc01daae5a5 212 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 213 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 214 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 215 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 216 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
bogdanm 92:4fc01daae5a5 217 } ADC_TypeDef;
bogdanm 92:4fc01daae5a5 218
bogdanm 92:4fc01daae5a5 219 typedef struct
bogdanm 92:4fc01daae5a5 220 {
bogdanm 92:4fc01daae5a5 221 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
bogdanm 92:4fc01daae5a5 222 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
bogdanm 92:4fc01daae5a5 223 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 92:4fc01daae5a5 224 AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm 92:4fc01daae5a5 225 } ADC_Common_TypeDef;
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @brief Controller Area Network TxMailBox
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231
bogdanm 92:4fc01daae5a5 232 typedef struct
bogdanm 92:4fc01daae5a5 233 {
bogdanm 92:4fc01daae5a5 234 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 92:4fc01daae5a5 235 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 92:4fc01daae5a5 236 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 92:4fc01daae5a5 237 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 92:4fc01daae5a5 238 } CAN_TxMailBox_TypeDef;
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 /**
bogdanm 92:4fc01daae5a5 241 * @brief Controller Area Network FIFOMailBox
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 typedef struct
bogdanm 92:4fc01daae5a5 245 {
bogdanm 92:4fc01daae5a5 246 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 92:4fc01daae5a5 247 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 92:4fc01daae5a5 248 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 92:4fc01daae5a5 249 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 92:4fc01daae5a5 250 } CAN_FIFOMailBox_TypeDef;
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 /**
bogdanm 92:4fc01daae5a5 253 * @brief Controller Area Network FilterRegister
bogdanm 92:4fc01daae5a5 254 */
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 typedef struct
bogdanm 92:4fc01daae5a5 257 {
bogdanm 92:4fc01daae5a5 258 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 92:4fc01daae5a5 259 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 92:4fc01daae5a5 260 } CAN_FilterRegister_TypeDef;
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 /**
bogdanm 92:4fc01daae5a5 263 * @brief Controller Area Network
bogdanm 92:4fc01daae5a5 264 */
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 typedef struct
bogdanm 92:4fc01daae5a5 267 {
bogdanm 92:4fc01daae5a5 268 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 269 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 270 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 271 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 272 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 273 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 274 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 275 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 276 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 92:4fc01daae5a5 277 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 92:4fc01daae5a5 278 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 92:4fc01daae5a5 279 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 92:4fc01daae5a5 280 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 92:4fc01daae5a5 281 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 92:4fc01daae5a5 282 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 92:4fc01daae5a5 283 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 92:4fc01daae5a5 284 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 92:4fc01daae5a5 285 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 92:4fc01daae5a5 286 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 92:4fc01daae5a5 287 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 92:4fc01daae5a5 288 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 92:4fc01daae5a5 289 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 92:4fc01daae5a5 290 } CAN_TypeDef;
bogdanm 92:4fc01daae5a5 291
bogdanm 92:4fc01daae5a5 292 /**
bogdanm 92:4fc01daae5a5 293 * @brief CRC calculation unit
bogdanm 92:4fc01daae5a5 294 */
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 typedef struct
bogdanm 92:4fc01daae5a5 297 {
bogdanm 92:4fc01daae5a5 298 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 299 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 300 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 92:4fc01daae5a5 301 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 92:4fc01daae5a5 302 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 303 } CRC_TypeDef;
bogdanm 92:4fc01daae5a5 304
bogdanm 92:4fc01daae5a5 305 /**
bogdanm 92:4fc01daae5a5 306 * @brief Digital to Analog Converter
bogdanm 92:4fc01daae5a5 307 */
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 typedef struct
bogdanm 92:4fc01daae5a5 310 {
bogdanm 92:4fc01daae5a5 311 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 312 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 313 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 314 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 315 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 316 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 317 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 318 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 319 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 320 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 321 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 322 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 323 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 324 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 325 } DAC_TypeDef;
bogdanm 92:4fc01daae5a5 326
bogdanm 92:4fc01daae5a5 327 /**
bogdanm 92:4fc01daae5a5 328 * @brief Debug MCU
bogdanm 92:4fc01daae5a5 329 */
bogdanm 92:4fc01daae5a5 330
bogdanm 92:4fc01daae5a5 331 typedef struct
bogdanm 92:4fc01daae5a5 332 {
bogdanm 92:4fc01daae5a5 333 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 334 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 335 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 336 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 337 }DBGMCU_TypeDef;
bogdanm 92:4fc01daae5a5 338
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 /**
bogdanm 92:4fc01daae5a5 341 * @brief DMA Controller
bogdanm 92:4fc01daae5a5 342 */
bogdanm 92:4fc01daae5a5 343
bogdanm 92:4fc01daae5a5 344 typedef struct
bogdanm 92:4fc01daae5a5 345 {
bogdanm 92:4fc01daae5a5 346 __IO uint32_t CR; /*!< DMA stream x configuration register */
bogdanm 92:4fc01daae5a5 347 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
bogdanm 92:4fc01daae5a5 348 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
bogdanm 92:4fc01daae5a5 349 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
bogdanm 92:4fc01daae5a5 350 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
bogdanm 92:4fc01daae5a5 351 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
bogdanm 92:4fc01daae5a5 352 } DMA_Stream_TypeDef;
bogdanm 92:4fc01daae5a5 353
bogdanm 92:4fc01daae5a5 354 typedef struct
bogdanm 92:4fc01daae5a5 355 {
bogdanm 92:4fc01daae5a5 356 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 357 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 358 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 359 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 360 } DMA_TypeDef;
bogdanm 92:4fc01daae5a5 361
bogdanm 92:4fc01daae5a5 362
bogdanm 92:4fc01daae5a5 363 /**
bogdanm 92:4fc01daae5a5 364 * @brief External Interrupt/Event Controller
bogdanm 92:4fc01daae5a5 365 */
bogdanm 92:4fc01daae5a5 366
bogdanm 92:4fc01daae5a5 367 typedef struct
bogdanm 92:4fc01daae5a5 368 {
bogdanm 92:4fc01daae5a5 369 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 370 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 371 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 372 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 373 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 374 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 375 } EXTI_TypeDef;
bogdanm 92:4fc01daae5a5 376
bogdanm 92:4fc01daae5a5 377 /**
bogdanm 92:4fc01daae5a5 378 * @brief FLASH Registers
bogdanm 92:4fc01daae5a5 379 */
bogdanm 92:4fc01daae5a5 380
bogdanm 92:4fc01daae5a5 381 typedef struct
bogdanm 92:4fc01daae5a5 382 {
bogdanm 92:4fc01daae5a5 383 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 384 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 385 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 386 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 387 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 388 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 389 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 390 } FLASH_TypeDef;
bogdanm 92:4fc01daae5a5 391
bogdanm 92:4fc01daae5a5 392
bogdanm 92:4fc01daae5a5 393 /**
bogdanm 92:4fc01daae5a5 394 * @brief Flexible Static Memory Controller
bogdanm 92:4fc01daae5a5 395 */
bogdanm 92:4fc01daae5a5 396
bogdanm 92:4fc01daae5a5 397 typedef struct
bogdanm 92:4fc01daae5a5 398 {
bogdanm 92:4fc01daae5a5 399 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
bogdanm 92:4fc01daae5a5 400 } FSMC_Bank1_TypeDef;
bogdanm 92:4fc01daae5a5 401
bogdanm 92:4fc01daae5a5 402 /**
bogdanm 92:4fc01daae5a5 403 * @brief Flexible Static Memory Controller Bank1E
bogdanm 92:4fc01daae5a5 404 */
bogdanm 92:4fc01daae5a5 405
bogdanm 92:4fc01daae5a5 406 typedef struct
bogdanm 92:4fc01daae5a5 407 {
bogdanm 92:4fc01daae5a5 408 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
bogdanm 92:4fc01daae5a5 409 } FSMC_Bank1E_TypeDef;
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 /**
bogdanm 92:4fc01daae5a5 412 * @brief Flexible Static Memory Controller Bank2
bogdanm 92:4fc01daae5a5 413 */
bogdanm 92:4fc01daae5a5 414
bogdanm 92:4fc01daae5a5 415 typedef struct
bogdanm 92:4fc01daae5a5 416 {
bogdanm 92:4fc01daae5a5 417 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 418 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 419 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
bogdanm 92:4fc01daae5a5 420 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
bogdanm 92:4fc01daae5a5 421 uint32_t RESERVED0; /*!< Reserved, 0x70 */
bogdanm 92:4fc01daae5a5 422 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 423 uint32_t RESERVED1; /*!< Reserved, 0x78 */
bogdanm 92:4fc01daae5a5 424 uint32_t RESERVED2; /*!< Reserved, 0x7C */
bogdanm 92:4fc01daae5a5 425 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 426 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 427 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
bogdanm 92:4fc01daae5a5 428 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
bogdanm 92:4fc01daae5a5 429 uint32_t RESERVED3; /*!< Reserved, 0x90 */
bogdanm 92:4fc01daae5a5 430 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
bogdanm 92:4fc01daae5a5 431 } FSMC_Bank2_3_TypeDef;
bogdanm 92:4fc01daae5a5 432
bogdanm 92:4fc01daae5a5 433 /**
bogdanm 92:4fc01daae5a5 434 * @brief Flexible Static Memory Controller Bank4
bogdanm 92:4fc01daae5a5 435 */
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 typedef struct
bogdanm 92:4fc01daae5a5 438 {
bogdanm 92:4fc01daae5a5 439 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
bogdanm 92:4fc01daae5a5 440 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
bogdanm 92:4fc01daae5a5 441 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
bogdanm 92:4fc01daae5a5 442 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
bogdanm 92:4fc01daae5a5 443 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
bogdanm 92:4fc01daae5a5 444 } FSMC_Bank4_TypeDef;
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 /**
bogdanm 92:4fc01daae5a5 448 * @brief General Purpose I/O
bogdanm 92:4fc01daae5a5 449 */
bogdanm 92:4fc01daae5a5 450
bogdanm 92:4fc01daae5a5 451 typedef struct
bogdanm 92:4fc01daae5a5 452 {
bogdanm 92:4fc01daae5a5 453 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 454 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 455 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 456 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 457 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 458 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 459 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 460 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 461 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 92:4fc01daae5a5 462 } GPIO_TypeDef;
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 /**
bogdanm 92:4fc01daae5a5 465 * @brief System configuration controller
bogdanm 92:4fc01daae5a5 466 */
bogdanm 92:4fc01daae5a5 467
bogdanm 92:4fc01daae5a5 468 typedef struct
bogdanm 92:4fc01daae5a5 469 {
bogdanm 92:4fc01daae5a5 470 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 471 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 472 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
bogdanm 92:4fc01daae5a5 473 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 92:4fc01daae5a5 474 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 475 } SYSCFG_TypeDef;
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 /**
bogdanm 92:4fc01daae5a5 478 * @brief Inter-integrated Circuit Interface
bogdanm 92:4fc01daae5a5 479 */
bogdanm 92:4fc01daae5a5 480
bogdanm 92:4fc01daae5a5 481 typedef struct
bogdanm 92:4fc01daae5a5 482 {
bogdanm 92:4fc01daae5a5 483 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 484 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 485 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 486 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 487 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 488 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 489 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 490 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 491 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 492 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 493 } I2C_TypeDef;
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 /**
bogdanm 92:4fc01daae5a5 496 * @brief Independent WATCHDOG
bogdanm 92:4fc01daae5a5 497 */
bogdanm 92:4fc01daae5a5 498
bogdanm 92:4fc01daae5a5 499 typedef struct
bogdanm 92:4fc01daae5a5 500 {
bogdanm 92:4fc01daae5a5 501 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 502 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 503 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 504 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 505 } IWDG_TypeDef;
bogdanm 92:4fc01daae5a5 506
bogdanm 92:4fc01daae5a5 507 /**
bogdanm 92:4fc01daae5a5 508 * @brief Power Control
bogdanm 92:4fc01daae5a5 509 */
bogdanm 92:4fc01daae5a5 510
bogdanm 92:4fc01daae5a5 511 typedef struct
bogdanm 92:4fc01daae5a5 512 {
bogdanm 92:4fc01daae5a5 513 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 514 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 515 } PWR_TypeDef;
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 /**
bogdanm 92:4fc01daae5a5 518 * @brief Reset and Clock Control
bogdanm 92:4fc01daae5a5 519 */
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 typedef struct
bogdanm 92:4fc01daae5a5 522 {
bogdanm 92:4fc01daae5a5 523 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 524 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 525 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 526 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 527 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 528 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 529 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 530 uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 92:4fc01daae5a5 531 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 532 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 533 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
bogdanm 92:4fc01daae5a5 534 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 535 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 536 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 537 uint32_t RESERVED2; /*!< Reserved, 0x3C */
bogdanm 92:4fc01daae5a5 538 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 539 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 540 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
bogdanm 92:4fc01daae5a5 541 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 542 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
bogdanm 92:4fc01daae5a5 543 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
bogdanm 92:4fc01daae5a5 544 uint32_t RESERVED4; /*!< Reserved, 0x5C */
bogdanm 92:4fc01daae5a5 545 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 546 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 547 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
bogdanm 92:4fc01daae5a5 548 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
bogdanm 92:4fc01daae5a5 549 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 550 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
bogdanm 92:4fc01daae5a5 551 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 552 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 553
bogdanm 92:4fc01daae5a5 554 } RCC_TypeDef;
bogdanm 92:4fc01daae5a5 555
bogdanm 92:4fc01daae5a5 556 /**
bogdanm 92:4fc01daae5a5 557 * @brief Real-Time Clock
bogdanm 92:4fc01daae5a5 558 */
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 typedef struct
bogdanm 92:4fc01daae5a5 561 {
bogdanm 92:4fc01daae5a5 562 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 563 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 564 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 565 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 566 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 567 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 568 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 569 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 570 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 571 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 572 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 573 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 574 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 575 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 576 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 577 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 578 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 579 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 580 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 581 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 92:4fc01daae5a5 582 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 583 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 92:4fc01daae5a5 584 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 92:4fc01daae5a5 585 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 92:4fc01daae5a5 586 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 92:4fc01daae5a5 587 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 92:4fc01daae5a5 588 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 92:4fc01daae5a5 589 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 92:4fc01daae5a5 590 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 92:4fc01daae5a5 591 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 92:4fc01daae5a5 592 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 92:4fc01daae5a5 593 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 92:4fc01daae5a5 594 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 595 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 92:4fc01daae5a5 596 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 92:4fc01daae5a5 597 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 92:4fc01daae5a5 598 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
bogdanm 92:4fc01daae5a5 599 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
bogdanm 92:4fc01daae5a5 600 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
bogdanm 92:4fc01daae5a5 601 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
bogdanm 92:4fc01daae5a5 602 } RTC_TypeDef;
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604
bogdanm 92:4fc01daae5a5 605 /**
bogdanm 92:4fc01daae5a5 606 * @brief SD host Interface
bogdanm 92:4fc01daae5a5 607 */
bogdanm 92:4fc01daae5a5 608
bogdanm 92:4fc01daae5a5 609 typedef struct
bogdanm 92:4fc01daae5a5 610 {
bogdanm 92:4fc01daae5a5 611 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 612 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 613 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 614 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 615 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 616 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 617 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 618 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 619 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 620 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 621 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 622 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 623 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 624 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 625 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 626 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 627 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
bogdanm 92:4fc01daae5a5 628 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 629 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
bogdanm 92:4fc01daae5a5 630 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
bogdanm 92:4fc01daae5a5 631 } SDIO_TypeDef;
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633 /**
bogdanm 92:4fc01daae5a5 634 * @brief Serial Peripheral Interface
bogdanm 92:4fc01daae5a5 635 */
bogdanm 92:4fc01daae5a5 636
bogdanm 92:4fc01daae5a5 637 typedef struct
bogdanm 92:4fc01daae5a5 638 {
bogdanm 92:4fc01daae5a5 639 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 640 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 641 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 642 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 643 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 644 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 645 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 646 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 647 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 648 } SPI_TypeDef;
bogdanm 92:4fc01daae5a5 649
bogdanm 92:4fc01daae5a5 650 /**
bogdanm 92:4fc01daae5a5 651 * @brief TIM
bogdanm 92:4fc01daae5a5 652 */
bogdanm 92:4fc01daae5a5 653
bogdanm 92:4fc01daae5a5 654 typedef struct
bogdanm 92:4fc01daae5a5 655 {
bogdanm 92:4fc01daae5a5 656 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 657 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 658 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 659 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 660 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 661 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 662 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 663 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 664 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 665 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 666 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 92:4fc01daae5a5 667 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 668 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 92:4fc01daae5a5 669 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 92:4fc01daae5a5 670 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 92:4fc01daae5a5 671 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 92:4fc01daae5a5 672 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 673 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 674 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 675 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 92:4fc01daae5a5 676 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 92:4fc01daae5a5 677 } TIM_TypeDef;
bogdanm 92:4fc01daae5a5 678
bogdanm 92:4fc01daae5a5 679 /**
bogdanm 92:4fc01daae5a5 680 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 92:4fc01daae5a5 681 */
bogdanm 92:4fc01daae5a5 682
bogdanm 92:4fc01daae5a5 683 typedef struct
bogdanm 92:4fc01daae5a5 684 {
bogdanm 92:4fc01daae5a5 685 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 686 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 687 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 688 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 689 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 690 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 691 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 692 } USART_TypeDef;
bogdanm 92:4fc01daae5a5 693
bogdanm 92:4fc01daae5a5 694 /**
bogdanm 92:4fc01daae5a5 695 * @brief Window WATCHDOG
bogdanm 92:4fc01daae5a5 696 */
bogdanm 92:4fc01daae5a5 697
bogdanm 92:4fc01daae5a5 698 typedef struct
bogdanm 92:4fc01daae5a5 699 {
bogdanm 92:4fc01daae5a5 700 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 701 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 702 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 703 } WWDG_TypeDef;
bogdanm 92:4fc01daae5a5 704
bogdanm 92:4fc01daae5a5 705
bogdanm 92:4fc01daae5a5 706 /**
bogdanm 92:4fc01daae5a5 707 * @brief RNG
bogdanm 92:4fc01daae5a5 708 */
bogdanm 92:4fc01daae5a5 709
bogdanm 92:4fc01daae5a5 710 typedef struct
bogdanm 92:4fc01daae5a5 711 {
bogdanm 92:4fc01daae5a5 712 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 713 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 714 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 715 } RNG_TypeDef;
bogdanm 92:4fc01daae5a5 716
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718
bogdanm 92:4fc01daae5a5 719 /**
bogdanm 92:4fc01daae5a5 720 * @brief __USB_OTG_Core_register
bogdanm 92:4fc01daae5a5 721 */
bogdanm 92:4fc01daae5a5 722 typedef struct
bogdanm 92:4fc01daae5a5 723 {
bogdanm 92:4fc01daae5a5 724 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
bogdanm 92:4fc01daae5a5 725 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
bogdanm 92:4fc01daae5a5 726 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
bogdanm 92:4fc01daae5a5 727 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
bogdanm 92:4fc01daae5a5 728 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
bogdanm 92:4fc01daae5a5 729 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
bogdanm 92:4fc01daae5a5 730 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
bogdanm 92:4fc01daae5a5 731 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
bogdanm 92:4fc01daae5a5 732 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
bogdanm 92:4fc01daae5a5 733 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
bogdanm 92:4fc01daae5a5 734 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
bogdanm 92:4fc01daae5a5 735 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
bogdanm 92:4fc01daae5a5 736 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
bogdanm 92:4fc01daae5a5 737 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
bogdanm 92:4fc01daae5a5 738 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
bogdanm 92:4fc01daae5a5 739 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
bogdanm 92:4fc01daae5a5 740 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
bogdanm 92:4fc01daae5a5 741 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
bogdanm 92:4fc01daae5a5 742 }
bogdanm 92:4fc01daae5a5 743 USB_OTG_GlobalTypeDef;
bogdanm 92:4fc01daae5a5 744
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746
bogdanm 92:4fc01daae5a5 747 /**
bogdanm 92:4fc01daae5a5 748 * @brief __device_Registers
bogdanm 92:4fc01daae5a5 749 */
bogdanm 92:4fc01daae5a5 750 typedef struct
bogdanm 92:4fc01daae5a5 751 {
bogdanm 92:4fc01daae5a5 752 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
bogdanm 92:4fc01daae5a5 753 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
bogdanm 92:4fc01daae5a5 754 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
bogdanm 92:4fc01daae5a5 755 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
bogdanm 92:4fc01daae5a5 756 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
bogdanm 92:4fc01daae5a5 757 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
bogdanm 92:4fc01daae5a5 758 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
bogdanm 92:4fc01daae5a5 759 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
bogdanm 92:4fc01daae5a5 760 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
bogdanm 92:4fc01daae5a5 761 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
bogdanm 92:4fc01daae5a5 762 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
bogdanm 92:4fc01daae5a5 763 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
bogdanm 92:4fc01daae5a5 764 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
bogdanm 92:4fc01daae5a5 765 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
bogdanm 92:4fc01daae5a5 766 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
bogdanm 92:4fc01daae5a5 767 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
bogdanm 92:4fc01daae5a5 768 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
bogdanm 92:4fc01daae5a5 769 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
bogdanm 92:4fc01daae5a5 770 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
bogdanm 92:4fc01daae5a5 771 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
bogdanm 92:4fc01daae5a5 772 }
bogdanm 92:4fc01daae5a5 773 USB_OTG_DeviceTypeDef;
bogdanm 92:4fc01daae5a5 774
bogdanm 92:4fc01daae5a5 775
bogdanm 92:4fc01daae5a5 776 /**
bogdanm 92:4fc01daae5a5 777 * @brief __IN_Endpoint-Specific_Register
bogdanm 92:4fc01daae5a5 778 */
bogdanm 92:4fc01daae5a5 779 typedef struct
bogdanm 92:4fc01daae5a5 780 {
bogdanm 92:4fc01daae5a5 781 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
bogdanm 92:4fc01daae5a5 782 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
bogdanm 92:4fc01daae5a5 783 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
bogdanm 92:4fc01daae5a5 784 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
bogdanm 92:4fc01daae5a5 785 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
bogdanm 92:4fc01daae5a5 786 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
bogdanm 92:4fc01daae5a5 787 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
bogdanm 92:4fc01daae5a5 788 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
bogdanm 92:4fc01daae5a5 789 }
bogdanm 92:4fc01daae5a5 790 USB_OTG_INEndpointTypeDef;
bogdanm 92:4fc01daae5a5 791
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 /**
bogdanm 92:4fc01daae5a5 794 * @brief __OUT_Endpoint-Specific_Registers
bogdanm 92:4fc01daae5a5 795 */
bogdanm 92:4fc01daae5a5 796 typedef struct
bogdanm 92:4fc01daae5a5 797 {
bogdanm 92:4fc01daae5a5 798 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
bogdanm 92:4fc01daae5a5 799 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
bogdanm 92:4fc01daae5a5 800 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
bogdanm 92:4fc01daae5a5 801 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
bogdanm 92:4fc01daae5a5 802 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
bogdanm 92:4fc01daae5a5 803 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
bogdanm 92:4fc01daae5a5 804 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
bogdanm 92:4fc01daae5a5 805 }
bogdanm 92:4fc01daae5a5 806 USB_OTG_OUTEndpointTypeDef;
bogdanm 92:4fc01daae5a5 807
bogdanm 92:4fc01daae5a5 808
bogdanm 92:4fc01daae5a5 809 /**
bogdanm 92:4fc01daae5a5 810 * @brief __Host_Mode_Register_Structures
bogdanm 92:4fc01daae5a5 811 */
bogdanm 92:4fc01daae5a5 812 typedef struct
bogdanm 92:4fc01daae5a5 813 {
bogdanm 92:4fc01daae5a5 814 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
bogdanm 92:4fc01daae5a5 815 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
bogdanm 92:4fc01daae5a5 816 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
bogdanm 92:4fc01daae5a5 817 uint32_t Reserved40C; /* Reserved 40Ch*/
bogdanm 92:4fc01daae5a5 818 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
bogdanm 92:4fc01daae5a5 819 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
bogdanm 92:4fc01daae5a5 820 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
bogdanm 92:4fc01daae5a5 821 }
bogdanm 92:4fc01daae5a5 822 USB_OTG_HostTypeDef;
bogdanm 92:4fc01daae5a5 823
bogdanm 92:4fc01daae5a5 824
bogdanm 92:4fc01daae5a5 825 /**
bogdanm 92:4fc01daae5a5 826 * @brief __Host_Channel_Specific_Registers
bogdanm 92:4fc01daae5a5 827 */
bogdanm 92:4fc01daae5a5 828 typedef struct
bogdanm 92:4fc01daae5a5 829 {
bogdanm 92:4fc01daae5a5 830 __IO uint32_t HCCHAR;
bogdanm 92:4fc01daae5a5 831 __IO uint32_t HCSPLT;
bogdanm 92:4fc01daae5a5 832 __IO uint32_t HCINT;
bogdanm 92:4fc01daae5a5 833 __IO uint32_t HCINTMSK;
bogdanm 92:4fc01daae5a5 834 __IO uint32_t HCTSIZ;
bogdanm 92:4fc01daae5a5 835 __IO uint32_t HCDMA;
bogdanm 92:4fc01daae5a5 836 uint32_t Reserved[2];
bogdanm 92:4fc01daae5a5 837 }
bogdanm 92:4fc01daae5a5 838 USB_OTG_HostChannelTypeDef;
bogdanm 92:4fc01daae5a5 839
bogdanm 92:4fc01daae5a5 840
bogdanm 92:4fc01daae5a5 841 /**
bogdanm 92:4fc01daae5a5 842 * @brief Peripheral_memory_map
bogdanm 92:4fc01daae5a5 843 */
Kojto 122:f9eeca106725 844 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 122:f9eeca106725 845 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
Kojto 122:f9eeca106725 846 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
Kojto 122:f9eeca106725 847 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
Kojto 122:f9eeca106725 848 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
Kojto 122:f9eeca106725 849 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 122:f9eeca106725 850 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
Kojto 122:f9eeca106725 851 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 852 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 853 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
Kojto 122:f9eeca106725 854 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 855 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
Kojto 122:f9eeca106725 856 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
bogdanm 92:4fc01daae5a5 857
bogdanm 92:4fc01daae5a5 858 /* Legacy defines */
bogdanm 92:4fc01daae5a5 859 #define SRAM_BASE SRAM1_BASE
bogdanm 92:4fc01daae5a5 860 #define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm 92:4fc01daae5a5 861
bogdanm 92:4fc01daae5a5 862
bogdanm 92:4fc01daae5a5 863 /*!< Peripheral memory map */
bogdanm 92:4fc01daae5a5 864 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 865 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 866 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 867 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
bogdanm 92:4fc01daae5a5 868
bogdanm 92:4fc01daae5a5 869 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 870 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 871 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 872 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 873 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 874 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 875 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 876 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 877 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 878 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 879 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 880 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 881 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 882 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 883 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 884 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 885 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 886 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 887 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 888 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
Kojto 122:f9eeca106725 889 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
Kojto 122:f9eeca106725 890 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 891 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 892 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 893 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 894 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
Kojto 122:f9eeca106725 895 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto 122:f9eeca106725 896 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 899 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 900 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 901 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 902 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 903 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 904 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
Kojto 122:f9eeca106725 905 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
Kojto 122:f9eeca106725 906 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto 122:f9eeca106725 907 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 908 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 909 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 910 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 911 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 912 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 913 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
bogdanm 92:4fc01daae5a5 914
bogdanm 92:4fc01daae5a5 915 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 916 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 917 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 918 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 919 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 920 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 921 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 922 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 923 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 924 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 925 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 926 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 927 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 928 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 929 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto 122:f9eeca106725 930 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto 122:f9eeca106725 931 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto 122:f9eeca106725 932 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto 122:f9eeca106725 933 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto 122:f9eeca106725 934 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto 122:f9eeca106725 935 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto 122:f9eeca106725 936 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto 122:f9eeca106725 937 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 938 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto 122:f9eeca106725 939 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto 122:f9eeca106725 940 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto 122:f9eeca106725 941 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto 122:f9eeca106725 942 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto 122:f9eeca106725 943 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto 122:f9eeca106725 944 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto 122:f9eeca106725 945 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
bogdanm 92:4fc01daae5a5 946
bogdanm 92:4fc01daae5a5 947 /*!< AHB2 peripherals */
Kojto 122:f9eeca106725 948 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
bogdanm 92:4fc01daae5a5 949
bogdanm 92:4fc01daae5a5 950 /*!< FSMC Bankx registers base address */
Kojto 122:f9eeca106725 951 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
Kojto 122:f9eeca106725 952 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
Kojto 122:f9eeca106725 953 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
Kojto 122:f9eeca106725 954 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
bogdanm 92:4fc01daae5a5 955
bogdanm 92:4fc01daae5a5 956 /* Debug MCU registers base address */
Kojto 122:f9eeca106725 957 #define DBGMCU_BASE 0xE0042000U
bogdanm 92:4fc01daae5a5 958
bogdanm 92:4fc01daae5a5 959 /*!< USB registers base address */
Kojto 122:f9eeca106725 960 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
Kojto 122:f9eeca106725 961 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto 122:f9eeca106725 962
Kojto 122:f9eeca106725 963 #define USB_OTG_GLOBAL_BASE 0x000U
Kojto 122:f9eeca106725 964 #define USB_OTG_DEVICE_BASE 0x800U
Kojto 122:f9eeca106725 965 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto 122:f9eeca106725 966 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto 122:f9eeca106725 967 #define USB_OTG_EP_REG_SIZE 0x20U
Kojto 122:f9eeca106725 968 #define USB_OTG_HOST_BASE 0x400U
Kojto 122:f9eeca106725 969 #define USB_OTG_HOST_PORT_BASE 0x440U
Kojto 122:f9eeca106725 970 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto 122:f9eeca106725 971 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto 122:f9eeca106725 972 #define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto 122:f9eeca106725 973 #define USB_OTG_FIFO_BASE 0x1000U
Kojto 122:f9eeca106725 974 #define USB_OTG_FIFO_SIZE 0x1000U
bogdanm 92:4fc01daae5a5 975
bogdanm 92:4fc01daae5a5 976 /**
bogdanm 92:4fc01daae5a5 977 * @}
bogdanm 92:4fc01daae5a5 978 */
bogdanm 92:4fc01daae5a5 979
bogdanm 92:4fc01daae5a5 980 /** @addtogroup Peripheral_declaration
bogdanm 92:4fc01daae5a5 981 * @{
bogdanm 92:4fc01daae5a5 982 */
bogdanm 92:4fc01daae5a5 983 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 92:4fc01daae5a5 984 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 92:4fc01daae5a5 985 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 92:4fc01daae5a5 986 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 92:4fc01daae5a5 987 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 92:4fc01daae5a5 988 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 92:4fc01daae5a5 989 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm 92:4fc01daae5a5 990 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm 92:4fc01daae5a5 991 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 92:4fc01daae5a5 992 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 92:4fc01daae5a5 993 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 92:4fc01daae5a5 994 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 92:4fc01daae5a5 995 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 92:4fc01daae5a5 996 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 92:4fc01daae5a5 997 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 92:4fc01daae5a5 998 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 92:4fc01daae5a5 999 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 92:4fc01daae5a5 1000 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 92:4fc01daae5a5 1001 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 92:4fc01daae5a5 1002 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 92:4fc01daae5a5 1003 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 92:4fc01daae5a5 1004 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 92:4fc01daae5a5 1005 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 92:4fc01daae5a5 1006 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 92:4fc01daae5a5 1007 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm 92:4fc01daae5a5 1008 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 92:4fc01daae5a5 1009 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 92:4fc01daae5a5 1010 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 92:4fc01daae5a5 1011 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 92:4fc01daae5a5 1012 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 92:4fc01daae5a5 1013 #define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm 92:4fc01daae5a5 1014 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 92:4fc01daae5a5 1015 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 92:4fc01daae5a5 1016 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 92:4fc01daae5a5 1017 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 92:4fc01daae5a5 1018 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 92:4fc01daae5a5 1019 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 92:4fc01daae5a5 1020 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 92:4fc01daae5a5 1021 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 92:4fc01daae5a5 1022 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 92:4fc01daae5a5 1023 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 92:4fc01daae5a5 1024 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 92:4fc01daae5a5 1025 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 92:4fc01daae5a5 1026 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 92:4fc01daae5a5 1027 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 92:4fc01daae5a5 1028 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 92:4fc01daae5a5 1029 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 92:4fc01daae5a5 1030 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 92:4fc01daae5a5 1031 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm 92:4fc01daae5a5 1032 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 92:4fc01daae5a5 1033 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
bogdanm 92:4fc01daae5a5 1034 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 92:4fc01daae5a5 1035 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 92:4fc01daae5a5 1036 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 92:4fc01daae5a5 1037 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 92:4fc01daae5a5 1038 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm 92:4fc01daae5a5 1039 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm 92:4fc01daae5a5 1040 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm 92:4fc01daae5a5 1041 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm 92:4fc01daae5a5 1042 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm 92:4fc01daae5a5 1043 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm 92:4fc01daae5a5 1044 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm 92:4fc01daae5a5 1045 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm 92:4fc01daae5a5 1046 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 92:4fc01daae5a5 1047 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm 92:4fc01daae5a5 1048 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm 92:4fc01daae5a5 1049 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm 92:4fc01daae5a5 1050 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm 92:4fc01daae5a5 1051 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm 92:4fc01daae5a5 1052 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm 92:4fc01daae5a5 1053 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 92:4fc01daae5a5 1054 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm 92:4fc01daae5a5 1055 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 92:4fc01daae5a5 1056 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm 92:4fc01daae5a5 1057 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm 92:4fc01daae5a5 1058 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
bogdanm 92:4fc01daae5a5 1059 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm 92:4fc01daae5a5 1060
bogdanm 92:4fc01daae5a5 1061 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 92:4fc01daae5a5 1062
bogdanm 92:4fc01daae5a5 1063 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
bogdanm 92:4fc01daae5a5 1064 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
bogdanm 92:4fc01daae5a5 1065
bogdanm 92:4fc01daae5a5 1066 /**
bogdanm 92:4fc01daae5a5 1067 * @}
bogdanm 92:4fc01daae5a5 1068 */
bogdanm 92:4fc01daae5a5 1069
bogdanm 92:4fc01daae5a5 1070 /** @addtogroup Exported_constants
bogdanm 92:4fc01daae5a5 1071 * @{
bogdanm 92:4fc01daae5a5 1072 */
bogdanm 92:4fc01daae5a5 1073
bogdanm 92:4fc01daae5a5 1074 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 92:4fc01daae5a5 1075 * @{
bogdanm 92:4fc01daae5a5 1076 */
bogdanm 92:4fc01daae5a5 1077
bogdanm 92:4fc01daae5a5 1078 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1079 /* Peripheral Registers_Bits_Definition */
bogdanm 92:4fc01daae5a5 1080 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1081
bogdanm 92:4fc01daae5a5 1082 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1083 /* */
bogdanm 92:4fc01daae5a5 1084 /* Analog to Digital Converter */
bogdanm 92:4fc01daae5a5 1085 /* */
bogdanm 92:4fc01daae5a5 1086 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1087 /******************** Bit definition for ADC_SR register ********************/
Kojto 122:f9eeca106725 1088 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
Kojto 122:f9eeca106725 1089 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
Kojto 122:f9eeca106725 1090 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
Kojto 122:f9eeca106725 1091 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
Kojto 122:f9eeca106725 1092 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
Kojto 122:f9eeca106725 1093 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
bogdanm 92:4fc01daae5a5 1094
bogdanm 92:4fc01daae5a5 1095 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 122:f9eeca106725 1096 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 122:f9eeca106725 1097 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1098 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1099 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1100 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1101 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1102 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
Kojto 122:f9eeca106725 1103 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
Kojto 122:f9eeca106725 1104 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
Kojto 122:f9eeca106725 1105 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
Kojto 122:f9eeca106725 1106 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
Kojto 122:f9eeca106725 1107 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
Kojto 122:f9eeca106725 1108 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
Kojto 122:f9eeca106725 1109 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
Kojto 122:f9eeca106725 1110 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 122:f9eeca106725 1111 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1112 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1113 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1114 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
Kojto 122:f9eeca106725 1115 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
Kojto 122:f9eeca106725 1116 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
Kojto 122:f9eeca106725 1117 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1118 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1119 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
bogdanm 92:4fc01daae5a5 1120
bogdanm 92:4fc01daae5a5 1121 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 122:f9eeca106725 1122 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
Kojto 122:f9eeca106725 1123 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
Kojto 122:f9eeca106725 1124 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
Kojto 122:f9eeca106725 1125 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
Kojto 122:f9eeca106725 1126 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
Kojto 122:f9eeca106725 1127 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
Kojto 122:f9eeca106725 1128 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 122:f9eeca106725 1129 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1130 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1131 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1132 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1133 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 122:f9eeca106725 1134 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1135 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1136 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
Kojto 122:f9eeca106725 1137 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 122:f9eeca106725 1138 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1139 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1140 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1141 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1142 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 122:f9eeca106725 1143 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1144 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1145 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
bogdanm 92:4fc01daae5a5 1146
bogdanm 92:4fc01daae5a5 1147 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 122:f9eeca106725 1148 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 122:f9eeca106725 1149 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1150 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1151 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1152 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 122:f9eeca106725 1153 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1154 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1155 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1156 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 122:f9eeca106725 1157 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1158 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1159 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1160 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 122:f9eeca106725 1161 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1162 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1163 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1164 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 122:f9eeca106725 1165 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1166 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1167 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1168 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 122:f9eeca106725 1169 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1170 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1171 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1172 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 122:f9eeca106725 1173 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1174 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1175 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1176 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 122:f9eeca106725 1177 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1178 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1179 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1180 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 122:f9eeca106725 1181 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1182 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1183 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1184
bogdanm 92:4fc01daae5a5 1185 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 122:f9eeca106725 1186 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 122:f9eeca106725 1187 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1188 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1189 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1190 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 122:f9eeca106725 1191 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1192 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1193 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1194 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 122:f9eeca106725 1195 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1196 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1197 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1198 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 122:f9eeca106725 1199 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1200 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1201 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1202 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 122:f9eeca106725 1203 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1204 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1205 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1206 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 122:f9eeca106725 1207 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1208 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1209 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1210 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 122:f9eeca106725 1211 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1212 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1213 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1214 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 122:f9eeca106725 1215 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1216 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1217 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1218 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 122:f9eeca106725 1219 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1220 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1221 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1222 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 122:f9eeca106725 1223 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1224 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1225 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 1226
bogdanm 92:4fc01daae5a5 1227 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 122:f9eeca106725 1228 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
bogdanm 92:4fc01daae5a5 1229
bogdanm 92:4fc01daae5a5 1230 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 122:f9eeca106725 1231 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
bogdanm 92:4fc01daae5a5 1232
bogdanm 92:4fc01daae5a5 1233 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 122:f9eeca106725 1234 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
bogdanm 92:4fc01daae5a5 1235
bogdanm 92:4fc01daae5a5 1236 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 122:f9eeca106725 1237 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
bogdanm 92:4fc01daae5a5 1238
bogdanm 92:4fc01daae5a5 1239 /******************* Bit definition for ADC_HTR register ********************/
Kojto 122:f9eeca106725 1240 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
bogdanm 92:4fc01daae5a5 1241
bogdanm 92:4fc01daae5a5 1242 /******************* Bit definition for ADC_LTR register ********************/
Kojto 122:f9eeca106725 1243 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
bogdanm 92:4fc01daae5a5 1244
bogdanm 92:4fc01daae5a5 1245 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 122:f9eeca106725 1246 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 122:f9eeca106725 1247 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1248 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1249 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1250 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1251 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1252 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 122:f9eeca106725 1253 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1254 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1255 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1256 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1257 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1258 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 122:f9eeca106725 1259 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1260 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1261 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1262 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1263 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1264 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 122:f9eeca106725 1265 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1266 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1267 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1268 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1269 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1270 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 122:f9eeca106725 1271 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1272 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1273 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1274 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 1275
bogdanm 92:4fc01daae5a5 1276 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 122:f9eeca106725 1277 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 122:f9eeca106725 1278 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1279 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1280 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1281 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1282 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1283 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 122:f9eeca106725 1284 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1285 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1286 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1287 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1288 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1289 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 122:f9eeca106725 1290 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1291 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1292 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1293 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1294 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1295 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 122:f9eeca106725 1296 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1297 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1298 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1299 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1300 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1301 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 122:f9eeca106725 1302 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1303 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1304 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1305 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1306 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1307 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 122:f9eeca106725 1308 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1309 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1310 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1311 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1312 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1313
bogdanm 92:4fc01daae5a5 1314 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 122:f9eeca106725 1315 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 122:f9eeca106725 1316 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1317 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1318 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1319 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1320 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1321 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 122:f9eeca106725 1322 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1323 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1324 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1325 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1326 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1327 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 122:f9eeca106725 1328 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1329 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1330 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1331 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1332 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1333 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 122:f9eeca106725 1334 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1335 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1336 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1337 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1338 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1339 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 122:f9eeca106725 1340 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1341 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1342 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1343 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1344 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1345 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 122:f9eeca106725 1346 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1347 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1348 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1349 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1350 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 1351
bogdanm 92:4fc01daae5a5 1352 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 122:f9eeca106725 1353 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 122:f9eeca106725 1354 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1355 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1356 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1357 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1358 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1359 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 122:f9eeca106725 1360 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1361 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1362 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1363 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1364 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1365 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 122:f9eeca106725 1366 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1367 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1368 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1369 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1370 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1371 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 122:f9eeca106725 1372 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1373 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1374 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1375 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1376 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1377 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 122:f9eeca106725 1378 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1379 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 1380
bogdanm 92:4fc01daae5a5 1381 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 122:f9eeca106725 1382 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
bogdanm 92:4fc01daae5a5 1383
bogdanm 92:4fc01daae5a5 1384 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 122:f9eeca106725 1385 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
bogdanm 92:4fc01daae5a5 1386
bogdanm 92:4fc01daae5a5 1387 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 122:f9eeca106725 1388 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
bogdanm 92:4fc01daae5a5 1389
bogdanm 92:4fc01daae5a5 1390 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 122:f9eeca106725 1391 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
bogdanm 92:4fc01daae5a5 1392
bogdanm 92:4fc01daae5a5 1393 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1394 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
Kojto 122:f9eeca106725 1395 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
bogdanm 92:4fc01daae5a5 1396
bogdanm 92:4fc01daae5a5 1397 /******************* Bit definition for ADC_CSR register ********************/
Kojto 122:f9eeca106725 1398 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
Kojto 122:f9eeca106725 1399 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
Kojto 122:f9eeca106725 1400 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
Kojto 122:f9eeca106725 1401 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
Kojto 122:f9eeca106725 1402 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
Kojto 122:f9eeca106725 1403 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
Kojto 122:f9eeca106725 1404 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
Kojto 122:f9eeca106725 1405 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
Kojto 122:f9eeca106725 1406 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
Kojto 122:f9eeca106725 1407 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
Kojto 122:f9eeca106725 1408 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
Kojto 122:f9eeca106725 1409 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
Kojto 122:f9eeca106725 1410 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
Kojto 122:f9eeca106725 1411 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
Kojto 122:f9eeca106725 1412 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
Kojto 122:f9eeca106725 1413 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
Kojto 122:f9eeca106725 1414 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
Kojto 122:f9eeca106725 1415 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
Kojto 122:f9eeca106725 1416
Kojto 122:f9eeca106725 1417 /* Legacy defines */
Kojto 122:f9eeca106725 1418 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto 122:f9eeca106725 1419 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto 122:f9eeca106725 1420 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
bogdanm 92:4fc01daae5a5 1421
bogdanm 92:4fc01daae5a5 1422 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1423 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 122:f9eeca106725 1424 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1425 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1426 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1427 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1428 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1429 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 122:f9eeca106725 1430 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 1431 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 1432 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 1433 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 1434 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
Kojto 122:f9eeca106725 1435 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 122:f9eeca106725 1436 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1437 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1438 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 122:f9eeca106725 1439 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1440 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1441 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
Kojto 122:f9eeca106725 1442 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
bogdanm 92:4fc01daae5a5 1443
bogdanm 92:4fc01daae5a5 1444 /******************* Bit definition for ADC_CDR register ********************/
Kojto 122:f9eeca106725 1445 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
Kojto 122:f9eeca106725 1446 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
bogdanm 92:4fc01daae5a5 1447
bogdanm 92:4fc01daae5a5 1448 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1449 /* */
bogdanm 92:4fc01daae5a5 1450 /* Controller Area Network */
bogdanm 92:4fc01daae5a5 1451 /* */
bogdanm 92:4fc01daae5a5 1452 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1453 /*!<CAN control and status registers */
bogdanm 92:4fc01daae5a5 1454 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 1455 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
Kojto 122:f9eeca106725 1456 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 1457 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 1458 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 1459 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 1460 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 1461 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 1462 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 1463 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
Kojto 122:f9eeca106725 1464 #define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
bogdanm 92:4fc01daae5a5 1465 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 1466 #define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 1467 #define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 1468 #define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
Kojto 122:f9eeca106725 1469 #define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 1470 #define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 1471 #define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
Kojto 122:f9eeca106725 1472 #define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
Kojto 122:f9eeca106725 1473 #define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
Kojto 122:f9eeca106725 1474 #define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
bogdanm 92:4fc01daae5a5 1475
bogdanm 92:4fc01daae5a5 1476 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 1477 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 1478 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 1479 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 1480 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 1481 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 1482 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 1483 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 1484 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 1485 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 1486 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 1487 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 1488 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 1489 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 1490 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 1491 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 1492 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
Kojto 122:f9eeca106725 1493
Kojto 122:f9eeca106725 1494 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 1495 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 1496 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 1497 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 1498
Kojto 122:f9eeca106725 1499 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 1500 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 1501 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 1502 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 92:4fc01daae5a5 1503
bogdanm 92:4fc01daae5a5 1504 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 1505 #define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 1506 #define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 1507 #define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 1508 #define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
bogdanm 92:4fc01daae5a5 1509
bogdanm 92:4fc01daae5a5 1510 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 1511 #define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 1512 #define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 1513 #define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 1514 #define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
bogdanm 92:4fc01daae5a5 1515
bogdanm 92:4fc01daae5a5 1516 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 1517 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 1518 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1519 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1520 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1521 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1522 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1523 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1524 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 1525 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 1526 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 1527 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 1528 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 1529 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 1530 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
Kojto 122:f9eeca106725 1531 #define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
Kojto 122:f9eeca106725 1532 #define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
Kojto 122:f9eeca106725 1533 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
Kojto 122:f9eeca106725 1534 #define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
Kojto 122:f9eeca106725 1535 #define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
bogdanm 92:4fc01daae5a5 1536
bogdanm 92:4fc01daae5a5 1537
bogdanm 92:4fc01daae5a5 1538 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 1539 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
Kojto 122:f9eeca106725 1540 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
Kojto 122:f9eeca106725 1541 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 1542
Kojto 122:f9eeca106725 1543 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 1544 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 1545 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 1546 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 1547
Kojto 122:f9eeca106725 1548 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 1549 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
bogdanm 92:4fc01daae5a5 1550
bogdanm 92:4fc01daae5a5 1551 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 1552 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 1553 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
Kojto 122:f9eeca106725 1554 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1555 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1556 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1557 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1558 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
Kojto 122:f9eeca106725 1559 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1560 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1561 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1562 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 1563 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1564 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1565 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 1566 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
bogdanm 92:4fc01daae5a5 1567
bogdanm 92:4fc01daae5a5 1568
bogdanm 92:4fc01daae5a5 1569 /*!<Mailbox registers */
bogdanm 92:4fc01daae5a5 1570 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 1571 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1572 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1573 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1574 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1575 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1576
bogdanm 92:4fc01daae5a5 1577 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 1578 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1579 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1580 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1581
bogdanm 92:4fc01daae5a5 1582 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 1583 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1584 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1585 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1586 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1587
bogdanm 92:4fc01daae5a5 1588 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 1589 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1590 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1591 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1592 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1593
bogdanm 92:4fc01daae5a5 1594 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 1595 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1596 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1597 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1598 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1599 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1600
bogdanm 92:4fc01daae5a5 1601 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 1602 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1603 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1604 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1605
bogdanm 92:4fc01daae5a5 1606 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 1607 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1608 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1609 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1610 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1611
bogdanm 92:4fc01daae5a5 1612 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 1613 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1614 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1615 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1616 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1617
bogdanm 92:4fc01daae5a5 1618 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 1619 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1620 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1621 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1622 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 1623 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1624
bogdanm 92:4fc01daae5a5 1625 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 1626 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1627 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1628 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1629
bogdanm 92:4fc01daae5a5 1630 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 1631 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1632 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1633 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1634 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1635
bogdanm 92:4fc01daae5a5 1636 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 1637 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1638 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1639 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1640 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1641
bogdanm 92:4fc01daae5a5 1642 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 1643 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1644 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1645 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1646 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1647
bogdanm 92:4fc01daae5a5 1648 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 1649 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1650 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 1651 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1652
bogdanm 92:4fc01daae5a5 1653 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 1654 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1655 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1656 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1657 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1658
bogdanm 92:4fc01daae5a5 1659 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 1660 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1661 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1662 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1663 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1664
bogdanm 92:4fc01daae5a5 1665 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 1666 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1667 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1668 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 1669 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
bogdanm 92:4fc01daae5a5 1670
bogdanm 92:4fc01daae5a5 1671 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 1672 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1673 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 1674 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
bogdanm 92:4fc01daae5a5 1675
bogdanm 92:4fc01daae5a5 1676 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 1677 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1678 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1679 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1680 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
bogdanm 92:4fc01daae5a5 1681
bogdanm 92:4fc01daae5a5 1682 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 1683 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1684 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1685 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1686 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
bogdanm 92:4fc01daae5a5 1687
bogdanm 92:4fc01daae5a5 1688 /*!<CAN filter registers */
bogdanm 92:4fc01daae5a5 1689 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 1690 #define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
Kojto 122:f9eeca106725 1691 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
bogdanm 92:4fc01daae5a5 1692
bogdanm 92:4fc01daae5a5 1693 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 1694 #define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
Kojto 122:f9eeca106725 1695 #define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 1696 #define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 1697 #define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 1698 #define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 1699 #define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 1700 #define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 1701 #define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 1702 #define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 1703 #define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 1704 #define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 1705 #define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 1706 #define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 1707 #define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 1708 #define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
Kojto 122:f9eeca106725 1709 #define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
Kojto 122:f9eeca106725 1710 #define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
Kojto 122:f9eeca106725 1711 #define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
Kojto 122:f9eeca106725 1712 #define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
Kojto 122:f9eeca106725 1713 #define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
Kojto 122:f9eeca106725 1714 #define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
Kojto 122:f9eeca106725 1715 #define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
Kojto 122:f9eeca106725 1716 #define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
Kojto 122:f9eeca106725 1717 #define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
Kojto 122:f9eeca106725 1718 #define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
Kojto 122:f9eeca106725 1719 #define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
Kojto 122:f9eeca106725 1720 #define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
Kojto 122:f9eeca106725 1721 #define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
Kojto 122:f9eeca106725 1722 #define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
bogdanm 92:4fc01daae5a5 1723
bogdanm 92:4fc01daae5a5 1724 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 1725 #define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 1726 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 1727 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 1728 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 1729 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 1730 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 1731 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 1732 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 1733 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 1734 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 1735 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 1736 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 1737 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 1738 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 1739 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
Kojto 122:f9eeca106725 1740 #define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
Kojto 122:f9eeca106725 1741 #define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
Kojto 122:f9eeca106725 1742 #define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
Kojto 122:f9eeca106725 1743 #define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
Kojto 122:f9eeca106725 1744 #define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
Kojto 122:f9eeca106725 1745 #define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
Kojto 122:f9eeca106725 1746 #define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
Kojto 122:f9eeca106725 1747 #define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
Kojto 122:f9eeca106725 1748 #define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
Kojto 122:f9eeca106725 1749 #define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
Kojto 122:f9eeca106725 1750 #define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
Kojto 122:f9eeca106725 1751 #define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
Kojto 122:f9eeca106725 1752 #define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
Kojto 122:f9eeca106725 1753 #define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
bogdanm 92:4fc01daae5a5 1754
bogdanm 92:4fc01daae5a5 1755 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 1756 #define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 1757 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
Kojto 122:f9eeca106725 1758 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
Kojto 122:f9eeca106725 1759 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
Kojto 122:f9eeca106725 1760 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
Kojto 122:f9eeca106725 1761 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
Kojto 122:f9eeca106725 1762 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
Kojto 122:f9eeca106725 1763 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
Kojto 122:f9eeca106725 1764 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
Kojto 122:f9eeca106725 1765 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
Kojto 122:f9eeca106725 1766 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
Kojto 122:f9eeca106725 1767 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
Kojto 122:f9eeca106725 1768 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
Kojto 122:f9eeca106725 1769 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
Kojto 122:f9eeca106725 1770 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
Kojto 122:f9eeca106725 1771 #define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
Kojto 122:f9eeca106725 1772 #define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
Kojto 122:f9eeca106725 1773 #define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
Kojto 122:f9eeca106725 1774 #define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
Kojto 122:f9eeca106725 1775 #define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
Kojto 122:f9eeca106725 1776 #define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
Kojto 122:f9eeca106725 1777 #define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
Kojto 122:f9eeca106725 1778 #define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
Kojto 122:f9eeca106725 1779 #define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
Kojto 122:f9eeca106725 1780 #define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
Kojto 122:f9eeca106725 1781 #define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
Kojto 122:f9eeca106725 1782 #define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
Kojto 122:f9eeca106725 1783 #define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
Kojto 122:f9eeca106725 1784 #define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
bogdanm 92:4fc01daae5a5 1785
bogdanm 92:4fc01daae5a5 1786 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 1787 #define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
Kojto 122:f9eeca106725 1788 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
Kojto 122:f9eeca106725 1789 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
Kojto 122:f9eeca106725 1790 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
Kojto 122:f9eeca106725 1791 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
Kojto 122:f9eeca106725 1792 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
Kojto 122:f9eeca106725 1793 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
Kojto 122:f9eeca106725 1794 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
Kojto 122:f9eeca106725 1795 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
Kojto 122:f9eeca106725 1796 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
Kojto 122:f9eeca106725 1797 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
Kojto 122:f9eeca106725 1798 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
Kojto 122:f9eeca106725 1799 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
Kojto 122:f9eeca106725 1800 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
Kojto 122:f9eeca106725 1801 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
Kojto 122:f9eeca106725 1802 #define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
Kojto 122:f9eeca106725 1803 #define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
Kojto 122:f9eeca106725 1804 #define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
Kojto 122:f9eeca106725 1805 #define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
Kojto 122:f9eeca106725 1806 #define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
Kojto 122:f9eeca106725 1807 #define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
Kojto 122:f9eeca106725 1808 #define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
Kojto 122:f9eeca106725 1809 #define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
Kojto 122:f9eeca106725 1810 #define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
Kojto 122:f9eeca106725 1811 #define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
Kojto 122:f9eeca106725 1812 #define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
Kojto 122:f9eeca106725 1813 #define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
Kojto 122:f9eeca106725 1814 #define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
Kojto 122:f9eeca106725 1815 #define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
bogdanm 92:4fc01daae5a5 1816
bogdanm 92:4fc01daae5a5 1817 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 1818 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1819 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1820 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1821 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1822 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1823 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1824 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1825 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1826 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1827 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1828 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1829 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1830 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1831 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1832 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1833 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1834 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1835 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1836 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1837 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1838 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1839 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1840 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1841 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1842 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1843 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1844 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1845 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1846 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1847 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1848 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1849 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1850
bogdanm 92:4fc01daae5a5 1851 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 1852 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1853 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1854 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1855 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1856 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1857 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1858 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1859 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1860 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1861 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1862 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1863 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1864 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1865 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1866 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1867 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1868 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1869 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1870 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1871 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1872 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1873 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1874 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1875 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1876 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1877 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1878 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1879 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1880 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1881 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1882 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1883 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1884
bogdanm 92:4fc01daae5a5 1885 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 1886 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1887 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1888 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1889 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1890 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1891 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1892 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1893 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1894 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1895 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1896 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1897 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1898 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1899 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1900 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1901 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1902 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1903 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1904 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1905 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1906 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1907 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1908 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1909 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1910 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1911 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1912 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1913 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1914 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1915 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1916 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1917 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1918
bogdanm 92:4fc01daae5a5 1919 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 1920 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1921 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1922 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1923 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1924 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1925 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1926 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1927 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1928 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1929 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1930 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1931 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1932 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1933 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1934 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1935 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1936 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1937 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1938 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1939 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1940 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1941 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1942 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1943 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1944 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1945 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1946 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1947 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1948 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1949 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1950 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1951 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1952
bogdanm 92:4fc01daae5a5 1953 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 1954 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1955 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1956 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1957 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1958 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1959 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1960 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1961 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1962 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1963 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1964 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1965 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1966 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1967 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1968 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1969 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1970 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1971 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1972 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1973 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1974 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1975 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1976 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1977 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1978 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1979 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1980 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1981 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1982 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1983 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1984 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1985 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 1986
bogdanm 92:4fc01daae5a5 1987 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 1988 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1989 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1990 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1991 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1992 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1993 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1994 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1995 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1996 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1997 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1998 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1999 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2000 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2001 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2002 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2003 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2004 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2005 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2006 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2007 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2008 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2009 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2010 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2011 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2012 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2013 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2014 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2015 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2016 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2017 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2018 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2019 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2020
bogdanm 92:4fc01daae5a5 2021 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 2022 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2023 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2024 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2025 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2026 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2027 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2028 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2029 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2030 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2031 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2032 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2033 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2034 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2035 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2036 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2037 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2038 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2039 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2040 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2041 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2042 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2043 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2044 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2045 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2046 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2047 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2048 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2049 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2050 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2051 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2052 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2053 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2054
bogdanm 92:4fc01daae5a5 2055 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 2056 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2057 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2058 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2059 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2060 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2061 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2062 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2063 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2064 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2065 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2066 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2067 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2068 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2069 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2070 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2071 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2072 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2073 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2074 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2075 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2076 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2077 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2078 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2079 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2080 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2081 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2082 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2083 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2084 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2085 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2086 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2087 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2088
bogdanm 92:4fc01daae5a5 2089 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 2090 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2091 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2092 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2093 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2094 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2095 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2096 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2097 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2098 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2099 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2100 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2101 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2102 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2103 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2104 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2105 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2106 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2107 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2108 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2109 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2110 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2111 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2112 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2113 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2114 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2115 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2116 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2117 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2118 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2119 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2120 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2121 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2122
bogdanm 92:4fc01daae5a5 2123 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 2124 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2125 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2126 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2127 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2128 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2129 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2130 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2131 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2132 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2133 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2134 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2135 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2136 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2137 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2138 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2139 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2140 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2141 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2142 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2143 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2144 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2145 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2146 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2147 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2148 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2149 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2150 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2151 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2152 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2153 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2154 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2155 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2156
bogdanm 92:4fc01daae5a5 2157 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 2158 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2159 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2160 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2161 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2162 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2163 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2164 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2165 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2166 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2167 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2168 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2169 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2170 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2171 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2172 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2173 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2174 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2175 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2176 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2177 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2178 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2179 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2180 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2181 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2182 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2183 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2184 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2185 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2186 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2187 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2188 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2189 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2190
bogdanm 92:4fc01daae5a5 2191 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 2192 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2193 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2194 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2195 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2196 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2197 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2198 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2199 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2200 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2201 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2202 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2203 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2204 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2205 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2206 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2207 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2208 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2209 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2210 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2211 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2212 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2213 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2214 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2215 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2216 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2217 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2218 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2219 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2220 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2221 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2222 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2223 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2224
bogdanm 92:4fc01daae5a5 2225 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 2226 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2227 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2228 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2229 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2230 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2231 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2232 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2233 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2234 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2235 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2236 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2237 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2238 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2239 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2240 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2241 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2242 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2243 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2244 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2245 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2246 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2247 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2248 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2249 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2250 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2251 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2252 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2253 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2254 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2255 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2256 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2257 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2258
bogdanm 92:4fc01daae5a5 2259 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 2260 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2261 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2262 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2263 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2264 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2265 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2266 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2267 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2268 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2269 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2270 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2271 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2272 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2273 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2274 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2275 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2276 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2277 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2278 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2279 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2280 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2281 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2282 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2283 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2284 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2285 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2286 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2287 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2288 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2289 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2290 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2291 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2292
bogdanm 92:4fc01daae5a5 2293 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 2294 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2295 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2296 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2297 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2298 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2299 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2300 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2301 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2302 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2303 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2304 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2305 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2306 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2307 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2308 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2309 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2310 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2311 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2312 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2313 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2314 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2315 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2316 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2317 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2318 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2319 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2320 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2321 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2322 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2323 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2324 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2325 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2326
bogdanm 92:4fc01daae5a5 2327 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 2328 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2329 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2330 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2331 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2332 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2333 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2334 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2335 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2336 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2337 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2338 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2339 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2340 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2341 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2342 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2343 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2344 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2345 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2346 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2347 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2348 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2349 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2350 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2351 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2352 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2353 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2354 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2355 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2356 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2357 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2358 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2359 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2360
bogdanm 92:4fc01daae5a5 2361 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 2362 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2363 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2364 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2365 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2366 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2367 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2368 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2369 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2370 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2371 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2372 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2373 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2374 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2375 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2376 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2377 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2378 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2379 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2380 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2381 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2382 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2383 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2384 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2385 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2386 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2387 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2388 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2389 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2390 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2391 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2392 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2393 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2394
bogdanm 92:4fc01daae5a5 2395 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 2396 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2397 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2398 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2399 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2400 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2401 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2402 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2403 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2404 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2405 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2406 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2407 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2408 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2409 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2410 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2411 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2412 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2413 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2414 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2415 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2416 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2417 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2418 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2419 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2420 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2421 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2422 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2423 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2424 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2425 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2426 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2427 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2428
bogdanm 92:4fc01daae5a5 2429 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 2430 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2431 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2432 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2433 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2434 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2435 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2436 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2437 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2438 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2439 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2440 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2441 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2442 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2443 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2444 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2445 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2446 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2447 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2448 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2449 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2450 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2451 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2452 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2453 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2454 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2455 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2456 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2457 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2458 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2459 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2460 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2461 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2462
bogdanm 92:4fc01daae5a5 2463 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 2464 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2465 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2466 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2467 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2468 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2469 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2470 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2471 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2472 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2473 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2474 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2475 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2476 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2477 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2478 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2479 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2480 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2481 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2482 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2483 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2484 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2485 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2486 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2487 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2488 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2489 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2490 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2491 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2492 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2493 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2494 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2495 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2496
bogdanm 92:4fc01daae5a5 2497 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 2498 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2499 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2500 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2501 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2502 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2503 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2504 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2505 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2506 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2507 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2508 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2509 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2510 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2511 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2512 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2513 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2514 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2515 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2516 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2517 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2518 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2519 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2520 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2521 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2522 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2523 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2524 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2525 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2526 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2527 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2528 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2529 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2530
bogdanm 92:4fc01daae5a5 2531 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 2532 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2533 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2534 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2535 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2536 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2537 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2538 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2539 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2540 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2541 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2542 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2543 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2544 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2545 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2546 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2547 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2548 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2549 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2550 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2551 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2552 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2553 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2554 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2555 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2556 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2557 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2558 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2559 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2560 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2561 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2562 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2563 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2564
bogdanm 92:4fc01daae5a5 2565 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 2566 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2567 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2568 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2569 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2570 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2571 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2572 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2573 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2574 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2575 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2576 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2577 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2578 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2579 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2580 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2581 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2582 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2583 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2584 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2585 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2586 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2587 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2588 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2589 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2590 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2591 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2592 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2593 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2594 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2595 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2596 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2597 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2598
bogdanm 92:4fc01daae5a5 2599 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 2600 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2601 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2602 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2603 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2604 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2605 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2606 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2607 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2608 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2609 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2610 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2611 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2612 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2613 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2614 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2615 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2616 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2617 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2618 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2619 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2620 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2621 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2622 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2623 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2624 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2625 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2626 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2627 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2628 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2629 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2630 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2631 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2632
bogdanm 92:4fc01daae5a5 2633 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 2634 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2635 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2636 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2637 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2638 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2639 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2640 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2641 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2642 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2643 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2644 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2645 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2646 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2647 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2648 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2649 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2650 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2651 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2652 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2653 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2654 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2655 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2656 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2657 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2658 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2659 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2660 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2661 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2662 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2663 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2664 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2665 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2666
bogdanm 92:4fc01daae5a5 2667 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 2668 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2669 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2670 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2671 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2672 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2673 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2674 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2675 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2676 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2677 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2678 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2679 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2680 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2681 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2682 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2683 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2684 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2685 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2686 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2687 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2688 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2689 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2690 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2691 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2692 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2693 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2694 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2695 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2696 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2697 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2698 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2699 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2700
bogdanm 92:4fc01daae5a5 2701 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 2702 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2703 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2704 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2705 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2706 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2707 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2708 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2709 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2710 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2711 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2712 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2713 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2714 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2715 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2716 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2717 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2718 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2719 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2720 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2721 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2722 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2723 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2724 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2725 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2726 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2727 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2728 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2729 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2730 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2731 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2732 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2733 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2734
bogdanm 92:4fc01daae5a5 2735 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 2736 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2737 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2738 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2739 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2740 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2741 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2742 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2743 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2744 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2745 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2746 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2747 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2748 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2749 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2750 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2751 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2752 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2753 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2754 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2755 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2756 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2757 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2758 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2759 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2760 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2761 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2762 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2763 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2764 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2765 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2766 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2767 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
bogdanm 92:4fc01daae5a5 2768
bogdanm 92:4fc01daae5a5 2769 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2770 /* */
bogdanm 92:4fc01daae5a5 2771 /* CRC calculation unit */
bogdanm 92:4fc01daae5a5 2772 /* */
bogdanm 92:4fc01daae5a5 2773 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2774 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 2775 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
bogdanm 92:4fc01daae5a5 2776
bogdanm 92:4fc01daae5a5 2777
bogdanm 92:4fc01daae5a5 2778 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 2779 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
bogdanm 92:4fc01daae5a5 2780
bogdanm 92:4fc01daae5a5 2781
bogdanm 92:4fc01daae5a5 2782 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 2783 #define CRC_CR_RESET 0x01U /*!< RESET bit */
bogdanm 92:4fc01daae5a5 2784
bogdanm 92:4fc01daae5a5 2785
bogdanm 92:4fc01daae5a5 2786 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2787 /* */
bogdanm 92:4fc01daae5a5 2788 /* Digital to Analog Converter */
bogdanm 92:4fc01daae5a5 2789 /* */
bogdanm 92:4fc01daae5a5 2790 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2791 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 2792 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
Kojto 122:f9eeca106725 2793 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 2794 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 2795
Kojto 122:f9eeca106725 2796 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 2797 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 2798 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 2799 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 2800
Kojto 122:f9eeca106725 2801 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 2802 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 2803 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 2804
Kojto 122:f9eeca106725 2805 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 2806 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 2807 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 2808 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 2809 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 2810
Kojto 122:f9eeca106725 2811 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
Kojto 122:f9eeca106725 2812 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
Kojto 122:f9eeca106725 2813 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
Kojto 122:f9eeca106725 2814 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 2815 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 2816
Kojto 122:f9eeca106725 2817 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 2818 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2819 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2820 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2821
Kojto 122:f9eeca106725 2822 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 2823 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2824 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2825
Kojto 122:f9eeca106725 2826 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 2827 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2828 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2829 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2830 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 2831
Kojto 122:f9eeca106725 2832 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 2833 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
bogdanm 92:4fc01daae5a5 2834
bogdanm 92:4fc01daae5a5 2835 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 2836 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
Kojto 122:f9eeca106725 2837 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
bogdanm 92:4fc01daae5a5 2838
bogdanm 92:4fc01daae5a5 2839 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 2840 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2841
bogdanm 92:4fc01daae5a5 2842 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 2843 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2844
bogdanm 92:4fc01daae5a5 2845 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 2846 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2847
bogdanm 92:4fc01daae5a5 2848 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 2849 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2850
bogdanm 92:4fc01daae5a5 2851 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 2852 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2853
bogdanm 92:4fc01daae5a5 2854 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 2855 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2856
bogdanm 92:4fc01daae5a5 2857 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 2858 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 2859 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2860
bogdanm 92:4fc01daae5a5 2861 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 2862 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 2863 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
bogdanm 92:4fc01daae5a5 2864
bogdanm 92:4fc01daae5a5 2865 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 2866 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 2867 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
bogdanm 92:4fc01daae5a5 2868
bogdanm 92:4fc01daae5a5 2869 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 2870 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
bogdanm 92:4fc01daae5a5 2871
bogdanm 92:4fc01daae5a5 2872 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 2873 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
bogdanm 92:4fc01daae5a5 2874
bogdanm 92:4fc01daae5a5 2875 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 2876 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 2877 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
bogdanm 92:4fc01daae5a5 2878
bogdanm 92:4fc01daae5a5 2879 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2880 /* */
bogdanm 92:4fc01daae5a5 2881 /* Debug MCU */
bogdanm 92:4fc01daae5a5 2882 /* */
bogdanm 92:4fc01daae5a5 2883 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2884
bogdanm 92:4fc01daae5a5 2885 /******************************************************************************/
bogdanm 92:4fc01daae5a5 2886 /* */
bogdanm 92:4fc01daae5a5 2887 /* DMA Controller */
bogdanm 92:4fc01daae5a5 2888 /* */
bogdanm 92:4fc01daae5a5 2889 /******************************************************************************/
Kojto 122:f9eeca106725 2890 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 122:f9eeca106725 2891 #define DMA_SxCR_CHSEL 0x0E000000U
Kojto 122:f9eeca106725 2892 #define DMA_SxCR_CHSEL_0 0x02000000U
Kojto 122:f9eeca106725 2893 #define DMA_SxCR_CHSEL_1 0x04000000U
Kojto 122:f9eeca106725 2894 #define DMA_SxCR_CHSEL_2 0x08000000U
Kojto 122:f9eeca106725 2895 #define DMA_SxCR_MBURST 0x01800000U
Kojto 122:f9eeca106725 2896 #define DMA_SxCR_MBURST_0 0x00800000U
Kojto 122:f9eeca106725 2897 #define DMA_SxCR_MBURST_1 0x01000000U
Kojto 122:f9eeca106725 2898 #define DMA_SxCR_PBURST 0x00600000U
Kojto 122:f9eeca106725 2899 #define DMA_SxCR_PBURST_0 0x00200000U
Kojto 122:f9eeca106725 2900 #define DMA_SxCR_PBURST_1 0x00400000U
Kojto 122:f9eeca106725 2901 #define DMA_SxCR_CT 0x00080000U
Kojto 122:f9eeca106725 2902 #define DMA_SxCR_DBM 0x00040000U
Kojto 122:f9eeca106725 2903 #define DMA_SxCR_PL 0x00030000U
Kojto 122:f9eeca106725 2904 #define DMA_SxCR_PL_0 0x00010000U
Kojto 122:f9eeca106725 2905 #define DMA_SxCR_PL_1 0x00020000U
Kojto 122:f9eeca106725 2906 #define DMA_SxCR_PINCOS 0x00008000U
Kojto 122:f9eeca106725 2907 #define DMA_SxCR_MSIZE 0x00006000U
Kojto 122:f9eeca106725 2908 #define DMA_SxCR_MSIZE_0 0x00002000U
Kojto 122:f9eeca106725 2909 #define DMA_SxCR_MSIZE_1 0x00004000U
Kojto 122:f9eeca106725 2910 #define DMA_SxCR_PSIZE 0x00001800U
Kojto 122:f9eeca106725 2911 #define DMA_SxCR_PSIZE_0 0x00000800U
Kojto 122:f9eeca106725 2912 #define DMA_SxCR_PSIZE_1 0x00001000U
Kojto 122:f9eeca106725 2913 #define DMA_SxCR_MINC 0x00000400U
Kojto 122:f9eeca106725 2914 #define DMA_SxCR_PINC 0x00000200U
Kojto 122:f9eeca106725 2915 #define DMA_SxCR_CIRC 0x00000100U
Kojto 122:f9eeca106725 2916 #define DMA_SxCR_DIR 0x000000C0U
Kojto 122:f9eeca106725 2917 #define DMA_SxCR_DIR_0 0x00000040U
Kojto 122:f9eeca106725 2918 #define DMA_SxCR_DIR_1 0x00000080U
Kojto 122:f9eeca106725 2919 #define DMA_SxCR_PFCTRL 0x00000020U
Kojto 122:f9eeca106725 2920 #define DMA_SxCR_TCIE 0x00000010U
Kojto 122:f9eeca106725 2921 #define DMA_SxCR_HTIE 0x00000008U
Kojto 122:f9eeca106725 2922 #define DMA_SxCR_TEIE 0x00000004U
Kojto 122:f9eeca106725 2923 #define DMA_SxCR_DMEIE 0x00000002U
Kojto 122:f9eeca106725 2924 #define DMA_SxCR_EN 0x00000001U
Kojto 122:f9eeca106725 2925
Kojto 122:f9eeca106725 2926 /* Legacy defines */
Kojto 122:f9eeca106725 2927 #define DMA_SxCR_ACK 0x00100000U
bogdanm 92:4fc01daae5a5 2928
bogdanm 92:4fc01daae5a5 2929 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 122:f9eeca106725 2930 #define DMA_SxNDT 0x0000FFFFU
Kojto 122:f9eeca106725 2931 #define DMA_SxNDT_0 0x00000001U
Kojto 122:f9eeca106725 2932 #define DMA_SxNDT_1 0x00000002U
Kojto 122:f9eeca106725 2933 #define DMA_SxNDT_2 0x00000004U
Kojto 122:f9eeca106725 2934 #define DMA_SxNDT_3 0x00000008U
Kojto 122:f9eeca106725 2935 #define DMA_SxNDT_4 0x00000010U
Kojto 122:f9eeca106725 2936 #define DMA_SxNDT_5 0x00000020U
Kojto 122:f9eeca106725 2937 #define DMA_SxNDT_6 0x00000040U
Kojto 122:f9eeca106725 2938 #define DMA_SxNDT_7 0x00000080U
Kojto 122:f9eeca106725 2939 #define DMA_SxNDT_8 0x00000100U
Kojto 122:f9eeca106725 2940 #define DMA_SxNDT_9 0x00000200U
Kojto 122:f9eeca106725 2941 #define DMA_SxNDT_10 0x00000400U
Kojto 122:f9eeca106725 2942 #define DMA_SxNDT_11 0x00000800U
Kojto 122:f9eeca106725 2943 #define DMA_SxNDT_12 0x00001000U
Kojto 122:f9eeca106725 2944 #define DMA_SxNDT_13 0x00002000U
Kojto 122:f9eeca106725 2945 #define DMA_SxNDT_14 0x00004000U
Kojto 122:f9eeca106725 2946 #define DMA_SxNDT_15 0x00008000U
bogdanm 92:4fc01daae5a5 2947
bogdanm 92:4fc01daae5a5 2948 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 122:f9eeca106725 2949 #define DMA_SxFCR_FEIE 0x00000080U
Kojto 122:f9eeca106725 2950 #define DMA_SxFCR_FS 0x00000038U
Kojto 122:f9eeca106725 2951 #define DMA_SxFCR_FS_0 0x00000008U
Kojto 122:f9eeca106725 2952 #define DMA_SxFCR_FS_1 0x00000010U
Kojto 122:f9eeca106725 2953 #define DMA_SxFCR_FS_2 0x00000020U
Kojto 122:f9eeca106725 2954 #define DMA_SxFCR_DMDIS 0x00000004U
Kojto 122:f9eeca106725 2955 #define DMA_SxFCR_FTH 0x00000003U
Kojto 122:f9eeca106725 2956 #define DMA_SxFCR_FTH_0 0x00000001U
Kojto 122:f9eeca106725 2957 #define DMA_SxFCR_FTH_1 0x00000002U
bogdanm 92:4fc01daae5a5 2958
bogdanm 92:4fc01daae5a5 2959 /******************** Bits definition for DMA_LISR register *****************/
Kojto 122:f9eeca106725 2960 #define DMA_LISR_TCIF3 0x08000000U
Kojto 122:f9eeca106725 2961 #define DMA_LISR_HTIF3 0x04000000U
Kojto 122:f9eeca106725 2962 #define DMA_LISR_TEIF3 0x02000000U
Kojto 122:f9eeca106725 2963 #define DMA_LISR_DMEIF3 0x01000000U
Kojto 122:f9eeca106725 2964 #define DMA_LISR_FEIF3 0x00400000U
Kojto 122:f9eeca106725 2965 #define DMA_LISR_TCIF2 0x00200000U
Kojto 122:f9eeca106725 2966 #define DMA_LISR_HTIF2 0x00100000U
Kojto 122:f9eeca106725 2967 #define DMA_LISR_TEIF2 0x00080000U
Kojto 122:f9eeca106725 2968 #define DMA_LISR_DMEIF2 0x00040000U
Kojto 122:f9eeca106725 2969 #define DMA_LISR_FEIF2 0x00010000U
Kojto 122:f9eeca106725 2970 #define DMA_LISR_TCIF1 0x00000800U
Kojto 122:f9eeca106725 2971 #define DMA_LISR_HTIF1 0x00000400U
Kojto 122:f9eeca106725 2972 #define DMA_LISR_TEIF1 0x00000200U
Kojto 122:f9eeca106725 2973 #define DMA_LISR_DMEIF1 0x00000100U
Kojto 122:f9eeca106725 2974 #define DMA_LISR_FEIF1 0x00000040U
Kojto 122:f9eeca106725 2975 #define DMA_LISR_TCIF0 0x00000020U
Kojto 122:f9eeca106725 2976 #define DMA_LISR_HTIF0 0x00000010U
Kojto 122:f9eeca106725 2977 #define DMA_LISR_TEIF0 0x00000008U
Kojto 122:f9eeca106725 2978 #define DMA_LISR_DMEIF0 0x00000004U
Kojto 122:f9eeca106725 2979 #define DMA_LISR_FEIF0 0x00000001U
bogdanm 92:4fc01daae5a5 2980
bogdanm 92:4fc01daae5a5 2981 /******************** Bits definition for DMA_HISR register *****************/
Kojto 122:f9eeca106725 2982 #define DMA_HISR_TCIF7 0x08000000U
Kojto 122:f9eeca106725 2983 #define DMA_HISR_HTIF7 0x04000000U
Kojto 122:f9eeca106725 2984 #define DMA_HISR_TEIF7 0x02000000U
Kojto 122:f9eeca106725 2985 #define DMA_HISR_DMEIF7 0x01000000U
Kojto 122:f9eeca106725 2986 #define DMA_HISR_FEIF7 0x00400000U
Kojto 122:f9eeca106725 2987 #define DMA_HISR_TCIF6 0x00200000U
Kojto 122:f9eeca106725 2988 #define DMA_HISR_HTIF6 0x00100000U
Kojto 122:f9eeca106725 2989 #define DMA_HISR_TEIF6 0x00080000U
Kojto 122:f9eeca106725 2990 #define DMA_HISR_DMEIF6 0x00040000U
Kojto 122:f9eeca106725 2991 #define DMA_HISR_FEIF6 0x00010000U
Kojto 122:f9eeca106725 2992 #define DMA_HISR_TCIF5 0x00000800U
Kojto 122:f9eeca106725 2993 #define DMA_HISR_HTIF5 0x00000400U
Kojto 122:f9eeca106725 2994 #define DMA_HISR_TEIF5 0x00000200U
Kojto 122:f9eeca106725 2995 #define DMA_HISR_DMEIF5 0x00000100U
Kojto 122:f9eeca106725 2996 #define DMA_HISR_FEIF5 0x00000040U
Kojto 122:f9eeca106725 2997 #define DMA_HISR_TCIF4 0x00000020U
Kojto 122:f9eeca106725 2998 #define DMA_HISR_HTIF4 0x00000010U
Kojto 122:f9eeca106725 2999 #define DMA_HISR_TEIF4 0x00000008U
Kojto 122:f9eeca106725 3000 #define DMA_HISR_DMEIF4 0x00000004U
Kojto 122:f9eeca106725 3001 #define DMA_HISR_FEIF4 0x00000001U
bogdanm 92:4fc01daae5a5 3002
bogdanm 92:4fc01daae5a5 3003 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 122:f9eeca106725 3004 #define DMA_LIFCR_CTCIF3 0x08000000U
Kojto 122:f9eeca106725 3005 #define DMA_LIFCR_CHTIF3 0x04000000U
Kojto 122:f9eeca106725 3006 #define DMA_LIFCR_CTEIF3 0x02000000U
Kojto 122:f9eeca106725 3007 #define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto 122:f9eeca106725 3008 #define DMA_LIFCR_CFEIF3 0x00400000U
Kojto 122:f9eeca106725 3009 #define DMA_LIFCR_CTCIF2 0x00200000U
Kojto 122:f9eeca106725 3010 #define DMA_LIFCR_CHTIF2 0x00100000U
Kojto 122:f9eeca106725 3011 #define DMA_LIFCR_CTEIF2 0x00080000U
Kojto 122:f9eeca106725 3012 #define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto 122:f9eeca106725 3013 #define DMA_LIFCR_CFEIF2 0x00010000U
Kojto 122:f9eeca106725 3014 #define DMA_LIFCR_CTCIF1 0x00000800U
Kojto 122:f9eeca106725 3015 #define DMA_LIFCR_CHTIF1 0x00000400U
Kojto 122:f9eeca106725 3016 #define DMA_LIFCR_CTEIF1 0x00000200U
Kojto 122:f9eeca106725 3017 #define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto 122:f9eeca106725 3018 #define DMA_LIFCR_CFEIF1 0x00000040U
Kojto 122:f9eeca106725 3019 #define DMA_LIFCR_CTCIF0 0x00000020U
Kojto 122:f9eeca106725 3020 #define DMA_LIFCR_CHTIF0 0x00000010U
Kojto 122:f9eeca106725 3021 #define DMA_LIFCR_CTEIF0 0x00000008U
Kojto 122:f9eeca106725 3022 #define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto 122:f9eeca106725 3023 #define DMA_LIFCR_CFEIF0 0x00000001U
bogdanm 92:4fc01daae5a5 3024
bogdanm 92:4fc01daae5a5 3025 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 122:f9eeca106725 3026 #define DMA_HIFCR_CTCIF7 0x08000000U
Kojto 122:f9eeca106725 3027 #define DMA_HIFCR_CHTIF7 0x04000000U
Kojto 122:f9eeca106725 3028 #define DMA_HIFCR_CTEIF7 0x02000000U
Kojto 122:f9eeca106725 3029 #define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto 122:f9eeca106725 3030 #define DMA_HIFCR_CFEIF7 0x00400000U
Kojto 122:f9eeca106725 3031 #define DMA_HIFCR_CTCIF6 0x00200000U
Kojto 122:f9eeca106725 3032 #define DMA_HIFCR_CHTIF6 0x00100000U
Kojto 122:f9eeca106725 3033 #define DMA_HIFCR_CTEIF6 0x00080000U
Kojto 122:f9eeca106725 3034 #define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto 122:f9eeca106725 3035 #define DMA_HIFCR_CFEIF6 0x00010000U
Kojto 122:f9eeca106725 3036 #define DMA_HIFCR_CTCIF5 0x00000800U
Kojto 122:f9eeca106725 3037 #define DMA_HIFCR_CHTIF5 0x00000400U
Kojto 122:f9eeca106725 3038 #define DMA_HIFCR_CTEIF5 0x00000200U
Kojto 122:f9eeca106725 3039 #define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto 122:f9eeca106725 3040 #define DMA_HIFCR_CFEIF5 0x00000040U
Kojto 122:f9eeca106725 3041 #define DMA_HIFCR_CTCIF4 0x00000020U
Kojto 122:f9eeca106725 3042 #define DMA_HIFCR_CHTIF4 0x00000010U
Kojto 122:f9eeca106725 3043 #define DMA_HIFCR_CTEIF4 0x00000008U
Kojto 122:f9eeca106725 3044 #define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto 122:f9eeca106725 3045 #define DMA_HIFCR_CFEIF4 0x00000001U
bogdanm 92:4fc01daae5a5 3046
bogdanm 92:4fc01daae5a5 3047
bogdanm 92:4fc01daae5a5 3048 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3049 /* */
bogdanm 92:4fc01daae5a5 3050 /* External Interrupt/Event Controller */
bogdanm 92:4fc01daae5a5 3051 /* */
bogdanm 92:4fc01daae5a5 3052 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3053 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 3054 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 3055 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 3056 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 3057 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 3058 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 3059 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 3060 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 3061 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 3062 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 3063 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 3064 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 3065 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 3066 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 3067 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 3068 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 3069 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 3070 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 3071 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 3072 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 3073 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 3074 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 3075 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 3076 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
bogdanm 92:4fc01daae5a5 3077
bogdanm 92:4fc01daae5a5 3078 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 3079 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 3080 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 3081 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 3082 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 3083 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 3084 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 3085 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 3086 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 3087 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 3088 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 3089 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 3090 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 3091 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 3092 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 3093 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 3094 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 3095 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 3096 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 3097 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 3098 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 3099 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 3100 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 3101 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
bogdanm 92:4fc01daae5a5 3102
bogdanm 92:4fc01daae5a5 3103 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 3104 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 3105 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 3106 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 3107 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 3108 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 3109 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 3110 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 3111 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 3112 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 3113 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 3114 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 3115 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 3116 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 3117 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 3118 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 3119 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 3120 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 3121 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 3122 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 3123 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 3124 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 3125 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 3126 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
bogdanm 92:4fc01daae5a5 3127
bogdanm 92:4fc01daae5a5 3128 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 3129 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 3130 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 3131 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 3132 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 3133 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 3134 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 3135 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 3136 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 3137 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 3138 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 3139 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 3140 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 3141 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 3142 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 3143 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 3144 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 3145 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 3146 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 3147 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 3148 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 3149 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 3150 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 3151 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
bogdanm 92:4fc01daae5a5 3152
bogdanm 92:4fc01daae5a5 3153 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 3154 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 3155 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 3156 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 3157 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 3158 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 3159 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 3160 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 3161 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 3162 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 3163 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 3164 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 3165 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 3166 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 3167 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 3168 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 3169 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 3170 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 3171 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 3172 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 3173 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 3174 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 3175 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 3176 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
bogdanm 92:4fc01daae5a5 3177
bogdanm 92:4fc01daae5a5 3178 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 3179 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 3180 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 3181 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 3182 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 3183 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 3184 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 3185 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 3186 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 3187 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 3188 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 3189 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 3190 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 3191 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 3192 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 3193 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 3194 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 3195 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 3196 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 3197 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 3198 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 3199 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 3200 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 3201 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
bogdanm 92:4fc01daae5a5 3202
bogdanm 92:4fc01daae5a5 3203 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3204 /* */
bogdanm 92:4fc01daae5a5 3205 /* FLASH */
bogdanm 92:4fc01daae5a5 3206 /* */
bogdanm 92:4fc01daae5a5 3207 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3208 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 122:f9eeca106725 3209 #define FLASH_ACR_LATENCY 0x0000000FU
Kojto 122:f9eeca106725 3210 #define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto 122:f9eeca106725 3211 #define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto 122:f9eeca106725 3212 #define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto 122:f9eeca106725 3213 #define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto 122:f9eeca106725 3214 #define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto 122:f9eeca106725 3215 #define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto 122:f9eeca106725 3216 #define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto 122:f9eeca106725 3217 #define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto 122:f9eeca106725 3218
Kojto 122:f9eeca106725 3219 #define FLASH_ACR_PRFTEN 0x00000100U
Kojto 122:f9eeca106725 3220 #define FLASH_ACR_ICEN 0x00000200U
Kojto 122:f9eeca106725 3221 #define FLASH_ACR_DCEN 0x00000400U
Kojto 122:f9eeca106725 3222 #define FLASH_ACR_ICRST 0x00000800U
Kojto 122:f9eeca106725 3223 #define FLASH_ACR_DCRST 0x00001000U
Kojto 122:f9eeca106725 3224 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
Kojto 122:f9eeca106725 3225 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
bogdanm 92:4fc01daae5a5 3226
bogdanm 92:4fc01daae5a5 3227 /******************* Bits definition for FLASH_SR register ******************/
Kojto 122:f9eeca106725 3228 #define FLASH_SR_EOP 0x00000001U
Kojto 122:f9eeca106725 3229 #define FLASH_SR_SOP 0x00000002U
Kojto 122:f9eeca106725 3230 #define FLASH_SR_WRPERR 0x00000010U
Kojto 122:f9eeca106725 3231 #define FLASH_SR_PGAERR 0x00000020U
Kojto 122:f9eeca106725 3232 #define FLASH_SR_PGPERR 0x00000040U
Kojto 122:f9eeca106725 3233 #define FLASH_SR_PGSERR 0x00000080U
Kojto 122:f9eeca106725 3234 #define FLASH_SR_BSY 0x00010000U
bogdanm 92:4fc01daae5a5 3235
bogdanm 92:4fc01daae5a5 3236 /******************* Bits definition for FLASH_CR register ******************/
Kojto 122:f9eeca106725 3237 #define FLASH_CR_PG 0x00000001U
Kojto 122:f9eeca106725 3238 #define FLASH_CR_SER 0x00000002U
Kojto 122:f9eeca106725 3239 #define FLASH_CR_MER 0x00000004U
Kojto 122:f9eeca106725 3240 #define FLASH_CR_SNB 0x000000F8U
Kojto 122:f9eeca106725 3241 #define FLASH_CR_SNB_0 0x00000008U
Kojto 122:f9eeca106725 3242 #define FLASH_CR_SNB_1 0x00000010U
Kojto 122:f9eeca106725 3243 #define FLASH_CR_SNB_2 0x00000020U
Kojto 122:f9eeca106725 3244 #define FLASH_CR_SNB_3 0x00000040U
Kojto 122:f9eeca106725 3245 #define FLASH_CR_SNB_4 0x00000080U
Kojto 122:f9eeca106725 3246 #define FLASH_CR_PSIZE 0x00000300U
Kojto 122:f9eeca106725 3247 #define FLASH_CR_PSIZE_0 0x00000100U
Kojto 122:f9eeca106725 3248 #define FLASH_CR_PSIZE_1 0x00000200U
Kojto 122:f9eeca106725 3249 #define FLASH_CR_STRT 0x00010000U
Kojto 122:f9eeca106725 3250 #define FLASH_CR_EOPIE 0x01000000U
Kojto 122:f9eeca106725 3251 #define FLASH_CR_LOCK 0x80000000U
bogdanm 92:4fc01daae5a5 3252
bogdanm 92:4fc01daae5a5 3253 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 122:f9eeca106725 3254 #define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto 122:f9eeca106725 3255 #define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto 122:f9eeca106725 3256 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto 122:f9eeca106725 3257 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto 122:f9eeca106725 3258 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto 122:f9eeca106725 3259
Kojto 122:f9eeca106725 3260 #define FLASH_OPTCR_WDG_SW 0x00000020U
Kojto 122:f9eeca106725 3261 #define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto 122:f9eeca106725 3262 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto 122:f9eeca106725 3263 #define FLASH_OPTCR_RDP 0x0000FF00U
Kojto 122:f9eeca106725 3264 #define FLASH_OPTCR_RDP_0 0x00000100U
Kojto 122:f9eeca106725 3265 #define FLASH_OPTCR_RDP_1 0x00000200U
Kojto 122:f9eeca106725 3266 #define FLASH_OPTCR_RDP_2 0x00000400U
Kojto 122:f9eeca106725 3267 #define FLASH_OPTCR_RDP_3 0x00000800U
Kojto 122:f9eeca106725 3268 #define FLASH_OPTCR_RDP_4 0x00001000U
Kojto 122:f9eeca106725 3269 #define FLASH_OPTCR_RDP_5 0x00002000U
Kojto 122:f9eeca106725 3270 #define FLASH_OPTCR_RDP_6 0x00004000U
Kojto 122:f9eeca106725 3271 #define FLASH_OPTCR_RDP_7 0x00008000U
Kojto 122:f9eeca106725 3272 #define FLASH_OPTCR_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 3273 #define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 3274 #define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 3275 #define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 3276 #define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 3277 #define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 3278 #define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 3279 #define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 3280 #define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 3281 #define FLASH_OPTCR_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 3282 #define FLASH_OPTCR_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 3283 #define FLASH_OPTCR_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 3284 #define FLASH_OPTCR_nWRP_11 0x08000000U
bogdanm 92:4fc01daae5a5 3285
bogdanm 92:4fc01daae5a5 3286 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 122:f9eeca106725 3287 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 3288 #define FLASH_OPTCR1_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 3289 #define FLASH_OPTCR1_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 3290 #define FLASH_OPTCR1_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 3291 #define FLASH_OPTCR1_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 3292 #define FLASH_OPTCR1_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 3293 #define FLASH_OPTCR1_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 3294 #define FLASH_OPTCR1_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 3295 #define FLASH_OPTCR1_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 3296 #define FLASH_OPTCR1_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 3297 #define FLASH_OPTCR1_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 3298 #define FLASH_OPTCR1_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 3299 #define FLASH_OPTCR1_nWRP_11 0x08000000U
bogdanm 92:4fc01daae5a5 3300
bogdanm 92:4fc01daae5a5 3301 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3302 /* */
bogdanm 92:4fc01daae5a5 3303 /* Flexible Static Memory Controller */
bogdanm 92:4fc01daae5a5 3304 /* */
bogdanm 92:4fc01daae5a5 3305 /******************************************************************************/
bogdanm 92:4fc01daae5a5 3306 /****************** Bit definition for FSMC_BCR1 register *******************/
Kojto 122:f9eeca106725 3307 #define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3308 #define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3309
Kojto 122:f9eeca106725 3310 #define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3311 #define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3312 #define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3313
Kojto 122:f9eeca106725 3314 #define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3315 #define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3316 #define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3317
Kojto 122:f9eeca106725 3318 #define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3319 #define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3320 #define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3321 #define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 3322 #define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3323 #define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3324 #define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3325 #define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3326 #define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3327 #define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 3328 #define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3329 #define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3330 #define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3331 #define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3332
bogdanm 92:4fc01daae5a5 3333 /****************** Bit definition for FSMC_BCR2 register *******************/
Kojto 122:f9eeca106725 3334 #define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3335 #define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3336
Kojto 122:f9eeca106725 3337 #define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3338 #define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3339 #define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3340
Kojto 122:f9eeca106725 3341 #define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3342 #define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3343 #define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3344
Kojto 122:f9eeca106725 3345 #define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3346 #define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3347 #define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3348 #define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 3349 #define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3350 #define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3351 #define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3352 #define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3353 #define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3354 #define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 3355 #define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3356 #define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3357 #define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3358 #define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3359
bogdanm 92:4fc01daae5a5 3360 /****************** Bit definition for FSMC_BCR3 register *******************/
Kojto 122:f9eeca106725 3361 #define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3362 #define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3363
Kojto 122:f9eeca106725 3364 #define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3365 #define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3366 #define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3367
Kojto 122:f9eeca106725 3368 #define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3369 #define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3370 #define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3371
Kojto 122:f9eeca106725 3372 #define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3373 #define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3374 #define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3375 #define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 3376 #define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3377 #define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3378 #define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3379 #define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3380 #define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3381 #define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 3382 #define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3383 #define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3384 #define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3385 #define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3386
bogdanm 92:4fc01daae5a5 3387 /****************** Bit definition for FSMC_BCR4 register *******************/
Kojto 122:f9eeca106725 3388 #define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3389 #define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3390
Kojto 122:f9eeca106725 3391 #define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3392 #define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3393 #define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3394
Kojto 122:f9eeca106725 3395 #define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3396 #define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3397 #define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3398
Kojto 122:f9eeca106725 3399 #define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3400 #define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3401 #define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3402 #define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 3403 #define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3404 #define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3405 #define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3406 #define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3407 #define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3408 #define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 3409 #define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3410 #define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3411 #define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3412 #define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
bogdanm 92:4fc01daae5a5 3413
bogdanm 92:4fc01daae5a5 3414 /****************** Bit definition for FSMC_BTR1 register ******************/
Kojto 122:f9eeca106725 3415 #define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3416 #define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3417 #define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3418 #define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3419 #define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3420
Kojto 122:f9eeca106725 3421 #define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3422 #define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3423 #define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3424 #define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3425 #define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3426
Kojto 122:f9eeca106725 3427 #define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3428 #define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3429 #define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3430 #define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3431 #define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3432 #define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3433 #define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3434 #define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3435 #define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3436
Kojto 122:f9eeca106725 3437 #define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3438 #define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3439 #define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3440 #define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3441 #define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3442
Kojto 122:f9eeca106725 3443 #define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3444 #define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3445 #define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3446 #define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3447 #define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3448
Kojto 122:f9eeca106725 3449 #define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3450 #define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3451 #define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3452 #define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3453 #define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3454
Kojto 122:f9eeca106725 3455 #define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3456 #define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3457 #define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3458
bogdanm 92:4fc01daae5a5 3459 /****************** Bit definition for FSMC_BTR2 register *******************/
Kojto 122:f9eeca106725 3460 #define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3461 #define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3462 #define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3463 #define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3464 #define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3465
Kojto 122:f9eeca106725 3466 #define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3467 #define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3468 #define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3469 #define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3470 #define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3471
Kojto 122:f9eeca106725 3472 #define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3473 #define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3474 #define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3475 #define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3476 #define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3477 #define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3478 #define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3479 #define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3480 #define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3481
Kojto 122:f9eeca106725 3482 #define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3483 #define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3484 #define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3485 #define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3486 #define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3487
Kojto 122:f9eeca106725 3488 #define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3489 #define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3490 #define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3491 #define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3492 #define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3493
Kojto 122:f9eeca106725 3494 #define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3495 #define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3496 #define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3497 #define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3498 #define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3499
Kojto 122:f9eeca106725 3500 #define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3501 #define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3502 #define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3503
bogdanm 92:4fc01daae5a5 3504 /******************* Bit definition for FSMC_BTR3 register *******************/
Kojto 122:f9eeca106725 3505 #define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3506 #define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3507 #define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3508 #define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3509 #define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3510
Kojto 122:f9eeca106725 3511 #define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3512 #define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3513 #define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3514 #define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3515 #define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3516
Kojto 122:f9eeca106725 3517 #define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3518 #define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3519 #define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3520 #define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3521 #define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3522 #define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3523 #define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3524 #define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3525 #define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3526
Kojto 122:f9eeca106725 3527 #define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3528 #define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3529 #define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3530 #define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3531 #define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3532
Kojto 122:f9eeca106725 3533 #define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3534 #define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3535 #define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3536 #define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3537 #define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3538
Kojto 122:f9eeca106725 3539 #define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3540 #define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3541 #define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3542 #define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3543 #define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3544
Kojto 122:f9eeca106725 3545 #define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3546 #define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3547 #define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3548
bogdanm 92:4fc01daae5a5 3549 /****************** Bit definition for FSMC_BTR4 register *******************/
Kojto 122:f9eeca106725 3550 #define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3551 #define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3552 #define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3553 #define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3554 #define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3555
Kojto 122:f9eeca106725 3556 #define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3557 #define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3558 #define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3559 #define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3560 #define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3561
Kojto 122:f9eeca106725 3562 #define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3563 #define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3564 #define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3565 #define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3566 #define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3567 #define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3568 #define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3569 #define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3570 #define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3571
Kojto 122:f9eeca106725 3572 #define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3573 #define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3574 #define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3575 #define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3576 #define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3577
Kojto 122:f9eeca106725 3578 #define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3579 #define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3580 #define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3581 #define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3582 #define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3583
Kojto 122:f9eeca106725 3584 #define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3585 #define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3586 #define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3587 #define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3588 #define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3589
Kojto 122:f9eeca106725 3590 #define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3591 #define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3592 #define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3593
bogdanm 92:4fc01daae5a5 3594 /****************** Bit definition for FSMC_BWTR1 register ******************/
Kojto 122:f9eeca106725 3595 #define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3596 #define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3597 #define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3598 #define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3599 #define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3600
Kojto 122:f9eeca106725 3601 #define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3602 #define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3603 #define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3604 #define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3605 #define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3606
Kojto 122:f9eeca106725 3607 #define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3608 #define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3609 #define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3610 #define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3611 #define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3612 #define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3613 #define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3614 #define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3615 #define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3616
Kojto 122:f9eeca106725 3617 #define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3618 #define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3619 #define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3620 #define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3621 #define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3622
Kojto 122:f9eeca106725 3623 #define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3624 #define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3625 #define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3626
bogdanm 92:4fc01daae5a5 3627 /****************** Bit definition for FSMC_BWTR2 register ******************/
Kojto 122:f9eeca106725 3628 #define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3629 #define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3630 #define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3631 #define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3632 #define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3633
Kojto 122:f9eeca106725 3634 #define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3635 #define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3636 #define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3637 #define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3638 #define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3639
Kojto 122:f9eeca106725 3640 #define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3641 #define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3642 #define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3643 #define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3644 #define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3645 #define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3646 #define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3647 #define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3648 #define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3649
Kojto 122:f9eeca106725 3650 #define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3651 #define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3652 #define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3653 #define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3654 #define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3655 #define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3656 #define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3657 #define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3658
bogdanm 92:4fc01daae5a5 3659 /****************** Bit definition for FSMC_BWTR3 register ******************/
Kojto 122:f9eeca106725 3660 #define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3661 #define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3662 #define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3663 #define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3664 #define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3665
Kojto 122:f9eeca106725 3666 #define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3667 #define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3668 #define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3669 #define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3670 #define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3671
Kojto 122:f9eeca106725 3672 #define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3673 #define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3674 #define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3675 #define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3676 #define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3677 #define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3678 #define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3679 #define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3680 #define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3681
Kojto 122:f9eeca106725 3682 #define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3683 #define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3684 #define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3685 #define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3686 #define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3687
Kojto 122:f9eeca106725 3688 #define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3689 #define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3690 #define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3691
bogdanm 92:4fc01daae5a5 3692 /****************** Bit definition for FSMC_BWTR4 register ******************/
Kojto 122:f9eeca106725 3693 #define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3694 #define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3695 #define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3696 #define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3697 #define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3698
Kojto 122:f9eeca106725 3699 #define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3700 #define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3701 #define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3702 #define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3703 #define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3704
Kojto 122:f9eeca106725 3705 #define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3706 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3707 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3708 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3709 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3710 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3711 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3712 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3713 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3714
Kojto 122:f9eeca106725 3715 #define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3716 #define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3717 #define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3718 #define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3719 #define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3720 #define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3721 #define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3722 #define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 3723
bogdanm 92:4fc01daae5a5 3724 /****************** Bit definition for FSMC_PCR2 register *******************/
Kojto 122:f9eeca106725 3725 #define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
Kojto 122:f9eeca106725 3726 #define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 122:f9eeca106725 3727 #define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
Kojto 122:f9eeca106725 3728
Kojto 122:f9eeca106725 3729 #define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 122:f9eeca106725 3730 #define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3731 #define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3732
Kojto 122:f9eeca106725 3733 #define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
Kojto 122:f9eeca106725 3734
Kojto 122:f9eeca106725 3735 #define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 122:f9eeca106725 3736 #define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 3737 #define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 3738 #define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 3739 #define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3740
Kojto 122:f9eeca106725 3741 #define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 122:f9eeca106725 3742 #define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3743 #define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3744 #define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3745 #define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3746
Kojto 122:f9eeca106725 3747 #define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
Kojto 122:f9eeca106725 3748 #define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3749 #define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3750 #define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3751
bogdanm 92:4fc01daae5a5 3752 /****************** Bit definition for FSMC_PCR3 register *******************/
Kojto 122:f9eeca106725 3753 #define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
Kojto 122:f9eeca106725 3754 #define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 122:f9eeca106725 3755 #define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
Kojto 122:f9eeca106725 3756
Kojto 122:f9eeca106725 3757 #define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 122:f9eeca106725 3758 #define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3759 #define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3760
Kojto 122:f9eeca106725 3761 #define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
Kojto 122:f9eeca106725 3762
Kojto 122:f9eeca106725 3763 #define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 122:f9eeca106725 3764 #define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 3765 #define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 3766 #define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 3767 #define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3768
Kojto 122:f9eeca106725 3769 #define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 122:f9eeca106725 3770 #define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3771 #define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3772 #define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3773 #define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3774
Kojto 122:f9eeca106725 3775 #define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
Kojto 122:f9eeca106725 3776 #define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3777 #define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3778 #define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3779
bogdanm 92:4fc01daae5a5 3780 /****************** Bit definition for FSMC_PCR4 register *******************/
Kojto 122:f9eeca106725 3781 #define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
Kojto 122:f9eeca106725 3782 #define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 122:f9eeca106725 3783 #define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
Kojto 122:f9eeca106725 3784
Kojto 122:f9eeca106725 3785 #define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 122:f9eeca106725 3786 #define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3787 #define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3788
Kojto 122:f9eeca106725 3789 #define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
Kojto 122:f9eeca106725 3790
Kojto 122:f9eeca106725 3791 #define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 122:f9eeca106725 3792 #define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 3793 #define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 3794 #define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 3795 #define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3796
Kojto 122:f9eeca106725 3797 #define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 122:f9eeca106725 3798 #define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3799 #define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3800 #define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3801 #define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3802
Kojto 122:f9eeca106725 3803 #define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
Kojto 122:f9eeca106725 3804 #define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3805 #define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3806 #define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 3807
bogdanm 92:4fc01daae5a5 3808 /******************* Bit definition for FSMC_SR2 register *******************/
Kojto 122:f9eeca106725 3809 #define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
Kojto 122:f9eeca106725 3810 #define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
Kojto 122:f9eeca106725 3811 #define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
Kojto 122:f9eeca106725 3812 #define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
Kojto 122:f9eeca106725 3813 #define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
Kojto 122:f9eeca106725 3814 #define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
Kojto 122:f9eeca106725 3815 #define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3816
bogdanm 92:4fc01daae5a5 3817 /******************* Bit definition for FSMC_SR3 register *******************/
Kojto 122:f9eeca106725 3818 #define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
Kojto 122:f9eeca106725 3819 #define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
Kojto 122:f9eeca106725 3820 #define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
Kojto 122:f9eeca106725 3821 #define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
Kojto 122:f9eeca106725 3822 #define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
Kojto 122:f9eeca106725 3823 #define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
Kojto 122:f9eeca106725 3824 #define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3825
bogdanm 92:4fc01daae5a5 3826 /******************* Bit definition for FSMC_SR4 register *******************/
Kojto 122:f9eeca106725 3827 #define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
Kojto 122:f9eeca106725 3828 #define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
Kojto 122:f9eeca106725 3829 #define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
Kojto 122:f9eeca106725 3830 #define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
Kojto 122:f9eeca106725 3831 #define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
Kojto 122:f9eeca106725 3832 #define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
Kojto 122:f9eeca106725 3833 #define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
bogdanm 92:4fc01daae5a5 3834
bogdanm 92:4fc01daae5a5 3835 /****************** Bit definition for FSMC_PMEM2 register ******************/
Kojto 122:f9eeca106725 3836 #define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
Kojto 122:f9eeca106725 3837 #define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3838 #define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3839 #define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3840 #define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3841 #define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3842 #define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3843 #define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3844 #define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3845
Kojto 122:f9eeca106725 3846 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
Kojto 122:f9eeca106725 3847 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3848 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3849 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3850 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3851 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3852 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3853 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3854 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3855
Kojto 122:f9eeca106725 3856 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
Kojto 122:f9eeca106725 3857 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3858 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3859 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3860 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3861 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3862 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3863 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3864 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3865
Kojto 122:f9eeca106725 3866 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
Kojto 122:f9eeca106725 3867 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3868 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3869 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3870 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3871 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3872 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3873 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3874 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3875
bogdanm 92:4fc01daae5a5 3876 /****************** Bit definition for FSMC_PMEM3 register ******************/
Kojto 122:f9eeca106725 3877 #define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
Kojto 122:f9eeca106725 3878 #define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3879 #define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3880 #define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3881 #define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3882 #define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3883 #define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3884 #define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3885 #define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3886
Kojto 122:f9eeca106725 3887 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
Kojto 122:f9eeca106725 3888 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3889 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3890 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3891 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3892 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3893 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3894 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3895 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3896
Kojto 122:f9eeca106725 3897 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
Kojto 122:f9eeca106725 3898 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3899 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3900 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3901 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3902 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3903 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3904 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3905 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3906
Kojto 122:f9eeca106725 3907 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
Kojto 122:f9eeca106725 3908 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3909 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3910 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3911 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3912 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3913 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3914 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3915 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3916
bogdanm 92:4fc01daae5a5 3917 /****************** Bit definition for FSMC_PMEM4 register ******************/
Kojto 122:f9eeca106725 3918 #define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
Kojto 122:f9eeca106725 3919 #define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3920 #define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3921 #define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3922 #define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3923 #define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3924 #define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3925 #define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3926 #define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3927
Kojto 122:f9eeca106725 3928 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
Kojto 122:f9eeca106725 3929 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3930 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3931 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3932 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3933 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3934 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3935 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3936 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3937
Kojto 122:f9eeca106725 3938 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
Kojto 122:f9eeca106725 3939 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3940 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3941 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3942 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3943 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3944 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3945 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3946 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3947
Kojto 122:f9eeca106725 3948 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
Kojto 122:f9eeca106725 3949 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3950 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3951 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3952 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3953 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3954 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3955 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3956 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3957
bogdanm 92:4fc01daae5a5 3958 /****************** Bit definition for FSMC_PATT2 register ******************/
Kojto 122:f9eeca106725 3959 #define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
Kojto 122:f9eeca106725 3960 #define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3961 #define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3962 #define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3963 #define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3964 #define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 3965 #define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 3966 #define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 3967 #define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 3968
Kojto 122:f9eeca106725 3969 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
Kojto 122:f9eeca106725 3970 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3971 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3972 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3973 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3974 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3975 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3976 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3977 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3978
Kojto 122:f9eeca106725 3979 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
Kojto 122:f9eeca106725 3980 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3981 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3982 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3983 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3984 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3985 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3986 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3987 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3988
Kojto 122:f9eeca106725 3989 #define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
Kojto 122:f9eeca106725 3990 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3991 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3992 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3993 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3994 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3995 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3996 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3997 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 3998
bogdanm 92:4fc01daae5a5 3999 /****************** Bit definition for FSMC_PATT3 register ******************/
Kojto 122:f9eeca106725 4000 #define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
Kojto 122:f9eeca106725 4001 #define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4002 #define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4003 #define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4004 #define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4005 #define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4006 #define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4007 #define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4008 #define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4009
Kojto 122:f9eeca106725 4010 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
Kojto 122:f9eeca106725 4011 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4012 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4013 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4014 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4015 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4016 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4017 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4018 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4019
Kojto 122:f9eeca106725 4020 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
Kojto 122:f9eeca106725 4021 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4022 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4023 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4024 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4025 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4026 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4027 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4028 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4029
Kojto 122:f9eeca106725 4030 #define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
Kojto 122:f9eeca106725 4031 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4032 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4033 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4034 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4035 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4036 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4037 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4038 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4039
bogdanm 92:4fc01daae5a5 4040 /****************** Bit definition for FSMC_PATT4 register ******************/
Kojto 122:f9eeca106725 4041 #define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
Kojto 122:f9eeca106725 4042 #define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4043 #define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4044 #define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4045 #define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4046 #define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4047 #define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4048 #define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4049 #define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4050
Kojto 122:f9eeca106725 4051 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
Kojto 122:f9eeca106725 4052 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4053 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4054 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4055 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4056 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4057 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4058 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4059 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4060
Kojto 122:f9eeca106725 4061 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
Kojto 122:f9eeca106725 4062 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4063 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4064 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4065 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4066 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4067 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4068 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4069 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4070
Kojto 122:f9eeca106725 4071 #define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
Kojto 122:f9eeca106725 4072 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4073 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4074 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4075 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4076 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4077 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4078 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4079 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4080
bogdanm 92:4fc01daae5a5 4081 /****************** Bit definition for FSMC_PIO4 register *******************/
Kojto 122:f9eeca106725 4082 #define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
Kojto 122:f9eeca106725 4083 #define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4084 #define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4085 #define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4086 #define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4087 #define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4088 #define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4089 #define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4090 #define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4091
Kojto 122:f9eeca106725 4092 #define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
Kojto 122:f9eeca106725 4093 #define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4094 #define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4095 #define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4096 #define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4097 #define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4098 #define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4099 #define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4100 #define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4101
Kojto 122:f9eeca106725 4102 #define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
Kojto 122:f9eeca106725 4103 #define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4104 #define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4105 #define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4106 #define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4107 #define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4108 #define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4109 #define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4110 #define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4111
Kojto 122:f9eeca106725 4112 #define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
Kojto 122:f9eeca106725 4113 #define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4114 #define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4115 #define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4116 #define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4117 #define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4118 #define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4119 #define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4120 #define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 4121
bogdanm 92:4fc01daae5a5 4122 /****************** Bit definition for FSMC_ECCR2 register ******************/
Kojto 122:f9eeca106725 4123 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
bogdanm 92:4fc01daae5a5 4124
bogdanm 92:4fc01daae5a5 4125 /****************** Bit definition for FSMC_ECCR3 register ******************/
Kojto 122:f9eeca106725 4126 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
bogdanm 92:4fc01daae5a5 4127
bogdanm 92:4fc01daae5a5 4128 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4129 /* */
bogdanm 92:4fc01daae5a5 4130 /* General Purpose I/O */
bogdanm 92:4fc01daae5a5 4131 /* */
bogdanm 92:4fc01daae5a5 4132 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4133 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 4134 #define GPIO_MODER_MODER0 0x00000003U
Kojto 122:f9eeca106725 4135 #define GPIO_MODER_MODER0_0 0x00000001U
Kojto 122:f9eeca106725 4136 #define GPIO_MODER_MODER0_1 0x00000002U
Kojto 122:f9eeca106725 4137
Kojto 122:f9eeca106725 4138 #define GPIO_MODER_MODER1 0x0000000CU
Kojto 122:f9eeca106725 4139 #define GPIO_MODER_MODER1_0 0x00000004U
Kojto 122:f9eeca106725 4140 #define GPIO_MODER_MODER1_1 0x00000008U
Kojto 122:f9eeca106725 4141
Kojto 122:f9eeca106725 4142 #define GPIO_MODER_MODER2 0x00000030U
Kojto 122:f9eeca106725 4143 #define GPIO_MODER_MODER2_0 0x00000010U
Kojto 122:f9eeca106725 4144 #define GPIO_MODER_MODER2_1 0x00000020U
Kojto 122:f9eeca106725 4145
Kojto 122:f9eeca106725 4146 #define GPIO_MODER_MODER3 0x000000C0U
Kojto 122:f9eeca106725 4147 #define GPIO_MODER_MODER3_0 0x00000040U
Kojto 122:f9eeca106725 4148 #define GPIO_MODER_MODER3_1 0x00000080U
Kojto 122:f9eeca106725 4149
Kojto 122:f9eeca106725 4150 #define GPIO_MODER_MODER4 0x00000300U
Kojto 122:f9eeca106725 4151 #define GPIO_MODER_MODER4_0 0x00000100U
Kojto 122:f9eeca106725 4152 #define GPIO_MODER_MODER4_1 0x00000200U
Kojto 122:f9eeca106725 4153
Kojto 122:f9eeca106725 4154 #define GPIO_MODER_MODER5 0x00000C00U
Kojto 122:f9eeca106725 4155 #define GPIO_MODER_MODER5_0 0x00000400U
Kojto 122:f9eeca106725 4156 #define GPIO_MODER_MODER5_1 0x00000800U
Kojto 122:f9eeca106725 4157
Kojto 122:f9eeca106725 4158 #define GPIO_MODER_MODER6 0x00003000U
Kojto 122:f9eeca106725 4159 #define GPIO_MODER_MODER6_0 0x00001000U
Kojto 122:f9eeca106725 4160 #define GPIO_MODER_MODER6_1 0x00002000U
Kojto 122:f9eeca106725 4161
Kojto 122:f9eeca106725 4162 #define GPIO_MODER_MODER7 0x0000C000U
Kojto 122:f9eeca106725 4163 #define GPIO_MODER_MODER7_0 0x00004000U
Kojto 122:f9eeca106725 4164 #define GPIO_MODER_MODER7_1 0x00008000U
Kojto 122:f9eeca106725 4165
Kojto 122:f9eeca106725 4166 #define GPIO_MODER_MODER8 0x00030000U
Kojto 122:f9eeca106725 4167 #define GPIO_MODER_MODER8_0 0x00010000U
Kojto 122:f9eeca106725 4168 #define GPIO_MODER_MODER8_1 0x00020000U
Kojto 122:f9eeca106725 4169
Kojto 122:f9eeca106725 4170 #define GPIO_MODER_MODER9 0x000C0000U
Kojto 122:f9eeca106725 4171 #define GPIO_MODER_MODER9_0 0x00040000U
Kojto 122:f9eeca106725 4172 #define GPIO_MODER_MODER9_1 0x00080000U
Kojto 122:f9eeca106725 4173
Kojto 122:f9eeca106725 4174 #define GPIO_MODER_MODER10 0x00300000U
Kojto 122:f9eeca106725 4175 #define GPIO_MODER_MODER10_0 0x00100000U
Kojto 122:f9eeca106725 4176 #define GPIO_MODER_MODER10_1 0x00200000U
Kojto 122:f9eeca106725 4177
Kojto 122:f9eeca106725 4178 #define GPIO_MODER_MODER11 0x00C00000U
Kojto 122:f9eeca106725 4179 #define GPIO_MODER_MODER11_0 0x00400000U
Kojto 122:f9eeca106725 4180 #define GPIO_MODER_MODER11_1 0x00800000U
Kojto 122:f9eeca106725 4181
Kojto 122:f9eeca106725 4182 #define GPIO_MODER_MODER12 0x03000000U
Kojto 122:f9eeca106725 4183 #define GPIO_MODER_MODER12_0 0x01000000U
Kojto 122:f9eeca106725 4184 #define GPIO_MODER_MODER12_1 0x02000000U
Kojto 122:f9eeca106725 4185
Kojto 122:f9eeca106725 4186 #define GPIO_MODER_MODER13 0x0C000000U
Kojto 122:f9eeca106725 4187 #define GPIO_MODER_MODER13_0 0x04000000U
Kojto 122:f9eeca106725 4188 #define GPIO_MODER_MODER13_1 0x08000000U
Kojto 122:f9eeca106725 4189
Kojto 122:f9eeca106725 4190 #define GPIO_MODER_MODER14 0x30000000U
Kojto 122:f9eeca106725 4191 #define GPIO_MODER_MODER14_0 0x10000000U
Kojto 122:f9eeca106725 4192 #define GPIO_MODER_MODER14_1 0x20000000U
Kojto 122:f9eeca106725 4193
Kojto 122:f9eeca106725 4194 #define GPIO_MODER_MODER15 0xC0000000U
Kojto 122:f9eeca106725 4195 #define GPIO_MODER_MODER15_0 0x40000000U
Kojto 122:f9eeca106725 4196 #define GPIO_MODER_MODER15_1 0x80000000U
bogdanm 92:4fc01daae5a5 4197
bogdanm 92:4fc01daae5a5 4198 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 4199 #define GPIO_OTYPER_OT_0 0x00000001U
Kojto 122:f9eeca106725 4200 #define GPIO_OTYPER_OT_1 0x00000002U
Kojto 122:f9eeca106725 4201 #define GPIO_OTYPER_OT_2 0x00000004U
Kojto 122:f9eeca106725 4202 #define GPIO_OTYPER_OT_3 0x00000008U
Kojto 122:f9eeca106725 4203 #define GPIO_OTYPER_OT_4 0x00000010U
Kojto 122:f9eeca106725 4204 #define GPIO_OTYPER_OT_5 0x00000020U
Kojto 122:f9eeca106725 4205 #define GPIO_OTYPER_OT_6 0x00000040U
Kojto 122:f9eeca106725 4206 #define GPIO_OTYPER_OT_7 0x00000080U
Kojto 122:f9eeca106725 4207 #define GPIO_OTYPER_OT_8 0x00000100U
Kojto 122:f9eeca106725 4208 #define GPIO_OTYPER_OT_9 0x00000200U
Kojto 122:f9eeca106725 4209 #define GPIO_OTYPER_OT_10 0x00000400U
Kojto 122:f9eeca106725 4210 #define GPIO_OTYPER_OT_11 0x00000800U
Kojto 122:f9eeca106725 4211 #define GPIO_OTYPER_OT_12 0x00001000U
Kojto 122:f9eeca106725 4212 #define GPIO_OTYPER_OT_13 0x00002000U
Kojto 122:f9eeca106725 4213 #define GPIO_OTYPER_OT_14 0x00004000U
Kojto 122:f9eeca106725 4214 #define GPIO_OTYPER_OT_15 0x00008000U
bogdanm 92:4fc01daae5a5 4215
bogdanm 92:4fc01daae5a5 4216 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 4217 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto 122:f9eeca106725 4218 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto 122:f9eeca106725 4219 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto 122:f9eeca106725 4220
Kojto 122:f9eeca106725 4221 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto 122:f9eeca106725 4222 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto 122:f9eeca106725 4223 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto 122:f9eeca106725 4224
Kojto 122:f9eeca106725 4225 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto 122:f9eeca106725 4226 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto 122:f9eeca106725 4227 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto 122:f9eeca106725 4228
Kojto 122:f9eeca106725 4229 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto 122:f9eeca106725 4230 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto 122:f9eeca106725 4231 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto 122:f9eeca106725 4232
Kojto 122:f9eeca106725 4233 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto 122:f9eeca106725 4234 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto 122:f9eeca106725 4235 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto 122:f9eeca106725 4236
Kojto 122:f9eeca106725 4237 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto 122:f9eeca106725 4238 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto 122:f9eeca106725 4239 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto 122:f9eeca106725 4240
Kojto 122:f9eeca106725 4241 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto 122:f9eeca106725 4242 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto 122:f9eeca106725 4243 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto 122:f9eeca106725 4244
Kojto 122:f9eeca106725 4245 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto 122:f9eeca106725 4246 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto 122:f9eeca106725 4247 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto 122:f9eeca106725 4248
Kojto 122:f9eeca106725 4249 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto 122:f9eeca106725 4250 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto 122:f9eeca106725 4251 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto 122:f9eeca106725 4252
Kojto 122:f9eeca106725 4253 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto 122:f9eeca106725 4254 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto 122:f9eeca106725 4255 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto 122:f9eeca106725 4256
Kojto 122:f9eeca106725 4257 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto 122:f9eeca106725 4258 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto 122:f9eeca106725 4259 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto 122:f9eeca106725 4260
Kojto 122:f9eeca106725 4261 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto 122:f9eeca106725 4262 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto 122:f9eeca106725 4263 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto 122:f9eeca106725 4264
Kojto 122:f9eeca106725 4265 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto 122:f9eeca106725 4266 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto 122:f9eeca106725 4267 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto 122:f9eeca106725 4268
Kojto 122:f9eeca106725 4269 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto 122:f9eeca106725 4270 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto 122:f9eeca106725 4271 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto 122:f9eeca106725 4272
Kojto 122:f9eeca106725 4273 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto 122:f9eeca106725 4274 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto 122:f9eeca106725 4275 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto 122:f9eeca106725 4276
Kojto 122:f9eeca106725 4277 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto 122:f9eeca106725 4278 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto 122:f9eeca106725 4279 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
bogdanm 92:4fc01daae5a5 4280
bogdanm 92:4fc01daae5a5 4281 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 4282 #define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto 122:f9eeca106725 4283 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto 122:f9eeca106725 4284 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto 122:f9eeca106725 4285
Kojto 122:f9eeca106725 4286 #define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto 122:f9eeca106725 4287 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto 122:f9eeca106725 4288 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto 122:f9eeca106725 4289
Kojto 122:f9eeca106725 4290 #define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto 122:f9eeca106725 4291 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto 122:f9eeca106725 4292 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto 122:f9eeca106725 4293
Kojto 122:f9eeca106725 4294 #define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto 122:f9eeca106725 4295 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto 122:f9eeca106725 4296 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto 122:f9eeca106725 4297
Kojto 122:f9eeca106725 4298 #define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto 122:f9eeca106725 4299 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto 122:f9eeca106725 4300 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto 122:f9eeca106725 4301
Kojto 122:f9eeca106725 4302 #define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto 122:f9eeca106725 4303 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto 122:f9eeca106725 4304 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto 122:f9eeca106725 4305
Kojto 122:f9eeca106725 4306 #define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto 122:f9eeca106725 4307 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto 122:f9eeca106725 4308 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto 122:f9eeca106725 4309
Kojto 122:f9eeca106725 4310 #define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto 122:f9eeca106725 4311 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto 122:f9eeca106725 4312 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto 122:f9eeca106725 4313
Kojto 122:f9eeca106725 4314 #define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto 122:f9eeca106725 4315 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto 122:f9eeca106725 4316 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto 122:f9eeca106725 4317
Kojto 122:f9eeca106725 4318 #define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto 122:f9eeca106725 4319 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto 122:f9eeca106725 4320 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto 122:f9eeca106725 4321
Kojto 122:f9eeca106725 4322 #define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto 122:f9eeca106725 4323 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto 122:f9eeca106725 4324 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto 122:f9eeca106725 4325
Kojto 122:f9eeca106725 4326 #define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto 122:f9eeca106725 4327 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto 122:f9eeca106725 4328 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto 122:f9eeca106725 4329
Kojto 122:f9eeca106725 4330 #define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto 122:f9eeca106725 4331 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto 122:f9eeca106725 4332 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto 122:f9eeca106725 4333
Kojto 122:f9eeca106725 4334 #define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto 122:f9eeca106725 4335 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto 122:f9eeca106725 4336 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto 122:f9eeca106725 4337
Kojto 122:f9eeca106725 4338 #define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto 122:f9eeca106725 4339 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto 122:f9eeca106725 4340 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto 122:f9eeca106725 4341
Kojto 122:f9eeca106725 4342 #define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto 122:f9eeca106725 4343 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto 122:f9eeca106725 4344 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
bogdanm 92:4fc01daae5a5 4345
bogdanm 92:4fc01daae5a5 4346 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 4347 #define GPIO_IDR_IDR_0 0x00000001U
Kojto 122:f9eeca106725 4348 #define GPIO_IDR_IDR_1 0x00000002U
Kojto 122:f9eeca106725 4349 #define GPIO_IDR_IDR_2 0x00000004U
Kojto 122:f9eeca106725 4350 #define GPIO_IDR_IDR_3 0x00000008U
Kojto 122:f9eeca106725 4351 #define GPIO_IDR_IDR_4 0x00000010U
Kojto 122:f9eeca106725 4352 #define GPIO_IDR_IDR_5 0x00000020U
Kojto 122:f9eeca106725 4353 #define GPIO_IDR_IDR_6 0x00000040U
Kojto 122:f9eeca106725 4354 #define GPIO_IDR_IDR_7 0x00000080U
Kojto 122:f9eeca106725 4355 #define GPIO_IDR_IDR_8 0x00000100U
Kojto 122:f9eeca106725 4356 #define GPIO_IDR_IDR_9 0x00000200U
Kojto 122:f9eeca106725 4357 #define GPIO_IDR_IDR_10 0x00000400U
Kojto 122:f9eeca106725 4358 #define GPIO_IDR_IDR_11 0x00000800U
Kojto 122:f9eeca106725 4359 #define GPIO_IDR_IDR_12 0x00001000U
Kojto 122:f9eeca106725 4360 #define GPIO_IDR_IDR_13 0x00002000U
Kojto 122:f9eeca106725 4361 #define GPIO_IDR_IDR_14 0x00004000U
Kojto 122:f9eeca106725 4362 #define GPIO_IDR_IDR_15 0x00008000U
bogdanm 92:4fc01daae5a5 4363 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4364 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm 92:4fc01daae5a5 4365 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm 92:4fc01daae5a5 4366 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm 92:4fc01daae5a5 4367 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm 92:4fc01daae5a5 4368 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm 92:4fc01daae5a5 4369 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm 92:4fc01daae5a5 4370 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm 92:4fc01daae5a5 4371 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm 92:4fc01daae5a5 4372 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm 92:4fc01daae5a5 4373 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm 92:4fc01daae5a5 4374 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm 92:4fc01daae5a5 4375 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm 92:4fc01daae5a5 4376 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm 92:4fc01daae5a5 4377 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm 92:4fc01daae5a5 4378 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm 92:4fc01daae5a5 4379 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm 92:4fc01daae5a5 4380
bogdanm 92:4fc01daae5a5 4381 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 4382 #define GPIO_ODR_ODR_0 0x00000001U
Kojto 122:f9eeca106725 4383 #define GPIO_ODR_ODR_1 0x00000002U
Kojto 122:f9eeca106725 4384 #define GPIO_ODR_ODR_2 0x00000004U
Kojto 122:f9eeca106725 4385 #define GPIO_ODR_ODR_3 0x00000008U
Kojto 122:f9eeca106725 4386 #define GPIO_ODR_ODR_4 0x00000010U
Kojto 122:f9eeca106725 4387 #define GPIO_ODR_ODR_5 0x00000020U
Kojto 122:f9eeca106725 4388 #define GPIO_ODR_ODR_6 0x00000040U
Kojto 122:f9eeca106725 4389 #define GPIO_ODR_ODR_7 0x00000080U
Kojto 122:f9eeca106725 4390 #define GPIO_ODR_ODR_8 0x00000100U
Kojto 122:f9eeca106725 4391 #define GPIO_ODR_ODR_9 0x00000200U
Kojto 122:f9eeca106725 4392 #define GPIO_ODR_ODR_10 0x00000400U
Kojto 122:f9eeca106725 4393 #define GPIO_ODR_ODR_11 0x00000800U
Kojto 122:f9eeca106725 4394 #define GPIO_ODR_ODR_12 0x00001000U
Kojto 122:f9eeca106725 4395 #define GPIO_ODR_ODR_13 0x00002000U
Kojto 122:f9eeca106725 4396 #define GPIO_ODR_ODR_14 0x00004000U
Kojto 122:f9eeca106725 4397 #define GPIO_ODR_ODR_15 0x00008000U
bogdanm 92:4fc01daae5a5 4398 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4399 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm 92:4fc01daae5a5 4400 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm 92:4fc01daae5a5 4401 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm 92:4fc01daae5a5 4402 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm 92:4fc01daae5a5 4403 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm 92:4fc01daae5a5 4404 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm 92:4fc01daae5a5 4405 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm 92:4fc01daae5a5 4406 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm 92:4fc01daae5a5 4407 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm 92:4fc01daae5a5 4408 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm 92:4fc01daae5a5 4409 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm 92:4fc01daae5a5 4410 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm 92:4fc01daae5a5 4411 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm 92:4fc01daae5a5 4412 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm 92:4fc01daae5a5 4413 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm 92:4fc01daae5a5 4414 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm 92:4fc01daae5a5 4415
bogdanm 92:4fc01daae5a5 4416 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 4417 #define GPIO_BSRR_BS_0 0x00000001U
Kojto 122:f9eeca106725 4418 #define GPIO_BSRR_BS_1 0x00000002U
Kojto 122:f9eeca106725 4419 #define GPIO_BSRR_BS_2 0x00000004U
Kojto 122:f9eeca106725 4420 #define GPIO_BSRR_BS_3 0x00000008U
Kojto 122:f9eeca106725 4421 #define GPIO_BSRR_BS_4 0x00000010U
Kojto 122:f9eeca106725 4422 #define GPIO_BSRR_BS_5 0x00000020U
Kojto 122:f9eeca106725 4423 #define GPIO_BSRR_BS_6 0x00000040U
Kojto 122:f9eeca106725 4424 #define GPIO_BSRR_BS_7 0x00000080U
Kojto 122:f9eeca106725 4425 #define GPIO_BSRR_BS_8 0x00000100U
Kojto 122:f9eeca106725 4426 #define GPIO_BSRR_BS_9 0x00000200U
Kojto 122:f9eeca106725 4427 #define GPIO_BSRR_BS_10 0x00000400U
Kojto 122:f9eeca106725 4428 #define GPIO_BSRR_BS_11 0x00000800U
Kojto 122:f9eeca106725 4429 #define GPIO_BSRR_BS_12 0x00001000U
Kojto 122:f9eeca106725 4430 #define GPIO_BSRR_BS_13 0x00002000U
Kojto 122:f9eeca106725 4431 #define GPIO_BSRR_BS_14 0x00004000U
Kojto 122:f9eeca106725 4432 #define GPIO_BSRR_BS_15 0x00008000U
Kojto 122:f9eeca106725 4433 #define GPIO_BSRR_BR_0 0x00010000U
Kojto 122:f9eeca106725 4434 #define GPIO_BSRR_BR_1 0x00020000U
Kojto 122:f9eeca106725 4435 #define GPIO_BSRR_BR_2 0x00040000U
Kojto 122:f9eeca106725 4436 #define GPIO_BSRR_BR_3 0x00080000U
Kojto 122:f9eeca106725 4437 #define GPIO_BSRR_BR_4 0x00100000U
Kojto 122:f9eeca106725 4438 #define GPIO_BSRR_BR_5 0x00200000U
Kojto 122:f9eeca106725 4439 #define GPIO_BSRR_BR_6 0x00400000U
Kojto 122:f9eeca106725 4440 #define GPIO_BSRR_BR_7 0x00800000U
Kojto 122:f9eeca106725 4441 #define GPIO_BSRR_BR_8 0x01000000U
Kojto 122:f9eeca106725 4442 #define GPIO_BSRR_BR_9 0x02000000U
Kojto 122:f9eeca106725 4443 #define GPIO_BSRR_BR_10 0x04000000U
Kojto 122:f9eeca106725 4444 #define GPIO_BSRR_BR_11 0x08000000U
Kojto 122:f9eeca106725 4445 #define GPIO_BSRR_BR_12 0x10000000U
Kojto 122:f9eeca106725 4446 #define GPIO_BSRR_BR_13 0x20000000U
Kojto 122:f9eeca106725 4447 #define GPIO_BSRR_BR_14 0x40000000U
Kojto 122:f9eeca106725 4448 #define GPIO_BSRR_BR_15 0x80000000U
bogdanm 92:4fc01daae5a5 4449
bogdanm 92:4fc01daae5a5 4450 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 122:f9eeca106725 4451 #define GPIO_LCKR_LCK0 0x00000001U
Kojto 122:f9eeca106725 4452 #define GPIO_LCKR_LCK1 0x00000002U
Kojto 122:f9eeca106725 4453 #define GPIO_LCKR_LCK2 0x00000004U
Kojto 122:f9eeca106725 4454 #define GPIO_LCKR_LCK3 0x00000008U
Kojto 122:f9eeca106725 4455 #define GPIO_LCKR_LCK4 0x00000010U
Kojto 122:f9eeca106725 4456 #define GPIO_LCKR_LCK5 0x00000020U
Kojto 122:f9eeca106725 4457 #define GPIO_LCKR_LCK6 0x00000040U
Kojto 122:f9eeca106725 4458 #define GPIO_LCKR_LCK7 0x00000080U
Kojto 122:f9eeca106725 4459 #define GPIO_LCKR_LCK8 0x00000100U
Kojto 122:f9eeca106725 4460 #define GPIO_LCKR_LCK9 0x00000200U
Kojto 122:f9eeca106725 4461 #define GPIO_LCKR_LCK10 0x00000400U
Kojto 122:f9eeca106725 4462 #define GPIO_LCKR_LCK11 0x00000800U
Kojto 122:f9eeca106725 4463 #define GPIO_LCKR_LCK12 0x00001000U
Kojto 122:f9eeca106725 4464 #define GPIO_LCKR_LCK13 0x00002000U
Kojto 122:f9eeca106725 4465 #define GPIO_LCKR_LCK14 0x00004000U
Kojto 122:f9eeca106725 4466 #define GPIO_LCKR_LCK15 0x00008000U
Kojto 122:f9eeca106725 4467 #define GPIO_LCKR_LCKK 0x00010000U
bogdanm 92:4fc01daae5a5 4468
bogdanm 92:4fc01daae5a5 4469 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4470 /* */
bogdanm 92:4fc01daae5a5 4471 /* Inter-integrated Circuit Interface */
bogdanm 92:4fc01daae5a5 4472 /* */
bogdanm 92:4fc01daae5a5 4473 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4474 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 122:f9eeca106725 4475 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
Kojto 122:f9eeca106725 4476 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
Kojto 122:f9eeca106725 4477 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
Kojto 122:f9eeca106725 4478 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
Kojto 122:f9eeca106725 4479 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
Kojto 122:f9eeca106725 4480 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
Kojto 122:f9eeca106725 4481 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
Kojto 122:f9eeca106725 4482 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
Kojto 122:f9eeca106725 4483 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
Kojto 122:f9eeca106725 4484 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
Kojto 122:f9eeca106725 4485 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
Kojto 122:f9eeca106725 4486 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
Kojto 122:f9eeca106725 4487 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
Kojto 122:f9eeca106725 4488 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
bogdanm 92:4fc01daae5a5 4489
bogdanm 92:4fc01daae5a5 4490 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 4491 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 122:f9eeca106725 4492 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4493 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4494 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4495 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4496 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4497 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4498
Kojto 122:f9eeca106725 4499 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 4500 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
Kojto 122:f9eeca106725 4501 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
Kojto 122:f9eeca106725 4502 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
Kojto 122:f9eeca106725 4503 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
bogdanm 92:4fc01daae5a5 4504
bogdanm 92:4fc01daae5a5 4505 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 122:f9eeca106725 4506 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
Kojto 122:f9eeca106725 4507 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
Kojto 122:f9eeca106725 4508
Kojto 122:f9eeca106725 4509 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4510 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4511 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4512 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4513 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4514 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4515 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4516 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4517 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
Kojto 122:f9eeca106725 4518 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
Kojto 122:f9eeca106725 4519
Kojto 122:f9eeca106725 4520 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
bogdanm 92:4fc01daae5a5 4521
bogdanm 92:4fc01daae5a5 4522 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 122:f9eeca106725 4523 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
Kojto 122:f9eeca106725 4524 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
bogdanm 92:4fc01daae5a5 4525
bogdanm 92:4fc01daae5a5 4526 /******************** Bit definition for I2C_DR register ********************/
Kojto 122:f9eeca106725 4527 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
bogdanm 92:4fc01daae5a5 4528
bogdanm 92:4fc01daae5a5 4529 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 122:f9eeca106725 4530 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
Kojto 122:f9eeca106725 4531 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
Kojto 122:f9eeca106725 4532 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
Kojto 122:f9eeca106725 4533 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
Kojto 122:f9eeca106725 4534 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
Kojto 122:f9eeca106725 4535 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
Kojto 122:f9eeca106725 4536 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
Kojto 122:f9eeca106725 4537 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
Kojto 122:f9eeca106725 4538 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
Kojto 122:f9eeca106725 4539 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
Kojto 122:f9eeca106725 4540 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
Kojto 122:f9eeca106725 4541 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
Kojto 122:f9eeca106725 4542 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
Kojto 122:f9eeca106725 4543 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
bogdanm 92:4fc01daae5a5 4544
bogdanm 92:4fc01daae5a5 4545 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 122:f9eeca106725 4546 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
Kojto 122:f9eeca106725 4547 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
Kojto 122:f9eeca106725 4548 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
Kojto 122:f9eeca106725 4549 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
Kojto 122:f9eeca106725 4550 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
Kojto 122:f9eeca106725 4551 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
Kojto 122:f9eeca106725 4552 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
Kojto 122:f9eeca106725 4553 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
bogdanm 92:4fc01daae5a5 4554
bogdanm 92:4fc01daae5a5 4555 /******************* Bit definition for I2C_CCR register ********************/
Kojto 122:f9eeca106725 4556 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 122:f9eeca106725 4557 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
Kojto 122:f9eeca106725 4558 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
bogdanm 92:4fc01daae5a5 4559
bogdanm 92:4fc01daae5a5 4560 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 122:f9eeca106725 4561 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 92:4fc01daae5a5 4562
bogdanm 92:4fc01daae5a5 4563 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 122:f9eeca106725 4564 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
Kojto 122:f9eeca106725 4565 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
bogdanm 92:4fc01daae5a5 4566
bogdanm 92:4fc01daae5a5 4567 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4568 /* */
bogdanm 92:4fc01daae5a5 4569 /* Independent WATCHDOG */
bogdanm 92:4fc01daae5a5 4570 /* */
bogdanm 92:4fc01daae5a5 4571 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4572 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 4573 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
bogdanm 92:4fc01daae5a5 4574
bogdanm 92:4fc01daae5a5 4575 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 4576 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 4577 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 4578 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 4579 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
bogdanm 92:4fc01daae5a5 4580
bogdanm 92:4fc01daae5a5 4581 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 4582 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
bogdanm 92:4fc01daae5a5 4583
bogdanm 92:4fc01daae5a5 4584 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 4585 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
Kojto 122:f9eeca106725 4586 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
bogdanm 92:4fc01daae5a5 4587
bogdanm 92:4fc01daae5a5 4588
bogdanm 92:4fc01daae5a5 4589 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4590 /* */
bogdanm 92:4fc01daae5a5 4591 /* Power Control */
bogdanm 92:4fc01daae5a5 4592 /* */
bogdanm 92:4fc01daae5a5 4593 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4594 /******************** Bit definition for PWR_CR register ********************/
Kojto 122:f9eeca106725 4595 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
Kojto 122:f9eeca106725 4596 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 4597 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 4598 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 4599 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 4600
Kojto 122:f9eeca106725 4601 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 4602 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
Kojto 122:f9eeca106725 4603 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
Kojto 122:f9eeca106725 4604 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 4605
bogdanm 92:4fc01daae5a5 4606 /*!< PVD level configuration */
Kojto 122:f9eeca106725 4607 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
Kojto 122:f9eeca106725 4608 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
Kojto 122:f9eeca106725 4609 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
Kojto 122:f9eeca106725 4610 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
Kojto 122:f9eeca106725 4611 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
Kojto 122:f9eeca106725 4612 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
Kojto 122:f9eeca106725 4613 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
Kojto 122:f9eeca106725 4614 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
Kojto 122:f9eeca106725 4615
Kojto 122:f9eeca106725 4616 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
Kojto 122:f9eeca106725 4617 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
Kojto 122:f9eeca106725 4618 #define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
bogdanm 92:4fc01daae5a5 4619
bogdanm 92:4fc01daae5a5 4620 /* Legacy define */
bogdanm 92:4fc01daae5a5 4621 #define PWR_CR_PMODE PWR_CR_VOS
bogdanm 92:4fc01daae5a5 4622
bogdanm 92:4fc01daae5a5 4623 /******************* Bit definition for PWR_CSR register ********************/
Kojto 122:f9eeca106725 4624 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
Kojto 122:f9eeca106725 4625 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
Kojto 122:f9eeca106725 4626 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
Kojto 122:f9eeca106725 4627 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
Kojto 122:f9eeca106725 4628 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
Kojto 122:f9eeca106725 4629 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
Kojto 122:f9eeca106725 4630 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
bogdanm 92:4fc01daae5a5 4631
bogdanm 92:4fc01daae5a5 4632 /* Legacy define */
bogdanm 92:4fc01daae5a5 4633 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm 92:4fc01daae5a5 4634
bogdanm 92:4fc01daae5a5 4635 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4636 /* */
bogdanm 92:4fc01daae5a5 4637 /* Reset and Clock Control */
bogdanm 92:4fc01daae5a5 4638 /* */
bogdanm 92:4fc01daae5a5 4639 /******************************************************************************/
bogdanm 92:4fc01daae5a5 4640 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 4641 #define RCC_CR_HSION 0x00000001U
Kojto 122:f9eeca106725 4642 #define RCC_CR_HSIRDY 0x00000002U
Kojto 122:f9eeca106725 4643
Kojto 122:f9eeca106725 4644 #define RCC_CR_HSITRIM 0x000000F8U
Kojto 122:f9eeca106725 4645 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
Kojto 122:f9eeca106725 4646 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
Kojto 122:f9eeca106725 4647 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
Kojto 122:f9eeca106725 4648 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
Kojto 122:f9eeca106725 4649 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
Kojto 122:f9eeca106725 4650
Kojto 122:f9eeca106725 4651 #define RCC_CR_HSICAL 0x0000FF00U
Kojto 122:f9eeca106725 4652 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
Kojto 122:f9eeca106725 4653 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
Kojto 122:f9eeca106725 4654 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
Kojto 122:f9eeca106725 4655 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
Kojto 122:f9eeca106725 4656 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
Kojto 122:f9eeca106725 4657 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
Kojto 122:f9eeca106725 4658 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
Kojto 122:f9eeca106725 4659 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
Kojto 122:f9eeca106725 4660
Kojto 122:f9eeca106725 4661 #define RCC_CR_HSEON 0x00010000U
Kojto 122:f9eeca106725 4662 #define RCC_CR_HSERDY 0x00020000U
Kojto 122:f9eeca106725 4663 #define RCC_CR_HSEBYP 0x00040000U
Kojto 122:f9eeca106725 4664 #define RCC_CR_CSSON 0x00080000U
Kojto 122:f9eeca106725 4665 #define RCC_CR_PLLON 0x01000000U
Kojto 122:f9eeca106725 4666 #define RCC_CR_PLLRDY 0x02000000U
Kojto 122:f9eeca106725 4667 #define RCC_CR_PLLI2SON 0x04000000U
Kojto 122:f9eeca106725 4668 #define RCC_CR_PLLI2SRDY 0x08000000U
bogdanm 92:4fc01daae5a5 4669
bogdanm 92:4fc01daae5a5 4670 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 122:f9eeca106725 4671 #define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto 122:f9eeca106725 4672 #define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto 122:f9eeca106725 4673 #define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto 122:f9eeca106725 4674 #define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto 122:f9eeca106725 4675 #define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto 122:f9eeca106725 4676 #define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto 122:f9eeca106725 4677 #define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto 122:f9eeca106725 4678
Kojto 122:f9eeca106725 4679 #define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto 122:f9eeca106725 4680 #define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto 122:f9eeca106725 4681 #define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto 122:f9eeca106725 4682 #define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto 122:f9eeca106725 4683 #define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto 122:f9eeca106725 4684 #define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto 122:f9eeca106725 4685 #define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto 122:f9eeca106725 4686 #define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto 122:f9eeca106725 4687 #define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto 122:f9eeca106725 4688 #define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto 122:f9eeca106725 4689
Kojto 122:f9eeca106725 4690 #define RCC_PLLCFGR_PLLP 0x00030000U
Kojto 122:f9eeca106725 4691 #define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto 122:f9eeca106725 4692 #define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto 122:f9eeca106725 4693
Kojto 122:f9eeca106725 4694 #define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto 122:f9eeca106725 4695 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto 122:f9eeca106725 4696 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto 122:f9eeca106725 4697
Kojto 122:f9eeca106725 4698 #define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto 122:f9eeca106725 4699 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto 122:f9eeca106725 4700 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto 122:f9eeca106725 4701 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto 122:f9eeca106725 4702 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
bogdanm 92:4fc01daae5a5 4703
bogdanm 92:4fc01daae5a5 4704 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 92:4fc01daae5a5 4705 /*!< SW configuration */
Kojto 122:f9eeca106725 4706 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 4707 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 4708 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 4709
Kojto 122:f9eeca106725 4710 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 4711 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 4712 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
bogdanm 92:4fc01daae5a5 4713
bogdanm 92:4fc01daae5a5 4714 /*!< SWS configuration */
Kojto 122:f9eeca106725 4715 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 4716 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
Kojto 122:f9eeca106725 4717 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
Kojto 122:f9eeca106725 4718
Kojto 122:f9eeca106725 4719 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 4720 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 4721 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
bogdanm 92:4fc01daae5a5 4722
bogdanm 92:4fc01daae5a5 4723 /*!< HPRE configuration */
Kojto 122:f9eeca106725 4724 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 4725 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
Kojto 122:f9eeca106725 4726 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
Kojto 122:f9eeca106725 4727 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
Kojto 122:f9eeca106725 4728 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
Kojto 122:f9eeca106725 4729
Kojto 122:f9eeca106725 4730 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 4731 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 4732 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 4733 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 4734 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 4735 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 4736 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 4737 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 4738 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
bogdanm 92:4fc01daae5a5 4739
bogdanm 92:4fc01daae5a5 4740 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 4741 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 4742 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 4743 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 4744 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
Kojto 122:f9eeca106725 4745
Kojto 122:f9eeca106725 4746 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 4747 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 4748 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 4749 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 4750 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
bogdanm 92:4fc01daae5a5 4751
bogdanm 92:4fc01daae5a5 4752 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 4753 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 4754 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
Kojto 122:f9eeca106725 4755 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4756 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
Kojto 122:f9eeca106725 4757
Kojto 122:f9eeca106725 4758 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 4759 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 4760 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 4761 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 4762 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
bogdanm 92:4fc01daae5a5 4763
bogdanm 92:4fc01daae5a5 4764 /*!< RTCPRE configuration */
Kojto 122:f9eeca106725 4765 #define RCC_CFGR_RTCPRE 0x001F0000U
Kojto 122:f9eeca106725 4766 #define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto 122:f9eeca106725 4767 #define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto 122:f9eeca106725 4768 #define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto 122:f9eeca106725 4769 #define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto 122:f9eeca106725 4770 #define RCC_CFGR_RTCPRE_4 0x00100000U
bogdanm 92:4fc01daae5a5 4771
bogdanm 92:4fc01daae5a5 4772 /*!< MCO1 configuration */
Kojto 122:f9eeca106725 4773 #define RCC_CFGR_MCO1 0x00600000U
Kojto 122:f9eeca106725 4774 #define RCC_CFGR_MCO1_0 0x00200000U
Kojto 122:f9eeca106725 4775 #define RCC_CFGR_MCO1_1 0x00400000U
Kojto 122:f9eeca106725 4776
Kojto 122:f9eeca106725 4777 #define RCC_CFGR_I2SSRC 0x00800000U
Kojto 122:f9eeca106725 4778
Kojto 122:f9eeca106725 4779 #define RCC_CFGR_MCO1PRE 0x07000000U
Kojto 122:f9eeca106725 4780 #define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto 122:f9eeca106725 4781 #define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto 122:f9eeca106725 4782 #define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto 122:f9eeca106725 4783
Kojto 122:f9eeca106725 4784 #define RCC_CFGR_MCO2PRE 0x38000000U
Kojto 122:f9eeca106725 4785 #define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto 122:f9eeca106725 4786 #define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto 122:f9eeca106725 4787 #define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto 122:f9eeca106725 4788
Kojto 122:f9eeca106725 4789 #define RCC_CFGR_MCO2 0xC0000000U
Kojto 122:f9eeca106725 4790 #define RCC_CFGR_MCO2_0 0x40000000U
Kojto 122:f9eeca106725 4791 #define RCC_CFGR_MCO2_1 0x80000000U
bogdanm 92:4fc01daae5a5 4792
bogdanm 92:4fc01daae5a5 4793 /******************** Bit definition for RCC_CIR register *******************/
Kojto 122:f9eeca106725 4794 #define RCC_CIR_LSIRDYF 0x00000001U
Kojto 122:f9eeca106725 4795 #define RCC_CIR_LSERDYF 0x00000002U
Kojto 122:f9eeca106725 4796 #define RCC_CIR_HSIRDYF 0x00000004U
Kojto 122:f9eeca106725 4797 #define RCC_CIR_HSERDYF 0x00000008U
Kojto 122:f9eeca106725 4798 #define RCC_CIR_PLLRDYF 0x00000010U
Kojto 122:f9eeca106725 4799 #define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto 122:f9eeca106725 4800
Kojto 122:f9eeca106725 4801 #define RCC_CIR_CSSF 0x00000080U
Kojto 122:f9eeca106725 4802 #define RCC_CIR_LSIRDYIE 0x00000100U
Kojto 122:f9eeca106725 4803 #define RCC_CIR_LSERDYIE 0x00000200U
Kojto 122:f9eeca106725 4804 #define RCC_CIR_HSIRDYIE 0x00000400U
Kojto 122:f9eeca106725 4805 #define RCC_CIR_HSERDYIE 0x00000800U
Kojto 122:f9eeca106725 4806 #define RCC_CIR_PLLRDYIE 0x00001000U
Kojto 122:f9eeca106725 4807 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto 122:f9eeca106725 4808
Kojto 122:f9eeca106725 4809 #define RCC_CIR_LSIRDYC 0x00010000U
Kojto 122:f9eeca106725 4810 #define RCC_CIR_LSERDYC 0x00020000U
Kojto 122:f9eeca106725 4811 #define RCC_CIR_HSIRDYC 0x00040000U
Kojto 122:f9eeca106725 4812 #define RCC_CIR_HSERDYC 0x00080000U
Kojto 122:f9eeca106725 4813 #define RCC_CIR_PLLRDYC 0x00100000U
Kojto 122:f9eeca106725 4814 #define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto 122:f9eeca106725 4815
Kojto 122:f9eeca106725 4816 #define RCC_CIR_CSSC 0x00800000U
bogdanm 92:4fc01daae5a5 4817
bogdanm 92:4fc01daae5a5 4818 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 122:f9eeca106725 4819 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto 122:f9eeca106725 4820 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto 122:f9eeca106725 4821 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto 122:f9eeca106725 4822 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto 122:f9eeca106725 4823 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto 122:f9eeca106725 4824 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
Kojto 122:f9eeca106725 4825 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
Kojto 122:f9eeca106725 4826 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto 122:f9eeca106725 4827 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
Kojto 122:f9eeca106725 4828 #define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto 122:f9eeca106725 4829 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto 122:f9eeca106725 4830 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto 122:f9eeca106725 4831 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
bogdanm 92:4fc01daae5a5 4832
bogdanm 92:4fc01daae5a5 4833 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 122:f9eeca106725 4834 #define RCC_AHB2RSTR_RNGRST 0x00000040U
Kojto 122:f9eeca106725 4835 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
bogdanm 92:4fc01daae5a5 4836
bogdanm 92:4fc01daae5a5 4837 /******************** Bit definition for RCC_AHB3RSTR register **************/
bogdanm 92:4fc01daae5a5 4838
Kojto 122:f9eeca106725 4839 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
bogdanm 92:4fc01daae5a5 4840
bogdanm 92:4fc01daae5a5 4841 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 122:f9eeca106725 4842 #define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto 122:f9eeca106725 4843 #define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto 122:f9eeca106725 4844 #define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto 122:f9eeca106725 4845 #define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto 122:f9eeca106725 4846 #define RCC_APB1RSTR_TIM6RST 0x00000010U
Kojto 122:f9eeca106725 4847 #define RCC_APB1RSTR_TIM7RST 0x00000020U
Kojto 122:f9eeca106725 4848 #define RCC_APB1RSTR_TIM12RST 0x00000040U
Kojto 122:f9eeca106725 4849 #define RCC_APB1RSTR_TIM13RST 0x00000080U
Kojto 122:f9eeca106725 4850 #define RCC_APB1RSTR_TIM14RST 0x00000100U
Kojto 122:f9eeca106725 4851 #define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto 122:f9eeca106725 4852 #define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto 122:f9eeca106725 4853 #define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto 122:f9eeca106725 4854 #define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto 122:f9eeca106725 4855 #define RCC_APB1RSTR_USART3RST 0x00040000U
Kojto 122:f9eeca106725 4856 #define RCC_APB1RSTR_UART4RST 0x00080000U
Kojto 122:f9eeca106725 4857 #define RCC_APB1RSTR_UART5RST 0x00100000U
Kojto 122:f9eeca106725 4858 #define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto 122:f9eeca106725 4859 #define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto 122:f9eeca106725 4860 #define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto 122:f9eeca106725 4861 #define RCC_APB1RSTR_CAN1RST 0x02000000U
Kojto 122:f9eeca106725 4862 #define RCC_APB1RSTR_CAN2RST 0x04000000U
Kojto 122:f9eeca106725 4863 #define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto 122:f9eeca106725 4864 #define RCC_APB1RSTR_DACRST 0x20000000U
bogdanm 92:4fc01daae5a5 4865
bogdanm 92:4fc01daae5a5 4866 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 122:f9eeca106725 4867 #define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto 122:f9eeca106725 4868 #define RCC_APB2RSTR_TIM8RST 0x00000002U
Kojto 122:f9eeca106725 4869 #define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto 122:f9eeca106725 4870 #define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto 122:f9eeca106725 4871 #define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto 122:f9eeca106725 4872 #define RCC_APB2RSTR_SDIORST 0x00000800U
Kojto 122:f9eeca106725 4873 #define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto 122:f9eeca106725 4874 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto 122:f9eeca106725 4875 #define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto 122:f9eeca106725 4876 #define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto 122:f9eeca106725 4877 #define RCC_APB2RSTR_TIM11RST 0x00040000U
bogdanm 92:4fc01daae5a5 4878
bogdanm 92:4fc01daae5a5 4879 /* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 4880 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm 92:4fc01daae5a5 4881
bogdanm 92:4fc01daae5a5 4882 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 122:f9eeca106725 4883 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto 122:f9eeca106725 4884 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto 122:f9eeca106725 4885 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto 122:f9eeca106725 4886 #define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto 122:f9eeca106725 4887 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto 122:f9eeca106725 4888 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
Kojto 122:f9eeca106725 4889 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
Kojto 122:f9eeca106725 4890 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto 122:f9eeca106725 4891 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
Kojto 122:f9eeca106725 4892 #define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto 122:f9eeca106725 4893 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto 122:f9eeca106725 4894 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
Kojto 122:f9eeca106725 4895 #define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto 122:f9eeca106725 4896 #define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto 122:f9eeca106725 4897
Kojto 122:f9eeca106725 4898 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
Kojto 122:f9eeca106725 4899 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
bogdanm 92:4fc01daae5a5 4900
bogdanm 92:4fc01daae5a5 4901 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 122:f9eeca106725 4902 #define RCC_AHB2ENR_RNGEN 0x00000040U
Kojto 122:f9eeca106725 4903 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
bogdanm 92:4fc01daae5a5 4904
bogdanm 92:4fc01daae5a5 4905 /******************** Bit definition for RCC_AHB3ENR register ***************/
bogdanm 92:4fc01daae5a5 4906
Kojto 122:f9eeca106725 4907 #define RCC_AHB3ENR_FSMCEN 0x00000001U
bogdanm 92:4fc01daae5a5 4908
bogdanm 92:4fc01daae5a5 4909 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 122:f9eeca106725 4910 #define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto 122:f9eeca106725 4911 #define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto 122:f9eeca106725 4912 #define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto 122:f9eeca106725 4913 #define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto 122:f9eeca106725 4914 #define RCC_APB1ENR_TIM6EN 0x00000010U
Kojto 122:f9eeca106725 4915 #define RCC_APB1ENR_TIM7EN 0x00000020U
Kojto 122:f9eeca106725 4916 #define RCC_APB1ENR_TIM12EN 0x00000040U
Kojto 122:f9eeca106725 4917 #define RCC_APB1ENR_TIM13EN 0x00000080U
Kojto 122:f9eeca106725 4918 #define RCC_APB1ENR_TIM14EN 0x00000100U
Kojto 122:f9eeca106725 4919 #define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto 122:f9eeca106725 4920 #define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto 122:f9eeca106725 4921 #define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto 122:f9eeca106725 4922 #define RCC_APB1ENR_USART2EN 0x00020000U
Kojto 122:f9eeca106725 4923 #define RCC_APB1ENR_USART3EN 0x00040000U
Kojto 122:f9eeca106725 4924 #define RCC_APB1ENR_UART4EN 0x00080000U
Kojto 122:f9eeca106725 4925 #define RCC_APB1ENR_UART5EN 0x00100000U
Kojto 122:f9eeca106725 4926 #define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto 122:f9eeca106725 4927 #define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto 122:f9eeca106725 4928 #define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto 122:f9eeca106725 4929 #define RCC_APB1ENR_CAN1EN 0x02000000U
Kojto 122:f9eeca106725 4930 #define RCC_APB1ENR_CAN2EN 0x04000000U
Kojto 122:f9eeca106725 4931 #define RCC_APB1ENR_PWREN 0x10000000U
Kojto 122:f9eeca106725 4932 #define RCC_APB1ENR_DACEN 0x20000000U
bogdanm 92:4fc01daae5a5 4933
bogdanm 92:4fc01daae5a5 4934 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 122:f9eeca106725 4935 #define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto 122:f9eeca106725 4936 #define RCC_APB2ENR_TIM8EN 0x00000002U
Kojto 122:f9eeca106725 4937 #define RCC_APB2ENR_USART1EN 0x00000010U
Kojto 122:f9eeca106725 4938 #define RCC_APB2ENR_USART6EN 0x00000020U
Kojto 122:f9eeca106725 4939 #define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto 122:f9eeca106725 4940 #define RCC_APB2ENR_ADC2EN 0x00000200U
Kojto 122:f9eeca106725 4941 #define RCC_APB2ENR_ADC3EN 0x00000400U
Kojto 122:f9eeca106725 4942 #define RCC_APB2ENR_SDIOEN 0x00000800U
Kojto 122:f9eeca106725 4943 #define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto 122:f9eeca106725 4944 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto 122:f9eeca106725 4945 #define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto 122:f9eeca106725 4946 #define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto 122:f9eeca106725 4947 #define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto 122:f9eeca106725 4948 #define RCC_APB2ENR_SPI5EN 0x00100000U
Kojto 122:f9eeca106725 4949 #define RCC_APB2ENR_SPI6EN 0x00200000U
bogdanm 92:4fc01daae5a5 4950
bogdanm 92:4fc01daae5a5 4951 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 122:f9eeca106725 4952 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto 122:f9eeca106725 4953 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto 122:f9eeca106725 4954 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto 122:f9eeca106725 4955 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto 122:f9eeca106725 4956 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto 122:f9eeca106725 4957 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
Kojto 122:f9eeca106725 4958 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
Kojto 122:f9eeca106725 4959 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto 122:f9eeca106725 4960 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
Kojto 122:f9eeca106725 4961 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto 122:f9eeca106725 4962 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto 122:f9eeca106725 4963 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto 122:f9eeca106725 4964 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto 122:f9eeca106725 4965 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto 122:f9eeca106725 4966 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto 122:f9eeca106725 4967 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto 122:f9eeca106725 4968 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
Kojto 122:f9eeca106725 4969 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
bogdanm 92:4fc01daae5a5 4970
bogdanm 92:4fc01daae5a5 4971 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 122:f9eeca106725 4972 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
Kojto 122:f9eeca106725 4973 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
bogdanm 92:4fc01daae5a5 4974
bogdanm 92:4fc01daae5a5 4975 /******************** Bit definition for RCC_AHB3LPENR register *************/
bogdanm 92:4fc01daae5a5 4976
Kojto 122:f9eeca106725 4977 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
bogdanm 92:4fc01daae5a5 4978
bogdanm 92:4fc01daae5a5 4979 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 122:f9eeca106725 4980 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto 122:f9eeca106725 4981 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto 122:f9eeca106725 4982 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto 122:f9eeca106725 4983 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto 122:f9eeca106725 4984 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
Kojto 122:f9eeca106725 4985 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
Kojto 122:f9eeca106725 4986 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
Kojto 122:f9eeca106725 4987 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
Kojto 122:f9eeca106725 4988 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
Kojto 122:f9eeca106725 4989 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto 122:f9eeca106725 4990 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto 122:f9eeca106725 4991 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto 122:f9eeca106725 4992 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto 122:f9eeca106725 4993 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
Kojto 122:f9eeca106725 4994 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
Kojto 122:f9eeca106725 4995 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
Kojto 122:f9eeca106725 4996 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto 122:f9eeca106725 4997 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto 122:f9eeca106725 4998 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto 122:f9eeca106725 4999 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
Kojto 122:f9eeca106725 5000 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
Kojto 122:f9eeca106725 5001 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto 122:f9eeca106725 5002 #define RCC_APB1LPENR_DACLPEN 0x20000000U
bogdanm 92:4fc01daae5a5 5003
bogdanm 92:4fc01daae5a5 5004 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 122:f9eeca106725 5005 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto 122:f9eeca106725 5006 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
Kojto 122:f9eeca106725 5007 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto 122:f9eeca106725 5008 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto 122:f9eeca106725 5009 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto 122:f9eeca106725 5010 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
Kojto 122:f9eeca106725 5011 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
Kojto 122:f9eeca106725 5012 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
Kojto 122:f9eeca106725 5013 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto 122:f9eeca106725 5014 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto 122:f9eeca106725 5015 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto 122:f9eeca106725 5016 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto 122:f9eeca106725 5017 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
bogdanm 92:4fc01daae5a5 5018
bogdanm 92:4fc01daae5a5 5019 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 5020 #define RCC_BDCR_LSEON 0x00000001U
Kojto 122:f9eeca106725 5021 #define RCC_BDCR_LSERDY 0x00000002U
Kojto 122:f9eeca106725 5022 #define RCC_BDCR_LSEBYP 0x00000004U
Kojto 122:f9eeca106725 5023
Kojto 122:f9eeca106725 5024 #define RCC_BDCR_RTCSEL 0x00000300U
Kojto 122:f9eeca106725 5025 #define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto 122:f9eeca106725 5026 #define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto 122:f9eeca106725 5027
Kojto 122:f9eeca106725 5028 #define RCC_BDCR_RTCEN 0x00008000U
Kojto 122:f9eeca106725 5029 #define RCC_BDCR_BDRST 0x00010000U
bogdanm 92:4fc01daae5a5 5030
bogdanm 92:4fc01daae5a5 5031 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 5032 #define RCC_CSR_LSION 0x00000001U
Kojto 122:f9eeca106725 5033 #define RCC_CSR_LSIRDY 0x00000002U
Kojto 122:f9eeca106725 5034 #define RCC_CSR_RMVF 0x01000000U
Kojto 122:f9eeca106725 5035 #define RCC_CSR_BORRSTF 0x02000000U
Kojto 122:f9eeca106725 5036 #define RCC_CSR_PADRSTF 0x04000000U
Kojto 122:f9eeca106725 5037 #define RCC_CSR_PORRSTF 0x08000000U
Kojto 122:f9eeca106725 5038 #define RCC_CSR_SFTRSTF 0x10000000U
Kojto 122:f9eeca106725 5039 #define RCC_CSR_WDGRSTF 0x20000000U
Kojto 122:f9eeca106725 5040 #define RCC_CSR_WWDGRSTF 0x40000000U
Kojto 122:f9eeca106725 5041 #define RCC_CSR_LPWRRSTF 0x80000000U
bogdanm 92:4fc01daae5a5 5042
bogdanm 92:4fc01daae5a5 5043 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 122:f9eeca106725 5044 #define RCC_SSCGR_MODPER 0x00001FFFU
Kojto 122:f9eeca106725 5045 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto 122:f9eeca106725 5046 #define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto 122:f9eeca106725 5047 #define RCC_SSCGR_SSCGEN 0x80000000U
bogdanm 92:4fc01daae5a5 5048
bogdanm 92:4fc01daae5a5 5049 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 122:f9eeca106725 5050 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto 122:f9eeca106725 5051 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto 122:f9eeca106725 5052 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto 122:f9eeca106725 5053 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto 122:f9eeca106725 5054 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto 122:f9eeca106725 5055 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto 122:f9eeca106725 5056 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto 122:f9eeca106725 5057 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto 122:f9eeca106725 5058 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto 122:f9eeca106725 5059 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto 122:f9eeca106725 5060
Kojto 122:f9eeca106725 5061 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto 122:f9eeca106725 5062 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto 122:f9eeca106725 5063 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto 122:f9eeca106725 5064 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
bogdanm 92:4fc01daae5a5 5065
bogdanm 92:4fc01daae5a5 5066 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5067 /* */
bogdanm 92:4fc01daae5a5 5068 /* RNG */
bogdanm 92:4fc01daae5a5 5069 /* */
bogdanm 92:4fc01daae5a5 5070 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5071 /******************** Bits definition for RNG_CR register *******************/
Kojto 122:f9eeca106725 5072 #define RNG_CR_RNGEN 0x00000004U
Kojto 122:f9eeca106725 5073 #define RNG_CR_IE 0x00000008U
bogdanm 92:4fc01daae5a5 5074
bogdanm 92:4fc01daae5a5 5075 /******************** Bits definition for RNG_SR register *******************/
Kojto 122:f9eeca106725 5076 #define RNG_SR_DRDY 0x00000001U
Kojto 122:f9eeca106725 5077 #define RNG_SR_CECS 0x00000002U
Kojto 122:f9eeca106725 5078 #define RNG_SR_SECS 0x00000004U
Kojto 122:f9eeca106725 5079 #define RNG_SR_CEIS 0x00000020U
Kojto 122:f9eeca106725 5080 #define RNG_SR_SEIS 0x00000040U
bogdanm 92:4fc01daae5a5 5081
bogdanm 92:4fc01daae5a5 5082 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5083 /* */
bogdanm 92:4fc01daae5a5 5084 /* Real-Time Clock (RTC) */
bogdanm 92:4fc01daae5a5 5085 /* */
bogdanm 92:4fc01daae5a5 5086 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5087 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 5088 #define RTC_TR_PM 0x00400000U
Kojto 122:f9eeca106725 5089 #define RTC_TR_HT 0x00300000U
Kojto 122:f9eeca106725 5090 #define RTC_TR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5091 #define RTC_TR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5092 #define RTC_TR_HU 0x000F0000U
Kojto 122:f9eeca106725 5093 #define RTC_TR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5094 #define RTC_TR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5095 #define RTC_TR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5096 #define RTC_TR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5097 #define RTC_TR_MNT 0x00007000U
Kojto 122:f9eeca106725 5098 #define RTC_TR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5099 #define RTC_TR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5100 #define RTC_TR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5101 #define RTC_TR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5102 #define RTC_TR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5103 #define RTC_TR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5104 #define RTC_TR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5105 #define RTC_TR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5106 #define RTC_TR_ST 0x00000070U
Kojto 122:f9eeca106725 5107 #define RTC_TR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5108 #define RTC_TR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5109 #define RTC_TR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5110 #define RTC_TR_SU 0x0000000FU
Kojto 122:f9eeca106725 5111 #define RTC_TR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5112 #define RTC_TR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5113 #define RTC_TR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5114 #define RTC_TR_SU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5115
bogdanm 92:4fc01daae5a5 5116 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 5117 #define RTC_DR_YT 0x00F00000U
Kojto 122:f9eeca106725 5118 #define RTC_DR_YT_0 0x00100000U
Kojto 122:f9eeca106725 5119 #define RTC_DR_YT_1 0x00200000U
Kojto 122:f9eeca106725 5120 #define RTC_DR_YT_2 0x00400000U
Kojto 122:f9eeca106725 5121 #define RTC_DR_YT_3 0x00800000U
Kojto 122:f9eeca106725 5122 #define RTC_DR_YU 0x000F0000U
Kojto 122:f9eeca106725 5123 #define RTC_DR_YU_0 0x00010000U
Kojto 122:f9eeca106725 5124 #define RTC_DR_YU_1 0x00020000U
Kojto 122:f9eeca106725 5125 #define RTC_DR_YU_2 0x00040000U
Kojto 122:f9eeca106725 5126 #define RTC_DR_YU_3 0x00080000U
Kojto 122:f9eeca106725 5127 #define RTC_DR_WDU 0x0000E000U
Kojto 122:f9eeca106725 5128 #define RTC_DR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 5129 #define RTC_DR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 5130 #define RTC_DR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 5131 #define RTC_DR_MT 0x00001000U
Kojto 122:f9eeca106725 5132 #define RTC_DR_MU 0x00000F00U
Kojto 122:f9eeca106725 5133 #define RTC_DR_MU_0 0x00000100U
Kojto 122:f9eeca106725 5134 #define RTC_DR_MU_1 0x00000200U
Kojto 122:f9eeca106725 5135 #define RTC_DR_MU_2 0x00000400U
Kojto 122:f9eeca106725 5136 #define RTC_DR_MU_3 0x00000800U
Kojto 122:f9eeca106725 5137 #define RTC_DR_DT 0x00000030U
Kojto 122:f9eeca106725 5138 #define RTC_DR_DT_0 0x00000010U
Kojto 122:f9eeca106725 5139 #define RTC_DR_DT_1 0x00000020U
Kojto 122:f9eeca106725 5140 #define RTC_DR_DU 0x0000000FU
Kojto 122:f9eeca106725 5141 #define RTC_DR_DU_0 0x00000001U
Kojto 122:f9eeca106725 5142 #define RTC_DR_DU_1 0x00000002U
Kojto 122:f9eeca106725 5143 #define RTC_DR_DU_2 0x00000004U
Kojto 122:f9eeca106725 5144 #define RTC_DR_DU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5145
bogdanm 92:4fc01daae5a5 5146 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 5147 #define RTC_CR_COE 0x00800000U
Kojto 122:f9eeca106725 5148 #define RTC_CR_OSEL 0x00600000U
Kojto 122:f9eeca106725 5149 #define RTC_CR_OSEL_0 0x00200000U
Kojto 122:f9eeca106725 5150 #define RTC_CR_OSEL_1 0x00400000U
Kojto 122:f9eeca106725 5151 #define RTC_CR_POL 0x00100000U
Kojto 122:f9eeca106725 5152 #define RTC_CR_COSEL 0x00080000U
Kojto 122:f9eeca106725 5153 #define RTC_CR_BCK 0x00040000U
Kojto 122:f9eeca106725 5154 #define RTC_CR_SUB1H 0x00020000U
Kojto 122:f9eeca106725 5155 #define RTC_CR_ADD1H 0x00010000U
Kojto 122:f9eeca106725 5156 #define RTC_CR_TSIE 0x00008000U
Kojto 122:f9eeca106725 5157 #define RTC_CR_WUTIE 0x00004000U
Kojto 122:f9eeca106725 5158 #define RTC_CR_ALRBIE 0x00002000U
Kojto 122:f9eeca106725 5159 #define RTC_CR_ALRAIE 0x00001000U
Kojto 122:f9eeca106725 5160 #define RTC_CR_TSE 0x00000800U
Kojto 122:f9eeca106725 5161 #define RTC_CR_WUTE 0x00000400U
Kojto 122:f9eeca106725 5162 #define RTC_CR_ALRBE 0x00000200U
Kojto 122:f9eeca106725 5163 #define RTC_CR_ALRAE 0x00000100U
Kojto 122:f9eeca106725 5164 #define RTC_CR_DCE 0x00000080U
Kojto 122:f9eeca106725 5165 #define RTC_CR_FMT 0x00000040U
Kojto 122:f9eeca106725 5166 #define RTC_CR_BYPSHAD 0x00000020U
Kojto 122:f9eeca106725 5167 #define RTC_CR_REFCKON 0x00000010U
Kojto 122:f9eeca106725 5168 #define RTC_CR_TSEDGE 0x00000008U
Kojto 122:f9eeca106725 5169 #define RTC_CR_WUCKSEL 0x00000007U
Kojto 122:f9eeca106725 5170 #define RTC_CR_WUCKSEL_0 0x00000001U
Kojto 122:f9eeca106725 5171 #define RTC_CR_WUCKSEL_1 0x00000002U
Kojto 122:f9eeca106725 5172 #define RTC_CR_WUCKSEL_2 0x00000004U
bogdanm 92:4fc01daae5a5 5173
bogdanm 92:4fc01daae5a5 5174 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 5175 #define RTC_ISR_RECALPF 0x00010000U
Kojto 122:f9eeca106725 5176 #define RTC_ISR_TAMP1F 0x00002000U
Kojto 122:f9eeca106725 5177 #define RTC_ISR_TAMP2F 0x00004000U
Kojto 122:f9eeca106725 5178 #define RTC_ISR_TSOVF 0x00001000U
Kojto 122:f9eeca106725 5179 #define RTC_ISR_TSF 0x00000800U
Kojto 122:f9eeca106725 5180 #define RTC_ISR_WUTF 0x00000400U
Kojto 122:f9eeca106725 5181 #define RTC_ISR_ALRBF 0x00000200U
Kojto 122:f9eeca106725 5182 #define RTC_ISR_ALRAF 0x00000100U
Kojto 122:f9eeca106725 5183 #define RTC_ISR_INIT 0x00000080U
Kojto 122:f9eeca106725 5184 #define RTC_ISR_INITF 0x00000040U
Kojto 122:f9eeca106725 5185 #define RTC_ISR_RSF 0x00000020U
Kojto 122:f9eeca106725 5186 #define RTC_ISR_INITS 0x00000010U
Kojto 122:f9eeca106725 5187 #define RTC_ISR_SHPF 0x00000008U
Kojto 122:f9eeca106725 5188 #define RTC_ISR_WUTWF 0x00000004U
Kojto 122:f9eeca106725 5189 #define RTC_ISR_ALRBWF 0x00000002U
Kojto 122:f9eeca106725 5190 #define RTC_ISR_ALRAWF 0x00000001U
bogdanm 92:4fc01daae5a5 5191
bogdanm 92:4fc01daae5a5 5192 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 5193 #define RTC_PRER_PREDIV_A 0x007F0000U
Kojto 122:f9eeca106725 5194 #define RTC_PRER_PREDIV_S 0x00007FFFU
bogdanm 92:4fc01daae5a5 5195
bogdanm 92:4fc01daae5a5 5196 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 5197 #define RTC_WUTR_WUT 0x0000FFFFU
bogdanm 92:4fc01daae5a5 5198
bogdanm 92:4fc01daae5a5 5199 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 122:f9eeca106725 5200 #define RTC_CALIBR_DCS 0x00000080U
Kojto 122:f9eeca106725 5201 #define RTC_CALIBR_DC 0x0000001FU
bogdanm 92:4fc01daae5a5 5202
bogdanm 92:4fc01daae5a5 5203 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 5204 #define RTC_ALRMAR_MSK4 0x80000000U
Kojto 122:f9eeca106725 5205 #define RTC_ALRMAR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 5206 #define RTC_ALRMAR_DT 0x30000000U
Kojto 122:f9eeca106725 5207 #define RTC_ALRMAR_DT_0 0x10000000U
Kojto 122:f9eeca106725 5208 #define RTC_ALRMAR_DT_1 0x20000000U
Kojto 122:f9eeca106725 5209 #define RTC_ALRMAR_DU 0x0F000000U
Kojto 122:f9eeca106725 5210 #define RTC_ALRMAR_DU_0 0x01000000U
Kojto 122:f9eeca106725 5211 #define RTC_ALRMAR_DU_1 0x02000000U
Kojto 122:f9eeca106725 5212 #define RTC_ALRMAR_DU_2 0x04000000U
Kojto 122:f9eeca106725 5213 #define RTC_ALRMAR_DU_3 0x08000000U
Kojto 122:f9eeca106725 5214 #define RTC_ALRMAR_MSK3 0x00800000U
Kojto 122:f9eeca106725 5215 #define RTC_ALRMAR_PM 0x00400000U
Kojto 122:f9eeca106725 5216 #define RTC_ALRMAR_HT 0x00300000U
Kojto 122:f9eeca106725 5217 #define RTC_ALRMAR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5218 #define RTC_ALRMAR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5219 #define RTC_ALRMAR_HU 0x000F0000U
Kojto 122:f9eeca106725 5220 #define RTC_ALRMAR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5221 #define RTC_ALRMAR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5222 #define RTC_ALRMAR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5223 #define RTC_ALRMAR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5224 #define RTC_ALRMAR_MSK2 0x00008000U
Kojto 122:f9eeca106725 5225 #define RTC_ALRMAR_MNT 0x00007000U
Kojto 122:f9eeca106725 5226 #define RTC_ALRMAR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5227 #define RTC_ALRMAR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5228 #define RTC_ALRMAR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5229 #define RTC_ALRMAR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5230 #define RTC_ALRMAR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5231 #define RTC_ALRMAR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5232 #define RTC_ALRMAR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5233 #define RTC_ALRMAR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5234 #define RTC_ALRMAR_MSK1 0x00000080U
Kojto 122:f9eeca106725 5235 #define RTC_ALRMAR_ST 0x00000070U
Kojto 122:f9eeca106725 5236 #define RTC_ALRMAR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5237 #define RTC_ALRMAR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5238 #define RTC_ALRMAR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5239 #define RTC_ALRMAR_SU 0x0000000FU
Kojto 122:f9eeca106725 5240 #define RTC_ALRMAR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5241 #define RTC_ALRMAR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5242 #define RTC_ALRMAR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5243 #define RTC_ALRMAR_SU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5244
bogdanm 92:4fc01daae5a5 5245 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 5246 #define RTC_ALRMBR_MSK4 0x80000000U
Kojto 122:f9eeca106725 5247 #define RTC_ALRMBR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 5248 #define RTC_ALRMBR_DT 0x30000000U
Kojto 122:f9eeca106725 5249 #define RTC_ALRMBR_DT_0 0x10000000U
Kojto 122:f9eeca106725 5250 #define RTC_ALRMBR_DT_1 0x20000000U
Kojto 122:f9eeca106725 5251 #define RTC_ALRMBR_DU 0x0F000000U
Kojto 122:f9eeca106725 5252 #define RTC_ALRMBR_DU_0 0x01000000U
Kojto 122:f9eeca106725 5253 #define RTC_ALRMBR_DU_1 0x02000000U
Kojto 122:f9eeca106725 5254 #define RTC_ALRMBR_DU_2 0x04000000U
Kojto 122:f9eeca106725 5255 #define RTC_ALRMBR_DU_3 0x08000000U
Kojto 122:f9eeca106725 5256 #define RTC_ALRMBR_MSK3 0x00800000U
Kojto 122:f9eeca106725 5257 #define RTC_ALRMBR_PM 0x00400000U
Kojto 122:f9eeca106725 5258 #define RTC_ALRMBR_HT 0x00300000U
Kojto 122:f9eeca106725 5259 #define RTC_ALRMBR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5260 #define RTC_ALRMBR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5261 #define RTC_ALRMBR_HU 0x000F0000U
Kojto 122:f9eeca106725 5262 #define RTC_ALRMBR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5263 #define RTC_ALRMBR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5264 #define RTC_ALRMBR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5265 #define RTC_ALRMBR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5266 #define RTC_ALRMBR_MSK2 0x00008000U
Kojto 122:f9eeca106725 5267 #define RTC_ALRMBR_MNT 0x00007000U
Kojto 122:f9eeca106725 5268 #define RTC_ALRMBR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5269 #define RTC_ALRMBR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5270 #define RTC_ALRMBR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5271 #define RTC_ALRMBR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5272 #define RTC_ALRMBR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5273 #define RTC_ALRMBR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5274 #define RTC_ALRMBR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5275 #define RTC_ALRMBR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5276 #define RTC_ALRMBR_MSK1 0x00000080U
Kojto 122:f9eeca106725 5277 #define RTC_ALRMBR_ST 0x00000070U
Kojto 122:f9eeca106725 5278 #define RTC_ALRMBR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5279 #define RTC_ALRMBR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5280 #define RTC_ALRMBR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5281 #define RTC_ALRMBR_SU 0x0000000FU
Kojto 122:f9eeca106725 5282 #define RTC_ALRMBR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5283 #define RTC_ALRMBR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5284 #define RTC_ALRMBR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5285 #define RTC_ALRMBR_SU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5286
bogdanm 92:4fc01daae5a5 5287 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 5288 #define RTC_WPR_KEY 0x000000FFU
bogdanm 92:4fc01daae5a5 5289
bogdanm 92:4fc01daae5a5 5290 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 5291 #define RTC_SSR_SS 0x0000FFFFU
bogdanm 92:4fc01daae5a5 5292
bogdanm 92:4fc01daae5a5 5293 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 5294 #define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto 122:f9eeca106725 5295 #define RTC_SHIFTR_ADD1S 0x80000000U
bogdanm 92:4fc01daae5a5 5296
bogdanm 92:4fc01daae5a5 5297 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 5298 #define RTC_TSTR_PM 0x00400000U
Kojto 122:f9eeca106725 5299 #define RTC_TSTR_HT 0x00300000U
Kojto 122:f9eeca106725 5300 #define RTC_TSTR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5301 #define RTC_TSTR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5302 #define RTC_TSTR_HU 0x000F0000U
Kojto 122:f9eeca106725 5303 #define RTC_TSTR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5304 #define RTC_TSTR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5305 #define RTC_TSTR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5306 #define RTC_TSTR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5307 #define RTC_TSTR_MNT 0x00007000U
Kojto 122:f9eeca106725 5308 #define RTC_TSTR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5309 #define RTC_TSTR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5310 #define RTC_TSTR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5311 #define RTC_TSTR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5312 #define RTC_TSTR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5313 #define RTC_TSTR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5314 #define RTC_TSTR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5315 #define RTC_TSTR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5316 #define RTC_TSTR_ST 0x00000070U
Kojto 122:f9eeca106725 5317 #define RTC_TSTR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5318 #define RTC_TSTR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5319 #define RTC_TSTR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5320 #define RTC_TSTR_SU 0x0000000FU
Kojto 122:f9eeca106725 5321 #define RTC_TSTR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5322 #define RTC_TSTR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5323 #define RTC_TSTR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5324 #define RTC_TSTR_SU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5325
bogdanm 92:4fc01daae5a5 5326 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 5327 #define RTC_TSDR_WDU 0x0000E000U
Kojto 122:f9eeca106725 5328 #define RTC_TSDR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 5329 #define RTC_TSDR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 5330 #define RTC_TSDR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 5331 #define RTC_TSDR_MT 0x00001000U
Kojto 122:f9eeca106725 5332 #define RTC_TSDR_MU 0x00000F00U
Kojto 122:f9eeca106725 5333 #define RTC_TSDR_MU_0 0x00000100U
Kojto 122:f9eeca106725 5334 #define RTC_TSDR_MU_1 0x00000200U
Kojto 122:f9eeca106725 5335 #define RTC_TSDR_MU_2 0x00000400U
Kojto 122:f9eeca106725 5336 #define RTC_TSDR_MU_3 0x00000800U
Kojto 122:f9eeca106725 5337 #define RTC_TSDR_DT 0x00000030U
Kojto 122:f9eeca106725 5338 #define RTC_TSDR_DT_0 0x00000010U
Kojto 122:f9eeca106725 5339 #define RTC_TSDR_DT_1 0x00000020U
Kojto 122:f9eeca106725 5340 #define RTC_TSDR_DU 0x0000000FU
Kojto 122:f9eeca106725 5341 #define RTC_TSDR_DU_0 0x00000001U
Kojto 122:f9eeca106725 5342 #define RTC_TSDR_DU_1 0x00000002U
Kojto 122:f9eeca106725 5343 #define RTC_TSDR_DU_2 0x00000004U
Kojto 122:f9eeca106725 5344 #define RTC_TSDR_DU_3 0x00000008U
bogdanm 92:4fc01daae5a5 5345
bogdanm 92:4fc01daae5a5 5346 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 5347 #define RTC_TSSSR_SS 0x0000FFFFU
bogdanm 92:4fc01daae5a5 5348
bogdanm 92:4fc01daae5a5 5349 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 5350 #define RTC_CALR_CALP 0x00008000U
Kojto 122:f9eeca106725 5351 #define RTC_CALR_CALW8 0x00004000U
Kojto 122:f9eeca106725 5352 #define RTC_CALR_CALW16 0x00002000U
Kojto 122:f9eeca106725 5353 #define RTC_CALR_CALM 0x000001FFU
Kojto 122:f9eeca106725 5354 #define RTC_CALR_CALM_0 0x00000001U
Kojto 122:f9eeca106725 5355 #define RTC_CALR_CALM_1 0x00000002U
Kojto 122:f9eeca106725 5356 #define RTC_CALR_CALM_2 0x00000004U
Kojto 122:f9eeca106725 5357 #define RTC_CALR_CALM_3 0x00000008U
Kojto 122:f9eeca106725 5358 #define RTC_CALR_CALM_4 0x00000010U
Kojto 122:f9eeca106725 5359 #define RTC_CALR_CALM_5 0x00000020U
Kojto 122:f9eeca106725 5360 #define RTC_CALR_CALM_6 0x00000040U
Kojto 122:f9eeca106725 5361 #define RTC_CALR_CALM_7 0x00000080U
Kojto 122:f9eeca106725 5362 #define RTC_CALR_CALM_8 0x00000100U
bogdanm 92:4fc01daae5a5 5363
bogdanm 92:4fc01daae5a5 5364 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 122:f9eeca106725 5365 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
Kojto 122:f9eeca106725 5366 #define RTC_TAFCR_TSINSEL 0x00020000U
Kojto 122:f9eeca106725 5367 #define RTC_TAFCR_TAMPINSEL 0x00010000U
Kojto 122:f9eeca106725 5368 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
Kojto 122:f9eeca106725 5369 #define RTC_TAFCR_TAMPPRCH 0x00006000U
Kojto 122:f9eeca106725 5370 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
Kojto 122:f9eeca106725 5371 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
Kojto 122:f9eeca106725 5372 #define RTC_TAFCR_TAMPFLT 0x00001800U
Kojto 122:f9eeca106725 5373 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
Kojto 122:f9eeca106725 5374 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
Kojto 122:f9eeca106725 5375 #define RTC_TAFCR_TAMPFREQ 0x00000700U
Kojto 122:f9eeca106725 5376 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
Kojto 122:f9eeca106725 5377 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
Kojto 122:f9eeca106725 5378 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
Kojto 122:f9eeca106725 5379 #define RTC_TAFCR_TAMPTS 0x00000080U
Kojto 122:f9eeca106725 5380 #define RTC_TAFCR_TAMP2TRG 0x00000010U
Kojto 122:f9eeca106725 5381 #define RTC_TAFCR_TAMP2E 0x00000008U
Kojto 122:f9eeca106725 5382 #define RTC_TAFCR_TAMPIE 0x00000004U
Kojto 122:f9eeca106725 5383 #define RTC_TAFCR_TAMP1TRG 0x00000002U
Kojto 122:f9eeca106725 5384 #define RTC_TAFCR_TAMP1E 0x00000001U
bogdanm 92:4fc01daae5a5 5385
bogdanm 92:4fc01daae5a5 5386 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 5387 #define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 5388 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 5389 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 5390 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 5391 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 5392 #define RTC_ALRMASSR_SS 0x00007FFFU
bogdanm 92:4fc01daae5a5 5393
bogdanm 92:4fc01daae5a5 5394 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 5395 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 5396 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 5397 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 5398 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 5399 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 5400 #define RTC_ALRMBSSR_SS 0x00007FFFU
bogdanm 92:4fc01daae5a5 5401
bogdanm 92:4fc01daae5a5 5402 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 5403 #define RTC_BKP0R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5404
bogdanm 92:4fc01daae5a5 5405 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 5406 #define RTC_BKP1R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5407
bogdanm 92:4fc01daae5a5 5408 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 5409 #define RTC_BKP2R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5410
bogdanm 92:4fc01daae5a5 5411 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 5412 #define RTC_BKP3R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5413
bogdanm 92:4fc01daae5a5 5414 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 5415 #define RTC_BKP4R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5416
bogdanm 92:4fc01daae5a5 5417 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 5418 #define RTC_BKP5R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5419
bogdanm 92:4fc01daae5a5 5420 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 5421 #define RTC_BKP6R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5422
bogdanm 92:4fc01daae5a5 5423 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 5424 #define RTC_BKP7R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5425
bogdanm 92:4fc01daae5a5 5426 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 5427 #define RTC_BKP8R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5428
bogdanm 92:4fc01daae5a5 5429 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 5430 #define RTC_BKP9R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5431
bogdanm 92:4fc01daae5a5 5432 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 5433 #define RTC_BKP10R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5434
bogdanm 92:4fc01daae5a5 5435 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 5436 #define RTC_BKP11R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5437
bogdanm 92:4fc01daae5a5 5438 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 5439 #define RTC_BKP12R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5440
bogdanm 92:4fc01daae5a5 5441 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 5442 #define RTC_BKP13R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5443
bogdanm 92:4fc01daae5a5 5444 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 5445 #define RTC_BKP14R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5446
bogdanm 92:4fc01daae5a5 5447 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 5448 #define RTC_BKP15R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5449
bogdanm 92:4fc01daae5a5 5450 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 5451 #define RTC_BKP16R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5452
bogdanm 92:4fc01daae5a5 5453 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 5454 #define RTC_BKP17R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5455
bogdanm 92:4fc01daae5a5 5456 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 5457 #define RTC_BKP18R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5458
bogdanm 92:4fc01daae5a5 5459 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 5460 #define RTC_BKP19R 0xFFFFFFFFU
bogdanm 92:4fc01daae5a5 5461
bogdanm 92:4fc01daae5a5 5462
bogdanm 92:4fc01daae5a5 5463
bogdanm 92:4fc01daae5a5 5464 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5465 /* */
bogdanm 92:4fc01daae5a5 5466 /* SD host Interface */
bogdanm 92:4fc01daae5a5 5467 /* */
bogdanm 92:4fc01daae5a5 5468 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5469 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 122:f9eeca106725 5470 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 122:f9eeca106725 5471 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 5472 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5473
bogdanm 92:4fc01daae5a5 5474 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 122:f9eeca106725 5475 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
Kojto 122:f9eeca106725 5476 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
Kojto 122:f9eeca106725 5477 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
Kojto 122:f9eeca106725 5478 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
Kojto 122:f9eeca106725 5479
Kojto 122:f9eeca106725 5480 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 122:f9eeca106725 5481 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
Kojto 122:f9eeca106725 5482 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
Kojto 122:f9eeca106725 5483
Kojto 122:f9eeca106725 5484 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
Kojto 122:f9eeca106725 5485 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
bogdanm 92:4fc01daae5a5 5486
bogdanm 92:4fc01daae5a5 5487 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 122:f9eeca106725 5488 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
bogdanm 92:4fc01daae5a5 5489
bogdanm 92:4fc01daae5a5 5490 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 122:f9eeca106725 5491 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
Kojto 122:f9eeca106725 5492
Kojto 122:f9eeca106725 5493 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 122:f9eeca106725 5494 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
Kojto 122:f9eeca106725 5495 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
Kojto 122:f9eeca106725 5496
Kojto 122:f9eeca106725 5497 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
Kojto 122:f9eeca106725 5498 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 122:f9eeca106725 5499 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
Kojto 122:f9eeca106725 5500 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
Kojto 122:f9eeca106725 5501 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
Kojto 122:f9eeca106725 5502 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
Kojto 122:f9eeca106725 5503 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
bogdanm 92:4fc01daae5a5 5504
bogdanm 92:4fc01daae5a5 5505 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 122:f9eeca106725 5506 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
bogdanm 92:4fc01daae5a5 5507
bogdanm 92:4fc01daae5a5 5508 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 122:f9eeca106725 5509 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
bogdanm 92:4fc01daae5a5 5510
bogdanm 92:4fc01daae5a5 5511 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 122:f9eeca106725 5512 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
bogdanm 92:4fc01daae5a5 5513
bogdanm 92:4fc01daae5a5 5514 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 122:f9eeca106725 5515 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
bogdanm 92:4fc01daae5a5 5516
bogdanm 92:4fc01daae5a5 5517 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 122:f9eeca106725 5518 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
bogdanm 92:4fc01daae5a5 5519
bogdanm 92:4fc01daae5a5 5520 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 122:f9eeca106725 5521 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
bogdanm 92:4fc01daae5a5 5522
bogdanm 92:4fc01daae5a5 5523 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 122:f9eeca106725 5524 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
bogdanm 92:4fc01daae5a5 5525
bogdanm 92:4fc01daae5a5 5526 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 122:f9eeca106725 5527 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
bogdanm 92:4fc01daae5a5 5528
bogdanm 92:4fc01daae5a5 5529 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 122:f9eeca106725 5530 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
Kojto 122:f9eeca106725 5531 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
Kojto 122:f9eeca106725 5532 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
Kojto 122:f9eeca106725 5533 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
Kojto 122:f9eeca106725 5534
Kojto 122:f9eeca106725 5535 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 122:f9eeca106725 5536 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 5537 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 5538 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 5539 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 5540
Kojto 122:f9eeca106725 5541 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
Kojto 122:f9eeca106725 5542 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
Kojto 122:f9eeca106725 5543 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
Kojto 122:f9eeca106725 5544 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
bogdanm 92:4fc01daae5a5 5545
bogdanm 92:4fc01daae5a5 5546 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 122:f9eeca106725 5547 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
bogdanm 92:4fc01daae5a5 5548
bogdanm 92:4fc01daae5a5 5549 /****************** Bit definition for SDIO_STA register ********************/
Kojto 122:f9eeca106725 5550 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
Kojto 122:f9eeca106725 5551 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
Kojto 122:f9eeca106725 5552 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
Kojto 122:f9eeca106725 5553 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
Kojto 122:f9eeca106725 5554 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
Kojto 122:f9eeca106725 5555 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
Kojto 122:f9eeca106725 5556 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
Kojto 122:f9eeca106725 5557 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
Kojto 122:f9eeca106725 5558 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 122:f9eeca106725 5559 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
Kojto 122:f9eeca106725 5560 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
Kojto 122:f9eeca106725 5561 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
Kojto 122:f9eeca106725 5562 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
Kojto 122:f9eeca106725 5563 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
Kojto 122:f9eeca106725 5564 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 122:f9eeca106725 5565 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 122:f9eeca106725 5566 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
Kojto 122:f9eeca106725 5567 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
Kojto 122:f9eeca106725 5568 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
Kojto 122:f9eeca106725 5569 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
Kojto 122:f9eeca106725 5570 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
Kojto 122:f9eeca106725 5571 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
Kojto 122:f9eeca106725 5572 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
Kojto 122:f9eeca106725 5573 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
bogdanm 92:4fc01daae5a5 5574
bogdanm 92:4fc01daae5a5 5575 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 122:f9eeca106725 5576 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 5577 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 5578 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 5579 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 5580 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
Kojto 122:f9eeca106725 5581 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
Kojto 122:f9eeca106725 5582 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
Kojto 122:f9eeca106725 5583 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
Kojto 122:f9eeca106725 5584 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
Kojto 122:f9eeca106725 5585 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
Kojto 122:f9eeca106725 5586 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
Kojto 122:f9eeca106725 5587 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
Kojto 122:f9eeca106725 5588 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
bogdanm 92:4fc01daae5a5 5589
bogdanm 92:4fc01daae5a5 5590 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 122:f9eeca106725 5591 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 5592 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 5593 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 5594 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 5595 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 122:f9eeca106725 5596 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 122:f9eeca106725 5597 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
Kojto 122:f9eeca106725 5598 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
Kojto 122:f9eeca106725 5599 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
Kojto 122:f9eeca106725 5600 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
Kojto 122:f9eeca106725 5601 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
Kojto 122:f9eeca106725 5602 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
Kojto 122:f9eeca106725 5603 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
Kojto 122:f9eeca106725 5604 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
Kojto 122:f9eeca106725 5605 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 122:f9eeca106725 5606 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
Kojto 122:f9eeca106725 5607 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 5608 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 5609 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 5610 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 5611 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
Kojto 122:f9eeca106725 5612 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
Kojto 122:f9eeca106725 5613 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 122:f9eeca106725 5614 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
bogdanm 92:4fc01daae5a5 5615
bogdanm 92:4fc01daae5a5 5616 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 122:f9eeca106725 5617 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
bogdanm 92:4fc01daae5a5 5618
bogdanm 92:4fc01daae5a5 5619 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 122:f9eeca106725 5620 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
bogdanm 92:4fc01daae5a5 5621
bogdanm 92:4fc01daae5a5 5622 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5623 /* */
bogdanm 92:4fc01daae5a5 5624 /* Serial Peripheral Interface */
bogdanm 92:4fc01daae5a5 5625 /* */
bogdanm 92:4fc01daae5a5 5626 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5627 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 5628 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
Kojto 122:f9eeca106725 5629 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
Kojto 122:f9eeca106725 5630 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
Kojto 122:f9eeca106725 5631
Kojto 122:f9eeca106725 5632 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 5633 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 5634 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 5635 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 5636
Kojto 122:f9eeca106725 5637 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
Kojto 122:f9eeca106725 5638 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
Kojto 122:f9eeca106725 5639 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
Kojto 122:f9eeca106725 5640 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
Kojto 122:f9eeca106725 5641 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
Kojto 122:f9eeca106725 5642 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
Kojto 122:f9eeca106725 5643 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
Kojto 122:f9eeca106725 5644 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
Kojto 122:f9eeca106725 5645 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
Kojto 122:f9eeca106725 5646 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
bogdanm 92:4fc01daae5a5 5647
bogdanm 92:4fc01daae5a5 5648 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 5649 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 5650 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 5651 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
Kojto 122:f9eeca106725 5652 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
Kojto 122:f9eeca106725 5653 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 5654 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 5655 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
bogdanm 92:4fc01daae5a5 5656
bogdanm 92:4fc01daae5a5 5657 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 5658 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
Kojto 122:f9eeca106725 5659 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
Kojto 122:f9eeca106725 5660 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
Kojto 122:f9eeca106725 5661 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
Kojto 122:f9eeca106725 5662 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
Kojto 122:f9eeca106725 5663 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
Kojto 122:f9eeca106725 5664 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
Kojto 122:f9eeca106725 5665 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
Kojto 122:f9eeca106725 5666 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
bogdanm 92:4fc01daae5a5 5667
bogdanm 92:4fc01daae5a5 5668 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 5669 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
bogdanm 92:4fc01daae5a5 5670
bogdanm 92:4fc01daae5a5 5671 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 5672 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
bogdanm 92:4fc01daae5a5 5673
bogdanm 92:4fc01daae5a5 5674 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 5675 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
bogdanm 92:4fc01daae5a5 5676
bogdanm 92:4fc01daae5a5 5677 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 5678 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
bogdanm 92:4fc01daae5a5 5679
bogdanm 92:4fc01daae5a5 5680 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 122:f9eeca106725 5681 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 5682
Kojto 122:f9eeca106725 5683 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 5684 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 5685 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 5686
Kojto 122:f9eeca106725 5687 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
Kojto 122:f9eeca106725 5688
Kojto 122:f9eeca106725 5689 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 5690 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 5691 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 5692
Kojto 122:f9eeca106725 5693 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 5694
Kojto 122:f9eeca106725 5695 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 5696 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 5697 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 5698
Kojto 122:f9eeca106725 5699 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
Kojto 122:f9eeca106725 5700 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
bogdanm 92:4fc01daae5a5 5701
bogdanm 92:4fc01daae5a5 5702 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 122:f9eeca106725 5703 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 5704 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 5705 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
bogdanm 92:4fc01daae5a5 5706
bogdanm 92:4fc01daae5a5 5707 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5708 /* */
bogdanm 92:4fc01daae5a5 5709 /* SYSCFG */
bogdanm 92:4fc01daae5a5 5710 /* */
bogdanm 92:4fc01daae5a5 5711 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5712 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 122:f9eeca106725 5713 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 5714 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
Kojto 122:f9eeca106725 5715 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
Kojto 122:f9eeca106725 5716 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
bogdanm 92:4fc01daae5a5 5717
bogdanm 92:4fc01daae5a5 5718 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 122:f9eeca106725 5719 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
bogdanm 92:4fc01daae5a5 5720 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 5721 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
bogdanm 92:4fc01daae5a5 5722
bogdanm 92:4fc01daae5a5 5723 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 5724 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
Kojto 122:f9eeca106725 5725 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
Kojto 122:f9eeca106725 5726 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
Kojto 122:f9eeca106725 5727 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
bogdanm 92:4fc01daae5a5 5728 /**
bogdanm 92:4fc01daae5a5 5729 * @brief EXTI0 configuration
bogdanm 92:4fc01daae5a5 5730 */
Kojto 122:f9eeca106725 5731 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
Kojto 122:f9eeca106725 5732 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
Kojto 122:f9eeca106725 5733 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
Kojto 122:f9eeca106725 5734 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
Kojto 122:f9eeca106725 5735 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
Kojto 122:f9eeca106725 5736 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
Kojto 122:f9eeca106725 5737 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
Kojto 122:f9eeca106725 5738 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
Kojto 122:f9eeca106725 5739 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
bogdanm 92:4fc01daae5a5 5740
bogdanm 92:4fc01daae5a5 5741 /**
bogdanm 92:4fc01daae5a5 5742 * @brief EXTI1 configuration
bogdanm 92:4fc01daae5a5 5743 */
Kojto 122:f9eeca106725 5744 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
Kojto 122:f9eeca106725 5745 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
Kojto 122:f9eeca106725 5746 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
Kojto 122:f9eeca106725 5747 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
Kojto 122:f9eeca106725 5748 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
Kojto 122:f9eeca106725 5749 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
Kojto 122:f9eeca106725 5750 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
Kojto 122:f9eeca106725 5751 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
Kojto 122:f9eeca106725 5752 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
bogdanm 92:4fc01daae5a5 5753
bogdanm 92:4fc01daae5a5 5754 /**
bogdanm 92:4fc01daae5a5 5755 * @brief EXTI2 configuration
bogdanm 92:4fc01daae5a5 5756 */
Kojto 122:f9eeca106725 5757 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
Kojto 122:f9eeca106725 5758 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
Kojto 122:f9eeca106725 5759 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
Kojto 122:f9eeca106725 5760 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
Kojto 122:f9eeca106725 5761 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
Kojto 122:f9eeca106725 5762 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
Kojto 122:f9eeca106725 5763 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
Kojto 122:f9eeca106725 5764 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
Kojto 122:f9eeca106725 5765 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
bogdanm 92:4fc01daae5a5 5766
bogdanm 92:4fc01daae5a5 5767 /**
bogdanm 92:4fc01daae5a5 5768 * @brief EXTI3 configuration
bogdanm 92:4fc01daae5a5 5769 */
Kojto 122:f9eeca106725 5770 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
Kojto 122:f9eeca106725 5771 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
Kojto 122:f9eeca106725 5772 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
Kojto 122:f9eeca106725 5773 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
Kojto 122:f9eeca106725 5774 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
Kojto 122:f9eeca106725 5775 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
Kojto 122:f9eeca106725 5776 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
Kojto 122:f9eeca106725 5777 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
Kojto 122:f9eeca106725 5778 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
bogdanm 92:4fc01daae5a5 5779
bogdanm 92:4fc01daae5a5 5780 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 5781 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
Kojto 122:f9eeca106725 5782 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
Kojto 122:f9eeca106725 5783 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
Kojto 122:f9eeca106725 5784 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
bogdanm 92:4fc01daae5a5 5785 /**
bogdanm 92:4fc01daae5a5 5786 * @brief EXTI4 configuration
bogdanm 92:4fc01daae5a5 5787 */
Kojto 122:f9eeca106725 5788 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
Kojto 122:f9eeca106725 5789 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
Kojto 122:f9eeca106725 5790 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
Kojto 122:f9eeca106725 5791 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
Kojto 122:f9eeca106725 5792 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
Kojto 122:f9eeca106725 5793 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
Kojto 122:f9eeca106725 5794 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
Kojto 122:f9eeca106725 5795 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
Kojto 122:f9eeca106725 5796 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
bogdanm 92:4fc01daae5a5 5797
bogdanm 92:4fc01daae5a5 5798 /**
bogdanm 92:4fc01daae5a5 5799 * @brief EXTI5 configuration
bogdanm 92:4fc01daae5a5 5800 */
Kojto 122:f9eeca106725 5801 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
Kojto 122:f9eeca106725 5802 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
Kojto 122:f9eeca106725 5803 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
Kojto 122:f9eeca106725 5804 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
Kojto 122:f9eeca106725 5805 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
Kojto 122:f9eeca106725 5806 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
Kojto 122:f9eeca106725 5807 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
Kojto 122:f9eeca106725 5808 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
Kojto 122:f9eeca106725 5809 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
bogdanm 92:4fc01daae5a5 5810
bogdanm 92:4fc01daae5a5 5811 /**
bogdanm 92:4fc01daae5a5 5812 * @brief EXTI6 configuration
bogdanm 92:4fc01daae5a5 5813 */
Kojto 122:f9eeca106725 5814 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
Kojto 122:f9eeca106725 5815 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
Kojto 122:f9eeca106725 5816 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
Kojto 122:f9eeca106725 5817 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
Kojto 122:f9eeca106725 5818 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
Kojto 122:f9eeca106725 5819 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
Kojto 122:f9eeca106725 5820 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
Kojto 122:f9eeca106725 5821 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
Kojto 122:f9eeca106725 5822 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
bogdanm 92:4fc01daae5a5 5823
bogdanm 92:4fc01daae5a5 5824 /**
bogdanm 92:4fc01daae5a5 5825 * @brief EXTI7 configuration
bogdanm 92:4fc01daae5a5 5826 */
Kojto 122:f9eeca106725 5827 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
Kojto 122:f9eeca106725 5828 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
Kojto 122:f9eeca106725 5829 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
Kojto 122:f9eeca106725 5830 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
Kojto 122:f9eeca106725 5831 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
Kojto 122:f9eeca106725 5832 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
Kojto 122:f9eeca106725 5833 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
Kojto 122:f9eeca106725 5834 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
Kojto 122:f9eeca106725 5835 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
bogdanm 92:4fc01daae5a5 5836
bogdanm 92:4fc01daae5a5 5837
bogdanm 92:4fc01daae5a5 5838 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 5839 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
Kojto 122:f9eeca106725 5840 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
Kojto 122:f9eeca106725 5841 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
Kojto 122:f9eeca106725 5842 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
bogdanm 92:4fc01daae5a5 5843
bogdanm 92:4fc01daae5a5 5844 /**
bogdanm 92:4fc01daae5a5 5845 * @brief EXTI8 configuration
bogdanm 92:4fc01daae5a5 5846 */
Kojto 122:f9eeca106725 5847 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
Kojto 122:f9eeca106725 5848 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
Kojto 122:f9eeca106725 5849 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
Kojto 122:f9eeca106725 5850 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
Kojto 122:f9eeca106725 5851 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
Kojto 122:f9eeca106725 5852 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
Kojto 122:f9eeca106725 5853 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
Kojto 122:f9eeca106725 5854 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
Kojto 122:f9eeca106725 5855 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
bogdanm 92:4fc01daae5a5 5856
bogdanm 92:4fc01daae5a5 5857 /**
bogdanm 92:4fc01daae5a5 5858 * @brief EXTI9 configuration
bogdanm 92:4fc01daae5a5 5859 */
Kojto 122:f9eeca106725 5860 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
Kojto 122:f9eeca106725 5861 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
Kojto 122:f9eeca106725 5862 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
Kojto 122:f9eeca106725 5863 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
Kojto 122:f9eeca106725 5864 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
Kojto 122:f9eeca106725 5865 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
Kojto 122:f9eeca106725 5866 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
Kojto 122:f9eeca106725 5867 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
Kojto 122:f9eeca106725 5868 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
bogdanm 92:4fc01daae5a5 5869
bogdanm 92:4fc01daae5a5 5870 /**
bogdanm 92:4fc01daae5a5 5871 * @brief EXTI10 configuration
bogdanm 92:4fc01daae5a5 5872 */
Kojto 122:f9eeca106725 5873 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
Kojto 122:f9eeca106725 5874 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
Kojto 122:f9eeca106725 5875 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
Kojto 122:f9eeca106725 5876 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
Kojto 122:f9eeca106725 5877 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
Kojto 122:f9eeca106725 5878 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
Kojto 122:f9eeca106725 5879 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
Kojto 122:f9eeca106725 5880 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
Kojto 122:f9eeca106725 5881 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
bogdanm 92:4fc01daae5a5 5882
bogdanm 92:4fc01daae5a5 5883 /**
bogdanm 92:4fc01daae5a5 5884 * @brief EXTI11 configuration
bogdanm 92:4fc01daae5a5 5885 */
Kojto 122:f9eeca106725 5886 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
Kojto 122:f9eeca106725 5887 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
Kojto 122:f9eeca106725 5888 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
Kojto 122:f9eeca106725 5889 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
Kojto 122:f9eeca106725 5890 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
Kojto 122:f9eeca106725 5891 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
Kojto 122:f9eeca106725 5892 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
Kojto 122:f9eeca106725 5893 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
Kojto 122:f9eeca106725 5894 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
bogdanm 92:4fc01daae5a5 5895
bogdanm 92:4fc01daae5a5 5896 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 122:f9eeca106725 5897 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
Kojto 122:f9eeca106725 5898 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
Kojto 122:f9eeca106725 5899 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
Kojto 122:f9eeca106725 5900 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
bogdanm 92:4fc01daae5a5 5901 /**
bogdanm 92:4fc01daae5a5 5902 * @brief EXTI12 configuration
bogdanm 92:4fc01daae5a5 5903 */
Kojto 122:f9eeca106725 5904 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
Kojto 122:f9eeca106725 5905 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
Kojto 122:f9eeca106725 5906 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
Kojto 122:f9eeca106725 5907 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
Kojto 122:f9eeca106725 5908 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
Kojto 122:f9eeca106725 5909 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
Kojto 122:f9eeca106725 5910 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
Kojto 122:f9eeca106725 5911 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
bogdanm 92:4fc01daae5a5 5912
bogdanm 92:4fc01daae5a5 5913 /**
bogdanm 92:4fc01daae5a5 5914 * @brief EXTI13 configuration
bogdanm 92:4fc01daae5a5 5915 */
Kojto 122:f9eeca106725 5916 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
Kojto 122:f9eeca106725 5917 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
Kojto 122:f9eeca106725 5918 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
Kojto 122:f9eeca106725 5919 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
Kojto 122:f9eeca106725 5920 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
Kojto 122:f9eeca106725 5921 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
Kojto 122:f9eeca106725 5922 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
Kojto 122:f9eeca106725 5923 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
bogdanm 92:4fc01daae5a5 5924
bogdanm 92:4fc01daae5a5 5925 /**
bogdanm 92:4fc01daae5a5 5926 * @brief EXTI14 configuration
bogdanm 92:4fc01daae5a5 5927 */
Kojto 122:f9eeca106725 5928 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
Kojto 122:f9eeca106725 5929 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
Kojto 122:f9eeca106725 5930 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
Kojto 122:f9eeca106725 5931 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
Kojto 122:f9eeca106725 5932 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
Kojto 122:f9eeca106725 5933 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
Kojto 122:f9eeca106725 5934 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
Kojto 122:f9eeca106725 5935 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
bogdanm 92:4fc01daae5a5 5936
bogdanm 92:4fc01daae5a5 5937 /**
bogdanm 92:4fc01daae5a5 5938 * @brief EXTI15 configuration
bogdanm 92:4fc01daae5a5 5939 */
Kojto 122:f9eeca106725 5940 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
Kojto 122:f9eeca106725 5941 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
Kojto 122:f9eeca106725 5942 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
Kojto 122:f9eeca106725 5943 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
Kojto 122:f9eeca106725 5944 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
Kojto 122:f9eeca106725 5945 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
Kojto 122:f9eeca106725 5946 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
Kojto 122:f9eeca106725 5947 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
bogdanm 92:4fc01daae5a5 5948
bogdanm 92:4fc01daae5a5 5949 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 122:f9eeca106725 5950 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
Kojto 122:f9eeca106725 5951 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
bogdanm 92:4fc01daae5a5 5952
bogdanm 92:4fc01daae5a5 5953 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5954 /* */
bogdanm 92:4fc01daae5a5 5955 /* TIM */
bogdanm 92:4fc01daae5a5 5956 /* */
bogdanm 92:4fc01daae5a5 5957 /******************************************************************************/
bogdanm 92:4fc01daae5a5 5958 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 5959 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
Kojto 122:f9eeca106725 5960 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
Kojto 122:f9eeca106725 5961 #define TIM_CR1_URS 0x0004U /*!<Update request source */
Kojto 122:f9eeca106725 5962 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
Kojto 122:f9eeca106725 5963 #define TIM_CR1_DIR 0x0010U /*!<Direction */
Kojto 122:f9eeca106725 5964
Kojto 122:f9eeca106725 5965 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 5966 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
Kojto 122:f9eeca106725 5967 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
Kojto 122:f9eeca106725 5968
Kojto 122:f9eeca106725 5969 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 5970
Kojto 122:f9eeca106725 5971 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 5972 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 5973 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 5974
bogdanm 92:4fc01daae5a5 5975 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 5976 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 5977 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 5978 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 5979
Kojto 122:f9eeca106725 5980 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 5981 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 5982 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 5983 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 5984
Kojto 122:f9eeca106725 5985 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
Kojto 122:f9eeca106725 5986 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 5987 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 5988 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 5989 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 5990 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 5991 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 5992 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
bogdanm 92:4fc01daae5a5 5993
bogdanm 92:4fc01daae5a5 5994 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 5995 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 5996 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 5997 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 5998 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 5999
Kojto 122:f9eeca106725 6000 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 6001 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6002 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6003 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6004
Kojto 122:f9eeca106725 6005 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
Kojto 122:f9eeca106725 6006
Kojto 122:f9eeca106725 6007 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 6008 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6009 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6010 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6011 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6012
Kojto 122:f9eeca106725 6013 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 6014 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6015 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6016
Kojto 122:f9eeca106725 6017 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
Kojto 122:f9eeca106725 6018 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
bogdanm 92:4fc01daae5a5 6019
bogdanm 92:4fc01daae5a5 6020 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 6021 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
Kojto 122:f9eeca106725 6022 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 6023 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 6024 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 6025 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 6026 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
Kojto 122:f9eeca106725 6027 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 6028 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
Kojto 122:f9eeca106725 6029 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
Kojto 122:f9eeca106725 6030 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 6031 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 6032 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 6033 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 6034 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
Kojto 122:f9eeca106725 6035 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
bogdanm 92:4fc01daae5a5 6036
bogdanm 92:4fc01daae5a5 6037 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 6038 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 6039 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 6040 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 6041 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 6042 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 6043 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 6044 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 6045 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 6046 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 6047 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 6048 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 6049 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 92:4fc01daae5a5 6050
bogdanm 92:4fc01daae5a5 6051 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 6052 #define TIM_EGR_UG 0x01U /*!<Update Generation */
Kojto 122:f9eeca106725 6053 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 6054 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 6055 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 6056 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 6057 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 6058 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
Kojto 122:f9eeca106725 6059 #define TIM_EGR_BG 0x80U /*!<Break Generation */
bogdanm 92:4fc01daae5a5 6060
bogdanm 92:4fc01daae5a5 6061 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 6062 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 6063 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6064 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6065
Kojto 122:f9eeca106725 6066 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 6067 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 6068
Kojto 122:f9eeca106725 6069 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 6070 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6071 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6072 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6073
Kojto 122:f9eeca106725 6074 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 6075
Kojto 122:f9eeca106725 6076 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 6077 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6078 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6079
Kojto 122:f9eeca106725 6080 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 6081 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 6082
Kojto 122:f9eeca106725 6083 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 6084 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6085 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6086 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6087
Kojto 122:f9eeca106725 6088 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
bogdanm 92:4fc01daae5a5 6089
bogdanm 92:4fc01daae5a5 6090 /*----------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 6091
Kojto 122:f9eeca106725 6092 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 6093 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6094 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6095
Kojto 122:f9eeca106725 6096 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 6097 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6098 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6099 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6100 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6101
Kojto 122:f9eeca106725 6102 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 6103 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6104 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6105
Kojto 122:f9eeca106725 6106 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 6107 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6108 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6109 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6110 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6111
bogdanm 92:4fc01daae5a5 6112 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 6113 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 6114 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6115 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6116
Kojto 122:f9eeca106725 6117 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 6118 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 6119
Kojto 122:f9eeca106725 6120 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 6121 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6122 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6123 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6124
Kojto 122:f9eeca106725 6125 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 6126
Kojto 122:f9eeca106725 6127 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 6128 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6129 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6130
Kojto 122:f9eeca106725 6131 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 6132 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 6133
Kojto 122:f9eeca106725 6134 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 6135 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6136 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6137 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6138
Kojto 122:f9eeca106725 6139 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
bogdanm 92:4fc01daae5a5 6140
bogdanm 92:4fc01daae5a5 6141 /*----------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 6142
Kojto 122:f9eeca106725 6143 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 6144 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6145 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6146
Kojto 122:f9eeca106725 6147 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 6148 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6149 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6150 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6151 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6152
Kojto 122:f9eeca106725 6153 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 6154 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6155 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6156
Kojto 122:f9eeca106725 6157 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 6158 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6159 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6160 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6161 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6162
bogdanm 92:4fc01daae5a5 6163 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 6164 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 6165 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 6166 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 6167 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 6168 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 6169 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 6170 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 6171 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 6172 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 6173 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 6174 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 6175 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 6176 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 6177 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 6178 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 92:4fc01daae5a5 6179
bogdanm 92:4fc01daae5a5 6180 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 6181 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
bogdanm 92:4fc01daae5a5 6182
bogdanm 92:4fc01daae5a5 6183 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 6184 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
bogdanm 92:4fc01daae5a5 6185
bogdanm 92:4fc01daae5a5 6186 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 6187 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
bogdanm 92:4fc01daae5a5 6188
bogdanm 92:4fc01daae5a5 6189 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 6190 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
bogdanm 92:4fc01daae5a5 6191
bogdanm 92:4fc01daae5a5 6192 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 6193 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
bogdanm 92:4fc01daae5a5 6194
bogdanm 92:4fc01daae5a5 6195 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 6196 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
bogdanm 92:4fc01daae5a5 6197
bogdanm 92:4fc01daae5a5 6198 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 6199 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
bogdanm 92:4fc01daae5a5 6200
bogdanm 92:4fc01daae5a5 6201 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 6202 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
bogdanm 92:4fc01daae5a5 6203
bogdanm 92:4fc01daae5a5 6204 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 6205 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 6206 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6207 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6208 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6209 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6210 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6211 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6212 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6213 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 6214
Kojto 122:f9eeca106725 6215 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 6216 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6217 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6218
Kojto 122:f9eeca106725 6219 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 6220 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 6221 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
Kojto 122:f9eeca106725 6222 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
Kojto 122:f9eeca106725 6223 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
Kojto 122:f9eeca106725 6224 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
bogdanm 92:4fc01daae5a5 6225
bogdanm 92:4fc01daae5a5 6226 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 6227 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 6228 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6229 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6230 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6231 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6232 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6233
Kojto 122:f9eeca106725 6234 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 6235 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6236 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6237 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6238 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6239 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
bogdanm 92:4fc01daae5a5 6240
bogdanm 92:4fc01daae5a5 6241 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 6242 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
bogdanm 92:4fc01daae5a5 6243
bogdanm 92:4fc01daae5a5 6244 /******************* Bit definition for TIM_OR register *********************/
Kojto 122:f9eeca106725 6245 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 122:f9eeca106725 6246 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
Kojto 122:f9eeca106725 6247 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
Kojto 122:f9eeca106725 6248 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 122:f9eeca106725 6249 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6250 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6251
bogdanm 92:4fc01daae5a5 6252
bogdanm 92:4fc01daae5a5 6253 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6254 /* */
bogdanm 92:4fc01daae5a5 6255 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 92:4fc01daae5a5 6256 /* */
bogdanm 92:4fc01daae5a5 6257 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6258 /******************* Bit definition for USART_SR register *******************/
Kojto 122:f9eeca106725 6259 #define USART_SR_PE 0x0001U /*!<Parity Error */
Kojto 122:f9eeca106725 6260 #define USART_SR_FE 0x0002U /*!<Framing Error */
Kojto 122:f9eeca106725 6261 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
Kojto 122:f9eeca106725 6262 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
Kojto 122:f9eeca106725 6263 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
Kojto 122:f9eeca106725 6264 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
Kojto 122:f9eeca106725 6265 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
Kojto 122:f9eeca106725 6266 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
Kojto 122:f9eeca106725 6267 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
Kojto 122:f9eeca106725 6268 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
bogdanm 92:4fc01daae5a5 6269
bogdanm 92:4fc01daae5a5 6270 /******************* Bit definition for USART_DR register *******************/
Kojto 122:f9eeca106725 6271 #define USART_DR_DR 0x01FFU /*!<Data value */
bogdanm 92:4fc01daae5a5 6272
bogdanm 92:4fc01daae5a5 6273 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 6274 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
Kojto 122:f9eeca106725 6275 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
bogdanm 92:4fc01daae5a5 6276
bogdanm 92:4fc01daae5a5 6277 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 6278 #define USART_CR1_SBK 0x0001U /*!<Send Break */
Kojto 122:f9eeca106725 6279 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
Kojto 122:f9eeca106725 6280 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
Kojto 122:f9eeca106725 6281 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
Kojto 122:f9eeca106725 6282 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
Kojto 122:f9eeca106725 6283 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
Kojto 122:f9eeca106725 6284 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 6285 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 6286 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 6287 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
Kojto 122:f9eeca106725 6288 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
Kojto 122:f9eeca106725 6289 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
Kojto 122:f9eeca106725 6290 #define USART_CR1_M 0x1000U /*!<Word length */
Kojto 122:f9eeca106725 6291 #define USART_CR1_UE 0x2000U /*!<USART Enable */
Kojto 122:f9eeca106725 6292 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
bogdanm 92:4fc01daae5a5 6293
bogdanm 92:4fc01daae5a5 6294 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 6295 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
Kojto 122:f9eeca106725 6296 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
Kojto 122:f9eeca106725 6297 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 6298 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
Kojto 122:f9eeca106725 6299 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
Kojto 122:f9eeca106725 6300 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
Kojto 122:f9eeca106725 6301 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
Kojto 122:f9eeca106725 6302
Kojto 122:f9eeca106725 6303 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 6304 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6305 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6306
Kojto 122:f9eeca106725 6307 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
bogdanm 92:4fc01daae5a5 6308
bogdanm 92:4fc01daae5a5 6309 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 6310 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 6311 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
Kojto 122:f9eeca106725 6312 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
Kojto 122:f9eeca106725 6313 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
Kojto 122:f9eeca106725 6314 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
Kojto 122:f9eeca106725 6315 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
Kojto 122:f9eeca106725 6316 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
Kojto 122:f9eeca106725 6317 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
Kojto 122:f9eeca106725 6318 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
Kojto 122:f9eeca106725 6319 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
Kojto 122:f9eeca106725 6320 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
Kojto 122:f9eeca106725 6321 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
bogdanm 92:4fc01daae5a5 6322
bogdanm 92:4fc01daae5a5 6323 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 6324 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 6325 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6326 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6327 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6328 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6329 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6330 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6331 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6332 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 6333
Kojto 122:f9eeca106725 6334 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
bogdanm 92:4fc01daae5a5 6335
bogdanm 92:4fc01daae5a5 6336 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6337 /* */
bogdanm 92:4fc01daae5a5 6338 /* Window WATCHDOG */
bogdanm 92:4fc01daae5a5 6339 /* */
bogdanm 92:4fc01daae5a5 6340 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6341 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 6342 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 6343 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 6344 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 6345 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
Kojto 122:f9eeca106725 6346 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
Kojto 122:f9eeca106725 6347 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
Kojto 122:f9eeca106725 6348 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
Kojto 122:f9eeca106725 6349 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
Kojto 122:f9eeca106725 6350 /* Legacy defines */
Kojto 122:f9eeca106725 6351 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 6352 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 6353 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 6354 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 6355 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 6356 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 6357 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 6358
Kojto 122:f9eeca106725 6359 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
bogdanm 92:4fc01daae5a5 6360
bogdanm 92:4fc01daae5a5 6361 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 6362 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 6363 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6364 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6365 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6366 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6367 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6368 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6369 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6370 /* Legacy defines */
Kojto 122:f9eeca106725 6371 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 6372 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 6373 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 6374 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 6375 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 6376 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 6377 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 6378
Kojto 122:f9eeca106725 6379 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 6380 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
Kojto 122:f9eeca106725 6381 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
Kojto 122:f9eeca106725 6382 /* Legacy defines */
Kojto 122:f9eeca106725 6383 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 6384 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 6385
Kojto 122:f9eeca106725 6386 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
bogdanm 92:4fc01daae5a5 6387
bogdanm 92:4fc01daae5a5 6388 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 6389 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
bogdanm 92:4fc01daae5a5 6390
bogdanm 92:4fc01daae5a5 6391
bogdanm 92:4fc01daae5a5 6392 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6393 /* */
bogdanm 92:4fc01daae5a5 6394 /* DBG */
bogdanm 92:4fc01daae5a5 6395 /* */
bogdanm 92:4fc01daae5a5 6396 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6397 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 6398 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto 122:f9eeca106725 6399 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
bogdanm 92:4fc01daae5a5 6400
bogdanm 92:4fc01daae5a5 6401 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 6402 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto 122:f9eeca106725 6403 #define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto 122:f9eeca106725 6404 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto 122:f9eeca106725 6405 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto 122:f9eeca106725 6406
Kojto 122:f9eeca106725 6407 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto 122:f9eeca106725 6408 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
Kojto 122:f9eeca106725 6409 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6410
bogdanm 92:4fc01daae5a5 6411 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 122:f9eeca106725 6412 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto 122:f9eeca106725 6413 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto 122:f9eeca106725 6414 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto 122:f9eeca106725 6415 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto 122:f9eeca106725 6416 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto 122:f9eeca106725 6417 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto 122:f9eeca106725 6418 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto 122:f9eeca106725 6419 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto 122:f9eeca106725 6420 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto 122:f9eeca106725 6421 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto 122:f9eeca106725 6422 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto 122:f9eeca106725 6423 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto 122:f9eeca106725 6424 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto 122:f9eeca106725 6425 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto 122:f9eeca106725 6426 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto 122:f9eeca106725 6427 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto 122:f9eeca106725 6428 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
bogdanm 92:4fc01daae5a5 6429 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm 92:4fc01daae5a5 6430 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm 92:4fc01daae5a5 6431
bogdanm 92:4fc01daae5a5 6432 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 122:f9eeca106725 6433 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto 122:f9eeca106725 6434 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto 122:f9eeca106725 6435 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto 122:f9eeca106725 6436 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto 122:f9eeca106725 6437 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
bogdanm 92:4fc01daae5a5 6438
bogdanm 92:4fc01daae5a5 6439 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6440 /* */
bogdanm 92:4fc01daae5a5 6441 /* USB_OTG */
bogdanm 92:4fc01daae5a5 6442 /* */
bogdanm 92:4fc01daae5a5 6443 /******************************************************************************/
bogdanm 92:4fc01daae5a5 6444 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 122:f9eeca106725 6445 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
Kojto 122:f9eeca106725 6446 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
Kojto 122:f9eeca106725 6447 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
Kojto 122:f9eeca106725 6448 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
Kojto 122:f9eeca106725 6449 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 6450 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
Kojto 122:f9eeca106725 6451 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
Kojto 122:f9eeca106725 6452 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
Kojto 122:f9eeca106725 6453 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
Kojto 122:f9eeca106725 6454 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
bogdanm 92:4fc01daae5a5 6455
bogdanm 92:4fc01daae5a5 6456 /******************** Bit definition forUSB_OTG_HCFG register ********************/
bogdanm 92:4fc01daae5a5 6457
Kojto 122:f9eeca106725 6458 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
Kojto 122:f9eeca106725 6459 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6460 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6461 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
bogdanm 92:4fc01daae5a5 6462
bogdanm 92:4fc01daae5a5 6463 /******************** Bit definition forUSB_OTG_DCFG register ********************/
bogdanm 92:4fc01daae5a5 6464
Kojto 122:f9eeca106725 6465 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
Kojto 122:f9eeca106725 6466 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6467 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6468 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
Kojto 122:f9eeca106725 6469
Kojto 122:f9eeca106725 6470 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
Kojto 122:f9eeca106725 6471 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6472 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6473 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6474 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6475 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
Kojto 122:f9eeca106725 6476 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
Kojto 122:f9eeca106725 6477 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
Kojto 122:f9eeca106725 6478
Kojto 122:f9eeca106725 6479 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
Kojto 122:f9eeca106725 6480 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 6481 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6482
Kojto 122:f9eeca106725 6483 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
Kojto 122:f9eeca106725 6484 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6485 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6486
bogdanm 92:4fc01daae5a5 6487 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 122:f9eeca106725 6488 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
Kojto 122:f9eeca106725 6489 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
Kojto 122:f9eeca106725 6490 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
bogdanm 92:4fc01daae5a5 6491
bogdanm 92:4fc01daae5a5 6492 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 122:f9eeca106725 6493 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
Kojto 122:f9eeca106725 6494 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
Kojto 122:f9eeca106725 6495 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
Kojto 122:f9eeca106725 6496 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
Kojto 122:f9eeca106725 6497 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
Kojto 122:f9eeca106725 6498 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
bogdanm 92:4fc01daae5a5 6499
bogdanm 92:4fc01daae5a5 6500 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 122:f9eeca106725 6501 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
Kojto 122:f9eeca106725 6502 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
Kojto 122:f9eeca106725 6503 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
Kojto 122:f9eeca106725 6504 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
Kojto 122:f9eeca106725 6505
Kojto 122:f9eeca106725 6506 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
Kojto 122:f9eeca106725 6507 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6508 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6509 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6510 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
Kojto 122:f9eeca106725 6511 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
Kojto 122:f9eeca106725 6512 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
Kojto 122:f9eeca106725 6513 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
Kojto 122:f9eeca106725 6514 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
bogdanm 92:4fc01daae5a5 6515
bogdanm 92:4fc01daae5a5 6516 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 122:f9eeca106725 6517 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
bogdanm 92:4fc01daae5a5 6518
bogdanm 92:4fc01daae5a5 6519 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 122:f9eeca106725 6520 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
Kojto 122:f9eeca106725 6521 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
bogdanm 92:4fc01daae5a5 6522
bogdanm 92:4fc01daae5a5 6523 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 122:f9eeca106725 6524 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
Kojto 122:f9eeca106725 6525
Kojto 122:f9eeca106725 6526 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
Kojto 122:f9eeca106725 6527 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 6528 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 6529 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
Kojto 122:f9eeca106725 6530 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
bogdanm 92:4fc01daae5a5 6531
bogdanm 92:4fc01daae5a5 6532 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 122:f9eeca106725 6533 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
Kojto 122:f9eeca106725 6534
Kojto 122:f9eeca106725 6535 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
Kojto 122:f9eeca106725 6536 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 6537 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 6538 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
Kojto 122:f9eeca106725 6539 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
Kojto 122:f9eeca106725 6540 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
Kojto 122:f9eeca106725 6541 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
Kojto 122:f9eeca106725 6542 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
bogdanm 92:4fc01daae5a5 6543
bogdanm 92:4fc01daae5a5 6544 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
bogdanm 92:4fc01daae5a5 6545
Kojto 122:f9eeca106725 6546 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
Kojto 122:f9eeca106725 6547 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6548 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6549 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6550 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 122:f9eeca106725 6551 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
Kojto 122:f9eeca106725 6552 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
Kojto 122:f9eeca106725 6553
Kojto 122:f9eeca106725 6554 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
Kojto 122:f9eeca106725 6555 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6556 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6557 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6558 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6559 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
Kojto 122:f9eeca106725 6560 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
Kojto 122:f9eeca106725 6561 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
Kojto 122:f9eeca106725 6562 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
Kojto 122:f9eeca106725 6563 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
Kojto 122:f9eeca106725 6564 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
Kojto 122:f9eeca106725 6565 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
Kojto 122:f9eeca106725 6566 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
Kojto 122:f9eeca106725 6567 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
Kojto 122:f9eeca106725 6568 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
Kojto 122:f9eeca106725 6569 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
Kojto 122:f9eeca106725 6570 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
Kojto 122:f9eeca106725 6571 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
bogdanm 92:4fc01daae5a5 6572
bogdanm 92:4fc01daae5a5 6573 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 122:f9eeca106725 6574 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
Kojto 122:f9eeca106725 6575 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
Kojto 122:f9eeca106725 6576 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
Kojto 122:f9eeca106725 6577 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
Kojto 122:f9eeca106725 6578 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
Kojto 122:f9eeca106725 6579
Kojto 122:f9eeca106725 6580 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
Kojto 122:f9eeca106725 6581 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 6582 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 6583 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 6584 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
Kojto 122:f9eeca106725 6585 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
Kojto 122:f9eeca106725 6586 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
Kojto 122:f9eeca106725 6587 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
bogdanm 92:4fc01daae5a5 6588
bogdanm 92:4fc01daae5a5 6589 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 122:f9eeca106725 6590 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 6591 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 6592 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 6593 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 6594 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 6595 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 6596 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 6597 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6598
bogdanm 92:4fc01daae5a5 6599 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 122:f9eeca106725 6600 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
Kojto 122:f9eeca106725 6601
Kojto 122:f9eeca106725 6602 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
Kojto 122:f9eeca106725 6603 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6604 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6605 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6606 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6607 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6608 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6609 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6610 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 6611
Kojto 122:f9eeca106725 6612 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
Kojto 122:f9eeca106725 6613 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6614 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6615 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6616 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6617 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6618 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6619 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6620 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
bogdanm 92:4fc01daae5a5 6621
bogdanm 92:4fc01daae5a5 6622 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 122:f9eeca106725 6623 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
bogdanm 92:4fc01daae5a5 6624
bogdanm 92:4fc01daae5a5 6625 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 122:f9eeca106725 6626 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 6627 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 6628 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
Kojto 122:f9eeca106725 6629 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
Kojto 122:f9eeca106725 6630 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
Kojto 122:f9eeca106725 6631 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 6632 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
bogdanm 92:4fc01daae5a5 6633
bogdanm 92:4fc01daae5a5 6634 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 122:f9eeca106725 6635 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
Kojto 122:f9eeca106725 6636 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
Kojto 122:f9eeca106725 6637 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
Kojto 122:f9eeca106725 6638 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
Kojto 122:f9eeca106725 6639 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
Kojto 122:f9eeca106725 6640 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
Kojto 122:f9eeca106725 6641 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
Kojto 122:f9eeca106725 6642 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
Kojto 122:f9eeca106725 6643 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
Kojto 122:f9eeca106725 6644 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
Kojto 122:f9eeca106725 6645 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
Kojto 122:f9eeca106725 6646 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
Kojto 122:f9eeca106725 6647 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
Kojto 122:f9eeca106725 6648 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
Kojto 122:f9eeca106725 6649 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
Kojto 122:f9eeca106725 6650 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
Kojto 122:f9eeca106725 6651 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
Kojto 122:f9eeca106725 6652 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
Kojto 122:f9eeca106725 6653 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
Kojto 122:f9eeca106725 6654 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
Kojto 122:f9eeca106725 6655 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
Kojto 122:f9eeca106725 6656 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
Kojto 122:f9eeca106725 6657 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
Kojto 122:f9eeca106725 6658 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
Kojto 122:f9eeca106725 6659 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
Kojto 122:f9eeca106725 6660 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
bogdanm 92:4fc01daae5a5 6661
bogdanm 92:4fc01daae5a5 6662 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 122:f9eeca106725 6663 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
Kojto 122:f9eeca106725 6664 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
Kojto 122:f9eeca106725 6665 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
Kojto 122:f9eeca106725 6666 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
Kojto 122:f9eeca106725 6667 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
Kojto 122:f9eeca106725 6668 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
Kojto 122:f9eeca106725 6669 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
Kojto 122:f9eeca106725 6670 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
Kojto 122:f9eeca106725 6671 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
Kojto 122:f9eeca106725 6672 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
Kojto 122:f9eeca106725 6673 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
Kojto 122:f9eeca106725 6674 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 122:f9eeca106725 6675 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
Kojto 122:f9eeca106725 6676 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
Kojto 122:f9eeca106725 6677 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
Kojto 122:f9eeca106725 6678 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
Kojto 122:f9eeca106725 6679 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
Kojto 122:f9eeca106725 6680 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
Kojto 122:f9eeca106725 6681 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
Kojto 122:f9eeca106725 6682 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
Kojto 122:f9eeca106725 6683 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
Kojto 122:f9eeca106725 6684 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
Kojto 122:f9eeca106725 6685 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
Kojto 122:f9eeca106725 6686 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
Kojto 122:f9eeca106725 6687 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
Kojto 122:f9eeca106725 6688 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
bogdanm 92:4fc01daae5a5 6689
bogdanm 92:4fc01daae5a5 6690 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 122:f9eeca106725 6691 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
Kojto 122:f9eeca106725 6692 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
bogdanm 92:4fc01daae5a5 6693
bogdanm 92:4fc01daae5a5 6694 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 122:f9eeca106725 6695 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
bogdanm 92:4fc01daae5a5 6696
bogdanm 92:4fc01daae5a5 6697 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 122:f9eeca106725 6698 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 6699 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 6700 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 6701 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6702
bogdanm 92:4fc01daae5a5 6703 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 122:f9eeca106725 6704 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 6705 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
bogdanm 92:4fc01daae5a5 6706
bogdanm 92:4fc01daae5a5 6707 /******************** Bit definition for OTG register ********************/
bogdanm 92:4fc01daae5a5 6708
Kojto 122:f9eeca106725 6709 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 6710 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6711 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6712 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6713 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6714 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 6715
Kojto 122:f9eeca106725 6716 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 6717 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6718 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6719
Kojto 122:f9eeca106725 6720 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 6721 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6722 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6723 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6724 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6725
Kojto 122:f9eeca106725 6726 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 6727 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6728 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6729 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6730 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6731
Kojto 122:f9eeca106725 6732 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 6733 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6734 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6735 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6736 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6737
bogdanm 92:4fc01daae5a5 6738 /******************** Bit definition for OTG register ********************/
bogdanm 92:4fc01daae5a5 6739
Kojto 122:f9eeca106725 6740 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 6741 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6742 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6743 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6744 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6745 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 6746
Kojto 122:f9eeca106725 6747 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 6748 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6749 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6750
Kojto 122:f9eeca106725 6751 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 6752 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6753 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6754 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6755 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6756
Kojto 122:f9eeca106725 6757 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 6758 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6759 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6760 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6761 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6762
Kojto 122:f9eeca106725 6763 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 6764 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6765 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6766 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6767 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
bogdanm 92:4fc01daae5a5 6768
bogdanm 92:4fc01daae5a5 6769 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 122:f9eeca106725 6770 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
bogdanm 92:4fc01daae5a5 6771
bogdanm 92:4fc01daae5a5 6772 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 122:f9eeca106725 6773 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
bogdanm 92:4fc01daae5a5 6774
bogdanm 92:4fc01daae5a5 6775 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 6776 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
Kojto 122:f9eeca106725 6777 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
Kojto 122:f9eeca106725 6778 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
Kojto 122:f9eeca106725 6779 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
bogdanm 92:4fc01daae5a5 6780
bogdanm 92:4fc01daae5a5 6781 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 122:f9eeca106725 6782 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
bogdanm 92:4fc01daae5a5 6783
bogdanm 92:4fc01daae5a5 6784 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 122:f9eeca106725 6785 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
Kojto 122:f9eeca106725 6786
Kojto 122:f9eeca106725 6787 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
Kojto 122:f9eeca106725 6788 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6789 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6790 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6791 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6792 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6793 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6794 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6795 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 6796
Kojto 122:f9eeca106725 6797 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
Kojto 122:f9eeca106725 6798 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6799 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6800 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6801 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6802 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6803 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6804 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
bogdanm 92:4fc01daae5a5 6805
bogdanm 92:4fc01daae5a5 6806 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 122:f9eeca106725 6807 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
Kojto 122:f9eeca106725 6808 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
Kojto 122:f9eeca106725 6809
Kojto 122:f9eeca106725 6810 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
Kojto 122:f9eeca106725 6811 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6812 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6813 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
Kojto 122:f9eeca106725 6814 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
Kojto 122:f9eeca106725 6815 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
Kojto 122:f9eeca106725 6816 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
Kojto 122:f9eeca106725 6817 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
Kojto 122:f9eeca106725 6818 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
Kojto 122:f9eeca106725 6819 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
Kojto 122:f9eeca106725 6820 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
Kojto 122:f9eeca106725 6821
Kojto 122:f9eeca106725 6822 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
Kojto 122:f9eeca106725 6823 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6824 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6825 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6826 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6827 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6828 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6829 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6830 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 6831 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
Kojto 122:f9eeca106725 6832 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
bogdanm 92:4fc01daae5a5 6833
bogdanm 92:4fc01daae5a5 6834 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 122:f9eeca106725 6835 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
bogdanm 92:4fc01daae5a5 6836
bogdanm 92:4fc01daae5a5 6837 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 122:f9eeca106725 6838 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
Kojto 122:f9eeca106725 6839 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
bogdanm 92:4fc01daae5a5 6840
bogdanm 92:4fc01daae5a5 6841 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 122:f9eeca106725 6842 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
Kojto 122:f9eeca106725 6843 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
Kojto 122:f9eeca106725 6844 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
Kojto 122:f9eeca106725 6845 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
Kojto 122:f9eeca106725 6846 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
Kojto 122:f9eeca106725 6847 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
bogdanm 92:4fc01daae5a5 6848
bogdanm 92:4fc01daae5a5 6849 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 122:f9eeca106725 6850 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
Kojto 122:f9eeca106725 6851 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
bogdanm 92:4fc01daae5a5 6852
bogdanm 92:4fc01daae5a5 6853 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 122:f9eeca106725 6854 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
bogdanm 92:4fc01daae5a5 6855
bogdanm 92:4fc01daae5a5 6856 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 6857 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 6858 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 6859 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 6860 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 6861 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 6862 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 6863 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 6864 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 6865 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
bogdanm 92:4fc01daae5a5 6866
bogdanm 92:4fc01daae5a5 6867 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 122:f9eeca106725 6868 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
Kojto 122:f9eeca106725 6869 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
Kojto 122:f9eeca106725 6870 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
Kojto 122:f9eeca106725 6871 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
Kojto 122:f9eeca106725 6872 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
Kojto 122:f9eeca106725 6873 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
Kojto 122:f9eeca106725 6874 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
Kojto 122:f9eeca106725 6875 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
Kojto 122:f9eeca106725 6876 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
Kojto 122:f9eeca106725 6877
Kojto 122:f9eeca106725 6878 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
Kojto 122:f9eeca106725 6879 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6880 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6881 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
Kojto 122:f9eeca106725 6882
Kojto 122:f9eeca106725 6883 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
Kojto 122:f9eeca106725 6884 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6885 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6886 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6887 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6888
Kojto 122:f9eeca106725 6889 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
Kojto 122:f9eeca106725 6890 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6891 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 6892
bogdanm 92:4fc01daae5a5 6893 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 6894 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 6895 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 6896 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
Kojto 122:f9eeca106725 6897 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 6898 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 6899 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 6900 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 6901 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 6902 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
Kojto 122:f9eeca106725 6903 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 6904 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
bogdanm 92:4fc01daae5a5 6905
bogdanm 92:4fc01daae5a5 6906 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 122:f9eeca106725 6907 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
Kojto 122:f9eeca106725 6908 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
bogdanm 92:4fc01daae5a5 6909
bogdanm 92:4fc01daae5a5 6910 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 122:f9eeca106725 6911 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 6912 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 6913 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
Kojto 122:f9eeca106725 6914 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 6915
Kojto 122:f9eeca106725 6916 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 6917 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6918 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6919 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 6920
Kojto 122:f9eeca106725 6921 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
Kojto 122:f9eeca106725 6922 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6923 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6924 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6925 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6926 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 6927 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 6928 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 6929 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 6930 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 6931 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
bogdanm 92:4fc01daae5a5 6932
bogdanm 92:4fc01daae5a5 6933 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 122:f9eeca106725 6934 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 6935
Kojto 122:f9eeca106725 6936 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
Kojto 122:f9eeca106725 6937 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 6938 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6939 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6940 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6941 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
Kojto 122:f9eeca106725 6942 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
Kojto 122:f9eeca106725 6943
Kojto 122:f9eeca106725 6944 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 6945 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6946 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6947
Kojto 122:f9eeca106725 6948 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
Kojto 122:f9eeca106725 6949 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6950 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6951
Kojto 122:f9eeca106725 6952 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
Kojto 122:f9eeca106725 6953 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6954 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6955 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6956 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6957 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6958 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6959 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6960 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
Kojto 122:f9eeca106725 6961 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
Kojto 122:f9eeca106725 6962 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
bogdanm 92:4fc01daae5a5 6963
bogdanm 92:4fc01daae5a5 6964 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
bogdanm 92:4fc01daae5a5 6965
Kojto 122:f9eeca106725 6966 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
Kojto 122:f9eeca106725 6967 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6968 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6969 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6970 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6971 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6972 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6973 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6974
Kojto 122:f9eeca106725 6975 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
Kojto 122:f9eeca106725 6976 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 6977 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 6978 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 6979 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 6980 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 6981 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6982 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6983
Kojto 122:f9eeca106725 6984 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
Kojto 122:f9eeca106725 6985 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6986 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6987 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
Kojto 122:f9eeca106725 6988 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
bogdanm 92:4fc01daae5a5 6989
bogdanm 92:4fc01daae5a5 6990 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 122:f9eeca106725 6991 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
Kojto 122:f9eeca106725 6992 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
Kojto 122:f9eeca106725 6993 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 6994 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
Kojto 122:f9eeca106725 6995 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
Kojto 122:f9eeca106725 6996 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
Kojto 122:f9eeca106725 6997 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
Kojto 122:f9eeca106725 6998 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
Kojto 122:f9eeca106725 6999 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
Kojto 122:f9eeca106725 7000 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
Kojto 122:f9eeca106725 7001 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
bogdanm 92:4fc01daae5a5 7002
bogdanm 92:4fc01daae5a5 7003 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 122:f9eeca106725 7004 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 7005 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 7006 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
Kojto 122:f9eeca106725 7007 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
Kojto 122:f9eeca106725 7008 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
Kojto 122:f9eeca106725 7009 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
Kojto 122:f9eeca106725 7010 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
Kojto 122:f9eeca106725 7011 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
Kojto 122:f9eeca106725 7012 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
Kojto 122:f9eeca106725 7013 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
Kojto 122:f9eeca106725 7014 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
bogdanm 92:4fc01daae5a5 7015
bogdanm 92:4fc01daae5a5 7016 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 122:f9eeca106725 7017 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
Kojto 122:f9eeca106725 7018 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
Kojto 122:f9eeca106725 7019 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 7020 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
Kojto 122:f9eeca106725 7021 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
Kojto 122:f9eeca106725 7022 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
Kojto 122:f9eeca106725 7023 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
Kojto 122:f9eeca106725 7024 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
Kojto 122:f9eeca106725 7025 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
Kojto 122:f9eeca106725 7026 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
Kojto 122:f9eeca106725 7027 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
bogdanm 92:4fc01daae5a5 7028
bogdanm 92:4fc01daae5a5 7029 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
bogdanm 92:4fc01daae5a5 7030
Kojto 122:f9eeca106725 7031 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7032 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7033 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
bogdanm 92:4fc01daae5a5 7034 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 122:f9eeca106725 7035 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7036 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7037 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
Kojto 122:f9eeca106725 7038 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
Kojto 122:f9eeca106725 7039 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7040 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 7041
bogdanm 92:4fc01daae5a5 7042 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 122:f9eeca106725 7043 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
bogdanm 92:4fc01daae5a5 7044
bogdanm 92:4fc01daae5a5 7045 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 122:f9eeca106725 7046 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
bogdanm 92:4fc01daae5a5 7047
bogdanm 92:4fc01daae5a5 7048 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 122:f9eeca106725 7049 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
bogdanm 92:4fc01daae5a5 7050
bogdanm 92:4fc01daae5a5 7051 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 122:f9eeca106725 7052 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 122:f9eeca106725 7053 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
bogdanm 92:4fc01daae5a5 7054
bogdanm 92:4fc01daae5a5 7055 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
bogdanm 92:4fc01daae5a5 7056
Kojto 122:f9eeca106725 7057 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 122:f9eeca106725 7058 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 7059 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 7060 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 7061 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 7062 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 7063 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7064 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7065 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
Kojto 122:f9eeca106725 7066 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 7067 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 7068 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 7069 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 7070 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
bogdanm 92:4fc01daae5a5 7071
bogdanm 92:4fc01daae5a5 7072 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 122:f9eeca106725 7073 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 7074 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 7075 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
Kojto 122:f9eeca106725 7076 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
Kojto 122:f9eeca106725 7077 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
Kojto 122:f9eeca106725 7078 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
bogdanm 92:4fc01daae5a5 7079
bogdanm 92:4fc01daae5a5 7080 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
bogdanm 92:4fc01daae5a5 7081
Kojto 122:f9eeca106725 7082 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7083 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7084
Kojto 122:f9eeca106725 7085 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
Kojto 122:f9eeca106725 7086 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7087 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 7088
bogdanm 92:4fc01daae5a5 7089 /******************** Bit definition for PCGCCTL register ********************/
Kojto 122:f9eeca106725 7090 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
Kojto 122:f9eeca106725 7091 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 7092 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 7093
bogdanm 92:4fc01daae5a5 7094 /**
bogdanm 92:4fc01daae5a5 7095 * @}
bogdanm 92:4fc01daae5a5 7096 */
bogdanm 92:4fc01daae5a5 7097
bogdanm 92:4fc01daae5a5 7098 /**
bogdanm 92:4fc01daae5a5 7099 * @}
bogdanm 92:4fc01daae5a5 7100 */
bogdanm 92:4fc01daae5a5 7101
bogdanm 92:4fc01daae5a5 7102 /** @addtogroup Exported_macros
bogdanm 92:4fc01daae5a5 7103 * @{
bogdanm 92:4fc01daae5a5 7104 */
bogdanm 92:4fc01daae5a5 7105
bogdanm 92:4fc01daae5a5 7106 /******************************* ADC Instances ********************************/
bogdanm 92:4fc01daae5a5 7107 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
bogdanm 92:4fc01daae5a5 7108 ((INSTANCE) == ADC2) || \
bogdanm 92:4fc01daae5a5 7109 ((INSTANCE) == ADC3))
bogdanm 92:4fc01daae5a5 7110
bogdanm 92:4fc01daae5a5 7111 /******************************* CAN Instances ********************************/
bogdanm 92:4fc01daae5a5 7112 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
bogdanm 92:4fc01daae5a5 7113 ((INSTANCE) == CAN2))
bogdanm 92:4fc01daae5a5 7114
bogdanm 92:4fc01daae5a5 7115 /******************************* CRC Instances ********************************/
bogdanm 92:4fc01daae5a5 7116 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 92:4fc01daae5a5 7117
bogdanm 92:4fc01daae5a5 7118 /******************************* DAC Instances ********************************/
bogdanm 92:4fc01daae5a5 7119 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 92:4fc01daae5a5 7120
bogdanm 92:4fc01daae5a5 7121 /******************************** DMA Instances *******************************/
bogdanm 92:4fc01daae5a5 7122 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 92:4fc01daae5a5 7123 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 92:4fc01daae5a5 7124 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 92:4fc01daae5a5 7125 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 92:4fc01daae5a5 7126 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 92:4fc01daae5a5 7127 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 92:4fc01daae5a5 7128 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 92:4fc01daae5a5 7129 ((INSTANCE) == DMA1_Stream7) || \
bogdanm 92:4fc01daae5a5 7130 ((INSTANCE) == DMA2_Stream0) || \
bogdanm 92:4fc01daae5a5 7131 ((INSTANCE) == DMA2_Stream1) || \
bogdanm 92:4fc01daae5a5 7132 ((INSTANCE) == DMA2_Stream2) || \
bogdanm 92:4fc01daae5a5 7133 ((INSTANCE) == DMA2_Stream3) || \
bogdanm 92:4fc01daae5a5 7134 ((INSTANCE) == DMA2_Stream4) || \
bogdanm 92:4fc01daae5a5 7135 ((INSTANCE) == DMA2_Stream5) || \
bogdanm 92:4fc01daae5a5 7136 ((INSTANCE) == DMA2_Stream6) || \
bogdanm 92:4fc01daae5a5 7137 ((INSTANCE) == DMA2_Stream7))
bogdanm 92:4fc01daae5a5 7138
bogdanm 92:4fc01daae5a5 7139 /******************************* GPIO Instances *******************************/
bogdanm 92:4fc01daae5a5 7140 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 92:4fc01daae5a5 7141 ((INSTANCE) == GPIOB) || \
bogdanm 92:4fc01daae5a5 7142 ((INSTANCE) == GPIOC) || \
bogdanm 92:4fc01daae5a5 7143 ((INSTANCE) == GPIOD) || \
bogdanm 92:4fc01daae5a5 7144 ((INSTANCE) == GPIOE) || \
bogdanm 92:4fc01daae5a5 7145 ((INSTANCE) == GPIOF) || \
bogdanm 92:4fc01daae5a5 7146 ((INSTANCE) == GPIOG) || \
bogdanm 92:4fc01daae5a5 7147 ((INSTANCE) == GPIOH) || \
bogdanm 92:4fc01daae5a5 7148 ((INSTANCE) == GPIOI))
bogdanm 92:4fc01daae5a5 7149
bogdanm 92:4fc01daae5a5 7150 /******************************** I2C Instances *******************************/
bogdanm 92:4fc01daae5a5 7151 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 92:4fc01daae5a5 7152 ((INSTANCE) == I2C2) || \
bogdanm 92:4fc01daae5a5 7153 ((INSTANCE) == I2C3))
bogdanm 92:4fc01daae5a5 7154
bogdanm 92:4fc01daae5a5 7155 /******************************** I2S Instances *******************************/
Kojto 99:dbbf35b96557 7156 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7157 ((INSTANCE) == SPI3))
bogdanm 92:4fc01daae5a5 7158
bogdanm 92:4fc01daae5a5 7159 /*************************** I2S Extended Instances ***************************/
Kojto 99:dbbf35b96557 7160 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
Kojto 99:dbbf35b96557 7161 ((INSTANCE) == SPI3) || \
Kojto 99:dbbf35b96557 7162 ((INSTANCE) == I2S2ext) || \
Kojto 99:dbbf35b96557 7163 ((INSTANCE) == I2S3ext))
bogdanm 92:4fc01daae5a5 7164
bogdanm 92:4fc01daae5a5 7165 /******************************* RNG Instances ********************************/
bogdanm 92:4fc01daae5a5 7166 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm 92:4fc01daae5a5 7167
bogdanm 92:4fc01daae5a5 7168 /****************************** RTC Instances *********************************/
bogdanm 92:4fc01daae5a5 7169 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 92:4fc01daae5a5 7170
bogdanm 92:4fc01daae5a5 7171 /******************************** SPI Instances *******************************/
bogdanm 92:4fc01daae5a5 7172 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 92:4fc01daae5a5 7173 ((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7174 ((INSTANCE) == SPI3))
bogdanm 92:4fc01daae5a5 7175
bogdanm 92:4fc01daae5a5 7176 /*************************** SPI Extended Instances ***************************/
bogdanm 92:4fc01daae5a5 7177 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 92:4fc01daae5a5 7178 ((INSTANCE) == SPI2) || \
bogdanm 92:4fc01daae5a5 7179 ((INSTANCE) == SPI3) || \
bogdanm 92:4fc01daae5a5 7180 ((INSTANCE) == I2S2ext) || \
bogdanm 92:4fc01daae5a5 7181 ((INSTANCE) == I2S3ext))
bogdanm 92:4fc01daae5a5 7182
bogdanm 92:4fc01daae5a5 7183 /****************** TIM Instances : All supported instances *******************/
bogdanm 92:4fc01daae5a5 7184 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7185 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7186 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7187 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7188 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7189 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7190 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7191 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7192 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7193 ((INSTANCE) == TIM10) || \
bogdanm 92:4fc01daae5a5 7194 ((INSTANCE) == TIM11) || \
bogdanm 92:4fc01daae5a5 7195 ((INSTANCE) == TIM12) || \
bogdanm 92:4fc01daae5a5 7196 ((INSTANCE) == TIM13) || \
bogdanm 92:4fc01daae5a5 7197 ((INSTANCE) == TIM14))
bogdanm 92:4fc01daae5a5 7198
bogdanm 92:4fc01daae5a5 7199 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 92:4fc01daae5a5 7200 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7201 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7202 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7203 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7204 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7205 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7206 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7207 ((INSTANCE) == TIM10) || \
bogdanm 92:4fc01daae5a5 7208 ((INSTANCE) == TIM11) || \
bogdanm 92:4fc01daae5a5 7209 ((INSTANCE) == TIM12) || \
bogdanm 92:4fc01daae5a5 7210 ((INSTANCE) == TIM13) || \
bogdanm 92:4fc01daae5a5 7211 ((INSTANCE) == TIM14))
bogdanm 92:4fc01daae5a5 7212
bogdanm 92:4fc01daae5a5 7213 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7214 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7215 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7216 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7217 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7218 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7219 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7220 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7221 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7222
bogdanm 92:4fc01daae5a5 7223 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7224 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7225 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7226 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7227 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7228 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7229 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7230
bogdanm 92:4fc01daae5a5 7231 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 92:4fc01daae5a5 7232 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7233 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7234 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7235 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7236 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7237 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7238
bogdanm 92:4fc01daae5a5 7239 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 92:4fc01daae5a5 7240 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7241 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7242
bogdanm 92:4fc01daae5a5 7243 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 92:4fc01daae5a5 7244 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7245 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7246 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7247 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7248 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7249 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7250
bogdanm 92:4fc01daae5a5 7251 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 92:4fc01daae5a5 7252 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7253 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7254 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7255 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7256 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7257 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7258 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7259 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7260
bogdanm 92:4fc01daae5a5 7261 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 92:4fc01daae5a5 7262 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7263 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7264 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7265 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7266 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7267 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7268
bogdanm 92:4fc01daae5a5 7269 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 92:4fc01daae5a5 7270 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7271 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7272 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7273 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7274 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7275 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7276
bogdanm 92:4fc01daae5a5 7277 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 92:4fc01daae5a5 7278 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7279 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7280 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7281 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7282 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7283 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7284
bogdanm 92:4fc01daae5a5 7285 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 92:4fc01daae5a5 7286 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7287 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7288 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7289 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7290 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7291 ((INSTANCE) == TIM6) || \
bogdanm 92:4fc01daae5a5 7292 ((INSTANCE) == TIM7) || \
bogdanm 92:4fc01daae5a5 7293 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7294 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7295 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7296
bogdanm 92:4fc01daae5a5 7297 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 92:4fc01daae5a5 7298 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7299 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7300 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7301 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7302 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7303 ((INSTANCE) == TIM8) || \
bogdanm 92:4fc01daae5a5 7304 ((INSTANCE) == TIM9) || \
bogdanm 92:4fc01daae5a5 7305 ((INSTANCE) == TIM12))
bogdanm 92:4fc01daae5a5 7306
bogdanm 92:4fc01daae5a5 7307 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 92:4fc01daae5a5 7308 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7309 ((INSTANCE) == TIM5))
bogdanm 92:4fc01daae5a5 7310
bogdanm 92:4fc01daae5a5 7311 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 92:4fc01daae5a5 7312 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 92:4fc01daae5a5 7313 ((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7314 ((INSTANCE) == TIM3) || \
bogdanm 92:4fc01daae5a5 7315 ((INSTANCE) == TIM4) || \
bogdanm 92:4fc01daae5a5 7316 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7317 ((INSTANCE) == TIM8))
bogdanm 92:4fc01daae5a5 7318
bogdanm 92:4fc01daae5a5 7319 /****************** TIM Instances : remapping capability **********************/
bogdanm 92:4fc01daae5a5 7320 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 92:4fc01daae5a5 7321 ((INSTANCE) == TIM5) || \
bogdanm 92:4fc01daae5a5 7322 ((INSTANCE) == TIM11))
bogdanm 92:4fc01daae5a5 7323
bogdanm 92:4fc01daae5a5 7324 /******************* TIM Instances : output(s) available **********************/
bogdanm 92:4fc01daae5a5 7325 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 92:4fc01daae5a5 7326 ((((INSTANCE) == TIM1) && \
bogdanm 92:4fc01daae5a5 7327 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7328 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7329 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7330 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7331 || \
bogdanm 92:4fc01daae5a5 7332 (((INSTANCE) == TIM2) && \
bogdanm 92:4fc01daae5a5 7333 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7334 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7335 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7336 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7337 || \
bogdanm 92:4fc01daae5a5 7338 (((INSTANCE) == TIM3) && \
bogdanm 92:4fc01daae5a5 7339 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7340 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7341 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7342 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7343 || \
bogdanm 92:4fc01daae5a5 7344 (((INSTANCE) == TIM4) && \
bogdanm 92:4fc01daae5a5 7345 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7346 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7347 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7348 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7349 || \
bogdanm 92:4fc01daae5a5 7350 (((INSTANCE) == TIM5) && \
bogdanm 92:4fc01daae5a5 7351 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7352 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7353 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7354 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7355 || \
bogdanm 92:4fc01daae5a5 7356 (((INSTANCE) == TIM8) && \
bogdanm 92:4fc01daae5a5 7357 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7358 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7359 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 7360 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 92:4fc01daae5a5 7361 || \
bogdanm 92:4fc01daae5a5 7362 (((INSTANCE) == TIM9) && \
bogdanm 92:4fc01daae5a5 7363 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7364 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 92:4fc01daae5a5 7365 || \
bogdanm 92:4fc01daae5a5 7366 (((INSTANCE) == TIM10) && \
bogdanm 92:4fc01daae5a5 7367 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7368 || \
bogdanm 92:4fc01daae5a5 7369 (((INSTANCE) == TIM11) && \
bogdanm 92:4fc01daae5a5 7370 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7371 || \
bogdanm 92:4fc01daae5a5 7372 (((INSTANCE) == TIM12) && \
bogdanm 92:4fc01daae5a5 7373 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7374 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 92:4fc01daae5a5 7375 || \
bogdanm 92:4fc01daae5a5 7376 (((INSTANCE) == TIM13) && \
bogdanm 92:4fc01daae5a5 7377 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 92:4fc01daae5a5 7378 || \
bogdanm 92:4fc01daae5a5 7379 (((INSTANCE) == TIM14) && \
bogdanm 92:4fc01daae5a5 7380 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 92:4fc01daae5a5 7381
bogdanm 92:4fc01daae5a5 7382 /************ TIM Instances : complementary output(s) available ***************/
bogdanm 92:4fc01daae5a5 7383 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 92:4fc01daae5a5 7384 ((((INSTANCE) == TIM1) && \
bogdanm 92:4fc01daae5a5 7385 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7386 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7387 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 92:4fc01daae5a5 7388 || \
bogdanm 92:4fc01daae5a5 7389 (((INSTANCE) == TIM8) && \
bogdanm 92:4fc01daae5a5 7390 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 7391 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 7392 ((CHANNEL) == TIM_CHANNEL_3))))
bogdanm 92:4fc01daae5a5 7393
bogdanm 92:4fc01daae5a5 7394 /******************** USART Instances : Synchronous mode **********************/
bogdanm 92:4fc01daae5a5 7395 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7396 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7397 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7398 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7399
bogdanm 92:4fc01daae5a5 7400 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 92:4fc01daae5a5 7401 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7402 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7403 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7404 ((INSTANCE) == UART4) || \
bogdanm 92:4fc01daae5a5 7405 ((INSTANCE) == UART5) || \
bogdanm 92:4fc01daae5a5 7406 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7407
bogdanm 92:4fc01daae5a5 7408 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 92:4fc01daae5a5 7409 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7410 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7411 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7412 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7413
bogdanm 92:4fc01daae5a5 7414 /********************* UART Instances : Smard card mode ***********************/
bogdanm 92:4fc01daae5a5 7415 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7416 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7417 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7418 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7419
bogdanm 92:4fc01daae5a5 7420 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 92:4fc01daae5a5 7421 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 92:4fc01daae5a5 7422 ((INSTANCE) == USART2) || \
bogdanm 92:4fc01daae5a5 7423 ((INSTANCE) == USART3) || \
bogdanm 92:4fc01daae5a5 7424 ((INSTANCE) == UART4) || \
bogdanm 92:4fc01daae5a5 7425 ((INSTANCE) == UART5) || \
bogdanm 92:4fc01daae5a5 7426 ((INSTANCE) == USART6))
bogdanm 92:4fc01daae5a5 7427
Kojto 122:f9eeca106725 7428 /*********************** PCD Instances ****************************************/
Kojto 122:f9eeca106725 7429 /*********************** PCD Instances ****************************************/
Kojto 122:f9eeca106725 7430 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
Kojto 122:f9eeca106725 7431 ((INSTANCE) == USB_OTG_HS))
Kojto 122:f9eeca106725 7432
Kojto 122:f9eeca106725 7433 /*********************** HCD Instances ****************************************/
Kojto 122:f9eeca106725 7434 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
Kojto 122:f9eeca106725 7435 ((INSTANCE) == USB_OTG_HS))
Kojto 122:f9eeca106725 7436
bogdanm 92:4fc01daae5a5 7437 /****************************** IWDG Instances ********************************/
bogdanm 92:4fc01daae5a5 7438 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 92:4fc01daae5a5 7439
bogdanm 92:4fc01daae5a5 7440 /****************************** WWDG Instances ********************************/
bogdanm 92:4fc01daae5a5 7441 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 92:4fc01daae5a5 7442
Kojto 99:dbbf35b96557 7443 /****************************** SDIO Instances ********************************/
Kojto 99:dbbf35b96557 7444 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 99:dbbf35b96557 7445
Kojto 99:dbbf35b96557 7446 /****************************** USB Exported Constants ************************/
Kojto 122:f9eeca106725 7447 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
Kojto 122:f9eeca106725 7448 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
Kojto 122:f9eeca106725 7449 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
Kojto 122:f9eeca106725 7450 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
Kojto 122:f9eeca106725 7451
Kojto 122:f9eeca106725 7452 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
Kojto 122:f9eeca106725 7453 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Kojto 122:f9eeca106725 7454 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
Kojto 122:f9eeca106725 7455 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
Kojto 99:dbbf35b96557 7456
bogdanm 92:4fc01daae5a5 7457 /******************************************************************************/
bogdanm 92:4fc01daae5a5 7458 /* For a painless codes migration between the STM32F4xx device product */
bogdanm 92:4fc01daae5a5 7459 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 92:4fc01daae5a5 7460 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 92:4fc01daae5a5 7461 /* No need to update developed interrupt code when moving across */
bogdanm 92:4fc01daae5a5 7462 /* product lines within the same STM32F4 Family */
bogdanm 92:4fc01daae5a5 7463 /******************************************************************************/
bogdanm 92:4fc01daae5a5 7464
bogdanm 92:4fc01daae5a5 7465 /* Aliases for __IRQn */
bogdanm 92:4fc01daae5a5 7466 #define FMC_IRQn FSMC_IRQn
bogdanm 92:4fc01daae5a5 7467
bogdanm 92:4fc01daae5a5 7468 /* Aliases for __IRQHandler */
bogdanm 92:4fc01daae5a5 7469 #define FMC_IRQHandler FSMC_IRQHandler
bogdanm 92:4fc01daae5a5 7470
bogdanm 92:4fc01daae5a5 7471 /**
bogdanm 92:4fc01daae5a5 7472 * @}
bogdanm 92:4fc01daae5a5 7473 */
bogdanm 92:4fc01daae5a5 7474
bogdanm 92:4fc01daae5a5 7475 /**
bogdanm 92:4fc01daae5a5 7476 * @}
bogdanm 92:4fc01daae5a5 7477 */
bogdanm 92:4fc01daae5a5 7478
bogdanm 92:4fc01daae5a5 7479 /**
bogdanm 92:4fc01daae5a5 7480 * @}
bogdanm 92:4fc01daae5a5 7481 */
bogdanm 92:4fc01daae5a5 7482
bogdanm 92:4fc01daae5a5 7483 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 7484 }
bogdanm 92:4fc01daae5a5 7485 #endif /* __cplusplus */
bogdanm 92:4fc01daae5a5 7486
bogdanm 92:4fc01daae5a5 7487 #endif /* __STM32F405xx_H */
bogdanm 92:4fc01daae5a5 7488
bogdanm 92:4fc01daae5a5 7489
bogdanm 92:4fc01daae5a5 7490
bogdanm 92:4fc01daae5a5 7491 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/