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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_B96B_F446VE/stm32f446xx.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
112:6f327212ef96 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 112:6f327212ef96 1 /**
Kojto 112:6f327212ef96 2 ******************************************************************************
Kojto 112:6f327212ef96 3 * @file stm32f446xx.h
Kojto 112:6f327212ef96 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.5.0
Kojto 122:f9eeca106725 6 * @date 22-April-2016
Kojto 112:6f327212ef96 7 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
Kojto 112:6f327212ef96 8 *
Kojto 112:6f327212ef96 9 * This file contains:
Kojto 112:6f327212ef96 10 * - Data structures and the address mapping for all peripherals
Kojto 122:f9eeca106725 11 * - peripherals registers declarations and bits definition
Kojto 122:f9eeca106725 12 * - Macros to access peripheral's registers hardware
Kojto 112:6f327212ef96 13 *
Kojto 112:6f327212ef96 14 ******************************************************************************
Kojto 112:6f327212ef96 15 * @attention
Kojto 112:6f327212ef96 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 112:6f327212ef96 18 *
Kojto 112:6f327212ef96 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 112:6f327212ef96 20 * are permitted provided that the following conditions are met:
Kojto 112:6f327212ef96 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 112:6f327212ef96 22 * this list of conditions and the following disclaimer.
Kojto 112:6f327212ef96 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 112:6f327212ef96 24 * this list of conditions and the following disclaimer in the documentation
Kojto 112:6f327212ef96 25 * and/or other materials provided with the distribution.
Kojto 112:6f327212ef96 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 112:6f327212ef96 27 * may be used to endorse or promote products derived from this software
Kojto 112:6f327212ef96 28 * without specific prior written permission.
Kojto 112:6f327212ef96 29 *
Kojto 112:6f327212ef96 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 112:6f327212ef96 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 112:6f327212ef96 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 112:6f327212ef96 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 112:6f327212ef96 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 112:6f327212ef96 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 112:6f327212ef96 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 112:6f327212ef96 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 112:6f327212ef96 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 112:6f327212ef96 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 112:6f327212ef96 40 *
Kojto 112:6f327212ef96 41 ******************************************************************************
Kojto 112:6f327212ef96 42 */
Kojto 112:6f327212ef96 43
Kojto 112:6f327212ef96 44 /** @addtogroup CMSIS_Device
Kojto 112:6f327212ef96 45 * @{
Kojto 112:6f327212ef96 46 */
Kojto 112:6f327212ef96 47
Kojto 112:6f327212ef96 48 /** @addtogroup stm32f446xx
Kojto 112:6f327212ef96 49 * @{
Kojto 112:6f327212ef96 50 */
Kojto 112:6f327212ef96 51
Kojto 112:6f327212ef96 52 #ifndef __STM32F446xx_H
Kojto 112:6f327212ef96 53 #define __STM32F446xx_H
Kojto 112:6f327212ef96 54
Kojto 112:6f327212ef96 55 #ifdef __cplusplus
Kojto 112:6f327212ef96 56 extern "C" {
Kojto 112:6f327212ef96 57 #endif /* __cplusplus */
Kojto 112:6f327212ef96 58
Kojto 112:6f327212ef96 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 112:6f327212ef96 60 * @{
Kojto 112:6f327212ef96 61 */
Kojto 112:6f327212ef96 62
Kojto 112:6f327212ef96 63 /**
Kojto 112:6f327212ef96 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 112:6f327212ef96 65 */
Kojto 122:f9eeca106725 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
Kojto 122:f9eeca106725 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
Kojto 122:f9eeca106725 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 70 #ifndef __FPU_PRESENT
Kojto 122:f9eeca106725 71 #define __FPU_PRESENT 1U /*!< FPU present */
Kojto 122:f9eeca106725 72 #endif /* __FPU_PRESENT */
Kojto 112:6f327212ef96 73
Kojto 112:6f327212ef96 74 /**
Kojto 112:6f327212ef96 75 * @}
Kojto 112:6f327212ef96 76 */
Kojto 112:6f327212ef96 77
Kojto 112:6f327212ef96 78 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 112:6f327212ef96 79 * @{
Kojto 112:6f327212ef96 80 */
Kojto 112:6f327212ef96 81
Kojto 112:6f327212ef96 82 /**
Kojto 112:6f327212ef96 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 112:6f327212ef96 84 * in @ref Library_configuration_section
Kojto 112:6f327212ef96 85 */
Kojto 112:6f327212ef96 86 typedef enum
Kojto 112:6f327212ef96 87 {
Kojto 112:6f327212ef96 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 112:6f327212ef96 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 112:6f327212ef96 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 112:6f327212ef96 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 112:6f327212ef96 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 112:6f327212ef96 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 112:6f327212ef96 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 112:6f327212ef96 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 112:6f327212ef96 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 112:6f327212ef96 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 112:6f327212ef96 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 112:6f327212ef96 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 112:6f327212ef96 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 112:6f327212ef96 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 112:6f327212ef96 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 112:6f327212ef96 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 112:6f327212ef96 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 112:6f327212ef96 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 112:6f327212ef96 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 112:6f327212ef96 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 112:6f327212ef96 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 112:6f327212ef96 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 112:6f327212ef96 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 112:6f327212ef96 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 112:6f327212ef96 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 112:6f327212ef96 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 112:6f327212ef96 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 112:6f327212ef96 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 112:6f327212ef96 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 112:6f327212ef96 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 112:6f327212ef96 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 112:6f327212ef96 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 112:6f327212ef96 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 112:6f327212ef96 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 112:6f327212ef96 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 112:6f327212ef96 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 112:6f327212ef96 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 112:6f327212ef96 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 112:6f327212ef96 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 112:6f327212ef96 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 112:6f327212ef96 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 112:6f327212ef96 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 112:6f327212ef96 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 112:6f327212ef96 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 112:6f327212ef96 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 112:6f327212ef96 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 112:6f327212ef96 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 112:6f327212ef96 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 112:6f327212ef96 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 112:6f327212ef96 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 112:6f327212ef96 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 112:6f327212ef96 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 112:6f327212ef96 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 112:6f327212ef96 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
Kojto 112:6f327212ef96 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
Kojto 112:6f327212ef96 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
Kojto 112:6f327212ef96 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
Kojto 112:6f327212ef96 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 112:6f327212ef96 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
Kojto 112:6f327212ef96 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 112:6f327212ef96 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 112:6f327212ef96 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 112:6f327212ef96 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
Kojto 112:6f327212ef96 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
Kojto 112:6f327212ef96 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 112:6f327212ef96 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 112:6f327212ef96 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 112:6f327212ef96 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 112:6f327212ef96 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 112:6f327212ef96 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 112:6f327212ef96 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 112:6f327212ef96 159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
Kojto 112:6f327212ef96 160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
Kojto 112:6f327212ef96 161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
Kojto 112:6f327212ef96 162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
Kojto 112:6f327212ef96 163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 112:6f327212ef96 164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 112:6f327212ef96 165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 112:6f327212ef96 166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 112:6f327212ef96 167 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 112:6f327212ef96 168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 112:6f327212ef96 169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 112:6f327212ef96 170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
Kojto 112:6f327212ef96 171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
Kojto 112:6f327212ef96 172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
Kojto 112:6f327212ef96 173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
Kojto 112:6f327212ef96 174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
Kojto 112:6f327212ef96 175 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 112:6f327212ef96 176 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 112:6f327212ef96 177 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
Kojto 112:6f327212ef96 178 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
Kojto 112:6f327212ef96 179 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
Kojto 112:6f327212ef96 180 CEC_IRQn = 93, /*!< CEC global Interrupt */
Kojto 112:6f327212ef96 181 SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
Kojto 112:6f327212ef96 182 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
Kojto 112:6f327212ef96 183 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
Kojto 112:6f327212ef96 184 } IRQn_Type;
Kojto 112:6f327212ef96 185
Kojto 112:6f327212ef96 186 /**
Kojto 112:6f327212ef96 187 * @}
Kojto 112:6f327212ef96 188 */
Kojto 112:6f327212ef96 189
Kojto 112:6f327212ef96 190 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 112:6f327212ef96 191 #include "system_stm32f4xx.h"
Kojto 112:6f327212ef96 192 #include <stdint.h>
Kojto 112:6f327212ef96 193
Kojto 112:6f327212ef96 194 /** @addtogroup Peripheral_registers_structures
Kojto 112:6f327212ef96 195 * @{
Kojto 112:6f327212ef96 196 */
Kojto 112:6f327212ef96 197
Kojto 112:6f327212ef96 198 /**
Kojto 112:6f327212ef96 199 * @brief Analog to Digital Converter
Kojto 112:6f327212ef96 200 */
Kojto 112:6f327212ef96 201
Kojto 112:6f327212ef96 202 typedef struct
Kojto 112:6f327212ef96 203 {
Kojto 112:6f327212ef96 204 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 205 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 112:6f327212ef96 206 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 112:6f327212ef96 207 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 112:6f327212ef96 208 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 112:6f327212ef96 209 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 112:6f327212ef96 210 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 112:6f327212ef96 211 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 112:6f327212ef96 212 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 112:6f327212ef96 213 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 112:6f327212ef96 214 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 112:6f327212ef96 215 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 112:6f327212ef96 216 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 112:6f327212ef96 217 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 112:6f327212ef96 218 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 112:6f327212ef96 219 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 112:6f327212ef96 220 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 112:6f327212ef96 221 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 112:6f327212ef96 222 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 112:6f327212ef96 223 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 112:6f327212ef96 224 } ADC_TypeDef;
Kojto 112:6f327212ef96 225
Kojto 112:6f327212ef96 226 typedef struct
Kojto 112:6f327212ef96 227 {
Kojto 112:6f327212ef96 228 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 112:6f327212ef96 229 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 112:6f327212ef96 230 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 112:6f327212ef96 231 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 112:6f327212ef96 232 } ADC_Common_TypeDef;
Kojto 112:6f327212ef96 233
Kojto 112:6f327212ef96 234
Kojto 112:6f327212ef96 235 /**
Kojto 112:6f327212ef96 236 * @brief Controller Area Network TxMailBox
Kojto 112:6f327212ef96 237 */
Kojto 112:6f327212ef96 238
Kojto 112:6f327212ef96 239 typedef struct
Kojto 112:6f327212ef96 240 {
Kojto 112:6f327212ef96 241 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 112:6f327212ef96 242 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 112:6f327212ef96 243 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 112:6f327212ef96 244 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 112:6f327212ef96 245 } CAN_TxMailBox_TypeDef;
Kojto 112:6f327212ef96 246
Kojto 112:6f327212ef96 247 /**
Kojto 112:6f327212ef96 248 * @brief Controller Area Network FIFOMailBox
Kojto 112:6f327212ef96 249 */
Kojto 112:6f327212ef96 250
Kojto 112:6f327212ef96 251 typedef struct
Kojto 112:6f327212ef96 252 {
Kojto 112:6f327212ef96 253 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 112:6f327212ef96 254 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 112:6f327212ef96 255 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 112:6f327212ef96 256 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 112:6f327212ef96 257 } CAN_FIFOMailBox_TypeDef;
Kojto 112:6f327212ef96 258
Kojto 112:6f327212ef96 259 /**
Kojto 112:6f327212ef96 260 * @brief Controller Area Network FilterRegister
Kojto 112:6f327212ef96 261 */
Kojto 112:6f327212ef96 262
Kojto 112:6f327212ef96 263 typedef struct
Kojto 112:6f327212ef96 264 {
Kojto 112:6f327212ef96 265 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 112:6f327212ef96 266 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 112:6f327212ef96 267 } CAN_FilterRegister_TypeDef;
Kojto 112:6f327212ef96 268
Kojto 112:6f327212ef96 269 /**
Kojto 112:6f327212ef96 270 * @brief Controller Area Network
Kojto 112:6f327212ef96 271 */
Kojto 112:6f327212ef96 272
Kojto 112:6f327212ef96 273 typedef struct
Kojto 112:6f327212ef96 274 {
Kojto 112:6f327212ef96 275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 112:6f327212ef96 279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 112:6f327212ef96 280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 112:6f327212ef96 281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 112:6f327212ef96 283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 112:6f327212ef96 284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 112:6f327212ef96 285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 112:6f327212ef96 286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 112:6f327212ef96 287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 112:6f327212ef96 288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 112:6f327212ef96 289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 112:6f327212ef96 290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 112:6f327212ef96 291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 112:6f327212ef96 292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 112:6f327212ef96 293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 112:6f327212ef96 294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 112:6f327212ef96 295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 112:6f327212ef96 296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 112:6f327212ef96 297 } CAN_TypeDef;
Kojto 112:6f327212ef96 298
Kojto 112:6f327212ef96 299 /**
Kojto 112:6f327212ef96 300 * @brief Consumer Electronics Control
Kojto 112:6f327212ef96 301 */
Kojto 112:6f327212ef96 302
Kojto 112:6f327212ef96 303 typedef struct
Kojto 112:6f327212ef96 304 {
Kojto 112:6f327212ef96 305 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 112:6f327212ef96 306 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 112:6f327212ef96 307 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 112:6f327212ef96 308 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 112:6f327212ef96 309 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 112:6f327212ef96 310 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 112:6f327212ef96 311 }CEC_TypeDef;
Kojto 112:6f327212ef96 312
Kojto 112:6f327212ef96 313 /**
Kojto 112:6f327212ef96 314 * @brief CRC calculation unit
Kojto 112:6f327212ef96 315 */
Kojto 112:6f327212ef96 316
Kojto 112:6f327212ef96 317 typedef struct
Kojto 112:6f327212ef96 318 {
Kojto 112:6f327212ef96 319 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 112:6f327212ef96 320 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 112:6f327212ef96 321 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 112:6f327212ef96 322 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 112:6f327212ef96 323 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 324 } CRC_TypeDef;
Kojto 112:6f327212ef96 325
Kojto 112:6f327212ef96 326 /**
Kojto 112:6f327212ef96 327 * @brief Digital to Analog Converter
Kojto 112:6f327212ef96 328 */
Kojto 112:6f327212ef96 329
Kojto 112:6f327212ef96 330 typedef struct
Kojto 112:6f327212ef96 331 {
Kojto 112:6f327212ef96 332 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 333 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 112:6f327212ef96 334 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 112:6f327212ef96 335 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 112:6f327212ef96 336 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 112:6f327212ef96 337 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 112:6f327212ef96 338 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 112:6f327212ef96 339 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 112:6f327212ef96 340 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 112:6f327212ef96 341 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 112:6f327212ef96 342 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 112:6f327212ef96 343 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 112:6f327212ef96 344 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 112:6f327212ef96 345 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 112:6f327212ef96 346 } DAC_TypeDef;
Kojto 112:6f327212ef96 347
Kojto 112:6f327212ef96 348 /**
Kojto 112:6f327212ef96 349 * @brief Debug MCU
Kojto 112:6f327212ef96 350 */
Kojto 112:6f327212ef96 351
Kojto 112:6f327212ef96 352 typedef struct
Kojto 112:6f327212ef96 353 {
Kojto 112:6f327212ef96 354 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 112:6f327212ef96 355 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 356 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 112:6f327212ef96 357 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 112:6f327212ef96 358 }DBGMCU_TypeDef;
Kojto 112:6f327212ef96 359
Kojto 112:6f327212ef96 360 /**
Kojto 112:6f327212ef96 361 * @brief DCMI
Kojto 112:6f327212ef96 362 */
Kojto 112:6f327212ef96 363
Kojto 112:6f327212ef96 364 typedef struct
Kojto 112:6f327212ef96 365 {
Kojto 112:6f327212ef96 366 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 367 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 368 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 369 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
Kojto 112:6f327212ef96 370 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
Kojto 112:6f327212ef96 371 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
Kojto 112:6f327212ef96 372 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
Kojto 112:6f327212ef96 373 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
Kojto 112:6f327212ef96 374 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
Kojto 112:6f327212ef96 375 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
Kojto 112:6f327212ef96 376 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
Kojto 112:6f327212ef96 377 } DCMI_TypeDef;
Kojto 112:6f327212ef96 378
Kojto 112:6f327212ef96 379 /**
Kojto 112:6f327212ef96 380 * @brief DMA Controller
Kojto 112:6f327212ef96 381 */
Kojto 112:6f327212ef96 382
Kojto 112:6f327212ef96 383 typedef struct
Kojto 112:6f327212ef96 384 {
Kojto 112:6f327212ef96 385 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 112:6f327212ef96 386 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 112:6f327212ef96 387 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 112:6f327212ef96 388 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 112:6f327212ef96 389 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 112:6f327212ef96 390 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 112:6f327212ef96 391 } DMA_Stream_TypeDef;
Kojto 112:6f327212ef96 392
Kojto 112:6f327212ef96 393 typedef struct
Kojto 112:6f327212ef96 394 {
Kojto 112:6f327212ef96 395 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 396 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 397 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 112:6f327212ef96 398 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 399 } DMA_TypeDef;
Kojto 112:6f327212ef96 400
Kojto 112:6f327212ef96 401
Kojto 112:6f327212ef96 402 /**
Kojto 112:6f327212ef96 403 * @brief External Interrupt/Event Controller
Kojto 112:6f327212ef96 404 */
Kojto 112:6f327212ef96 405
Kojto 112:6f327212ef96 406 typedef struct
Kojto 112:6f327212ef96 407 {
Kojto 112:6f327212ef96 408 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 112:6f327212ef96 409 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 112:6f327212ef96 410 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 112:6f327212ef96 411 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 112:6f327212ef96 412 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 112:6f327212ef96 413 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 112:6f327212ef96 414 } EXTI_TypeDef;
Kojto 112:6f327212ef96 415
Kojto 112:6f327212ef96 416 /**
Kojto 112:6f327212ef96 417 * @brief FLASH Registers
Kojto 112:6f327212ef96 418 */
Kojto 112:6f327212ef96 419
Kojto 112:6f327212ef96 420 typedef struct
Kojto 112:6f327212ef96 421 {
Kojto 112:6f327212ef96 422 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 423 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 112:6f327212ef96 424 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 112:6f327212ef96 425 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 426 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 112:6f327212ef96 427 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 112:6f327212ef96 428 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 112:6f327212ef96 429 } FLASH_TypeDef;
Kojto 112:6f327212ef96 430
Kojto 112:6f327212ef96 431 /**
Kojto 112:6f327212ef96 432 * @brief Flexible Memory Controller
Kojto 112:6f327212ef96 433 */
Kojto 112:6f327212ef96 434
Kojto 112:6f327212ef96 435 typedef struct
Kojto 112:6f327212ef96 436 {
Kojto 112:6f327212ef96 437 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
Kojto 112:6f327212ef96 438 } FMC_Bank1_TypeDef;
Kojto 112:6f327212ef96 439
Kojto 112:6f327212ef96 440 /**
Kojto 112:6f327212ef96 441 * @brief Flexible Memory Controller Bank1E
Kojto 112:6f327212ef96 442 */
Kojto 112:6f327212ef96 443
Kojto 112:6f327212ef96 444 typedef struct
Kojto 112:6f327212ef96 445 {
Kojto 112:6f327212ef96 446 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
Kojto 112:6f327212ef96 447 } FMC_Bank1E_TypeDef;
Kojto 112:6f327212ef96 448
Kojto 112:6f327212ef96 449 /**
Kojto 112:6f327212ef96 450 * @brief Flexible Memory Controller Bank3
Kojto 112:6f327212ef96 451 */
Kojto 112:6f327212ef96 452
Kojto 112:6f327212ef96 453 typedef struct
Kojto 112:6f327212ef96 454 {
Kojto 112:6f327212ef96 455 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
Kojto 112:6f327212ef96 456 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
Kojto 112:6f327212ef96 457 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
Kojto 112:6f327212ef96 458 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
Kojto 112:6f327212ef96 459 uint32_t RESERVED; /*!< Reserved, 0x90 */
Kojto 112:6f327212ef96 460 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
Kojto 112:6f327212ef96 461 } FMC_Bank3_TypeDef;
Kojto 112:6f327212ef96 462
Kojto 112:6f327212ef96 463 /**
Kojto 112:6f327212ef96 464 * @brief Flexible Memory Controller Bank5_6
Kojto 112:6f327212ef96 465 */
Kojto 112:6f327212ef96 466
Kojto 112:6f327212ef96 467 typedef struct
Kojto 112:6f327212ef96 468 {
Kojto 112:6f327212ef96 469 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
Kojto 112:6f327212ef96 470 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
Kojto 112:6f327212ef96 471 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
Kojto 112:6f327212ef96 472 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
Kojto 112:6f327212ef96 473 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
Kojto 112:6f327212ef96 474 } FMC_Bank5_6_TypeDef;
Kojto 112:6f327212ef96 475
Kojto 112:6f327212ef96 476 /**
Kojto 112:6f327212ef96 477 * @brief General Purpose I/O
Kojto 112:6f327212ef96 478 */
Kojto 112:6f327212ef96 479
Kojto 112:6f327212ef96 480 typedef struct
Kojto 112:6f327212ef96 481 {
Kojto 112:6f327212ef96 482 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 112:6f327212ef96 483 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 112:6f327212ef96 484 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 112:6f327212ef96 485 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 112:6f327212ef96 486 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 112:6f327212ef96 487 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 112:6f327212ef96 488 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 112:6f327212ef96 489 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 112:6f327212ef96 490 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 112:6f327212ef96 491 } GPIO_TypeDef;
Kojto 112:6f327212ef96 492
Kojto 112:6f327212ef96 493 /**
Kojto 112:6f327212ef96 494 * @brief System configuration controller
Kojto 112:6f327212ef96 495 */
Kojto 112:6f327212ef96 496
Kojto 112:6f327212ef96 497 typedef struct
Kojto 112:6f327212ef96 498 {
Kojto 112:6f327212ef96 499 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 112:6f327212ef96 500 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 501 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 112:6f327212ef96 502 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 112:6f327212ef96 503 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 112:6f327212ef96 504 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
Kojto 112:6f327212ef96 505 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
Kojto 112:6f327212ef96 506 } SYSCFG_TypeDef;
Kojto 112:6f327212ef96 507
Kojto 112:6f327212ef96 508 /**
Kojto 112:6f327212ef96 509 * @brief Inter-integrated Circuit Interface
Kojto 112:6f327212ef96 510 */
Kojto 112:6f327212ef96 511
Kojto 112:6f327212ef96 512 typedef struct
Kojto 112:6f327212ef96 513 {
Kojto 112:6f327212ef96 514 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 515 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 516 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 112:6f327212ef96 517 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 112:6f327212ef96 518 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 112:6f327212ef96 519 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 112:6f327212ef96 520 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 112:6f327212ef96 521 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 112:6f327212ef96 522 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 112:6f327212ef96 523 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 112:6f327212ef96 524 } I2C_TypeDef;
Kojto 112:6f327212ef96 525
Kojto 112:6f327212ef96 526 /**
Kojto 112:6f327212ef96 527 * @brief Inter-integrated Circuit Interface
Kojto 112:6f327212ef96 528 */
Kojto 112:6f327212ef96 529
Kojto 112:6f327212ef96 530 typedef struct
Kojto 112:6f327212ef96 531 {
Kojto 112:6f327212ef96 532 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 533 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 534 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
Kojto 112:6f327212ef96 535 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
Kojto 112:6f327212ef96 536 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
Kojto 112:6f327212ef96 537 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
Kojto 112:6f327212ef96 538 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 539 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
Kojto 112:6f327212ef96 540 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
Kojto 112:6f327212ef96 541 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
Kojto 112:6f327212ef96 542 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
Kojto 112:6f327212ef96 543 } FMPI2C_TypeDef;
Kojto 112:6f327212ef96 544
Kojto 112:6f327212ef96 545 /**
Kojto 112:6f327212ef96 546 * @brief Independent WATCHDOG
Kojto 112:6f327212ef96 547 */
Kojto 112:6f327212ef96 548
Kojto 112:6f327212ef96 549 typedef struct
Kojto 112:6f327212ef96 550 {
Kojto 112:6f327212ef96 551 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 112:6f327212ef96 552 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 112:6f327212ef96 553 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 112:6f327212ef96 554 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 555 } IWDG_TypeDef;
Kojto 112:6f327212ef96 556
Kojto 112:6f327212ef96 557 /**
Kojto 112:6f327212ef96 558 * @brief Power Control
Kojto 112:6f327212ef96 559 */
Kojto 112:6f327212ef96 560
Kojto 112:6f327212ef96 561 typedef struct
Kojto 112:6f327212ef96 562 {
Kojto 112:6f327212ef96 563 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 564 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 565 } PWR_TypeDef;
Kojto 112:6f327212ef96 566
Kojto 112:6f327212ef96 567 /**
Kojto 112:6f327212ef96 568 * @brief Reset and Clock Control
Kojto 112:6f327212ef96 569 */
Kojto 112:6f327212ef96 570
Kojto 112:6f327212ef96 571 typedef struct
Kojto 112:6f327212ef96 572 {
Kojto 112:6f327212ef96 573 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 574 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 575 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 112:6f327212ef96 576 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 112:6f327212ef96 577 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 112:6f327212ef96 578 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 112:6f327212ef96 579 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 112:6f327212ef96 580 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 112:6f327212ef96 581 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 112:6f327212ef96 582 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 112:6f327212ef96 583 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 112:6f327212ef96 584 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 112:6f327212ef96 585 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 112:6f327212ef96 586 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 112:6f327212ef96 587 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 112:6f327212ef96 588 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 112:6f327212ef96 589 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 112:6f327212ef96 590 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 112:6f327212ef96 591 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 112:6f327212ef96 592 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 112:6f327212ef96 593 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 112:6f327212ef96 594 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 112:6f327212ef96 595 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 112:6f327212ef96 596 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 112:6f327212ef96 597 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 112:6f327212ef96 598 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 112:6f327212ef96 599 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 112:6f327212ef96 600 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 112:6f327212ef96 601 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 112:6f327212ef96 602 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 112:6f327212ef96 603 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
Kojto 112:6f327212ef96 604 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
Kojto 112:6f327212ef96 605 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
Kojto 112:6f327212ef96 606 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
Kojto 112:6f327212ef96 607 } RCC_TypeDef;
Kojto 112:6f327212ef96 608
Kojto 112:6f327212ef96 609 /**
Kojto 112:6f327212ef96 610 * @brief Real-Time Clock
Kojto 112:6f327212ef96 611 */
Kojto 112:6f327212ef96 612
Kojto 112:6f327212ef96 613 typedef struct
Kojto 112:6f327212ef96 614 {
Kojto 112:6f327212ef96 615 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 112:6f327212ef96 616 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 112:6f327212ef96 617 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 618 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 619 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 112:6f327212ef96 620 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 112:6f327212ef96 621 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 112:6f327212ef96 622 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 112:6f327212ef96 623 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 112:6f327212ef96 624 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 112:6f327212ef96 625 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 112:6f327212ef96 626 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 112:6f327212ef96 627 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 112:6f327212ef96 628 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 112:6f327212ef96 629 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 112:6f327212ef96 630 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 112:6f327212ef96 631 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 112:6f327212ef96 632 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 112:6f327212ef96 633 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 112:6f327212ef96 634 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 112:6f327212ef96 635 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 112:6f327212ef96 636 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 112:6f327212ef96 637 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 112:6f327212ef96 638 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 112:6f327212ef96 639 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 112:6f327212ef96 640 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 112:6f327212ef96 641 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 112:6f327212ef96 642 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 112:6f327212ef96 643 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 112:6f327212ef96 644 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 112:6f327212ef96 645 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 112:6f327212ef96 646 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 112:6f327212ef96 647 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 112:6f327212ef96 648 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 112:6f327212ef96 649 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 112:6f327212ef96 650 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 112:6f327212ef96 651 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 112:6f327212ef96 652 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 112:6f327212ef96 653 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 112:6f327212ef96 654 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 112:6f327212ef96 655 } RTC_TypeDef;
Kojto 112:6f327212ef96 656
Kojto 112:6f327212ef96 657 /**
Kojto 112:6f327212ef96 658 * @brief Serial Audio Interface
Kojto 112:6f327212ef96 659 */
Kojto 112:6f327212ef96 660
Kojto 112:6f327212ef96 661 typedef struct
Kojto 112:6f327212ef96 662 {
Kojto 112:6f327212ef96 663 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 112:6f327212ef96 664 } SAI_TypeDef;
Kojto 112:6f327212ef96 665
Kojto 112:6f327212ef96 666 typedef struct
Kojto 112:6f327212ef96 667 {
Kojto 112:6f327212ef96 668 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 112:6f327212ef96 669 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 112:6f327212ef96 670 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 112:6f327212ef96 671 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 112:6f327212ef96 672 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 112:6f327212ef96 673 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 674 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 112:6f327212ef96 675 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 112:6f327212ef96 676 } SAI_Block_TypeDef;
Kojto 112:6f327212ef96 677
Kojto 112:6f327212ef96 678 /**
Kojto 112:6f327212ef96 679 * @brief SD host Interface
Kojto 112:6f327212ef96 680 */
Kojto 112:6f327212ef96 681
Kojto 112:6f327212ef96 682 typedef struct
Kojto 112:6f327212ef96 683 {
Kojto 112:6f327212ef96 684 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 685 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 112:6f327212ef96 686 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 112:6f327212ef96 687 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 112:6f327212ef96 688 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 112:6f327212ef96 689 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 112:6f327212ef96 690 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 112:6f327212ef96 691 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 112:6f327212ef96 692 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 112:6f327212ef96 693 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 112:6f327212ef96 694 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 112:6f327212ef96 695 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 112:6f327212ef96 696 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 112:6f327212ef96 697 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 112:6f327212ef96 698 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 112:6f327212ef96 699 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 112:6f327212ef96 700 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 112:6f327212ef96 701 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 112:6f327212ef96 702 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 112:6f327212ef96 703 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 112:6f327212ef96 704 } SDIO_TypeDef;
Kojto 112:6f327212ef96 705
Kojto 112:6f327212ef96 706 /**
Kojto 112:6f327212ef96 707 * @brief Serial Peripheral Interface
Kojto 112:6f327212ef96 708 */
Kojto 112:6f327212ef96 709
Kojto 112:6f327212ef96 710 typedef struct
Kojto 112:6f327212ef96 711 {
Kojto 112:6f327212ef96 712 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 112:6f327212ef96 713 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 714 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 715 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 112:6f327212ef96 716 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 112:6f327212ef96 717 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 112:6f327212ef96 718 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 112:6f327212ef96 719 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 112:6f327212ef96 720 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 112:6f327212ef96 721 } SPI_TypeDef;
Kojto 112:6f327212ef96 722
Kojto 112:6f327212ef96 723 /**
Kojto 112:6f327212ef96 724 * @brief QUAD Serial Peripheral Interface
Kojto 112:6f327212ef96 725 */
Kojto 112:6f327212ef96 726
Kojto 112:6f327212ef96 727 typedef struct
Kojto 112:6f327212ef96 728 {
Kojto 112:6f327212ef96 729 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 730 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 731 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 732 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 733 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 112:6f327212ef96 734 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 112:6f327212ef96 735 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 112:6f327212ef96 736 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 112:6f327212ef96 737 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 112:6f327212ef96 738 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 112:6f327212ef96 739 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 112:6f327212ef96 740 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 112:6f327212ef96 741 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 112:6f327212ef96 742 } QUADSPI_TypeDef;
Kojto 112:6f327212ef96 743
Kojto 112:6f327212ef96 744 /**
Kojto 112:6f327212ef96 745 * @brief SPDIFRX Interface
Kojto 112:6f327212ef96 746 */
Kojto 112:6f327212ef96 747
Kojto 112:6f327212ef96 748 typedef struct
Kojto 112:6f327212ef96 749 {
Kojto 112:6f327212ef96 750 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 751 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
Kojto 112:6f327212ef96 752 uint16_t RESERVED0; /*!< Reserved, 0x06 */
Kojto 112:6f327212ef96 753 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 754 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 755 uint16_t RESERVED1; /*!< Reserved, 0x0E */
Kojto 112:6f327212ef96 756 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
Kojto 112:6f327212ef96 757 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
Kojto 112:6f327212ef96 758 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
Kojto 112:6f327212ef96 759 uint16_t RESERVED2; /*!< Reserved, 0x1A */
Kojto 112:6f327212ef96 760 } SPDIFRX_TypeDef;
Kojto 112:6f327212ef96 761
Kojto 112:6f327212ef96 762 /**
Kojto 112:6f327212ef96 763 * @brief TIM
Kojto 112:6f327212ef96 764 */
Kojto 112:6f327212ef96 765
Kojto 112:6f327212ef96 766 typedef struct
Kojto 112:6f327212ef96 767 {
Kojto 112:6f327212ef96 768 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 769 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 770 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 771 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 112:6f327212ef96 772 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 112:6f327212ef96 773 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 112:6f327212ef96 774 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 112:6f327212ef96 775 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 112:6f327212ef96 776 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 112:6f327212ef96 777 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 112:6f327212ef96 778 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 112:6f327212ef96 779 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 112:6f327212ef96 780 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 112:6f327212ef96 781 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 112:6f327212ef96 782 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 112:6f327212ef96 783 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 112:6f327212ef96 784 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 112:6f327212ef96 785 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 112:6f327212ef96 786 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 112:6f327212ef96 787 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 112:6f327212ef96 788 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 112:6f327212ef96 789 } TIM_TypeDef;
Kojto 112:6f327212ef96 790
Kojto 112:6f327212ef96 791 /**
Kojto 112:6f327212ef96 792 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 112:6f327212ef96 793 */
Kojto 112:6f327212ef96 794
Kojto 112:6f327212ef96 795 typedef struct
Kojto 112:6f327212ef96 796 {
Kojto 112:6f327212ef96 797 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 798 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 112:6f327212ef96 799 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 112:6f327212ef96 800 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 112:6f327212ef96 801 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 112:6f327212ef96 802 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 112:6f327212ef96 803 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 112:6f327212ef96 804 } USART_TypeDef;
Kojto 112:6f327212ef96 805
Kojto 112:6f327212ef96 806 /**
Kojto 112:6f327212ef96 807 * @brief Window WATCHDOG
Kojto 112:6f327212ef96 808 */
Kojto 112:6f327212ef96 809
Kojto 112:6f327212ef96 810 typedef struct
Kojto 112:6f327212ef96 811 {
Kojto 112:6f327212ef96 812 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 813 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 814 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 815 } WWDG_TypeDef;
Kojto 112:6f327212ef96 816
Kojto 112:6f327212ef96 817 /**
Kojto 112:6f327212ef96 818 * @brief USB_OTG_Core_Registers
Kojto 112:6f327212ef96 819 */
Kojto 112:6f327212ef96 820 typedef struct
Kojto 112:6f327212ef96 821 {
Kojto 112:6f327212ef96 822 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
Kojto 112:6f327212ef96 823 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
Kojto 112:6f327212ef96 824 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
Kojto 112:6f327212ef96 825 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
Kojto 112:6f327212ef96 826 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
Kojto 112:6f327212ef96 827 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
Kojto 112:6f327212ef96 828 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
Kojto 112:6f327212ef96 829 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
Kojto 112:6f327212ef96 830 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
Kojto 112:6f327212ef96 831 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
Kojto 112:6f327212ef96 832 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
Kojto 112:6f327212ef96 833 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
Kojto 112:6f327212ef96 834 uint32_t Reserved30[2]; /*!< Reserved 030h */
Kojto 112:6f327212ef96 835 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
Kojto 112:6f327212ef96 836 __IO uint32_t CID; /*!< User ID Register 03Ch */
Kojto 112:6f327212ef96 837 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
Kojto 112:6f327212ef96 838 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
Kojto 112:6f327212ef96 839 uint32_t Reserved6; /*!< Reserved 050h */
Kojto 112:6f327212ef96 840 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
Kojto 122:f9eeca106725 841 uint32_t Reserved; /*!< Reserved 058h */
Kojto 112:6f327212ef96 842 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
Kojto 122:f9eeca106725 843 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
Kojto 112:6f327212ef96 844 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
Kojto 112:6f327212ef96 845 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 112:6f327212ef96 846 } USB_OTG_GlobalTypeDef;
Kojto 112:6f327212ef96 847
Kojto 112:6f327212ef96 848 /**
Kojto 112:6f327212ef96 849 * @brief USB_OTG_device_Registers
Kojto 112:6f327212ef96 850 */
Kojto 112:6f327212ef96 851 typedef struct
Kojto 112:6f327212ef96 852 {
Kojto 112:6f327212ef96 853 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
Kojto 112:6f327212ef96 854 __IO uint32_t DCTL; /*!< dev Control Register 804h */
Kojto 112:6f327212ef96 855 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
Kojto 112:6f327212ef96 856 uint32_t Reserved0C; /*!< Reserved 80Ch */
Kojto 112:6f327212ef96 857 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
Kojto 112:6f327212ef96 858 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
Kojto 112:6f327212ef96 859 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
Kojto 112:6f327212ef96 860 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
Kojto 112:6f327212ef96 861 uint32_t Reserved20; /*!< Reserved 820h */
Kojto 112:6f327212ef96 862 uint32_t Reserved9; /*!< Reserved 824h */
Kojto 112:6f327212ef96 863 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
Kojto 112:6f327212ef96 864 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
Kojto 112:6f327212ef96 865 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
Kojto 112:6f327212ef96 866 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
Kojto 112:6f327212ef96 867 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
Kojto 112:6f327212ef96 868 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
Kojto 112:6f327212ef96 869 uint32_t Reserved40; /*!< dedicated EP mask 840h */
Kojto 112:6f327212ef96 870 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
Kojto 112:6f327212ef96 871 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
Kojto 112:6f327212ef96 872 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
Kojto 112:6f327212ef96 873 } USB_OTG_DeviceTypeDef;
Kojto 112:6f327212ef96 874
Kojto 112:6f327212ef96 875 /**
Kojto 112:6f327212ef96 876 * @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto 112:6f327212ef96 877 */
Kojto 112:6f327212ef96 878 typedef struct
Kojto 112:6f327212ef96 879 {
Kojto 112:6f327212ef96 880 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 112:6f327212ef96 881 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
Kojto 112:6f327212ef96 882 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 112:6f327212ef96 883 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 112:6f327212ef96 884 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 112:6f327212ef96 885 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 112:6f327212ef96 886 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 112:6f327212ef96 887 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 112:6f327212ef96 888 } USB_OTG_INEndpointTypeDef;
Kojto 112:6f327212ef96 889
Kojto 112:6f327212ef96 890 /**
Kojto 112:6f327212ef96 891 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto 112:6f327212ef96 892 */
Kojto 112:6f327212ef96 893 typedef struct
Kojto 112:6f327212ef96 894 {
Kojto 112:6f327212ef96 895 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
Kojto 112:6f327212ef96 896 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
Kojto 112:6f327212ef96 897 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
Kojto 112:6f327212ef96 898 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
Kojto 112:6f327212ef96 899 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
Kojto 112:6f327212ef96 900 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
Kojto 112:6f327212ef96 901 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto 112:6f327212ef96 902 } USB_OTG_OUTEndpointTypeDef;
Kojto 112:6f327212ef96 903
Kojto 112:6f327212ef96 904 /**
Kojto 112:6f327212ef96 905 * @brief USB_OTG_Host_Mode_Register_Structures
Kojto 112:6f327212ef96 906 */
Kojto 112:6f327212ef96 907 typedef struct
Kojto 112:6f327212ef96 908 {
Kojto 112:6f327212ef96 909 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
Kojto 112:6f327212ef96 910 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
Kojto 112:6f327212ef96 911 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
Kojto 112:6f327212ef96 912 uint32_t Reserved40C; /*!< Reserved 40Ch */
Kojto 112:6f327212ef96 913 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
Kojto 112:6f327212ef96 914 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
Kojto 112:6f327212ef96 915 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
Kojto 112:6f327212ef96 916 } USB_OTG_HostTypeDef;
Kojto 112:6f327212ef96 917
Kojto 112:6f327212ef96 918 /**
Kojto 112:6f327212ef96 919 * @brief USB_OTG_Host_Channel_Specific_Registers
Kojto 112:6f327212ef96 920 */
Kojto 112:6f327212ef96 921 typedef struct
Kojto 112:6f327212ef96 922 {
Kojto 112:6f327212ef96 923 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
Kojto 112:6f327212ef96 924 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
Kojto 112:6f327212ef96 925 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
Kojto 112:6f327212ef96 926 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
Kojto 112:6f327212ef96 927 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
Kojto 112:6f327212ef96 928 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
Kojto 112:6f327212ef96 929 uint32_t Reserved[2]; /*!< Reserved */
Kojto 112:6f327212ef96 930 } USB_OTG_HostChannelTypeDef;
Kojto 112:6f327212ef96 931
Kojto 112:6f327212ef96 932 /**
Kojto 112:6f327212ef96 933 * @}
Kojto 112:6f327212ef96 934 */
Kojto 112:6f327212ef96 935
Kojto 112:6f327212ef96 936 /** @addtogroup Peripheral_memory_map
Kojto 112:6f327212ef96 937 * @{
Kojto 112:6f327212ef96 938 */
Kojto 122:f9eeca106725 939 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 122:f9eeca106725 940 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
Kojto 122:f9eeca106725 941 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
Kojto 122:f9eeca106725 942 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
Kojto 122:f9eeca106725 943 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 122:f9eeca106725 944 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
Kojto 122:f9eeca106725 945 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
Kojto 122:f9eeca106725 946
Kojto 122:f9eeca106725 947 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 948 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 949 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
Kojto 122:f9eeca106725 950 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 951 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
Kojto 112:6f327212ef96 952
Kojto 112:6f327212ef96 953 /* Legacy defines */
Kojto 112:6f327212ef96 954 #define SRAM_BASE SRAM1_BASE
Kojto 112:6f327212ef96 955 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 112:6f327212ef96 956
Kojto 112:6f327212ef96 957
Kojto 112:6f327212ef96 958 /*!< Peripheral memory map */
Kojto 112:6f327212ef96 959 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 960 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 961 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 962 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
Kojto 112:6f327212ef96 963
Kojto 112:6f327212ef96 964 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 965 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 966 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 967 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 968 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 969 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 970 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 971 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 972 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 973 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 974 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 975 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 976 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 977 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 978 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 979 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 980 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 981 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 982 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
Kojto 122:f9eeca106725 983 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
Kojto 122:f9eeca106725 984 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 985 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 986 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 987 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 988 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 989 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
Kojto 122:f9eeca106725 990 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
Kojto 122:f9eeca106725 991 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto 122:f9eeca106725 992 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto 112:6f327212ef96 993
Kojto 112:6f327212ef96 994 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 995 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 996 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 997 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 998 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 999 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 1000 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
Kojto 122:f9eeca106725 1001 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
Kojto 122:f9eeca106725 1002 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto 122:f9eeca106725 1003 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 1004 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1005 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 1006 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 1007 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 1008 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 1009 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 1010 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 1011 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 1012 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
Kojto 122:f9eeca106725 1013 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
Kojto 122:f9eeca106725 1014 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 1015 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
Kojto 122:f9eeca106725 1016 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
Kojto 112:6f327212ef96 1017
Kojto 112:6f327212ef96 1018 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 1019 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 1020 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1021 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 1022 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 1023 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1024 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 1025 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 1026 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 1027 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1028 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 1029 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 1030 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 1031 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto 122:f9eeca106725 1032 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto 122:f9eeca106725 1033 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto 122:f9eeca106725 1034 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto 122:f9eeca106725 1035 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto 122:f9eeca106725 1036 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto 122:f9eeca106725 1037 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto 122:f9eeca106725 1038 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto 122:f9eeca106725 1039 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 1040 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto 122:f9eeca106725 1041 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto 122:f9eeca106725 1042 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto 122:f9eeca106725 1043 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto 122:f9eeca106725 1044 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto 122:f9eeca106725 1045 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto 122:f9eeca106725 1046 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto 122:f9eeca106725 1047 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
Kojto 112:6f327212ef96 1048
Kojto 112:6f327212ef96 1049 /*!< AHB2 peripherals */
Kojto 122:f9eeca106725 1050 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
Kojto 112:6f327212ef96 1051
Kojto 112:6f327212ef96 1052 /*!< FMC Bankx registers base address */
Kojto 122:f9eeca106725 1053 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
Kojto 122:f9eeca106725 1054 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
Kojto 122:f9eeca106725 1055 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
Kojto 122:f9eeca106725 1056 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
Kojto 112:6f327212ef96 1057
Kojto 112:6f327212ef96 1058 /*!< Debug MCU registers base address */
Kojto 122:f9eeca106725 1059 #define DBGMCU_BASE 0xE0042000U
Kojto 112:6f327212ef96 1060
Kojto 112:6f327212ef96 1061 /*!< USB registers base address */
Kojto 122:f9eeca106725 1062 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
Kojto 122:f9eeca106725 1063 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto 122:f9eeca106725 1064
Kojto 122:f9eeca106725 1065 #define USB_OTG_GLOBAL_BASE 0x000U
Kojto 122:f9eeca106725 1066 #define USB_OTG_DEVICE_BASE 0x800U
Kojto 122:f9eeca106725 1067 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto 122:f9eeca106725 1068 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto 122:f9eeca106725 1069 #define USB_OTG_EP_REG_SIZE 0x20U
Kojto 122:f9eeca106725 1070 #define USB_OTG_HOST_BASE 0x400U
Kojto 122:f9eeca106725 1071 #define USB_OTG_HOST_PORT_BASE 0x440U
Kojto 122:f9eeca106725 1072 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto 122:f9eeca106725 1073 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto 122:f9eeca106725 1074 #define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto 122:f9eeca106725 1075 #define USB_OTG_FIFO_BASE 0x1000U
Kojto 122:f9eeca106725 1076 #define USB_OTG_FIFO_SIZE 0x1000U
Kojto 112:6f327212ef96 1077
Kojto 112:6f327212ef96 1078 /**
Kojto 112:6f327212ef96 1079 * @}
Kojto 112:6f327212ef96 1080 */
Kojto 112:6f327212ef96 1081
Kojto 112:6f327212ef96 1082 /** @addtogroup Peripheral_declaration
Kojto 112:6f327212ef96 1083 * @{
Kojto 112:6f327212ef96 1084 */
Kojto 112:6f327212ef96 1085 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 112:6f327212ef96 1086 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 112:6f327212ef96 1087 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 112:6f327212ef96 1088 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 112:6f327212ef96 1089 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 112:6f327212ef96 1090 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 112:6f327212ef96 1091 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto 112:6f327212ef96 1092 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto 112:6f327212ef96 1093 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 112:6f327212ef96 1094 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 112:6f327212ef96 1095 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 112:6f327212ef96 1096 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 112:6f327212ef96 1097 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 112:6f327212ef96 1098 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 112:6f327212ef96 1099 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto 112:6f327212ef96 1100 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 112:6f327212ef96 1101 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 112:6f327212ef96 1102 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 112:6f327212ef96 1103 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 112:6f327212ef96 1104 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 112:6f327212ef96 1105 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 112:6f327212ef96 1106 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 112:6f327212ef96 1107 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
Kojto 112:6f327212ef96 1108 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 112:6f327212ef96 1109 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto 112:6f327212ef96 1110 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 112:6f327212ef96 1111 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 112:6f327212ef96 1112 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 112:6f327212ef96 1113 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 112:6f327212ef96 1114 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto 112:6f327212ef96 1115 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 112:6f327212ef96 1116 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 112:6f327212ef96 1117 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 112:6f327212ef96 1118 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 112:6f327212ef96 1119 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 112:6f327212ef96 1120 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto 112:6f327212ef96 1121 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 112:6f327212ef96 1122 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 112:6f327212ef96 1123 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 112:6f327212ef96 1124 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 112:6f327212ef96 1125 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 112:6f327212ef96 1126 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 112:6f327212ef96 1127 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 112:6f327212ef96 1128 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 112:6f327212ef96 1129 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 112:6f327212ef96 1130 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 112:6f327212ef96 1131 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 112:6f327212ef96 1132 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto 112:6f327212ef96 1133 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto 112:6f327212ef96 1134 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto 112:6f327212ef96 1135
Kojto 112:6f327212ef96 1136 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 112:6f327212ef96 1137 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 112:6f327212ef96 1138 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 112:6f327212ef96 1139 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 112:6f327212ef96 1140 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 112:6f327212ef96 1141 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 112:6f327212ef96 1142 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 112:6f327212ef96 1143 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 112:6f327212ef96 1144 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 112:6f327212ef96 1145 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 112:6f327212ef96 1146 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 112:6f327212ef96 1147 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 112:6f327212ef96 1148 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 112:6f327212ef96 1149 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 112:6f327212ef96 1150 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 112:6f327212ef96 1151 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 112:6f327212ef96 1152 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 112:6f327212ef96 1153 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 112:6f327212ef96 1154 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 112:6f327212ef96 1155 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 112:6f327212ef96 1156 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 112:6f327212ef96 1157 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 112:6f327212ef96 1158 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 112:6f327212ef96 1159 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 112:6f327212ef96 1160 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 112:6f327212ef96 1161 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 112:6f327212ef96 1162 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 112:6f327212ef96 1163 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 112:6f327212ef96 1164 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 112:6f327212ef96 1165 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto 112:6f327212ef96 1166 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto 112:6f327212ef96 1167 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto 112:6f327212ef96 1168 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto 112:6f327212ef96 1169 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto 112:6f327212ef96 1170 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 112:6f327212ef96 1171
Kojto 112:6f327212ef96 1172 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 112:6f327212ef96 1173
Kojto 112:6f327212ef96 1174 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 112:6f327212ef96 1175 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto 112:6f327212ef96 1176
Kojto 112:6f327212ef96 1177 /**
Kojto 112:6f327212ef96 1178 * @}
Kojto 112:6f327212ef96 1179 */
Kojto 112:6f327212ef96 1180
Kojto 112:6f327212ef96 1181 /** @addtogroup Exported_constants
Kojto 112:6f327212ef96 1182 * @{
Kojto 112:6f327212ef96 1183 */
Kojto 112:6f327212ef96 1184
Kojto 112:6f327212ef96 1185 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 112:6f327212ef96 1186 * @{
Kojto 112:6f327212ef96 1187 */
Kojto 112:6f327212ef96 1188
Kojto 112:6f327212ef96 1189 /******************************************************************************/
Kojto 112:6f327212ef96 1190 /* Peripheral Registers_Bits_Definition */
Kojto 112:6f327212ef96 1191 /******************************************************************************/
Kojto 112:6f327212ef96 1192
Kojto 112:6f327212ef96 1193 /******************************************************************************/
Kojto 112:6f327212ef96 1194 /* */
Kojto 112:6f327212ef96 1195 /* Analog to Digital Converter */
Kojto 112:6f327212ef96 1196 /* */
Kojto 112:6f327212ef96 1197 /******************************************************************************/
Kojto 112:6f327212ef96 1198 /******************** Bit definition for ADC_SR register ********************/
Kojto 122:f9eeca106725 1199 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
Kojto 122:f9eeca106725 1200 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
Kojto 122:f9eeca106725 1201 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
Kojto 122:f9eeca106725 1202 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
Kojto 122:f9eeca106725 1203 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
Kojto 122:f9eeca106725 1204 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
Kojto 112:6f327212ef96 1205
Kojto 112:6f327212ef96 1206 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 122:f9eeca106725 1207 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 122:f9eeca106725 1208 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1209 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1210 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1211 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1212 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1213 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
Kojto 122:f9eeca106725 1214 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
Kojto 122:f9eeca106725 1215 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
Kojto 122:f9eeca106725 1216 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
Kojto 122:f9eeca106725 1217 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
Kojto 122:f9eeca106725 1218 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
Kojto 122:f9eeca106725 1219 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
Kojto 122:f9eeca106725 1220 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
Kojto 122:f9eeca106725 1221 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 122:f9eeca106725 1222 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1223 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1224 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1225 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
Kojto 122:f9eeca106725 1226 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
Kojto 122:f9eeca106725 1227 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
Kojto 122:f9eeca106725 1228 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1229 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1230 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
Kojto 112:6f327212ef96 1231
Kojto 112:6f327212ef96 1232 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 122:f9eeca106725 1233 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
Kojto 122:f9eeca106725 1234 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
Kojto 122:f9eeca106725 1235 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
Kojto 122:f9eeca106725 1236 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
Kojto 122:f9eeca106725 1237 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
Kojto 122:f9eeca106725 1238 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
Kojto 122:f9eeca106725 1239 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 122:f9eeca106725 1240 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1241 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1242 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1243 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1244 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 122:f9eeca106725 1245 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1246 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1247 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
Kojto 122:f9eeca106725 1248 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 122:f9eeca106725 1249 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1250 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1251 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1252 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1253 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 122:f9eeca106725 1254 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1255 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1256 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
Kojto 112:6f327212ef96 1257
Kojto 112:6f327212ef96 1258 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 122:f9eeca106725 1259 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 122:f9eeca106725 1260 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1261 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1262 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1263 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 122:f9eeca106725 1264 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1265 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1266 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1267 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 122:f9eeca106725 1268 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1269 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1270 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1271 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 122:f9eeca106725 1272 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1273 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1274 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1275 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 122:f9eeca106725 1276 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1277 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1278 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1279 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 122:f9eeca106725 1280 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1281 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1282 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1283 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 122:f9eeca106725 1284 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1285 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1286 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1287 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 122:f9eeca106725 1288 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1289 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1290 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1291 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 122:f9eeca106725 1292 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1293 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1294 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
Kojto 112:6f327212ef96 1295
Kojto 112:6f327212ef96 1296 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 122:f9eeca106725 1297 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 122:f9eeca106725 1298 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1299 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1300 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1301 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 122:f9eeca106725 1302 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1303 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1304 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1305 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 122:f9eeca106725 1306 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1307 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1308 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1309 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 122:f9eeca106725 1310 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1311 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1312 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1313 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 122:f9eeca106725 1314 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1315 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1316 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1317 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 122:f9eeca106725 1318 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1319 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1320 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1321 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 122:f9eeca106725 1322 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1323 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1324 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1325 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 122:f9eeca106725 1326 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1327 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1328 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1329 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 122:f9eeca106725 1330 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1331 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1332 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1333 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 122:f9eeca106725 1334 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1335 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1336 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
Kojto 112:6f327212ef96 1337
Kojto 112:6f327212ef96 1338 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 122:f9eeca106725 1339 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
Kojto 112:6f327212ef96 1340
Kojto 112:6f327212ef96 1341 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 122:f9eeca106725 1342 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
Kojto 112:6f327212ef96 1343
Kojto 112:6f327212ef96 1344 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 122:f9eeca106725 1345 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
Kojto 112:6f327212ef96 1346
Kojto 112:6f327212ef96 1347 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 122:f9eeca106725 1348 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
Kojto 112:6f327212ef96 1349
Kojto 112:6f327212ef96 1350 /******************* Bit definition for ADC_HTR register ********************/
Kojto 122:f9eeca106725 1351 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
Kojto 112:6f327212ef96 1352
Kojto 112:6f327212ef96 1353 /******************* Bit definition for ADC_LTR register ********************/
Kojto 122:f9eeca106725 1354 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
Kojto 112:6f327212ef96 1355
Kojto 112:6f327212ef96 1356 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 122:f9eeca106725 1357 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 122:f9eeca106725 1358 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1359 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1360 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1361 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1362 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1363 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 122:f9eeca106725 1364 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1365 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1366 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1367 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1368 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1369 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 122:f9eeca106725 1370 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1371 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1372 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1373 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1374 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1375 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 122:f9eeca106725 1376 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1377 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1378 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1379 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1380 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1381 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 122:f9eeca106725 1382 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1383 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1384 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1385 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
Kojto 112:6f327212ef96 1386
Kojto 112:6f327212ef96 1387 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 122:f9eeca106725 1388 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 122:f9eeca106725 1389 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1390 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1391 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1392 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1393 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1394 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 122:f9eeca106725 1395 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1396 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1397 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1398 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1399 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1400 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 122:f9eeca106725 1401 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1402 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1403 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1404 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1405 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1406 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 122:f9eeca106725 1407 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1408 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1409 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1410 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1411 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1412 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 122:f9eeca106725 1413 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1414 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1415 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1416 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1417 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1418 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 122:f9eeca106725 1419 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1420 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1421 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1422 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1423 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
Kojto 112:6f327212ef96 1424
Kojto 112:6f327212ef96 1425 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 122:f9eeca106725 1426 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 122:f9eeca106725 1427 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1428 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1429 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1430 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1431 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1432 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 122:f9eeca106725 1433 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1434 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1435 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1436 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1437 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1438 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 122:f9eeca106725 1439 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1440 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1441 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1442 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1443 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1444 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 122:f9eeca106725 1445 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1446 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1447 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1448 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1449 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1450 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 122:f9eeca106725 1451 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1452 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1453 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1454 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1455 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1456 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 122:f9eeca106725 1457 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1458 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1459 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1460 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1461 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
Kojto 112:6f327212ef96 1462
Kojto 112:6f327212ef96 1463 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 122:f9eeca106725 1464 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 122:f9eeca106725 1465 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1466 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1467 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1468 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1469 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1470 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 122:f9eeca106725 1471 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1472 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1473 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1474 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1475 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1476 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 122:f9eeca106725 1477 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1478 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1479 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1480 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1481 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1482 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 122:f9eeca106725 1483 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1484 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1485 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1486 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1487 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1488 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 122:f9eeca106725 1489 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1490 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
Kojto 112:6f327212ef96 1491
Kojto 112:6f327212ef96 1492 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 122:f9eeca106725 1493 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
Kojto 112:6f327212ef96 1494
Kojto 112:6f327212ef96 1495 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 122:f9eeca106725 1496 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
Kojto 112:6f327212ef96 1497
Kojto 112:6f327212ef96 1498 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 122:f9eeca106725 1499 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
Kojto 112:6f327212ef96 1500
Kojto 112:6f327212ef96 1501 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 122:f9eeca106725 1502 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
Kojto 112:6f327212ef96 1503
Kojto 112:6f327212ef96 1504 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1505 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
Kojto 122:f9eeca106725 1506 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
Kojto 112:6f327212ef96 1507
Kojto 112:6f327212ef96 1508 /******************* Bit definition for ADC_CSR register ********************/
Kojto 122:f9eeca106725 1509 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
Kojto 122:f9eeca106725 1510 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
Kojto 122:f9eeca106725 1511 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
Kojto 122:f9eeca106725 1512 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
Kojto 122:f9eeca106725 1513 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
Kojto 122:f9eeca106725 1514 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
Kojto 122:f9eeca106725 1515 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
Kojto 122:f9eeca106725 1516 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
Kojto 122:f9eeca106725 1517 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
Kojto 122:f9eeca106725 1518 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
Kojto 122:f9eeca106725 1519 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
Kojto 122:f9eeca106725 1520 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
Kojto 122:f9eeca106725 1521 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
Kojto 122:f9eeca106725 1522 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
Kojto 122:f9eeca106725 1523 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
Kojto 122:f9eeca106725 1524 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
Kojto 122:f9eeca106725 1525 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
Kojto 122:f9eeca106725 1526 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
Kojto 122:f9eeca106725 1527
Kojto 122:f9eeca106725 1528 /* Legacy defines */
Kojto 122:f9eeca106725 1529 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto 122:f9eeca106725 1530 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto 122:f9eeca106725 1531 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
Kojto 112:6f327212ef96 1532
Kojto 112:6f327212ef96 1533 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1534 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 122:f9eeca106725 1535 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1536 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1537 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1538 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1539 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1540 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 122:f9eeca106725 1541 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 1542 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 1543 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 1544 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 1545 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
Kojto 122:f9eeca106725 1546 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 122:f9eeca106725 1547 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1548 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1549 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 122:f9eeca106725 1550 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1551 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1552 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
Kojto 122:f9eeca106725 1553 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
Kojto 112:6f327212ef96 1554
Kojto 112:6f327212ef96 1555 /******************* Bit definition for ADC_CDR register ********************/
Kojto 122:f9eeca106725 1556 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
Kojto 122:f9eeca106725 1557 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
Kojto 112:6f327212ef96 1558
Kojto 112:6f327212ef96 1559 /******************************************************************************/
Kojto 112:6f327212ef96 1560 /* */
Kojto 112:6f327212ef96 1561 /* Controller Area Network */
Kojto 112:6f327212ef96 1562 /* */
Kojto 112:6f327212ef96 1563 /******************************************************************************/
Kojto 112:6f327212ef96 1564 /*!<CAN control and status registers */
Kojto 112:6f327212ef96 1565 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 1566 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
Kojto 122:f9eeca106725 1567 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 1568 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 1569 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 1570 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 1571 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 1572 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 1573 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 1574 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
Kojto 122:f9eeca106725 1575 #define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
Kojto 112:6f327212ef96 1576 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 1577 #define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 1578 #define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 1579 #define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
Kojto 122:f9eeca106725 1580 #define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 1581 #define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 1582 #define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
Kojto 122:f9eeca106725 1583 #define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
Kojto 122:f9eeca106725 1584 #define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
Kojto 122:f9eeca106725 1585 #define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
Kojto 112:6f327212ef96 1586
Kojto 112:6f327212ef96 1587 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 1588 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 1589 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 1590 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 1591 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 1592 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 1593 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 1594 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 1595 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 1596 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 1597 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 1598 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 1599 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 1600 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 1601 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 1602 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 1603 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
Kojto 122:f9eeca106725 1604
Kojto 122:f9eeca106725 1605 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 1606 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 1607 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 1608 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 1609
Kojto 122:f9eeca106725 1610 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 1611 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 1612 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 1613 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 112:6f327212ef96 1614
Kojto 112:6f327212ef96 1615 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 1616 #define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 1617 #define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 1618 #define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 1619 #define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
Kojto 112:6f327212ef96 1620
Kojto 112:6f327212ef96 1621 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 1622 #define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 1623 #define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 1624 #define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 1625 #define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
Kojto 112:6f327212ef96 1626
Kojto 112:6f327212ef96 1627 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 1628 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 1629 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1630 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1631 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1632 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 1633 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 1634 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 1635 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 1636 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 1637 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 1638 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 1639 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 1640 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 1641 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
Kojto 122:f9eeca106725 1642 #define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
Kojto 122:f9eeca106725 1643 #define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
Kojto 122:f9eeca106725 1644 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
Kojto 122:f9eeca106725 1645 #define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
Kojto 122:f9eeca106725 1646 #define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
Kojto 112:6f327212ef96 1647
Kojto 112:6f327212ef96 1648
Kojto 112:6f327212ef96 1649 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 1650 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
Kojto 122:f9eeca106725 1651 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
Kojto 122:f9eeca106725 1652 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 1653
Kojto 122:f9eeca106725 1654 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 1655 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 1656 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 1657 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 1658
Kojto 122:f9eeca106725 1659 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 1660 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
Kojto 112:6f327212ef96 1661
Kojto 112:6f327212ef96 1662 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 1663 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 1664 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
Kojto 122:f9eeca106725 1665 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1666 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1667 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1668 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1669 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
Kojto 122:f9eeca106725 1670 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1671 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1672 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1673 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 1674 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1675 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1676 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 1677 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
Kojto 112:6f327212ef96 1678
Kojto 112:6f327212ef96 1679
Kojto 112:6f327212ef96 1680 /*!<Mailbox registers */
Kojto 112:6f327212ef96 1681 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 1682 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1683 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1684 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1685 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1686 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1687
Kojto 112:6f327212ef96 1688 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 1689 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1690 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1691 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1692
Kojto 112:6f327212ef96 1693 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 1694 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1695 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1696 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1697 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 112:6f327212ef96 1698
Kojto 112:6f327212ef96 1699 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 1700 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1701 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1702 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1703 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 112:6f327212ef96 1704
Kojto 112:6f327212ef96 1705 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 1706 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1707 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1708 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1709 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1710 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1711
Kojto 112:6f327212ef96 1712 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 1713 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1714 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1715 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1716
Kojto 112:6f327212ef96 1717 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 1718 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1719 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1720 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1721 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 112:6f327212ef96 1722
Kojto 112:6f327212ef96 1723 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 1724 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1725 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1726 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1727 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 112:6f327212ef96 1728
Kojto 112:6f327212ef96 1729 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 1730 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 1731 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1732 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1733 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 1734 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1735
Kojto 112:6f327212ef96 1736 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 1737 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1738 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 1739 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1740
Kojto 112:6f327212ef96 1741 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 1742 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1743 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1744 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1745 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 112:6f327212ef96 1746
Kojto 112:6f327212ef96 1747 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 1748 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1749 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1750 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1751 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 112:6f327212ef96 1752
Kojto 112:6f327212ef96 1753 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 1754 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1755 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1756 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 1757 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1758
Kojto 112:6f327212ef96 1759 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 1760 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1761 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 1762 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1763
Kojto 112:6f327212ef96 1764 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 1765 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1766 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1767 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1768 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 112:6f327212ef96 1769
Kojto 112:6f327212ef96 1770 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 1771 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1772 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1773 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1774 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 112:6f327212ef96 1775
Kojto 112:6f327212ef96 1776 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 1777 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 1778 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 1779 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 1780 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1781
Kojto 112:6f327212ef96 1782 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 1783 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 1784 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 1785 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1786
Kojto 112:6f327212ef96 1787 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 1788 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 1789 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 1790 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 1791 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 112:6f327212ef96 1792
Kojto 112:6f327212ef96 1793 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 1794 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 1795 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 1796 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 1797 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 112:6f327212ef96 1798
Kojto 112:6f327212ef96 1799 /*!<CAN filter registers */
Kojto 112:6f327212ef96 1800 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 1801 #define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
Kojto 122:f9eeca106725 1802 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
Kojto 112:6f327212ef96 1803
Kojto 112:6f327212ef96 1804 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 1805 #define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
Kojto 122:f9eeca106725 1806 #define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 1807 #define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 1808 #define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 1809 #define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 1810 #define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 1811 #define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 1812 #define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 1813 #define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 1814 #define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 1815 #define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 1816 #define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 1817 #define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 1818 #define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 1819 #define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
Kojto 122:f9eeca106725 1820 #define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
Kojto 122:f9eeca106725 1821 #define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
Kojto 122:f9eeca106725 1822 #define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
Kojto 122:f9eeca106725 1823 #define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
Kojto 122:f9eeca106725 1824 #define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
Kojto 122:f9eeca106725 1825 #define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
Kojto 122:f9eeca106725 1826 #define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
Kojto 122:f9eeca106725 1827 #define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
Kojto 122:f9eeca106725 1828 #define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
Kojto 122:f9eeca106725 1829 #define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
Kojto 122:f9eeca106725 1830 #define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
Kojto 122:f9eeca106725 1831 #define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
Kojto 122:f9eeca106725 1832 #define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
Kojto 122:f9eeca106725 1833 #define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
Kojto 112:6f327212ef96 1834
Kojto 112:6f327212ef96 1835 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 1836 #define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 1837 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 1838 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 1839 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 1840 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 1841 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 1842 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 1843 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 1844 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 1845 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 1846 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 1847 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 1848 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 1849 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 1850 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
Kojto 122:f9eeca106725 1851 #define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
Kojto 122:f9eeca106725 1852 #define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
Kojto 122:f9eeca106725 1853 #define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
Kojto 122:f9eeca106725 1854 #define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
Kojto 122:f9eeca106725 1855 #define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
Kojto 122:f9eeca106725 1856 #define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
Kojto 122:f9eeca106725 1857 #define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
Kojto 122:f9eeca106725 1858 #define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
Kojto 122:f9eeca106725 1859 #define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
Kojto 122:f9eeca106725 1860 #define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
Kojto 122:f9eeca106725 1861 #define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
Kojto 122:f9eeca106725 1862 #define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
Kojto 122:f9eeca106725 1863 #define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
Kojto 122:f9eeca106725 1864 #define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
Kojto 112:6f327212ef96 1865
Kojto 112:6f327212ef96 1866 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 1867 #define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 1868 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
Kojto 122:f9eeca106725 1869 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
Kojto 122:f9eeca106725 1870 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
Kojto 122:f9eeca106725 1871 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
Kojto 122:f9eeca106725 1872 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
Kojto 122:f9eeca106725 1873 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
Kojto 122:f9eeca106725 1874 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
Kojto 122:f9eeca106725 1875 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
Kojto 122:f9eeca106725 1876 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
Kojto 122:f9eeca106725 1877 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
Kojto 122:f9eeca106725 1878 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
Kojto 122:f9eeca106725 1879 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
Kojto 122:f9eeca106725 1880 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
Kojto 122:f9eeca106725 1881 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
Kojto 122:f9eeca106725 1882 #define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
Kojto 122:f9eeca106725 1883 #define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
Kojto 122:f9eeca106725 1884 #define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
Kojto 122:f9eeca106725 1885 #define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
Kojto 122:f9eeca106725 1886 #define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
Kojto 122:f9eeca106725 1887 #define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
Kojto 122:f9eeca106725 1888 #define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
Kojto 122:f9eeca106725 1889 #define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
Kojto 122:f9eeca106725 1890 #define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
Kojto 122:f9eeca106725 1891 #define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
Kojto 122:f9eeca106725 1892 #define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
Kojto 122:f9eeca106725 1893 #define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
Kojto 122:f9eeca106725 1894 #define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
Kojto 122:f9eeca106725 1895 #define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
Kojto 112:6f327212ef96 1896
Kojto 112:6f327212ef96 1897 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 1898 #define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
Kojto 122:f9eeca106725 1899 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
Kojto 122:f9eeca106725 1900 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
Kojto 122:f9eeca106725 1901 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
Kojto 122:f9eeca106725 1902 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
Kojto 122:f9eeca106725 1903 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
Kojto 122:f9eeca106725 1904 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
Kojto 122:f9eeca106725 1905 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
Kojto 122:f9eeca106725 1906 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
Kojto 122:f9eeca106725 1907 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
Kojto 122:f9eeca106725 1908 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
Kojto 122:f9eeca106725 1909 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
Kojto 122:f9eeca106725 1910 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
Kojto 122:f9eeca106725 1911 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
Kojto 122:f9eeca106725 1912 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
Kojto 122:f9eeca106725 1913 #define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
Kojto 122:f9eeca106725 1914 #define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
Kojto 122:f9eeca106725 1915 #define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
Kojto 122:f9eeca106725 1916 #define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
Kojto 122:f9eeca106725 1917 #define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
Kojto 122:f9eeca106725 1918 #define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
Kojto 122:f9eeca106725 1919 #define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
Kojto 122:f9eeca106725 1920 #define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
Kojto 122:f9eeca106725 1921 #define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
Kojto 122:f9eeca106725 1922 #define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
Kojto 122:f9eeca106725 1923 #define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
Kojto 122:f9eeca106725 1924 #define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
Kojto 122:f9eeca106725 1925 #define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
Kojto 122:f9eeca106725 1926 #define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
Kojto 112:6f327212ef96 1927
Kojto 112:6f327212ef96 1928
Kojto 112:6f327212ef96 1929 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 1930 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1931 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1932 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1933 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1934 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1935 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1936 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1937 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1938 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1939 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1940 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1941 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1942 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1943 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1944 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1945 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1946 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1947 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1948 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1949 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1950 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1951 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1952 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1953 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1954 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1955 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1956 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1957 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1958 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1959 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1960 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1961 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 1962
Kojto 112:6f327212ef96 1963 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 1964 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1965 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 1966 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 1967 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 1968 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 1969 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 1970 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 1971 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 1972 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 1973 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 1974 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 1975 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 1976 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 1977 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 1978 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 1979 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 1980 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 1981 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 1982 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 1983 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 1984 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 1985 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 1986 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 1987 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 1988 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 1989 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 1990 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 1991 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 1992 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 1993 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 1994 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 1995 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 1996
Kojto 112:6f327212ef96 1997 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 1998 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 1999 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2000 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2001 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2002 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2003 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2004 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2005 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2006 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2007 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2008 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2009 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2010 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2011 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2012 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2013 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2014 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2015 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2016 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2017 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2018 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2019 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2020 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2021 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2022 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2023 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2024 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2025 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2026 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2027 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2028 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2029 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2030
Kojto 112:6f327212ef96 2031 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 2032 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2033 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2034 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2035 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2036 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2037 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2038 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2039 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2040 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2041 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2042 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2043 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2044 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2045 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2046 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2047 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2048 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2049 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2050 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2051 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2052 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2053 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2054 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2055 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2056 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2057 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2058 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2059 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2060 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2061 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2062 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2063 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2064
Kojto 112:6f327212ef96 2065 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 2066 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2067 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2068 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2069 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2070 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2071 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2072 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2073 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2074 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2075 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2076 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2077 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2078 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2079 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2080 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2081 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2082 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2083 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2084 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2085 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2086 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2087 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2088 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2089 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2090 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2091 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2092 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2093 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2094 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2095 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2096 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2097 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2098
Kojto 112:6f327212ef96 2099 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 2100 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2101 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2102 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2103 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2104 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2105 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2106 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2107 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2108 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2109 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2110 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2111 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2112 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2113 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2114 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2115 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2116 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2117 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2118 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2119 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2120 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2121 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2122 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2123 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2124 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2125 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2126 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2127 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2128 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2129 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2130 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2131 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2132
Kojto 112:6f327212ef96 2133 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 2134 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2135 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2136 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2137 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2138 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2139 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2140 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2141 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2142 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2143 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2144 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2145 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2146 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2147 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2148 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2149 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2150 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2151 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2152 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2153 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2154 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2155 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2156 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2157 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2158 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2159 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2160 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2161 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2162 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2163 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2164 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2165 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2166
Kojto 112:6f327212ef96 2167 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 2168 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2169 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2170 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2171 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2172 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2173 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2174 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2175 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2176 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2177 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2178 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2179 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2180 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2181 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2182 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2183 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2184 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2185 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2186 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2187 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2188 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2189 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2190 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2191 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2192 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2193 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2194 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2195 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2196 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2197 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2198 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2199 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2200
Kojto 112:6f327212ef96 2201 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 2202 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2203 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2204 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2205 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2206 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2207 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2208 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2209 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2210 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2211 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2212 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2213 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2214 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2215 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2216 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2217 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2218 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2219 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2220 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2221 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2222 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2223 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2224 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2225 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2226 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2227 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2228 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2229 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2230 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2231 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2232 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2233 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2234
Kojto 112:6f327212ef96 2235 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 2236 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2237 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2238 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2239 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2240 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2241 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2242 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2243 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2244 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2245 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2246 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2247 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2248 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2249 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2250 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2251 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2252 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2253 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2254 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2255 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2256 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2257 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2258 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2259 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2260 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2261 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2262 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2263 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2264 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2265 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2266 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2267 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2268
Kojto 112:6f327212ef96 2269 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 2270 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2271 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2272 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2273 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2274 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2275 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2276 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2277 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2278 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2279 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2280 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2281 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2282 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2283 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2284 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2285 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2286 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2287 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2288 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2289 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2290 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2291 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2292 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2293 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2294 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2295 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2296 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2297 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2298 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2299 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2300 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2301 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2302
Kojto 112:6f327212ef96 2303 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 2304 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2305 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2306 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2307 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2308 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2309 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2310 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2311 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2312 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2313 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2314 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2315 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2316 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2317 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2318 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2319 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2320 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2321 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2322 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2323 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2324 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2325 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2326 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2327 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2328 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2329 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2330 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2331 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2332 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2333 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2334 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2335 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2336
Kojto 112:6f327212ef96 2337 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 2338 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2339 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2340 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2341 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2342 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2343 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2344 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2345 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2346 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2347 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2348 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2349 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2350 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2351 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2352 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2353 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2354 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2355 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2356 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2357 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2358 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2359 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2360 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2361 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2362 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2363 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2364 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2365 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2366 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2367 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2368 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2369 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2370
Kojto 112:6f327212ef96 2371 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 2372 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2373 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2374 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2375 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2376 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2377 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2378 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2379 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2380 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2381 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2382 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2383 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2384 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2385 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2386 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2387 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2388 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2389 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2390 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2391 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2392 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2393 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2394 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2395 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2396 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2397 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2398 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2399 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2400 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2401 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2402 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2403 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2404
Kojto 112:6f327212ef96 2405 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 2406 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2407 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2408 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2409 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2410 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2411 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2412 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2413 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2414 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2415 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2416 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2417 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2418 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2419 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2420 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2421 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2422 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2423 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2424 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2425 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2426 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2427 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2428 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2429 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2430 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2431 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2432 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2433 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2434 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2435 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2436 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2437 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2438
Kojto 112:6f327212ef96 2439 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 2440 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2441 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2442 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2443 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2444 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2445 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2446 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2447 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2448 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2449 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2450 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2451 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2452 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2453 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2454 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2455 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2456 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2457 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2458 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2459 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2460 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2461 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2462 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2463 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2464 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2465 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2466 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2467 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2468 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2469 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2470 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2471 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2472
Kojto 112:6f327212ef96 2473 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 2474 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2475 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2476 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2477 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2478 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2479 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2480 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2481 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2482 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2483 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2484 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2485 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2486 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2487 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2488 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2489 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2490 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2491 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2492 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2493 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2494 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2495 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2496 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2497 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2498 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2499 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2500 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2501 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2502 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2503 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2504 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2505 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2506
Kojto 112:6f327212ef96 2507 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 2508 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2509 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2510 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2511 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2512 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2513 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2514 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2515 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2516 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2517 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2518 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2519 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2520 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2521 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2522 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2523 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2524 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2525 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2526 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2527 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2528 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2529 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2530 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2531 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2532 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2533 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2534 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2535 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2536 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2537 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2538 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2539 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2540
Kojto 112:6f327212ef96 2541 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 2542 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2543 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2544 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2545 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2546 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2547 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2548 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2549 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2550 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2551 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2552 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2553 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2554 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2555 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2556 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2557 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2558 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2559 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2560 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2561 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2562 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2563 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2564 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2565 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2566 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2567 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2568 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2569 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2570 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2571 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2572 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2573 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2574
Kojto 112:6f327212ef96 2575 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 2576 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2577 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2578 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2579 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2580 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2581 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2582 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2583 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2584 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2585 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2586 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2587 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2588 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2589 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2590 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2591 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2592 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2593 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2594 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2595 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2596 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2597 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2598 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2599 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2600 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2601 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2602 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2603 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2604 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2605 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2606 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2607 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2608
Kojto 112:6f327212ef96 2609 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 2610 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2611 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2612 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2613 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2614 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2615 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2616 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2617 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2618 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2619 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2620 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2621 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2622 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2623 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2624 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2625 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2626 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2627 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2628 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2629 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2630 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2631 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2632 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2633 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2634 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2635 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2636 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2637 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2638 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2639 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2640 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2641 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2642
Kojto 112:6f327212ef96 2643 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 2644 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2645 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2646 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2647 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2648 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2649 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2650 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2651 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2652 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2653 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2654 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2655 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2656 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2657 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2658 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2659 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2660 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2661 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2662 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2663 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2664 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2665 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2666 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2667 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2668 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2669 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2670 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2671 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2672 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2673 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2674 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2675 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2676
Kojto 112:6f327212ef96 2677 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 2678 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2679 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2680 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2681 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2682 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2683 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2684 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2685 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2686 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2687 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2688 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2689 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2690 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2691 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2692 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2693 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2694 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2695 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2696 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2697 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2698 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2699 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2700 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2701 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2702 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2703 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2704 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2705 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2706 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2707 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2708 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2709 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2710
Kojto 112:6f327212ef96 2711 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 2712 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2713 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2714 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2715 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2716 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2717 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2718 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2719 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2720 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2721 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2722 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2723 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2724 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2725 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2726 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2727 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2728 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2729 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2730 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2731 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2732 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2733 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2734 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2735 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2736 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2737 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2738 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2739 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2740 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2741 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2742 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2743 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2744
Kojto 112:6f327212ef96 2745 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 2746 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2747 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2748 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2749 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2750 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2751 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2752 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2753 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2754 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2755 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2756 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2757 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2758 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2759 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2760 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2761 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2762 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2763 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2764 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2765 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2766 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2767 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2768 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2769 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2770 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2771 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2772 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2773 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2774 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2775 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2776 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2777 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2778
Kojto 112:6f327212ef96 2779 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 2780 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2781 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2782 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2783 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2784 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2785 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2786 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2787 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2788 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2789 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2790 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2791 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2792 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2793 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2794 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2795 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2796 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2797 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2798 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2799 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2800 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2801 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2802 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2803 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2804 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2805 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2806 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2807 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2808 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2809 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2810 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2811 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2812
Kojto 112:6f327212ef96 2813 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 2814 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2815 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2816 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2817 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2818 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2819 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2820 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2821 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2822 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2823 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2824 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2825 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2826 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2827 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2828 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2829 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2830 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2831 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2832 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2833 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2834 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2835 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2836 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2837 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2838 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2839 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2840 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2841 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2842 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2843 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2844 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2845 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2846
Kojto 112:6f327212ef96 2847 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 2848 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2849 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2850 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2851 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2852 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2853 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2854 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2855 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2856 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2857 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2858 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2859 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2860 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2861 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2862 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2863 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2864 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2865 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2866 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2867 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2868 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2869 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2870 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2871 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2872 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2873 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2874 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2875 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2876 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2877 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2878 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2879 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2880
Kojto 112:6f327212ef96 2881 /******************************************************************************/
Kojto 112:6f327212ef96 2882 /* */
Kojto 112:6f327212ef96 2883 /* HDMI-CEC (CEC) */
Kojto 112:6f327212ef96 2884 /* */
Kojto 112:6f327212ef96 2885 /******************************************************************************/
Kojto 112:6f327212ef96 2886
Kojto 112:6f327212ef96 2887 /******************* Bit definition for CEC_CR register *********************/
Kojto 122:f9eeca106725 2888 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
Kojto 122:f9eeca106725 2889 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
Kojto 122:f9eeca106725 2890 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
Kojto 112:6f327212ef96 2891
Kojto 112:6f327212ef96 2892 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 122:f9eeca106725 2893 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
Kojto 122:f9eeca106725 2894 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
Kojto 122:f9eeca106725 2895 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
Kojto 122:f9eeca106725 2896 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
Kojto 122:f9eeca106725 2897 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Bit Period Error generation */
Kojto 122:f9eeca106725 2898 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
Kojto 122:f9eeca106725 2899 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast No error generation */
Kojto 122:f9eeca106725 2900 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
Kojto 122:f9eeca106725 2901 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
Kojto 112:6f327212ef96 2902
Kojto 112:6f327212ef96 2903 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 122:f9eeca106725 2904 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
Kojto 112:6f327212ef96 2905
Kojto 112:6f327212ef96 2906 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 122:f9eeca106725 2907 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
Kojto 112:6f327212ef96 2908
Kojto 112:6f327212ef96 2909 /******************* Bit definition for CEC_ISR register ********************/
Kojto 122:f9eeca106725 2910 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
Kojto 122:f9eeca106725 2911 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
Kojto 122:f9eeca106725 2912 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
Kojto 122:f9eeca106725 2913 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
Kojto 122:f9eeca106725 2914 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
Kojto 122:f9eeca106725 2915 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
Kojto 122:f9eeca106725 2916 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
Kojto 122:f9eeca106725 2917 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
Kojto 122:f9eeca106725 2918 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
Kojto 122:f9eeca106725 2919 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
Kojto 122:f9eeca106725 2920 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
Kojto 122:f9eeca106725 2921 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
Kojto 122:f9eeca106725 2922 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
Kojto 112:6f327212ef96 2923
Kojto 112:6f327212ef96 2924 /******************* Bit definition for CEC_IER register ********************/
Kojto 122:f9eeca106725 2925 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
Kojto 122:f9eeca106725 2926 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
Kojto 122:f9eeca106725 2927 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
Kojto 122:f9eeca106725 2928 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 122:f9eeca106725 2929 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable */
Kojto 122:f9eeca106725 2930 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 122:f9eeca106725 2931 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 122:f9eeca106725 2932 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
Kojto 122:f9eeca106725 2933 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
Kojto 122:f9eeca106725 2934 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
Kojto 122:f9eeca106725 2935 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 122:f9eeca106725 2936 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
Kojto 122:f9eeca106725 2937 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 112:6f327212ef96 2938
Kojto 112:6f327212ef96 2939 /******************************************************************************/
Kojto 112:6f327212ef96 2940 /* */
Kojto 112:6f327212ef96 2941 /* CRC calculation unit */
Kojto 112:6f327212ef96 2942 /* */
Kojto 112:6f327212ef96 2943 /******************************************************************************/
Kojto 112:6f327212ef96 2944 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 2945 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
Kojto 112:6f327212ef96 2946
Kojto 112:6f327212ef96 2947
Kojto 112:6f327212ef96 2948 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 2949 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
Kojto 112:6f327212ef96 2950
Kojto 112:6f327212ef96 2951
Kojto 112:6f327212ef96 2952 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 2953 #define CRC_CR_RESET 0x01U /*!< RESET bit */
Kojto 112:6f327212ef96 2954
Kojto 112:6f327212ef96 2955 /******************************************************************************/
Kojto 112:6f327212ef96 2956 /* */
Kojto 112:6f327212ef96 2957 /* Digital to Analog Converter */
Kojto 112:6f327212ef96 2958 /* */
Kojto 112:6f327212ef96 2959 /******************************************************************************/
Kojto 112:6f327212ef96 2960 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 2961 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
Kojto 122:f9eeca106725 2962 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 2963 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 2964
Kojto 122:f9eeca106725 2965 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 2966 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 2967 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 2968 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 2969
Kojto 122:f9eeca106725 2970 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 2971 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 2972 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 2973
Kojto 122:f9eeca106725 2974 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 2975 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 2976 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 2977 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 2978 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 2979
Kojto 122:f9eeca106725 2980 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
Kojto 122:f9eeca106725 2981 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
Kojto 122:f9eeca106725 2982 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
Kojto 122:f9eeca106725 2983 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 2984 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 2985
Kojto 122:f9eeca106725 2986 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 2987 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2988 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2989 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2990
Kojto 122:f9eeca106725 2991 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 2992 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2993 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2994
Kojto 122:f9eeca106725 2995 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 2996 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2997 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2998 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2999 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3000
Kojto 122:f9eeca106725 3001 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 3002 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
Kojto 112:6f327212ef96 3003
Kojto 112:6f327212ef96 3004 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 3005 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
Kojto 122:f9eeca106725 3006 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
Kojto 112:6f327212ef96 3007
Kojto 112:6f327212ef96 3008 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 3009 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
Kojto 112:6f327212ef96 3010
Kojto 112:6f327212ef96 3011 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 3012 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
Kojto 112:6f327212ef96 3013
Kojto 112:6f327212ef96 3014 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 3015 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
Kojto 112:6f327212ef96 3016
Kojto 112:6f327212ef96 3017 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 3018 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
Kojto 112:6f327212ef96 3019
Kojto 112:6f327212ef96 3020 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 3021 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
Kojto 112:6f327212ef96 3022
Kojto 112:6f327212ef96 3023 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 3024 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
Kojto 112:6f327212ef96 3025
Kojto 112:6f327212ef96 3026 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 3027 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 3028 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
Kojto 112:6f327212ef96 3029
Kojto 112:6f327212ef96 3030 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 3031 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 3032 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
Kojto 112:6f327212ef96 3033
Kojto 112:6f327212ef96 3034 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 3035 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 3036 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
Kojto 112:6f327212ef96 3037
Kojto 112:6f327212ef96 3038 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 3039 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
Kojto 112:6f327212ef96 3040
Kojto 112:6f327212ef96 3041 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 3042 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
Kojto 112:6f327212ef96 3043
Kojto 112:6f327212ef96 3044 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 3045 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 3046 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
Kojto 112:6f327212ef96 3047
Kojto 112:6f327212ef96 3048 /******************************************************************************/
Kojto 112:6f327212ef96 3049 /* */
Kojto 112:6f327212ef96 3050 /* Debug MCU */
Kojto 112:6f327212ef96 3051 /* */
Kojto 112:6f327212ef96 3052 /******************************************************************************/
Kojto 112:6f327212ef96 3053
Kojto 112:6f327212ef96 3054 /******************************************************************************/
Kojto 112:6f327212ef96 3055 /* */
Kojto 112:6f327212ef96 3056 /* DCMI */
Kojto 112:6f327212ef96 3057 /* */
Kojto 112:6f327212ef96 3058 /******************************************************************************/
Kojto 112:6f327212ef96 3059 /******************** Bits definition for DCMI_CR register ******************/
Kojto 122:f9eeca106725 3060 #define DCMI_CR_CAPTURE 0x00000001U
Kojto 122:f9eeca106725 3061 #define DCMI_CR_CM 0x00000002U
Kojto 122:f9eeca106725 3062 #define DCMI_CR_CROP 0x00000004U
Kojto 122:f9eeca106725 3063 #define DCMI_CR_JPEG 0x00000008U
Kojto 122:f9eeca106725 3064 #define DCMI_CR_ESS 0x00000010U
Kojto 122:f9eeca106725 3065 #define DCMI_CR_PCKPOL 0x00000020U
Kojto 122:f9eeca106725 3066 #define DCMI_CR_HSPOL 0x00000040U
Kojto 122:f9eeca106725 3067 #define DCMI_CR_VSPOL 0x00000080U
Kojto 122:f9eeca106725 3068 #define DCMI_CR_FCRC_0 0x00000100U
Kojto 122:f9eeca106725 3069 #define DCMI_CR_FCRC_1 0x00000200U
Kojto 122:f9eeca106725 3070 #define DCMI_CR_EDM_0 0x00000400U
Kojto 122:f9eeca106725 3071 #define DCMI_CR_EDM_1 0x00000800U
Kojto 122:f9eeca106725 3072 #define DCMI_CR_OUTEN 0x00002000U
Kojto 122:f9eeca106725 3073 #define DCMI_CR_ENABLE 0x00004000U
Kojto 122:f9eeca106725 3074 #define DCMI_CR_BSM_0 0x00010000U
Kojto 122:f9eeca106725 3075 #define DCMI_CR_BSM_1 0x00020000U
Kojto 122:f9eeca106725 3076 #define DCMI_CR_OEBS 0x00040000U
Kojto 122:f9eeca106725 3077 #define DCMI_CR_LSM 0x00080000U
Kojto 122:f9eeca106725 3078 #define DCMI_CR_OELS 0x00100000U
Kojto 112:6f327212ef96 3079
Kojto 112:6f327212ef96 3080 /******************** Bits definition for DCMI_SR register ******************/
Kojto 122:f9eeca106725 3081 #define DCMI_SR_HSYNC 0x00000001U
Kojto 122:f9eeca106725 3082 #define DCMI_SR_VSYNC 0x00000002U
Kojto 122:f9eeca106725 3083 #define DCMI_SR_FNE 0x00000004U
Kojto 122:f9eeca106725 3084
Kojto 122:f9eeca106725 3085 /******************** Bits definition for DCMI_RIS register ****************/
Kojto 122:f9eeca106725 3086 #define DCMI_RIS_FRAME_RIS 0x00000001U
Kojto 122:f9eeca106725 3087 #define DCMI_RIS_OVR_RIS 0x00000002U
Kojto 122:f9eeca106725 3088 #define DCMI_RIS_ERR_RIS 0x00000004U
Kojto 122:f9eeca106725 3089 #define DCMI_RIS_VSYNC_RIS 0x00000008U
Kojto 122:f9eeca106725 3090 #define DCMI_RIS_LINE_RIS 0x00000010U
Kojto 122:f9eeca106725 3091 /* Legacy defines */
Kojto 122:f9eeca106725 3092 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
Kojto 122:f9eeca106725 3093 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
Kojto 122:f9eeca106725 3094 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
Kojto 122:f9eeca106725 3095 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
Kojto 122:f9eeca106725 3096 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
Kojto 122:f9eeca106725 3097 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
Kojto 112:6f327212ef96 3098
Kojto 112:6f327212ef96 3099 /******************** Bits definition for DCMI_IER register *****************/
Kojto 122:f9eeca106725 3100 #define DCMI_IER_FRAME_IE 0x00000001U
Kojto 122:f9eeca106725 3101 #define DCMI_IER_OVR_IE 0x00000002U
Kojto 122:f9eeca106725 3102 #define DCMI_IER_ERR_IE 0x00000004U
Kojto 122:f9eeca106725 3103 #define DCMI_IER_VSYNC_IE 0x00000008U
Kojto 122:f9eeca106725 3104 #define DCMI_IER_LINE_IE 0x00000010U
Kojto 122:f9eeca106725 3105 /* Legacy defines */
Kojto 122:f9eeca106725 3106 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
Kojto 122:f9eeca106725 3107
Kojto 122:f9eeca106725 3108 /******************** Bits definition for DCMI_MIS register *****************/
Kojto 122:f9eeca106725 3109 #define DCMI_MIS_FRAME_MIS 0x00000001U
Kojto 122:f9eeca106725 3110 #define DCMI_MIS_OVR_MIS 0x00000002U
Kojto 122:f9eeca106725 3111 #define DCMI_MIS_ERR_MIS 0x00000004U
Kojto 122:f9eeca106725 3112 #define DCMI_MIS_VSYNC_MIS 0x00000008U
Kojto 122:f9eeca106725 3113 #define DCMI_MIS_LINE_MIS 0x00000010U
Kojto 122:f9eeca106725 3114
Kojto 122:f9eeca106725 3115 /* Legacy defines */
Kojto 122:f9eeca106725 3116 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
Kojto 122:f9eeca106725 3117 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
Kojto 122:f9eeca106725 3118 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
Kojto 122:f9eeca106725 3119 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
Kojto 122:f9eeca106725 3120 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
Kojto 112:6f327212ef96 3121
Kojto 112:6f327212ef96 3122 /******************** Bits definition for DCMI_ICR register *****************/
Kojto 122:f9eeca106725 3123 #define DCMI_ICR_FRAME_ISC 0x00000001U
Kojto 122:f9eeca106725 3124 #define DCMI_ICR_OVR_ISC 0x00000002U
Kojto 122:f9eeca106725 3125 #define DCMI_ICR_ERR_ISC 0x00000004U
Kojto 122:f9eeca106725 3126 #define DCMI_ICR_VSYNC_ISC 0x00000008U
Kojto 122:f9eeca106725 3127 #define DCMI_ICR_LINE_ISC 0x00000010U
Kojto 122:f9eeca106725 3128
Kojto 122:f9eeca106725 3129 /* Legacy defines */
Kojto 122:f9eeca106725 3130 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
Kojto 122:f9eeca106725 3131
Kojto 122:f9eeca106725 3132 /******************** Bits definition for DCMI_ESCR register ******************/
Kojto 122:f9eeca106725 3133 #define DCMI_ESCR_FSC 0x000000FFU
Kojto 122:f9eeca106725 3134 #define DCMI_ESCR_LSC 0x0000FF00U
Kojto 122:f9eeca106725 3135 #define DCMI_ESCR_LEC 0x00FF0000U
Kojto 122:f9eeca106725 3136 #define DCMI_ESCR_FEC 0xFF000000U
Kojto 122:f9eeca106725 3137
Kojto 122:f9eeca106725 3138 /******************** Bits definition for DCMI_ESUR register ******************/
Kojto 122:f9eeca106725 3139 #define DCMI_ESUR_FSU 0x000000FFU
Kojto 122:f9eeca106725 3140 #define DCMI_ESUR_LSU 0x0000FF00U
Kojto 122:f9eeca106725 3141 #define DCMI_ESUR_LEU 0x00FF0000U
Kojto 122:f9eeca106725 3142 #define DCMI_ESUR_FEU 0xFF000000U
Kojto 122:f9eeca106725 3143
Kojto 122:f9eeca106725 3144 /******************** Bits definition for DCMI_CWSTRT register ******************/
Kojto 122:f9eeca106725 3145 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
Kojto 122:f9eeca106725 3146 #define DCMI_CWSTRT_VST 0x1FFF0000U
Kojto 122:f9eeca106725 3147
Kojto 122:f9eeca106725 3148 /******************** Bits definition for DCMI_CWSIZE register ******************/
Kojto 122:f9eeca106725 3149 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
Kojto 122:f9eeca106725 3150 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
Kojto 122:f9eeca106725 3151
Kojto 122:f9eeca106725 3152 /******************** Bits definition for DCMI_DR register ******************/
Kojto 122:f9eeca106725 3153 #define DCMI_DR_BYTE0 0x000000FFU
Kojto 122:f9eeca106725 3154 #define DCMI_DR_BYTE1 0x0000FF00U
Kojto 122:f9eeca106725 3155 #define DCMI_DR_BYTE2 0x00FF0000U
Kojto 122:f9eeca106725 3156 #define DCMI_DR_BYTE3 0xFF000000U
Kojto 112:6f327212ef96 3157
Kojto 112:6f327212ef96 3158 /******************************************************************************/
Kojto 112:6f327212ef96 3159 /* */
Kojto 112:6f327212ef96 3160 /* DMA Controller */
Kojto 112:6f327212ef96 3161 /* */
Kojto 112:6f327212ef96 3162 /******************************************************************************/
Kojto 122:f9eeca106725 3163 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 122:f9eeca106725 3164 #define DMA_SxCR_CHSEL 0x0E000000U
Kojto 122:f9eeca106725 3165 #define DMA_SxCR_CHSEL_0 0x02000000U
Kojto 122:f9eeca106725 3166 #define DMA_SxCR_CHSEL_1 0x04000000U
Kojto 122:f9eeca106725 3167 #define DMA_SxCR_CHSEL_2 0x08000000U
Kojto 122:f9eeca106725 3168 #define DMA_SxCR_MBURST 0x01800000U
Kojto 122:f9eeca106725 3169 #define DMA_SxCR_MBURST_0 0x00800000U
Kojto 122:f9eeca106725 3170 #define DMA_SxCR_MBURST_1 0x01000000U
Kojto 122:f9eeca106725 3171 #define DMA_SxCR_PBURST 0x00600000U
Kojto 122:f9eeca106725 3172 #define DMA_SxCR_PBURST_0 0x00200000U
Kojto 122:f9eeca106725 3173 #define DMA_SxCR_PBURST_1 0x00400000U
Kojto 122:f9eeca106725 3174 #define DMA_SxCR_CT 0x00080000U
Kojto 122:f9eeca106725 3175 #define DMA_SxCR_DBM 0x00040000U
Kojto 122:f9eeca106725 3176 #define DMA_SxCR_PL 0x00030000U
Kojto 122:f9eeca106725 3177 #define DMA_SxCR_PL_0 0x00010000U
Kojto 122:f9eeca106725 3178 #define DMA_SxCR_PL_1 0x00020000U
Kojto 122:f9eeca106725 3179 #define DMA_SxCR_PINCOS 0x00008000U
Kojto 122:f9eeca106725 3180 #define DMA_SxCR_MSIZE 0x00006000U
Kojto 122:f9eeca106725 3181 #define DMA_SxCR_MSIZE_0 0x00002000U
Kojto 122:f9eeca106725 3182 #define DMA_SxCR_MSIZE_1 0x00004000U
Kojto 122:f9eeca106725 3183 #define DMA_SxCR_PSIZE 0x00001800U
Kojto 122:f9eeca106725 3184 #define DMA_SxCR_PSIZE_0 0x00000800U
Kojto 122:f9eeca106725 3185 #define DMA_SxCR_PSIZE_1 0x00001000U
Kojto 122:f9eeca106725 3186 #define DMA_SxCR_MINC 0x00000400U
Kojto 122:f9eeca106725 3187 #define DMA_SxCR_PINC 0x00000200U
Kojto 122:f9eeca106725 3188 #define DMA_SxCR_CIRC 0x00000100U
Kojto 122:f9eeca106725 3189 #define DMA_SxCR_DIR 0x000000C0U
Kojto 122:f9eeca106725 3190 #define DMA_SxCR_DIR_0 0x00000040U
Kojto 122:f9eeca106725 3191 #define DMA_SxCR_DIR_1 0x00000080U
Kojto 122:f9eeca106725 3192 #define DMA_SxCR_PFCTRL 0x00000020U
Kojto 122:f9eeca106725 3193 #define DMA_SxCR_TCIE 0x00000010U
Kojto 122:f9eeca106725 3194 #define DMA_SxCR_HTIE 0x00000008U
Kojto 122:f9eeca106725 3195 #define DMA_SxCR_TEIE 0x00000004U
Kojto 122:f9eeca106725 3196 #define DMA_SxCR_DMEIE 0x00000002U
Kojto 122:f9eeca106725 3197 #define DMA_SxCR_EN 0x00000001U
Kojto 122:f9eeca106725 3198
Kojto 122:f9eeca106725 3199 /* Legacy defines */
Kojto 122:f9eeca106725 3200 #define DMA_SxCR_ACK 0x00100000U
Kojto 112:6f327212ef96 3201
Kojto 112:6f327212ef96 3202 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 122:f9eeca106725 3203 #define DMA_SxNDT 0x0000FFFFU
Kojto 122:f9eeca106725 3204 #define DMA_SxNDT_0 0x00000001U
Kojto 122:f9eeca106725 3205 #define DMA_SxNDT_1 0x00000002U
Kojto 122:f9eeca106725 3206 #define DMA_SxNDT_2 0x00000004U
Kojto 122:f9eeca106725 3207 #define DMA_SxNDT_3 0x00000008U
Kojto 122:f9eeca106725 3208 #define DMA_SxNDT_4 0x00000010U
Kojto 122:f9eeca106725 3209 #define DMA_SxNDT_5 0x00000020U
Kojto 122:f9eeca106725 3210 #define DMA_SxNDT_6 0x00000040U
Kojto 122:f9eeca106725 3211 #define DMA_SxNDT_7 0x00000080U
Kojto 122:f9eeca106725 3212 #define DMA_SxNDT_8 0x00000100U
Kojto 122:f9eeca106725 3213 #define DMA_SxNDT_9 0x00000200U
Kojto 122:f9eeca106725 3214 #define DMA_SxNDT_10 0x00000400U
Kojto 122:f9eeca106725 3215 #define DMA_SxNDT_11 0x00000800U
Kojto 122:f9eeca106725 3216 #define DMA_SxNDT_12 0x00001000U
Kojto 122:f9eeca106725 3217 #define DMA_SxNDT_13 0x00002000U
Kojto 122:f9eeca106725 3218 #define DMA_SxNDT_14 0x00004000U
Kojto 122:f9eeca106725 3219 #define DMA_SxNDT_15 0x00008000U
Kojto 112:6f327212ef96 3220
Kojto 112:6f327212ef96 3221 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 122:f9eeca106725 3222 #define DMA_SxFCR_FEIE 0x00000080U
Kojto 122:f9eeca106725 3223 #define DMA_SxFCR_FS 0x00000038U
Kojto 122:f9eeca106725 3224 #define DMA_SxFCR_FS_0 0x00000008U
Kojto 122:f9eeca106725 3225 #define DMA_SxFCR_FS_1 0x00000010U
Kojto 122:f9eeca106725 3226 #define DMA_SxFCR_FS_2 0x00000020U
Kojto 122:f9eeca106725 3227 #define DMA_SxFCR_DMDIS 0x00000004U
Kojto 122:f9eeca106725 3228 #define DMA_SxFCR_FTH 0x00000003U
Kojto 122:f9eeca106725 3229 #define DMA_SxFCR_FTH_0 0x00000001U
Kojto 122:f9eeca106725 3230 #define DMA_SxFCR_FTH_1 0x00000002U
Kojto 112:6f327212ef96 3231
Kojto 112:6f327212ef96 3232 /******************** Bits definition for DMA_LISR register *****************/
Kojto 122:f9eeca106725 3233 #define DMA_LISR_TCIF3 0x08000000U
Kojto 122:f9eeca106725 3234 #define DMA_LISR_HTIF3 0x04000000U
Kojto 122:f9eeca106725 3235 #define DMA_LISR_TEIF3 0x02000000U
Kojto 122:f9eeca106725 3236 #define DMA_LISR_DMEIF3 0x01000000U
Kojto 122:f9eeca106725 3237 #define DMA_LISR_FEIF3 0x00400000U
Kojto 122:f9eeca106725 3238 #define DMA_LISR_TCIF2 0x00200000U
Kojto 122:f9eeca106725 3239 #define DMA_LISR_HTIF2 0x00100000U
Kojto 122:f9eeca106725 3240 #define DMA_LISR_TEIF2 0x00080000U
Kojto 122:f9eeca106725 3241 #define DMA_LISR_DMEIF2 0x00040000U
Kojto 122:f9eeca106725 3242 #define DMA_LISR_FEIF2 0x00010000U
Kojto 122:f9eeca106725 3243 #define DMA_LISR_TCIF1 0x00000800U
Kojto 122:f9eeca106725 3244 #define DMA_LISR_HTIF1 0x00000400U
Kojto 122:f9eeca106725 3245 #define DMA_LISR_TEIF1 0x00000200U
Kojto 122:f9eeca106725 3246 #define DMA_LISR_DMEIF1 0x00000100U
Kojto 122:f9eeca106725 3247 #define DMA_LISR_FEIF1 0x00000040U
Kojto 122:f9eeca106725 3248 #define DMA_LISR_TCIF0 0x00000020U
Kojto 122:f9eeca106725 3249 #define DMA_LISR_HTIF0 0x00000010U
Kojto 122:f9eeca106725 3250 #define DMA_LISR_TEIF0 0x00000008U
Kojto 122:f9eeca106725 3251 #define DMA_LISR_DMEIF0 0x00000004U
Kojto 122:f9eeca106725 3252 #define DMA_LISR_FEIF0 0x00000001U
Kojto 112:6f327212ef96 3253
Kojto 112:6f327212ef96 3254 /******************** Bits definition for DMA_HISR register *****************/
Kojto 122:f9eeca106725 3255 #define DMA_HISR_TCIF7 0x08000000U
Kojto 122:f9eeca106725 3256 #define DMA_HISR_HTIF7 0x04000000U
Kojto 122:f9eeca106725 3257 #define DMA_HISR_TEIF7 0x02000000U
Kojto 122:f9eeca106725 3258 #define DMA_HISR_DMEIF7 0x01000000U
Kojto 122:f9eeca106725 3259 #define DMA_HISR_FEIF7 0x00400000U
Kojto 122:f9eeca106725 3260 #define DMA_HISR_TCIF6 0x00200000U
Kojto 122:f9eeca106725 3261 #define DMA_HISR_HTIF6 0x00100000U
Kojto 122:f9eeca106725 3262 #define DMA_HISR_TEIF6 0x00080000U
Kojto 122:f9eeca106725 3263 #define DMA_HISR_DMEIF6 0x00040000U
Kojto 122:f9eeca106725 3264 #define DMA_HISR_FEIF6 0x00010000U
Kojto 122:f9eeca106725 3265 #define DMA_HISR_TCIF5 0x00000800U
Kojto 122:f9eeca106725 3266 #define DMA_HISR_HTIF5 0x00000400U
Kojto 122:f9eeca106725 3267 #define DMA_HISR_TEIF5 0x00000200U
Kojto 122:f9eeca106725 3268 #define DMA_HISR_DMEIF5 0x00000100U
Kojto 122:f9eeca106725 3269 #define DMA_HISR_FEIF5 0x00000040U
Kojto 122:f9eeca106725 3270 #define DMA_HISR_TCIF4 0x00000020U
Kojto 122:f9eeca106725 3271 #define DMA_HISR_HTIF4 0x00000010U
Kojto 122:f9eeca106725 3272 #define DMA_HISR_TEIF4 0x00000008U
Kojto 122:f9eeca106725 3273 #define DMA_HISR_DMEIF4 0x00000004U
Kojto 122:f9eeca106725 3274 #define DMA_HISR_FEIF4 0x00000001U
Kojto 112:6f327212ef96 3275
Kojto 112:6f327212ef96 3276 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 122:f9eeca106725 3277 #define DMA_LIFCR_CTCIF3 0x08000000U
Kojto 122:f9eeca106725 3278 #define DMA_LIFCR_CHTIF3 0x04000000U
Kojto 122:f9eeca106725 3279 #define DMA_LIFCR_CTEIF3 0x02000000U
Kojto 122:f9eeca106725 3280 #define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto 122:f9eeca106725 3281 #define DMA_LIFCR_CFEIF3 0x00400000U
Kojto 122:f9eeca106725 3282 #define DMA_LIFCR_CTCIF2 0x00200000U
Kojto 122:f9eeca106725 3283 #define DMA_LIFCR_CHTIF2 0x00100000U
Kojto 122:f9eeca106725 3284 #define DMA_LIFCR_CTEIF2 0x00080000U
Kojto 122:f9eeca106725 3285 #define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto 122:f9eeca106725 3286 #define DMA_LIFCR_CFEIF2 0x00010000U
Kojto 122:f9eeca106725 3287 #define DMA_LIFCR_CTCIF1 0x00000800U
Kojto 122:f9eeca106725 3288 #define DMA_LIFCR_CHTIF1 0x00000400U
Kojto 122:f9eeca106725 3289 #define DMA_LIFCR_CTEIF1 0x00000200U
Kojto 122:f9eeca106725 3290 #define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto 122:f9eeca106725 3291 #define DMA_LIFCR_CFEIF1 0x00000040U
Kojto 122:f9eeca106725 3292 #define DMA_LIFCR_CTCIF0 0x00000020U
Kojto 122:f9eeca106725 3293 #define DMA_LIFCR_CHTIF0 0x00000010U
Kojto 122:f9eeca106725 3294 #define DMA_LIFCR_CTEIF0 0x00000008U
Kojto 122:f9eeca106725 3295 #define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto 122:f9eeca106725 3296 #define DMA_LIFCR_CFEIF0 0x00000001U
Kojto 112:6f327212ef96 3297
Kojto 112:6f327212ef96 3298 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 122:f9eeca106725 3299 #define DMA_HIFCR_CTCIF7 0x08000000U
Kojto 122:f9eeca106725 3300 #define DMA_HIFCR_CHTIF7 0x04000000U
Kojto 122:f9eeca106725 3301 #define DMA_HIFCR_CTEIF7 0x02000000U
Kojto 122:f9eeca106725 3302 #define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto 122:f9eeca106725 3303 #define DMA_HIFCR_CFEIF7 0x00400000U
Kojto 122:f9eeca106725 3304 #define DMA_HIFCR_CTCIF6 0x00200000U
Kojto 122:f9eeca106725 3305 #define DMA_HIFCR_CHTIF6 0x00100000U
Kojto 122:f9eeca106725 3306 #define DMA_HIFCR_CTEIF6 0x00080000U
Kojto 122:f9eeca106725 3307 #define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto 122:f9eeca106725 3308 #define DMA_HIFCR_CFEIF6 0x00010000U
Kojto 122:f9eeca106725 3309 #define DMA_HIFCR_CTCIF5 0x00000800U
Kojto 122:f9eeca106725 3310 #define DMA_HIFCR_CHTIF5 0x00000400U
Kojto 122:f9eeca106725 3311 #define DMA_HIFCR_CTEIF5 0x00000200U
Kojto 122:f9eeca106725 3312 #define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto 122:f9eeca106725 3313 #define DMA_HIFCR_CFEIF5 0x00000040U
Kojto 122:f9eeca106725 3314 #define DMA_HIFCR_CTCIF4 0x00000020U
Kojto 122:f9eeca106725 3315 #define DMA_HIFCR_CHTIF4 0x00000010U
Kojto 122:f9eeca106725 3316 #define DMA_HIFCR_CTEIF4 0x00000008U
Kojto 122:f9eeca106725 3317 #define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto 122:f9eeca106725 3318 #define DMA_HIFCR_CFEIF4 0x00000001U
Kojto 112:6f327212ef96 3319
Kojto 112:6f327212ef96 3320
Kojto 112:6f327212ef96 3321 /******************************************************************************/
Kojto 112:6f327212ef96 3322 /* */
Kojto 112:6f327212ef96 3323 /* External Interrupt/Event Controller */
Kojto 112:6f327212ef96 3324 /* */
Kojto 112:6f327212ef96 3325 /******************************************************************************/
Kojto 112:6f327212ef96 3326 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 3327 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 3328 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 3329 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 3330 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 3331 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 3332 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 3333 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 3334 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 3335 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 3336 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 3337 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 3338 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 3339 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 3340 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 3341 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 3342 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 3343 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 3344 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 3345 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 3346 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 3347 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 3348 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 3349 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
Kojto 112:6f327212ef96 3350
Kojto 112:6f327212ef96 3351 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 3352 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 3353 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 3354 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 3355 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 3356 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 3357 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 3358 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 3359 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 3360 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 3361 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 3362 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 3363 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 3364 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 3365 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 3366 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 3367 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 3368 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 3369 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 3370 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 3371 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 3372 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 3373 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 3374 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
Kojto 112:6f327212ef96 3375
Kojto 112:6f327212ef96 3376 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 3377 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 3378 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 3379 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 3380 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 3381 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 3382 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 3383 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 3384 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 3385 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 3386 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 3387 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 3388 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 3389 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 3390 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 3391 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 3392 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 3393 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 3394 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 3395 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 3396 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 3397 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 3398 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 3399 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
Kojto 112:6f327212ef96 3400
Kojto 112:6f327212ef96 3401 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 3402 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 3403 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 3404 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 3405 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 3406 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 3407 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 3408 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 3409 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 3410 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 3411 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 3412 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 3413 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 3414 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 3415 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 3416 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 3417 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 3418 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 3419 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 3420 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 3421 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 3422 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 3423 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 3424 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
Kojto 112:6f327212ef96 3425
Kojto 112:6f327212ef96 3426 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 3427 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 3428 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 3429 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 3430 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 3431 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 3432 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 3433 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 3434 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 3435 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 3436 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 3437 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 3438 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 3439 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 3440 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 3441 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 3442 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 3443 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 3444 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 3445 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 3446 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 3447 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 3448 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 3449 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
Kojto 112:6f327212ef96 3450
Kojto 112:6f327212ef96 3451 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 3452 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 3453 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 3454 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 3455 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 3456 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 3457 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 3458 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 3459 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 3460 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 3461 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 3462 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 3463 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 3464 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 3465 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 3466 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 3467 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 3468 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 3469 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 3470 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 3471 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 3472 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 3473 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 3474 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
Kojto 112:6f327212ef96 3475
Kojto 112:6f327212ef96 3476 /******************************************************************************/
Kojto 112:6f327212ef96 3477 /* */
Kojto 112:6f327212ef96 3478 /* FLASH */
Kojto 112:6f327212ef96 3479 /* */
Kojto 112:6f327212ef96 3480 /******************************************************************************/
Kojto 112:6f327212ef96 3481 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 122:f9eeca106725 3482 #define FLASH_ACR_LATENCY 0x0000000FU
Kojto 122:f9eeca106725 3483 #define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto 122:f9eeca106725 3484 #define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto 122:f9eeca106725 3485 #define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto 122:f9eeca106725 3486 #define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto 122:f9eeca106725 3487 #define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto 122:f9eeca106725 3488 #define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto 122:f9eeca106725 3489 #define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto 122:f9eeca106725 3490 #define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto 122:f9eeca106725 3491 #define FLASH_ACR_LATENCY_8WS 0x00000008U
Kojto 122:f9eeca106725 3492 #define FLASH_ACR_LATENCY_9WS 0x00000009U
Kojto 122:f9eeca106725 3493 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
Kojto 122:f9eeca106725 3494 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
Kojto 122:f9eeca106725 3495 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
Kojto 122:f9eeca106725 3496 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
Kojto 122:f9eeca106725 3497 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
Kojto 122:f9eeca106725 3498 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
Kojto 122:f9eeca106725 3499 #define FLASH_ACR_PRFTEN 0x00000100U
Kojto 122:f9eeca106725 3500 #define FLASH_ACR_ICEN 0x00000200U
Kojto 122:f9eeca106725 3501 #define FLASH_ACR_DCEN 0x00000400U
Kojto 122:f9eeca106725 3502 #define FLASH_ACR_ICRST 0x00000800U
Kojto 122:f9eeca106725 3503 #define FLASH_ACR_DCRST 0x00001000U
Kojto 122:f9eeca106725 3504 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
Kojto 122:f9eeca106725 3505 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
Kojto 112:6f327212ef96 3506
Kojto 112:6f327212ef96 3507 /******************* Bits definition for FLASH_SR register ******************/
Kojto 122:f9eeca106725 3508 #define FLASH_SR_EOP 0x00000001U
Kojto 122:f9eeca106725 3509 #define FLASH_SR_SOP 0x00000002U
Kojto 122:f9eeca106725 3510 #define FLASH_SR_WRPERR 0x00000010U
Kojto 122:f9eeca106725 3511 #define FLASH_SR_PGAERR 0x00000020U
Kojto 122:f9eeca106725 3512 #define FLASH_SR_PGPERR 0x00000040U
Kojto 122:f9eeca106725 3513 #define FLASH_SR_PGSERR 0x00000080U
Kojto 122:f9eeca106725 3514 #define FLASH_SR_BSY 0x00010000U
Kojto 112:6f327212ef96 3515
Kojto 112:6f327212ef96 3516 /******************* Bits definition for FLASH_CR register ******************/
Kojto 122:f9eeca106725 3517 #define FLASH_CR_PG 0x00000001U
Kojto 122:f9eeca106725 3518 #define FLASH_CR_SER 0x00000002U
Kojto 122:f9eeca106725 3519 #define FLASH_CR_MER 0x00000004U
Kojto 112:6f327212ef96 3520 #define FLASH_CR_MER1 FLASH_CR_MER
Kojto 122:f9eeca106725 3521 #define FLASH_CR_SNB 0x000000F8U
Kojto 122:f9eeca106725 3522 #define FLASH_CR_SNB_0 0x00000008U
Kojto 122:f9eeca106725 3523 #define FLASH_CR_SNB_1 0x00000010U
Kojto 122:f9eeca106725 3524 #define FLASH_CR_SNB_2 0x00000020U
Kojto 122:f9eeca106725 3525 #define FLASH_CR_SNB_3 0x00000040U
Kojto 122:f9eeca106725 3526 #define FLASH_CR_SNB_4 0x00000080U
Kojto 122:f9eeca106725 3527 #define FLASH_CR_PSIZE 0x00000300U
Kojto 122:f9eeca106725 3528 #define FLASH_CR_PSIZE_0 0x00000100U
Kojto 122:f9eeca106725 3529 #define FLASH_CR_PSIZE_1 0x00000200U
Kojto 122:f9eeca106725 3530 #define FLASH_CR_MER2 0x00008000U
Kojto 122:f9eeca106725 3531 #define FLASH_CR_STRT 0x00010000U
Kojto 122:f9eeca106725 3532 #define FLASH_CR_EOPIE 0x01000000U
Kojto 122:f9eeca106725 3533 #define FLASH_CR_LOCK 0x80000000U
Kojto 112:6f327212ef96 3534
Kojto 112:6f327212ef96 3535 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 122:f9eeca106725 3536 #define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto 122:f9eeca106725 3537 #define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto 122:f9eeca106725 3538 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto 122:f9eeca106725 3539 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto 122:f9eeca106725 3540 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto 122:f9eeca106725 3541 #define FLASH_OPTCR_BFB2 0x00000010U
Kojto 122:f9eeca106725 3542 #define FLASH_OPTCR_WDG_SW 0x00000020U
Kojto 122:f9eeca106725 3543 #define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto 122:f9eeca106725 3544 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto 122:f9eeca106725 3545 #define FLASH_OPTCR_RDP 0x0000FF00U
Kojto 122:f9eeca106725 3546 #define FLASH_OPTCR_RDP_0 0x00000100U
Kojto 122:f9eeca106725 3547 #define FLASH_OPTCR_RDP_1 0x00000200U
Kojto 122:f9eeca106725 3548 #define FLASH_OPTCR_RDP_2 0x00000400U
Kojto 122:f9eeca106725 3549 #define FLASH_OPTCR_RDP_3 0x00000800U
Kojto 122:f9eeca106725 3550 #define FLASH_OPTCR_RDP_4 0x00001000U
Kojto 122:f9eeca106725 3551 #define FLASH_OPTCR_RDP_5 0x00002000U
Kojto 122:f9eeca106725 3552 #define FLASH_OPTCR_RDP_6 0x00004000U
Kojto 122:f9eeca106725 3553 #define FLASH_OPTCR_RDP_7 0x00008000U
Kojto 122:f9eeca106725 3554 #define FLASH_OPTCR_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 3555 #define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 3556 #define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 3557 #define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 3558 #define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 3559 #define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 3560 #define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 3561 #define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 3562 #define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 3563 #define FLASH_OPTCR_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 3564 #define FLASH_OPTCR_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 3565 #define FLASH_OPTCR_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 3566 #define FLASH_OPTCR_nWRP_11 0x08000000U
Kojto 122:f9eeca106725 3567 #define FLASH_OPTCR_DB1M 0x40000000U
Kojto 122:f9eeca106725 3568 #define FLASH_OPTCR_SPRMOD 0x80000000U
Kojto 112:6f327212ef96 3569
Kojto 112:6f327212ef96 3570 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 122:f9eeca106725 3571 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 3572 #define FLASH_OPTCR1_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 3573 #define FLASH_OPTCR1_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 3574 #define FLASH_OPTCR1_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 3575 #define FLASH_OPTCR1_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 3576 #define FLASH_OPTCR1_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 3577 #define FLASH_OPTCR1_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 3578 #define FLASH_OPTCR1_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 3579 #define FLASH_OPTCR1_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 3580 #define FLASH_OPTCR1_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 3581 #define FLASH_OPTCR1_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 3582 #define FLASH_OPTCR1_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 3583 #define FLASH_OPTCR1_nWRP_11 0x08000000U
Kojto 112:6f327212ef96 3584
Kojto 112:6f327212ef96 3585 /******************************************************************************/
Kojto 112:6f327212ef96 3586 /* */
Kojto 112:6f327212ef96 3587 /* Flexible Memory Controller */
Kojto 112:6f327212ef96 3588 /* */
Kojto 112:6f327212ef96 3589 /******************************************************************************/
Kojto 112:6f327212ef96 3590 /****************** Bit definition for FMC_BCR1 register *******************/
Kojto 122:f9eeca106725 3591 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3592 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3593
Kojto 122:f9eeca106725 3594 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3595 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3596 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3597
Kojto 122:f9eeca106725 3598 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3599 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3600 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3601
Kojto 122:f9eeca106725 3602 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3603 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3604 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3605 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3606 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3607 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3608 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3609 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3610 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 3611 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3612 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3613 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3614 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 122:f9eeca106725 3615 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
Kojto 122:f9eeca106725 3616 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
Kojto 112:6f327212ef96 3617
Kojto 112:6f327212ef96 3618 /****************** Bit definition for FMC_BCR2 register *******************/
Kojto 122:f9eeca106725 3619 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3620 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3621
Kojto 122:f9eeca106725 3622 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3623 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3624 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3625
Kojto 122:f9eeca106725 3626 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3627 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3628 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3629
Kojto 122:f9eeca106725 3630 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3631 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3632 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3633 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3634 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3635 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3636 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3637 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3638 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 112:6f327212ef96 3639
Kojto 112:6f327212ef96 3640 /****************** Bit definition for FMC_BCR3 register *******************/
Kojto 122:f9eeca106725 3641 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3642 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3643
Kojto 122:f9eeca106725 3644 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3645 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3646 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3647
Kojto 122:f9eeca106725 3648 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3649 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3650 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3651
Kojto 122:f9eeca106725 3652 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3653 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3654 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3655 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3656 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3657 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3658 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3659 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3660 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 112:6f327212ef96 3661
Kojto 112:6f327212ef96 3662 /****************** Bit definition for FMC_BCR4 register *******************/
Kojto 122:f9eeca106725 3663 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 3664 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 3665
Kojto 122:f9eeca106725 3666 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 3667 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 3668 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 3669
Kojto 122:f9eeca106725 3670 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 3671 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3672 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3673
Kojto 122:f9eeca106725 3674 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 3675 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 3676 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 3677 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 3678 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 3679 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 3680 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 3681 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 3682 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 112:6f327212ef96 3683
Kojto 112:6f327212ef96 3684 /****************** Bit definition for FMC_BTR1 register ******************/
Kojto 122:f9eeca106725 3685 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3686 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3687 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3688 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3689 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3690
Kojto 122:f9eeca106725 3691 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3692 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3693 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3694 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3695 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3696
Kojto 122:f9eeca106725 3697 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3698 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3699 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3700 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3701 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3702 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3703 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3704 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3705 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3706
Kojto 122:f9eeca106725 3707 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3708 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3709 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3710 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3711 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3712
Kojto 122:f9eeca106725 3713 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3714 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3715 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3716 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3717 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3718
Kojto 122:f9eeca106725 3719 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3720 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3721 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3722 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3723 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3724
Kojto 122:f9eeca106725 3725 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3726 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3727 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3728
Kojto 112:6f327212ef96 3729 /****************** Bit definition for FMC_BTR2 register *******************/
Kojto 122:f9eeca106725 3730 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3731 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3732 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3733 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3734 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3735
Kojto 122:f9eeca106725 3736 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3737 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3738 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3739 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3740 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3741
Kojto 122:f9eeca106725 3742 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3743 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3744 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3745 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3746 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3747 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3748 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3749 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3750 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3751
Kojto 122:f9eeca106725 3752 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3753 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3754 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3755 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3756 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3757
Kojto 122:f9eeca106725 3758 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3759 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3760 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3761 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3762 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3763
Kojto 122:f9eeca106725 3764 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3765 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3766 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3767 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3768 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3769
Kojto 122:f9eeca106725 3770 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3771 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3772 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3773
Kojto 112:6f327212ef96 3774 /******************* Bit definition for FMC_BTR3 register *******************/
Kojto 122:f9eeca106725 3775 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3776 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3777 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3778 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3779 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3780
Kojto 122:f9eeca106725 3781 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3782 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3783 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3784 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3785 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3786
Kojto 122:f9eeca106725 3787 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3788 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3789 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3790 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3791 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3792 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3793 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3794 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3795 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3796
Kojto 122:f9eeca106725 3797 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3798 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3799 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3800 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3801 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3802
Kojto 122:f9eeca106725 3803 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3804 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3805 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3806 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3807 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3808
Kojto 122:f9eeca106725 3809 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3810 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3811 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3812 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3813 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3814
Kojto 122:f9eeca106725 3815 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3816 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3817 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3818
Kojto 112:6f327212ef96 3819 /****************** Bit definition for FMC_BTR4 register *******************/
Kojto 122:f9eeca106725 3820 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3821 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3822 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3823 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3824 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3825
Kojto 122:f9eeca106725 3826 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3827 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3828 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3829 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3830 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3831
Kojto 122:f9eeca106725 3832 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3833 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3834 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3835 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3836 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3837 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3838 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3839 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3840 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3841
Kojto 122:f9eeca106725 3842 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 3843 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3844 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3845 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3846 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3847
Kojto 122:f9eeca106725 3848 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 3849 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3850 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3851 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3852 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3853
Kojto 122:f9eeca106725 3854 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 3855 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3856 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3857 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3858 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3859
Kojto 122:f9eeca106725 3860 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3861 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3862 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3863
Kojto 112:6f327212ef96 3864 /****************** Bit definition for FMC_BWTR1 register ******************/
Kojto 122:f9eeca106725 3865 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3866 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3867 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3868 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3869 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3870
Kojto 122:f9eeca106725 3871 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3872 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3873 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3874 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3875 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3876
Kojto 122:f9eeca106725 3877 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3878 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3879 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3880 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3881 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3882 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3883 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3884 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3885 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3886
Kojto 122:f9eeca106725 3887 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3888 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3889 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3890 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3891 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3892
Kojto 122:f9eeca106725 3893 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3894 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3895 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3896
Kojto 112:6f327212ef96 3897 /****************** Bit definition for FMC_BWTR2 register ******************/
Kojto 122:f9eeca106725 3898 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3899 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3900 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3901 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3902 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3903
Kojto 122:f9eeca106725 3904 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3905 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3906 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3907 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3908 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3909
Kojto 122:f9eeca106725 3910 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3911 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3912 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3913 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3914 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3915 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3916 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3917 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3918 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3919
Kojto 122:f9eeca106725 3920 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3921 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3922 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3923 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3924 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3925
Kojto 122:f9eeca106725 3926 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3927 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3928 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3929
Kojto 112:6f327212ef96 3930 /****************** Bit definition for FMC_BWTR3 register ******************/
Kojto 122:f9eeca106725 3931 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3932 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3933 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3934 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3935 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3936
Kojto 122:f9eeca106725 3937 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3938 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3939 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3940 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3941 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3942
Kojto 122:f9eeca106725 3943 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3944 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3945 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3946 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3947 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3948 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3949 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3950 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3951 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3952
Kojto 122:f9eeca106725 3953 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3954 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3955 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3956 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3957 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3958
Kojto 122:f9eeca106725 3959 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3960 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3961 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3962
Kojto 112:6f327212ef96 3963 /****************** Bit definition for FMC_BWTR4 register ******************/
Kojto 122:f9eeca106725 3964 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 3965 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 3966 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 3967 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 3968 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 3969
Kojto 122:f9eeca106725 3970 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 3971 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 3972 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 3973 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 3974 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 3975
Kojto 122:f9eeca106725 3976 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 3977 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3978 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3979 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3980 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3981 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 3982 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 3983 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 3984 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 3985
Kojto 122:f9eeca106725 3986 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 122:f9eeca106725 3987 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3988 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3989 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3990 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3991
Kojto 122:f9eeca106725 3992 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 3993 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3994 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 3995
Kojto 112:6f327212ef96 3996 /****************** Bit definition for FMC_PCR register *******************/
Kojto 122:f9eeca106725 3997 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
Kojto 122:f9eeca106725 3998 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 122:f9eeca106725 3999 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
Kojto 122:f9eeca106725 4000
Kojto 122:f9eeca106725 4001 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 122:f9eeca106725 4002 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4003 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4004
Kojto 122:f9eeca106725 4005 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
Kojto 122:f9eeca106725 4006
Kojto 122:f9eeca106725 4007 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 122:f9eeca106725 4008 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 4009 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 4010 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 4011 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4012
Kojto 122:f9eeca106725 4013 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 122:f9eeca106725 4014 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4015 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4016 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4017 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4018
Kojto 122:f9eeca106725 4019 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
Kojto 122:f9eeca106725 4020 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4021 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4022 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
Kojto 112:6f327212ef96 4023
Kojto 112:6f327212ef96 4024 /******************* Bit definition for FMC_SR register *******************/
Kojto 122:f9eeca106725 4025 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
Kojto 122:f9eeca106725 4026 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
Kojto 122:f9eeca106725 4027 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
Kojto 122:f9eeca106725 4028 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
Kojto 122:f9eeca106725 4029 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
Kojto 122:f9eeca106725 4030 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
Kojto 122:f9eeca106725 4031 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
Kojto 112:6f327212ef96 4032
Kojto 112:6f327212ef96 4033 /****************** Bit definition for FMC_PMEM register ******************/
Kojto 122:f9eeca106725 4034 #define FMC_PMEM_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
Kojto 122:f9eeca106725 4035 #define FMC_PMEM_MEMSET2_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4036 #define FMC_PMEM_MEMSET2_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4037 #define FMC_PMEM_MEMSET2_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4038 #define FMC_PMEM_MEMSET2_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4039 #define FMC_PMEM_MEMSET2_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4040 #define FMC_PMEM_MEMSET2_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4041 #define FMC_PMEM_MEMSET2_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4042 #define FMC_PMEM_MEMSET2_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4043
Kojto 122:f9eeca106725 4044 #define FMC_PMEM_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
Kojto 122:f9eeca106725 4045 #define FMC_PMEM_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4046 #define FMC_PMEM_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4047 #define FMC_PMEM_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4048 #define FMC_PMEM_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4049 #define FMC_PMEM_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4050 #define FMC_PMEM_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4051 #define FMC_PMEM_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4052 #define FMC_PMEM_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4053
Kojto 122:f9eeca106725 4054 #define FMC_PMEM_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
Kojto 122:f9eeca106725 4055 #define FMC_PMEM_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4056 #define FMC_PMEM_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4057 #define FMC_PMEM_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4058 #define FMC_PMEM_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4059 #define FMC_PMEM_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4060 #define FMC_PMEM_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4061 #define FMC_PMEM_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4062 #define FMC_PMEM_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4063
Kojto 122:f9eeca106725 4064 #define FMC_PMEM_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
Kojto 122:f9eeca106725 4065 #define FMC_PMEM_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4066 #define FMC_PMEM_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4067 #define FMC_PMEM_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4068 #define FMC_PMEM_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4069 #define FMC_PMEM_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4070 #define FMC_PMEM_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4071 #define FMC_PMEM_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4072 #define FMC_PMEM_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
Kojto 112:6f327212ef96 4073
Kojto 112:6f327212ef96 4074 /****************** Bit definition for FMC_PATT register ******************/
Kojto 122:f9eeca106725 4075 #define FMC_PATT_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
Kojto 122:f9eeca106725 4076 #define FMC_PATT_ATTSET2_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4077 #define FMC_PATT_ATTSET2_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4078 #define FMC_PATT_ATTSET2_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4079 #define FMC_PATT_ATTSET2_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4080 #define FMC_PATT_ATTSET2_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4081 #define FMC_PATT_ATTSET2_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4082 #define FMC_PATT_ATTSET2_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4083 #define FMC_PATT_ATTSET2_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4084
Kojto 122:f9eeca106725 4085 #define FMC_PATT_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
Kojto 122:f9eeca106725 4086 #define FMC_PATT_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4087 #define FMC_PATT_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4088 #define FMC_PATT_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4089 #define FMC_PATT_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4090 #define FMC_PATT_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4091 #define FMC_PATT_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4092 #define FMC_PATT_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4093 #define FMC_PATT_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4094
Kojto 122:f9eeca106725 4095 #define FMC_PATT_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
Kojto 122:f9eeca106725 4096 #define FMC_PATT_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4097 #define FMC_PATT_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4098 #define FMC_PATT_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4099 #define FMC_PATT_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4100 #define FMC_PATT_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4101 #define FMC_PATT_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4102 #define FMC_PATT_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4103 #define FMC_PATT_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4104
Kojto 122:f9eeca106725 4105 #define FMC_PATT_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
Kojto 122:f9eeca106725 4106 #define FMC_PATT_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4107 #define FMC_PATT_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4108 #define FMC_PATT_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4109 #define FMC_PATT_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4110 #define FMC_PATT_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4111 #define FMC_PATT_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4112 #define FMC_PATT_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4113 #define FMC_PATT_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
Kojto 112:6f327212ef96 4114
Kojto 112:6f327212ef96 4115 /****************** Bit definition for FMC_ECCR register ******************/
Kojto 122:f9eeca106725 4116 #define FMC_ECCR_ECC2 0xFFFFFFFFU /*!<ECC result */
Kojto 112:6f327212ef96 4117
Kojto 112:6f327212ef96 4118 /****************** Bit definition for FMC_SDCR1 register ******************/
Kojto 122:f9eeca106725 4119 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
Kojto 122:f9eeca106725 4120 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4121 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4122
Kojto 122:f9eeca106725 4123 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4124 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4125 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4126
Kojto 122:f9eeca106725 4127 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4128 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4129 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4130
Kojto 122:f9eeca106725 4131 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
Kojto 122:f9eeca106725 4132
Kojto 122:f9eeca106725 4133 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
Kojto 122:f9eeca106725 4134 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 4135 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 4136
Kojto 122:f9eeca106725 4137 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
Kojto 122:f9eeca106725 4138
Kojto 122:f9eeca106725 4139 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
Kojto 122:f9eeca106725 4140 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 4141 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 4142
Kojto 122:f9eeca106725 4143 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
Kojto 122:f9eeca106725 4144
Kojto 122:f9eeca106725 4145 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
Kojto 122:f9eeca106725 4146 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4147 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
Kojto 112:6f327212ef96 4148
Kojto 112:6f327212ef96 4149 /****************** Bit definition for FMC_SDCR2 register ******************/
Kojto 122:f9eeca106725 4150 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
Kojto 122:f9eeca106725 4151 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4152 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4153
Kojto 122:f9eeca106725 4154 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4155 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4156 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4157
Kojto 122:f9eeca106725 4158 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4159 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4160 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4161
Kojto 122:f9eeca106725 4162 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
Kojto 122:f9eeca106725 4163
Kojto 122:f9eeca106725 4164 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
Kojto 122:f9eeca106725 4165 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 4166 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 4167
Kojto 122:f9eeca106725 4168 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
Kojto 122:f9eeca106725 4169
Kojto 122:f9eeca106725 4170 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
Kojto 122:f9eeca106725 4171 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 4172 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 4173
Kojto 122:f9eeca106725 4174 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
Kojto 122:f9eeca106725 4175
Kojto 122:f9eeca106725 4176 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
Kojto 122:f9eeca106725 4177 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4178 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
Kojto 112:6f327212ef96 4179
Kojto 112:6f327212ef96 4180 /****************** Bit definition for FMC_SDTR1 register ******************/
Kojto 122:f9eeca106725 4181 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 122:f9eeca106725 4182 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4183 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4184 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4185 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
Kojto 112:6f327212ef96 4186
Kojto 122:f9eeca106725 4187 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 122:f9eeca106725 4188 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4189 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4190 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4191 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4192
Kojto 122:f9eeca106725 4193 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 122:f9eeca106725 4194 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4195 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4196 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4197 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4198
Kojto 122:f9eeca106725 4199 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 122:f9eeca106725 4200 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4201 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4202 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4203
Kojto 122:f9eeca106725 4204 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 122:f9eeca106725 4205 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4206 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4207 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4208
Kojto 122:f9eeca106725 4209 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 122:f9eeca106725 4210 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4211 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4212 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4213
Kojto 122:f9eeca106725 4214 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
Kojto 122:f9eeca106725 4215 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4216 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4217 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
Kojto 112:6f327212ef96 4218
Kojto 112:6f327212ef96 4219 /****************** Bit definition for FMC_SDTR2 register ******************/
Kojto 122:f9eeca106725 4220 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 122:f9eeca106725 4221 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4222 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4223 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4224 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
Kojto 112:6f327212ef96 4225
Kojto 122:f9eeca106725 4226 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 122:f9eeca106725 4227 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4228 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4229 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4230 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4231
Kojto 122:f9eeca106725 4232 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 122:f9eeca106725 4233 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4234 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4235 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4236 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4237
Kojto 122:f9eeca106725 4238 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 122:f9eeca106725 4239 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4240 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4241 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4242
Kojto 122:f9eeca106725 4243 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 122:f9eeca106725 4244 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4245 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4246 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4247
Kojto 122:f9eeca106725 4248 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 122:f9eeca106725 4249 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4250 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4251 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4252
Kojto 122:f9eeca106725 4253 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
Kojto 122:f9eeca106725 4254 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4255 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4256 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
Kojto 112:6f327212ef96 4257
Kojto 112:6f327212ef96 4258 /****************** Bit definition for FMC_SDCMR register ******************/
Kojto 122:f9eeca106725 4259 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
Kojto 122:f9eeca106725 4260 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4261 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4262 #define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
Kojto 112:6f327212ef96 4263
Kojto 122:f9eeca106725 4264 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
Kojto 122:f9eeca106725 4265
Kojto 122:f9eeca106725 4266 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
Kojto 122:f9eeca106725 4267
Kojto 122:f9eeca106725 4268 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
Kojto 122:f9eeca106725 4269 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 4270 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 4271 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 4272 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 4273
Kojto 122:f9eeca106725 4274 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
Kojto 112:6f327212ef96 4275
Kojto 112:6f327212ef96 4276 /****************** Bit definition for FMC_SDRTR register ******************/
Kojto 122:f9eeca106725 4277 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
Kojto 122:f9eeca106725 4278
Kojto 122:f9eeca106725 4279 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
Kojto 122:f9eeca106725 4280
Kojto 122:f9eeca106725 4281 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
Kojto 112:6f327212ef96 4282
Kojto 112:6f327212ef96 4283 /****************** Bit definition for FMC_SDSR register ******************/
Kojto 122:f9eeca106725 4284 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
Kojto 122:f9eeca106725 4285
Kojto 122:f9eeca106725 4286 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
Kojto 122:f9eeca106725 4287 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 4288 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 4289
Kojto 122:f9eeca106725 4290 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
Kojto 122:f9eeca106725 4291 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 4292 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 4293 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
Kojto 112:6f327212ef96 4294
Kojto 112:6f327212ef96 4295 /******************************************************************************/
Kojto 112:6f327212ef96 4296 /* */
Kojto 112:6f327212ef96 4297 /* General Purpose I/O */
Kojto 112:6f327212ef96 4298 /* */
Kojto 112:6f327212ef96 4299 /******************************************************************************/
Kojto 112:6f327212ef96 4300 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 4301 #define GPIO_MODER_MODER0 0x00000003U
Kojto 122:f9eeca106725 4302 #define GPIO_MODER_MODER0_0 0x00000001U
Kojto 122:f9eeca106725 4303 #define GPIO_MODER_MODER0_1 0x00000002U
Kojto 122:f9eeca106725 4304
Kojto 122:f9eeca106725 4305 #define GPIO_MODER_MODER1 0x0000000CU
Kojto 122:f9eeca106725 4306 #define GPIO_MODER_MODER1_0 0x00000004U
Kojto 122:f9eeca106725 4307 #define GPIO_MODER_MODER1_1 0x00000008U
Kojto 122:f9eeca106725 4308
Kojto 122:f9eeca106725 4309 #define GPIO_MODER_MODER2 0x00000030U
Kojto 122:f9eeca106725 4310 #define GPIO_MODER_MODER2_0 0x00000010U
Kojto 122:f9eeca106725 4311 #define GPIO_MODER_MODER2_1 0x00000020U
Kojto 122:f9eeca106725 4312
Kojto 122:f9eeca106725 4313 #define GPIO_MODER_MODER3 0x000000C0U
Kojto 122:f9eeca106725 4314 #define GPIO_MODER_MODER3_0 0x00000040U
Kojto 122:f9eeca106725 4315 #define GPIO_MODER_MODER3_1 0x00000080U
Kojto 122:f9eeca106725 4316
Kojto 122:f9eeca106725 4317 #define GPIO_MODER_MODER4 0x00000300U
Kojto 122:f9eeca106725 4318 #define GPIO_MODER_MODER4_0 0x00000100U
Kojto 122:f9eeca106725 4319 #define GPIO_MODER_MODER4_1 0x00000200U
Kojto 122:f9eeca106725 4320
Kojto 122:f9eeca106725 4321 #define GPIO_MODER_MODER5 0x00000C00U
Kojto 122:f9eeca106725 4322 #define GPIO_MODER_MODER5_0 0x00000400U
Kojto 122:f9eeca106725 4323 #define GPIO_MODER_MODER5_1 0x00000800U
Kojto 122:f9eeca106725 4324
Kojto 122:f9eeca106725 4325 #define GPIO_MODER_MODER6 0x00003000U
Kojto 122:f9eeca106725 4326 #define GPIO_MODER_MODER6_0 0x00001000U
Kojto 122:f9eeca106725 4327 #define GPIO_MODER_MODER6_1 0x00002000U
Kojto 122:f9eeca106725 4328
Kojto 122:f9eeca106725 4329 #define GPIO_MODER_MODER7 0x0000C000U
Kojto 122:f9eeca106725 4330 #define GPIO_MODER_MODER7_0 0x00004000U
Kojto 122:f9eeca106725 4331 #define GPIO_MODER_MODER7_1 0x00008000U
Kojto 122:f9eeca106725 4332
Kojto 122:f9eeca106725 4333 #define GPIO_MODER_MODER8 0x00030000U
Kojto 122:f9eeca106725 4334 #define GPIO_MODER_MODER8_0 0x00010000U
Kojto 122:f9eeca106725 4335 #define GPIO_MODER_MODER8_1 0x00020000U
Kojto 122:f9eeca106725 4336
Kojto 122:f9eeca106725 4337 #define GPIO_MODER_MODER9 0x000C0000U
Kojto 122:f9eeca106725 4338 #define GPIO_MODER_MODER9_0 0x00040000U
Kojto 122:f9eeca106725 4339 #define GPIO_MODER_MODER9_1 0x00080000U
Kojto 122:f9eeca106725 4340
Kojto 122:f9eeca106725 4341 #define GPIO_MODER_MODER10 0x00300000U
Kojto 122:f9eeca106725 4342 #define GPIO_MODER_MODER10_0 0x00100000U
Kojto 122:f9eeca106725 4343 #define GPIO_MODER_MODER10_1 0x00200000U
Kojto 122:f9eeca106725 4344
Kojto 122:f9eeca106725 4345 #define GPIO_MODER_MODER11 0x00C00000U
Kojto 122:f9eeca106725 4346 #define GPIO_MODER_MODER11_0 0x00400000U
Kojto 122:f9eeca106725 4347 #define GPIO_MODER_MODER11_1 0x00800000U
Kojto 122:f9eeca106725 4348
Kojto 122:f9eeca106725 4349 #define GPIO_MODER_MODER12 0x03000000U
Kojto 122:f9eeca106725 4350 #define GPIO_MODER_MODER12_0 0x01000000U
Kojto 122:f9eeca106725 4351 #define GPIO_MODER_MODER12_1 0x02000000U
Kojto 122:f9eeca106725 4352
Kojto 122:f9eeca106725 4353 #define GPIO_MODER_MODER13 0x0C000000U
Kojto 122:f9eeca106725 4354 #define GPIO_MODER_MODER13_0 0x04000000U
Kojto 122:f9eeca106725 4355 #define GPIO_MODER_MODER13_1 0x08000000U
Kojto 122:f9eeca106725 4356
Kojto 122:f9eeca106725 4357 #define GPIO_MODER_MODER14 0x30000000U
Kojto 122:f9eeca106725 4358 #define GPIO_MODER_MODER14_0 0x10000000U
Kojto 122:f9eeca106725 4359 #define GPIO_MODER_MODER14_1 0x20000000U
Kojto 122:f9eeca106725 4360
Kojto 122:f9eeca106725 4361 #define GPIO_MODER_MODER15 0xC0000000U
Kojto 122:f9eeca106725 4362 #define GPIO_MODER_MODER15_0 0x40000000U
Kojto 122:f9eeca106725 4363 #define GPIO_MODER_MODER15_1 0x80000000U
Kojto 112:6f327212ef96 4364
Kojto 112:6f327212ef96 4365 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 4366 #define GPIO_OTYPER_OT_0 0x00000001U
Kojto 122:f9eeca106725 4367 #define GPIO_OTYPER_OT_1 0x00000002U
Kojto 122:f9eeca106725 4368 #define GPIO_OTYPER_OT_2 0x00000004U
Kojto 122:f9eeca106725 4369 #define GPIO_OTYPER_OT_3 0x00000008U
Kojto 122:f9eeca106725 4370 #define GPIO_OTYPER_OT_4 0x00000010U
Kojto 122:f9eeca106725 4371 #define GPIO_OTYPER_OT_5 0x00000020U
Kojto 122:f9eeca106725 4372 #define GPIO_OTYPER_OT_6 0x00000040U
Kojto 122:f9eeca106725 4373 #define GPIO_OTYPER_OT_7 0x00000080U
Kojto 122:f9eeca106725 4374 #define GPIO_OTYPER_OT_8 0x00000100U
Kojto 122:f9eeca106725 4375 #define GPIO_OTYPER_OT_9 0x00000200U
Kojto 122:f9eeca106725 4376 #define GPIO_OTYPER_OT_10 0x00000400U
Kojto 122:f9eeca106725 4377 #define GPIO_OTYPER_OT_11 0x00000800U
Kojto 122:f9eeca106725 4378 #define GPIO_OTYPER_OT_12 0x00001000U
Kojto 122:f9eeca106725 4379 #define GPIO_OTYPER_OT_13 0x00002000U
Kojto 122:f9eeca106725 4380 #define GPIO_OTYPER_OT_14 0x00004000U
Kojto 122:f9eeca106725 4381 #define GPIO_OTYPER_OT_15 0x00008000U
Kojto 112:6f327212ef96 4382
Kojto 112:6f327212ef96 4383 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 4384 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto 122:f9eeca106725 4385 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto 122:f9eeca106725 4386 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto 122:f9eeca106725 4387
Kojto 122:f9eeca106725 4388 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto 122:f9eeca106725 4389 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto 122:f9eeca106725 4390 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto 122:f9eeca106725 4391
Kojto 122:f9eeca106725 4392 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto 122:f9eeca106725 4393 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto 122:f9eeca106725 4394 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto 122:f9eeca106725 4395
Kojto 122:f9eeca106725 4396 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto 122:f9eeca106725 4397 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto 122:f9eeca106725 4398 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto 122:f9eeca106725 4399
Kojto 122:f9eeca106725 4400 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto 122:f9eeca106725 4401 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto 122:f9eeca106725 4402 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto 122:f9eeca106725 4403
Kojto 122:f9eeca106725 4404 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto 122:f9eeca106725 4405 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto 122:f9eeca106725 4406 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto 122:f9eeca106725 4407
Kojto 122:f9eeca106725 4408 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto 122:f9eeca106725 4409 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto 122:f9eeca106725 4410 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto 122:f9eeca106725 4411
Kojto 122:f9eeca106725 4412 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto 122:f9eeca106725 4413 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto 122:f9eeca106725 4414 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto 122:f9eeca106725 4415
Kojto 122:f9eeca106725 4416 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto 122:f9eeca106725 4417 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto 122:f9eeca106725 4418 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto 122:f9eeca106725 4419
Kojto 122:f9eeca106725 4420 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto 122:f9eeca106725 4421 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto 122:f9eeca106725 4422 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto 122:f9eeca106725 4423
Kojto 122:f9eeca106725 4424 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto 122:f9eeca106725 4425 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto 122:f9eeca106725 4426 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto 122:f9eeca106725 4427
Kojto 122:f9eeca106725 4428 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto 122:f9eeca106725 4429 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto 122:f9eeca106725 4430 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto 122:f9eeca106725 4431
Kojto 122:f9eeca106725 4432 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto 122:f9eeca106725 4433 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto 122:f9eeca106725 4434 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto 122:f9eeca106725 4435
Kojto 122:f9eeca106725 4436 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto 122:f9eeca106725 4437 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto 122:f9eeca106725 4438 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto 122:f9eeca106725 4439
Kojto 122:f9eeca106725 4440 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto 122:f9eeca106725 4441 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto 122:f9eeca106725 4442 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto 122:f9eeca106725 4443
Kojto 122:f9eeca106725 4444 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto 122:f9eeca106725 4445 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto 122:f9eeca106725 4446 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
Kojto 112:6f327212ef96 4447
Kojto 112:6f327212ef96 4448 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 4449 #define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto 122:f9eeca106725 4450 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto 122:f9eeca106725 4451 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto 122:f9eeca106725 4452
Kojto 122:f9eeca106725 4453 #define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto 122:f9eeca106725 4454 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto 122:f9eeca106725 4455 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto 122:f9eeca106725 4456
Kojto 122:f9eeca106725 4457 #define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto 122:f9eeca106725 4458 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto 122:f9eeca106725 4459 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto 122:f9eeca106725 4460
Kojto 122:f9eeca106725 4461 #define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto 122:f9eeca106725 4462 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto 122:f9eeca106725 4463 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto 122:f9eeca106725 4464
Kojto 122:f9eeca106725 4465 #define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto 122:f9eeca106725 4466 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto 122:f9eeca106725 4467 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto 122:f9eeca106725 4468
Kojto 122:f9eeca106725 4469 #define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto 122:f9eeca106725 4470 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto 122:f9eeca106725 4471 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto 122:f9eeca106725 4472
Kojto 122:f9eeca106725 4473 #define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto 122:f9eeca106725 4474 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto 122:f9eeca106725 4475 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto 122:f9eeca106725 4476
Kojto 122:f9eeca106725 4477 #define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto 122:f9eeca106725 4478 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto 122:f9eeca106725 4479 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto 122:f9eeca106725 4480
Kojto 122:f9eeca106725 4481 #define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto 122:f9eeca106725 4482 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto 122:f9eeca106725 4483 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto 122:f9eeca106725 4484
Kojto 122:f9eeca106725 4485 #define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto 122:f9eeca106725 4486 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto 122:f9eeca106725 4487 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto 122:f9eeca106725 4488
Kojto 122:f9eeca106725 4489 #define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto 122:f9eeca106725 4490 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto 122:f9eeca106725 4491 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto 122:f9eeca106725 4492
Kojto 122:f9eeca106725 4493 #define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto 122:f9eeca106725 4494 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto 122:f9eeca106725 4495 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto 122:f9eeca106725 4496
Kojto 122:f9eeca106725 4497 #define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto 122:f9eeca106725 4498 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto 122:f9eeca106725 4499 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto 122:f9eeca106725 4500
Kojto 122:f9eeca106725 4501 #define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto 122:f9eeca106725 4502 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto 122:f9eeca106725 4503 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto 122:f9eeca106725 4504
Kojto 122:f9eeca106725 4505 #define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto 122:f9eeca106725 4506 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto 122:f9eeca106725 4507 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto 122:f9eeca106725 4508
Kojto 122:f9eeca106725 4509 #define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto 122:f9eeca106725 4510 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto 122:f9eeca106725 4511 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
Kojto 112:6f327212ef96 4512
Kojto 112:6f327212ef96 4513 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 4514 #define GPIO_IDR_IDR_0 0x00000001U
Kojto 122:f9eeca106725 4515 #define GPIO_IDR_IDR_1 0x00000002U
Kojto 122:f9eeca106725 4516 #define GPIO_IDR_IDR_2 0x00000004U
Kojto 122:f9eeca106725 4517 #define GPIO_IDR_IDR_3 0x00000008U
Kojto 122:f9eeca106725 4518 #define GPIO_IDR_IDR_4 0x00000010U
Kojto 122:f9eeca106725 4519 #define GPIO_IDR_IDR_5 0x00000020U
Kojto 122:f9eeca106725 4520 #define GPIO_IDR_IDR_6 0x00000040U
Kojto 122:f9eeca106725 4521 #define GPIO_IDR_IDR_7 0x00000080U
Kojto 122:f9eeca106725 4522 #define GPIO_IDR_IDR_8 0x00000100U
Kojto 122:f9eeca106725 4523 #define GPIO_IDR_IDR_9 0x00000200U
Kojto 122:f9eeca106725 4524 #define GPIO_IDR_IDR_10 0x00000400U
Kojto 122:f9eeca106725 4525 #define GPIO_IDR_IDR_11 0x00000800U
Kojto 122:f9eeca106725 4526 #define GPIO_IDR_IDR_12 0x00001000U
Kojto 122:f9eeca106725 4527 #define GPIO_IDR_IDR_13 0x00002000U
Kojto 122:f9eeca106725 4528 #define GPIO_IDR_IDR_14 0x00004000U
Kojto 122:f9eeca106725 4529 #define GPIO_IDR_IDR_15 0x00008000U
Kojto 112:6f327212ef96 4530 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 4531 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 112:6f327212ef96 4532 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 112:6f327212ef96 4533 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 112:6f327212ef96 4534 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 112:6f327212ef96 4535 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 112:6f327212ef96 4536 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 112:6f327212ef96 4537 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 112:6f327212ef96 4538 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 112:6f327212ef96 4539 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 112:6f327212ef96 4540 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 112:6f327212ef96 4541 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 112:6f327212ef96 4542 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 112:6f327212ef96 4543 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 112:6f327212ef96 4544 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 112:6f327212ef96 4545 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 112:6f327212ef96 4546 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 112:6f327212ef96 4547
Kojto 112:6f327212ef96 4548 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 4549 #define GPIO_ODR_ODR_0 0x00000001U
Kojto 122:f9eeca106725 4550 #define GPIO_ODR_ODR_1 0x00000002U
Kojto 122:f9eeca106725 4551 #define GPIO_ODR_ODR_2 0x00000004U
Kojto 122:f9eeca106725 4552 #define GPIO_ODR_ODR_3 0x00000008U
Kojto 122:f9eeca106725 4553 #define GPIO_ODR_ODR_4 0x00000010U
Kojto 122:f9eeca106725 4554 #define GPIO_ODR_ODR_5 0x00000020U
Kojto 122:f9eeca106725 4555 #define GPIO_ODR_ODR_6 0x00000040U
Kojto 122:f9eeca106725 4556 #define GPIO_ODR_ODR_7 0x00000080U
Kojto 122:f9eeca106725 4557 #define GPIO_ODR_ODR_8 0x00000100U
Kojto 122:f9eeca106725 4558 #define GPIO_ODR_ODR_9 0x00000200U
Kojto 122:f9eeca106725 4559 #define GPIO_ODR_ODR_10 0x00000400U
Kojto 122:f9eeca106725 4560 #define GPIO_ODR_ODR_11 0x00000800U
Kojto 122:f9eeca106725 4561 #define GPIO_ODR_ODR_12 0x00001000U
Kojto 122:f9eeca106725 4562 #define GPIO_ODR_ODR_13 0x00002000U
Kojto 122:f9eeca106725 4563 #define GPIO_ODR_ODR_14 0x00004000U
Kojto 122:f9eeca106725 4564 #define GPIO_ODR_ODR_15 0x00008000U
Kojto 112:6f327212ef96 4565 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 4566 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 112:6f327212ef96 4567 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 112:6f327212ef96 4568 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 112:6f327212ef96 4569 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 112:6f327212ef96 4570 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 112:6f327212ef96 4571 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 112:6f327212ef96 4572 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 112:6f327212ef96 4573 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 112:6f327212ef96 4574 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 112:6f327212ef96 4575 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 112:6f327212ef96 4576 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 112:6f327212ef96 4577 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 112:6f327212ef96 4578 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 112:6f327212ef96 4579 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 112:6f327212ef96 4580 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 112:6f327212ef96 4581 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 112:6f327212ef96 4582
Kojto 112:6f327212ef96 4583 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 4584 #define GPIO_BSRR_BS_0 0x00000001U
Kojto 122:f9eeca106725 4585 #define GPIO_BSRR_BS_1 0x00000002U
Kojto 122:f9eeca106725 4586 #define GPIO_BSRR_BS_2 0x00000004U
Kojto 122:f9eeca106725 4587 #define GPIO_BSRR_BS_3 0x00000008U
Kojto 122:f9eeca106725 4588 #define GPIO_BSRR_BS_4 0x00000010U
Kojto 122:f9eeca106725 4589 #define GPIO_BSRR_BS_5 0x00000020U
Kojto 122:f9eeca106725 4590 #define GPIO_BSRR_BS_6 0x00000040U
Kojto 122:f9eeca106725 4591 #define GPIO_BSRR_BS_7 0x00000080U
Kojto 122:f9eeca106725 4592 #define GPIO_BSRR_BS_8 0x00000100U
Kojto 122:f9eeca106725 4593 #define GPIO_BSRR_BS_9 0x00000200U
Kojto 122:f9eeca106725 4594 #define GPIO_BSRR_BS_10 0x00000400U
Kojto 122:f9eeca106725 4595 #define GPIO_BSRR_BS_11 0x00000800U
Kojto 122:f9eeca106725 4596 #define GPIO_BSRR_BS_12 0x00001000U
Kojto 122:f9eeca106725 4597 #define GPIO_BSRR_BS_13 0x00002000U
Kojto 122:f9eeca106725 4598 #define GPIO_BSRR_BS_14 0x00004000U
Kojto 122:f9eeca106725 4599 #define GPIO_BSRR_BS_15 0x00008000U
Kojto 122:f9eeca106725 4600 #define GPIO_BSRR_BR_0 0x00010000U
Kojto 122:f9eeca106725 4601 #define GPIO_BSRR_BR_1 0x00020000U
Kojto 122:f9eeca106725 4602 #define GPIO_BSRR_BR_2 0x00040000U
Kojto 122:f9eeca106725 4603 #define GPIO_BSRR_BR_3 0x00080000U
Kojto 122:f9eeca106725 4604 #define GPIO_BSRR_BR_4 0x00100000U
Kojto 122:f9eeca106725 4605 #define GPIO_BSRR_BR_5 0x00200000U
Kojto 122:f9eeca106725 4606 #define GPIO_BSRR_BR_6 0x00400000U
Kojto 122:f9eeca106725 4607 #define GPIO_BSRR_BR_7 0x00800000U
Kojto 122:f9eeca106725 4608 #define GPIO_BSRR_BR_8 0x01000000U
Kojto 122:f9eeca106725 4609 #define GPIO_BSRR_BR_9 0x02000000U
Kojto 122:f9eeca106725 4610 #define GPIO_BSRR_BR_10 0x04000000U
Kojto 122:f9eeca106725 4611 #define GPIO_BSRR_BR_11 0x08000000U
Kojto 122:f9eeca106725 4612 #define GPIO_BSRR_BR_12 0x10000000U
Kojto 122:f9eeca106725 4613 #define GPIO_BSRR_BR_13 0x20000000U
Kojto 122:f9eeca106725 4614 #define GPIO_BSRR_BR_14 0x40000000U
Kojto 122:f9eeca106725 4615 #define GPIO_BSRR_BR_15 0x80000000U
Kojto 112:6f327212ef96 4616
Kojto 112:6f327212ef96 4617 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 122:f9eeca106725 4618 #define GPIO_LCKR_LCK0 0x00000001U
Kojto 122:f9eeca106725 4619 #define GPIO_LCKR_LCK1 0x00000002U
Kojto 122:f9eeca106725 4620 #define GPIO_LCKR_LCK2 0x00000004U
Kojto 122:f9eeca106725 4621 #define GPIO_LCKR_LCK3 0x00000008U
Kojto 122:f9eeca106725 4622 #define GPIO_LCKR_LCK4 0x00000010U
Kojto 122:f9eeca106725 4623 #define GPIO_LCKR_LCK5 0x00000020U
Kojto 122:f9eeca106725 4624 #define GPIO_LCKR_LCK6 0x00000040U
Kojto 122:f9eeca106725 4625 #define GPIO_LCKR_LCK7 0x00000080U
Kojto 122:f9eeca106725 4626 #define GPIO_LCKR_LCK8 0x00000100U
Kojto 122:f9eeca106725 4627 #define GPIO_LCKR_LCK9 0x00000200U
Kojto 122:f9eeca106725 4628 #define GPIO_LCKR_LCK10 0x00000400U
Kojto 122:f9eeca106725 4629 #define GPIO_LCKR_LCK11 0x00000800U
Kojto 122:f9eeca106725 4630 #define GPIO_LCKR_LCK12 0x00001000U
Kojto 122:f9eeca106725 4631 #define GPIO_LCKR_LCK13 0x00002000U
Kojto 122:f9eeca106725 4632 #define GPIO_LCKR_LCK14 0x00004000U
Kojto 122:f9eeca106725 4633 #define GPIO_LCKR_LCK15 0x00008000U
Kojto 122:f9eeca106725 4634 #define GPIO_LCKR_LCKK 0x00010000U
Kojto 112:6f327212ef96 4635
Kojto 112:6f327212ef96 4636 /******************************************************************************/
Kojto 112:6f327212ef96 4637 /* */
Kojto 112:6f327212ef96 4638 /* Inter-integrated Circuit Interface */
Kojto 112:6f327212ef96 4639 /* */
Kojto 112:6f327212ef96 4640 /******************************************************************************/
Kojto 112:6f327212ef96 4641 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 122:f9eeca106725 4642 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
Kojto 122:f9eeca106725 4643 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
Kojto 122:f9eeca106725 4644 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
Kojto 122:f9eeca106725 4645 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
Kojto 122:f9eeca106725 4646 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
Kojto 122:f9eeca106725 4647 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
Kojto 122:f9eeca106725 4648 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
Kojto 122:f9eeca106725 4649 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
Kojto 122:f9eeca106725 4650 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
Kojto 122:f9eeca106725 4651 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
Kojto 122:f9eeca106725 4652 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
Kojto 122:f9eeca106725 4653 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
Kojto 122:f9eeca106725 4654 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
Kojto 122:f9eeca106725 4655 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
Kojto 112:6f327212ef96 4656
Kojto 112:6f327212ef96 4657 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 4658 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 122:f9eeca106725 4659 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4660 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4661 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4662 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4663 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4664 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4665
Kojto 122:f9eeca106725 4666 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 4667 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
Kojto 122:f9eeca106725 4668 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
Kojto 122:f9eeca106725 4669 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
Kojto 122:f9eeca106725 4670 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
Kojto 112:6f327212ef96 4671
Kojto 112:6f327212ef96 4672 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 122:f9eeca106725 4673 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
Kojto 122:f9eeca106725 4674 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
Kojto 122:f9eeca106725 4675
Kojto 122:f9eeca106725 4676 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4677 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4678 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4679 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4680 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4681 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4682 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4683 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4684 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
Kojto 122:f9eeca106725 4685 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
Kojto 122:f9eeca106725 4686
Kojto 122:f9eeca106725 4687 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
Kojto 112:6f327212ef96 4688
Kojto 112:6f327212ef96 4689 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 122:f9eeca106725 4690 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
Kojto 122:f9eeca106725 4691 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
Kojto 112:6f327212ef96 4692
Kojto 112:6f327212ef96 4693 /******************** Bit definition for I2C_DR register ********************/
Kojto 122:f9eeca106725 4694 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
Kojto 112:6f327212ef96 4695
Kojto 112:6f327212ef96 4696 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 122:f9eeca106725 4697 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
Kojto 122:f9eeca106725 4698 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
Kojto 122:f9eeca106725 4699 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
Kojto 122:f9eeca106725 4700 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
Kojto 122:f9eeca106725 4701 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
Kojto 122:f9eeca106725 4702 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
Kojto 122:f9eeca106725 4703 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
Kojto 122:f9eeca106725 4704 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
Kojto 122:f9eeca106725 4705 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
Kojto 122:f9eeca106725 4706 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
Kojto 122:f9eeca106725 4707 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
Kojto 122:f9eeca106725 4708 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
Kojto 122:f9eeca106725 4709 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
Kojto 122:f9eeca106725 4710 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
Kojto 112:6f327212ef96 4711
Kojto 112:6f327212ef96 4712 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 122:f9eeca106725 4713 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
Kojto 122:f9eeca106725 4714 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
Kojto 122:f9eeca106725 4715 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
Kojto 122:f9eeca106725 4716 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
Kojto 122:f9eeca106725 4717 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
Kojto 122:f9eeca106725 4718 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
Kojto 122:f9eeca106725 4719 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
Kojto 122:f9eeca106725 4720 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
Kojto 112:6f327212ef96 4721
Kojto 112:6f327212ef96 4722 /******************* Bit definition for I2C_CCR register ********************/
Kojto 122:f9eeca106725 4723 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 122:f9eeca106725 4724 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
Kojto 122:f9eeca106725 4725 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
Kojto 112:6f327212ef96 4726
Kojto 112:6f327212ef96 4727 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 122:f9eeca106725 4728 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 112:6f327212ef96 4729
Kojto 112:6f327212ef96 4730 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 122:f9eeca106725 4731 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
Kojto 122:f9eeca106725 4732 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
Kojto 112:6f327212ef96 4733
Kojto 112:6f327212ef96 4734 /******************************************************************************/
Kojto 112:6f327212ef96 4735 /* */
Kojto 112:6f327212ef96 4736 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
Kojto 112:6f327212ef96 4737 /* */
Kojto 112:6f327212ef96 4738 /******************************************************************************/
Kojto 112:6f327212ef96 4739 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 4740 #define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
Kojto 122:f9eeca106725 4741 #define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
Kojto 122:f9eeca106725 4742 #define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
Kojto 122:f9eeca106725 4743 #define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 4744 #define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 4745 #define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 4746 #define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 4747 #define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 4748 #define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
Kojto 122:f9eeca106725 4749 #define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 4750 #define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 4751 #define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 4752 #define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
Kojto 122:f9eeca106725 4753 #define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
Kojto 122:f9eeca106725 4754 #define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
Kojto 122:f9eeca106725 4755 #define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
Kojto 122:f9eeca106725 4756 #define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 4757 #define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
Kojto 122:f9eeca106725 4758 #define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
Kojto 112:6f327212ef96 4759
Kojto 112:6f327212ef96 4760 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 4761 #define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 4762 #define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 4763 #define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 4764 #define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 4765 #define FMPI2C_CR2_START 0x00002000U /*!< START generation */
Kojto 122:f9eeca106725 4766 #define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 4767 #define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 4768 #define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
Kojto 122:f9eeca106725 4769 #define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 4770 #define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 4771 #define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
Kojto 112:6f327212ef96 4772
Kojto 112:6f327212ef96 4773 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 4774 #define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
Kojto 122:f9eeca106725 4775 #define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 4776 #define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
Kojto 112:6f327212ef96 4777
Kojto 112:6f327212ef96 4778 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 122:f9eeca106725 4779 #define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
Kojto 122:f9eeca106725 4780 #define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
Kojto 122:f9eeca106725 4781 #define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
Kojto 112:6f327212ef96 4782
Kojto 112:6f327212ef96 4783 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 122:f9eeca106725 4784 #define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 4785 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 4786 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
Kojto 122:f9eeca106725 4787 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
Kojto 122:f9eeca106725 4788 #define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
Kojto 112:6f327212ef96 4789
Kojto 112:6f327212ef96 4790 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 122:f9eeca106725 4791 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
Kojto 122:f9eeca106725 4792 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 4793 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
Kojto 122:f9eeca106725 4794 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
Kojto 122:f9eeca106725 4795 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
Kojto 112:6f327212ef96 4796
Kojto 112:6f327212ef96 4797 /****************** Bit definition for I2C_ISR register *********************/
Kojto 122:f9eeca106725 4798 #define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
Kojto 122:f9eeca106725 4799 #define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 4800 #define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
Kojto 122:f9eeca106725 4801 #define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
Kojto 122:f9eeca106725 4802 #define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
Kojto 122:f9eeca106725 4803 #define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
Kojto 122:f9eeca106725 4804 #define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 4805 #define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
Kojto 122:f9eeca106725 4806 #define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
Kojto 122:f9eeca106725 4807 #define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
Kojto 122:f9eeca106725 4808 #define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 4809 #define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
Kojto 122:f9eeca106725 4810 #define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 4811 #define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
Kojto 122:f9eeca106725 4812 #define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
Kojto 122:f9eeca106725 4813 #define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 4814 #define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
Kojto 112:6f327212ef96 4815
Kojto 112:6f327212ef96 4816 /****************** Bit definition for I2C_ICR register *********************/
Kojto 122:f9eeca106725 4817 #define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
Kojto 122:f9eeca106725 4818 #define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
Kojto 122:f9eeca106725 4819 #define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 4820 #define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
Kojto 122:f9eeca106725 4821 #define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 4822 #define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 4823 #define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
Kojto 122:f9eeca106725 4824 #define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
Kojto 122:f9eeca106725 4825 #define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
Kojto 112:6f327212ef96 4826
Kojto 112:6f327212ef96 4827 /****************** Bit definition for I2C_PECR register *********************/
Kojto 122:f9eeca106725 4828 #define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
Kojto 112:6f327212ef96 4829
Kojto 112:6f327212ef96 4830 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 4831 #define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
Kojto 112:6f327212ef96 4832
Kojto 112:6f327212ef96 4833 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 122:f9eeca106725 4834 #define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
Kojto 112:6f327212ef96 4835
Kojto 112:6f327212ef96 4836 /******************************************************************************/
Kojto 112:6f327212ef96 4837 /* */
Kojto 112:6f327212ef96 4838 /* Independent WATCHDOG */
Kojto 112:6f327212ef96 4839 /* */
Kojto 112:6f327212ef96 4840 /******************************************************************************/
Kojto 112:6f327212ef96 4841 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 4842 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
Kojto 112:6f327212ef96 4843
Kojto 112:6f327212ef96 4844 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 4845 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 4846 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 4847 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 4848 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
Kojto 112:6f327212ef96 4849
Kojto 112:6f327212ef96 4850 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 4851 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
Kojto 112:6f327212ef96 4852
Kojto 112:6f327212ef96 4853 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 4854 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
Kojto 122:f9eeca106725 4855 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
Kojto 112:6f327212ef96 4856
Kojto 112:6f327212ef96 4857
Kojto 112:6f327212ef96 4858 /******************************************************************************/
Kojto 112:6f327212ef96 4859 /* */
Kojto 112:6f327212ef96 4860 /* Power Control */
Kojto 112:6f327212ef96 4861 /* */
Kojto 112:6f327212ef96 4862 /******************************************************************************/
Kojto 112:6f327212ef96 4863 /******************** Bit definition for PWR_CR register ********************/
Kojto 122:f9eeca106725 4864 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
Kojto 122:f9eeca106725 4865 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 4866 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 4867 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 4868 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 4869
Kojto 122:f9eeca106725 4870 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 4871 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
Kojto 122:f9eeca106725 4872 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
Kojto 122:f9eeca106725 4873 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
Kojto 112:6f327212ef96 4874
Kojto 112:6f327212ef96 4875 /*!< PVD level configuration */
Kojto 122:f9eeca106725 4876 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
Kojto 122:f9eeca106725 4877 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
Kojto 122:f9eeca106725 4878 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
Kojto 122:f9eeca106725 4879 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
Kojto 122:f9eeca106725 4880 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
Kojto 122:f9eeca106725 4881 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
Kojto 122:f9eeca106725 4882 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
Kojto 122:f9eeca106725 4883 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
Kojto 122:f9eeca106725 4884 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
Kojto 122:f9eeca106725 4885 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
Kojto 122:f9eeca106725 4886 #define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
Kojto 122:f9eeca106725 4887 #define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
Kojto 122:f9eeca106725 4888 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 4889 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 122:f9eeca106725 4890 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
Kojto 122:f9eeca106725 4891 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4892 #define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
Kojto 122:f9eeca106725 4893 #define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
Kojto 122:f9eeca106725 4894 #define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
Kojto 122:f9eeca106725 4895 #define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
Kojto 122:f9eeca106725 4896 #define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4897 #define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
Kojto 122:f9eeca106725 4898 #define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
Kojto 112:6f327212ef96 4899
Kojto 112:6f327212ef96 4900 /* Legacy define */
Kojto 112:6f327212ef96 4901 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 112:6f327212ef96 4902 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
Kojto 112:6f327212ef96 4903 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
Kojto 112:6f327212ef96 4904
Kojto 112:6f327212ef96 4905 /******************* Bit definition for PWR_CSR register ********************/
Kojto 122:f9eeca106725 4906 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
Kojto 122:f9eeca106725 4907 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
Kojto 122:f9eeca106725 4908 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
Kojto 122:f9eeca106725 4909 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
Kojto 122:f9eeca106725 4910 #define PWR_CSR_EWUP2 0x00000080U /*!< Enable WKUP pin 2 */
Kojto 122:f9eeca106725 4911 #define PWR_CSR_EWUP1 0x00000100U /*!< Enable WKUP pin 1 */
Kojto 122:f9eeca106725 4912 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
Kojto 122:f9eeca106725 4913 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
Kojto 122:f9eeca106725 4914 #define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
Kojto 122:f9eeca106725 4915 #define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
Kojto 122:f9eeca106725 4916 #define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
Kojto 112:6f327212ef96 4917
Kojto 112:6f327212ef96 4918 /* Legacy define */
Kojto 112:6f327212ef96 4919 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 112:6f327212ef96 4920
Kojto 112:6f327212ef96 4921 /******************************************************************************/
Kojto 112:6f327212ef96 4922 /* */
Kojto 112:6f327212ef96 4923 /* QUADSPI */
Kojto 112:6f327212ef96 4924 /* */
Kojto 112:6f327212ef96 4925 /******************************************************************************/
Kojto 112:6f327212ef96 4926 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 122:f9eeca106725 4927 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
Kojto 122:f9eeca106725 4928 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
Kojto 122:f9eeca106725 4929 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
Kojto 122:f9eeca106725 4930 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
Kojto 122:f9eeca106725 4931 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
Kojto 122:f9eeca106725 4932 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
Kojto 122:f9eeca106725 4933 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
Kojto 122:f9eeca106725 4934 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
Kojto 122:f9eeca106725 4935 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 4936 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 4937 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 4938 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
Kojto 122:f9eeca106725 4939 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
Kojto 122:f9eeca106725 4940 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
Kojto 122:f9eeca106725 4941 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
Kojto 122:f9eeca106725 4942 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
Kojto 122:f9eeca106725 4943 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
Kojto 122:f9eeca106725 4944 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 4945 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4946 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
Kojto 122:f9eeca106725 4947 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
Kojto 122:f9eeca106725 4948 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 4949 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4950 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
Kojto 122:f9eeca106725 4951 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
Kojto 122:f9eeca106725 4952 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
Kojto 122:f9eeca106725 4953 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
Kojto 122:f9eeca106725 4954 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
Kojto 122:f9eeca106725 4955 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
Kojto 112:6f327212ef96 4956
Kojto 112:6f327212ef96 4957 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 122:f9eeca106725 4958 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
Kojto 122:f9eeca106725 4959 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 122:f9eeca106725 4960 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 4961 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 4962 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 4963 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
Kojto 122:f9eeca106725 4964 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
Kojto 122:f9eeca106725 4965 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
Kojto 122:f9eeca106725 4966 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
Kojto 122:f9eeca106725 4967 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
Kojto 122:f9eeca106725 4968 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
Kojto 112:6f327212ef96 4969
Kojto 112:6f327212ef96 4970 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 122:f9eeca106725 4971 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
Kojto 122:f9eeca106725 4972 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
Kojto 122:f9eeca106725 4973 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 4974 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
Kojto 122:f9eeca106725 4975 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
Kojto 122:f9eeca106725 4976 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
Kojto 122:f9eeca106725 4977 #define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 4978 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 4979 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 4980 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 4981 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
Kojto 122:f9eeca106725 4982 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
Kojto 122:f9eeca106725 4983 #define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
Kojto 112:6f327212ef96 4984
Kojto 112:6f327212ef96 4985 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 122:f9eeca106725 4986 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
Kojto 122:f9eeca106725 4987 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
Kojto 122:f9eeca106725 4988 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
Kojto 122:f9eeca106725 4989 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
Kojto 112:6f327212ef96 4990
Kojto 112:6f327212ef96 4991 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 122:f9eeca106725 4992 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
Kojto 112:6f327212ef96 4993
Kojto 112:6f327212ef96 4994 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 122:f9eeca106725 4995 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
Kojto 122:f9eeca106725 4996 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 4997 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 4998 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
Kojto 122:f9eeca106725 4999 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
Kojto 122:f9eeca106725 5000 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
Kojto 122:f9eeca106725 5001 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
Kojto 122:f9eeca106725 5002 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
Kojto 122:f9eeca106725 5003 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
Kojto 122:f9eeca106725 5004 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 5005 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 5006 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 5007 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
Kojto 122:f9eeca106725 5008 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 5009 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 5010 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
Kojto 122:f9eeca106725 5011 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5012 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5013 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 122:f9eeca106725 5014 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5015 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5016 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 5017 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5018 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5019 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
Kojto 122:f9eeca106725 5020 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5021 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5022 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5023 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
Kojto 122:f9eeca106725 5024 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5025 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
Kojto 122:f9eeca106725 5026 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5027 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5028 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
Kojto 122:f9eeca106725 5029 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5030 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5031 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
Kojto 122:f9eeca106725 5032 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
Kojto 122:f9eeca106725 5033 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
Kojto 112:6f327212ef96 5034 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 122:f9eeca106725 5035 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
Kojto 112:6f327212ef96 5036
Kojto 112:6f327212ef96 5037 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 122:f9eeca106725 5038 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 112:6f327212ef96 5039
Kojto 112:6f327212ef96 5040 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 122:f9eeca106725 5041 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
Kojto 112:6f327212ef96 5042
Kojto 112:6f327212ef96 5043 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 122:f9eeca106725 5044 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
Kojto 112:6f327212ef96 5045
Kojto 112:6f327212ef96 5046 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 122:f9eeca106725 5047 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
Kojto 112:6f327212ef96 5048
Kojto 112:6f327212ef96 5049 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 122:f9eeca106725 5050 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
Kojto 112:6f327212ef96 5051
Kojto 112:6f327212ef96 5052 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 122:f9eeca106725 5053 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
Kojto 112:6f327212ef96 5054
Kojto 112:6f327212ef96 5055 /******************************************************************************/
Kojto 112:6f327212ef96 5056 /* */
Kojto 112:6f327212ef96 5057 /* Reset and Clock Control */
Kojto 112:6f327212ef96 5058 /* */
Kojto 112:6f327212ef96 5059 /******************************************************************************/
Kojto 112:6f327212ef96 5060 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 5061 #define RCC_CR_HSION 0x00000001U
Kojto 122:f9eeca106725 5062 #define RCC_CR_HSIRDY 0x00000002U
Kojto 122:f9eeca106725 5063
Kojto 122:f9eeca106725 5064 #define RCC_CR_HSITRIM 0x000000F8U
Kojto 122:f9eeca106725 5065 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
Kojto 122:f9eeca106725 5066 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
Kojto 122:f9eeca106725 5067 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
Kojto 122:f9eeca106725 5068 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
Kojto 122:f9eeca106725 5069 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
Kojto 122:f9eeca106725 5070
Kojto 122:f9eeca106725 5071 #define RCC_CR_HSICAL 0x0000FF00U
Kojto 122:f9eeca106725 5072 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
Kojto 122:f9eeca106725 5073 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
Kojto 122:f9eeca106725 5074 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
Kojto 122:f9eeca106725 5075 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
Kojto 122:f9eeca106725 5076 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
Kojto 122:f9eeca106725 5077 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
Kojto 122:f9eeca106725 5078 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
Kojto 122:f9eeca106725 5079 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
Kojto 122:f9eeca106725 5080
Kojto 122:f9eeca106725 5081 #define RCC_CR_HSEON 0x00010000U
Kojto 122:f9eeca106725 5082 #define RCC_CR_HSERDY 0x00020000U
Kojto 122:f9eeca106725 5083 #define RCC_CR_HSEBYP 0x00040000U
Kojto 122:f9eeca106725 5084 #define RCC_CR_CSSON 0x00080000U
Kojto 122:f9eeca106725 5085 #define RCC_CR_PLLON 0x01000000U
Kojto 122:f9eeca106725 5086 #define RCC_CR_PLLRDY 0x02000000U
Kojto 122:f9eeca106725 5087 #define RCC_CR_PLLI2SON 0x04000000U
Kojto 122:f9eeca106725 5088 #define RCC_CR_PLLI2SRDY 0x08000000U
Kojto 122:f9eeca106725 5089 #define RCC_CR_PLLSAION 0x10000000U
Kojto 122:f9eeca106725 5090 #define RCC_CR_PLLSAIRDY 0x20000000U
Kojto 112:6f327212ef96 5091
Kojto 112:6f327212ef96 5092 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 122:f9eeca106725 5093 #define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto 122:f9eeca106725 5094 #define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto 122:f9eeca106725 5095 #define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto 122:f9eeca106725 5096 #define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto 122:f9eeca106725 5097 #define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto 122:f9eeca106725 5098 #define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto 122:f9eeca106725 5099 #define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto 122:f9eeca106725 5100
Kojto 122:f9eeca106725 5101 #define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto 122:f9eeca106725 5102 #define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto 122:f9eeca106725 5103 #define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto 122:f9eeca106725 5104 #define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto 122:f9eeca106725 5105 #define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto 122:f9eeca106725 5106 #define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto 122:f9eeca106725 5107 #define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto 122:f9eeca106725 5108 #define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto 122:f9eeca106725 5109 #define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto 122:f9eeca106725 5110 #define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto 122:f9eeca106725 5111
Kojto 122:f9eeca106725 5112 #define RCC_PLLCFGR_PLLP 0x00030000U
Kojto 122:f9eeca106725 5113 #define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto 122:f9eeca106725 5114 #define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto 122:f9eeca106725 5115
Kojto 122:f9eeca106725 5116 #define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto 122:f9eeca106725 5117 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto 122:f9eeca106725 5118 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto 122:f9eeca106725 5119
Kojto 122:f9eeca106725 5120 #define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto 122:f9eeca106725 5121 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto 122:f9eeca106725 5122 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto 122:f9eeca106725 5123 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto 122:f9eeca106725 5124 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
Kojto 122:f9eeca106725 5125
Kojto 122:f9eeca106725 5126 #define RCC_PLLCFGR_PLLR 0x70000000U
Kojto 122:f9eeca106725 5127 #define RCC_PLLCFGR_PLLR_0 0x10000000U
Kojto 122:f9eeca106725 5128 #define RCC_PLLCFGR_PLLR_1 0x20000000U
Kojto 122:f9eeca106725 5129 #define RCC_PLLCFGR_PLLR_2 0x40000000U
Kojto 112:6f327212ef96 5130
Kojto 112:6f327212ef96 5131
Kojto 112:6f327212ef96 5132 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 112:6f327212ef96 5133 /*!< SW configuration */
Kojto 122:f9eeca106725 5134 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 5135 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 5136 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 5137
Kojto 122:f9eeca106725 5138 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 5139 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 5140 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
Kojto 122:f9eeca106725 5141 #define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
Kojto 112:6f327212ef96 5142
Kojto 112:6f327212ef96 5143 /*!< SWS configuration */
Kojto 122:f9eeca106725 5144 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 5145 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
Kojto 122:f9eeca106725 5146 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
Kojto 122:f9eeca106725 5147
Kojto 122:f9eeca106725 5148 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 5149 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 5150 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
Kojto 122:f9eeca106725 5151 #define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
Kojto 112:6f327212ef96 5152
Kojto 112:6f327212ef96 5153 /*!< HPRE configuration */
Kojto 122:f9eeca106725 5154 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 5155 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
Kojto 122:f9eeca106725 5156 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
Kojto 122:f9eeca106725 5157 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
Kojto 122:f9eeca106725 5158 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
Kojto 122:f9eeca106725 5159
Kojto 122:f9eeca106725 5160 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 5161 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 5162 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 5163 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 5164 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 5165 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 5166 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 5167 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 5168 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
Kojto 112:6f327212ef96 5169
Kojto 112:6f327212ef96 5170 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 5171 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 5172 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 5173 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 5174 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5175
Kojto 122:f9eeca106725 5176 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 5177 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 5178 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 5179 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 5180 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
Kojto 112:6f327212ef96 5181
Kojto 112:6f327212ef96 5182 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 5183 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 5184 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5185 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5186 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5187
Kojto 122:f9eeca106725 5188 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 5189 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 5190 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 5191 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 5192 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
Kojto 112:6f327212ef96 5193
Kojto 112:6f327212ef96 5194 /*!< RTCPRE configuration */
Kojto 122:f9eeca106725 5195 #define RCC_CFGR_RTCPRE 0x001F0000U
Kojto 122:f9eeca106725 5196 #define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto 122:f9eeca106725 5197 #define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto 122:f9eeca106725 5198 #define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto 122:f9eeca106725 5199 #define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto 122:f9eeca106725 5200 #define RCC_CFGR_RTCPRE_4 0x00100000U
Kojto 112:6f327212ef96 5201
Kojto 112:6f327212ef96 5202 /*!< MCO1 configuration */
Kojto 122:f9eeca106725 5203 #define RCC_CFGR_MCO1 0x00600000U
Kojto 122:f9eeca106725 5204 #define RCC_CFGR_MCO1_0 0x00200000U
Kojto 122:f9eeca106725 5205 #define RCC_CFGR_MCO1_1 0x00400000U
Kojto 122:f9eeca106725 5206
Kojto 122:f9eeca106725 5207 #define RCC_CFGR_I2SSRC 0x00800000U
Kojto 122:f9eeca106725 5208
Kojto 122:f9eeca106725 5209 #define RCC_CFGR_MCO1PRE 0x07000000U
Kojto 122:f9eeca106725 5210 #define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto 122:f9eeca106725 5211 #define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto 122:f9eeca106725 5212 #define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto 122:f9eeca106725 5213
Kojto 122:f9eeca106725 5214 #define RCC_CFGR_MCO2PRE 0x38000000U
Kojto 122:f9eeca106725 5215 #define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto 122:f9eeca106725 5216 #define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto 122:f9eeca106725 5217 #define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto 122:f9eeca106725 5218
Kojto 122:f9eeca106725 5219 #define RCC_CFGR_MCO2 0xC0000000U
Kojto 122:f9eeca106725 5220 #define RCC_CFGR_MCO2_0 0x40000000U
Kojto 122:f9eeca106725 5221 #define RCC_CFGR_MCO2_1 0x80000000U
Kojto 112:6f327212ef96 5222
Kojto 112:6f327212ef96 5223 /******************** Bit definition for RCC_CIR register *******************/
Kojto 122:f9eeca106725 5224 #define RCC_CIR_LSIRDYF 0x00000001U
Kojto 122:f9eeca106725 5225 #define RCC_CIR_LSERDYF 0x00000002U
Kojto 122:f9eeca106725 5226 #define RCC_CIR_HSIRDYF 0x00000004U
Kojto 122:f9eeca106725 5227 #define RCC_CIR_HSERDYF 0x00000008U
Kojto 122:f9eeca106725 5228 #define RCC_CIR_PLLRDYF 0x00000010U
Kojto 122:f9eeca106725 5229 #define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto 122:f9eeca106725 5230 #define RCC_CIR_PLLSAIRDYF 0x00000040U
Kojto 122:f9eeca106725 5231 #define RCC_CIR_CSSF 0x00000080U
Kojto 122:f9eeca106725 5232 #define RCC_CIR_LSIRDYIE 0x00000100U
Kojto 122:f9eeca106725 5233 #define RCC_CIR_LSERDYIE 0x00000200U
Kojto 122:f9eeca106725 5234 #define RCC_CIR_HSIRDYIE 0x00000400U
Kojto 122:f9eeca106725 5235 #define RCC_CIR_HSERDYIE 0x00000800U
Kojto 122:f9eeca106725 5236 #define RCC_CIR_PLLRDYIE 0x00001000U
Kojto 122:f9eeca106725 5237 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto 122:f9eeca106725 5238 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
Kojto 122:f9eeca106725 5239 #define RCC_CIR_LSIRDYC 0x00010000U
Kojto 122:f9eeca106725 5240 #define RCC_CIR_LSERDYC 0x00020000U
Kojto 122:f9eeca106725 5241 #define RCC_CIR_HSIRDYC 0x00040000U
Kojto 122:f9eeca106725 5242 #define RCC_CIR_HSERDYC 0x00080000U
Kojto 122:f9eeca106725 5243 #define RCC_CIR_PLLRDYC 0x00100000U
Kojto 122:f9eeca106725 5244 #define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto 122:f9eeca106725 5245 #define RCC_CIR_PLLSAIRDYC 0x00400000U
Kojto 122:f9eeca106725 5246 #define RCC_CIR_CSSC 0x00800000U
Kojto 112:6f327212ef96 5247
Kojto 112:6f327212ef96 5248 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 122:f9eeca106725 5249 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto 122:f9eeca106725 5250 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto 122:f9eeca106725 5251 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto 122:f9eeca106725 5252 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto 122:f9eeca106725 5253 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto 122:f9eeca106725 5254 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
Kojto 122:f9eeca106725 5255 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
Kojto 122:f9eeca106725 5256 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto 122:f9eeca106725 5257 #define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto 122:f9eeca106725 5258 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto 122:f9eeca106725 5259 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto 122:f9eeca106725 5260 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
Kojto 112:6f327212ef96 5261
Kojto 112:6f327212ef96 5262 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 122:f9eeca106725 5263 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
Kojto 122:f9eeca106725 5264 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
Kojto 112:6f327212ef96 5265
Kojto 112:6f327212ef96 5266 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 122:f9eeca106725 5267 #define RCC_AHB3RSTR_FMCRST 0x00000001U
Kojto 122:f9eeca106725 5268 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
Kojto 112:6f327212ef96 5269
Kojto 112:6f327212ef96 5270 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 122:f9eeca106725 5271 #define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto 122:f9eeca106725 5272 #define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto 122:f9eeca106725 5273 #define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto 122:f9eeca106725 5274 #define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto 122:f9eeca106725 5275 #define RCC_APB1RSTR_TIM6RST 0x00000010U
Kojto 122:f9eeca106725 5276 #define RCC_APB1RSTR_TIM7RST 0x00000020U
Kojto 122:f9eeca106725 5277 #define RCC_APB1RSTR_TIM12RST 0x00000040U
Kojto 122:f9eeca106725 5278 #define RCC_APB1RSTR_TIM13RST 0x00000080U
Kojto 122:f9eeca106725 5279 #define RCC_APB1RSTR_TIM14RST 0x00000100U
Kojto 122:f9eeca106725 5280 #define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto 122:f9eeca106725 5281 #define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto 122:f9eeca106725 5282 #define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto 122:f9eeca106725 5283 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
Kojto 122:f9eeca106725 5284 #define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto 122:f9eeca106725 5285 #define RCC_APB1RSTR_USART3RST 0x00040000U
Kojto 122:f9eeca106725 5286 #define RCC_APB1RSTR_UART4RST 0x00080000U
Kojto 122:f9eeca106725 5287 #define RCC_APB1RSTR_UART5RST 0x00100000U
Kojto 122:f9eeca106725 5288 #define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto 122:f9eeca106725 5289 #define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto 122:f9eeca106725 5290 #define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto 122:f9eeca106725 5291 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
Kojto 122:f9eeca106725 5292 #define RCC_APB1RSTR_CAN1RST 0x02000000U
Kojto 122:f9eeca106725 5293 #define RCC_APB1RSTR_CAN2RST 0x04000000U
Kojto 122:f9eeca106725 5294 #define RCC_APB1RSTR_CECRST 0x08000000U
Kojto 122:f9eeca106725 5295 #define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto 122:f9eeca106725 5296 #define RCC_APB1RSTR_DACRST 0x20000000U
Kojto 112:6f327212ef96 5297
Kojto 112:6f327212ef96 5298 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 122:f9eeca106725 5299 #define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto 122:f9eeca106725 5300 #define RCC_APB2RSTR_TIM8RST 0x00000002U
Kojto 122:f9eeca106725 5301 #define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto 122:f9eeca106725 5302 #define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto 122:f9eeca106725 5303 #define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto 122:f9eeca106725 5304 #define RCC_APB2RSTR_SDIORST 0x00000800U
Kojto 122:f9eeca106725 5305 #define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto 122:f9eeca106725 5306 #define RCC_APB2RSTR_SPI4RST 0x00002000U
Kojto 122:f9eeca106725 5307 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto 122:f9eeca106725 5308 #define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto 122:f9eeca106725 5309 #define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto 122:f9eeca106725 5310 #define RCC_APB2RSTR_TIM11RST 0x00040000U
Kojto 122:f9eeca106725 5311 #define RCC_APB2RSTR_SAI1RST 0x00400000U
Kojto 122:f9eeca106725 5312 #define RCC_APB2RSTR_SAI2RST 0x00800000U
Kojto 112:6f327212ef96 5313
Kojto 112:6f327212ef96 5314 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 5315 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 112:6f327212ef96 5316
Kojto 112:6f327212ef96 5317 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 122:f9eeca106725 5318 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto 122:f9eeca106725 5319 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto 122:f9eeca106725 5320 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto 122:f9eeca106725 5321 #define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto 122:f9eeca106725 5322 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto 122:f9eeca106725 5323 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
Kojto 122:f9eeca106725 5324 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
Kojto 122:f9eeca106725 5325 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto 122:f9eeca106725 5326
Kojto 122:f9eeca106725 5327 #define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto 122:f9eeca106725 5328 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto 122:f9eeca106725 5329 #define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto 122:f9eeca106725 5330 #define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto 122:f9eeca106725 5331
Kojto 122:f9eeca106725 5332 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
Kojto 122:f9eeca106725 5333 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
Kojto 112:6f327212ef96 5334
Kojto 112:6f327212ef96 5335 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 122:f9eeca106725 5336 #define RCC_AHB2ENR_DCMIEN 0x00000001U
Kojto 122:f9eeca106725 5337 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
Kojto 112:6f327212ef96 5338
Kojto 112:6f327212ef96 5339 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 122:f9eeca106725 5340 #define RCC_AHB3ENR_FMCEN 0x00000001U
Kojto 122:f9eeca106725 5341 #define RCC_AHB3ENR_QSPIEN 0x00000002U
Kojto 112:6f327212ef96 5342
Kojto 112:6f327212ef96 5343 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 122:f9eeca106725 5344 #define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto 122:f9eeca106725 5345 #define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto 122:f9eeca106725 5346 #define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto 122:f9eeca106725 5347 #define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto 122:f9eeca106725 5348 #define RCC_APB1ENR_TIM6EN 0x00000010U
Kojto 122:f9eeca106725 5349 #define RCC_APB1ENR_TIM7EN 0x00000020U
Kojto 122:f9eeca106725 5350 #define RCC_APB1ENR_TIM12EN 0x00000040U
Kojto 122:f9eeca106725 5351 #define RCC_APB1ENR_TIM13EN 0x00000080U
Kojto 122:f9eeca106725 5352 #define RCC_APB1ENR_TIM14EN 0x00000100U
Kojto 122:f9eeca106725 5353 #define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto 122:f9eeca106725 5354 #define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto 122:f9eeca106725 5355 #define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto 122:f9eeca106725 5356 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
Kojto 122:f9eeca106725 5357 #define RCC_APB1ENR_USART2EN 0x00020000U
Kojto 122:f9eeca106725 5358 #define RCC_APB1ENR_USART3EN 0x00040000U
Kojto 122:f9eeca106725 5359 #define RCC_APB1ENR_UART4EN 0x00080000U
Kojto 122:f9eeca106725 5360 #define RCC_APB1ENR_UART5EN 0x00100000U
Kojto 122:f9eeca106725 5361 #define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto 122:f9eeca106725 5362 #define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto 122:f9eeca106725 5363 #define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto 122:f9eeca106725 5364 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
Kojto 122:f9eeca106725 5365 #define RCC_APB1ENR_CAN1EN 0x02000000U
Kojto 122:f9eeca106725 5366 #define RCC_APB1ENR_CAN2EN 0x04000000U
Kojto 122:f9eeca106725 5367 #define RCC_APB1ENR_CECEN 0x08000000U
Kojto 122:f9eeca106725 5368 #define RCC_APB1ENR_PWREN 0x10000000U
Kojto 122:f9eeca106725 5369 #define RCC_APB1ENR_DACEN 0x20000000U
Kojto 112:6f327212ef96 5370
Kojto 112:6f327212ef96 5371 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 122:f9eeca106725 5372 #define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto 122:f9eeca106725 5373 #define RCC_APB2ENR_TIM8EN 0x00000002U
Kojto 122:f9eeca106725 5374 #define RCC_APB2ENR_USART1EN 0x00000010U
Kojto 122:f9eeca106725 5375 #define RCC_APB2ENR_USART6EN 0x00000020U
Kojto 122:f9eeca106725 5376 #define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto 122:f9eeca106725 5377 #define RCC_APB2ENR_ADC2EN 0x00000200U
Kojto 122:f9eeca106725 5378 #define RCC_APB2ENR_ADC3EN 0x00000400U
Kojto 122:f9eeca106725 5379 #define RCC_APB2ENR_SDIOEN 0x00000800U
Kojto 122:f9eeca106725 5380 #define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto 122:f9eeca106725 5381 #define RCC_APB2ENR_SPI4EN 0x00002000U
Kojto 122:f9eeca106725 5382 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto 122:f9eeca106725 5383 #define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto 122:f9eeca106725 5384 #define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto 122:f9eeca106725 5385 #define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto 122:f9eeca106725 5386 #define RCC_APB2ENR_SAI1EN 0x00400000U
Kojto 122:f9eeca106725 5387 #define RCC_APB2ENR_SAI2EN 0x00800000U
Kojto 112:6f327212ef96 5388
Kojto 112:6f327212ef96 5389 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 122:f9eeca106725 5390 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto 122:f9eeca106725 5391 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto 122:f9eeca106725 5392 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto 122:f9eeca106725 5393 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto 122:f9eeca106725 5394 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto 122:f9eeca106725 5395 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
Kojto 122:f9eeca106725 5396 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
Kojto 122:f9eeca106725 5397 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto 122:f9eeca106725 5398 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
Kojto 122:f9eeca106725 5399 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
Kojto 122:f9eeca106725 5400 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
Kojto 122:f9eeca106725 5401
Kojto 122:f9eeca106725 5402 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto 122:f9eeca106725 5403 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto 122:f9eeca106725 5404 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto 122:f9eeca106725 5405 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto 122:f9eeca106725 5406 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto 122:f9eeca106725 5407 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto 122:f9eeca106725 5408 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto 122:f9eeca106725 5409
Kojto 122:f9eeca106725 5410 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
Kojto 122:f9eeca106725 5411 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
Kojto 112:6f327212ef96 5412
Kojto 112:6f327212ef96 5413 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 122:f9eeca106725 5414 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
Kojto 122:f9eeca106725 5415 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
Kojto 112:6f327212ef96 5416
Kojto 112:6f327212ef96 5417 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 122:f9eeca106725 5418 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
Kojto 122:f9eeca106725 5419 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
Kojto 112:6f327212ef96 5420
Kojto 112:6f327212ef96 5421 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 122:f9eeca106725 5422 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto 122:f9eeca106725 5423 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto 122:f9eeca106725 5424 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto 122:f9eeca106725 5425 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto 122:f9eeca106725 5426 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
Kojto 122:f9eeca106725 5427 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
Kojto 122:f9eeca106725 5428 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
Kojto 122:f9eeca106725 5429 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
Kojto 122:f9eeca106725 5430 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
Kojto 122:f9eeca106725 5431 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto 122:f9eeca106725 5432 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto 122:f9eeca106725 5433 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto 122:f9eeca106725 5434 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
Kojto 122:f9eeca106725 5435 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto 122:f9eeca106725 5436 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
Kojto 122:f9eeca106725 5437 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
Kojto 122:f9eeca106725 5438 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
Kojto 122:f9eeca106725 5439 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto 122:f9eeca106725 5440 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto 122:f9eeca106725 5441 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto 122:f9eeca106725 5442 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
Kojto 122:f9eeca106725 5443 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
Kojto 122:f9eeca106725 5444 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
Kojto 122:f9eeca106725 5445 #define RCC_APB1LPENR_CECLPEN 0x08000000U
Kojto 122:f9eeca106725 5446 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto 122:f9eeca106725 5447 #define RCC_APB1LPENR_DACLPEN 0x20000000U
Kojto 112:6f327212ef96 5448
Kojto 112:6f327212ef96 5449 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 122:f9eeca106725 5450 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto 122:f9eeca106725 5451 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
Kojto 122:f9eeca106725 5452 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto 122:f9eeca106725 5453 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto 122:f9eeca106725 5454 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto 122:f9eeca106725 5455 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
Kojto 122:f9eeca106725 5456 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
Kojto 122:f9eeca106725 5457 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
Kojto 122:f9eeca106725 5458 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto 122:f9eeca106725 5459 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
Kojto 122:f9eeca106725 5460 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto 122:f9eeca106725 5461 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto 122:f9eeca106725 5462 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto 122:f9eeca106725 5463 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
Kojto 122:f9eeca106725 5464 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
Kojto 122:f9eeca106725 5465 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
Kojto 112:6f327212ef96 5466
Kojto 112:6f327212ef96 5467 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 5468 #define RCC_BDCR_LSEON 0x00000001U
Kojto 122:f9eeca106725 5469 #define RCC_BDCR_LSERDY 0x00000002U
Kojto 122:f9eeca106725 5470 #define RCC_BDCR_LSEBYP 0x00000004U
Kojto 122:f9eeca106725 5471 #define RCC_BDCR_LSEMOD 0x00000008U
Kojto 122:f9eeca106725 5472
Kojto 122:f9eeca106725 5473 #define RCC_BDCR_RTCSEL 0x00000300U
Kojto 122:f9eeca106725 5474 #define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto 122:f9eeca106725 5475 #define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto 122:f9eeca106725 5476
Kojto 122:f9eeca106725 5477 #define RCC_BDCR_RTCEN 0x00008000U
Kojto 122:f9eeca106725 5478 #define RCC_BDCR_BDRST 0x00010000U
Kojto 112:6f327212ef96 5479
Kojto 112:6f327212ef96 5480 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 5481 #define RCC_CSR_LSION 0x00000001U
Kojto 122:f9eeca106725 5482 #define RCC_CSR_LSIRDY 0x00000002U
Kojto 122:f9eeca106725 5483 #define RCC_CSR_RMVF 0x01000000U
Kojto 122:f9eeca106725 5484 #define RCC_CSR_BORRSTF 0x02000000U
Kojto 122:f9eeca106725 5485 #define RCC_CSR_PADRSTF 0x04000000U
Kojto 122:f9eeca106725 5486 #define RCC_CSR_PORRSTF 0x08000000U
Kojto 122:f9eeca106725 5487 #define RCC_CSR_SFTRSTF 0x10000000U
Kojto 122:f9eeca106725 5488 #define RCC_CSR_WDGRSTF 0x20000000U
Kojto 122:f9eeca106725 5489 #define RCC_CSR_WWDGRSTF 0x40000000U
Kojto 122:f9eeca106725 5490 #define RCC_CSR_LPWRRSTF 0x80000000U
Kojto 112:6f327212ef96 5491
Kojto 112:6f327212ef96 5492 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 122:f9eeca106725 5493 #define RCC_SSCGR_MODPER 0x00001FFFU
Kojto 122:f9eeca106725 5494 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto 122:f9eeca106725 5495 #define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto 122:f9eeca106725 5496 #define RCC_SSCGR_SSCGEN 0x80000000U
Kojto 112:6f327212ef96 5497
Kojto 112:6f327212ef96 5498 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 122:f9eeca106725 5499 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
Kojto 122:f9eeca106725 5500 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
Kojto 122:f9eeca106725 5501 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
Kojto 122:f9eeca106725 5502 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
Kojto 122:f9eeca106725 5503 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
Kojto 122:f9eeca106725 5504 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
Kojto 122:f9eeca106725 5505 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
Kojto 122:f9eeca106725 5506
Kojto 122:f9eeca106725 5507 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto 122:f9eeca106725 5508 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto 122:f9eeca106725 5509 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto 122:f9eeca106725 5510 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto 122:f9eeca106725 5511 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto 122:f9eeca106725 5512 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto 122:f9eeca106725 5513 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto 122:f9eeca106725 5514 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto 122:f9eeca106725 5515 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto 122:f9eeca106725 5516 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto 122:f9eeca106725 5517
Kojto 122:f9eeca106725 5518 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
Kojto 122:f9eeca106725 5519 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
Kojto 122:f9eeca106725 5520 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
Kojto 122:f9eeca106725 5521
Kojto 122:f9eeca106725 5522 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
Kojto 122:f9eeca106725 5523 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
Kojto 122:f9eeca106725 5524 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
Kojto 122:f9eeca106725 5525 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
Kojto 122:f9eeca106725 5526 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
Kojto 122:f9eeca106725 5527
Kojto 122:f9eeca106725 5528 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto 122:f9eeca106725 5529 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto 122:f9eeca106725 5530 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto 122:f9eeca106725 5531 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
Kojto 112:6f327212ef96 5532
Kojto 112:6f327212ef96 5533
Kojto 112:6f327212ef96 5534 /******************** Bit definition for RCC_PLLSAICFGR register ************/
Kojto 122:f9eeca106725 5535 #define RCC_PLLSAICFGR_PLLSAIM 0x0000003FU
Kojto 122:f9eeca106725 5536 #define RCC_PLLSAICFGR_PLLSAIM_0 0x00000001U
Kojto 122:f9eeca106725 5537 #define RCC_PLLSAICFGR_PLLSAIM_1 0x00000002U
Kojto 122:f9eeca106725 5538 #define RCC_PLLSAICFGR_PLLSAIM_2 0x00000004U
Kojto 122:f9eeca106725 5539 #define RCC_PLLSAICFGR_PLLSAIM_3 0x00000008U
Kojto 122:f9eeca106725 5540 #define RCC_PLLSAICFGR_PLLSAIM_4 0x00000010U
Kojto 122:f9eeca106725 5541 #define RCC_PLLSAICFGR_PLLSAIM_5 0x00000020U
Kojto 122:f9eeca106725 5542
Kojto 122:f9eeca106725 5543 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
Kojto 122:f9eeca106725 5544 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
Kojto 122:f9eeca106725 5545 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
Kojto 122:f9eeca106725 5546 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
Kojto 122:f9eeca106725 5547 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
Kojto 122:f9eeca106725 5548 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
Kojto 122:f9eeca106725 5549 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
Kojto 122:f9eeca106725 5550 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
Kojto 122:f9eeca106725 5551 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
Kojto 122:f9eeca106725 5552 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
Kojto 122:f9eeca106725 5553
Kojto 122:f9eeca106725 5554 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
Kojto 122:f9eeca106725 5555 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
Kojto 122:f9eeca106725 5556 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
Kojto 122:f9eeca106725 5557
Kojto 122:f9eeca106725 5558 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
Kojto 122:f9eeca106725 5559 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
Kojto 122:f9eeca106725 5560 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
Kojto 122:f9eeca106725 5561 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
Kojto 122:f9eeca106725 5562 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
Kojto 112:6f327212ef96 5563
Kojto 112:6f327212ef96 5564 /******************** Bit definition for RCC_DCKCFGR register ***************/
Kojto 122:f9eeca106725 5565 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
Kojto 122:f9eeca106725 5566 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
Kojto 122:f9eeca106725 5567 #define RCC_DCKCFGR_SAI1SRC 0x00300000U
Kojto 122:f9eeca106725 5568 #define RCC_DCKCFGR_SAI1SRC_0 0x00100000U
Kojto 122:f9eeca106725 5569 #define RCC_DCKCFGR_SAI1SRC_1 0x00200000U
Kojto 122:f9eeca106725 5570 #define RCC_DCKCFGR_SAI2SRC 0x00C00000U
Kojto 122:f9eeca106725 5571 #define RCC_DCKCFGR_SAI2SRC_0 0x00400000U
Kojto 122:f9eeca106725 5572 #define RCC_DCKCFGR_SAI2SRC_1 0x00800000U
Kojto 122:f9eeca106725 5573 #define RCC_DCKCFGR_TIMPRE 0x01000000U
Kojto 122:f9eeca106725 5574 #define RCC_DCKCFGR_I2S1SRC 0x06000000U
Kojto 122:f9eeca106725 5575 #define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
Kojto 122:f9eeca106725 5576 #define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
Kojto 122:f9eeca106725 5577 #define RCC_DCKCFGR_I2S2SRC 0x18000000U
Kojto 122:f9eeca106725 5578 #define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
Kojto 122:f9eeca106725 5579 #define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
Kojto 112:6f327212ef96 5580
Kojto 112:6f327212ef96 5581 /******************** Bit definition for RCC_CKGATENR register ***************/
Kojto 122:f9eeca106725 5582 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
Kojto 122:f9eeca106725 5583 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
Kojto 122:f9eeca106725 5584 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
Kojto 122:f9eeca106725 5585 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
Kojto 122:f9eeca106725 5586 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
Kojto 122:f9eeca106725 5587 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
Kojto 122:f9eeca106725 5588 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
Kojto 112:6f327212ef96 5589
Kojto 112:6f327212ef96 5590 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
Kojto 122:f9eeca106725 5591 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
Kojto 122:f9eeca106725 5592 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
Kojto 122:f9eeca106725 5593 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
Kojto 122:f9eeca106725 5594 #define RCC_DCKCFGR2_CECSEL 0x04000000U
Kojto 122:f9eeca106725 5595 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
Kojto 122:f9eeca106725 5596 #define RCC_DCKCFGR2_SDIOSEL 0x10000000U
Kojto 122:f9eeca106725 5597 #define RCC_DCKCFGR2_SPDIFRXSEL 0x20000000U
Kojto 112:6f327212ef96 5598
Kojto 112:6f327212ef96 5599 /******************************************************************************/
Kojto 112:6f327212ef96 5600 /* */
Kojto 112:6f327212ef96 5601 /* Real-Time Clock (RTC) */
Kojto 112:6f327212ef96 5602 /* */
Kojto 112:6f327212ef96 5603 /******************************************************************************/
Kojto 112:6f327212ef96 5604 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 5605 #define RTC_TR_PM 0x00400000U
Kojto 122:f9eeca106725 5606 #define RTC_TR_HT 0x00300000U
Kojto 122:f9eeca106725 5607 #define RTC_TR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5608 #define RTC_TR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5609 #define RTC_TR_HU 0x000F0000U
Kojto 122:f9eeca106725 5610 #define RTC_TR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5611 #define RTC_TR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5612 #define RTC_TR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5613 #define RTC_TR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5614 #define RTC_TR_MNT 0x00007000U
Kojto 122:f9eeca106725 5615 #define RTC_TR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5616 #define RTC_TR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5617 #define RTC_TR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5618 #define RTC_TR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5619 #define RTC_TR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5620 #define RTC_TR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5621 #define RTC_TR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5622 #define RTC_TR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5623 #define RTC_TR_ST 0x00000070U
Kojto 122:f9eeca106725 5624 #define RTC_TR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5625 #define RTC_TR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5626 #define RTC_TR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5627 #define RTC_TR_SU 0x0000000FU
Kojto 122:f9eeca106725 5628 #define RTC_TR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5629 #define RTC_TR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5630 #define RTC_TR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5631 #define RTC_TR_SU_3 0x00000008U
Kojto 112:6f327212ef96 5632
Kojto 112:6f327212ef96 5633 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 5634 #define RTC_DR_YT 0x00F00000U
Kojto 122:f9eeca106725 5635 #define RTC_DR_YT_0 0x00100000U
Kojto 122:f9eeca106725 5636 #define RTC_DR_YT_1 0x00200000U
Kojto 122:f9eeca106725 5637 #define RTC_DR_YT_2 0x00400000U
Kojto 122:f9eeca106725 5638 #define RTC_DR_YT_3 0x00800000U
Kojto 122:f9eeca106725 5639 #define RTC_DR_YU 0x000F0000U
Kojto 122:f9eeca106725 5640 #define RTC_DR_YU_0 0x00010000U
Kojto 122:f9eeca106725 5641 #define RTC_DR_YU_1 0x00020000U
Kojto 122:f9eeca106725 5642 #define RTC_DR_YU_2 0x00040000U
Kojto 122:f9eeca106725 5643 #define RTC_DR_YU_3 0x00080000U
Kojto 122:f9eeca106725 5644 #define RTC_DR_WDU 0x0000E000U
Kojto 122:f9eeca106725 5645 #define RTC_DR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 5646 #define RTC_DR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 5647 #define RTC_DR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 5648 #define RTC_DR_MT 0x00001000U
Kojto 122:f9eeca106725 5649 #define RTC_DR_MU 0x00000F00U
Kojto 122:f9eeca106725 5650 #define RTC_DR_MU_0 0x00000100U
Kojto 122:f9eeca106725 5651 #define RTC_DR_MU_1 0x00000200U
Kojto 122:f9eeca106725 5652 #define RTC_DR_MU_2 0x00000400U
Kojto 122:f9eeca106725 5653 #define RTC_DR_MU_3 0x00000800U
Kojto 122:f9eeca106725 5654 #define RTC_DR_DT 0x00000030U
Kojto 122:f9eeca106725 5655 #define RTC_DR_DT_0 0x00000010U
Kojto 122:f9eeca106725 5656 #define RTC_DR_DT_1 0x00000020U
Kojto 122:f9eeca106725 5657 #define RTC_DR_DU 0x0000000FU
Kojto 122:f9eeca106725 5658 #define RTC_DR_DU_0 0x00000001U
Kojto 122:f9eeca106725 5659 #define RTC_DR_DU_1 0x00000002U
Kojto 122:f9eeca106725 5660 #define RTC_DR_DU_2 0x00000004U
Kojto 122:f9eeca106725 5661 #define RTC_DR_DU_3 0x00000008U
Kojto 112:6f327212ef96 5662
Kojto 112:6f327212ef96 5663 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 5664 #define RTC_CR_COE 0x00800000U
Kojto 122:f9eeca106725 5665 #define RTC_CR_OSEL 0x00600000U
Kojto 122:f9eeca106725 5666 #define RTC_CR_OSEL_0 0x00200000U
Kojto 122:f9eeca106725 5667 #define RTC_CR_OSEL_1 0x00400000U
Kojto 122:f9eeca106725 5668 #define RTC_CR_POL 0x00100000U
Kojto 122:f9eeca106725 5669 #define RTC_CR_COSEL 0x00080000U
Kojto 122:f9eeca106725 5670 #define RTC_CR_BCK 0x00040000U
Kojto 122:f9eeca106725 5671 #define RTC_CR_SUB1H 0x00020000U
Kojto 122:f9eeca106725 5672 #define RTC_CR_ADD1H 0x00010000U
Kojto 122:f9eeca106725 5673 #define RTC_CR_TSIE 0x00008000U
Kojto 122:f9eeca106725 5674 #define RTC_CR_WUTIE 0x00004000U
Kojto 122:f9eeca106725 5675 #define RTC_CR_ALRBIE 0x00002000U
Kojto 122:f9eeca106725 5676 #define RTC_CR_ALRAIE 0x00001000U
Kojto 122:f9eeca106725 5677 #define RTC_CR_TSE 0x00000800U
Kojto 122:f9eeca106725 5678 #define RTC_CR_WUTE 0x00000400U
Kojto 122:f9eeca106725 5679 #define RTC_CR_ALRBE 0x00000200U
Kojto 122:f9eeca106725 5680 #define RTC_CR_ALRAE 0x00000100U
Kojto 122:f9eeca106725 5681 #define RTC_CR_DCE 0x00000080U
Kojto 122:f9eeca106725 5682 #define RTC_CR_FMT 0x00000040U
Kojto 122:f9eeca106725 5683 #define RTC_CR_BYPSHAD 0x00000020U
Kojto 122:f9eeca106725 5684 #define RTC_CR_REFCKON 0x00000010U
Kojto 122:f9eeca106725 5685 #define RTC_CR_TSEDGE 0x00000008U
Kojto 122:f9eeca106725 5686 #define RTC_CR_WUCKSEL 0x00000007U
Kojto 122:f9eeca106725 5687 #define RTC_CR_WUCKSEL_0 0x00000001U
Kojto 122:f9eeca106725 5688 #define RTC_CR_WUCKSEL_1 0x00000002U
Kojto 122:f9eeca106725 5689 #define RTC_CR_WUCKSEL_2 0x00000004U
Kojto 112:6f327212ef96 5690
Kojto 112:6f327212ef96 5691 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 5692 #define RTC_ISR_RECALPF 0x00010000U
Kojto 122:f9eeca106725 5693 #define RTC_ISR_TAMP1F 0x00002000U
Kojto 122:f9eeca106725 5694 #define RTC_ISR_TAMP2F 0x00004000U
Kojto 122:f9eeca106725 5695 #define RTC_ISR_TSOVF 0x00001000U
Kojto 122:f9eeca106725 5696 #define RTC_ISR_TSF 0x00000800U
Kojto 122:f9eeca106725 5697 #define RTC_ISR_WUTF 0x00000400U
Kojto 122:f9eeca106725 5698 #define RTC_ISR_ALRBF 0x00000200U
Kojto 122:f9eeca106725 5699 #define RTC_ISR_ALRAF 0x00000100U
Kojto 122:f9eeca106725 5700 #define RTC_ISR_INIT 0x00000080U
Kojto 122:f9eeca106725 5701 #define RTC_ISR_INITF 0x00000040U
Kojto 122:f9eeca106725 5702 #define RTC_ISR_RSF 0x00000020U
Kojto 122:f9eeca106725 5703 #define RTC_ISR_INITS 0x00000010U
Kojto 122:f9eeca106725 5704 #define RTC_ISR_SHPF 0x00000008U
Kojto 122:f9eeca106725 5705 #define RTC_ISR_WUTWF 0x00000004U
Kojto 122:f9eeca106725 5706 #define RTC_ISR_ALRBWF 0x00000002U
Kojto 122:f9eeca106725 5707 #define RTC_ISR_ALRAWF 0x00000001U
Kojto 112:6f327212ef96 5708
Kojto 112:6f327212ef96 5709 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 5710 #define RTC_PRER_PREDIV_A 0x007F0000U
Kojto 122:f9eeca106725 5711 #define RTC_PRER_PREDIV_S 0x00007FFFU
Kojto 112:6f327212ef96 5712
Kojto 112:6f327212ef96 5713 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 5714 #define RTC_WUTR_WUT 0x0000FFFFU
Kojto 112:6f327212ef96 5715
Kojto 112:6f327212ef96 5716 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 122:f9eeca106725 5717 #define RTC_CALIBR_DCS 0x00000080U
Kojto 122:f9eeca106725 5718 #define RTC_CALIBR_DC 0x0000001FU
Kojto 112:6f327212ef96 5719
Kojto 112:6f327212ef96 5720 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 5721 #define RTC_ALRMAR_MSK4 0x80000000U
Kojto 122:f9eeca106725 5722 #define RTC_ALRMAR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 5723 #define RTC_ALRMAR_DT 0x30000000U
Kojto 122:f9eeca106725 5724 #define RTC_ALRMAR_DT_0 0x10000000U
Kojto 122:f9eeca106725 5725 #define RTC_ALRMAR_DT_1 0x20000000U
Kojto 122:f9eeca106725 5726 #define RTC_ALRMAR_DU 0x0F000000U
Kojto 122:f9eeca106725 5727 #define RTC_ALRMAR_DU_0 0x01000000U
Kojto 122:f9eeca106725 5728 #define RTC_ALRMAR_DU_1 0x02000000U
Kojto 122:f9eeca106725 5729 #define RTC_ALRMAR_DU_2 0x04000000U
Kojto 122:f9eeca106725 5730 #define RTC_ALRMAR_DU_3 0x08000000U
Kojto 122:f9eeca106725 5731 #define RTC_ALRMAR_MSK3 0x00800000U
Kojto 122:f9eeca106725 5732 #define RTC_ALRMAR_PM 0x00400000U
Kojto 122:f9eeca106725 5733 #define RTC_ALRMAR_HT 0x00300000U
Kojto 122:f9eeca106725 5734 #define RTC_ALRMAR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5735 #define RTC_ALRMAR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5736 #define RTC_ALRMAR_HU 0x000F0000U
Kojto 122:f9eeca106725 5737 #define RTC_ALRMAR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5738 #define RTC_ALRMAR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5739 #define RTC_ALRMAR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5740 #define RTC_ALRMAR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5741 #define RTC_ALRMAR_MSK2 0x00008000U
Kojto 122:f9eeca106725 5742 #define RTC_ALRMAR_MNT 0x00007000U
Kojto 122:f9eeca106725 5743 #define RTC_ALRMAR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5744 #define RTC_ALRMAR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5745 #define RTC_ALRMAR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5746 #define RTC_ALRMAR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5747 #define RTC_ALRMAR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5748 #define RTC_ALRMAR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5749 #define RTC_ALRMAR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5750 #define RTC_ALRMAR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5751 #define RTC_ALRMAR_MSK1 0x00000080U
Kojto 122:f9eeca106725 5752 #define RTC_ALRMAR_ST 0x00000070U
Kojto 122:f9eeca106725 5753 #define RTC_ALRMAR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5754 #define RTC_ALRMAR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5755 #define RTC_ALRMAR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5756 #define RTC_ALRMAR_SU 0x0000000FU
Kojto 122:f9eeca106725 5757 #define RTC_ALRMAR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5758 #define RTC_ALRMAR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5759 #define RTC_ALRMAR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5760 #define RTC_ALRMAR_SU_3 0x00000008U
Kojto 112:6f327212ef96 5761
Kojto 112:6f327212ef96 5762 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 5763 #define RTC_ALRMBR_MSK4 0x80000000U
Kojto 122:f9eeca106725 5764 #define RTC_ALRMBR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 5765 #define RTC_ALRMBR_DT 0x30000000U
Kojto 122:f9eeca106725 5766 #define RTC_ALRMBR_DT_0 0x10000000U
Kojto 122:f9eeca106725 5767 #define RTC_ALRMBR_DT_1 0x20000000U
Kojto 122:f9eeca106725 5768 #define RTC_ALRMBR_DU 0x0F000000U
Kojto 122:f9eeca106725 5769 #define RTC_ALRMBR_DU_0 0x01000000U
Kojto 122:f9eeca106725 5770 #define RTC_ALRMBR_DU_1 0x02000000U
Kojto 122:f9eeca106725 5771 #define RTC_ALRMBR_DU_2 0x04000000U
Kojto 122:f9eeca106725 5772 #define RTC_ALRMBR_DU_3 0x08000000U
Kojto 122:f9eeca106725 5773 #define RTC_ALRMBR_MSK3 0x00800000U
Kojto 122:f9eeca106725 5774 #define RTC_ALRMBR_PM 0x00400000U
Kojto 122:f9eeca106725 5775 #define RTC_ALRMBR_HT 0x00300000U
Kojto 122:f9eeca106725 5776 #define RTC_ALRMBR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5777 #define RTC_ALRMBR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5778 #define RTC_ALRMBR_HU 0x000F0000U
Kojto 122:f9eeca106725 5779 #define RTC_ALRMBR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5780 #define RTC_ALRMBR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5781 #define RTC_ALRMBR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5782 #define RTC_ALRMBR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5783 #define RTC_ALRMBR_MSK2 0x00008000U
Kojto 122:f9eeca106725 5784 #define RTC_ALRMBR_MNT 0x00007000U
Kojto 122:f9eeca106725 5785 #define RTC_ALRMBR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5786 #define RTC_ALRMBR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5787 #define RTC_ALRMBR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5788 #define RTC_ALRMBR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5789 #define RTC_ALRMBR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5790 #define RTC_ALRMBR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5791 #define RTC_ALRMBR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5792 #define RTC_ALRMBR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5793 #define RTC_ALRMBR_MSK1 0x00000080U
Kojto 122:f9eeca106725 5794 #define RTC_ALRMBR_ST 0x00000070U
Kojto 122:f9eeca106725 5795 #define RTC_ALRMBR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5796 #define RTC_ALRMBR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5797 #define RTC_ALRMBR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5798 #define RTC_ALRMBR_SU 0x0000000FU
Kojto 122:f9eeca106725 5799 #define RTC_ALRMBR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5800 #define RTC_ALRMBR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5801 #define RTC_ALRMBR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5802 #define RTC_ALRMBR_SU_3 0x00000008U
Kojto 112:6f327212ef96 5803
Kojto 112:6f327212ef96 5804 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 5805 #define RTC_WPR_KEY 0x000000FFU
Kojto 112:6f327212ef96 5806
Kojto 112:6f327212ef96 5807 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 5808 #define RTC_SSR_SS 0x0000FFFFU
Kojto 112:6f327212ef96 5809
Kojto 112:6f327212ef96 5810 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 5811 #define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto 122:f9eeca106725 5812 #define RTC_SHIFTR_ADD1S 0x80000000U
Kojto 112:6f327212ef96 5813
Kojto 112:6f327212ef96 5814 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 5815 #define RTC_TSTR_PM 0x00400000U
Kojto 122:f9eeca106725 5816 #define RTC_TSTR_HT 0x00300000U
Kojto 122:f9eeca106725 5817 #define RTC_TSTR_HT_0 0x00100000U
Kojto 122:f9eeca106725 5818 #define RTC_TSTR_HT_1 0x00200000U
Kojto 122:f9eeca106725 5819 #define RTC_TSTR_HU 0x000F0000U
Kojto 122:f9eeca106725 5820 #define RTC_TSTR_HU_0 0x00010000U
Kojto 122:f9eeca106725 5821 #define RTC_TSTR_HU_1 0x00020000U
Kojto 122:f9eeca106725 5822 #define RTC_TSTR_HU_2 0x00040000U
Kojto 122:f9eeca106725 5823 #define RTC_TSTR_HU_3 0x00080000U
Kojto 122:f9eeca106725 5824 #define RTC_TSTR_MNT 0x00007000U
Kojto 122:f9eeca106725 5825 #define RTC_TSTR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 5826 #define RTC_TSTR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 5827 #define RTC_TSTR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 5828 #define RTC_TSTR_MNU 0x00000F00U
Kojto 122:f9eeca106725 5829 #define RTC_TSTR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 5830 #define RTC_TSTR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 5831 #define RTC_TSTR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 5832 #define RTC_TSTR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 5833 #define RTC_TSTR_ST 0x00000070U
Kojto 122:f9eeca106725 5834 #define RTC_TSTR_ST_0 0x00000010U
Kojto 122:f9eeca106725 5835 #define RTC_TSTR_ST_1 0x00000020U
Kojto 122:f9eeca106725 5836 #define RTC_TSTR_ST_2 0x00000040U
Kojto 122:f9eeca106725 5837 #define RTC_TSTR_SU 0x0000000FU
Kojto 122:f9eeca106725 5838 #define RTC_TSTR_SU_0 0x00000001U
Kojto 122:f9eeca106725 5839 #define RTC_TSTR_SU_1 0x00000002U
Kojto 122:f9eeca106725 5840 #define RTC_TSTR_SU_2 0x00000004U
Kojto 122:f9eeca106725 5841 #define RTC_TSTR_SU_3 0x00000008U
Kojto 112:6f327212ef96 5842
Kojto 112:6f327212ef96 5843 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 5844 #define RTC_TSDR_WDU 0x0000E000U
Kojto 122:f9eeca106725 5845 #define RTC_TSDR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 5846 #define RTC_TSDR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 5847 #define RTC_TSDR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 5848 #define RTC_TSDR_MT 0x00001000U
Kojto 122:f9eeca106725 5849 #define RTC_TSDR_MU 0x00000F00U
Kojto 122:f9eeca106725 5850 #define RTC_TSDR_MU_0 0x00000100U
Kojto 122:f9eeca106725 5851 #define RTC_TSDR_MU_1 0x00000200U
Kojto 122:f9eeca106725 5852 #define RTC_TSDR_MU_2 0x00000400U
Kojto 122:f9eeca106725 5853 #define RTC_TSDR_MU_3 0x00000800U
Kojto 122:f9eeca106725 5854 #define RTC_TSDR_DT 0x00000030U
Kojto 122:f9eeca106725 5855 #define RTC_TSDR_DT_0 0x00000010U
Kojto 122:f9eeca106725 5856 #define RTC_TSDR_DT_1 0x00000020U
Kojto 122:f9eeca106725 5857 #define RTC_TSDR_DU 0x0000000FU
Kojto 122:f9eeca106725 5858 #define RTC_TSDR_DU_0 0x00000001U
Kojto 122:f9eeca106725 5859 #define RTC_TSDR_DU_1 0x00000002U
Kojto 122:f9eeca106725 5860 #define RTC_TSDR_DU_2 0x00000004U
Kojto 122:f9eeca106725 5861 #define RTC_TSDR_DU_3 0x00000008U
Kojto 112:6f327212ef96 5862
Kojto 112:6f327212ef96 5863 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 5864 #define RTC_TSSSR_SS 0x0000FFFFU
Kojto 112:6f327212ef96 5865
Kojto 112:6f327212ef96 5866 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 5867 #define RTC_CALR_CALP 0x00008000U
Kojto 122:f9eeca106725 5868 #define RTC_CALR_CALW8 0x00004000U
Kojto 122:f9eeca106725 5869 #define RTC_CALR_CALW16 0x00002000U
Kojto 122:f9eeca106725 5870 #define RTC_CALR_CALM 0x000001FFU
Kojto 122:f9eeca106725 5871 #define RTC_CALR_CALM_0 0x00000001U
Kojto 122:f9eeca106725 5872 #define RTC_CALR_CALM_1 0x00000002U
Kojto 122:f9eeca106725 5873 #define RTC_CALR_CALM_2 0x00000004U
Kojto 122:f9eeca106725 5874 #define RTC_CALR_CALM_3 0x00000008U
Kojto 122:f9eeca106725 5875 #define RTC_CALR_CALM_4 0x00000010U
Kojto 122:f9eeca106725 5876 #define RTC_CALR_CALM_5 0x00000020U
Kojto 122:f9eeca106725 5877 #define RTC_CALR_CALM_6 0x00000040U
Kojto 122:f9eeca106725 5878 #define RTC_CALR_CALM_7 0x00000080U
Kojto 122:f9eeca106725 5879 #define RTC_CALR_CALM_8 0x00000100U
Kojto 112:6f327212ef96 5880
Kojto 112:6f327212ef96 5881 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 122:f9eeca106725 5882 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
Kojto 122:f9eeca106725 5883 #define RTC_TAFCR_TSINSEL 0x00020000U
Kojto 122:f9eeca106725 5884 #define RTC_TAFCR_TAMPINSEL 0x00010000U
Kojto 122:f9eeca106725 5885 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
Kojto 122:f9eeca106725 5886 #define RTC_TAFCR_TAMPPRCH 0x00006000U
Kojto 122:f9eeca106725 5887 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
Kojto 122:f9eeca106725 5888 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
Kojto 122:f9eeca106725 5889 #define RTC_TAFCR_TAMPFLT 0x00001800U
Kojto 122:f9eeca106725 5890 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
Kojto 122:f9eeca106725 5891 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
Kojto 122:f9eeca106725 5892 #define RTC_TAFCR_TAMPFREQ 0x00000700U
Kojto 122:f9eeca106725 5893 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
Kojto 122:f9eeca106725 5894 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
Kojto 122:f9eeca106725 5895 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
Kojto 122:f9eeca106725 5896 #define RTC_TAFCR_TAMPTS 0x00000080U
Kojto 122:f9eeca106725 5897 #define RTC_TAFCR_TAMP2TRG 0x00000010U
Kojto 122:f9eeca106725 5898 #define RTC_TAFCR_TAMP2E 0x00000008U
Kojto 122:f9eeca106725 5899 #define RTC_TAFCR_TAMPIE 0x00000004U
Kojto 122:f9eeca106725 5900 #define RTC_TAFCR_TAMP1TRG 0x00000002U
Kojto 122:f9eeca106725 5901 #define RTC_TAFCR_TAMP1E 0x00000001U
Kojto 112:6f327212ef96 5902
Kojto 112:6f327212ef96 5903 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 5904 #define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 5905 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 5906 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 5907 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 5908 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 5909 #define RTC_ALRMASSR_SS 0x00007FFFU
Kojto 112:6f327212ef96 5910
Kojto 112:6f327212ef96 5911 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 5912 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 5913 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 5914 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 5915 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 5916 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 5917 #define RTC_ALRMBSSR_SS 0x00007FFFU
Kojto 112:6f327212ef96 5918
Kojto 112:6f327212ef96 5919 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 5920 #define RTC_BKP0R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5921
Kojto 112:6f327212ef96 5922 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 5923 #define RTC_BKP1R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5924
Kojto 112:6f327212ef96 5925 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 5926 #define RTC_BKP2R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5927
Kojto 112:6f327212ef96 5928 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 5929 #define RTC_BKP3R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5930
Kojto 112:6f327212ef96 5931 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 5932 #define RTC_BKP4R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5933
Kojto 112:6f327212ef96 5934 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 5935 #define RTC_BKP5R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5936
Kojto 112:6f327212ef96 5937 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 5938 #define RTC_BKP6R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5939
Kojto 112:6f327212ef96 5940 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 5941 #define RTC_BKP7R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5942
Kojto 112:6f327212ef96 5943 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 5944 #define RTC_BKP8R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5945
Kojto 112:6f327212ef96 5946 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 5947 #define RTC_BKP9R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5948
Kojto 112:6f327212ef96 5949 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 5950 #define RTC_BKP10R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5951
Kojto 112:6f327212ef96 5952 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 5953 #define RTC_BKP11R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5954
Kojto 112:6f327212ef96 5955 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 5956 #define RTC_BKP12R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5957
Kojto 112:6f327212ef96 5958 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 5959 #define RTC_BKP13R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5960
Kojto 112:6f327212ef96 5961 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 5962 #define RTC_BKP14R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5963
Kojto 112:6f327212ef96 5964 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 5965 #define RTC_BKP15R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5966
Kojto 112:6f327212ef96 5967 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 5968 #define RTC_BKP16R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5969
Kojto 112:6f327212ef96 5970 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 5971 #define RTC_BKP17R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5972
Kojto 112:6f327212ef96 5973 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 5974 #define RTC_BKP18R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5975
Kojto 112:6f327212ef96 5976 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 5977 #define RTC_BKP19R 0xFFFFFFFFU
Kojto 112:6f327212ef96 5978
Kojto 112:6f327212ef96 5979 /******************************************************************************/
Kojto 112:6f327212ef96 5980 /* */
Kojto 112:6f327212ef96 5981 /* Serial Audio Interface */
Kojto 112:6f327212ef96 5982 /* */
Kojto 112:6f327212ef96 5983 /******************************************************************************/
Kojto 112:6f327212ef96 5984 /******************** Bit definition for SAI_GCR register *******************/
Kojto 122:f9eeca106725 5985 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 122:f9eeca106725 5986 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 5987 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 5988
Kojto 122:f9eeca106725 5989 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 122:f9eeca106725 5990 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 5991 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
Kojto 112:6f327212ef96 5992
Kojto 112:6f327212ef96 5993 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 122:f9eeca106725 5994 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 122:f9eeca106725 5995 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 5996 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 5997
Kojto 122:f9eeca106725 5998 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 122:f9eeca106725 5999 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6000 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6001
Kojto 122:f9eeca106725 6002 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
Kojto 122:f9eeca106725 6003 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 6004 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 6005 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 6006
Kojto 122:f9eeca106725 6007 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
Kojto 122:f9eeca106725 6008 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
Kojto 122:f9eeca106725 6009
Kojto 122:f9eeca106725 6010 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 122:f9eeca106725 6011 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6012 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6013
Kojto 122:f9eeca106725 6014 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
Kojto 122:f9eeca106725 6015 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
Kojto 122:f9eeca106725 6016 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
Kojto 122:f9eeca106725 6017 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
Kojto 122:f9eeca106725 6018 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
Kojto 122:f9eeca106725 6019
Kojto 122:f9eeca106725 6020 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 122:f9eeca106725 6021 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6022 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6023 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6024 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 112:6f327212ef96 6025
Kojto 112:6f327212ef96 6026 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 122:f9eeca106725 6027 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
Kojto 122:f9eeca106725 6028 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6029 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6030 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6031
Kojto 122:f9eeca106725 6032 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
Kojto 122:f9eeca106725 6033 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
Kojto 122:f9eeca106725 6034 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
Kojto 122:f9eeca106725 6035 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
Kojto 122:f9eeca106725 6036
Kojto 122:f9eeca106725 6037 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 122:f9eeca106725 6038 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 6039 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 6040 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 6041 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 6042 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 6043 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6044
Kojto 122:f9eeca106725 6045 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
Kojto 122:f9eeca106725 6046
Kojto 122:f9eeca106725 6047 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
Kojto 122:f9eeca106725 6048 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6049 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
Kojto 112:6f327212ef96 6050
Kojto 112:6f327212ef96 6051 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 122:f9eeca106725 6052 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
Kojto 122:f9eeca106725 6053 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6054 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6055 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6056 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6057 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6058 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6059 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6060 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 6061
Kojto 122:f9eeca106725 6062 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
Kojto 122:f9eeca106725 6063 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6064 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6065 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6066 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6067 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6068 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6069 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6070
Kojto 122:f9eeca106725 6071 #define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
Kojto 122:f9eeca106725 6072 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
Kojto 122:f9eeca106725 6073 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
Kojto 122:f9eeca106725 6074 /* Legacy defines */
Kojto 122:f9eeca106725 6075 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
Kojto 112:6f327212ef96 6076
Kojto 112:6f327212ef96 6077 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 122:f9eeca106725 6078 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
Kojto 122:f9eeca106725 6079 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6080 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6081 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6082 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6083 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6084
Kojto 122:f9eeca106725 6085 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
Kojto 122:f9eeca106725 6086 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 6087 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 6088
Kojto 122:f9eeca106725 6089 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 122:f9eeca106725 6090 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6091 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6092 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6093 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6094
Kojto 122:f9eeca106725 6095 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 112:6f327212ef96 6096
Kojto 112:6f327212ef96 6097 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 122:f9eeca106725 6098 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
Kojto 122:f9eeca106725 6099 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
Kojto 122:f9eeca106725 6100 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
Kojto 122:f9eeca106725 6101 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
Kojto 122:f9eeca106725 6102 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
Kojto 122:f9eeca106725 6103 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 122:f9eeca106725 6104 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
Kojto 112:6f327212ef96 6105
Kojto 112:6f327212ef96 6106 /******************** Bit definition for SAI_xSR register *******************/
Kojto 122:f9eeca106725 6107 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
Kojto 122:f9eeca106725 6108 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
Kojto 122:f9eeca106725 6109 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
Kojto 122:f9eeca106725 6110 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
Kojto 122:f9eeca106725 6111 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
Kojto 122:f9eeca106725 6112 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 6113 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
Kojto 122:f9eeca106725 6114
Kojto 122:f9eeca106725 6115 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 122:f9eeca106725 6116 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6117 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6118 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
Kojto 112:6f327212ef96 6119
Kojto 112:6f327212ef96 6120 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 122:f9eeca106725 6121 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
Kojto 122:f9eeca106725 6122 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
Kojto 122:f9eeca106725 6123 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
Kojto 122:f9eeca106725 6124 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
Kojto 122:f9eeca106725 6125 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
Kojto 122:f9eeca106725 6126 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 6127 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
Kojto 112:6f327212ef96 6128
Kojto 112:6f327212ef96 6129 /****************** Bit definition for SAI_xDR register ******************/
Kojto 122:f9eeca106725 6130 #define SAI_xDR_DATA 0xFFFFFFFFU
Kojto 112:6f327212ef96 6131
Kojto 112:6f327212ef96 6132 /******************************************************************************/
Kojto 112:6f327212ef96 6133 /* */
Kojto 112:6f327212ef96 6134 /* SPDIF-RX Interface */
Kojto 112:6f327212ef96 6135 /* */
Kojto 112:6f327212ef96 6136 /******************************************************************************/
Kojto 112:6f327212ef96 6137 /******************** Bit definition for SPDIFRX_CR register *******************/
Kojto 122:f9eeca106725 6138 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
Kojto 122:f9eeca106725 6139 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
Kojto 122:f9eeca106725 6140 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
Kojto 122:f9eeca106725 6141 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
Kojto 122:f9eeca106725 6142 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
Kojto 122:f9eeca106725 6143 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
Kojto 122:f9eeca106725 6144 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
Kojto 122:f9eeca106725 6145 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
Kojto 122:f9eeca106725 6146 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
Kojto 122:f9eeca106725 6147 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
Kojto 122:f9eeca106725 6148 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
Kojto 122:f9eeca106725 6149 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
Kojto 122:f9eeca106725 6150 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIFRX input selection */
Kojto 112:6f327212ef96 6151
Kojto 112:6f327212ef96 6152 /******************* Bit definition for SPDIFRX_IMR register *******************/
Kojto 122:f9eeca106725 6153 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
Kojto 122:f9eeca106725 6154 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
Kojto 122:f9eeca106725 6155 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
Kojto 122:f9eeca106725 6156 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
Kojto 122:f9eeca106725 6157 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
Kojto 122:f9eeca106725 6158 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
Kojto 122:f9eeca106725 6159 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
Kojto 112:6f327212ef96 6160
Kojto 112:6f327212ef96 6161 /******************* Bit definition for SPDIFRX_SR register *******************/
Kojto 122:f9eeca106725 6162 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
Kojto 122:f9eeca106725 6163 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
Kojto 122:f9eeca106725 6164 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
Kojto 122:f9eeca106725 6165 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
Kojto 122:f9eeca106725 6166 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
Kojto 122:f9eeca106725 6167 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
Kojto 122:f9eeca106725 6168 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
Kojto 122:f9eeca106725 6169 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
Kojto 122:f9eeca106725 6170 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
Kojto 122:f9eeca106725 6171 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with SPDIFRX_clk */
Kojto 112:6f327212ef96 6172
Kojto 112:6f327212ef96 6173 /******************* Bit definition for SPDIFRX_IFCR register *******************/
Kojto 122:f9eeca106725 6174 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
Kojto 122:f9eeca106725 6175 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
Kojto 122:f9eeca106725 6176 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
Kojto 122:f9eeca106725 6177 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
Kojto 112:6f327212ef96 6178
Kojto 112:6f327212ef96 6179 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
Kojto 122:f9eeca106725 6180 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
Kojto 122:f9eeca106725 6181 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
Kojto 122:f9eeca106725 6182 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
Kojto 122:f9eeca106725 6183 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
Kojto 122:f9eeca106725 6184 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
Kojto 122:f9eeca106725 6185 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
Kojto 112:6f327212ef96 6186
Kojto 112:6f327212ef96 6187 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
Kojto 122:f9eeca106725 6188 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
Kojto 122:f9eeca106725 6189 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
Kojto 122:f9eeca106725 6190 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
Kojto 122:f9eeca106725 6191 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
Kojto 122:f9eeca106725 6192 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
Kojto 122:f9eeca106725 6193 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
Kojto 112:6f327212ef96 6194
Kojto 112:6f327212ef96 6195 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
Kojto 122:f9eeca106725 6196 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
Kojto 122:f9eeca106725 6197 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
Kojto 112:6f327212ef96 6198
Kojto 112:6f327212ef96 6199 /******************* Bit definition for SPDIFRX_CSR register *******************/
Kojto 122:f9eeca106725 6200 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
Kojto 122:f9eeca106725 6201 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
Kojto 122:f9eeca106725 6202 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
Kojto 112:6f327212ef96 6203
Kojto 112:6f327212ef96 6204 /******************* Bit definition for SPDIFRX_DIR register *******************/
Kojto 122:f9eeca106725 6205 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
Kojto 122:f9eeca106725 6206 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
Kojto 112:6f327212ef96 6207
Kojto 112:6f327212ef96 6208
Kojto 112:6f327212ef96 6209 /******************************************************************************/
Kojto 112:6f327212ef96 6210 /* */
Kojto 112:6f327212ef96 6211 /* SD host Interface */
Kojto 112:6f327212ef96 6212 /* */
Kojto 112:6f327212ef96 6213 /******************************************************************************/
Kojto 112:6f327212ef96 6214 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 122:f9eeca106725 6215 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 122:f9eeca106725 6216 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 6217 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
Kojto 112:6f327212ef96 6218
Kojto 112:6f327212ef96 6219 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 122:f9eeca106725 6220 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
Kojto 122:f9eeca106725 6221 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
Kojto 122:f9eeca106725 6222 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
Kojto 122:f9eeca106725 6223 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
Kojto 122:f9eeca106725 6224
Kojto 122:f9eeca106725 6225 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 122:f9eeca106725 6226 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
Kojto 122:f9eeca106725 6227 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6228
Kojto 122:f9eeca106725 6229 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
Kojto 122:f9eeca106725 6230 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
Kojto 112:6f327212ef96 6231
Kojto 112:6f327212ef96 6232 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 122:f9eeca106725 6233 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
Kojto 112:6f327212ef96 6234
Kojto 112:6f327212ef96 6235 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 122:f9eeca106725 6236 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
Kojto 122:f9eeca106725 6237
Kojto 122:f9eeca106725 6238 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 122:f9eeca106725 6239 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
Kojto 122:f9eeca106725 6240 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
Kojto 122:f9eeca106725 6241
Kojto 122:f9eeca106725 6242 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
Kojto 122:f9eeca106725 6243 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 122:f9eeca106725 6244 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
Kojto 122:f9eeca106725 6245 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
Kojto 112:6f327212ef96 6246
Kojto 112:6f327212ef96 6247 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 122:f9eeca106725 6248 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
Kojto 112:6f327212ef96 6249
Kojto 112:6f327212ef96 6250 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 122:f9eeca106725 6251 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
Kojto 112:6f327212ef96 6252
Kojto 112:6f327212ef96 6253 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 122:f9eeca106725 6254 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
Kojto 112:6f327212ef96 6255
Kojto 112:6f327212ef96 6256 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 122:f9eeca106725 6257 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
Kojto 112:6f327212ef96 6258
Kojto 112:6f327212ef96 6259 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 122:f9eeca106725 6260 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
Kojto 112:6f327212ef96 6261
Kojto 112:6f327212ef96 6262 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 122:f9eeca106725 6263 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
Kojto 112:6f327212ef96 6264
Kojto 112:6f327212ef96 6265 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 122:f9eeca106725 6266 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
Kojto 112:6f327212ef96 6267
Kojto 112:6f327212ef96 6268 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 122:f9eeca106725 6269 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
Kojto 112:6f327212ef96 6270
Kojto 112:6f327212ef96 6271 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 122:f9eeca106725 6272 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
Kojto 122:f9eeca106725 6273 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
Kojto 122:f9eeca106725 6274 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
Kojto 122:f9eeca106725 6275 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
Kojto 122:f9eeca106725 6276
Kojto 122:f9eeca106725 6277 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 122:f9eeca106725 6278 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6279 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6280 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6281 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6282
Kojto 122:f9eeca106725 6283 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
Kojto 122:f9eeca106725 6284 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
Kojto 122:f9eeca106725 6285 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
Kojto 122:f9eeca106725 6286 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
Kojto 112:6f327212ef96 6287
Kojto 112:6f327212ef96 6288 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 122:f9eeca106725 6289 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
Kojto 112:6f327212ef96 6290
Kojto 112:6f327212ef96 6291 /****************** Bit definition for SDIO_STA register ********************/
Kojto 122:f9eeca106725 6292 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
Kojto 122:f9eeca106725 6293 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
Kojto 122:f9eeca106725 6294 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
Kojto 122:f9eeca106725 6295 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
Kojto 122:f9eeca106725 6296 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
Kojto 122:f9eeca106725 6297 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
Kojto 122:f9eeca106725 6298 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
Kojto 122:f9eeca106725 6299 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
Kojto 122:f9eeca106725 6300 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 122:f9eeca106725 6301 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
Kojto 122:f9eeca106725 6302 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
Kojto 122:f9eeca106725 6303 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
Kojto 122:f9eeca106725 6304 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
Kojto 122:f9eeca106725 6305 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 122:f9eeca106725 6306 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 122:f9eeca106725 6307 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
Kojto 122:f9eeca106725 6308 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
Kojto 122:f9eeca106725 6309 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
Kojto 122:f9eeca106725 6310 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
Kojto 122:f9eeca106725 6311 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
Kojto 122:f9eeca106725 6312 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
Kojto 122:f9eeca106725 6313 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
Kojto 112:6f327212ef96 6314
Kojto 112:6f327212ef96 6315 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 122:f9eeca106725 6316 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 6317 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 6318 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 6319 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 6320 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
Kojto 122:f9eeca106725 6321 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
Kojto 122:f9eeca106725 6322 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
Kojto 122:f9eeca106725 6323 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
Kojto 122:f9eeca106725 6324 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
Kojto 122:f9eeca106725 6325 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
Kojto 122:f9eeca106725 6326 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
Kojto 112:6f327212ef96 6327
Kojto 112:6f327212ef96 6328 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 122:f9eeca106725 6329 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 6330 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 6331 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 6332 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 6333 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 122:f9eeca106725 6334 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 122:f9eeca106725 6335 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
Kojto 122:f9eeca106725 6336 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
Kojto 122:f9eeca106725 6337 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
Kojto 122:f9eeca106725 6338 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
Kojto 122:f9eeca106725 6339 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
Kojto 122:f9eeca106725 6340 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
Kojto 122:f9eeca106725 6341 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
Kojto 122:f9eeca106725 6342 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 122:f9eeca106725 6343 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
Kojto 122:f9eeca106725 6344 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 6345 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 6346 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 6347 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 6348 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
Kojto 122:f9eeca106725 6349 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
Kojto 122:f9eeca106725 6350 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 112:6f327212ef96 6351
Kojto 112:6f327212ef96 6352 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 122:f9eeca106725 6353 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 112:6f327212ef96 6354
Kojto 112:6f327212ef96 6355 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 122:f9eeca106725 6356 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
Kojto 112:6f327212ef96 6357
Kojto 112:6f327212ef96 6358 /******************************************************************************/
Kojto 112:6f327212ef96 6359 /* */
Kojto 112:6f327212ef96 6360 /* Serial Peripheral Interface */
Kojto 112:6f327212ef96 6361 /* */
Kojto 112:6f327212ef96 6362 /******************************************************************************/
Kojto 112:6f327212ef96 6363 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 6364 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
Kojto 122:f9eeca106725 6365 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
Kojto 122:f9eeca106725 6366 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
Kojto 122:f9eeca106725 6367
Kojto 122:f9eeca106725 6368 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 6369 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 6370 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 6371 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 6372
Kojto 122:f9eeca106725 6373 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
Kojto 122:f9eeca106725 6374 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
Kojto 122:f9eeca106725 6375 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
Kojto 122:f9eeca106725 6376 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
Kojto 122:f9eeca106725 6377 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
Kojto 122:f9eeca106725 6378 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
Kojto 122:f9eeca106725 6379 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
Kojto 122:f9eeca106725 6380 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
Kojto 122:f9eeca106725 6381 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
Kojto 122:f9eeca106725 6382 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
Kojto 112:6f327212ef96 6383
Kojto 112:6f327212ef96 6384 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 6385 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 6386 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 6387 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
Kojto 122:f9eeca106725 6388 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
Kojto 122:f9eeca106725 6389 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 6390 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 6391 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
Kojto 112:6f327212ef96 6392
Kojto 112:6f327212ef96 6393 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 6394 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
Kojto 122:f9eeca106725 6395 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
Kojto 122:f9eeca106725 6396 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
Kojto 122:f9eeca106725 6397 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
Kojto 122:f9eeca106725 6398 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
Kojto 122:f9eeca106725 6399 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
Kojto 122:f9eeca106725 6400 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
Kojto 122:f9eeca106725 6401 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
Kojto 122:f9eeca106725 6402 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
Kojto 112:6f327212ef96 6403
Kojto 112:6f327212ef96 6404 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 6405 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
Kojto 112:6f327212ef96 6406
Kojto 112:6f327212ef96 6407 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 6408 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
Kojto 112:6f327212ef96 6409
Kojto 112:6f327212ef96 6410 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 6411 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
Kojto 112:6f327212ef96 6412
Kojto 112:6f327212ef96 6413 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 6414 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
Kojto 112:6f327212ef96 6415
Kojto 112:6f327212ef96 6416 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 122:f9eeca106725 6417 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 6418
Kojto 122:f9eeca106725 6419 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 6420 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 6421 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 6422
Kojto 122:f9eeca106725 6423 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
Kojto 122:f9eeca106725 6424
Kojto 122:f9eeca106725 6425 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 6426 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6427 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6428
Kojto 122:f9eeca106725 6429 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 6430
Kojto 122:f9eeca106725 6431 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 6432 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6433 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6434
Kojto 122:f9eeca106725 6435 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
Kojto 122:f9eeca106725 6436 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
Kojto 122:f9eeca106725 6437 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
Kojto 112:6f327212ef96 6438
Kojto 112:6f327212ef96 6439 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 122:f9eeca106725 6440 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 6441 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 6442 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
Kojto 112:6f327212ef96 6443
Kojto 112:6f327212ef96 6444 /******************************************************************************/
Kojto 112:6f327212ef96 6445 /* */
Kojto 112:6f327212ef96 6446 /* SYSCFG */
Kojto 112:6f327212ef96 6447 /* */
Kojto 112:6f327212ef96 6448 /******************************************************************************/
Kojto 112:6f327212ef96 6449 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 122:f9eeca106725 6450 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 6451 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
Kojto 122:f9eeca106725 6452 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
Kojto 122:f9eeca106725 6453 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
Kojto 122:f9eeca106725 6454
Kojto 122:f9eeca106725 6455 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
Kojto 122:f9eeca106725 6456 #define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
Kojto 112:6f327212ef96 6457
Kojto 112:6f327212ef96 6458 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 122:f9eeca106725 6459 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 6460 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 6461 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 6462 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 6463
Kojto 112:6f327212ef96 6464 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 6465 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
Kojto 122:f9eeca106725 6466 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
Kojto 122:f9eeca106725 6467 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
Kojto 122:f9eeca106725 6468 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
Kojto 112:6f327212ef96 6469 /**
Kojto 112:6f327212ef96 6470 * @brief EXTI0 configuration
Kojto 112:6f327212ef96 6471 */
Kojto 122:f9eeca106725 6472 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
Kojto 122:f9eeca106725 6473 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
Kojto 122:f9eeca106725 6474 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
Kojto 122:f9eeca106725 6475 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
Kojto 122:f9eeca106725 6476 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
Kojto 122:f9eeca106725 6477 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
Kojto 122:f9eeca106725 6478 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
Kojto 122:f9eeca106725 6479 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
Kojto 122:f9eeca106725 6480 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
Kojto 122:f9eeca106725 6481 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
Kojto 122:f9eeca106725 6482 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
Kojto 112:6f327212ef96 6483
Kojto 112:6f327212ef96 6484 /**
Kojto 112:6f327212ef96 6485 * @brief EXTI1 configuration
Kojto 112:6f327212ef96 6486 */
Kojto 122:f9eeca106725 6487 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
Kojto 122:f9eeca106725 6488 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
Kojto 122:f9eeca106725 6489 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
Kojto 122:f9eeca106725 6490 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
Kojto 122:f9eeca106725 6491 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
Kojto 122:f9eeca106725 6492 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
Kojto 122:f9eeca106725 6493 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
Kojto 122:f9eeca106725 6494 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
Kojto 122:f9eeca106725 6495 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
Kojto 122:f9eeca106725 6496 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
Kojto 122:f9eeca106725 6497 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
Kojto 112:6f327212ef96 6498
Kojto 112:6f327212ef96 6499
Kojto 112:6f327212ef96 6500 /**
Kojto 112:6f327212ef96 6501 * @brief EXTI2 configuration
Kojto 112:6f327212ef96 6502 */
Kojto 122:f9eeca106725 6503 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
Kojto 122:f9eeca106725 6504 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
Kojto 122:f9eeca106725 6505 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
Kojto 122:f9eeca106725 6506 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
Kojto 122:f9eeca106725 6507 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
Kojto 122:f9eeca106725 6508 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
Kojto 122:f9eeca106725 6509 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
Kojto 122:f9eeca106725 6510 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
Kojto 122:f9eeca106725 6511 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
Kojto 122:f9eeca106725 6512 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
Kojto 122:f9eeca106725 6513 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
Kojto 112:6f327212ef96 6514
Kojto 112:6f327212ef96 6515
Kojto 112:6f327212ef96 6516 /**
Kojto 112:6f327212ef96 6517 * @brief EXTI3 configuration
Kojto 112:6f327212ef96 6518 */
Kojto 122:f9eeca106725 6519 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
Kojto 122:f9eeca106725 6520 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
Kojto 122:f9eeca106725 6521 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
Kojto 122:f9eeca106725 6522 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
Kojto 122:f9eeca106725 6523 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
Kojto 122:f9eeca106725 6524 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
Kojto 122:f9eeca106725 6525 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
Kojto 122:f9eeca106725 6526 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
Kojto 122:f9eeca106725 6527 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
Kojto 122:f9eeca106725 6528 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
Kojto 122:f9eeca106725 6529 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
Kojto 112:6f327212ef96 6530
Kojto 112:6f327212ef96 6531
Kojto 112:6f327212ef96 6532 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 6533 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
Kojto 122:f9eeca106725 6534 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
Kojto 122:f9eeca106725 6535 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
Kojto 122:f9eeca106725 6536 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
Kojto 112:6f327212ef96 6537 /**
Kojto 112:6f327212ef96 6538 * @brief EXTI4 configuration
Kojto 112:6f327212ef96 6539 */
Kojto 122:f9eeca106725 6540 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
Kojto 122:f9eeca106725 6541 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
Kojto 122:f9eeca106725 6542 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
Kojto 122:f9eeca106725 6543 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
Kojto 122:f9eeca106725 6544 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
Kojto 122:f9eeca106725 6545 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
Kojto 122:f9eeca106725 6546 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
Kojto 122:f9eeca106725 6547 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
Kojto 122:f9eeca106725 6548 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
Kojto 122:f9eeca106725 6549 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
Kojto 122:f9eeca106725 6550 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
Kojto 112:6f327212ef96 6551
Kojto 112:6f327212ef96 6552 /**
Kojto 112:6f327212ef96 6553 * @brief EXTI5 configuration
Kojto 112:6f327212ef96 6554 */
Kojto 122:f9eeca106725 6555 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
Kojto 122:f9eeca106725 6556 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
Kojto 122:f9eeca106725 6557 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
Kojto 122:f9eeca106725 6558 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
Kojto 122:f9eeca106725 6559 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
Kojto 122:f9eeca106725 6560 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
Kojto 122:f9eeca106725 6561 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
Kojto 122:f9eeca106725 6562 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
Kojto 122:f9eeca106725 6563 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
Kojto 122:f9eeca106725 6564 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
Kojto 122:f9eeca106725 6565 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
Kojto 112:6f327212ef96 6566
Kojto 112:6f327212ef96 6567 /**
Kojto 112:6f327212ef96 6568 * @brief EXTI6 configuration
Kojto 112:6f327212ef96 6569 */
Kojto 122:f9eeca106725 6570 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
Kojto 122:f9eeca106725 6571 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
Kojto 122:f9eeca106725 6572 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
Kojto 122:f9eeca106725 6573 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
Kojto 122:f9eeca106725 6574 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
Kojto 122:f9eeca106725 6575 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
Kojto 122:f9eeca106725 6576 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
Kojto 122:f9eeca106725 6577 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
Kojto 122:f9eeca106725 6578 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
Kojto 122:f9eeca106725 6579 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
Kojto 122:f9eeca106725 6580 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
Kojto 112:6f327212ef96 6581
Kojto 112:6f327212ef96 6582
Kojto 112:6f327212ef96 6583 /**
Kojto 112:6f327212ef96 6584 * @brief EXTI7 configuration
Kojto 112:6f327212ef96 6585 */
Kojto 122:f9eeca106725 6586 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
Kojto 122:f9eeca106725 6587 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
Kojto 122:f9eeca106725 6588 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
Kojto 122:f9eeca106725 6589 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
Kojto 122:f9eeca106725 6590 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
Kojto 122:f9eeca106725 6591 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
Kojto 122:f9eeca106725 6592 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
Kojto 122:f9eeca106725 6593 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
Kojto 122:f9eeca106725 6594 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
Kojto 122:f9eeca106725 6595 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
Kojto 122:f9eeca106725 6596 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
Kojto 112:6f327212ef96 6597
Kojto 112:6f327212ef96 6598 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 6599 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
Kojto 122:f9eeca106725 6600 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
Kojto 122:f9eeca106725 6601 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
Kojto 122:f9eeca106725 6602 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
Kojto 112:6f327212ef96 6603
Kojto 112:6f327212ef96 6604 /**
Kojto 112:6f327212ef96 6605 * @brief EXTI8 configuration
Kojto 112:6f327212ef96 6606 */
Kojto 122:f9eeca106725 6607 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
Kojto 122:f9eeca106725 6608 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
Kojto 122:f9eeca106725 6609 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
Kojto 122:f9eeca106725 6610 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
Kojto 122:f9eeca106725 6611 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
Kojto 122:f9eeca106725 6612 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
Kojto 122:f9eeca106725 6613 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
Kojto 122:f9eeca106725 6614 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
Kojto 122:f9eeca106725 6615 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
Kojto 122:f9eeca106725 6616 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
Kojto 112:6f327212ef96 6617
Kojto 112:6f327212ef96 6618 /**
Kojto 112:6f327212ef96 6619 * @brief EXTI9 configuration
Kojto 112:6f327212ef96 6620 */
Kojto 122:f9eeca106725 6621 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
Kojto 122:f9eeca106725 6622 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
Kojto 122:f9eeca106725 6623 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
Kojto 122:f9eeca106725 6624 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
Kojto 122:f9eeca106725 6625 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
Kojto 122:f9eeca106725 6626 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
Kojto 122:f9eeca106725 6627 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
Kojto 122:f9eeca106725 6628 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
Kojto 122:f9eeca106725 6629 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
Kojto 122:f9eeca106725 6630 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
Kojto 112:6f327212ef96 6631
Kojto 112:6f327212ef96 6632
Kojto 112:6f327212ef96 6633 /**
Kojto 112:6f327212ef96 6634 * @brief EXTI10 configuration
Kojto 112:6f327212ef96 6635 */
Kojto 122:f9eeca106725 6636 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
Kojto 122:f9eeca106725 6637 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
Kojto 122:f9eeca106725 6638 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
Kojto 122:f9eeca106725 6639 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
Kojto 122:f9eeca106725 6640 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
Kojto 122:f9eeca106725 6641 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
Kojto 122:f9eeca106725 6642 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
Kojto 122:f9eeca106725 6643 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
Kojto 122:f9eeca106725 6644 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
Kojto 122:f9eeca106725 6645 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
Kojto 112:6f327212ef96 6646
Kojto 112:6f327212ef96 6647
Kojto 112:6f327212ef96 6648 /**
Kojto 112:6f327212ef96 6649 * @brief EXTI11 configuration
Kojto 112:6f327212ef96 6650 */
Kojto 122:f9eeca106725 6651 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
Kojto 122:f9eeca106725 6652 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
Kojto 122:f9eeca106725 6653 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
Kojto 122:f9eeca106725 6654 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
Kojto 122:f9eeca106725 6655 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
Kojto 122:f9eeca106725 6656 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
Kojto 122:f9eeca106725 6657 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
Kojto 122:f9eeca106725 6658 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
Kojto 122:f9eeca106725 6659 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
Kojto 122:f9eeca106725 6660 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
Kojto 112:6f327212ef96 6661
Kojto 112:6f327212ef96 6662
Kojto 112:6f327212ef96 6663 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 122:f9eeca106725 6664 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
Kojto 122:f9eeca106725 6665 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
Kojto 122:f9eeca106725 6666 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
Kojto 122:f9eeca106725 6667 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
Kojto 112:6f327212ef96 6668 /**
Kojto 112:6f327212ef96 6669 * @brief EXTI12 configuration
Kojto 112:6f327212ef96 6670 */
Kojto 122:f9eeca106725 6671 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
Kojto 122:f9eeca106725 6672 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
Kojto 122:f9eeca106725 6673 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
Kojto 122:f9eeca106725 6674 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
Kojto 122:f9eeca106725 6675 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
Kojto 122:f9eeca106725 6676 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
Kojto 122:f9eeca106725 6677 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
Kojto 122:f9eeca106725 6678 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
Kojto 122:f9eeca106725 6679 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
Kojto 122:f9eeca106725 6680 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
Kojto 112:6f327212ef96 6681
Kojto 112:6f327212ef96 6682
Kojto 112:6f327212ef96 6683 /**
Kojto 112:6f327212ef96 6684 * @brief EXTI13 configuration
Kojto 112:6f327212ef96 6685 */
Kojto 122:f9eeca106725 6686 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
Kojto 122:f9eeca106725 6687 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
Kojto 122:f9eeca106725 6688 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
Kojto 122:f9eeca106725 6689 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
Kojto 122:f9eeca106725 6690 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
Kojto 122:f9eeca106725 6691 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
Kojto 122:f9eeca106725 6692 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
Kojto 122:f9eeca106725 6693 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
Kojto 122:f9eeca106725 6694 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
Kojto 122:f9eeca106725 6695 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
Kojto 112:6f327212ef96 6696
Kojto 112:6f327212ef96 6697
Kojto 112:6f327212ef96 6698 /**
Kojto 112:6f327212ef96 6699 * @brief EXTI14 configuration
Kojto 112:6f327212ef96 6700 */
Kojto 122:f9eeca106725 6701 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
Kojto 122:f9eeca106725 6702 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
Kojto 122:f9eeca106725 6703 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
Kojto 122:f9eeca106725 6704 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
Kojto 122:f9eeca106725 6705 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
Kojto 122:f9eeca106725 6706 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
Kojto 122:f9eeca106725 6707 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
Kojto 122:f9eeca106725 6708 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
Kojto 122:f9eeca106725 6709 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
Kojto 122:f9eeca106725 6710 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
Kojto 112:6f327212ef96 6711
Kojto 112:6f327212ef96 6712
Kojto 112:6f327212ef96 6713 /**
Kojto 112:6f327212ef96 6714 * @brief EXTI15 configuration
Kojto 112:6f327212ef96 6715 */
Kojto 122:f9eeca106725 6716 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
Kojto 122:f9eeca106725 6717 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
Kojto 122:f9eeca106725 6718 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
Kojto 122:f9eeca106725 6719 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
Kojto 122:f9eeca106725 6720 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
Kojto 122:f9eeca106725 6721 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
Kojto 122:f9eeca106725 6722 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
Kojto 122:f9eeca106725 6723 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
Kojto 122:f9eeca106725 6724 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
Kojto 122:f9eeca106725 6725 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
Kojto 112:6f327212ef96 6726
Kojto 112:6f327212ef96 6727 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 122:f9eeca106725 6728 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
Kojto 122:f9eeca106725 6729 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
Kojto 112:6f327212ef96 6730
Kojto 112:6f327212ef96 6731 /****************** Bit definition for SYSCFG_CFGR register ****************/
Kojto 122:f9eeca106725 6732 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
Kojto 122:f9eeca106725 6733 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
Kojto 112:6f327212ef96 6734
Kojto 112:6f327212ef96 6735 /******************************************************************************/
Kojto 112:6f327212ef96 6736 /* */
Kojto 112:6f327212ef96 6737 /* TIM */
Kojto 112:6f327212ef96 6738 /* */
Kojto 112:6f327212ef96 6739 /******************************************************************************/
Kojto 112:6f327212ef96 6740 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 6741 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
Kojto 122:f9eeca106725 6742 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
Kojto 122:f9eeca106725 6743 #define TIM_CR1_URS 0x0004U /*!<Update request source */
Kojto 122:f9eeca106725 6744 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
Kojto 122:f9eeca106725 6745 #define TIM_CR1_DIR 0x0010U /*!<Direction */
Kojto 122:f9eeca106725 6746
Kojto 122:f9eeca106725 6747 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 6748 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
Kojto 122:f9eeca106725 6749 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
Kojto 122:f9eeca106725 6750
Kojto 122:f9eeca106725 6751 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 6752
Kojto 122:f9eeca106725 6753 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 6754 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6755 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
Kojto 112:6f327212ef96 6756
Kojto 112:6f327212ef96 6757 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 6758 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 6759 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 6760 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 6761
Kojto 122:f9eeca106725 6762 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 6763 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6764 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6765 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6766
Kojto 122:f9eeca106725 6767 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
Kojto 122:f9eeca106725 6768 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 6769 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 6770 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 6771 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 6772 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 6773 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 6774 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
Kojto 112:6f327212ef96 6775
Kojto 112:6f327212ef96 6776 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 6777 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 6778 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6779 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6780 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6781
Kojto 122:f9eeca106725 6782 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 6783 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6784 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6785 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6786
Kojto 122:f9eeca106725 6787 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
Kojto 122:f9eeca106725 6788
Kojto 122:f9eeca106725 6789 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 6790 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6791 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6792 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6793 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6794
Kojto 122:f9eeca106725 6795 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 6796 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6797 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6798
Kojto 122:f9eeca106725 6799 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
Kojto 122:f9eeca106725 6800 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
Kojto 112:6f327212ef96 6801
Kojto 112:6f327212ef96 6802 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 6803 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
Kojto 122:f9eeca106725 6804 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 6805 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 6806 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 6807 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 6808 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
Kojto 122:f9eeca106725 6809 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 6810 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
Kojto 122:f9eeca106725 6811 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
Kojto 122:f9eeca106725 6812 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 6813 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 6814 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 6815 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 6816 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
Kojto 122:f9eeca106725 6817 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
Kojto 112:6f327212ef96 6818
Kojto 112:6f327212ef96 6819 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 6820 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 6821 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 6822 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 6823 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 6824 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 6825 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 6826 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 6827 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 6828 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 6829 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 6830 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 6831 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
Kojto 112:6f327212ef96 6832
Kojto 112:6f327212ef96 6833 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 6834 #define TIM_EGR_UG 0x01U /*!<Update Generation */
Kojto 122:f9eeca106725 6835 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 6836 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 6837 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 6838 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 6839 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 6840 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
Kojto 122:f9eeca106725 6841 #define TIM_EGR_BG 0x80U /*!<Break Generation */
Kojto 112:6f327212ef96 6842
Kojto 112:6f327212ef96 6843 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 6844 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 6845 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6846 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6847
Kojto 122:f9eeca106725 6848 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 6849 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 6850
Kojto 122:f9eeca106725 6851 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 6852 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6853 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6854 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6855
Kojto 122:f9eeca106725 6856 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 6857
Kojto 122:f9eeca106725 6858 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 6859 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6860 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6861
Kojto 122:f9eeca106725 6862 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 6863 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 6864
Kojto 122:f9eeca106725 6865 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 6866 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6867 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6868 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6869
Kojto 122:f9eeca106725 6870 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
Kojto 112:6f327212ef96 6871
Kojto 112:6f327212ef96 6872 /*----------------------------------------------------------------------------*/
Kojto 112:6f327212ef96 6873
Kojto 122:f9eeca106725 6874 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 6875 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6876 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6877
Kojto 122:f9eeca106725 6878 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 6879 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6880 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6881 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6882 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6883
Kojto 122:f9eeca106725 6884 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 6885 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6886 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6887
Kojto 122:f9eeca106725 6888 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 6889 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6890 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6891 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6892 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
Kojto 112:6f327212ef96 6893
Kojto 112:6f327212ef96 6894 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 6895 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 6896 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6897 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6898
Kojto 122:f9eeca106725 6899 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 6900 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 6901
Kojto 122:f9eeca106725 6902 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 6903 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6904 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6905 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6906
Kojto 122:f9eeca106725 6907 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 6908
Kojto 122:f9eeca106725 6909 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 6910 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6911 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6912
Kojto 122:f9eeca106725 6913 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 6914 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 6915
Kojto 122:f9eeca106725 6916 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 6917 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6918 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6919 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6920
Kojto 122:f9eeca106725 6921 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
Kojto 112:6f327212ef96 6922
Kojto 112:6f327212ef96 6923 /*----------------------------------------------------------------------------*/
Kojto 112:6f327212ef96 6924
Kojto 122:f9eeca106725 6925 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 6926 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6927 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6928
Kojto 122:f9eeca106725 6929 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 6930 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6931 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6932 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 6933 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 6934
Kojto 122:f9eeca106725 6935 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 6936 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6937 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6938
Kojto 122:f9eeca106725 6939 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 6940 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6941 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6942 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6943 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
Kojto 112:6f327212ef96 6944
Kojto 112:6f327212ef96 6945 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 6946 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 6947 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 6948 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 6949 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 6950 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 6951 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 6952 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 6953 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 6954 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 6955 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 6956 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 6957 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 6958 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 6959 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 6960 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 112:6f327212ef96 6961
Kojto 112:6f327212ef96 6962 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 6963 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
Kojto 112:6f327212ef96 6964
Kojto 112:6f327212ef96 6965 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 6966 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
Kojto 112:6f327212ef96 6967
Kojto 112:6f327212ef96 6968 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 6969 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
Kojto 112:6f327212ef96 6970
Kojto 112:6f327212ef96 6971 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 6972 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
Kojto 112:6f327212ef96 6973
Kojto 112:6f327212ef96 6974 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 6975 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
Kojto 112:6f327212ef96 6976
Kojto 112:6f327212ef96 6977 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 6978 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
Kojto 112:6f327212ef96 6979
Kojto 112:6f327212ef96 6980 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 6981 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
Kojto 112:6f327212ef96 6982
Kojto 112:6f327212ef96 6983 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 6984 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
Kojto 112:6f327212ef96 6985
Kojto 112:6f327212ef96 6986 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 6987 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 6988 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6989 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6990 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6991 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6992 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6993 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6994 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6995 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 6996
Kojto 122:f9eeca106725 6997 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 6998 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6999 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7000
Kojto 122:f9eeca106725 7001 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 7002 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 7003 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
Kojto 122:f9eeca106725 7004 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
Kojto 122:f9eeca106725 7005 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
Kojto 122:f9eeca106725 7006 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
Kojto 112:6f327212ef96 7007
Kojto 112:6f327212ef96 7008 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 7009 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 7010 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7011 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7012 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7013 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7014 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7015
Kojto 122:f9eeca106725 7016 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 7017 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7018 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7019 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 7020 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 7021 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
Kojto 112:6f327212ef96 7022
Kojto 112:6f327212ef96 7023 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 7024 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
Kojto 112:6f327212ef96 7025
Kojto 112:6f327212ef96 7026 /******************* Bit definition for TIM_OR register *********************/
Kojto 122:f9eeca106725 7027 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 122:f9eeca106725 7028 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
Kojto 122:f9eeca106725 7029 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
Kojto 122:f9eeca106725 7030 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 122:f9eeca106725 7031 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7032 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
Kojto 112:6f327212ef96 7033
Kojto 112:6f327212ef96 7034
Kojto 112:6f327212ef96 7035 /******************************************************************************/
Kojto 112:6f327212ef96 7036 /* */
Kojto 112:6f327212ef96 7037 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 112:6f327212ef96 7038 /* */
Kojto 112:6f327212ef96 7039 /******************************************************************************/
Kojto 112:6f327212ef96 7040 /******************* Bit definition for USART_SR register *******************/
Kojto 122:f9eeca106725 7041 #define USART_SR_PE 0x0001U /*!<Parity Error */
Kojto 122:f9eeca106725 7042 #define USART_SR_FE 0x0002U /*!<Framing Error */
Kojto 122:f9eeca106725 7043 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
Kojto 122:f9eeca106725 7044 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
Kojto 122:f9eeca106725 7045 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
Kojto 122:f9eeca106725 7046 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
Kojto 122:f9eeca106725 7047 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
Kojto 122:f9eeca106725 7048 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
Kojto 122:f9eeca106725 7049 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
Kojto 122:f9eeca106725 7050 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
Kojto 112:6f327212ef96 7051
Kojto 112:6f327212ef96 7052 /******************* Bit definition for USART_DR register *******************/
Kojto 122:f9eeca106725 7053 #define USART_DR_DR 0x01FFU /*!<Data value */
Kojto 112:6f327212ef96 7054
Kojto 112:6f327212ef96 7055 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 7056 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
Kojto 122:f9eeca106725 7057 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
Kojto 112:6f327212ef96 7058
Kojto 112:6f327212ef96 7059 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 7060 #define USART_CR1_SBK 0x0001U /*!<Send Break */
Kojto 122:f9eeca106725 7061 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
Kojto 122:f9eeca106725 7062 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
Kojto 122:f9eeca106725 7063 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
Kojto 122:f9eeca106725 7064 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
Kojto 122:f9eeca106725 7065 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
Kojto 122:f9eeca106725 7066 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 7067 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 7068 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
Kojto 122:f9eeca106725 7069 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
Kojto 122:f9eeca106725 7070 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
Kojto 122:f9eeca106725 7071 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
Kojto 122:f9eeca106725 7072 #define USART_CR1_M 0x1000U /*!<Word length */
Kojto 122:f9eeca106725 7073 #define USART_CR1_UE 0x2000U /*!<USART Enable */
Kojto 122:f9eeca106725 7074 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
Kojto 112:6f327212ef96 7075
Kojto 112:6f327212ef96 7076 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 7077 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
Kojto 122:f9eeca106725 7078 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
Kojto 122:f9eeca106725 7079 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 7080 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
Kojto 122:f9eeca106725 7081 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
Kojto 122:f9eeca106725 7082 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
Kojto 122:f9eeca106725 7083 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
Kojto 122:f9eeca106725 7084
Kojto 122:f9eeca106725 7085 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 7086 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7087 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7088
Kojto 122:f9eeca106725 7089 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
Kojto 112:6f327212ef96 7090
Kojto 112:6f327212ef96 7091 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 7092 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 7093 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
Kojto 122:f9eeca106725 7094 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
Kojto 122:f9eeca106725 7095 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
Kojto 122:f9eeca106725 7096 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
Kojto 122:f9eeca106725 7097 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
Kojto 122:f9eeca106725 7098 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
Kojto 122:f9eeca106725 7099 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
Kojto 122:f9eeca106725 7100 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
Kojto 122:f9eeca106725 7101 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
Kojto 122:f9eeca106725 7102 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
Kojto 122:f9eeca106725 7103 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
Kojto 112:6f327212ef96 7104
Kojto 112:6f327212ef96 7105 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 7106 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 7107 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7108 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7109 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7110 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7111 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7112 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 7113 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 7114 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
Kojto 122:f9eeca106725 7115
Kojto 122:f9eeca106725 7116 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
Kojto 112:6f327212ef96 7117
Kojto 112:6f327212ef96 7118 /******************************************************************************/
Kojto 112:6f327212ef96 7119 /* */
Kojto 112:6f327212ef96 7120 /* Window WATCHDOG */
Kojto 112:6f327212ef96 7121 /* */
Kojto 112:6f327212ef96 7122 /******************************************************************************/
Kojto 112:6f327212ef96 7123 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 7124 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 7125 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 7126 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 7127 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
Kojto 122:f9eeca106725 7128 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
Kojto 122:f9eeca106725 7129 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
Kojto 122:f9eeca106725 7130 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
Kojto 122:f9eeca106725 7131 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
Kojto 122:f9eeca106725 7132 /* Legacy defines */
Kojto 122:f9eeca106725 7133 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 7134 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 7135 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 7136 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 7137 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 7138 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 7139 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 7140
Kojto 122:f9eeca106725 7141 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
Kojto 112:6f327212ef96 7142
Kojto 112:6f327212ef96 7143 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 7144 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 7145 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7146 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7147 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7148 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7149 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7150 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 7151 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 7152 /* Legacy defines */
Kojto 122:f9eeca106725 7153 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 7154 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 7155 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 7156 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 7157 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 7158 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 7159 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 7160
Kojto 122:f9eeca106725 7161 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 7162 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
Kojto 122:f9eeca106725 7163 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
Kojto 122:f9eeca106725 7164 /* Legacy defines */
Kojto 122:f9eeca106725 7165 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 7166 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 7167
Kojto 122:f9eeca106725 7168 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
Kojto 112:6f327212ef96 7169
Kojto 112:6f327212ef96 7170 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 7171 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
Kojto 112:6f327212ef96 7172
Kojto 112:6f327212ef96 7173
Kojto 112:6f327212ef96 7174 /******************************************************************************/
Kojto 112:6f327212ef96 7175 /* */
Kojto 112:6f327212ef96 7176 /* DBG */
Kojto 112:6f327212ef96 7177 /* */
Kojto 112:6f327212ef96 7178 /******************************************************************************/
Kojto 112:6f327212ef96 7179 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 7180 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto 122:f9eeca106725 7181 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
Kojto 112:6f327212ef96 7182
Kojto 112:6f327212ef96 7183 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 7184 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto 122:f9eeca106725 7185 #define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto 122:f9eeca106725 7186 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto 122:f9eeca106725 7187 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto 122:f9eeca106725 7188
Kojto 122:f9eeca106725 7189 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto 122:f9eeca106725 7190 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
Kojto 122:f9eeca106725 7191 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
Kojto 112:6f327212ef96 7192
Kojto 112:6f327212ef96 7193 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 122:f9eeca106725 7194 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto 122:f9eeca106725 7195 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto 122:f9eeca106725 7196 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto 122:f9eeca106725 7197 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto 122:f9eeca106725 7198 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto 122:f9eeca106725 7199 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto 122:f9eeca106725 7200 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto 122:f9eeca106725 7201 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto 122:f9eeca106725 7202 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto 122:f9eeca106725 7203 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto 122:f9eeca106725 7204 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto 122:f9eeca106725 7205 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto 122:f9eeca106725 7206 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto 122:f9eeca106725 7207 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto 122:f9eeca106725 7208 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto 122:f9eeca106725 7209 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto 122:f9eeca106725 7210 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
Kojto 112:6f327212ef96 7211 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 7212 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 112:6f327212ef96 7213
Kojto 112:6f327212ef96 7214 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 122:f9eeca106725 7215 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto 122:f9eeca106725 7216 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto 122:f9eeca106725 7217 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto 122:f9eeca106725 7218 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto 122:f9eeca106725 7219 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
Kojto 112:6f327212ef96 7220
Kojto 112:6f327212ef96 7221
Kojto 112:6f327212ef96 7222 /******************************************************************************/
Kojto 112:6f327212ef96 7223 /* */
Kojto 112:6f327212ef96 7224 /* USB_OTG */
Kojto 112:6f327212ef96 7225 /* */
Kojto 112:6f327212ef96 7226 /******************************************************************************/
Kojto 122:f9eeca106725 7227 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
Kojto 122:f9eeca106725 7228 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
Kojto 122:f9eeca106725 7229 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
Kojto 122:f9eeca106725 7230 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
Kojto 122:f9eeca106725 7231 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
Kojto 122:f9eeca106725 7232 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
Kojto 122:f9eeca106725 7233 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
Kojto 122:f9eeca106725 7234 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
Kojto 122:f9eeca106725 7235 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
Kojto 122:f9eeca106725 7236 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 7237 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
Kojto 122:f9eeca106725 7238 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 7239 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
Kojto 122:f9eeca106725 7240 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
Kojto 122:f9eeca106725 7241 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
Kojto 122:f9eeca106725 7242 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
Kojto 122:f9eeca106725 7243 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
Kojto 122:f9eeca106725 7244 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
Kojto 122:f9eeca106725 7245 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
Kojto 122:f9eeca106725 7246
Kojto 122:f9eeca106725 7247 /******************** Bit definition for USB_OTG_HCFG register ********************/
Kojto 122:f9eeca106725 7248
Kojto 122:f9eeca106725 7249 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
Kojto 122:f9eeca106725 7250 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7251 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7252 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
Kojto 122:f9eeca106725 7253
Kojto 122:f9eeca106725 7254 /******************** Bit definition for USB_OTG_DCFG register ********************/
Kojto 122:f9eeca106725 7255
Kojto 122:f9eeca106725 7256 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
Kojto 122:f9eeca106725 7257 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7258 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7259 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
Kojto 122:f9eeca106725 7260
Kojto 122:f9eeca106725 7261 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
Kojto 122:f9eeca106725 7262 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7263 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7264 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7265 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 7266 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
Kojto 122:f9eeca106725 7267 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
Kojto 122:f9eeca106725 7268 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
Kojto 122:f9eeca106725 7269
Kojto 122:f9eeca106725 7270 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
Kojto 122:f9eeca106725 7271 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 7272 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7273
Kojto 122:f9eeca106725 7274 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
Kojto 122:f9eeca106725 7275 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7276 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7277
Kojto 122:f9eeca106725 7278 /******************** Bit definition for USB_OTG_PCGCR register ********************/
Kojto 122:f9eeca106725 7279 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
Kojto 122:f9eeca106725 7280 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
Kojto 122:f9eeca106725 7281 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
Kojto 122:f9eeca106725 7282
Kojto 122:f9eeca106725 7283 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
Kojto 122:f9eeca106725 7284 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
Kojto 122:f9eeca106725 7285 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
Kojto 122:f9eeca106725 7286 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
Kojto 122:f9eeca106725 7287 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
Kojto 122:f9eeca106725 7288 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
Kojto 122:f9eeca106725 7289 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
Kojto 122:f9eeca106725 7290 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
Kojto 122:f9eeca106725 7291
Kojto 122:f9eeca106725 7292 /******************** Bit definition for USB_OTG_DCTL register ********************/
Kojto 122:f9eeca106725 7293 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
Kojto 122:f9eeca106725 7294 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
Kojto 122:f9eeca106725 7295 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
Kojto 122:f9eeca106725 7296 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
Kojto 122:f9eeca106725 7297
Kojto 122:f9eeca106725 7298 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
Kojto 122:f9eeca106725 7299 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7300 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7301 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7302 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
Kojto 122:f9eeca106725 7303 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
Kojto 122:f9eeca106725 7304 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
Kojto 122:f9eeca106725 7305 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
Kojto 122:f9eeca106725 7306 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
Kojto 122:f9eeca106725 7307
Kojto 122:f9eeca106725 7308 /******************** Bit definition for USB_OTG_HFIR register ********************/
Kojto 122:f9eeca106725 7309 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
Kojto 122:f9eeca106725 7310
Kojto 122:f9eeca106725 7311 /******************** Bit definition for USB_OTG_HFNUM register ********************/
Kojto 122:f9eeca106725 7312 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
Kojto 122:f9eeca106725 7313 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
Kojto 122:f9eeca106725 7314
Kojto 122:f9eeca106725 7315 /******************** Bit definition for USB_OTG_DSTS register ********************/
Kojto 122:f9eeca106725 7316 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
Kojto 122:f9eeca106725 7317
Kojto 122:f9eeca106725 7318 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
Kojto 122:f9eeca106725 7319 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 7320 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 7321 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
Kojto 122:f9eeca106725 7322 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
Kojto 122:f9eeca106725 7323
Kojto 122:f9eeca106725 7324 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
Kojto 122:f9eeca106725 7325 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
Kojto 122:f9eeca106725 7326 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
Kojto 122:f9eeca106725 7327 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 7328 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 7329 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
Kojto 122:f9eeca106725 7330 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
Kojto 122:f9eeca106725 7331 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
Kojto 122:f9eeca106725 7332 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
Kojto 122:f9eeca106725 7333 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
Kojto 122:f9eeca106725 7334
Kojto 122:f9eeca106725 7335 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
Kojto 122:f9eeca106725 7336
Kojto 122:f9eeca106725 7337 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
Kojto 122:f9eeca106725 7338 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7339 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7340 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7341 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 122:f9eeca106725 7342 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
Kojto 122:f9eeca106725 7343 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
Kojto 122:f9eeca106725 7344 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
Kojto 122:f9eeca106725 7345 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7346 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 7347 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7348 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7349 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
Kojto 122:f9eeca106725 7350 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
Kojto 122:f9eeca106725 7351 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
Kojto 122:f9eeca106725 7352 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
Kojto 122:f9eeca106725 7353 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
Kojto 122:f9eeca106725 7354 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
Kojto 122:f9eeca106725 7355 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
Kojto 122:f9eeca106725 7356 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
Kojto 122:f9eeca106725 7357 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
Kojto 122:f9eeca106725 7358 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
Kojto 122:f9eeca106725 7359 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
Kojto 122:f9eeca106725 7360 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
Kojto 122:f9eeca106725 7361 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
Kojto 122:f9eeca106725 7362
Kojto 122:f9eeca106725 7363 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
Kojto 122:f9eeca106725 7364 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
Kojto 122:f9eeca106725 7365 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
Kojto 122:f9eeca106725 7366 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
Kojto 122:f9eeca106725 7367 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
Kojto 122:f9eeca106725 7368 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
Kojto 122:f9eeca106725 7369 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
Kojto 122:f9eeca106725 7370 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 7371 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 7372 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 7373 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
Kojto 122:f9eeca106725 7374 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
Kojto 122:f9eeca106725 7375 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
Kojto 122:f9eeca106725 7376 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
Kojto 122:f9eeca106725 7377
Kojto 122:f9eeca106725 7378 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
Kojto 122:f9eeca106725 7379 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 7380 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 7381 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 7382 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 7383 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 7384 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 7385 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 7386 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 7387
Kojto 122:f9eeca106725 7388 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
Kojto 122:f9eeca106725 7389 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
Kojto 122:f9eeca106725 7390 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
Kojto 122:f9eeca106725 7391 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7392 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7393 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7394 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7395 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7396 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7397 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7398 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 7399
Kojto 122:f9eeca106725 7400 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
Kojto 122:f9eeca106725 7401 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7402 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7403 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7404 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7405 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7406 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7407 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7408 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 7409
Kojto 122:f9eeca106725 7410 /******************** Bit definition for USB_OTG_HAINT register ********************/
Kojto 122:f9eeca106725 7411 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
Kojto 122:f9eeca106725 7412
Kojto 122:f9eeca106725 7413 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
Kojto 122:f9eeca106725 7414 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 7415 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 7416 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
Kojto 122:f9eeca106725 7417 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
Kojto 122:f9eeca106725 7418 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
Kojto 122:f9eeca106725 7419 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
Kojto 122:f9eeca106725 7420 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 7421 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 7422
Kojto 122:f9eeca106725 7423 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
Kojto 122:f9eeca106725 7424 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
Kojto 122:f9eeca106725 7425 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
Kojto 122:f9eeca106725 7426 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
Kojto 122:f9eeca106725 7427 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
Kojto 122:f9eeca106725 7428 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
Kojto 122:f9eeca106725 7429 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
Kojto 122:f9eeca106725 7430 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
Kojto 122:f9eeca106725 7431 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
Kojto 122:f9eeca106725 7432 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
Kojto 122:f9eeca106725 7433 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
Kojto 122:f9eeca106725 7434 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
Kojto 122:f9eeca106725 7435 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
Kojto 122:f9eeca106725 7436 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
Kojto 122:f9eeca106725 7437 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
Kojto 122:f9eeca106725 7438 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
Kojto 122:f9eeca106725 7439 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
Kojto 122:f9eeca106725 7440 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
Kojto 122:f9eeca106725 7441 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
Kojto 122:f9eeca106725 7442 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
Kojto 122:f9eeca106725 7443 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
Kojto 122:f9eeca106725 7444 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
Kojto 122:f9eeca106725 7445 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
Kojto 122:f9eeca106725 7446 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
Kojto 122:f9eeca106725 7447 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
Kojto 122:f9eeca106725 7448 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
Kojto 122:f9eeca106725 7449 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
Kojto 122:f9eeca106725 7450 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
Kojto 122:f9eeca106725 7451 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
Kojto 122:f9eeca106725 7452
Kojto 122:f9eeca106725 7453 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
Kojto 122:f9eeca106725 7454 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
Kojto 122:f9eeca106725 7455 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
Kojto 122:f9eeca106725 7456 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
Kojto 122:f9eeca106725 7457 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
Kojto 122:f9eeca106725 7458 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
Kojto 122:f9eeca106725 7459 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
Kojto 122:f9eeca106725 7460 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
Kojto 122:f9eeca106725 7461 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
Kojto 122:f9eeca106725 7462 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
Kojto 122:f9eeca106725 7463 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
Kojto 122:f9eeca106725 7464 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
Kojto 122:f9eeca106725 7465 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 122:f9eeca106725 7466 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
Kojto 122:f9eeca106725 7467 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
Kojto 122:f9eeca106725 7468 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
Kojto 122:f9eeca106725 7469 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
Kojto 122:f9eeca106725 7470 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
Kojto 122:f9eeca106725 7471 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
Kojto 122:f9eeca106725 7472 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
Kojto 122:f9eeca106725 7473 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
Kojto 122:f9eeca106725 7474 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
Kojto 122:f9eeca106725 7475 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
Kojto 122:f9eeca106725 7476 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
Kojto 122:f9eeca106725 7477 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
Kojto 122:f9eeca106725 7478 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
Kojto 122:f9eeca106725 7479 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
Kojto 122:f9eeca106725 7480 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
Kojto 122:f9eeca106725 7481 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
Kojto 122:f9eeca106725 7482
Kojto 122:f9eeca106725 7483 /******************** Bit definition for USB_OTG_DAINT register ********************/
Kojto 122:f9eeca106725 7484 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
Kojto 122:f9eeca106725 7485 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
Kojto 122:f9eeca106725 7486
Kojto 122:f9eeca106725 7487 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
Kojto 122:f9eeca106725 7488 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
Kojto 112:6f327212ef96 7489
Kojto 112:6f327212ef96 7490 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 122:f9eeca106725 7491 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 7492 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 7493 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 7494 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 7495
Kojto 122:f9eeca106725 7496 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
Kojto 122:f9eeca106725 7497 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 7498 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
Kojto 112:6f327212ef96 7499
Kojto 112:6f327212ef96 7500 /******************** Bit definition for OTG register ********************/
Kojto 112:6f327212ef96 7501
Kojto 122:f9eeca106725 7502 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 7503 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7504 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7505 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7506 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7507 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 7508
Kojto 122:f9eeca106725 7509 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 7510 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7511 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7512
Kojto 122:f9eeca106725 7513 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 7514 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7515 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7516 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7517 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7518
Kojto 122:f9eeca106725 7519 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 7520 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7521 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7522 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7523 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7524
Kojto 122:f9eeca106725 7525 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 7526 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7527 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7528 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7529 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 112:6f327212ef96 7530
Kojto 112:6f327212ef96 7531 /******************** Bit definition for OTG register ********************/
Kojto 112:6f327212ef96 7532
Kojto 122:f9eeca106725 7533 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 7534 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7535 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7536 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7537 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7538 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 7539
Kojto 122:f9eeca106725 7540 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 7541 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7542 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7543
Kojto 122:f9eeca106725 7544 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 7545 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7546 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7547 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7548 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7549
Kojto 122:f9eeca106725 7550 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 7551 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7552 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7553 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7554 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7555
Kojto 122:f9eeca106725 7556 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 7557 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7558 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7559 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7560 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7561
Kojto 122:f9eeca106725 7562 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
Kojto 122:f9eeca106725 7563 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
Kojto 122:f9eeca106725 7564
Kojto 122:f9eeca106725 7565 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
Kojto 122:f9eeca106725 7566 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
Kojto 112:6f327212ef96 7567
Kojto 112:6f327212ef96 7568 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 7569 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
Kojto 122:f9eeca106725 7570 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
Kojto 122:f9eeca106725 7571 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
Kojto 122:f9eeca106725 7572 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
Kojto 122:f9eeca106725 7573
Kojto 122:f9eeca106725 7574 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
Kojto 122:f9eeca106725 7575 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
Kojto 122:f9eeca106725 7576
Kojto 122:f9eeca106725 7577 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
Kojto 122:f9eeca106725 7578 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
Kojto 122:f9eeca106725 7579
Kojto 122:f9eeca106725 7580 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
Kojto 122:f9eeca106725 7581 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7582 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7583 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7584 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7585 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7586 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7587 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7588 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 7589
Kojto 122:f9eeca106725 7590 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
Kojto 122:f9eeca106725 7591 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7592 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7593 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7594 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7595 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7596 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7597 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7598
Kojto 122:f9eeca106725 7599 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
Kojto 122:f9eeca106725 7600 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
Kojto 122:f9eeca106725 7601 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
Kojto 122:f9eeca106725 7602
Kojto 122:f9eeca106725 7603 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
Kojto 122:f9eeca106725 7604 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 7605 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 7606 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
Kojto 122:f9eeca106725 7607 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
Kojto 122:f9eeca106725 7608 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
Kojto 122:f9eeca106725 7609 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
Kojto 122:f9eeca106725 7610 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
Kojto 122:f9eeca106725 7611 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
Kojto 122:f9eeca106725 7612 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
Kojto 122:f9eeca106725 7613 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
Kojto 122:f9eeca106725 7614
Kojto 122:f9eeca106725 7615 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
Kojto 122:f9eeca106725 7616 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7617 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7618 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7619 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7620 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7621 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7622 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7623 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 7624 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
Kojto 122:f9eeca106725 7625 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
Kojto 122:f9eeca106725 7626
Kojto 122:f9eeca106725 7627 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
Kojto 122:f9eeca106725 7628 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 122:f9eeca106725 7629
Kojto 122:f9eeca106725 7630 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
Kojto 122:f9eeca106725 7631 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
Kojto 122:f9eeca106725 7632 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
Kojto 122:f9eeca106725 7633
Kojto 122:f9eeca106725 7634 /******************** Bit definition for USB_OTG_GCCFG register ********************/
Kojto 122:f9eeca106725 7635 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
Kojto 122:f9eeca106725 7636 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
Kojto 122:f9eeca106725 7637
Kojto 122:f9eeca106725 7638 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
Kojto 122:f9eeca106725 7639 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
Kojto 122:f9eeca106725 7640 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 112:6f327212ef96 7641
Kojto 122:f9eeca106725 7642 /******************** Bit definition for USB_OTG_CID register ********************/
Kojto 122:f9eeca106725 7643 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
Kojto 112:6f327212ef96 7644
Kojto 112:6f327212ef96 7645 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
Kojto 122:f9eeca106725 7646 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
Kojto 122:f9eeca106725 7647 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
Kojto 122:f9eeca106725 7648 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 7649 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 7650 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
Kojto 122:f9eeca106725 7651 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
Kojto 122:f9eeca106725 7652 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
Kojto 122:f9eeca106725 7653 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
Kojto 122:f9eeca106725 7654 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
Kojto 122:f9eeca106725 7655 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
Kojto 122:f9eeca106725 7656 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
Kojto 122:f9eeca106725 7657 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
Kojto 122:f9eeca106725 7658 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
Kojto 122:f9eeca106725 7659 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
Kojto 122:f9eeca106725 7660 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
Kojto 122:f9eeca106725 7661
Kojto 122:f9eeca106725 7662 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 7663 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 7664 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 7665 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 7666 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 7667 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 7668 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 7669 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 7670 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 7671 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 7672
Kojto 122:f9eeca106725 7673 /******************** Bit definition for USB_OTG_HPRT register ********************/
Kojto 122:f9eeca106725 7674 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
Kojto 122:f9eeca106725 7675 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
Kojto 122:f9eeca106725 7676 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
Kojto 122:f9eeca106725 7677 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
Kojto 122:f9eeca106725 7678 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
Kojto 122:f9eeca106725 7679 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
Kojto 122:f9eeca106725 7680 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
Kojto 122:f9eeca106725 7681 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
Kojto 122:f9eeca106725 7682 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
Kojto 122:f9eeca106725 7683
Kojto 122:f9eeca106725 7684 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
Kojto 122:f9eeca106725 7685 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7686 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 7687 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
Kojto 122:f9eeca106725 7688
Kojto 122:f9eeca106725 7689 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
Kojto 122:f9eeca106725 7690 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7691 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7692 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7693 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7694
Kojto 122:f9eeca106725 7695 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
Kojto 122:f9eeca106725 7696 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7697 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7698
Kojto 122:f9eeca106725 7699 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 7700 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 7701 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 7702 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
Kojto 122:f9eeca106725 7703 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 7704 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 7705 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 7706 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 7707 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 7708 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
Kojto 122:f9eeca106725 7709 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 7710 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
Kojto 122:f9eeca106725 7711
Kojto 122:f9eeca106725 7712 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
Kojto 122:f9eeca106725 7713 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
Kojto 122:f9eeca106725 7714 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
Kojto 122:f9eeca106725 7715
Kojto 122:f9eeca106725 7716 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
Kojto 122:f9eeca106725 7717 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 7718 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 7719 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
Kojto 122:f9eeca106725 7720 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 7721
Kojto 122:f9eeca106725 7722 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 7723 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7724 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7725 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 7726
Kojto 122:f9eeca106725 7727 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
Kojto 122:f9eeca106725 7728 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7729 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7730 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7731 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7732 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 7733 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 7734 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 7735 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 7736 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 7737 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 122:f9eeca106725 7738
Kojto 122:f9eeca106725 7739 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
Kojto 122:f9eeca106725 7740 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 7741
Kojto 122:f9eeca106725 7742 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
Kojto 122:f9eeca106725 7743 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 7744 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7745 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7746 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7747 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
Kojto 122:f9eeca106725 7748 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
Kojto 122:f9eeca106725 7749
Kojto 122:f9eeca106725 7750 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 7751 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7752 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7753
Kojto 122:f9eeca106725 7754 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
Kojto 122:f9eeca106725 7755 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7756 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7757
Kojto 122:f9eeca106725 7758 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
Kojto 122:f9eeca106725 7759 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7760 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7761 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7762 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7763 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7764 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7765 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7766 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
Kojto 122:f9eeca106725 7767 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
Kojto 122:f9eeca106725 7768 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
Kojto 122:f9eeca106725 7769
Kojto 122:f9eeca106725 7770 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
Kojto 122:f9eeca106725 7771
Kojto 122:f9eeca106725 7772 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
Kojto 122:f9eeca106725 7773 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7774 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7775 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7776 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7777 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7778 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 7779 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 7780
Kojto 122:f9eeca106725 7781 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
Kojto 122:f9eeca106725 7782 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 7783 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 7784 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 7785 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 7786 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 7787 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 7788 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
Kojto 122:f9eeca106725 7789
Kojto 122:f9eeca106725 7790 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
Kojto 122:f9eeca106725 7791 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7792 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7793 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
Kojto 122:f9eeca106725 7794 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
Kojto 122:f9eeca106725 7795
Kojto 122:f9eeca106725 7796 /******************** Bit definition for USB_OTG_HCINT register ********************/
Kojto 122:f9eeca106725 7797 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
Kojto 122:f9eeca106725 7798 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
Kojto 122:f9eeca106725 7799 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 7800 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
Kojto 122:f9eeca106725 7801 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
Kojto 122:f9eeca106725 7802 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
Kojto 122:f9eeca106725 7803 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
Kojto 122:f9eeca106725 7804 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
Kojto 122:f9eeca106725 7805 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
Kojto 122:f9eeca106725 7806 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
Kojto 122:f9eeca106725 7807 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
Kojto 122:f9eeca106725 7808
Kojto 122:f9eeca106725 7809 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
Kojto 122:f9eeca106725 7810 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 7811 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 7812 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
Kojto 122:f9eeca106725 7813 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
Kojto 122:f9eeca106725 7814 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
Kojto 122:f9eeca106725 7815 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
Kojto 122:f9eeca106725 7816 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
Kojto 122:f9eeca106725 7817 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
Kojto 122:f9eeca106725 7818 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
Kojto 122:f9eeca106725 7819 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
Kojto 122:f9eeca106725 7820 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
Kojto 122:f9eeca106725 7821
Kojto 122:f9eeca106725 7822 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
Kojto 122:f9eeca106725 7823 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
Kojto 122:f9eeca106725 7824 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
Kojto 122:f9eeca106725 7825 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 7826 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
Kojto 122:f9eeca106725 7827 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
Kojto 122:f9eeca106725 7828 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
Kojto 122:f9eeca106725 7829 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
Kojto 122:f9eeca106725 7830 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
Kojto 122:f9eeca106725 7831 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
Kojto 122:f9eeca106725 7832 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
Kojto 122:f9eeca106725 7833 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
Kojto 112:6f327212ef96 7834
Kojto 112:6f327212ef96 7835 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 112:6f327212ef96 7836
Kojto 122:f9eeca106725 7837 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7838 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7839 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
Kojto 122:f9eeca106725 7840 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
Kojto 122:f9eeca106725 7841 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7842 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7843 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
Kojto 122:f9eeca106725 7844 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
Kojto 122:f9eeca106725 7845 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7846 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7847
Kojto 122:f9eeca106725 7848 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
Kojto 122:f9eeca106725 7849 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 122:f9eeca106725 7850
Kojto 122:f9eeca106725 7851 /******************** Bit definition for USB_OTG_HCDMA register ********************/
Kojto 122:f9eeca106725 7852 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 122:f9eeca106725 7853
Kojto 122:f9eeca106725 7854 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
Kojto 122:f9eeca106725 7855 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
Kojto 122:f9eeca106725 7856
Kojto 122:f9eeca106725 7857 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
Kojto 122:f9eeca106725 7858 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 122:f9eeca106725 7859 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
Kojto 122:f9eeca106725 7860
Kojto 122:f9eeca106725 7861 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
Kojto 122:f9eeca106725 7862
Kojto 122:f9eeca106725 7863 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 122:f9eeca106725 7864 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 7865 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 7866 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 7867 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 7868 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 7869 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7870 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7871 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
Kojto 122:f9eeca106725 7872 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 7873 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 7874 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 7875 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 7876 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 122:f9eeca106725 7877
Kojto 122:f9eeca106725 7878 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
Kojto 122:f9eeca106725 7879 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 7880 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 7881 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
Kojto 122:f9eeca106725 7882 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
Kojto 122:f9eeca106725 7883 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
Kojto 122:f9eeca106725 7884 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
Kojto 122:f9eeca106725 7885 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
Kojto 122:f9eeca106725 7886
Kojto 122:f9eeca106725 7887 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
Kojto 122:f9eeca106725 7888
Kojto 122:f9eeca106725 7889 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 7890 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 7891
Kojto 122:f9eeca106725 7892 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
Kojto 122:f9eeca106725 7893 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7894 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
Kojto 112:6f327212ef96 7895
Kojto 112:6f327212ef96 7896 /******************** Bit definition for PCGCCTL register ********************/
Kojto 122:f9eeca106725 7897 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
Kojto 122:f9eeca106725 7898 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 7899 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
Kojto 112:6f327212ef96 7900
Kojto 112:6f327212ef96 7901
Kojto 112:6f327212ef96 7902 /**
Kojto 112:6f327212ef96 7903 * @}
Kojto 112:6f327212ef96 7904 */
Kojto 112:6f327212ef96 7905
Kojto 112:6f327212ef96 7906 /**
Kojto 112:6f327212ef96 7907 * @}
Kojto 112:6f327212ef96 7908 */
Kojto 112:6f327212ef96 7909
Kojto 112:6f327212ef96 7910 /** @addtogroup Exported_macros
Kojto 112:6f327212ef96 7911 * @{
Kojto 112:6f327212ef96 7912 */
Kojto 112:6f327212ef96 7913
Kojto 112:6f327212ef96 7914 /******************************* ADC Instances ********************************/
Kojto 112:6f327212ef96 7915 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
Kojto 112:6f327212ef96 7916 ((INSTANCE) == ADC2) || \
Kojto 112:6f327212ef96 7917 ((INSTANCE) == ADC3))
Kojto 112:6f327212ef96 7918
Kojto 112:6f327212ef96 7919 /******************************* CAN Instances ********************************/
Kojto 112:6f327212ef96 7920 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
Kojto 112:6f327212ef96 7921 ((INSTANCE) == CAN2))
Kojto 112:6f327212ef96 7922
Kojto 112:6f327212ef96 7923 /******************************* CRC Instances ********************************/
Kojto 112:6f327212ef96 7924 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 112:6f327212ef96 7925
Kojto 112:6f327212ef96 7926 /******************************* DAC Instances ********************************/
Kojto 112:6f327212ef96 7927 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 112:6f327212ef96 7928
Kojto 112:6f327212ef96 7929 /******************************* DCMI Instances *******************************/
Kojto 112:6f327212ef96 7930 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
Kojto 112:6f327212ef96 7931
Kojto 112:6f327212ef96 7932 /******************************** DMA Instances *******************************/
Kojto 112:6f327212ef96 7933 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 112:6f327212ef96 7934 ((INSTANCE) == DMA1_Stream1) || \
Kojto 112:6f327212ef96 7935 ((INSTANCE) == DMA1_Stream2) || \
Kojto 112:6f327212ef96 7936 ((INSTANCE) == DMA1_Stream3) || \
Kojto 112:6f327212ef96 7937 ((INSTANCE) == DMA1_Stream4) || \
Kojto 112:6f327212ef96 7938 ((INSTANCE) == DMA1_Stream5) || \
Kojto 112:6f327212ef96 7939 ((INSTANCE) == DMA1_Stream6) || \
Kojto 112:6f327212ef96 7940 ((INSTANCE) == DMA1_Stream7) || \
Kojto 112:6f327212ef96 7941 ((INSTANCE) == DMA2_Stream0) || \
Kojto 112:6f327212ef96 7942 ((INSTANCE) == DMA2_Stream1) || \
Kojto 112:6f327212ef96 7943 ((INSTANCE) == DMA2_Stream2) || \
Kojto 112:6f327212ef96 7944 ((INSTANCE) == DMA2_Stream3) || \
Kojto 112:6f327212ef96 7945 ((INSTANCE) == DMA2_Stream4) || \
Kojto 112:6f327212ef96 7946 ((INSTANCE) == DMA2_Stream5) || \
Kojto 112:6f327212ef96 7947 ((INSTANCE) == DMA2_Stream6) || \
Kojto 112:6f327212ef96 7948 ((INSTANCE) == DMA2_Stream7))
Kojto 112:6f327212ef96 7949
Kojto 112:6f327212ef96 7950 /******************************* GPIO Instances *******************************/
Kojto 112:6f327212ef96 7951 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 112:6f327212ef96 7952 ((INSTANCE) == GPIOB) || \
Kojto 112:6f327212ef96 7953 ((INSTANCE) == GPIOC) || \
Kojto 112:6f327212ef96 7954 ((INSTANCE) == GPIOD) || \
Kojto 112:6f327212ef96 7955 ((INSTANCE) == GPIOE) || \
Kojto 112:6f327212ef96 7956 ((INSTANCE) == GPIOF) || \
Kojto 112:6f327212ef96 7957 ((INSTANCE) == GPIOG) || \
Kojto 112:6f327212ef96 7958 ((INSTANCE) == GPIOH))
Kojto 112:6f327212ef96 7959
Kojto 112:6f327212ef96 7960 /******************************** I2C Instances *******************************/
Kojto 112:6f327212ef96 7961 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 112:6f327212ef96 7962 ((INSTANCE) == I2C2) || \
Kojto 112:6f327212ef96 7963 ((INSTANCE) == I2C3))
Kojto 112:6f327212ef96 7964
Kojto 112:6f327212ef96 7965 /******************************** I2S Instances *******************************/
Kojto 112:6f327212ef96 7966 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 112:6f327212ef96 7967 ((INSTANCE) == SPI2) || \
Kojto 112:6f327212ef96 7968 ((INSTANCE) == SPI3))
Kojto 112:6f327212ef96 7969
Kojto 112:6f327212ef96 7970 /****************************** RTC Instances *********************************/
Kojto 112:6f327212ef96 7971 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 112:6f327212ef96 7972
Kojto 112:6f327212ef96 7973 /******************************* SAI Instances ********************************/
Kojto 122:f9eeca106725 7974 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
Kojto 112:6f327212ef96 7975 ((PERIPH) == SAI1_Block_B) || \
Kojto 112:6f327212ef96 7976 ((PERIPH) == SAI2_Block_A) || \
Kojto 112:6f327212ef96 7977 ((PERIPH) == SAI2_Block_B))
Kojto 122:f9eeca106725 7978 /* Legacy define */
Kojto 122:f9eeca106725 7979 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
Kojto 112:6f327212ef96 7980
Kojto 112:6f327212ef96 7981 /******************************** SPI Instances *******************************/
Kojto 112:6f327212ef96 7982 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 112:6f327212ef96 7983 ((INSTANCE) == SPI2) || \
Kojto 112:6f327212ef96 7984 ((INSTANCE) == SPI3) || \
Kojto 112:6f327212ef96 7985 ((INSTANCE) == SPI4))
Kojto 112:6f327212ef96 7986
Kojto 112:6f327212ef96 7987 /****************** TIM Instances : All supported instances *******************/
Kojto 112:6f327212ef96 7988 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7989 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7990 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7991 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7992 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7993 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 7994 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 7995 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 7996 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 7997 ((INSTANCE) == TIM10) || \
Kojto 112:6f327212ef96 7998 ((INSTANCE) == TIM11) || \
Kojto 112:6f327212ef96 7999 ((INSTANCE) == TIM12) || \
Kojto 112:6f327212ef96 8000 ((INSTANCE) == TIM13) || \
Kojto 112:6f327212ef96 8001 ((INSTANCE) == TIM14))
Kojto 112:6f327212ef96 8002
Kojto 112:6f327212ef96 8003 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 112:6f327212ef96 8004 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8005 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8006 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8007 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8008 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8009 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8010 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8011 ((INSTANCE) == TIM10) || \
Kojto 112:6f327212ef96 8012 ((INSTANCE) == TIM11) || \
Kojto 112:6f327212ef96 8013 ((INSTANCE) == TIM12) || \
Kojto 112:6f327212ef96 8014 ((INSTANCE) == TIM13) || \
Kojto 112:6f327212ef96 8015 ((INSTANCE) == TIM14))
Kojto 112:6f327212ef96 8016
Kojto 112:6f327212ef96 8017 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 112:6f327212ef96 8018 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8019 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8020 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8021 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8022 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8023 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8024 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8025 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 8026
Kojto 112:6f327212ef96 8027 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 112:6f327212ef96 8028 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8029 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8030 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8031 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8032 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8033 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8034
Kojto 112:6f327212ef96 8035 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 112:6f327212ef96 8036 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8037 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8038 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8039 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8040 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8041 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8042
Kojto 112:6f327212ef96 8043 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 112:6f327212ef96 8044 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8045 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8046
Kojto 112:6f327212ef96 8047 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 112:6f327212ef96 8048 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8049 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8050 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8051 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8052 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8053 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8054
Kojto 112:6f327212ef96 8055 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 112:6f327212ef96 8056 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8057 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8058 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8059 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8060 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8061 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 8062 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 8063 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8064
Kojto 112:6f327212ef96 8065 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 112:6f327212ef96 8066 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8067 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8068 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8069 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8070 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8071 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8072
Kojto 112:6f327212ef96 8073 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 112:6f327212ef96 8074 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8075 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8076 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8077 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8078 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8079 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8080
Kojto 112:6f327212ef96 8081 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 112:6f327212ef96 8082 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8083 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8084 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8085 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8086 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8087 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8088
Kojto 112:6f327212ef96 8089 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 112:6f327212ef96 8090 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8091 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8092 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8093 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8094 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8095 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 8096 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 8097 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8098 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8099 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 8100
Kojto 112:6f327212ef96 8101 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 112:6f327212ef96 8102 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8103 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8104 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8105 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8106 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8107 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8108 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8109 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 8110
Kojto 112:6f327212ef96 8111 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 112:6f327212ef96 8112 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8113 ((INSTANCE) == TIM5))
Kojto 112:6f327212ef96 8114
Kojto 112:6f327212ef96 8115 /***************** TIM Instances : external trigger input availabe ************/
Kojto 112:6f327212ef96 8116 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8117 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8118 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8119 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8120 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8121 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8122
Kojto 112:6f327212ef96 8123 /****************** TIM Instances : remapping capability **********************/
Kojto 112:6f327212ef96 8124 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8125 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8126 ((INSTANCE) == TIM11))
Kojto 112:6f327212ef96 8127
Kojto 112:6f327212ef96 8128 /******************* TIM Instances : output(s) available **********************/
Kojto 112:6f327212ef96 8129 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 112:6f327212ef96 8130 ((((INSTANCE) == TIM1) && \
Kojto 112:6f327212ef96 8131 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8132 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8133 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8134 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8135 || \
Kojto 112:6f327212ef96 8136 (((INSTANCE) == TIM2) && \
Kojto 112:6f327212ef96 8137 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8138 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8139 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8140 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8141 || \
Kojto 112:6f327212ef96 8142 (((INSTANCE) == TIM3) && \
Kojto 112:6f327212ef96 8143 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8144 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8145 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8146 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8147 || \
Kojto 112:6f327212ef96 8148 (((INSTANCE) == TIM4) && \
Kojto 112:6f327212ef96 8149 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8150 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8151 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8152 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8153 || \
Kojto 112:6f327212ef96 8154 (((INSTANCE) == TIM5) && \
Kojto 112:6f327212ef96 8155 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8156 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8157 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8158 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8159 || \
Kojto 112:6f327212ef96 8160 (((INSTANCE) == TIM8) && \
Kojto 112:6f327212ef96 8161 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8162 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8163 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8164 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8165 || \
Kojto 112:6f327212ef96 8166 (((INSTANCE) == TIM9) && \
Kojto 112:6f327212ef96 8167 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8168 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 112:6f327212ef96 8169 || \
Kojto 112:6f327212ef96 8170 (((INSTANCE) == TIM10) && \
Kojto 112:6f327212ef96 8171 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8172 || \
Kojto 112:6f327212ef96 8173 (((INSTANCE) == TIM11) && \
Kojto 112:6f327212ef96 8174 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8175 || \
Kojto 112:6f327212ef96 8176 (((INSTANCE) == TIM12) && \
Kojto 112:6f327212ef96 8177 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8178 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 112:6f327212ef96 8179 || \
Kojto 112:6f327212ef96 8180 (((INSTANCE) == TIM13) && \
Kojto 112:6f327212ef96 8181 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8182 || \
Kojto 112:6f327212ef96 8183 (((INSTANCE) == TIM14) && \
Kojto 112:6f327212ef96 8184 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 112:6f327212ef96 8185
Kojto 112:6f327212ef96 8186 /************ TIM Instances : complementary output(s) available ***************/
Kojto 112:6f327212ef96 8187 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 112:6f327212ef96 8188 ((((INSTANCE) == TIM1) && \
Kojto 112:6f327212ef96 8189 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8190 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8191 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 112:6f327212ef96 8192 || \
Kojto 112:6f327212ef96 8193 (((INSTANCE) == TIM8) && \
Kojto 112:6f327212ef96 8194 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8195 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8196 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 112:6f327212ef96 8197
Kojto 112:6f327212ef96 8198 /******************** USART Instances : Synchronous mode **********************/
Kojto 112:6f327212ef96 8199 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8200 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8201 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8202 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8203
Kojto 112:6f327212ef96 8204 /******************** UART Instances : Asynchronous mode **********************/
Kojto 112:6f327212ef96 8205 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8206 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8207 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8208 ((INSTANCE) == UART4) || \
Kojto 112:6f327212ef96 8209 ((INSTANCE) == UART5) || \
Kojto 112:6f327212ef96 8210 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8211
Kojto 112:6f327212ef96 8212 /****************** UART Instances : Hardware Flow control ********************/
Kojto 112:6f327212ef96 8213 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8214 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8215 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8216 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8217
Kojto 112:6f327212ef96 8218 /********************* UART Instances : Smard card mode ***********************/
Kojto 112:6f327212ef96 8219 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8220 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8221 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8222 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8223
Kojto 112:6f327212ef96 8224 /*********************** UART Instances : IRDA mode ***************************/
Kojto 112:6f327212ef96 8225 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8226 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8227 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8228 ((INSTANCE) == UART4) || \
Kojto 112:6f327212ef96 8229 ((INSTANCE) == UART5) || \
Kojto 112:6f327212ef96 8230 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8231
Kojto 122:f9eeca106725 8232 /*********************** PCD Instances ****************************************/
Kojto 122:f9eeca106725 8233 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
Kojto 122:f9eeca106725 8234 ((INSTANCE) == USB_OTG_HS))
Kojto 122:f9eeca106725 8235
Kojto 122:f9eeca106725 8236 /*********************** HCD Instances ****************************************/
Kojto 122:f9eeca106725 8237 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
Kojto 122:f9eeca106725 8238 ((INSTANCE) == USB_OTG_HS))
Kojto 122:f9eeca106725 8239
Kojto 112:6f327212ef96 8240 /****************************** SDIO Instances ********************************/
Kojto 112:6f327212ef96 8241 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 112:6f327212ef96 8242
Kojto 112:6f327212ef96 8243 /****************************** IWDG Instances ********************************/
Kojto 112:6f327212ef96 8244 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 112:6f327212ef96 8245
Kojto 112:6f327212ef96 8246 /****************************** WWDG Instances ********************************/
Kojto 112:6f327212ef96 8247 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 112:6f327212ef96 8248
Kojto 112:6f327212ef96 8249 /****************************** QSPI Instances ********************************/
Kojto 112:6f327212ef96 8250 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto 112:6f327212ef96 8251
Kojto 112:6f327212ef96 8252 /******************************* CEC Instances ********************************/
Kojto 112:6f327212ef96 8253 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto 112:6f327212ef96 8254
Kojto 112:6f327212ef96 8255 /***************************** FMPI2C Instances *******************************/
Kojto 112:6f327212ef96 8256 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
Kojto 112:6f327212ef96 8257
Kojto 112:6f327212ef96 8258 /******************************* SPDIFRX Instances ********************************/
Kojto 112:6f327212ef96 8259 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
Kojto 112:6f327212ef96 8260
Kojto 112:6f327212ef96 8261 /****************************** USB Exported Constants ************************/
Kojto 122:f9eeca106725 8262 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
Kojto 122:f9eeca106725 8263 #define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
Kojto 122:f9eeca106725 8264 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
Kojto 122:f9eeca106725 8265 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
Kojto 122:f9eeca106725 8266
Kojto 122:f9eeca106725 8267 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
Kojto 122:f9eeca106725 8268 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
Kojto 122:f9eeca106725 8269 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
Kojto 122:f9eeca106725 8270 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
Kojto 122:f9eeca106725 8271
Kojto 122:f9eeca106725 8272 /******************************************************************************/
Kojto 122:f9eeca106725 8273 /* For a painless codes migration between the STM32F4xx device product */
Kojto 122:f9eeca106725 8274 /* lines, the aliases defined below are put in place to overcome the */
Kojto 122:f9eeca106725 8275 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 122:f9eeca106725 8276 /* No need to update developed interrupt code when moving across */
Kojto 122:f9eeca106725 8277 /* product lines within the same STM32F4 Family */
Kojto 122:f9eeca106725 8278 /******************************************************************************/
Kojto 122:f9eeca106725 8279
Kojto 122:f9eeca106725 8280 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 8281 #define QuadSPI_IRQHandler QUADSPI_IRQHandler
Kojto 112:6f327212ef96 8282
Kojto 112:6f327212ef96 8283 /**
Kojto 112:6f327212ef96 8284 * @}
Kojto 112:6f327212ef96 8285 */
Kojto 112:6f327212ef96 8286
Kojto 112:6f327212ef96 8287 /**
Kojto 112:6f327212ef96 8288 * @}
Kojto 112:6f327212ef96 8289 */
Kojto 112:6f327212ef96 8290
Kojto 112:6f327212ef96 8291 /**
Kojto 112:6f327212ef96 8292 * @}
Kojto 112:6f327212ef96 8293 */
Kojto 112:6f327212ef96 8294
Kojto 112:6f327212ef96 8295 #ifdef __cplusplus
Kojto 112:6f327212ef96 8296 }
Kojto 112:6f327212ef96 8297 #endif /* __cplusplus */
Kojto 112:6f327212ef96 8298
Kojto 112:6f327212ef96 8299 #endif /* __STM32F446xx_H */
Kojto 112:6f327212ef96 8300
Kojto 112:6f327212ef96 8301
Kojto 112:6f327212ef96 8302
Kojto 112:6f327212ef96 8303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/