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TARGET_B96B_F446VE/stm32_hal_legacy.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 121:6c34061e7c34

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	112:6f327212ef96	1	/**
Kojto	112:6f327212ef96	2	******************************************************************************
Kojto	112:6f327212ef96	3	* @file stm32_hal_legacy.h
Kojto	112:6f327212ef96	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
Kojto	112:6f327212ef96	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto	112:6f327212ef96	8	* macros and functions maintained for legacy purpose.
Kojto	112:6f327212ef96	9	******************************************************************************
Kojto	112:6f327212ef96	10	* @attention
Kojto	112:6f327212ef96	11	*
Kojto	122:f9eeca106725	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	112:6f327212ef96	13	*
Kojto	112:6f327212ef96	14	* Redistribution and use in source and binary forms, with or without modification,
Kojto	112:6f327212ef96	15	* are permitted provided that the following conditions are met:
Kojto	112:6f327212ef96	16	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	112:6f327212ef96	17	* this list of conditions and the following disclaimer.
Kojto	112:6f327212ef96	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	112:6f327212ef96	19	* this list of conditions and the following disclaimer in the documentation
Kojto	112:6f327212ef96	20	* and/or other materials provided with the distribution.
Kojto	112:6f327212ef96	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	112:6f327212ef96	22	* may be used to endorse or promote products derived from this software
Kojto	112:6f327212ef96	23	* without specific prior written permission.
Kojto	112:6f327212ef96	24	*
Kojto	112:6f327212ef96	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	112:6f327212ef96	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	112:6f327212ef96	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	112:6f327212ef96	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	112:6f327212ef96	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	112:6f327212ef96	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	112:6f327212ef96	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	112:6f327212ef96	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	112:6f327212ef96	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	112:6f327212ef96	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	112:6f327212ef96	35	*
Kojto	112:6f327212ef96	36	******************************************************************************
Kojto	112:6f327212ef96	37	*/
Kojto	112:6f327212ef96	38
Kojto	112:6f327212ef96	39	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	112:6f327212ef96	40	#ifndef __STM32_HAL_LEGACY
Kojto	112:6f327212ef96	41	#define __STM32_HAL_LEGACY
Kojto	112:6f327212ef96	42
Kojto	112:6f327212ef96	43	#ifdef __cplusplus
Kojto	112:6f327212ef96	44	extern "C" {
Kojto	112:6f327212ef96	45	#endif
Kojto	112:6f327212ef96	46
Kojto	112:6f327212ef96	47	/* Includes ------------------------------------------------------------------*/
Kojto	112:6f327212ef96	48	/* Exported types ------------------------------------------------------------*/
Kojto	112:6f327212ef96	49	/* Exported constants --------------------------------------------------------*/
Kojto	112:6f327212ef96	50
Kojto	112:6f327212ef96	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	52	* @{
Kojto	112:6f327212ef96	53	*/
Kojto	112:6f327212ef96	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto	112:6f327212ef96	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto	112:6f327212ef96	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto	112:6f327212ef96	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto	112:6f327212ef96	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto	112:6f327212ef96	59
Kojto	112:6f327212ef96	60	/**
Kojto	112:6f327212ef96	61	* @}
Kojto	112:6f327212ef96	62	*/
Kojto	112:6f327212ef96	63
Kojto	112:6f327212ef96	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	65	* @{
Kojto	112:6f327212ef96	66	*/
Kojto	112:6f327212ef96	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto	112:6f327212ef96	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto	112:6f327212ef96	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto	112:6f327212ef96	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto	112:6f327212ef96	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto	112:6f327212ef96	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto	112:6f327212ef96	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto	112:6f327212ef96	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto	112:6f327212ef96	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto	112:6f327212ef96	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto	112:6f327212ef96	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto	112:6f327212ef96	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto	112:6f327212ef96	79	#define AWD_EVENT ADC_AWD_EVENT
Kojto	112:6f327212ef96	80	#define AWD1_EVENT ADC_AWD1_EVENT
Kojto	112:6f327212ef96	81	#define AWD2_EVENT ADC_AWD2_EVENT
Kojto	112:6f327212ef96	82	#define AWD3_EVENT ADC_AWD3_EVENT
Kojto	112:6f327212ef96	83	#define OVR_EVENT ADC_OVR_EVENT
Kojto	112:6f327212ef96	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto	112:6f327212ef96	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto	112:6f327212ef96	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto	112:6f327212ef96	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto	112:6f327212ef96	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto	112:6f327212ef96	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto	112:6f327212ef96	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto	112:6f327212ef96	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto	112:6f327212ef96	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto	112:6f327212ef96	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
Kojto	112:6f327212ef96	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
Kojto	112:6f327212ef96	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto	112:6f327212ef96	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto	112:6f327212ef96	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto	112:6f327212ef96	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto	112:6f327212ef96	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto	112:6f327212ef96	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto	112:6f327212ef96	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto	112:6f327212ef96	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto	112:6f327212ef96	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto	112:6f327212ef96	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto	122:f9eeca106725	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto	122:f9eeca106725	106	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
Kojto	122:f9eeca106725	107
Kojto	122:f9eeca106725	108	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
Kojto	122:f9eeca106725	109	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
Kojto	122:f9eeca106725	110	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
Kojto	122:f9eeca106725	111	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
Kojto	122:f9eeca106725	112	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
Kojto	122:f9eeca106725	113	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
Kojto	122:f9eeca106725	114	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
Kojto	112:6f327212ef96	115	/**
Kojto	112:6f327212ef96	116	* @}
Kojto	112:6f327212ef96	117	*/
Kojto	112:6f327212ef96	118
Kojto	112:6f327212ef96	119	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	120	* @{
Kojto	112:6f327212ef96	121	*/
Kojto	112:6f327212ef96	122
Kojto	112:6f327212ef96	123	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto	112:6f327212ef96	124
Kojto	112:6f327212ef96	125	/**
Kojto	112:6f327212ef96	126	* @}
Kojto	112:6f327212ef96	127	*/
Kojto	112:6f327212ef96	128
Kojto	112:6f327212ef96	129	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	130	* @{
Kojto	112:6f327212ef96	131	*/
Kojto	122:f9eeca106725	132	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto	122:f9eeca106725	133	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto	122:f9eeca106725	134	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto	122:f9eeca106725	135	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto	122:f9eeca106725	136	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
Kojto	122:f9eeca106725	137	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
Kojto	122:f9eeca106725	138	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
Kojto	122:f9eeca106725	139	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
Kojto	122:f9eeca106725	140	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
Kojto	122:f9eeca106725	141	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
Kojto	122:f9eeca106725	142	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	122:f9eeca106725	143	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
Kojto	122:f9eeca106725	144	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
Kojto	122:f9eeca106725	145	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	122:f9eeca106725	146
Kojto	122:f9eeca106725	147	#if defined(STM32L0) \|\| defined(STM32L4)
Kojto	122:f9eeca106725	148	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Kojto	122:f9eeca106725	149
Kojto	122:f9eeca106725	150	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
Kojto	122:f9eeca106725	151	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
Kojto	122:f9eeca106725	152	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
Kojto	122:f9eeca106725	153
Kojto	122:f9eeca106725	154	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
Kojto	122:f9eeca106725	155	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
Kojto	122:f9eeca106725	156	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
Kojto	122:f9eeca106725	157	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
Kojto	122:f9eeca106725	158	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
Kojto	122:f9eeca106725	159	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
Kojto	122:f9eeca106725	160	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
Kojto	122:f9eeca106725	161	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
Kojto	122:f9eeca106725	162	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
Kojto	122:f9eeca106725	163	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
Kojto	122:f9eeca106725	164	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
Kojto	122:f9eeca106725	165	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
Kojto	122:f9eeca106725	166	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
Kojto	122:f9eeca106725	167
Kojto	122:f9eeca106725	168	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
Kojto	122:f9eeca106725	169	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
Kojto	112:6f327212ef96	170
Kojto	122:f9eeca106725	171	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
Kojto	122:f9eeca106725	172	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
Kojto	122:f9eeca106725	173	#if defined(COMP_CSR_LOCK)
Kojto	122:f9eeca106725	174	#define COMP_FLAG_LOCK COMP_CSR_LOCK
Kojto	122:f9eeca106725	175	#elif defined(COMP_CSR_COMP1LOCK)
Kojto	122:f9eeca106725	176	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
Kojto	122:f9eeca106725	177	#elif defined(COMP_CSR_COMPxLOCK)
Kojto	122:f9eeca106725	178	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
Kojto	122:f9eeca106725	179	#endif
Kojto	122:f9eeca106725	180
Kojto	122:f9eeca106725	181	#if defined(STM32L4)
Kojto	122:f9eeca106725	182	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
Kojto	122:f9eeca106725	183	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
Kojto	122:f9eeca106725	184	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
Kojto	122:f9eeca106725	185	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
Kojto	122:f9eeca106725	186	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
Kojto	122:f9eeca106725	187	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
Kojto	122:f9eeca106725	188	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
Kojto	122:f9eeca106725	189	#endif
Kojto	122:f9eeca106725	190
Kojto	122:f9eeca106725	191	#if defined(STM32L0)
Kojto	122:f9eeca106725	192	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto	122:f9eeca106725	193	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
Kojto	122:f9eeca106725	194	#else
Kojto	122:f9eeca106725	195	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
Kojto	122:f9eeca106725	196	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto	122:f9eeca106725	197	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
Kojto	122:f9eeca106725	198	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
Kojto	122:f9eeca106725	199	#endif
Kojto	122:f9eeca106725	200
Kojto	122:f9eeca106725	201	#endif
Kojto	122:f9eeca106725	202	/**
Kojto	122:f9eeca106725	203	* @}
Kojto	122:f9eeca106725	204	*/
Kojto	122:f9eeca106725	205
Kojto	122:f9eeca106725	206	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
Kojto	122:f9eeca106725	207	* @{
Kojto	122:f9eeca106725	208	*/
Kojto	122:f9eeca106725	209	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
Kojto	112:6f327212ef96	210	/**
Kojto	112:6f327212ef96	211	* @}
Kojto	112:6f327212ef96	212	*/
Kojto	112:6f327212ef96	213
Kojto	112:6f327212ef96	214	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	215	* @{
Kojto	112:6f327212ef96	216	*/
Kojto	112:6f327212ef96	217
Kojto	112:6f327212ef96	218	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto	112:6f327212ef96	219	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto	112:6f327212ef96	220
Kojto	112:6f327212ef96	221	/**
Kojto	112:6f327212ef96	222	* @}
Kojto	112:6f327212ef96	223	*/
Kojto	112:6f327212ef96	224
Kojto	112:6f327212ef96	225	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	226	* @{
Kojto	112:6f327212ef96	227	*/
Kojto	112:6f327212ef96	228
Kojto	112:6f327212ef96	229	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto	112:6f327212ef96	230	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto	112:6f327212ef96	231	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto	122:f9eeca106725	232	#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
Kojto	112:6f327212ef96	233	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto	112:6f327212ef96	234	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto	112:6f327212ef96	235	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto	112:6f327212ef96	236	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto	112:6f327212ef96	237	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto	112:6f327212ef96	238
Kojto	112:6f327212ef96	239	/**
Kojto	112:6f327212ef96	240	* @}
Kojto	112:6f327212ef96	241	*/
Kojto	112:6f327212ef96	242
Kojto	112:6f327212ef96	243	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	244	* @{
Kojto	112:6f327212ef96	245	*/
Kojto	112:6f327212ef96	246	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto	112:6f327212ef96	247	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto	112:6f327212ef96	248	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto	112:6f327212ef96	249	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto	112:6f327212ef96	250	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto	112:6f327212ef96	251	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto	112:6f327212ef96	252	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto	112:6f327212ef96	253	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto	112:6f327212ef96	254	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto	112:6f327212ef96	255	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto	112:6f327212ef96	256	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto	112:6f327212ef96	257	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto	112:6f327212ef96	258	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto	112:6f327212ef96	259	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto	112:6f327212ef96	260	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto	112:6f327212ef96	261
Kojto	112:6f327212ef96	262	#define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto	112:6f327212ef96	263	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto	112:6f327212ef96	264	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto	112:6f327212ef96	265
Kojto	112:6f327212ef96	266
Kojto	112:6f327212ef96	267
Kojto	112:6f327212ef96	268	/**
Kojto	112:6f327212ef96	269	* @}
Kojto	112:6f327212ef96	270	*/
Kojto	112:6f327212ef96	271
Kojto	112:6f327212ef96	272	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	273	* @{
Kojto	112:6f327212ef96	274	*/
Kojto	112:6f327212ef96	275
Kojto	112:6f327212ef96	276	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto	112:6f327212ef96	277	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	112:6f327212ef96	278	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto	112:6f327212ef96	279	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto	112:6f327212ef96	280	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto	112:6f327212ef96	281	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto	112:6f327212ef96	282	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto	112:6f327212ef96	283	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto	112:6f327212ef96	284	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto	112:6f327212ef96	285	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto	112:6f327212ef96	286	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto	112:6f327212ef96	287	#define OBEX_PCROP OPTIONBYTE_PCROP
Kojto	112:6f327212ef96	288	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto	112:6f327212ef96	289	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto	112:6f327212ef96	290	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto	112:6f327212ef96	291	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto	112:6f327212ef96	292	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto	112:6f327212ef96	293	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto	112:6f327212ef96	294	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto	112:6f327212ef96	295	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto	112:6f327212ef96	296	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto	112:6f327212ef96	297	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto	112:6f327212ef96	298	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto	112:6f327212ef96	299	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto	112:6f327212ef96	300	#define PAGESIZE FLASH_PAGE_SIZE
Kojto	112:6f327212ef96	301	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto	112:6f327212ef96	302	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	112:6f327212ef96	303	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto	112:6f327212ef96	304	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto	112:6f327212ef96	305	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto	112:6f327212ef96	306	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto	112:6f327212ef96	307	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto	112:6f327212ef96	308	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto	112:6f327212ef96	309	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto	112:6f327212ef96	310	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto	112:6f327212ef96	311	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto	112:6f327212ef96	312	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto	112:6f327212ef96	313	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto	112:6f327212ef96	314	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto	112:6f327212ef96	315	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto	112:6f327212ef96	316	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto	112:6f327212ef96	317	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto	112:6f327212ef96	318	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto	112:6f327212ef96	319	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto	112:6f327212ef96	320	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto	112:6f327212ef96	321	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto	112:6f327212ef96	322	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto	112:6f327212ef96	323	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto	112:6f327212ef96	324	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto	112:6f327212ef96	325	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto	112:6f327212ef96	326	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto	112:6f327212ef96	327	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto	112:6f327212ef96	328	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto	112:6f327212ef96	329	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto	112:6f327212ef96	330	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto	112:6f327212ef96	331	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto	112:6f327212ef96	332	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto	112:6f327212ef96	333	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto	112:6f327212ef96	334	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto	112:6f327212ef96	335	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto	112:6f327212ef96	336	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto	112:6f327212ef96	337	#define OB_WDG_SW OB_IWDG_SW
Kojto	112:6f327212ef96	338	#define OB_WDG_HW OB_IWDG_HW
Kojto	112:6f327212ef96	339	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
Kojto	112:6f327212ef96	340	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
Kojto	112:6f327212ef96	341	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
Kojto	112:6f327212ef96	342	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
Kojto	112:6f327212ef96	343	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
Kojto	112:6f327212ef96	344	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
Kojto	112:6f327212ef96	345	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
Kojto	112:6f327212ef96	346	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
Kojto	112:6f327212ef96	347	/**
Kojto	112:6f327212ef96	348	* @}
Kojto	112:6f327212ef96	349	*/
Kojto	112:6f327212ef96	350
Kojto	112:6f327212ef96	351	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	352	* @{
Kojto	112:6f327212ef96	353	*/
Kojto	112:6f327212ef96	354
Kojto	112:6f327212ef96	355	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
Kojto	112:6f327212ef96	356	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
Kojto	112:6f327212ef96	357	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto	112:6f327212ef96	358	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto	112:6f327212ef96	359	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto	112:6f327212ef96	360	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto	112:6f327212ef96	361	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto	112:6f327212ef96	362	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto	112:6f327212ef96	363	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto	112:6f327212ef96	364	/**
Kojto	112:6f327212ef96	365	* @}
Kojto	112:6f327212ef96	366	*/
Kojto	112:6f327212ef96	367
Kojto	112:6f327212ef96	368
Kojto	112:6f327212ef96	369	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto	112:6f327212ef96	370	* @{
Kojto	112:6f327212ef96	371	*/
Kojto	112:6f327212ef96	372	#if defined(STM32L4) \|\| defined(STM32F7)
Kojto	112:6f327212ef96	373	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto	112:6f327212ef96	374	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto	112:6f327212ef96	375	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto	112:6f327212ef96	376	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto	112:6f327212ef96	377	#else
Kojto	112:6f327212ef96	378	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto	112:6f327212ef96	379	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto	112:6f327212ef96	380	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto	112:6f327212ef96	381	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto	112:6f327212ef96	382	#endif
Kojto	112:6f327212ef96	383	/**
Kojto	112:6f327212ef96	384	* @}
Kojto	112:6f327212ef96	385	*/
Kojto	112:6f327212ef96	386
Kojto	112:6f327212ef96	387	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	388	* @{
Kojto	112:6f327212ef96	389	*/
Kojto	112:6f327212ef96	390
Kojto	112:6f327212ef96	391	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto	112:6f327212ef96	392	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto	112:6f327212ef96	393	/**
Kojto	112:6f327212ef96	394	* @}
Kojto	112:6f327212ef96	395	*/
Kojto	112:6f327212ef96	396
Kojto	112:6f327212ef96	397	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	398	* @{
Kojto	112:6f327212ef96	399	*/
Kojto	112:6f327212ef96	400	#define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto	112:6f327212ef96	401	#define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto	112:6f327212ef96	402
Kojto	112:6f327212ef96	403	#if defined(STM32F4)
Kojto	112:6f327212ef96	404	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto	112:6f327212ef96	405	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto	112:6f327212ef96	406	#endif
Kojto	112:6f327212ef96	407
Kojto	112:6f327212ef96	408	#if defined(STM32F7)
Kojto	112:6f327212ef96	409	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto	112:6f327212ef96	410	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto	112:6f327212ef96	411	#endif
Kojto	112:6f327212ef96	412
Kojto	112:6f327212ef96	413	#if defined(STM32L4)
Kojto	112:6f327212ef96	414	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto	112:6f327212ef96	415	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto	112:6f327212ef96	416	#endif
Kojto	112:6f327212ef96	417
Kojto	112:6f327212ef96	418	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto	112:6f327212ef96	419	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto	112:6f327212ef96	420	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto	112:6f327212ef96	421
Kojto	122:f9eeca106725	422	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
Kojto	112:6f327212ef96	423	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto	112:6f327212ef96	424	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto	112:6f327212ef96	425	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
Kojto	112:6f327212ef96	426	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto	122:f9eeca106725	427	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
Kojto	112:6f327212ef96	428
Kojto	122:f9eeca106725	429	#if defined(STM32L1)
Kojto	122:f9eeca106725	430	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
Kojto	122:f9eeca106725	431	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
Kojto	122:f9eeca106725	432	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
Kojto	122:f9eeca106725	433	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto	122:f9eeca106725	434	#endif /* STM32L1 */
Kojto	122:f9eeca106725	435
Kojto	122:f9eeca106725	436	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
Kojto	122:f9eeca106725	437	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto	122:f9eeca106725	438	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto	122:f9eeca106725	439	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
Kojto	122:f9eeca106725	440	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
Kojto	122:f9eeca106725	441
Kojto	122:f9eeca106725	442	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
Kojto	112:6f327212ef96	443	/**
Kojto	112:6f327212ef96	444	* @}
Kojto	112:6f327212ef96	445	*/
Kojto	112:6f327212ef96	446
Kojto	112:6f327212ef96	447	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	448	* @{
Kojto	112:6f327212ef96	449	*/
Kojto	112:6f327212ef96	450	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto	112:6f327212ef96	451	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto	112:6f327212ef96	452	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto	112:6f327212ef96	453	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto	112:6f327212ef96	454	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto	112:6f327212ef96	455	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto	112:6f327212ef96	456	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto	112:6f327212ef96	457	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto	112:6f327212ef96	458	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto	122:f9eeca106725	459
Kojto	122:f9eeca106725	460	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
Kojto	122:f9eeca106725	461	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
Kojto	122:f9eeca106725	462	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
Kojto	122:f9eeca106725	463	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
Kojto	122:f9eeca106725	464	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
Kojto	122:f9eeca106725	465	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
Kojto	122:f9eeca106725	466	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
Kojto	122:f9eeca106725	467	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
Kojto	112:6f327212ef96	468	/**
Kojto	112:6f327212ef96	469	* @}
Kojto	112:6f327212ef96	470	*/
Kojto	112:6f327212ef96	471
Kojto	112:6f327212ef96	472	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	473	* @{
Kojto	112:6f327212ef96	474	*/
Kojto	112:6f327212ef96	475	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto	112:6f327212ef96	476	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto	112:6f327212ef96	477	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto	112:6f327212ef96	478	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto	112:6f327212ef96	479	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto	112:6f327212ef96	480	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto	112:6f327212ef96	481	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto	112:6f327212ef96	482	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto	122:f9eeca106725	483	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
Kojto	122:f9eeca106725	484	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto	122:f9eeca106725	485	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto	122:f9eeca106725	486	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto	122:f9eeca106725	487	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto	122:f9eeca106725	488	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto	122:f9eeca106725	489	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto	122:f9eeca106725	490	#endif
Kojto	112:6f327212ef96	491	/**
Kojto	112:6f327212ef96	492	* @}
Kojto	112:6f327212ef96	493	*/
Kojto	112:6f327212ef96	494
Kojto	112:6f327212ef96	495	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	496	* @{
Kojto	112:6f327212ef96	497	*/
Kojto	112:6f327212ef96	498	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	499	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	500
Kojto	112:6f327212ef96	501	/**
Kojto	112:6f327212ef96	502	* @}
Kojto	112:6f327212ef96	503	*/
Kojto	112:6f327212ef96	504
Kojto	112:6f327212ef96	505	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	506	* @{
Kojto	112:6f327212ef96	507	*/
Kojto	112:6f327212ef96	508	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto	112:6f327212ef96	509	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto	112:6f327212ef96	510	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto	112:6f327212ef96	511	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto	112:6f327212ef96	512	/**
Kojto	112:6f327212ef96	513	* @}
Kojto	112:6f327212ef96	514	*/
Kojto	112:6f327212ef96	515
Kojto	112:6f327212ef96	516	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	517	* @{
Kojto	112:6f327212ef96	518	*/
Kojto	112:6f327212ef96	519
Kojto	112:6f327212ef96	520	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto	112:6f327212ef96	521	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto	112:6f327212ef96	522	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto	112:6f327212ef96	523	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto	112:6f327212ef96	524
Kojto	112:6f327212ef96	525	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto	112:6f327212ef96	526	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto	112:6f327212ef96	527	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto	112:6f327212ef96	528
Kojto	112:6f327212ef96	529	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
Kojto	112:6f327212ef96	530	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto	112:6f327212ef96	531	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto	112:6f327212ef96	532	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto	112:6f327212ef96	533
Kojto	112:6f327212ef96	534	/* The following 3 definition have also been present in a temporary version of lptim.h */
Kojto	112:6f327212ef96	535	/* They need to be renamed also to the right name, just in case */
Kojto	112:6f327212ef96	536	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto	112:6f327212ef96	537	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto	112:6f327212ef96	538	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto	112:6f327212ef96	539
Kojto	112:6f327212ef96	540	/**
Kojto	112:6f327212ef96	541	* @}
Kojto	112:6f327212ef96	542	*/
Kojto	112:6f327212ef96	543
Kojto	112:6f327212ef96	544	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	545	* @{
Kojto	112:6f327212ef96	546	*/
Kojto	122:f9eeca106725	547	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
Kojto	122:f9eeca106725	548	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
Kojto	122:f9eeca106725	549	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
Kojto	122:f9eeca106725	550	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
Kojto	122:f9eeca106725	551
Kojto	112:6f327212ef96	552	#define NAND_AddressTypedef NAND_AddressTypeDef
Kojto	112:6f327212ef96	553
Kojto	112:6f327212ef96	554	#define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto	112:6f327212ef96	555	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto	112:6f327212ef96	556	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto	112:6f327212ef96	557	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto	112:6f327212ef96	558	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto	112:6f327212ef96	559	/**
Kojto	112:6f327212ef96	560	* @}
Kojto	112:6f327212ef96	561	*/
Kojto	112:6f327212ef96	562
Kojto	112:6f327212ef96	563	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	564	* @{
Kojto	112:6f327212ef96	565	*/
Kojto	112:6f327212ef96	566	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto	112:6f327212ef96	567	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto	112:6f327212ef96	568	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto	112:6f327212ef96	569	#define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto	112:6f327212ef96	570	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto	112:6f327212ef96	571
Kojto	112:6f327212ef96	572	#define __NOR_WRITE NOR_WRITE
Kojto	112:6f327212ef96	573	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto	112:6f327212ef96	574	/**
Kojto	112:6f327212ef96	575	* @}
Kojto	112:6f327212ef96	576	*/
Kojto	112:6f327212ef96	577
Kojto	112:6f327212ef96	578	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	579	* @{
Kojto	112:6f327212ef96	580	*/
Kojto	112:6f327212ef96	581
Kojto	112:6f327212ef96	582	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto	112:6f327212ef96	583	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto	112:6f327212ef96	584	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto	112:6f327212ef96	585	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto	112:6f327212ef96	586
Kojto	112:6f327212ef96	587	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto	112:6f327212ef96	588	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto	112:6f327212ef96	589	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto	112:6f327212ef96	590	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto	112:6f327212ef96	591
Kojto	112:6f327212ef96	592	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	112:6f327212ef96	593	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	112:6f327212ef96	594
Kojto	112:6f327212ef96	595	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	112:6f327212ef96	596	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	112:6f327212ef96	597
Kojto	112:6f327212ef96	598	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto	112:6f327212ef96	599	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	112:6f327212ef96	600
Kojto	112:6f327212ef96	601	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	112:6f327212ef96	602
Kojto	112:6f327212ef96	603	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto	112:6f327212ef96	604	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto	112:6f327212ef96	605	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto	112:6f327212ef96	606
Kojto	112:6f327212ef96	607	/**
Kojto	112:6f327212ef96	608	* @}
Kojto	112:6f327212ef96	609	*/
Kojto	112:6f327212ef96	610
Kojto	112:6f327212ef96	611	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	612	* @{
Kojto	112:6f327212ef96	613	*/
Kojto	112:6f327212ef96	614	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto	122:f9eeca106725	615	#if defined(STM32F7)
Kojto	122:f9eeca106725	616	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
Kojto	122:f9eeca106725	617	#endif
Kojto	112:6f327212ef96	618	/**
Kojto	112:6f327212ef96	619	* @}
Kojto	112:6f327212ef96	620	*/
Kojto	112:6f327212ef96	621
Kojto	112:6f327212ef96	622	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	623	* @{
Kojto	112:6f327212ef96	624	*/
Kojto	112:6f327212ef96	625
Kojto	112:6f327212ef96	626	/* Compact Flash-ATA registers description */
Kojto	112:6f327212ef96	627	#define CF_DATA ATA_DATA
Kojto	112:6f327212ef96	628	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto	112:6f327212ef96	629	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto	112:6f327212ef96	630	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto	112:6f327212ef96	631	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto	112:6f327212ef96	632	#define CF_CARD_HEAD ATA_CARD_HEAD
Kojto	112:6f327212ef96	633	#define CF_STATUS_CMD ATA_STATUS_CMD
Kojto	112:6f327212ef96	634	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto	112:6f327212ef96	635	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto	112:6f327212ef96	636
Kojto	112:6f327212ef96	637	/* Compact Flash-ATA commands */
Kojto	112:6f327212ef96	638	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto	112:6f327212ef96	639	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto	112:6f327212ef96	640	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto	112:6f327212ef96	641	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto	112:6f327212ef96	642
Kojto	112:6f327212ef96	643	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto	112:6f327212ef96	644	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto	112:6f327212ef96	645	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto	112:6f327212ef96	646	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto	112:6f327212ef96	647	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto	112:6f327212ef96	648	/**
Kojto	112:6f327212ef96	649	* @}
Kojto	112:6f327212ef96	650	*/
Kojto	112:6f327212ef96	651
Kojto	112:6f327212ef96	652	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	653	* @{
Kojto	112:6f327212ef96	654	*/
Kojto	112:6f327212ef96	655
Kojto	112:6f327212ef96	656	#define FORMAT_BIN RTC_FORMAT_BIN
Kojto	112:6f327212ef96	657	#define FORMAT_BCD RTC_FORMAT_BCD
Kojto	112:6f327212ef96	658
Kojto	112:6f327212ef96	659	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto	112:6f327212ef96	660	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	112:6f327212ef96	661	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	112:6f327212ef96	662	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	112:6f327212ef96	663	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	112:6f327212ef96	664
Kojto	112:6f327212ef96	665	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	112:6f327212ef96	666	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	112:6f327212ef96	667	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	112:6f327212ef96	668	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	112:6f327212ef96	669	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	112:6f327212ef96	670	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	112:6f327212ef96	671	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	112:6f327212ef96	672	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	112:6f327212ef96	673
Kojto	112:6f327212ef96	674	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto	112:6f327212ef96	675	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Kojto	112:6f327212ef96	676	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Kojto	112:6f327212ef96	677	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Kojto	112:6f327212ef96	678
Kojto	112:6f327212ef96	679	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto	112:6f327212ef96	680	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto	112:6f327212ef96	681	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Kojto	112:6f327212ef96	682
Kojto	112:6f327212ef96	683	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Kojto	112:6f327212ef96	684	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Kojto	112:6f327212ef96	685	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
Kojto	112:6f327212ef96	686
Kojto	112:6f327212ef96	687	/**
Kojto	112:6f327212ef96	688	* @}
Kojto	112:6f327212ef96	689	*/
Kojto	112:6f327212ef96	690
Kojto	112:6f327212ef96	691
Kojto	112:6f327212ef96	692	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	693	* @{
Kojto	112:6f327212ef96	694	*/
Kojto	112:6f327212ef96	695	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto	112:6f327212ef96	696	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto	112:6f327212ef96	697
Kojto	112:6f327212ef96	698	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	699	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	700	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	701	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	702
Kojto	112:6f327212ef96	703	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto	112:6f327212ef96	704	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto	112:6f327212ef96	705
Kojto	112:6f327212ef96	706	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto	112:6f327212ef96	707	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto	112:6f327212ef96	708	/**
Kojto	112:6f327212ef96	709	* @}
Kojto	112:6f327212ef96	710	*/
Kojto	112:6f327212ef96	711
Kojto	112:6f327212ef96	712
Kojto	122:f9eeca106725	713	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	714	* @{
Kojto	112:6f327212ef96	715	*/
Kojto	112:6f327212ef96	716	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto	112:6f327212ef96	717	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto	112:6f327212ef96	718	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto	112:6f327212ef96	719	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto	112:6f327212ef96	720	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto	112:6f327212ef96	721	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto	112:6f327212ef96	722	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto	112:6f327212ef96	723	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto	112:6f327212ef96	724	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto	112:6f327212ef96	725	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto	112:6f327212ef96	726	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto	112:6f327212ef96	727	/**
Kojto	112:6f327212ef96	728	* @}
Kojto	112:6f327212ef96	729	*/
Kojto	112:6f327212ef96	730
Kojto	122:f9eeca106725	731	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	732	* @{
Kojto	112:6f327212ef96	733	*/
Kojto	112:6f327212ef96	734	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto	112:6f327212ef96	735	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto	112:6f327212ef96	736
Kojto	112:6f327212ef96	737	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto	112:6f327212ef96	738	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto	112:6f327212ef96	739
Kojto	112:6f327212ef96	740	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto	112:6f327212ef96	741	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto	112:6f327212ef96	742
Kojto	112:6f327212ef96	743	/**
Kojto	112:6f327212ef96	744	* @}
Kojto	112:6f327212ef96	745	*/
Kojto	112:6f327212ef96	746
Kojto	112:6f327212ef96	747	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	748	* @{
Kojto	112:6f327212ef96	749	*/
Kojto	112:6f327212ef96	750	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto	112:6f327212ef96	751	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto	112:6f327212ef96	752
Kojto	112:6f327212ef96	753	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto	112:6f327212ef96	754	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto	112:6f327212ef96	755	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto	112:6f327212ef96	756	#define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto	112:6f327212ef96	757	#define TIM_DMABase_SR TIM_DMABASE_SR
Kojto	112:6f327212ef96	758	#define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto	112:6f327212ef96	759	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto	112:6f327212ef96	760	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto	112:6f327212ef96	761	#define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto	112:6f327212ef96	762	#define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto	112:6f327212ef96	763	#define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto	112:6f327212ef96	764	#define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto	112:6f327212ef96	765	#define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto	112:6f327212ef96	766	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto	112:6f327212ef96	767	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto	112:6f327212ef96	768	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto	112:6f327212ef96	769	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto	112:6f327212ef96	770	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto	112:6f327212ef96	771	#define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto	112:6f327212ef96	772	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto	112:6f327212ef96	773	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto	112:6f327212ef96	774	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto	112:6f327212ef96	775	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto	112:6f327212ef96	776	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto	112:6f327212ef96	777	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto	112:6f327212ef96	778	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto	112:6f327212ef96	779	#define TIM_DMABase_OR TIM_DMABASE_OR
Kojto	112:6f327212ef96	780
Kojto	112:6f327212ef96	781	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto	112:6f327212ef96	782	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto	112:6f327212ef96	783	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto	112:6f327212ef96	784	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto	112:6f327212ef96	785	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto	112:6f327212ef96	786	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto	112:6f327212ef96	787	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto	112:6f327212ef96	788	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto	112:6f327212ef96	789	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto	112:6f327212ef96	790
Kojto	112:6f327212ef96	791	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto	112:6f327212ef96	792	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto	112:6f327212ef96	793	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto	112:6f327212ef96	794	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto	112:6f327212ef96	795	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto	112:6f327212ef96	796	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto	112:6f327212ef96	797	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto	112:6f327212ef96	798	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto	112:6f327212ef96	799	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto	112:6f327212ef96	800	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto	112:6f327212ef96	801	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto	112:6f327212ef96	802	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto	112:6f327212ef96	803	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto	112:6f327212ef96	804	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto	112:6f327212ef96	805	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto	112:6f327212ef96	806	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto	112:6f327212ef96	807	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto	112:6f327212ef96	808	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto	112:6f327212ef96	809
Kojto	112:6f327212ef96	810	/**
Kojto	112:6f327212ef96	811	* @}
Kojto	112:6f327212ef96	812	*/
Kojto	112:6f327212ef96	813
Kojto	112:6f327212ef96	814	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	815	* @{
Kojto	112:6f327212ef96	816	*/
Kojto	112:6f327212ef96	817	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto	112:6f327212ef96	818	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto	112:6f327212ef96	819	/**
Kojto	112:6f327212ef96	820	* @}
Kojto	112:6f327212ef96	821	*/
Kojto	112:6f327212ef96	822
Kojto	112:6f327212ef96	823	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	824	* @{
Kojto	112:6f327212ef96	825	*/
Kojto	112:6f327212ef96	826	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	827	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	828	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	829	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	830
Kojto	112:6f327212ef96	831	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto	112:6f327212ef96	832	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto	112:6f327212ef96	833
Kojto	112:6f327212ef96	834	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto	112:6f327212ef96	835	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto	112:6f327212ef96	836	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto	112:6f327212ef96	837	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto	112:6f327212ef96	838
Kojto	112:6f327212ef96	839	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto	112:6f327212ef96	840	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto	112:6f327212ef96	841	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto	112:6f327212ef96	842	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto	112:6f327212ef96	843
Kojto	112:6f327212ef96	844	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto	112:6f327212ef96	845	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto	112:6f327212ef96	846
Kojto	112:6f327212ef96	847	/**
Kojto	112:6f327212ef96	848	* @}
Kojto	112:6f327212ef96	849	*/
Kojto	112:6f327212ef96	850
Kojto	112:6f327212ef96	851
Kojto	112:6f327212ef96	852	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	853	* @{
Kojto	112:6f327212ef96	854	*/
Kojto	112:6f327212ef96	855
Kojto	112:6f327212ef96	856	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto	112:6f327212ef96	857	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto	112:6f327212ef96	858
Kojto	112:6f327212ef96	859	#define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto	112:6f327212ef96	860	#define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto	112:6f327212ef96	861	/**
Kojto	112:6f327212ef96	862	* @}
Kojto	112:6f327212ef96	863	*/
Kojto	112:6f327212ef96	864
Kojto	112:6f327212ef96	865	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	866	* @{
Kojto	112:6f327212ef96	867	*/
Kojto	112:6f327212ef96	868	#define CFR_BASE WWDG_CFR_BASE
Kojto	112:6f327212ef96	869
Kojto	112:6f327212ef96	870	/**
Kojto	112:6f327212ef96	871	* @}
Kojto	112:6f327212ef96	872	*/
Kojto	112:6f327212ef96	873
Kojto	112:6f327212ef96	874	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	875	* @{
Kojto	112:6f327212ef96	876	*/
Kojto	112:6f327212ef96	877	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto	112:6f327212ef96	878	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto	112:6f327212ef96	879	#define CAN_IT_RQCP0 CAN_IT_TME
Kojto	112:6f327212ef96	880	#define CAN_IT_RQCP1 CAN_IT_TME
Kojto	112:6f327212ef96	881	#define CAN_IT_RQCP2 CAN_IT_TME
Kojto	112:6f327212ef96	882	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	112:6f327212ef96	883	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	122:f9eeca106725	884	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
Kojto	122:f9eeca106725	885	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
Kojto	122:f9eeca106725	886	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
Kojto	112:6f327212ef96	887
Kojto	112:6f327212ef96	888	/**
Kojto	112:6f327212ef96	889	* @}
Kojto	112:6f327212ef96	890	*/
Kojto	112:6f327212ef96	891
Kojto	112:6f327212ef96	892	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	893	* @{
Kojto	112:6f327212ef96	894	*/
Kojto	112:6f327212ef96	895
Kojto	112:6f327212ef96	896	#define VLAN_TAG ETH_VLAN_TAG
Kojto	112:6f327212ef96	897	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto	112:6f327212ef96	898	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto	112:6f327212ef96	899	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto	112:6f327212ef96	900	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto	112:6f327212ef96	901	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto	112:6f327212ef96	902	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto	112:6f327212ef96	903	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto	112:6f327212ef96	904
Kojto	122:f9eeca106725	905	#define ETH_MMCCR ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	906	#define ETH_MMCRIR ((uint32_t)0x00000104U)
Kojto	122:f9eeca106725	907	#define ETH_MMCTIR ((uint32_t)0x00000108U)
Kojto	122:f9eeca106725	908	#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
Kojto	122:f9eeca106725	909	#define ETH_MMCTIMR ((uint32_t)0x00000110U)
Kojto	122:f9eeca106725	910	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
Kojto	122:f9eeca106725	911	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
Kojto	122:f9eeca106725	912	#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
Kojto	122:f9eeca106725	913	#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
Kojto	122:f9eeca106725	914	#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
Kojto	122:f9eeca106725	915	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
Kojto	122:f9eeca106725	916
Kojto	122:f9eeca106725	917	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto	122:f9eeca106725	918	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto	122:f9eeca106725	919	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto	122:f9eeca106725	920	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto	122:f9eeca106725	921	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto	122:f9eeca106725	922	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto	122:f9eeca106725	923	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto	122:f9eeca106725	924	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto	122:f9eeca106725	925	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto	122:f9eeca106725	926	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto	122:f9eeca106725	927	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto	122:f9eeca106725	928	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto	122:f9eeca106725	929	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto	122:f9eeca106725	930	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto	122:f9eeca106725	931	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto	122:f9eeca106725	932	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto	122:f9eeca106725	933	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto	122:f9eeca106725	934	#if defined(STM32F1)
Kojto	122:f9eeca106725	935	#else
Kojto	122:f9eeca106725	936	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto	122:f9eeca106725	937	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto	122:f9eeca106725	938	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto	122:f9eeca106725	939	#endif
Kojto	122:f9eeca106725	940	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto	122:f9eeca106725	941	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto	122:f9eeca106725	942	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto	122:f9eeca106725	943	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto	122:f9eeca106725	944	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto	122:f9eeca106725	945	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto	122:f9eeca106725	946	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto	112:6f327212ef96	947
Kojto	112:6f327212ef96	948	/**
Kojto	112:6f327212ef96	949	* @}
Kojto	112:6f327212ef96	950	*/
Kojto	122:f9eeca106725	951
Kojto	122:f9eeca106725	952	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
Kojto	122:f9eeca106725	953	* @{
Kojto	122:f9eeca106725	954	*/
Kojto	122:f9eeca106725	955	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
Kojto	122:f9eeca106725	956	#define DCMI_IT_OVF DCMI_IT_OVR
Kojto	122:f9eeca106725	957	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
Kojto	122:f9eeca106725	958	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
Kojto	122:f9eeca106725	959
Kojto	122:f9eeca106725	960	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
Kojto	122:f9eeca106725	961	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
Kojto	122:f9eeca106725	962	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
Kojto	122:f9eeca106725	963
Kojto	122:f9eeca106725	964	/**
Kojto	122:f9eeca106725	965	* @}
Kojto	122:f9eeca106725	966	*/
Kojto	122:f9eeca106725	967
Kojto	122:f9eeca106725	968	#if defined(STM32L4xx) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
Kojto	122:f9eeca106725	969	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	970	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
Kojto	122:f9eeca106725	971	* @{
Kojto	122:f9eeca106725	972	*/
Kojto	122:f9eeca106725	973	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
Kojto	122:f9eeca106725	974	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
Kojto	122:f9eeca106725	975	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
Kojto	122:f9eeca106725	976	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
Kojto	122:f9eeca106725	977	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
Kojto	122:f9eeca106725	978
Kojto	122:f9eeca106725	979	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
Kojto	122:f9eeca106725	980	#define CM_RGB888 DMA2D_INPUT_RGB888
Kojto	122:f9eeca106725	981	#define CM_RGB565 DMA2D_INPUT_RGB565
Kojto	122:f9eeca106725	982	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
Kojto	122:f9eeca106725	983	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
Kojto	122:f9eeca106725	984	#define CM_L8 DMA2D_INPUT_L8
Kojto	122:f9eeca106725	985	#define CM_AL44 DMA2D_INPUT_AL44
Kojto	122:f9eeca106725	986	#define CM_AL88 DMA2D_INPUT_AL88
Kojto	122:f9eeca106725	987	#define CM_L4 DMA2D_INPUT_L4
Kojto	122:f9eeca106725	988	#define CM_A8 DMA2D_INPUT_A8
Kojto	122:f9eeca106725	989	#define CM_A4 DMA2D_INPUT_A4
Kojto	122:f9eeca106725	990	/**
Kojto	122:f9eeca106725	991	* @}
Kojto	122:f9eeca106725	992	*/
Kojto	122:f9eeca106725	993	#endif /* STM32L4xx \|\| STM32F7*/
Kojto	112:6f327212ef96	994
Kojto	112:6f327212ef96	995	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto	112:6f327212ef96	996	* @{
Kojto	112:6f327212ef96	997	*/
Kojto	112:6f327212ef96	998
Kojto	112:6f327212ef96	999	/**
Kojto	112:6f327212ef96	1000	* @}
Kojto	112:6f327212ef96	1001	*/
Kojto	112:6f327212ef96	1002
Kojto	112:6f327212ef96	1003	/* Exported functions --------------------------------------------------------*/
Kojto	112:6f327212ef96	1004
Kojto	112:6f327212ef96	1005	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1006	* @{
Kojto	112:6f327212ef96	1007	*/
Kojto	112:6f327212ef96	1008	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto	112:6f327212ef96	1009	/**
Kojto	112:6f327212ef96	1010	* @}
Kojto	112:6f327212ef96	1011	*/
Kojto	112:6f327212ef96	1012
Kojto	112:6f327212ef96	1013	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1014	* @{
Kojto	112:6f327212ef96	1015	*/
Kojto	122:f9eeca106725	1016	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
Kojto	122:f9eeca106725	1017	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
Kojto	112:6f327212ef96	1018	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto	112:6f327212ef96	1019	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto	112:6f327212ef96	1020	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto	112:6f327212ef96	1021	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto	112:6f327212ef96	1022
Kojto	112:6f327212ef96	1023	/HASH Algorithm Selection/
Kojto	112:6f327212ef96	1024
Kojto	112:6f327212ef96	1025	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto	112:6f327212ef96	1026	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto	112:6f327212ef96	1027	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto	112:6f327212ef96	1028	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto	112:6f327212ef96	1029
Kojto	112:6f327212ef96	1030	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto	112:6f327212ef96	1031	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto	112:6f327212ef96	1032
Kojto	112:6f327212ef96	1033	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto	112:6f327212ef96	1034	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto	112:6f327212ef96	1035	/**
Kojto	112:6f327212ef96	1036	* @}
Kojto	112:6f327212ef96	1037	*/
Kojto	112:6f327212ef96	1038
Kojto	112:6f327212ef96	1039	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1040	* @{
Kojto	112:6f327212ef96	1041	*/
Kojto	112:6f327212ef96	1042	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto	112:6f327212ef96	1043	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto	112:6f327212ef96	1044	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto	112:6f327212ef96	1045	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto	112:6f327212ef96	1046	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto	112:6f327212ef96	1047	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto	112:6f327212ef96	1048	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto	112:6f327212ef96	1049	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto	112:6f327212ef96	1050	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto	122:f9eeca106725	1051	#if defined(STM32L0)
Kojto	122:f9eeca106725	1052	#else
Kojto	112:6f327212ef96	1053	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto	122:f9eeca106725	1054	#endif
Kojto	112:6f327212ef96	1055	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto	112:6f327212ef96	1056	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto	112:6f327212ef96	1057	/**
Kojto	112:6f327212ef96	1058	* @}
Kojto	112:6f327212ef96	1059	*/
Kojto	112:6f327212ef96	1060
Kojto	112:6f327212ef96	1061	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1062	* @{
Kojto	112:6f327212ef96	1063	*/
Kojto	112:6f327212ef96	1064	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto	112:6f327212ef96	1065	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto	112:6f327212ef96	1066	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto	112:6f327212ef96	1067	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto	112:6f327212ef96	1068	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto	112:6f327212ef96	1069	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto	112:6f327212ef96	1070	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto	112:6f327212ef96	1071
Kojto	112:6f327212ef96	1072	/**
Kojto	112:6f327212ef96	1073	* @}
Kojto	112:6f327212ef96	1074	*/
Kojto	112:6f327212ef96	1075
Kojto	112:6f327212ef96	1076	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1077	* @{
Kojto	112:6f327212ef96	1078	*/
Kojto	122:f9eeca106725	1079	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto	122:f9eeca106725	1080	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto	122:f9eeca106725	1081	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
Kojto	122:f9eeca106725	1082	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
Kojto	112:6f327212ef96	1083
Kojto	112:6f327212ef96	1084	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto	112:6f327212ef96	1085	/**
Kojto	112:6f327212ef96	1086	* @}
Kojto	112:6f327212ef96	1087	*/
Kojto	112:6f327212ef96	1088
Kojto	112:6f327212ef96	1089	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto	112:6f327212ef96	1090	* @{
Kojto	112:6f327212ef96	1091	*/
Kojto	112:6f327212ef96	1092	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto	112:6f327212ef96	1093	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto	112:6f327212ef96	1094	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto	112:6f327212ef96	1095	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto	112:6f327212ef96	1096	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto	112:6f327212ef96	1097	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto	112:6f327212ef96	1098	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto	112:6f327212ef96	1099	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto	112:6f327212ef96	1100	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto	112:6f327212ef96	1101	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto	112:6f327212ef96	1102	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto	112:6f327212ef96	1103	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto	112:6f327212ef96	1104	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto	112:6f327212ef96	1105	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto	112:6f327212ef96	1106	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto	112:6f327212ef96	1107	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto	112:6f327212ef96	1108
Kojto	112:6f327212ef96	1109	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto	112:6f327212ef96	1110	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto	112:6f327212ef96	1111	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto	112:6f327212ef96	1112	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto	112:6f327212ef96	1113	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto	112:6f327212ef96	1114	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto	112:6f327212ef96	1115	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto	112:6f327212ef96	1116
Kojto	112:6f327212ef96	1117	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto	112:6f327212ef96	1118	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto	112:6f327212ef96	1119
Kojto	112:6f327212ef96	1120	#define DBP_BitNumber DBP_BIT_NUMBER
Kojto	112:6f327212ef96	1121	#define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto	112:6f327212ef96	1122	#define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto	112:6f327212ef96	1123	#define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto	112:6f327212ef96	1124	#define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto	112:6f327212ef96	1125	#define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto	112:6f327212ef96	1126	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto	112:6f327212ef96	1127	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto	112:6f327212ef96	1128	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto	112:6f327212ef96	1129	#define BRE_BitNumber BRE_BIT_NUMBER
Kojto	112:6f327212ef96	1130
Kojto	112:6f327212ef96	1131	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto	112:6f327212ef96	1132
Kojto	112:6f327212ef96	1133	/**
Kojto	112:6f327212ef96	1134	* @}
Kojto	112:6f327212ef96	1135	*/
Kojto	112:6f327212ef96	1136
Kojto	112:6f327212ef96	1137	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1138	* @{
Kojto	112:6f327212ef96	1139	*/
Kojto	112:6f327212ef96	1140	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto	112:6f327212ef96	1141	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto	112:6f327212ef96	1142	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto	112:6f327212ef96	1143	/**
Kojto	112:6f327212ef96	1144	* @}
Kojto	112:6f327212ef96	1145	*/
Kojto	112:6f327212ef96	1146
Kojto	112:6f327212ef96	1147	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1148	* @{
Kojto	112:6f327212ef96	1149	*/
Kojto	112:6f327212ef96	1150	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto	112:6f327212ef96	1151	/**
Kojto	112:6f327212ef96	1152	* @}
Kojto	112:6f327212ef96	1153	*/
Kojto	112:6f327212ef96	1154
Kojto	112:6f327212ef96	1155	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1156	* @{
Kojto	112:6f327212ef96	1157	*/
Kojto	112:6f327212ef96	1158	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto	112:6f327212ef96	1159	#define HAL_TIM_DMAError TIM_DMAError
Kojto	112:6f327212ef96	1160	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto	112:6f327212ef96	1161	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto	112:6f327212ef96	1162	/**
Kojto	112:6f327212ef96	1163	* @}
Kojto	112:6f327212ef96	1164	*/
Kojto	112:6f327212ef96	1165
Kojto	112:6f327212ef96	1166	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1167	* @{
Kojto	112:6f327212ef96	1168	*/
Kojto	112:6f327212ef96	1169	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto	112:6f327212ef96	1170	/**
Kojto	112:6f327212ef96	1171	* @}
Kojto	112:6f327212ef96	1172	*/
Kojto	112:6f327212ef96	1173
Kojto	112:6f327212ef96	1174	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1175	* @{
Kojto	112:6f327212ef96	1176	*/
Kojto	112:6f327212ef96	1177	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto	112:6f327212ef96	1178	/**
Kojto	112:6f327212ef96	1179	* @}
Kojto	112:6f327212ef96	1180	*/
Kojto	112:6f327212ef96	1181
Kojto	112:6f327212ef96	1182
Kojto	122:f9eeca106725	1183	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto	112:6f327212ef96	1184	* @{
Kojto	112:6f327212ef96	1185	*/
Kojto	112:6f327212ef96	1186
Kojto	112:6f327212ef96	1187	/**
Kojto	112:6f327212ef96	1188	* @}
Kojto	112:6f327212ef96	1189	*/
Kojto	112:6f327212ef96	1190
Kojto	112:6f327212ef96	1191	/* Exported macros ------------------------------------------------------------*/
Kojto	112:6f327212ef96	1192
Kojto	112:6f327212ef96	1193	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1194	* @{
Kojto	112:6f327212ef96	1195	*/
Kojto	112:6f327212ef96	1196	#define AES_IT_CC CRYP_IT_CC
Kojto	112:6f327212ef96	1197	#define AES_IT_ERR CRYP_IT_ERR
Kojto	112:6f327212ef96	1198	#define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto	112:6f327212ef96	1199	/**
Kojto	112:6f327212ef96	1200	* @}
Kojto	112:6f327212ef96	1201	*/
Kojto	112:6f327212ef96	1202
Kojto	112:6f327212ef96	1203	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1204	* @{
Kojto	112:6f327212ef96	1205	*/
Kojto	112:6f327212ef96	1206	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto	112:6f327212ef96	1207	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto	112:6f327212ef96	1208	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto	112:6f327212ef96	1209	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto	112:6f327212ef96	1210	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto	112:6f327212ef96	1211	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto	112:6f327212ef96	1212	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto	112:6f327212ef96	1213	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto	112:6f327212ef96	1214	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto	112:6f327212ef96	1215	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto	112:6f327212ef96	1216	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto	112:6f327212ef96	1217	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto	112:6f327212ef96	1218	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto	112:6f327212ef96	1219
Kojto	112:6f327212ef96	1220	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto	112:6f327212ef96	1221	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto	112:6f327212ef96	1222	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto	112:6f327212ef96	1223	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto	112:6f327212ef96	1224	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto	112:6f327212ef96	1225
Kojto	112:6f327212ef96	1226	/**
Kojto	112:6f327212ef96	1227	* @}
Kojto	112:6f327212ef96	1228	*/
Kojto	112:6f327212ef96	1229
Kojto	112:6f327212ef96	1230
Kojto	112:6f327212ef96	1231	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1232	* @{
Kojto	112:6f327212ef96	1233	*/
Kojto	112:6f327212ef96	1234	#define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto	112:6f327212ef96	1235	#define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto	112:6f327212ef96	1236	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto	112:6f327212ef96	1237	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto	112:6f327212ef96	1238	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	112:6f327212ef96	1239	#define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	112:6f327212ef96	1240	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto	112:6f327212ef96	1241	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto	112:6f327212ef96	1242	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto	112:6f327212ef96	1243	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto	112:6f327212ef96	1244	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto	112:6f327212ef96	1245	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto	112:6f327212ef96	1246	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto	112:6f327212ef96	1247
Kojto	112:6f327212ef96	1248	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	112:6f327212ef96	1249	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto	112:6f327212ef96	1250	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto	112:6f327212ef96	1251	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto	112:6f327212ef96	1252	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto	112:6f327212ef96	1253	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto	112:6f327212ef96	1254	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto	112:6f327212ef96	1255	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto	112:6f327212ef96	1256	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto	112:6f327212ef96	1257	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto	112:6f327212ef96	1258	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto	112:6f327212ef96	1259	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto	112:6f327212ef96	1260	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto	112:6f327212ef96	1261	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto	112:6f327212ef96	1262	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto	112:6f327212ef96	1263	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto	112:6f327212ef96	1264	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto	112:6f327212ef96	1265	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto	112:6f327212ef96	1266	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto	112:6f327212ef96	1267	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto	112:6f327212ef96	1268
Kojto	112:6f327212ef96	1269	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto	112:6f327212ef96	1270	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto	112:6f327212ef96	1271	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto	112:6f327212ef96	1272	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto	112:6f327212ef96	1273	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto	112:6f327212ef96	1274	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	112:6f327212ef96	1275	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	112:6f327212ef96	1276	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto	112:6f327212ef96	1277	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto	112:6f327212ef96	1278	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto	112:6f327212ef96	1279
Kojto	112:6f327212ef96	1280	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto	112:6f327212ef96	1281	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto	112:6f327212ef96	1282	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto	112:6f327212ef96	1283	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto	112:6f327212ef96	1284	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto	112:6f327212ef96	1285	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto	112:6f327212ef96	1286	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto	112:6f327212ef96	1287	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto	112:6f327212ef96	1288
Kojto	112:6f327212ef96	1289	#define __HAL_ADC_SQR1 ADC_SQR1
Kojto	112:6f327212ef96	1290	#define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto	112:6f327212ef96	1291	#define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto	112:6f327212ef96	1292	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto	112:6f327212ef96	1293	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto	112:6f327212ef96	1294	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto	112:6f327212ef96	1295	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto	112:6f327212ef96	1296	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto	112:6f327212ef96	1297	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto	112:6f327212ef96	1298	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto	112:6f327212ef96	1299	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto	112:6f327212ef96	1300	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	112:6f327212ef96	1301	#define __HAL_ADC_JSQR ADC_JSQR
Kojto	112:6f327212ef96	1302
Kojto	112:6f327212ef96	1303	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto	112:6f327212ef96	1304	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto	112:6f327212ef96	1305	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto	112:6f327212ef96	1306	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto	112:6f327212ef96	1307	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto	112:6f327212ef96	1308	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto	112:6f327212ef96	1309	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto	112:6f327212ef96	1310	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto	112:6f327212ef96	1311
Kojto	112:6f327212ef96	1312	/**
Kojto	112:6f327212ef96	1313	* @}
Kojto	112:6f327212ef96	1314	*/
Kojto	112:6f327212ef96	1315
Kojto	112:6f327212ef96	1316	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1317	* @{
Kojto	112:6f327212ef96	1318	*/
Kojto	112:6f327212ef96	1319	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto	112:6f327212ef96	1320	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto	112:6f327212ef96	1321	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto	112:6f327212ef96	1322	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto	112:6f327212ef96	1323
Kojto	112:6f327212ef96	1324	/**
Kojto	112:6f327212ef96	1325	* @}
Kojto	112:6f327212ef96	1326	*/
Kojto	112:6f327212ef96	1327
Kojto	112:6f327212ef96	1328	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1329	* @{
Kojto	112:6f327212ef96	1330	*/
Kojto	112:6f327212ef96	1331	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto	112:6f327212ef96	1332	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto	112:6f327212ef96	1333	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto	112:6f327212ef96	1334	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto	112:6f327212ef96	1335	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto	112:6f327212ef96	1336	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto	112:6f327212ef96	1337	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto	112:6f327212ef96	1338	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto	112:6f327212ef96	1339	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto	112:6f327212ef96	1340	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto	112:6f327212ef96	1341	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto	112:6f327212ef96	1342	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto	112:6f327212ef96	1343	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto	112:6f327212ef96	1344	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto	112:6f327212ef96	1345	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto	112:6f327212ef96	1346	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto	112:6f327212ef96	1347
Kojto	112:6f327212ef96	1348	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto	112:6f327212ef96	1349	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto	112:6f327212ef96	1350	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto	112:6f327212ef96	1351	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto	112:6f327212ef96	1352	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto	112:6f327212ef96	1353	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto	112:6f327212ef96	1354	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto	112:6f327212ef96	1355	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto	112:6f327212ef96	1356	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto	112:6f327212ef96	1357	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto	112:6f327212ef96	1358	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto	112:6f327212ef96	1359	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto	112:6f327212ef96	1360	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto	112:6f327212ef96	1361	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto	112:6f327212ef96	1362
Kojto	112:6f327212ef96	1363
Kojto	112:6f327212ef96	1364	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto	112:6f327212ef96	1365	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto	112:6f327212ef96	1366	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto	112:6f327212ef96	1367	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto	112:6f327212ef96	1368	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto	112:6f327212ef96	1369	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto	112:6f327212ef96	1370	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto	112:6f327212ef96	1371	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto	112:6f327212ef96	1372	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto	112:6f327212ef96	1373	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto	112:6f327212ef96	1374	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto	112:6f327212ef96	1375	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto	112:6f327212ef96	1376	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto	112:6f327212ef96	1377	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto	112:6f327212ef96	1378	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto	112:6f327212ef96	1379	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto	112:6f327212ef96	1380	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto	112:6f327212ef96	1381	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto	112:6f327212ef96	1382	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto	112:6f327212ef96	1383	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto	112:6f327212ef96	1384	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto	112:6f327212ef96	1385	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto	112:6f327212ef96	1386	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto	112:6f327212ef96	1387	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto	112:6f327212ef96	1388
Kojto	112:6f327212ef96	1389	/**
Kojto	112:6f327212ef96	1390	* @}
Kojto	112:6f327212ef96	1391	*/
Kojto	112:6f327212ef96	1392
Kojto	112:6f327212ef96	1393	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1394	* @{
Kojto	112:6f327212ef96	1395	*/
Kojto	122:f9eeca106725	1396	#if defined(STM32F3)
Kojto	122:f9eeca106725	1397	#define COMP_START __HAL_COMP_ENABLE
Kojto	122:f9eeca106725	1398	#define COMP_STOP __HAL_COMP_DISABLE
Kojto	122:f9eeca106725	1399	#define COMP_LOCK __HAL_COMP_LOCK
Kojto	122:f9eeca106725	1400
Kojto	122:f9eeca106725	1401	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	122:f9eeca106725	1402	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1403	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1404	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1405	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1406	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1407	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1408	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1409	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1410	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1411	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1412	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1413	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1414	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1415	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1416	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto	122:f9eeca106725	1417	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1418	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1419	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto	122:f9eeca106725	1420	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1421	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1422	__HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto	122:f9eeca106725	1423	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1424	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1425	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto	122:f9eeca106725	1426	# endif
Kojto	122:f9eeca106725	1427	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
Kojto	122:f9eeca106725	1428	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1429	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1430	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1431	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1432	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1433	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1434	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1435	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1436	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1437	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1438	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1439	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1440	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1441	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1442	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1443	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1444	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1445	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1446	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1447	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto	122:f9eeca106725	1448	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1449	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1450	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1451	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto	122:f9eeca106725	1452	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1453	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1454	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1455	__HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto	122:f9eeca106725	1456	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1457	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1458	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1459	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto	122:f9eeca106725	1460	# endif
Kojto	122:f9eeca106725	1461	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	122:f9eeca106725	1462	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1463	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1464	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1465	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1466	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1467	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1468	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1469	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1470	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1471	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1472	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1473	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1474	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1475	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1476	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1477	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1479	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1480	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1481	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1482	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1483	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1484	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1486	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1487	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1488	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1489	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1490	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1491	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1493	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1494	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1495	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1496	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
Kojto	122:f9eeca106725	1497	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1498	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1500	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1501	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1502	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1503	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
Kojto	122:f9eeca106725	1504	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1505	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1506	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1507	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1508	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1509	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1510	__HAL_COMP_COMP7_EXTI_GET_FLAG())
Kojto	122:f9eeca106725	1511	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1512	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1513	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1514	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1515	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1516	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1517	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
Kojto	122:f9eeca106725	1518	# endif
Kojto	122:f9eeca106725	1519	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
Kojto	112:6f327212ef96	1520	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	112:6f327212ef96	1521	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1522	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto	112:6f327212ef96	1523	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto	112:6f327212ef96	1524	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	112:6f327212ef96	1525	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1526	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	112:6f327212ef96	1527	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1528	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	112:6f327212ef96	1529	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto	122:f9eeca106725	1530	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	112:6f327212ef96	1531	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto	122:f9eeca106725	1532	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	112:6f327212ef96	1533	__HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto	122:f9eeca106725	1534	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	112:6f327212ef96	1535	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto	122:f9eeca106725	1536	# endif
Kojto	122:f9eeca106725	1537	#else
Kojto	122:f9eeca106725	1538	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1539	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1540	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto	122:f9eeca106725	1541	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto	122:f9eeca106725	1542	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1543	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1544	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto	122:f9eeca106725	1545	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto	122:f9eeca106725	1546	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	122:f9eeca106725	1547	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto	122:f9eeca106725	1548	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	122:f9eeca106725	1549	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto	122:f9eeca106725	1550	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	122:f9eeca106725	1551	__HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto	122:f9eeca106725	1552	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	122:f9eeca106725	1553	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto	122:f9eeca106725	1554	#endif
Kojto	122:f9eeca106725	1555
Kojto	112:6f327212ef96	1556	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto	112:6f327212ef96	1557
Kojto	122:f9eeca106725	1558	#if defined(STM32L0) \|\| defined(STM32L4)
Kojto	122:f9eeca106725	1559	/* Note: On these STM32 families, the only argument of this macro */
Kojto	122:f9eeca106725	1560	/* is COMP_FLAG_LOCK. */
Kojto	122:f9eeca106725	1561	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
Kojto	122:f9eeca106725	1562	/* argument. */
Kojto	122:f9eeca106725	1563	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
Kojto	122:f9eeca106725	1564	#endif
Kojto	112:6f327212ef96	1565	/**
Kojto	112:6f327212ef96	1566	* @}
Kojto	112:6f327212ef96	1567	*/
Kojto	112:6f327212ef96	1568
Kojto	122:f9eeca106725	1569	#if defined(STM32L0) \|\| defined(STM32L4)
Kojto	122:f9eeca106725	1570	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
Kojto	122:f9eeca106725	1571	* @{
Kojto	122:f9eeca106725	1572	*/
Kojto	122:f9eeca106725	1573	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto	122:f9eeca106725	1574	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto	122:f9eeca106725	1575	/**
Kojto	122:f9eeca106725	1576	* @}
Kojto	122:f9eeca106725	1577	*/
Kojto	122:f9eeca106725	1578	#endif
Kojto	122:f9eeca106725	1579
Kojto	112:6f327212ef96	1580	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1581	* @{
Kojto	112:6f327212ef96	1582	*/
Kojto	112:6f327212ef96	1583
Kojto	112:6f327212ef96	1584	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
Kojto	112:6f327212ef96	1585	((WAVE) == DAC_WAVE_NOISE)\|\| \
Kojto	112:6f327212ef96	1586	((WAVE) == DAC_WAVE_TRIANGLE))
Kojto	112:6f327212ef96	1587
Kojto	112:6f327212ef96	1588	/**
Kojto	112:6f327212ef96	1589	* @}
Kojto	112:6f327212ef96	1590	*/
Kojto	112:6f327212ef96	1591
Kojto	112:6f327212ef96	1592	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1593	* @{
Kojto	112:6f327212ef96	1594	*/
Kojto	112:6f327212ef96	1595
Kojto	112:6f327212ef96	1596	#define IS_WRPAREA IS_OB_WRPAREA
Kojto	112:6f327212ef96	1597	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto	112:6f327212ef96	1598	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto	112:6f327212ef96	1599	#define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto	112:6f327212ef96	1600	#define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto	112:6f327212ef96	1601	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto	112:6f327212ef96	1602
Kojto	112:6f327212ef96	1603	/**
Kojto	112:6f327212ef96	1604	* @}
Kojto	112:6f327212ef96	1605	*/
Kojto	112:6f327212ef96	1606
Kojto	112:6f327212ef96	1607	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1608	* @{
Kojto	112:6f327212ef96	1609	*/
Kojto	112:6f327212ef96	1610
Kojto	112:6f327212ef96	1611	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto	112:6f327212ef96	1612	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto	112:6f327212ef96	1613	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto	112:6f327212ef96	1614	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto	112:6f327212ef96	1615	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto	112:6f327212ef96	1616	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto	112:6f327212ef96	1617	#define __HAL_I2C_SPEED I2C_SPEED
Kojto	112:6f327212ef96	1618	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto	112:6f327212ef96	1619	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto	112:6f327212ef96	1620	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto	112:6f327212ef96	1621	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto	112:6f327212ef96	1622	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto	112:6f327212ef96	1623	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto	112:6f327212ef96	1624	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto	112:6f327212ef96	1625	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto	112:6f327212ef96	1626	/**
Kojto	112:6f327212ef96	1627	* @}
Kojto	112:6f327212ef96	1628	*/
Kojto	112:6f327212ef96	1629
Kojto	112:6f327212ef96	1630	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1631	* @{
Kojto	112:6f327212ef96	1632	*/
Kojto	112:6f327212ef96	1633
Kojto	112:6f327212ef96	1634	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto	112:6f327212ef96	1635	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto	112:6f327212ef96	1636
Kojto	112:6f327212ef96	1637	/**
Kojto	112:6f327212ef96	1638	* @}
Kojto	112:6f327212ef96	1639	*/
Kojto	112:6f327212ef96	1640
Kojto	112:6f327212ef96	1641	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1642	* @{
Kojto	112:6f327212ef96	1643	*/
Kojto	112:6f327212ef96	1644
Kojto	112:6f327212ef96	1645	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto	112:6f327212ef96	1646	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto	112:6f327212ef96	1647
Kojto	112:6f327212ef96	1648	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	112:6f327212ef96	1649	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	112:6f327212ef96	1650	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	112:6f327212ef96	1651	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	112:6f327212ef96	1652
Kojto	112:6f327212ef96	1653	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto	112:6f327212ef96	1654
Kojto	112:6f327212ef96	1655
Kojto	112:6f327212ef96	1656	/**
Kojto	112:6f327212ef96	1657	* @}
Kojto	112:6f327212ef96	1658	*/
Kojto	112:6f327212ef96	1659
Kojto	112:6f327212ef96	1660
Kojto	112:6f327212ef96	1661	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1662	* @{
Kojto	112:6f327212ef96	1663	*/
Kojto	112:6f327212ef96	1664	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto	112:6f327212ef96	1665	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto	112:6f327212ef96	1666	/**
Kojto	112:6f327212ef96	1667	* @}
Kojto	112:6f327212ef96	1668	*/
Kojto	112:6f327212ef96	1669
Kojto	112:6f327212ef96	1670
Kojto	112:6f327212ef96	1671	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1672	* @{
Kojto	112:6f327212ef96	1673	*/
Kojto	112:6f327212ef96	1674
Kojto	112:6f327212ef96	1675	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto	112:6f327212ef96	1676	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto	112:6f327212ef96	1677	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto	112:6f327212ef96	1678
Kojto	112:6f327212ef96	1679	/**
Kojto	112:6f327212ef96	1680	* @}
Kojto	112:6f327212ef96	1681	*/
Kojto	112:6f327212ef96	1682
Kojto	112:6f327212ef96	1683
Kojto	112:6f327212ef96	1684	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1685	* @{
Kojto	112:6f327212ef96	1686	*/
Kojto	112:6f327212ef96	1687	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto	112:6f327212ef96	1688	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto	112:6f327212ef96	1689	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto	112:6f327212ef96	1690	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto	112:6f327212ef96	1691	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto	112:6f327212ef96	1692	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto	112:6f327212ef96	1693	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto	112:6f327212ef96	1694	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto	112:6f327212ef96	1695	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto	112:6f327212ef96	1696	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto	112:6f327212ef96	1697	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto	112:6f327212ef96	1698	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto	112:6f327212ef96	1699	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto	112:6f327212ef96	1700
Kojto	112:6f327212ef96	1701	/**
Kojto	112:6f327212ef96	1702	* @}
Kojto	112:6f327212ef96	1703	*/
Kojto	112:6f327212ef96	1704
Kojto	112:6f327212ef96	1705
Kojto	112:6f327212ef96	1706	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	1707	* @{
Kojto	112:6f327212ef96	1708	*/
Kojto	112:6f327212ef96	1709	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	112:6f327212ef96	1710	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	112:6f327212ef96	1711	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1712	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1713	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	112:6f327212ef96	1714	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	112:6f327212ef96	1715	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto	112:6f327212ef96	1716	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto	112:6f327212ef96	1717	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto	112:6f327212ef96	1718	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto	112:6f327212ef96	1719	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto	112:6f327212ef96	1720	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto	112:6f327212ef96	1721	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto	112:6f327212ef96	1722	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto	112:6f327212ef96	1723	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto	112:6f327212ef96	1724	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto	122:f9eeca106725	1725	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
Kojto	112:6f327212ef96	1726	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	112:6f327212ef96	1727	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	112:6f327212ef96	1728	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1729	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1730	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	112:6f327212ef96	1731	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	112:6f327212ef96	1732	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1733	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	122:f9eeca106725	1734	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
Kojto	122:f9eeca106725	1735	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
Kojto	112:6f327212ef96	1736	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto	112:6f327212ef96	1737	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto	112:6f327212ef96	1738	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto	112:6f327212ef96	1739	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto	112:6f327212ef96	1740	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1741	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	1742	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto	112:6f327212ef96	1743	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto	112:6f327212ef96	1744
Kojto	112:6f327212ef96	1745	#if defined (STM32F4)
Kojto	112:6f327212ef96	1746	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto	112:6f327212ef96	1747	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto	112:6f327212ef96	1748	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto	112:6f327212ef96	1749	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto	112:6f327212ef96	1750	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto	112:6f327212ef96	1751	#else
Kojto	112:6f327212ef96	1752	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	1753	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	1754	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	1755	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto	112:6f327212ef96	1756	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto	112:6f327212ef96	1757	#endif /* STM32F4 */
Kojto	112:6f327212ef96	1758	/**
Kojto	112:6f327212ef96	1759	* @}
Kojto	112:6f327212ef96	1760	*/
Kojto	112:6f327212ef96	1761
Kojto	112:6f327212ef96	1762
Kojto	112:6f327212ef96	1763	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto	112:6f327212ef96	1764	* @{
Kojto	112:6f327212ef96	1765	*/
Kojto	112:6f327212ef96	1766
Kojto	112:6f327212ef96	1767	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto	112:6f327212ef96	1768	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto	112:6f327212ef96	1769
Kojto	112:6f327212ef96	1770	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto	112:6f327212ef96	1771	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto	112:6f327212ef96	1772
Kojto	112:6f327212ef96	1773	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto	112:6f327212ef96	1774	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto	112:6f327212ef96	1775	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1776	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1777	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto	112:6f327212ef96	1778	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto	112:6f327212ef96	1779	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto	112:6f327212ef96	1780	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto	112:6f327212ef96	1781	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto	112:6f327212ef96	1782	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto	112:6f327212ef96	1783	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1784	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1785	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto	112:6f327212ef96	1786	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto	112:6f327212ef96	1787	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto	112:6f327212ef96	1788	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto	112:6f327212ef96	1789	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto	112:6f327212ef96	1790	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto	112:6f327212ef96	1791	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto	112:6f327212ef96	1792	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto	112:6f327212ef96	1793	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto	112:6f327212ef96	1794	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto	112:6f327212ef96	1795	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1796	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1797	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto	112:6f327212ef96	1798	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto	112:6f327212ef96	1799	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1800	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1801	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto	112:6f327212ef96	1802	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto	112:6f327212ef96	1803	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	112:6f327212ef96	1804	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto	112:6f327212ef96	1805	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto	112:6f327212ef96	1806	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto	112:6f327212ef96	1807	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto	112:6f327212ef96	1808	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto	112:6f327212ef96	1809	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto	112:6f327212ef96	1810	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto	112:6f327212ef96	1811	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto	112:6f327212ef96	1812	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto	112:6f327212ef96	1813	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto	112:6f327212ef96	1814	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto	112:6f327212ef96	1815	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto	112:6f327212ef96	1816	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto	112:6f327212ef96	1817	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto	112:6f327212ef96	1818	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto	112:6f327212ef96	1819	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto	112:6f327212ef96	1820	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto	112:6f327212ef96	1821	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto	112:6f327212ef96	1822	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto	112:6f327212ef96	1823	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto	112:6f327212ef96	1824	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto	112:6f327212ef96	1825	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	112:6f327212ef96	1826	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	112:6f327212ef96	1827	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1828	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1829	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	112:6f327212ef96	1830	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	112:6f327212ef96	1831	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	112:6f327212ef96	1832	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	112:6f327212ef96	1833	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	112:6f327212ef96	1834	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	112:6f327212ef96	1835	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto	112:6f327212ef96	1836	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto	112:6f327212ef96	1837	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto	112:6f327212ef96	1838	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto	112:6f327212ef96	1839	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto	112:6f327212ef96	1840	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto	112:6f327212ef96	1841	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto	112:6f327212ef96	1842	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto	112:6f327212ef96	1843	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto	112:6f327212ef96	1844	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto	112:6f327212ef96	1845	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1846	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1847	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto	112:6f327212ef96	1848	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto	112:6f327212ef96	1849	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto	112:6f327212ef96	1850	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto	112:6f327212ef96	1851	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1852	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1853	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto	112:6f327212ef96	1854	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto	112:6f327212ef96	1855	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto	112:6f327212ef96	1856	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto	112:6f327212ef96	1857	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto	112:6f327212ef96	1858	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto	112:6f327212ef96	1859	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto	112:6f327212ef96	1860	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto	112:6f327212ef96	1861	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1862	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1863	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto	112:6f327212ef96	1864	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto	112:6f327212ef96	1865	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto	112:6f327212ef96	1866	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto	112:6f327212ef96	1867	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto	112:6f327212ef96	1868	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto	112:6f327212ef96	1869	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto	112:6f327212ef96	1870	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto	112:6f327212ef96	1871	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1872	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1873	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto	112:6f327212ef96	1874	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto	112:6f327212ef96	1875	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto	112:6f327212ef96	1876	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto	112:6f327212ef96	1877	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1878	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1879	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto	112:6f327212ef96	1880	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto	112:6f327212ef96	1881	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto	112:6f327212ef96	1882	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto	112:6f327212ef96	1883	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1884	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1885	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto	112:6f327212ef96	1886	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto	112:6f327212ef96	1887	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto	112:6f327212ef96	1888	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto	112:6f327212ef96	1889	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto	112:6f327212ef96	1890	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto	112:6f327212ef96	1891	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto	112:6f327212ef96	1892	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto	112:6f327212ef96	1893	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto	112:6f327212ef96	1894	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto	112:6f327212ef96	1895	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto	112:6f327212ef96	1896	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto	112:6f327212ef96	1897	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto	112:6f327212ef96	1898	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto	112:6f327212ef96	1899	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1900	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1901	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto	112:6f327212ef96	1902	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto	112:6f327212ef96	1903	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto	112:6f327212ef96	1904	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto	112:6f327212ef96	1905	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto	112:6f327212ef96	1906	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto	112:6f327212ef96	1907	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1908	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1909	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto	112:6f327212ef96	1910	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto	112:6f327212ef96	1911	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1912	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1913	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto	112:6f327212ef96	1914	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto	112:6f327212ef96	1915	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto	112:6f327212ef96	1916	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto	112:6f327212ef96	1917	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto	112:6f327212ef96	1918	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto	112:6f327212ef96	1919	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1920	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1921	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto	112:6f327212ef96	1922	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto	112:6f327212ef96	1923	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto	112:6f327212ef96	1924	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto	112:6f327212ef96	1925	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1926	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1927	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto	112:6f327212ef96	1928	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto	112:6f327212ef96	1929	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto	112:6f327212ef96	1930	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto	112:6f327212ef96	1931	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1932	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1933	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto	112:6f327212ef96	1934	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto	112:6f327212ef96	1935	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto	112:6f327212ef96	1936	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto	112:6f327212ef96	1937	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1938	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1939	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto	112:6f327212ef96	1940	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto	112:6f327212ef96	1941	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto	112:6f327212ef96	1942	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto	112:6f327212ef96	1943	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1944	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1945	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto	112:6f327212ef96	1946	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto	112:6f327212ef96	1947	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto	112:6f327212ef96	1948	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto	112:6f327212ef96	1949	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1950	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1951	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto	112:6f327212ef96	1952	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto	112:6f327212ef96	1953	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto	112:6f327212ef96	1954	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto	112:6f327212ef96	1955	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1956	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1957	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto	112:6f327212ef96	1958	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto	112:6f327212ef96	1959	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto	112:6f327212ef96	1960	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto	112:6f327212ef96	1961	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1962	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1963	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto	112:6f327212ef96	1964	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto	112:6f327212ef96	1965	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto	112:6f327212ef96	1966	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto	112:6f327212ef96	1967	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1968	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1969	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto	112:6f327212ef96	1970	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto	112:6f327212ef96	1971	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto	112:6f327212ef96	1972	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto	112:6f327212ef96	1973	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1974	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1975	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto	112:6f327212ef96	1976	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto	112:6f327212ef96	1977	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto	112:6f327212ef96	1978	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto	112:6f327212ef96	1979	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1980	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1981	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto	112:6f327212ef96	1982	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto	112:6f327212ef96	1983	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto	112:6f327212ef96	1984	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto	112:6f327212ef96	1985	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1986	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1987	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto	112:6f327212ef96	1988	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto	112:6f327212ef96	1989	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto	112:6f327212ef96	1990	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto	112:6f327212ef96	1991	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1992	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1993	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto	112:6f327212ef96	1994	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto	112:6f327212ef96	1995	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto	112:6f327212ef96	1996	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto	112:6f327212ef96	1997	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	1998	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	1999	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto	112:6f327212ef96	2000	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto	112:6f327212ef96	2001	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto	112:6f327212ef96	2002	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto	112:6f327212ef96	2003	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2004	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2005	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto	112:6f327212ef96	2006	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto	112:6f327212ef96	2007	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto	112:6f327212ef96	2008	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto	112:6f327212ef96	2009	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2010	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2011	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto	112:6f327212ef96	2012	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto	112:6f327212ef96	2013	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto	112:6f327212ef96	2014	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto	112:6f327212ef96	2015	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2016	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2017	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto	112:6f327212ef96	2018	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto	112:6f327212ef96	2019	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto	112:6f327212ef96	2020	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto	112:6f327212ef96	2021	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2022	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2023	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto	112:6f327212ef96	2024	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto	112:6f327212ef96	2025	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto	112:6f327212ef96	2026	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto	112:6f327212ef96	2027	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2028	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2029	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto	112:6f327212ef96	2030	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto	112:6f327212ef96	2031	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto	112:6f327212ef96	2032	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto	112:6f327212ef96	2033	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2034	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2035	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto	112:6f327212ef96	2036	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto	112:6f327212ef96	2037	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto	112:6f327212ef96	2038	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto	112:6f327212ef96	2039	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2040	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2041	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto	112:6f327212ef96	2042	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto	112:6f327212ef96	2043	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto	112:6f327212ef96	2044	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto	112:6f327212ef96	2045	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2046	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2047	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto	112:6f327212ef96	2048	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto	112:6f327212ef96	2049	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto	112:6f327212ef96	2050	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	112:6f327212ef96	2051	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto	112:6f327212ef96	2052	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto	112:6f327212ef96	2053	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2054	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2055	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto	112:6f327212ef96	2056	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto	112:6f327212ef96	2057	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto	112:6f327212ef96	2058	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto	112:6f327212ef96	2059	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2060	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2061	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto	112:6f327212ef96	2062	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto	112:6f327212ef96	2063	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto	112:6f327212ef96	2064	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto	112:6f327212ef96	2065	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2066	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2067	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto	112:6f327212ef96	2068	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto	112:6f327212ef96	2069	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto	112:6f327212ef96	2070	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto	112:6f327212ef96	2071	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2072	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2073	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto	112:6f327212ef96	2074	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto	112:6f327212ef96	2075	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto	112:6f327212ef96	2076	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto	112:6f327212ef96	2077	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2078	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2079	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2080	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2081	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto	112:6f327212ef96	2082	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto	112:6f327212ef96	2083	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2084	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2085	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto	112:6f327212ef96	2086	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto	112:6f327212ef96	2087	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto	112:6f327212ef96	2088	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto	112:6f327212ef96	2089	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2090	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2091	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto	112:6f327212ef96	2092	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto	112:6f327212ef96	2093	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto	112:6f327212ef96	2094	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto	112:6f327212ef96	2095	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2096	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2097	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto	112:6f327212ef96	2098	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto	112:6f327212ef96	2099	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto	112:6f327212ef96	2100	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto	112:6f327212ef96	2101	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto	112:6f327212ef96	2102	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto	112:6f327212ef96	2103	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto	112:6f327212ef96	2104	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto	112:6f327212ef96	2105	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto	112:6f327212ef96	2106	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto	112:6f327212ef96	2107	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto	112:6f327212ef96	2108	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto	112:6f327212ef96	2109	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto	112:6f327212ef96	2110	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto	112:6f327212ef96	2111	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto	112:6f327212ef96	2112	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto	112:6f327212ef96	2113	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto	112:6f327212ef96	2114	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto	112:6f327212ef96	2115	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto	112:6f327212ef96	2116	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto	112:6f327212ef96	2117	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto	112:6f327212ef96	2118	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto	112:6f327212ef96	2119	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto	112:6f327212ef96	2120	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto	112:6f327212ef96	2121	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2122	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2123	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto	112:6f327212ef96	2124	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto	112:6f327212ef96	2125	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto	112:6f327212ef96	2126	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto	112:6f327212ef96	2127	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2128	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2129	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto	112:6f327212ef96	2130	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto	112:6f327212ef96	2131	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto	112:6f327212ef96	2132	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto	112:6f327212ef96	2133	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2134	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2135	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto	112:6f327212ef96	2136	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto	112:6f327212ef96	2137	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto	112:6f327212ef96	2138	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto	112:6f327212ef96	2139	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2140	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2141	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto	112:6f327212ef96	2142	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto	112:6f327212ef96	2143	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto	112:6f327212ef96	2144	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto	112:6f327212ef96	2145	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2146	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2147	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto	112:6f327212ef96	2148	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto	112:6f327212ef96	2149	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto	112:6f327212ef96	2150	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto	112:6f327212ef96	2151	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2152	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2153	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto	112:6f327212ef96	2154	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto	112:6f327212ef96	2155	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto	112:6f327212ef96	2156	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto	112:6f327212ef96	2157	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2158	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2159	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto	112:6f327212ef96	2160	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto	112:6f327212ef96	2161	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto	112:6f327212ef96	2162	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto	112:6f327212ef96	2163	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2164	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2165	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto	112:6f327212ef96	2166	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto	112:6f327212ef96	2167	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto	112:6f327212ef96	2168	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto	112:6f327212ef96	2169	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2170	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2171	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto	112:6f327212ef96	2172	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto	112:6f327212ef96	2173	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto	112:6f327212ef96	2174	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto	112:6f327212ef96	2175	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2176	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2177	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto	112:6f327212ef96	2178	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto	112:6f327212ef96	2179	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto	112:6f327212ef96	2180	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto	112:6f327212ef96	2181	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto	112:6f327212ef96	2182	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto	112:6f327212ef96	2183	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto	112:6f327212ef96	2184	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto	112:6f327212ef96	2185	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2186	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2187	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto	112:6f327212ef96	2188	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto	112:6f327212ef96	2189	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto	112:6f327212ef96	2190	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto	112:6f327212ef96	2191	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2192	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2193	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto	112:6f327212ef96	2194	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto	112:6f327212ef96	2195	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto	112:6f327212ef96	2196	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto	112:6f327212ef96	2197	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2198	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2199	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto	112:6f327212ef96	2200	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto	112:6f327212ef96	2201	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto	112:6f327212ef96	2202	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto	112:6f327212ef96	2203	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2204	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2205	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto	112:6f327212ef96	2206	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto	112:6f327212ef96	2207	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto	112:6f327212ef96	2208	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto	112:6f327212ef96	2209	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2210	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2211	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto	112:6f327212ef96	2212	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto	112:6f327212ef96	2213	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto	112:6f327212ef96	2214	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto	112:6f327212ef96	2215	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2216	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2217	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto	112:6f327212ef96	2218	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto	112:6f327212ef96	2219	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto	112:6f327212ef96	2220	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto	112:6f327212ef96	2221	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2222	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto	122:f9eeca106725	2223	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto	122:f9eeca106725	2224	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto	112:6f327212ef96	2225	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto	112:6f327212ef96	2226	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto	112:6f327212ef96	2227	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2228	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto	122:f9eeca106725	2229	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto	122:f9eeca106725	2230	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto	112:6f327212ef96	2231	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto	112:6f327212ef96	2232	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto	122:f9eeca106725	2233	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto	122:f9eeca106725	2234	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto	112:6f327212ef96	2235	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto	112:6f327212ef96	2236	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto	122:f9eeca106725	2237	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto	122:f9eeca106725	2238	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto	112:6f327212ef96	2239	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto	112:6f327212ef96	2240	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto	112:6f327212ef96	2241	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto	112:6f327212ef96	2242	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2243	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2244	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto	112:6f327212ef96	2245	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto	112:6f327212ef96	2246	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto	112:6f327212ef96	2247	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto	112:6f327212ef96	2248	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto	112:6f327212ef96	2249	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2250	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2251	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto	112:6f327212ef96	2252	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto	112:6f327212ef96	2253	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto	112:6f327212ef96	2254	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto	112:6f327212ef96	2255	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto	112:6f327212ef96	2256	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto	112:6f327212ef96	2257	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2258	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2259	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto	112:6f327212ef96	2260	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto	112:6f327212ef96	2261	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto	112:6f327212ef96	2262	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto	112:6f327212ef96	2263	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2264	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2265	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto	112:6f327212ef96	2266	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto	112:6f327212ef96	2267	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2268	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2269	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto	112:6f327212ef96	2270	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto	112:6f327212ef96	2271	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto	112:6f327212ef96	2272	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto	112:6f327212ef96	2273
Kojto	112:6f327212ef96	2274	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	112:6f327212ef96	2275	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	112:6f327212ef96	2276	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2277	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2278	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto	112:6f327212ef96	2279	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto	112:6f327212ef96	2280	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto	112:6f327212ef96	2281	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto	112:6f327212ef96	2282	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2283	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2284	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2285	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2286	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2287	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2288	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2289	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2290	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto	112:6f327212ef96	2291	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto	112:6f327212ef96	2292	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto	112:6f327212ef96	2293	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto	112:6f327212ef96	2294	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto	112:6f327212ef96	2295	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2296	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2297	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto	112:6f327212ef96	2298	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto	112:6f327212ef96	2299	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto	112:6f327212ef96	2300	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto	112:6f327212ef96	2301	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto	112:6f327212ef96	2302	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2303	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2304	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto	112:6f327212ef96	2305	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto	112:6f327212ef96	2306	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto	112:6f327212ef96	2307	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto	112:6f327212ef96	2308	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2309	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2310	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto	112:6f327212ef96	2311	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto	112:6f327212ef96	2312	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto	112:6f327212ef96	2313	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto	112:6f327212ef96	2314	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2315	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2316	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2317	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2318	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2319	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2320	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2321	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2322	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2323	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2324	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2325	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2326	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2327	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto	112:6f327212ef96	2328	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto	112:6f327212ef96	2329	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2330	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2331	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto	112:6f327212ef96	2332	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto	112:6f327212ef96	2333	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto	112:6f327212ef96	2334	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto	112:6f327212ef96	2335	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto	112:6f327212ef96	2336	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto	112:6f327212ef96	2337	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2338	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2339	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto	112:6f327212ef96	2340	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto	112:6f327212ef96	2341	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto	112:6f327212ef96	2342	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto	112:6f327212ef96	2343	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2344	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2345	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto	112:6f327212ef96	2346	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto	112:6f327212ef96	2347	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto	112:6f327212ef96	2348	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto	112:6f327212ef96	2349	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2350	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2351	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto	112:6f327212ef96	2352	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto	112:6f327212ef96	2353	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto	112:6f327212ef96	2354	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto	112:6f327212ef96	2355	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2356	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2357	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto	112:6f327212ef96	2358	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto	112:6f327212ef96	2359	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto	112:6f327212ef96	2360	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2361	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2362	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto	112:6f327212ef96	2363	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto	112:6f327212ef96	2364	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto	112:6f327212ef96	2365	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto	112:6f327212ef96	2366	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto	112:6f327212ef96	2367	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto	112:6f327212ef96	2368	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2369	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2370	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto	112:6f327212ef96	2371	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto	112:6f327212ef96	2372	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto	112:6f327212ef96	2373	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto	112:6f327212ef96	2374	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2375	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2376	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto	112:6f327212ef96	2377	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto	112:6f327212ef96	2378	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto	112:6f327212ef96	2379	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto	112:6f327212ef96	2380	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2381	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2382	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2383	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2384	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	112:6f327212ef96	2385	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	112:6f327212ef96	2386	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2387	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2388	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2389	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2390	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto	112:6f327212ef96	2391	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto	112:6f327212ef96	2392	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	112:6f327212ef96	2393	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	112:6f327212ef96	2394	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2395	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2396	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto	112:6f327212ef96	2397	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto	112:6f327212ef96	2398	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	112:6f327212ef96	2399	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2400	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2401	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2402	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2403	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2404	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2405	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2406	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2407	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2408	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto	112:6f327212ef96	2409	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto	112:6f327212ef96	2410	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2411	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2412	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto	112:6f327212ef96	2413	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto	112:6f327212ef96	2414	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2415	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2416	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto	112:6f327212ef96	2417	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto	112:6f327212ef96	2418	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto	112:6f327212ef96	2419	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto	112:6f327212ef96	2420	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2421	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2422
Kojto	112:6f327212ef96	2423	/* alias define maintained for legacy */
Kojto	112:6f327212ef96	2424	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	112:6f327212ef96	2425	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	112:6f327212ef96	2426
Kojto	112:6f327212ef96	2427	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto	112:6f327212ef96	2428	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto	112:6f327212ef96	2429	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
Kojto	112:6f327212ef96	2430	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
Kojto	112:6f327212ef96	2431	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto	112:6f327212ef96	2432	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto	112:6f327212ef96	2433	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
Kojto	112:6f327212ef96	2434	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
Kojto	112:6f327212ef96	2435	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
Kojto	112:6f327212ef96	2436	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
Kojto	112:6f327212ef96	2437	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
Kojto	112:6f327212ef96	2438	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
Kojto	112:6f327212ef96	2439	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
Kojto	112:6f327212ef96	2440	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
Kojto	112:6f327212ef96	2441	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
Kojto	112:6f327212ef96	2442	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
Kojto	112:6f327212ef96	2443	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
Kojto	112:6f327212ef96	2444	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
Kojto	112:6f327212ef96	2445	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
Kojto	112:6f327212ef96	2446	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
Kojto	112:6f327212ef96	2447	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
Kojto	112:6f327212ef96	2448	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
Kojto	112:6f327212ef96	2449
Kojto	112:6f327212ef96	2450	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto	112:6f327212ef96	2451	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto	112:6f327212ef96	2452	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
Kojto	112:6f327212ef96	2453	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
Kojto	112:6f327212ef96	2454	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto	112:6f327212ef96	2455	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto	112:6f327212ef96	2456	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
Kojto	112:6f327212ef96	2457	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
Kojto	112:6f327212ef96	2458	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
Kojto	112:6f327212ef96	2459	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
Kojto	112:6f327212ef96	2460	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
Kojto	112:6f327212ef96	2461	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
Kojto	112:6f327212ef96	2462	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
Kojto	112:6f327212ef96	2463	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
Kojto	112:6f327212ef96	2464	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
Kojto	112:6f327212ef96	2465	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
Kojto	112:6f327212ef96	2466	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
Kojto	112:6f327212ef96	2467	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
Kojto	112:6f327212ef96	2468	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
Kojto	112:6f327212ef96	2469	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
Kojto	112:6f327212ef96	2470	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
Kojto	112:6f327212ef96	2471	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
Kojto	112:6f327212ef96	2472
Kojto	112:6f327212ef96	2473	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2474	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2475	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2476	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2477	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2478	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2479	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2480	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2481	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2482	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2483	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2484	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2485	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2486	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2487	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2488	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2489	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2490	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2491	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2492	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2493	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2494	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2495	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2496	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2497	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2498	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2499	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2500	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2501	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2502	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2503	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2504	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2505	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2506	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2507	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2508	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2509	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2510	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2511	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2512	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2513	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2514	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2515	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2516	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2517	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2518	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2519	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2520	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2521	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2522	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2523	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2524	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2525	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2526	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2527	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2528	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2529	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2530	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2531	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2532	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2533	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2534	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2535	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2536	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2537	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2538	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2539	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2540	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2541	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2542	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2543	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2544	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2545	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2546	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2547	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2548	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2549	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2550	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2551	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2552	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2553	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2554	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2555	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2556	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2557	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2558	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2559	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2560	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2561	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2562	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2563	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2564	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2565	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2566	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2567	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2568	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2569	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2570	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2571	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2572	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2573	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2574	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2575	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2576	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2577	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2578	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2579	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2580	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2581	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2582	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2583	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2584	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2585	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2586	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2587	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
Kojto	112:6f327212ef96	2588	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2589
Kojto	112:6f327212ef96	2590	#if defined(STM32F4)
Kojto	112:6f327212ef96	2591	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto	112:6f327212ef96	2592	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto	112:6f327212ef96	2593	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2594	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2595	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	112:6f327212ef96	2596	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto	122:f9eeca106725	2597	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
Kojto	122:f9eeca106725	2598	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2599	#define Sdmmc1ClockSelection SdioClockSelection
Kojto	112:6f327212ef96	2600	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto	112:6f327212ef96	2601	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto	112:6f327212ef96	2602	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto	112:6f327212ef96	2603	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto	112:6f327212ef96	2604	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto	112:6f327212ef96	2605	#endif
Kojto	112:6f327212ef96	2606
Kojto	112:6f327212ef96	2607	#if defined(STM32F7) \|\| defined(STM32L4)
Kojto	112:6f327212ef96	2608	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto	112:6f327212ef96	2609	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto	112:6f327212ef96	2610	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto	112:6f327212ef96	2611	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto	112:6f327212ef96	2612	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto	112:6f327212ef96	2613	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto	122:f9eeca106725	2614	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
Kojto	122:f9eeca106725	2615	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
Kojto	112:6f327212ef96	2616	#define SdioClockSelection Sdmmc1ClockSelection
Kojto	112:6f327212ef96	2617	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto	112:6f327212ef96	2618	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto	112:6f327212ef96	2619	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto	112:6f327212ef96	2620	#endif
Kojto	112:6f327212ef96	2621
Kojto	112:6f327212ef96	2622	#if defined(STM32F7)
Kojto	122:f9eeca106725	2623	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto	112:6f327212ef96	2624	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto	112:6f327212ef96	2625	#endif
Kojto	112:6f327212ef96	2626
Kojto	112:6f327212ef96	2627	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto	112:6f327212ef96	2628	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto	112:6f327212ef96	2629
Kojto	112:6f327212ef96	2630	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto	112:6f327212ef96	2631
Kojto	112:6f327212ef96	2632	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto	112:6f327212ef96	2633	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto	112:6f327212ef96	2634	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto	112:6f327212ef96	2635	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto	122:f9eeca106725	2636	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
Kojto	112:6f327212ef96	2637
Kojto	112:6f327212ef96	2638	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
Kojto	112:6f327212ef96	2639
Kojto	122:f9eeca106725	2640	#if defined(STM32L0)
Kojto	122:f9eeca106725	2641	#define RCC_IT_LSECSS RCC_IT_CSSLSE
Kojto	122:f9eeca106725	2642	#define RCC_IT_CSS RCC_IT_CSSHSE
Kojto	122:f9eeca106725	2643	#endif
Kojto	122:f9eeca106725	2644
Kojto	112:6f327212ef96	2645	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto	112:6f327212ef96	2646	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
Kojto	112:6f327212ef96	2647	#define RCC_MCO_NODIV RCC_MCODIV_1
Kojto	112:6f327212ef96	2648	#define RCC_MCO_DIV1 RCC_MCODIV_1
Kojto	112:6f327212ef96	2649	#define RCC_MCO_DIV2 RCC_MCODIV_2
Kojto	112:6f327212ef96	2650	#define RCC_MCO_DIV4 RCC_MCODIV_4
Kojto	112:6f327212ef96	2651	#define RCC_MCO_DIV8 RCC_MCODIV_8
Kojto	112:6f327212ef96	2652	#define RCC_MCO_DIV16 RCC_MCODIV_16
Kojto	112:6f327212ef96	2653	#define RCC_MCO_DIV32 RCC_MCODIV_32
Kojto	112:6f327212ef96	2654	#define RCC_MCO_DIV64 RCC_MCODIV_64
Kojto	112:6f327212ef96	2655	#define RCC_MCO_DIV128 RCC_MCODIV_128
Kojto	112:6f327212ef96	2656	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
Kojto	112:6f327212ef96	2657	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
Kojto	112:6f327212ef96	2658	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
Kojto	112:6f327212ef96	2659	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
Kojto	112:6f327212ef96	2660	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
Kojto	112:6f327212ef96	2661	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
Kojto	112:6f327212ef96	2662	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
Kojto	112:6f327212ef96	2663	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
Kojto	112:6f327212ef96	2664	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
Kojto	112:6f327212ef96	2665	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
Kojto	112:6f327212ef96	2666	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
Kojto	112:6f327212ef96	2667
Kojto	112:6f327212ef96	2668	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto	112:6f327212ef96	2669
Kojto	112:6f327212ef96	2670	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
Kojto	112:6f327212ef96	2671	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
Kojto	112:6f327212ef96	2672	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
Kojto	112:6f327212ef96	2673	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
Kojto	112:6f327212ef96	2674	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
Kojto	112:6f327212ef96	2675	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
Kojto	112:6f327212ef96	2676	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
Kojto	112:6f327212ef96	2677	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
Kojto	112:6f327212ef96	2678
Kojto	112:6f327212ef96	2679	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto	112:6f327212ef96	2680	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
Kojto	112:6f327212ef96	2681	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
Kojto	112:6f327212ef96	2682	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
Kojto	112:6f327212ef96	2683	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
Kojto	112:6f327212ef96	2684	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto	112:6f327212ef96	2685	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
Kojto	112:6f327212ef96	2686	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto	112:6f327212ef96	2687	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
Kojto	112:6f327212ef96	2688	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto	112:6f327212ef96	2689	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto	112:6f327212ef96	2690	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto	112:6f327212ef96	2691	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
Kojto	112:6f327212ef96	2692	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto	112:6f327212ef96	2693	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
Kojto	112:6f327212ef96	2694	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
Kojto	112:6f327212ef96	2695	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto	112:6f327212ef96	2696	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
Kojto	112:6f327212ef96	2697	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
Kojto	112:6f327212ef96	2698	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
Kojto	112:6f327212ef96	2699	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
Kojto	112:6f327212ef96	2700	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto	112:6f327212ef96	2701	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto	112:6f327212ef96	2702	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
Kojto	112:6f327212ef96	2703	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
Kojto	112:6f327212ef96	2704	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
Kojto	112:6f327212ef96	2705	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto	112:6f327212ef96	2706	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto	112:6f327212ef96	2707	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto	112:6f327212ef96	2708	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto	112:6f327212ef96	2709	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto	112:6f327212ef96	2710	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto	112:6f327212ef96	2711
Kojto	112:6f327212ef96	2712	#define CR_HSION_BB RCC_CR_HSION_BB
Kojto	112:6f327212ef96	2713	#define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto	112:6f327212ef96	2714	#define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto	112:6f327212ef96	2715	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto	112:6f327212ef96	2716	#define CR_MSION_BB RCC_CR_MSION_BB
Kojto	112:6f327212ef96	2717	#define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto	112:6f327212ef96	2718	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto	112:6f327212ef96	2719	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto	112:6f327212ef96	2720	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto	112:6f327212ef96	2721	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto	112:6f327212ef96	2722	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto	112:6f327212ef96	2723	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto	112:6f327212ef96	2724	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto	112:6f327212ef96	2725	#define CR_HSEON_BB RCC_CR_HSEON_BB
Kojto	112:6f327212ef96	2726	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
Kojto	112:6f327212ef96	2727	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto	112:6f327212ef96	2728	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto	112:6f327212ef96	2729
Kojto	122:f9eeca106725	2730	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
Kojto	122:f9eeca106725	2731	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
Kojto	122:f9eeca106725	2732	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
Kojto	122:f9eeca106725	2733	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
Kojto	122:f9eeca106725	2734	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
Kojto	122:f9eeca106725	2735
Kojto	122:f9eeca106725	2736	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
Kojto	122:f9eeca106725	2737
Kojto	122:f9eeca106725	2738	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
Kojto	122:f9eeca106725	2739	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
Kojto	122:f9eeca106725	2740
Kojto	122:f9eeca106725	2741	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
Kojto	122:f9eeca106725	2742	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
Kojto	122:f9eeca106725	2743	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
Kojto	122:f9eeca106725	2744	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
Kojto	122:f9eeca106725	2745	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
Kojto	122:f9eeca106725	2746	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
Kojto	122:f9eeca106725	2747
Kojto	122:f9eeca106725	2748	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
Kojto	122:f9eeca106725	2749	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
Kojto	122:f9eeca106725	2750	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
Kojto	122:f9eeca106725	2751	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
Kojto	122:f9eeca106725	2752	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
Kojto	122:f9eeca106725	2753	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
Kojto	122:f9eeca106725	2754	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
Kojto	122:f9eeca106725	2755	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
Kojto	122:f9eeca106725	2756	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
Kojto	122:f9eeca106725	2757	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
Kojto	122:f9eeca106725	2758	#define DfsdmClockSelection Dfsdm1ClockSelection
Kojto	122:f9eeca106725	2759	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
Kojto	122:f9eeca106725	2760	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
Kojto	122:f9eeca106725	2761	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2762	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
Kojto	122:f9eeca106725	2763	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
Kojto	122:f9eeca106725	2764
Kojto	112:6f327212ef96	2765	/**
Kojto	112:6f327212ef96	2766	* @}
Kojto	112:6f327212ef96	2767	*/
Kojto	112:6f327212ef96	2768
Kojto	112:6f327212ef96	2769	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2770	* @{
Kojto	112:6f327212ef96	2771	*/
Kojto	112:6f327212ef96	2772	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto	112:6f327212ef96	2773
Kojto	112:6f327212ef96	2774	/**
Kojto	112:6f327212ef96	2775	* @}
Kojto	112:6f327212ef96	2776	*/
Kojto	112:6f327212ef96	2777
Kojto	112:6f327212ef96	2778	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2779	* @{
Kojto	112:6f327212ef96	2780	*/
Kojto	112:6f327212ef96	2781
Kojto	112:6f327212ef96	2782	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	2783	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	2784	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	2785
Kojto	112:6f327212ef96	2786	#if defined (STM32F1)
Kojto	112:6f327212ef96	2787	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto	112:6f327212ef96	2788
Kojto	112:6f327212ef96	2789	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto	112:6f327212ef96	2790
Kojto	112:6f327212ef96	2791	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto	112:6f327212ef96	2792
Kojto	112:6f327212ef96	2793	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto	112:6f327212ef96	2794
Kojto	112:6f327212ef96	2795	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto	112:6f327212ef96	2796	#else
Kojto	112:6f327212ef96	2797	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto	112:6f327212ef96	2798	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto	112:6f327212ef96	2799	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto	112:6f327212ef96	2800	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto	112:6f327212ef96	2801	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto	112:6f327212ef96	2802	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto	112:6f327212ef96	2803	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto	112:6f327212ef96	2804	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto	112:6f327212ef96	2805	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto	112:6f327212ef96	2806	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto	112:6f327212ef96	2807	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto	112:6f327212ef96	2808	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto	112:6f327212ef96	2809	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto	112:6f327212ef96	2810	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto	112:6f327212ef96	2811	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto	112:6f327212ef96	2812	#endif /* STM32F1 */
Kojto	112:6f327212ef96	2813
Kojto	112:6f327212ef96	2814	#define IS_ALARM IS_RTC_ALARM
Kojto	112:6f327212ef96	2815	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto	112:6f327212ef96	2816	#define IS_TAMPER IS_RTC_TAMPER
Kojto	112:6f327212ef96	2817	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto	112:6f327212ef96	2818	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto	112:6f327212ef96	2819	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto	112:6f327212ef96	2820	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto	112:6f327212ef96	2821	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto	112:6f327212ef96	2822	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto	112:6f327212ef96	2823	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto	112:6f327212ef96	2824	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto	112:6f327212ef96	2825	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto	112:6f327212ef96	2826	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto	112:6f327212ef96	2827	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto	112:6f327212ef96	2828
Kojto	112:6f327212ef96	2829	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto	112:6f327212ef96	2830	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto	112:6f327212ef96	2831
Kojto	112:6f327212ef96	2832	/**
Kojto	112:6f327212ef96	2833	* @}
Kojto	112:6f327212ef96	2834	*/
Kojto	112:6f327212ef96	2835
Kojto	112:6f327212ef96	2836	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2837	* @{
Kojto	112:6f327212ef96	2838	*/
Kojto	112:6f327212ef96	2839
Kojto	112:6f327212ef96	2840	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto	112:6f327212ef96	2841	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto	112:6f327212ef96	2842
Kojto	112:6f327212ef96	2843	#if defined(STM32F4)
Kojto	112:6f327212ef96	2844	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto	112:6f327212ef96	2845	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto	112:6f327212ef96	2846	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto	112:6f327212ef96	2847	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto	112:6f327212ef96	2848	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto	112:6f327212ef96	2849	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto	112:6f327212ef96	2850	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto	112:6f327212ef96	2851	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto	112:6f327212ef96	2852	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto	112:6f327212ef96	2853	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto	112:6f327212ef96	2854	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto	112:6f327212ef96	2855	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto	112:6f327212ef96	2856	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto	112:6f327212ef96	2857	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto	112:6f327212ef96	2858	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto	112:6f327212ef96	2859	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto	112:6f327212ef96	2860	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto	112:6f327212ef96	2861	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto	112:6f327212ef96	2862	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto	112:6f327212ef96	2863	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto	112:6f327212ef96	2864	/* alias CMSIS */
Kojto	112:6f327212ef96	2865	#define SDMMC1_IRQn SDIO_IRQn
Kojto	112:6f327212ef96	2866	#define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto	112:6f327212ef96	2867	#endif
Kojto	112:6f327212ef96	2868
Kojto	112:6f327212ef96	2869	#if defined(STM32F7) \|\| defined(STM32L4)
Kojto	112:6f327212ef96	2870	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto	112:6f327212ef96	2871	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto	112:6f327212ef96	2872	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto	112:6f327212ef96	2873	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto	112:6f327212ef96	2874	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto	112:6f327212ef96	2875	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto	112:6f327212ef96	2876	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto	112:6f327212ef96	2877	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto	112:6f327212ef96	2878	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto	112:6f327212ef96	2879	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto	112:6f327212ef96	2880	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto	112:6f327212ef96	2881	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto	112:6f327212ef96	2882	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto	112:6f327212ef96	2883	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto	112:6f327212ef96	2884	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto	112:6f327212ef96	2885	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto	112:6f327212ef96	2886	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto	112:6f327212ef96	2887	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto	112:6f327212ef96	2888	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto	112:6f327212ef96	2889	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto	112:6f327212ef96	2890	/* alias CMSIS for compatibilities */
Kojto	112:6f327212ef96	2891	#define SDIO_IRQn SDMMC1_IRQn
Kojto	112:6f327212ef96	2892	#define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto	112:6f327212ef96	2893	#endif
Kojto	112:6f327212ef96	2894	/**
Kojto	112:6f327212ef96	2895	* @}
Kojto	112:6f327212ef96	2896	*/
Kojto	112:6f327212ef96	2897
Kojto	112:6f327212ef96	2898	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2899	* @{
Kojto	112:6f327212ef96	2900	*/
Kojto	112:6f327212ef96	2901
Kojto	112:6f327212ef96	2902	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto	112:6f327212ef96	2903	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto	112:6f327212ef96	2904	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto	112:6f327212ef96	2905	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto	112:6f327212ef96	2906	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto	112:6f327212ef96	2907	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto	112:6f327212ef96	2908
Kojto	112:6f327212ef96	2909	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2910	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2911
Kojto	112:6f327212ef96	2912	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto	112:6f327212ef96	2913
Kojto	112:6f327212ef96	2914	/**
Kojto	112:6f327212ef96	2915	* @}
Kojto	112:6f327212ef96	2916	*/
Kojto	112:6f327212ef96	2917
Kojto	112:6f327212ef96	2918	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2919	* @{
Kojto	112:6f327212ef96	2920	*/
Kojto	112:6f327212ef96	2921	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto	112:6f327212ef96	2922	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto	112:6f327212ef96	2923	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto	112:6f327212ef96	2924	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto	112:6f327212ef96	2925	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto	112:6f327212ef96	2926	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto	112:6f327212ef96	2927	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto	112:6f327212ef96	2928	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto	112:6f327212ef96	2929	/**
Kojto	112:6f327212ef96	2930	* @}
Kojto	112:6f327212ef96	2931	*/
Kojto	112:6f327212ef96	2932
Kojto	112:6f327212ef96	2933	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2934	* @{
Kojto	112:6f327212ef96	2935	*/
Kojto	112:6f327212ef96	2936
Kojto	112:6f327212ef96	2937	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto	112:6f327212ef96	2938	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto	112:6f327212ef96	2939	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto	112:6f327212ef96	2940
Kojto	112:6f327212ef96	2941	/**
Kojto	112:6f327212ef96	2942	* @}
Kojto	112:6f327212ef96	2943	*/
Kojto	112:6f327212ef96	2944
Kojto	112:6f327212ef96	2945	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2946	* @{
Kojto	112:6f327212ef96	2947	*/
Kojto	112:6f327212ef96	2948
Kojto	112:6f327212ef96	2949	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2950	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	112:6f327212ef96	2951	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2952	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	112:6f327212ef96	2953
Kojto	112:6f327212ef96	2954	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto	112:6f327212ef96	2955
Kojto	112:6f327212ef96	2956	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto	112:6f327212ef96	2957	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto	112:6f327212ef96	2958
Kojto	112:6f327212ef96	2959	/**
Kojto	112:6f327212ef96	2960	* @}
Kojto	112:6f327212ef96	2961	*/
Kojto	112:6f327212ef96	2962
Kojto	112:6f327212ef96	2963
Kojto	112:6f327212ef96	2964	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2965	* @{
Kojto	112:6f327212ef96	2966	*/
Kojto	112:6f327212ef96	2967
Kojto	112:6f327212ef96	2968	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto	112:6f327212ef96	2969	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto	112:6f327212ef96	2970	#define __USART_ENABLE __HAL_USART_ENABLE
Kojto	112:6f327212ef96	2971	#define __USART_DISABLE __HAL_USART_DISABLE
Kojto	112:6f327212ef96	2972
Kojto	112:6f327212ef96	2973	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2974	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	112:6f327212ef96	2975
Kojto	112:6f327212ef96	2976	/**
Kojto	112:6f327212ef96	2977	* @}
Kojto	112:6f327212ef96	2978	*/
Kojto	112:6f327212ef96	2979
Kojto	112:6f327212ef96	2980	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	2981	* @{
Kojto	112:6f327212ef96	2982	*/
Kojto	112:6f327212ef96	2983	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto	112:6f327212ef96	2984
Kojto	112:6f327212ef96	2985	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto	112:6f327212ef96	2986	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto	112:6f327212ef96	2987	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	112:6f327212ef96	2988	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto	112:6f327212ef96	2989
Kojto	112:6f327212ef96	2990	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto	112:6f327212ef96	2991	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto	112:6f327212ef96	2992	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	112:6f327212ef96	2993	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto	112:6f327212ef96	2994
Kojto	112:6f327212ef96	2995	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	2996	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	2997	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto	112:6f327212ef96	2998	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	2999	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	112:6f327212ef96	3000	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	3001	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	112:6f327212ef96	3002
Kojto	112:6f327212ef96	3003	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	3004	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	3005	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto	112:6f327212ef96	3006	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	3007	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	112:6f327212ef96	3008	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	3009	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	112:6f327212ef96	3010	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	112:6f327212ef96	3011
Kojto	112:6f327212ef96	3012	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	3013	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	3014	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto	112:6f327212ef96	3015	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	3016	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	112:6f327212ef96	3017	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	112:6f327212ef96	3018	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	112:6f327212ef96	3019	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	112:6f327212ef96	3020
Kojto	112:6f327212ef96	3021	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto	112:6f327212ef96	3022	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto	112:6f327212ef96	3023
Kojto	112:6f327212ef96	3024	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto	112:6f327212ef96	3025	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto	112:6f327212ef96	3026	/**
Kojto	112:6f327212ef96	3027	* @}
Kojto	112:6f327212ef96	3028	*/
Kojto	112:6f327212ef96	3029
Kojto	112:6f327212ef96	3030	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	3031	* @{
Kojto	112:6f327212ef96	3032	*/
Kojto	112:6f327212ef96	3033	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto	112:6f327212ef96	3034	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto	112:6f327212ef96	3035
Kojto	112:6f327212ef96	3036	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	112:6f327212ef96	3037	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto	112:6f327212ef96	3038
Kojto	112:6f327212ef96	3039	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	112:6f327212ef96	3040
Kojto	112:6f327212ef96	3041	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto	112:6f327212ef96	3042	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto	112:6f327212ef96	3043	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto	112:6f327212ef96	3044	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto	112:6f327212ef96	3045	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto	112:6f327212ef96	3046	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto	112:6f327212ef96	3047	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto	112:6f327212ef96	3048	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto	112:6f327212ef96	3049	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto	112:6f327212ef96	3050	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto	112:6f327212ef96	3051	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto	112:6f327212ef96	3052	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto	112:6f327212ef96	3053
Kojto	122:f9eeca106725	3054	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
Kojto	112:6f327212ef96	3055	/**
Kojto	112:6f327212ef96	3056	* @}
Kojto	112:6f327212ef96	3057	*/
Kojto	112:6f327212ef96	3058
Kojto	112:6f327212ef96	3059	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	3060	* @{
Kojto	112:6f327212ef96	3061	*/
Kojto	112:6f327212ef96	3062
Kojto	112:6f327212ef96	3063	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto	112:6f327212ef96	3064	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto	112:6f327212ef96	3065	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto	112:6f327212ef96	3066	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto	112:6f327212ef96	3067	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto	112:6f327212ef96	3068	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto	112:6f327212ef96	3069	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto	112:6f327212ef96	3070
Kojto	112:6f327212ef96	3071	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto	112:6f327212ef96	3072	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto	112:6f327212ef96	3073	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto	112:6f327212ef96	3074	/**
Kojto	112:6f327212ef96	3075	* @}
Kojto	112:6f327212ef96	3076	*/
Kojto	112:6f327212ef96	3077
Kojto	112:6f327212ef96	3078	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	3079	* @{
Kojto	112:6f327212ef96	3080	*/
Kojto	112:6f327212ef96	3081	#define __HAL_LTDC_LAYER LTDC_LAYER
Kojto	112:6f327212ef96	3082	/**
Kojto	112:6f327212ef96	3083	* @}
Kojto	112:6f327212ef96	3084	*/
Kojto	112:6f327212ef96	3085
Kojto	112:6f327212ef96	3086	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	3087	* @{
Kojto	112:6f327212ef96	3088	*/
Kojto	112:6f327212ef96	3089	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto	112:6f327212ef96	3090	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto	112:6f327212ef96	3091	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto	112:6f327212ef96	3092	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto	112:6f327212ef96	3093	#define SAI_STREOMODE SAI_STEREOMODE
Kojto	122:f9eeca106725	3094	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto	122:f9eeca106725	3095	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto	122:f9eeca106725	3096	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto	122:f9eeca106725	3097	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto	122:f9eeca106725	3098	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto	122:f9eeca106725	3099	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto	122:f9eeca106725	3100	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto	122:f9eeca106725	3101	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
Kojto	122:f9eeca106725	3102	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
Kojto	112:6f327212ef96	3103	/**
Kojto	112:6f327212ef96	3104	* @}
Kojto	112:6f327212ef96	3105	*/
Kojto	112:6f327212ef96	3106
Kojto	112:6f327212ef96	3107
Kojto	112:6f327212ef96	3108	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto	112:6f327212ef96	3109	* @{
Kojto	112:6f327212ef96	3110	*/
Kojto	112:6f327212ef96	3111
Kojto	112:6f327212ef96	3112	/**
Kojto	112:6f327212ef96	3113	* @}
Kojto	112:6f327212ef96	3114	*/
Kojto	112:6f327212ef96	3115
Kojto	112:6f327212ef96	3116	#ifdef __cplusplus
Kojto	112:6f327212ef96	3117	}
Kojto	112:6f327212ef96	3118	#endif
Kojto	112:6f327212ef96	3119
Kojto	112:6f327212ef96	3120	#endif /* ___STM32_HAL_LEGACY */
Kojto	112:6f327212ef96	3121
Kojto	112:6f327212ef96	3122	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	112:6f327212ef96	3123