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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
TARGET_NUCLEO_F401RE/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device/stm32f401xe.h@128:9bcdf88f62b0
Child:
145:64910690c574
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32f401xe.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V2.5.0
<> 128:9bcdf88f62b0 6 * @date 22-April-2016
<> 128:9bcdf88f62b0 7 * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
<> 128:9bcdf88f62b0 8 *
<> 128:9bcdf88f62b0 9 * This file contains:
<> 128:9bcdf88f62b0 10 * - Data structures and the address mapping for all peripherals
<> 128:9bcdf88f62b0 11 * - peripherals registers declarations and bits definition
<> 128:9bcdf88f62b0 12 * - Macros to access peripheral's registers hardware
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 ******************************************************************************
<> 128:9bcdf88f62b0 15 * @attention
<> 128:9bcdf88f62b0 16 *
<> 128:9bcdf88f62b0 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 18 *
<> 128:9bcdf88f62b0 19 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 20 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 22 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 24 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 25 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 27 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 28 * without specific prior written permission.
<> 128:9bcdf88f62b0 29 *
<> 128:9bcdf88f62b0 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 40 *
<> 128:9bcdf88f62b0 41 ******************************************************************************
<> 128:9bcdf88f62b0 42 */
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 /** @addtogroup CMSIS
<> 128:9bcdf88f62b0 45 * @{
<> 128:9bcdf88f62b0 46 */
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /** @addtogroup stm32f401xe
<> 128:9bcdf88f62b0 49 * @{
<> 128:9bcdf88f62b0 50 */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #ifndef __STM32F401xE_H
<> 128:9bcdf88f62b0 53 #define __STM32F401xE_H
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 #ifdef __cplusplus
<> 128:9bcdf88f62b0 56 extern "C" {
<> 128:9bcdf88f62b0 57 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 /** @addtogroup Configuration_section_for_CMSIS
<> 128:9bcdf88f62b0 61 * @{
<> 128:9bcdf88f62b0 62 */
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /**
<> 128:9bcdf88f62b0 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 128:9bcdf88f62b0 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
<> 128:9bcdf88f62b0 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
<> 128:9bcdf88f62b0 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 128:9bcdf88f62b0 71 #ifndef __FPU_PRESENT
<> 128:9bcdf88f62b0 72 #define __FPU_PRESENT 1U /*!< FPU present */
<> 128:9bcdf88f62b0 73 #endif /* __FPU_PRESENT */
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 /**
<> 128:9bcdf88f62b0 76 * @}
<> 128:9bcdf88f62b0 77 */
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /** @addtogroup Peripheral_interrupt_number_definition
<> 128:9bcdf88f62b0 80 * @{
<> 128:9bcdf88f62b0 81 */
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 /**
<> 128:9bcdf88f62b0 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
<> 128:9bcdf88f62b0 85 * in @ref Library_configuration_section
<> 128:9bcdf88f62b0 86 */
<> 128:9bcdf88f62b0 87 typedef enum
<> 128:9bcdf88f62b0 88 {
<> 128:9bcdf88f62b0 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 128:9bcdf88f62b0 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 128:9bcdf88f62b0 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 128:9bcdf88f62b0 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 128:9bcdf88f62b0 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 128:9bcdf88f62b0 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 128:9bcdf88f62b0 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 128:9bcdf88f62b0 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 128:9bcdf88f62b0 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 128:9bcdf88f62b0 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 128:9bcdf88f62b0 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 128:9bcdf88f62b0 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 128:9bcdf88f62b0 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 128:9bcdf88f62b0 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 128:9bcdf88f62b0 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 128:9bcdf88f62b0 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 128:9bcdf88f62b0 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 128:9bcdf88f62b0 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 128:9bcdf88f62b0 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 128:9bcdf88f62b0 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 128:9bcdf88f62b0 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 128:9bcdf88f62b0 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 128:9bcdf88f62b0 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 128:9bcdf88f62b0 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 128:9bcdf88f62b0 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 128:9bcdf88f62b0 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 128:9bcdf88f62b0 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 128:9bcdf88f62b0 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 128:9bcdf88f62b0 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 128:9bcdf88f62b0 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 128:9bcdf88f62b0 119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 128:9bcdf88f62b0 120 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 128:9bcdf88f62b0 121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 128:9bcdf88f62b0 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 128:9bcdf88f62b0 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 128:9bcdf88f62b0 124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 128:9bcdf88f62b0 125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 128:9bcdf88f62b0 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 128:9bcdf88f62b0 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 128:9bcdf88f62b0 128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 128:9bcdf88f62b0 129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 128:9bcdf88f62b0 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 128:9bcdf88f62b0 131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 128:9bcdf88f62b0 132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 128:9bcdf88f62b0 133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 128:9bcdf88f62b0 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 128:9bcdf88f62b0 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 128:9bcdf88f62b0 136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 128:9bcdf88f62b0 137 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 128:9bcdf88f62b0 138 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
<> 128:9bcdf88f62b0 139 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 128:9bcdf88f62b0 140 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 128:9bcdf88f62b0 141 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 128:9bcdf88f62b0 142 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 128:9bcdf88f62b0 143 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 128:9bcdf88f62b0 144 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 128:9bcdf88f62b0 145 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 128:9bcdf88f62b0 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 128:9bcdf88f62b0 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 128:9bcdf88f62b0 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 128:9bcdf88f62b0 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 128:9bcdf88f62b0 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 128:9bcdf88f62b0 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 128:9bcdf88f62b0 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 128:9bcdf88f62b0 153 FPU_IRQn = 81, /*!< FPU global interrupt */
<> 128:9bcdf88f62b0 154 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
<> 128:9bcdf88f62b0 155 } IRQn_Type;
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 /**
<> 128:9bcdf88f62b0 158 * @}
<> 128:9bcdf88f62b0 159 */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 128:9bcdf88f62b0 162 #include "system_stm32f4xx.h"
<> 128:9bcdf88f62b0 163 #include <stdint.h>
<> 128:9bcdf88f62b0 164
<> 128:9bcdf88f62b0 165 /** @addtogroup Peripheral_registers_structures
<> 128:9bcdf88f62b0 166 * @{
<> 128:9bcdf88f62b0 167 */
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 /**
<> 128:9bcdf88f62b0 170 * @brief Analog to Digital Converter
<> 128:9bcdf88f62b0 171 */
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 typedef struct
<> 128:9bcdf88f62b0 174 {
<> 128:9bcdf88f62b0 175 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 128:9bcdf88f62b0 177 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 128:9bcdf88f62b0 178 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 179 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 128:9bcdf88f62b0 180 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 181 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 182 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 128:9bcdf88f62b0 183 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 128:9bcdf88f62b0 184 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 185 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 186 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 128:9bcdf88f62b0 187 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 128:9bcdf88f62b0 188 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 128:9bcdf88f62b0 189 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 128:9bcdf88f62b0 190 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 128:9bcdf88f62b0 191 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 128:9bcdf88f62b0 192 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 128:9bcdf88f62b0 193 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 128:9bcdf88f62b0 194 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 195 } ADC_TypeDef;
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 typedef struct
<> 128:9bcdf88f62b0 198 {
<> 128:9bcdf88f62b0 199 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 128:9bcdf88f62b0 200 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 128:9bcdf88f62b0 201 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 128:9bcdf88f62b0 202 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 128:9bcdf88f62b0 203 } ADC_Common_TypeDef;
<> 128:9bcdf88f62b0 204
<> 128:9bcdf88f62b0 205 /**
<> 128:9bcdf88f62b0 206 * @brief CRC calculation unit
<> 128:9bcdf88f62b0 207 */
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 typedef struct
<> 128:9bcdf88f62b0 210 {
<> 128:9bcdf88f62b0 211 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 212 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 213 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 128:9bcdf88f62b0 214 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 128:9bcdf88f62b0 215 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 216 } CRC_TypeDef;
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 /**
<> 128:9bcdf88f62b0 219 * @brief Debug MCU
<> 128:9bcdf88f62b0 220 */
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 typedef struct
<> 128:9bcdf88f62b0 223 {
<> 128:9bcdf88f62b0 224 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 128:9bcdf88f62b0 225 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 226 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 227 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 228 }DBGMCU_TypeDef;
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230
<> 128:9bcdf88f62b0 231 /**
<> 128:9bcdf88f62b0 232 * @brief DMA Controller
<> 128:9bcdf88f62b0 233 */
<> 128:9bcdf88f62b0 234
<> 128:9bcdf88f62b0 235 typedef struct
<> 128:9bcdf88f62b0 236 {
<> 128:9bcdf88f62b0 237 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 128:9bcdf88f62b0 238 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 128:9bcdf88f62b0 239 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 128:9bcdf88f62b0 240 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 128:9bcdf88f62b0 241 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 128:9bcdf88f62b0 242 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 128:9bcdf88f62b0 243 } DMA_Stream_TypeDef;
<> 128:9bcdf88f62b0 244
<> 128:9bcdf88f62b0 245 typedef struct
<> 128:9bcdf88f62b0 246 {
<> 128:9bcdf88f62b0 247 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 248 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 249 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 250 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 251 } DMA_TypeDef;
<> 128:9bcdf88f62b0 252
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 /**
<> 128:9bcdf88f62b0 255 * @brief External Interrupt/Event Controller
<> 128:9bcdf88f62b0 256 */
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 typedef struct
<> 128:9bcdf88f62b0 259 {
<> 128:9bcdf88f62b0 260 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 261 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 262 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 263 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 264 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 265 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 266 } EXTI_TypeDef;
<> 128:9bcdf88f62b0 267
<> 128:9bcdf88f62b0 268 /**
<> 128:9bcdf88f62b0 269 * @brief FLASH Registers
<> 128:9bcdf88f62b0 270 */
<> 128:9bcdf88f62b0 271
<> 128:9bcdf88f62b0 272 typedef struct
<> 128:9bcdf88f62b0 273 {
<> 128:9bcdf88f62b0 274 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 275 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 276 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 277 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 278 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 279 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 128:9bcdf88f62b0 280 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 281 } FLASH_TypeDef;
<> 128:9bcdf88f62b0 282
<> 128:9bcdf88f62b0 283 /**
<> 128:9bcdf88f62b0 284 * @brief General Purpose I/O
<> 128:9bcdf88f62b0 285 */
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 typedef struct
<> 128:9bcdf88f62b0 288 {
<> 128:9bcdf88f62b0 289 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 290 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 291 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 292 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 293 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 294 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 295 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 296 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 297 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 128:9bcdf88f62b0 298 } GPIO_TypeDef;
<> 128:9bcdf88f62b0 299
<> 128:9bcdf88f62b0 300 /**
<> 128:9bcdf88f62b0 301 * @brief System configuration controller
<> 128:9bcdf88f62b0 302 */
<> 128:9bcdf88f62b0 303
<> 128:9bcdf88f62b0 304 typedef struct
<> 128:9bcdf88f62b0 305 {
<> 128:9bcdf88f62b0 306 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 307 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 308 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 128:9bcdf88f62b0 309 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
<> 128:9bcdf88f62b0 310 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 311 } SYSCFG_TypeDef;
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /**
<> 128:9bcdf88f62b0 314 * @brief Inter-integrated Circuit Interface
<> 128:9bcdf88f62b0 315 */
<> 128:9bcdf88f62b0 316
<> 128:9bcdf88f62b0 317 typedef struct
<> 128:9bcdf88f62b0 318 {
<> 128:9bcdf88f62b0 319 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 320 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 321 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 128:9bcdf88f62b0 322 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 128:9bcdf88f62b0 323 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 324 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 325 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 326 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 327 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 328 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 329 } I2C_TypeDef;
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 /**
<> 128:9bcdf88f62b0 332 * @brief Independent WATCHDOG
<> 128:9bcdf88f62b0 333 */
<> 128:9bcdf88f62b0 334
<> 128:9bcdf88f62b0 335 typedef struct
<> 128:9bcdf88f62b0 336 {
<> 128:9bcdf88f62b0 337 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 338 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 339 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 340 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 341 } IWDG_TypeDef;
<> 128:9bcdf88f62b0 342
<> 128:9bcdf88f62b0 343 /**
<> 128:9bcdf88f62b0 344 * @brief Power Control
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 typedef struct
<> 128:9bcdf88f62b0 348 {
<> 128:9bcdf88f62b0 349 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 350 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 351 } PWR_TypeDef;
<> 128:9bcdf88f62b0 352
<> 128:9bcdf88f62b0 353 /**
<> 128:9bcdf88f62b0 354 * @brief Reset and Clock Control
<> 128:9bcdf88f62b0 355 */
<> 128:9bcdf88f62b0 356
<> 128:9bcdf88f62b0 357 typedef struct
<> 128:9bcdf88f62b0 358 {
<> 128:9bcdf88f62b0 359 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 360 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 361 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 362 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 363 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 364 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 365 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 366 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 128:9bcdf88f62b0 367 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 368 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 369 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 128:9bcdf88f62b0 370 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 371 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 372 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 373 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 128:9bcdf88f62b0 374 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 375 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 376 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 128:9bcdf88f62b0 377 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 378 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 128:9bcdf88f62b0 379 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 128:9bcdf88f62b0 380 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 128:9bcdf88f62b0 381 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 128:9bcdf88f62b0 382 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 128:9bcdf88f62b0 383 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 128:9bcdf88f62b0 384 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 128:9bcdf88f62b0 385 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 128:9bcdf88f62b0 386 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 128:9bcdf88f62b0 387 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 388 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 128:9bcdf88f62b0 389 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
<> 128:9bcdf88f62b0 390 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
<> 128:9bcdf88f62b0 391 } RCC_TypeDef;
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /**
<> 128:9bcdf88f62b0 394 * @brief Real-Time Clock
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396
<> 128:9bcdf88f62b0 397 typedef struct
<> 128:9bcdf88f62b0 398 {
<> 128:9bcdf88f62b0 399 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 400 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 401 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 402 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 403 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 404 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 405 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 406 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 407 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 408 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 409 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 410 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 411 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 412 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 413 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 414 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 415 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 416 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 417 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 418 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 128:9bcdf88f62b0 419 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
<> 128:9bcdf88f62b0 420 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 128:9bcdf88f62b0 421 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 128:9bcdf88f62b0 422 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 128:9bcdf88f62b0 423 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 128:9bcdf88f62b0 424 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 128:9bcdf88f62b0 425 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 128:9bcdf88f62b0 426 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 128:9bcdf88f62b0 427 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 128:9bcdf88f62b0 428 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 128:9bcdf88f62b0 429 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 128:9bcdf88f62b0 430 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 128:9bcdf88f62b0 431 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 128:9bcdf88f62b0 432 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 128:9bcdf88f62b0 433 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 128:9bcdf88f62b0 434 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 128:9bcdf88f62b0 435 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 128:9bcdf88f62b0 436 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 128:9bcdf88f62b0 437 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 128:9bcdf88f62b0 438 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 128:9bcdf88f62b0 439 } RTC_TypeDef;
<> 128:9bcdf88f62b0 440
<> 128:9bcdf88f62b0 441
<> 128:9bcdf88f62b0 442 /**
<> 128:9bcdf88f62b0 443 * @brief SD host Interface
<> 128:9bcdf88f62b0 444 */
<> 128:9bcdf88f62b0 445
<> 128:9bcdf88f62b0 446 typedef struct
<> 128:9bcdf88f62b0 447 {
<> 128:9bcdf88f62b0 448 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 449 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 450 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 451 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 452 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 453 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 454 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 455 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 456 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 457 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 458 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 459 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 460 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 461 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 462 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 463 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 464 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 128:9bcdf88f62b0 465 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 466 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 128:9bcdf88f62b0 467 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 468 } SDIO_TypeDef;
<> 128:9bcdf88f62b0 469
<> 128:9bcdf88f62b0 470 /**
<> 128:9bcdf88f62b0 471 * @brief Serial Peripheral Interface
<> 128:9bcdf88f62b0 472 */
<> 128:9bcdf88f62b0 473
<> 128:9bcdf88f62b0 474 typedef struct
<> 128:9bcdf88f62b0 475 {
<> 128:9bcdf88f62b0 476 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 128:9bcdf88f62b0 477 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 478 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 479 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 480 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 128:9bcdf88f62b0 481 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 128:9bcdf88f62b0 482 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 128:9bcdf88f62b0 483 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 484 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 485 } SPI_TypeDef;
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487 /**
<> 128:9bcdf88f62b0 488 * @brief TIM
<> 128:9bcdf88f62b0 489 */
<> 128:9bcdf88f62b0 490
<> 128:9bcdf88f62b0 491 typedef struct
<> 128:9bcdf88f62b0 492 {
<> 128:9bcdf88f62b0 493 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 494 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 495 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 496 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 497 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 498 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 499 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 500 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 128:9bcdf88f62b0 501 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 502 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 503 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 128:9bcdf88f62b0 504 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 505 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 506 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 128:9bcdf88f62b0 507 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 128:9bcdf88f62b0 508 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 128:9bcdf88f62b0 509 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 128:9bcdf88f62b0 510 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 511 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 512 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 128:9bcdf88f62b0 513 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 514 } TIM_TypeDef;
<> 128:9bcdf88f62b0 515
<> 128:9bcdf88f62b0 516 /**
<> 128:9bcdf88f62b0 517 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 128:9bcdf88f62b0 518 */
<> 128:9bcdf88f62b0 519
<> 128:9bcdf88f62b0 520 typedef struct
<> 128:9bcdf88f62b0 521 {
<> 128:9bcdf88f62b0 522 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 523 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 524 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 525 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 526 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 128:9bcdf88f62b0 527 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 128:9bcdf88f62b0 528 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 529 } USART_TypeDef;
<> 128:9bcdf88f62b0 530
<> 128:9bcdf88f62b0 531 /**
<> 128:9bcdf88f62b0 532 * @brief Window WATCHDOG
<> 128:9bcdf88f62b0 533 */
<> 128:9bcdf88f62b0 534
<> 128:9bcdf88f62b0 535 typedef struct
<> 128:9bcdf88f62b0 536 {
<> 128:9bcdf88f62b0 537 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 538 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 539 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 540 } WWDG_TypeDef;
<> 128:9bcdf88f62b0 541
<> 128:9bcdf88f62b0 542 /**
<> 128:9bcdf88f62b0 543 * @brief __USB_OTG_Core_register
<> 128:9bcdf88f62b0 544 */
<> 128:9bcdf88f62b0 545 typedef struct
<> 128:9bcdf88f62b0 546 {
<> 128:9bcdf88f62b0 547 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
<> 128:9bcdf88f62b0 548 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
<> 128:9bcdf88f62b0 549 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
<> 128:9bcdf88f62b0 550 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
<> 128:9bcdf88f62b0 551 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
<> 128:9bcdf88f62b0 552 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
<> 128:9bcdf88f62b0 553 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
<> 128:9bcdf88f62b0 554 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
<> 128:9bcdf88f62b0 555 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
<> 128:9bcdf88f62b0 556 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
<> 128:9bcdf88f62b0 557 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
<> 128:9bcdf88f62b0 558 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
<> 128:9bcdf88f62b0 559 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
<> 128:9bcdf88f62b0 560 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
<> 128:9bcdf88f62b0 561 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
<> 128:9bcdf88f62b0 562 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
<> 128:9bcdf88f62b0 563 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
<> 128:9bcdf88f62b0 564 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
<> 128:9bcdf88f62b0 565 }
<> 128:9bcdf88f62b0 566 USB_OTG_GlobalTypeDef;
<> 128:9bcdf88f62b0 567
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569
<> 128:9bcdf88f62b0 570 /**
<> 128:9bcdf88f62b0 571 * @brief __device_Registers
<> 128:9bcdf88f62b0 572 */
<> 128:9bcdf88f62b0 573 typedef struct
<> 128:9bcdf88f62b0 574 {
<> 128:9bcdf88f62b0 575 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
<> 128:9bcdf88f62b0 576 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
<> 128:9bcdf88f62b0 577 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
<> 128:9bcdf88f62b0 578 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
<> 128:9bcdf88f62b0 579 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
<> 128:9bcdf88f62b0 580 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
<> 128:9bcdf88f62b0 581 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
<> 128:9bcdf88f62b0 582 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
<> 128:9bcdf88f62b0 583 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
<> 128:9bcdf88f62b0 584 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
<> 128:9bcdf88f62b0 585 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
<> 128:9bcdf88f62b0 586 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
<> 128:9bcdf88f62b0 587 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
<> 128:9bcdf88f62b0 588 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
<> 128:9bcdf88f62b0 589 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
<> 128:9bcdf88f62b0 590 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
<> 128:9bcdf88f62b0 591 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
<> 128:9bcdf88f62b0 592 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
<> 128:9bcdf88f62b0 593 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
<> 128:9bcdf88f62b0 594 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
<> 128:9bcdf88f62b0 595 }
<> 128:9bcdf88f62b0 596 USB_OTG_DeviceTypeDef;
<> 128:9bcdf88f62b0 597
<> 128:9bcdf88f62b0 598
<> 128:9bcdf88f62b0 599 /**
<> 128:9bcdf88f62b0 600 * @brief __IN_Endpoint-Specific_Register
<> 128:9bcdf88f62b0 601 */
<> 128:9bcdf88f62b0 602 typedef struct
<> 128:9bcdf88f62b0 603 {
<> 128:9bcdf88f62b0 604 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
<> 128:9bcdf88f62b0 605 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
<> 128:9bcdf88f62b0 606 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
<> 128:9bcdf88f62b0 607 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
<> 128:9bcdf88f62b0 608 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
<> 128:9bcdf88f62b0 609 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
<> 128:9bcdf88f62b0 610 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
<> 128:9bcdf88f62b0 611 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
<> 128:9bcdf88f62b0 612 }
<> 128:9bcdf88f62b0 613 USB_OTG_INEndpointTypeDef;
<> 128:9bcdf88f62b0 614
<> 128:9bcdf88f62b0 615
<> 128:9bcdf88f62b0 616 /**
<> 128:9bcdf88f62b0 617 * @brief __OUT_Endpoint-Specific_Registers
<> 128:9bcdf88f62b0 618 */
<> 128:9bcdf88f62b0 619 typedef struct
<> 128:9bcdf88f62b0 620 {
<> 128:9bcdf88f62b0 621 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
<> 128:9bcdf88f62b0 622 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
<> 128:9bcdf88f62b0 623 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
<> 128:9bcdf88f62b0 624 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
<> 128:9bcdf88f62b0 625 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
<> 128:9bcdf88f62b0 626 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
<> 128:9bcdf88f62b0 627 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
<> 128:9bcdf88f62b0 628 }
<> 128:9bcdf88f62b0 629 USB_OTG_OUTEndpointTypeDef;
<> 128:9bcdf88f62b0 630
<> 128:9bcdf88f62b0 631
<> 128:9bcdf88f62b0 632 /**
<> 128:9bcdf88f62b0 633 * @brief __Host_Mode_Register_Structures
<> 128:9bcdf88f62b0 634 */
<> 128:9bcdf88f62b0 635 typedef struct
<> 128:9bcdf88f62b0 636 {
<> 128:9bcdf88f62b0 637 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
<> 128:9bcdf88f62b0 638 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
<> 128:9bcdf88f62b0 639 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
<> 128:9bcdf88f62b0 640 uint32_t Reserved40C; /* Reserved 40Ch*/
<> 128:9bcdf88f62b0 641 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
<> 128:9bcdf88f62b0 642 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
<> 128:9bcdf88f62b0 643 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
<> 128:9bcdf88f62b0 644 }
<> 128:9bcdf88f62b0 645 USB_OTG_HostTypeDef;
<> 128:9bcdf88f62b0 646
<> 128:9bcdf88f62b0 647
<> 128:9bcdf88f62b0 648 /**
<> 128:9bcdf88f62b0 649 * @brief __Host_Channel_Specific_Registers
<> 128:9bcdf88f62b0 650 */
<> 128:9bcdf88f62b0 651 typedef struct
<> 128:9bcdf88f62b0 652 {
<> 128:9bcdf88f62b0 653 __IO uint32_t HCCHAR;
<> 128:9bcdf88f62b0 654 __IO uint32_t HCSPLT;
<> 128:9bcdf88f62b0 655 __IO uint32_t HCINT;
<> 128:9bcdf88f62b0 656 __IO uint32_t HCINTMSK;
<> 128:9bcdf88f62b0 657 __IO uint32_t HCTSIZ;
<> 128:9bcdf88f62b0 658 __IO uint32_t HCDMA;
<> 128:9bcdf88f62b0 659 uint32_t Reserved[2];
<> 128:9bcdf88f62b0 660 }
<> 128:9bcdf88f62b0 661 USB_OTG_HostChannelTypeDef;
<> 128:9bcdf88f62b0 662
<> 128:9bcdf88f62b0 663 /**
<> 128:9bcdf88f62b0 664 * @brief Peripheral_memory_map
<> 128:9bcdf88f62b0 665 */
<> 128:9bcdf88f62b0 666 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
<> 128:9bcdf88f62b0 667 #define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */
<> 128:9bcdf88f62b0 668 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 128:9bcdf88f62b0 669 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
<> 128:9bcdf88f62b0 670 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */
<> 128:9bcdf88f62b0 671 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
<> 128:9bcdf88f62b0 672 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
<> 128:9bcdf88f62b0 673 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
<> 128:9bcdf88f62b0 674
<> 128:9bcdf88f62b0 675 /* Legacy defines */
<> 128:9bcdf88f62b0 676 #define SRAM_BASE SRAM1_BASE
<> 128:9bcdf88f62b0 677 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 128:9bcdf88f62b0 678
<> 128:9bcdf88f62b0 679
<> 128:9bcdf88f62b0 680 /*!< Peripheral memory map */
<> 128:9bcdf88f62b0 681 #define APB1PERIPH_BASE PERIPH_BASE
<> 128:9bcdf88f62b0 682 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 128:9bcdf88f62b0 683 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 128:9bcdf88f62b0 684 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 128:9bcdf88f62b0 685
<> 128:9bcdf88f62b0 686 /*!< APB1 peripherals */
<> 128:9bcdf88f62b0 687 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 688 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 689 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 690 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 691 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 128:9bcdf88f62b0 692 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 693 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 694 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
<> 128:9bcdf88f62b0 695 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 696 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 697 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 698 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 699 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 128:9bcdf88f62b0 700 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 128:9bcdf88f62b0 701 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 128:9bcdf88f62b0 702 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 128:9bcdf88f62b0 703
<> 128:9bcdf88f62b0 704 /*!< APB2 peripherals */
<> 128:9bcdf88f62b0 705 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 706 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 707 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 128:9bcdf88f62b0 708 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 128:9bcdf88f62b0 709 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 128:9bcdf88f62b0 710 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 711 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 712 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 128:9bcdf88f62b0 713 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 714 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 715 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 716 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 717 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 128:9bcdf88f62b0 718
<> 128:9bcdf88f62b0 719 /*!< AHB1 peripherals */
<> 128:9bcdf88f62b0 720 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 721 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 722 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 723 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 724 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 725 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 128:9bcdf88f62b0 726 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 727 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 728 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 729 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 128:9bcdf88f62b0 730 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 128:9bcdf88f62b0 731 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 128:9bcdf88f62b0 732 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 128:9bcdf88f62b0 733 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 128:9bcdf88f62b0 734 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 128:9bcdf88f62b0 735 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 128:9bcdf88f62b0 736 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 128:9bcdf88f62b0 737 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 128:9bcdf88f62b0 738 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 128:9bcdf88f62b0 739 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 128:9bcdf88f62b0 740 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 128:9bcdf88f62b0 741 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 128:9bcdf88f62b0 742 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 128:9bcdf88f62b0 743 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 128:9bcdf88f62b0 744 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 128:9bcdf88f62b0 745 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 128:9bcdf88f62b0 746 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 128:9bcdf88f62b0 747
<> 128:9bcdf88f62b0 748 /* Debug MCU registers base address */
<> 128:9bcdf88f62b0 749 #define DBGMCU_BASE 0xE0042000U
<> 128:9bcdf88f62b0 750
<> 128:9bcdf88f62b0 751 /*!< USB registers base address */
<> 128:9bcdf88f62b0 752 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 128:9bcdf88f62b0 753
<> 128:9bcdf88f62b0 754 #define USB_OTG_GLOBAL_BASE 0x000U
<> 128:9bcdf88f62b0 755 #define USB_OTG_DEVICE_BASE 0x800U
<> 128:9bcdf88f62b0 756 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 128:9bcdf88f62b0 757 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 128:9bcdf88f62b0 758 #define USB_OTG_EP_REG_SIZE 0x20U
<> 128:9bcdf88f62b0 759 #define USB_OTG_HOST_BASE 0x400U
<> 128:9bcdf88f62b0 760 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 128:9bcdf88f62b0 761 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 128:9bcdf88f62b0 762 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 128:9bcdf88f62b0 763 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 128:9bcdf88f62b0 764 #define USB_OTG_FIFO_BASE 0x1000U
<> 128:9bcdf88f62b0 765 #define USB_OTG_FIFO_SIZE 0x1000U
<> 128:9bcdf88f62b0 766
<> 128:9bcdf88f62b0 767 /**
<> 128:9bcdf88f62b0 768 * @}
<> 128:9bcdf88f62b0 769 */
<> 128:9bcdf88f62b0 770
<> 128:9bcdf88f62b0 771 /** @addtogroup Peripheral_declaration
<> 128:9bcdf88f62b0 772 * @{
<> 128:9bcdf88f62b0 773 */
<> 128:9bcdf88f62b0 774 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 128:9bcdf88f62b0 775 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 128:9bcdf88f62b0 776 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 128:9bcdf88f62b0 777 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 128:9bcdf88f62b0 778 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 128:9bcdf88f62b0 779 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 128:9bcdf88f62b0 780 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 128:9bcdf88f62b0 781 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
<> 128:9bcdf88f62b0 782 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 128:9bcdf88f62b0 783 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 128:9bcdf88f62b0 784 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
<> 128:9bcdf88f62b0 785 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 128:9bcdf88f62b0 786 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 128:9bcdf88f62b0 787 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 128:9bcdf88f62b0 788 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 128:9bcdf88f62b0 789 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 128:9bcdf88f62b0 790 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 128:9bcdf88f62b0 791 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 128:9bcdf88f62b0 792 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 128:9bcdf88f62b0 793 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
<> 128:9bcdf88f62b0 794 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 128:9bcdf88f62b0 795 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
<> 128:9bcdf88f62b0 796 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 128:9bcdf88f62b0 797 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 128:9bcdf88f62b0 798 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 128:9bcdf88f62b0 799 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 128:9bcdf88f62b0 800 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 128:9bcdf88f62b0 801 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 128:9bcdf88f62b0 802 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 128:9bcdf88f62b0 803 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 128:9bcdf88f62b0 804 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 128:9bcdf88f62b0 805 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 128:9bcdf88f62b0 806 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 128:9bcdf88f62b0 807 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 128:9bcdf88f62b0 808 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 128:9bcdf88f62b0 809 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 128:9bcdf88f62b0 810 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 128:9bcdf88f62b0 811 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 128:9bcdf88f62b0 812 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 128:9bcdf88f62b0 813 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 128:9bcdf88f62b0 814 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 128:9bcdf88f62b0 815 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 128:9bcdf88f62b0 816 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 128:9bcdf88f62b0 817 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 128:9bcdf88f62b0 818 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 128:9bcdf88f62b0 819 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 128:9bcdf88f62b0 820 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 128:9bcdf88f62b0 821 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 128:9bcdf88f62b0 822 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 128:9bcdf88f62b0 823 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 128:9bcdf88f62b0 824 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 128:9bcdf88f62b0 825 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 128:9bcdf88f62b0 826 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 128:9bcdf88f62b0 827 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 128:9bcdf88f62b0 828 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 128:9bcdf88f62b0 829 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 128:9bcdf88f62b0 830
<> 128:9bcdf88f62b0 831 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 128:9bcdf88f62b0 832
<> 128:9bcdf88f62b0 833 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 128:9bcdf88f62b0 834
<> 128:9bcdf88f62b0 835 /**
<> 128:9bcdf88f62b0 836 * @}
<> 128:9bcdf88f62b0 837 */
<> 128:9bcdf88f62b0 838
<> 128:9bcdf88f62b0 839 /** @addtogroup Exported_constants
<> 128:9bcdf88f62b0 840 * @{
<> 128:9bcdf88f62b0 841 */
<> 128:9bcdf88f62b0 842
<> 128:9bcdf88f62b0 843 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 128:9bcdf88f62b0 844 * @{
<> 128:9bcdf88f62b0 845 */
<> 128:9bcdf88f62b0 846
<> 128:9bcdf88f62b0 847 /******************************************************************************/
<> 128:9bcdf88f62b0 848 /* Peripheral Registers_Bits_Definition */
<> 128:9bcdf88f62b0 849 /******************************************************************************/
<> 128:9bcdf88f62b0 850
<> 128:9bcdf88f62b0 851 /******************************************************************************/
<> 128:9bcdf88f62b0 852 /* */
<> 128:9bcdf88f62b0 853 /* Analog to Digital Converter */
<> 128:9bcdf88f62b0 854 /* */
<> 128:9bcdf88f62b0 855 /******************************************************************************/
<> 128:9bcdf88f62b0 856 /******************** Bit definition for ADC_SR register ********************/
<> 128:9bcdf88f62b0 857 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 128:9bcdf88f62b0 858 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 128:9bcdf88f62b0 859 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 128:9bcdf88f62b0 860 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 128:9bcdf88f62b0 861 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 128:9bcdf88f62b0 862 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
<> 128:9bcdf88f62b0 863
<> 128:9bcdf88f62b0 864 /******************* Bit definition for ADC_CR1 register ********************/
<> 128:9bcdf88f62b0 865 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 128:9bcdf88f62b0 866 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 867 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 868 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 869 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 870 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 871 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 128:9bcdf88f62b0 872 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 128:9bcdf88f62b0 873 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 128:9bcdf88f62b0 874 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 128:9bcdf88f62b0 875 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 128:9bcdf88f62b0 876 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 128:9bcdf88f62b0 877 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 128:9bcdf88f62b0 878 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 128:9bcdf88f62b0 879 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 128:9bcdf88f62b0 880 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 881 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 882 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 883 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 128:9bcdf88f62b0 884 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 128:9bcdf88f62b0 885 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 128:9bcdf88f62b0 886 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 887 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 888 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
<> 128:9bcdf88f62b0 889
<> 128:9bcdf88f62b0 890 /******************* Bit definition for ADC_CR2 register ********************/
<> 128:9bcdf88f62b0 891 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 128:9bcdf88f62b0 892 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 128:9bcdf88f62b0 893 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 128:9bcdf88f62b0 894 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 128:9bcdf88f62b0 895 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 128:9bcdf88f62b0 896 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 128:9bcdf88f62b0 897 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 128:9bcdf88f62b0 898 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 899 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 900 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 901 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 902 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 128:9bcdf88f62b0 903 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 904 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 905 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 128:9bcdf88f62b0 906 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 128:9bcdf88f62b0 907 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 908 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 909 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 910 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 911 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 128:9bcdf88f62b0 912 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 913 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 914 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
<> 128:9bcdf88f62b0 915
<> 128:9bcdf88f62b0 916 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 128:9bcdf88f62b0 917 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 128:9bcdf88f62b0 918 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 919 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 920 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 921 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 128:9bcdf88f62b0 922 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 128:9bcdf88f62b0 923 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 128:9bcdf88f62b0 924 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 128:9bcdf88f62b0 925 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 128:9bcdf88f62b0 926 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 128:9bcdf88f62b0 927 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 128:9bcdf88f62b0 928 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 128:9bcdf88f62b0 929 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 128:9bcdf88f62b0 930 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 128:9bcdf88f62b0 931 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 128:9bcdf88f62b0 932 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 128:9bcdf88f62b0 933 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 128:9bcdf88f62b0 934 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 935 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 936 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 937 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 128:9bcdf88f62b0 938 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 939 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 940 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 941 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 128:9bcdf88f62b0 942 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 943 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 944 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 945 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 128:9bcdf88f62b0 946 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 947 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 948 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 949 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 128:9bcdf88f62b0 950 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 951 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 952 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 953
<> 128:9bcdf88f62b0 954 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 128:9bcdf88f62b0 955 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 128:9bcdf88f62b0 956 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 957 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 958 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 959 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 128:9bcdf88f62b0 960 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 128:9bcdf88f62b0 961 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 128:9bcdf88f62b0 962 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 128:9bcdf88f62b0 963 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 128:9bcdf88f62b0 964 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 128:9bcdf88f62b0 965 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 128:9bcdf88f62b0 966 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 128:9bcdf88f62b0 967 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 128:9bcdf88f62b0 968 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 128:9bcdf88f62b0 969 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 128:9bcdf88f62b0 970 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 128:9bcdf88f62b0 971 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 128:9bcdf88f62b0 972 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 973 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 974 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 975 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 128:9bcdf88f62b0 976 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 977 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 978 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 979 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 128:9bcdf88f62b0 980 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 981 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 982 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 983 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 128:9bcdf88f62b0 984 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 985 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 986 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 987 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 128:9bcdf88f62b0 988 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 989 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 990 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 991 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 128:9bcdf88f62b0 992 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 993 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 994 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 995
<> 128:9bcdf88f62b0 996 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 128:9bcdf88f62b0 997 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
<> 128:9bcdf88f62b0 998
<> 128:9bcdf88f62b0 999 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 128:9bcdf88f62b0 1000 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
<> 128:9bcdf88f62b0 1001
<> 128:9bcdf88f62b0 1002 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 128:9bcdf88f62b0 1003 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
<> 128:9bcdf88f62b0 1004
<> 128:9bcdf88f62b0 1005 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 128:9bcdf88f62b0 1006 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
<> 128:9bcdf88f62b0 1007
<> 128:9bcdf88f62b0 1008 /******************* Bit definition for ADC_HTR register ********************/
<> 128:9bcdf88f62b0 1009 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
<> 128:9bcdf88f62b0 1010
<> 128:9bcdf88f62b0 1011 /******************* Bit definition for ADC_LTR register ********************/
<> 128:9bcdf88f62b0 1012 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
<> 128:9bcdf88f62b0 1013
<> 128:9bcdf88f62b0 1014 /******************* Bit definition for ADC_SQR1 register *******************/
<> 128:9bcdf88f62b0 1015 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1016 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1017 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1018 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1019 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1020 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1021 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1022 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1023 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1024 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1025 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1026 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1027 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1028 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1029 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1030 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1031 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1032 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1033 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1034 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1035 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1036 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1037 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1038 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1039 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 128:9bcdf88f62b0 1040 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1041 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1042 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1043 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1044
<> 128:9bcdf88f62b0 1045 /******************* Bit definition for ADC_SQR2 register *******************/
<> 128:9bcdf88f62b0 1046 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1047 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1048 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1049 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1050 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1051 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1052 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1053 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1054 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1055 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1056 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1057 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1058 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1059 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1060 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1061 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1062 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1063 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1064 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1065 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1066 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1067 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1068 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1069 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1070 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1071 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1072 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1073 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1074 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1075 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1076 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1077 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1078 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1079 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1080 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1081 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1082
<> 128:9bcdf88f62b0 1083 /******************* Bit definition for ADC_SQR3 register *******************/
<> 128:9bcdf88f62b0 1084 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 128:9bcdf88f62b0 1085 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1086 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1087 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1088 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1089 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1090 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 128:9bcdf88f62b0 1091 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1092 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1093 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1094 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1095 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1096 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 128:9bcdf88f62b0 1097 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1098 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1099 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1100 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1101 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1102 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1103 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1104 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1105 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1106 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1107 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1108 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1109 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1110 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1111 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1112 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1113 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1114 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 128:9bcdf88f62b0 1115 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1116 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1117 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1118 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1119 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1120
<> 128:9bcdf88f62b0 1121 /******************* Bit definition for ADC_JSQR register *******************/
<> 128:9bcdf88f62b0 1122 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 128:9bcdf88f62b0 1123 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1124 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1125 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1126 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1127 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1128 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 128:9bcdf88f62b0 1129 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1130 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1131 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1132 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1133 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1134 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 128:9bcdf88f62b0 1135 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1136 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1137 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1138 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1139 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1140 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 128:9bcdf88f62b0 1141 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1142 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1143 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1144 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1145 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1146 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 128:9bcdf88f62b0 1147 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1148 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1149
<> 128:9bcdf88f62b0 1150 /******************* Bit definition for ADC_JDR1 register *******************/
<> 128:9bcdf88f62b0 1151 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
<> 128:9bcdf88f62b0 1152
<> 128:9bcdf88f62b0 1153 /******************* Bit definition for ADC_JDR2 register *******************/
<> 128:9bcdf88f62b0 1154 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
<> 128:9bcdf88f62b0 1155
<> 128:9bcdf88f62b0 1156 /******************* Bit definition for ADC_JDR3 register *******************/
<> 128:9bcdf88f62b0 1157 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
<> 128:9bcdf88f62b0 1158
<> 128:9bcdf88f62b0 1159 /******************* Bit definition for ADC_JDR4 register *******************/
<> 128:9bcdf88f62b0 1160 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
<> 128:9bcdf88f62b0 1161
<> 128:9bcdf88f62b0 1162 /******************** Bit definition for ADC_DR register ********************/
<> 128:9bcdf88f62b0 1163 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 128:9bcdf88f62b0 1164 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
<> 128:9bcdf88f62b0 1165
<> 128:9bcdf88f62b0 1166 /******************* Bit definition for ADC_CSR register ********************/
<> 128:9bcdf88f62b0 1167 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 128:9bcdf88f62b0 1168 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 128:9bcdf88f62b0 1169 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 128:9bcdf88f62b0 1170 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 128:9bcdf88f62b0 1171 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 128:9bcdf88f62b0 1172 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
<> 128:9bcdf88f62b0 1173 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 128:9bcdf88f62b0 1174 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 128:9bcdf88f62b0 1175 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 128:9bcdf88f62b0 1176 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 128:9bcdf88f62b0 1177 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 128:9bcdf88f62b0 1178 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
<> 128:9bcdf88f62b0 1179 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 128:9bcdf88f62b0 1180 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 128:9bcdf88f62b0 1181 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 128:9bcdf88f62b0 1182 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 128:9bcdf88f62b0 1183 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 128:9bcdf88f62b0 1184 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
<> 128:9bcdf88f62b0 1185
<> 128:9bcdf88f62b0 1186 /* Legacy defines */
<> 128:9bcdf88f62b0 1187 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 128:9bcdf88f62b0 1188 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 128:9bcdf88f62b0 1189 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 128:9bcdf88f62b0 1190
<> 128:9bcdf88f62b0 1191 /******************* Bit definition for ADC_CCR register ********************/
<> 128:9bcdf88f62b0 1192 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 128:9bcdf88f62b0 1193 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1194 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1195 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1196 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1197 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 1198 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 128:9bcdf88f62b0 1199 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1200 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1201 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 128:9bcdf88f62b0 1202 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 128:9bcdf88f62b0 1203 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 128:9bcdf88f62b0 1204 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 128:9bcdf88f62b0 1205 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1206 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1207 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 128:9bcdf88f62b0 1208 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 1209 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 1210 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 128:9bcdf88f62b0 1211 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
<> 128:9bcdf88f62b0 1212
<> 128:9bcdf88f62b0 1213 /******************* Bit definition for ADC_CDR register ********************/
<> 128:9bcdf88f62b0 1214 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 128:9bcdf88f62b0 1215 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
<> 128:9bcdf88f62b0 1216
<> 128:9bcdf88f62b0 1217 /******************************************************************************/
<> 128:9bcdf88f62b0 1218 /* */
<> 128:9bcdf88f62b0 1219 /* CRC calculation unit */
<> 128:9bcdf88f62b0 1220 /* */
<> 128:9bcdf88f62b0 1221 /******************************************************************************/
<> 128:9bcdf88f62b0 1222 /******************* Bit definition for CRC_DR register *********************/
<> 128:9bcdf88f62b0 1223 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
<> 128:9bcdf88f62b0 1224
<> 128:9bcdf88f62b0 1225
<> 128:9bcdf88f62b0 1226 /******************* Bit definition for CRC_IDR register ********************/
<> 128:9bcdf88f62b0 1227 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
<> 128:9bcdf88f62b0 1228
<> 128:9bcdf88f62b0 1229
<> 128:9bcdf88f62b0 1230 /******************** Bit definition for CRC_CR register ********************/
<> 128:9bcdf88f62b0 1231 #define CRC_CR_RESET 0x01U /*!< RESET bit */
<> 128:9bcdf88f62b0 1232
<> 128:9bcdf88f62b0 1233 /******************************************************************************/
<> 128:9bcdf88f62b0 1234 /* */
<> 128:9bcdf88f62b0 1235 /* Debug MCU */
<> 128:9bcdf88f62b0 1236 /* */
<> 128:9bcdf88f62b0 1237 /******************************************************************************/
<> 128:9bcdf88f62b0 1238
<> 128:9bcdf88f62b0 1239 /******************************************************************************/
<> 128:9bcdf88f62b0 1240 /* */
<> 128:9bcdf88f62b0 1241 /* DMA Controller */
<> 128:9bcdf88f62b0 1242 /* */
<> 128:9bcdf88f62b0 1243 /******************************************************************************/
<> 128:9bcdf88f62b0 1244 /******************** Bits definition for DMA_SxCR register *****************/
<> 128:9bcdf88f62b0 1245 #define DMA_SxCR_CHSEL 0x0E000000U
<> 128:9bcdf88f62b0 1246 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 128:9bcdf88f62b0 1247 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 128:9bcdf88f62b0 1248 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 128:9bcdf88f62b0 1249 #define DMA_SxCR_MBURST 0x01800000U
<> 128:9bcdf88f62b0 1250 #define DMA_SxCR_MBURST_0 0x00800000U
<> 128:9bcdf88f62b0 1251 #define DMA_SxCR_MBURST_1 0x01000000U
<> 128:9bcdf88f62b0 1252 #define DMA_SxCR_PBURST 0x00600000U
<> 128:9bcdf88f62b0 1253 #define DMA_SxCR_PBURST_0 0x00200000U
<> 128:9bcdf88f62b0 1254 #define DMA_SxCR_PBURST_1 0x00400000U
<> 128:9bcdf88f62b0 1255 #define DMA_SxCR_CT 0x00080000U
<> 128:9bcdf88f62b0 1256 #define DMA_SxCR_DBM 0x00040000U
<> 128:9bcdf88f62b0 1257 #define DMA_SxCR_PL 0x00030000U
<> 128:9bcdf88f62b0 1258 #define DMA_SxCR_PL_0 0x00010000U
<> 128:9bcdf88f62b0 1259 #define DMA_SxCR_PL_1 0x00020000U
<> 128:9bcdf88f62b0 1260 #define DMA_SxCR_PINCOS 0x00008000U
<> 128:9bcdf88f62b0 1261 #define DMA_SxCR_MSIZE 0x00006000U
<> 128:9bcdf88f62b0 1262 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 128:9bcdf88f62b0 1263 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 128:9bcdf88f62b0 1264 #define DMA_SxCR_PSIZE 0x00001800U
<> 128:9bcdf88f62b0 1265 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 128:9bcdf88f62b0 1266 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 128:9bcdf88f62b0 1267 #define DMA_SxCR_MINC 0x00000400U
<> 128:9bcdf88f62b0 1268 #define DMA_SxCR_PINC 0x00000200U
<> 128:9bcdf88f62b0 1269 #define DMA_SxCR_CIRC 0x00000100U
<> 128:9bcdf88f62b0 1270 #define DMA_SxCR_DIR 0x000000C0U
<> 128:9bcdf88f62b0 1271 #define DMA_SxCR_DIR_0 0x00000040U
<> 128:9bcdf88f62b0 1272 #define DMA_SxCR_DIR_1 0x00000080U
<> 128:9bcdf88f62b0 1273 #define DMA_SxCR_PFCTRL 0x00000020U
<> 128:9bcdf88f62b0 1274 #define DMA_SxCR_TCIE 0x00000010U
<> 128:9bcdf88f62b0 1275 #define DMA_SxCR_HTIE 0x00000008U
<> 128:9bcdf88f62b0 1276 #define DMA_SxCR_TEIE 0x00000004U
<> 128:9bcdf88f62b0 1277 #define DMA_SxCR_DMEIE 0x00000002U
<> 128:9bcdf88f62b0 1278 #define DMA_SxCR_EN 0x00000001U
<> 128:9bcdf88f62b0 1279
<> 128:9bcdf88f62b0 1280 /* Legacy defines */
<> 128:9bcdf88f62b0 1281 #define DMA_SxCR_ACK 0x00100000U
<> 128:9bcdf88f62b0 1282
<> 128:9bcdf88f62b0 1283 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 128:9bcdf88f62b0 1284 #define DMA_SxNDT 0x0000FFFFU
<> 128:9bcdf88f62b0 1285 #define DMA_SxNDT_0 0x00000001U
<> 128:9bcdf88f62b0 1286 #define DMA_SxNDT_1 0x00000002U
<> 128:9bcdf88f62b0 1287 #define DMA_SxNDT_2 0x00000004U
<> 128:9bcdf88f62b0 1288 #define DMA_SxNDT_3 0x00000008U
<> 128:9bcdf88f62b0 1289 #define DMA_SxNDT_4 0x00000010U
<> 128:9bcdf88f62b0 1290 #define DMA_SxNDT_5 0x00000020U
<> 128:9bcdf88f62b0 1291 #define DMA_SxNDT_6 0x00000040U
<> 128:9bcdf88f62b0 1292 #define DMA_SxNDT_7 0x00000080U
<> 128:9bcdf88f62b0 1293 #define DMA_SxNDT_8 0x00000100U
<> 128:9bcdf88f62b0 1294 #define DMA_SxNDT_9 0x00000200U
<> 128:9bcdf88f62b0 1295 #define DMA_SxNDT_10 0x00000400U
<> 128:9bcdf88f62b0 1296 #define DMA_SxNDT_11 0x00000800U
<> 128:9bcdf88f62b0 1297 #define DMA_SxNDT_12 0x00001000U
<> 128:9bcdf88f62b0 1298 #define DMA_SxNDT_13 0x00002000U
<> 128:9bcdf88f62b0 1299 #define DMA_SxNDT_14 0x00004000U
<> 128:9bcdf88f62b0 1300 #define DMA_SxNDT_15 0x00008000U
<> 128:9bcdf88f62b0 1301
<> 128:9bcdf88f62b0 1302 /******************** Bits definition for DMA_SxFCR register ****************/
<> 128:9bcdf88f62b0 1303 #define DMA_SxFCR_FEIE 0x00000080U
<> 128:9bcdf88f62b0 1304 #define DMA_SxFCR_FS 0x00000038U
<> 128:9bcdf88f62b0 1305 #define DMA_SxFCR_FS_0 0x00000008U
<> 128:9bcdf88f62b0 1306 #define DMA_SxFCR_FS_1 0x00000010U
<> 128:9bcdf88f62b0 1307 #define DMA_SxFCR_FS_2 0x00000020U
<> 128:9bcdf88f62b0 1308 #define DMA_SxFCR_DMDIS 0x00000004U
<> 128:9bcdf88f62b0 1309 #define DMA_SxFCR_FTH 0x00000003U
<> 128:9bcdf88f62b0 1310 #define DMA_SxFCR_FTH_0 0x00000001U
<> 128:9bcdf88f62b0 1311 #define DMA_SxFCR_FTH_1 0x00000002U
<> 128:9bcdf88f62b0 1312
<> 128:9bcdf88f62b0 1313 /******************** Bits definition for DMA_LISR register *****************/
<> 128:9bcdf88f62b0 1314 #define DMA_LISR_TCIF3 0x08000000U
<> 128:9bcdf88f62b0 1315 #define DMA_LISR_HTIF3 0x04000000U
<> 128:9bcdf88f62b0 1316 #define DMA_LISR_TEIF3 0x02000000U
<> 128:9bcdf88f62b0 1317 #define DMA_LISR_DMEIF3 0x01000000U
<> 128:9bcdf88f62b0 1318 #define DMA_LISR_FEIF3 0x00400000U
<> 128:9bcdf88f62b0 1319 #define DMA_LISR_TCIF2 0x00200000U
<> 128:9bcdf88f62b0 1320 #define DMA_LISR_HTIF2 0x00100000U
<> 128:9bcdf88f62b0 1321 #define DMA_LISR_TEIF2 0x00080000U
<> 128:9bcdf88f62b0 1322 #define DMA_LISR_DMEIF2 0x00040000U
<> 128:9bcdf88f62b0 1323 #define DMA_LISR_FEIF2 0x00010000U
<> 128:9bcdf88f62b0 1324 #define DMA_LISR_TCIF1 0x00000800U
<> 128:9bcdf88f62b0 1325 #define DMA_LISR_HTIF1 0x00000400U
<> 128:9bcdf88f62b0 1326 #define DMA_LISR_TEIF1 0x00000200U
<> 128:9bcdf88f62b0 1327 #define DMA_LISR_DMEIF1 0x00000100U
<> 128:9bcdf88f62b0 1328 #define DMA_LISR_FEIF1 0x00000040U
<> 128:9bcdf88f62b0 1329 #define DMA_LISR_TCIF0 0x00000020U
<> 128:9bcdf88f62b0 1330 #define DMA_LISR_HTIF0 0x00000010U
<> 128:9bcdf88f62b0 1331 #define DMA_LISR_TEIF0 0x00000008U
<> 128:9bcdf88f62b0 1332 #define DMA_LISR_DMEIF0 0x00000004U
<> 128:9bcdf88f62b0 1333 #define DMA_LISR_FEIF0 0x00000001U
<> 128:9bcdf88f62b0 1334
<> 128:9bcdf88f62b0 1335 /******************** Bits definition for DMA_HISR register *****************/
<> 128:9bcdf88f62b0 1336 #define DMA_HISR_TCIF7 0x08000000U
<> 128:9bcdf88f62b0 1337 #define DMA_HISR_HTIF7 0x04000000U
<> 128:9bcdf88f62b0 1338 #define DMA_HISR_TEIF7 0x02000000U
<> 128:9bcdf88f62b0 1339 #define DMA_HISR_DMEIF7 0x01000000U
<> 128:9bcdf88f62b0 1340 #define DMA_HISR_FEIF7 0x00400000U
<> 128:9bcdf88f62b0 1341 #define DMA_HISR_TCIF6 0x00200000U
<> 128:9bcdf88f62b0 1342 #define DMA_HISR_HTIF6 0x00100000U
<> 128:9bcdf88f62b0 1343 #define DMA_HISR_TEIF6 0x00080000U
<> 128:9bcdf88f62b0 1344 #define DMA_HISR_DMEIF6 0x00040000U
<> 128:9bcdf88f62b0 1345 #define DMA_HISR_FEIF6 0x00010000U
<> 128:9bcdf88f62b0 1346 #define DMA_HISR_TCIF5 0x00000800U
<> 128:9bcdf88f62b0 1347 #define DMA_HISR_HTIF5 0x00000400U
<> 128:9bcdf88f62b0 1348 #define DMA_HISR_TEIF5 0x00000200U
<> 128:9bcdf88f62b0 1349 #define DMA_HISR_DMEIF5 0x00000100U
<> 128:9bcdf88f62b0 1350 #define DMA_HISR_FEIF5 0x00000040U
<> 128:9bcdf88f62b0 1351 #define DMA_HISR_TCIF4 0x00000020U
<> 128:9bcdf88f62b0 1352 #define DMA_HISR_HTIF4 0x00000010U
<> 128:9bcdf88f62b0 1353 #define DMA_HISR_TEIF4 0x00000008U
<> 128:9bcdf88f62b0 1354 #define DMA_HISR_DMEIF4 0x00000004U
<> 128:9bcdf88f62b0 1355 #define DMA_HISR_FEIF4 0x00000001U
<> 128:9bcdf88f62b0 1356
<> 128:9bcdf88f62b0 1357 /******************** Bits definition for DMA_LIFCR register ****************/
<> 128:9bcdf88f62b0 1358 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 128:9bcdf88f62b0 1359 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 128:9bcdf88f62b0 1360 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 128:9bcdf88f62b0 1361 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 128:9bcdf88f62b0 1362 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 128:9bcdf88f62b0 1363 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 128:9bcdf88f62b0 1364 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 128:9bcdf88f62b0 1365 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 128:9bcdf88f62b0 1366 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 128:9bcdf88f62b0 1367 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 128:9bcdf88f62b0 1368 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 128:9bcdf88f62b0 1369 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 128:9bcdf88f62b0 1370 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 128:9bcdf88f62b0 1371 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 128:9bcdf88f62b0 1372 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 128:9bcdf88f62b0 1373 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 128:9bcdf88f62b0 1374 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 128:9bcdf88f62b0 1375 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 128:9bcdf88f62b0 1376 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 128:9bcdf88f62b0 1377 #define DMA_LIFCR_CFEIF0 0x00000001U
<> 128:9bcdf88f62b0 1378
<> 128:9bcdf88f62b0 1379 /******************** Bits definition for DMA_HIFCR register ****************/
<> 128:9bcdf88f62b0 1380 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 128:9bcdf88f62b0 1381 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 128:9bcdf88f62b0 1382 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 128:9bcdf88f62b0 1383 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 128:9bcdf88f62b0 1384 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 128:9bcdf88f62b0 1385 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 128:9bcdf88f62b0 1386 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 128:9bcdf88f62b0 1387 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 128:9bcdf88f62b0 1388 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 128:9bcdf88f62b0 1389 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 128:9bcdf88f62b0 1390 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 128:9bcdf88f62b0 1391 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 128:9bcdf88f62b0 1392 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 128:9bcdf88f62b0 1393 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 128:9bcdf88f62b0 1394 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 128:9bcdf88f62b0 1395 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 128:9bcdf88f62b0 1396 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 128:9bcdf88f62b0 1397 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 128:9bcdf88f62b0 1398 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 128:9bcdf88f62b0 1399 #define DMA_HIFCR_CFEIF4 0x00000001U
<> 128:9bcdf88f62b0 1400
<> 128:9bcdf88f62b0 1401
<> 128:9bcdf88f62b0 1402 /******************************************************************************/
<> 128:9bcdf88f62b0 1403 /* */
<> 128:9bcdf88f62b0 1404 /* External Interrupt/Event Controller */
<> 128:9bcdf88f62b0 1405 /* */
<> 128:9bcdf88f62b0 1406 /******************************************************************************/
<> 128:9bcdf88f62b0 1407 /******************* Bit definition for EXTI_IMR register *******************/
<> 128:9bcdf88f62b0 1408 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 128:9bcdf88f62b0 1409 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 128:9bcdf88f62b0 1410 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 128:9bcdf88f62b0 1411 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 128:9bcdf88f62b0 1412 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 128:9bcdf88f62b0 1413 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 128:9bcdf88f62b0 1414 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 128:9bcdf88f62b0 1415 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 128:9bcdf88f62b0 1416 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 128:9bcdf88f62b0 1417 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 128:9bcdf88f62b0 1418 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 128:9bcdf88f62b0 1419 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 128:9bcdf88f62b0 1420 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 128:9bcdf88f62b0 1421 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 128:9bcdf88f62b0 1422 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 128:9bcdf88f62b0 1423 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 128:9bcdf88f62b0 1424 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 128:9bcdf88f62b0 1425 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 128:9bcdf88f62b0 1426 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 128:9bcdf88f62b0 1427 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 128:9bcdf88f62b0 1428 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 128:9bcdf88f62b0 1429 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 128:9bcdf88f62b0 1430 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 128:9bcdf88f62b0 1431
<> 128:9bcdf88f62b0 1432 /******************* Bit definition for EXTI_EMR register *******************/
<> 128:9bcdf88f62b0 1433 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 128:9bcdf88f62b0 1434 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 128:9bcdf88f62b0 1435 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 128:9bcdf88f62b0 1436 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 128:9bcdf88f62b0 1437 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 128:9bcdf88f62b0 1438 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 128:9bcdf88f62b0 1439 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 128:9bcdf88f62b0 1440 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 128:9bcdf88f62b0 1441 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 128:9bcdf88f62b0 1442 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 128:9bcdf88f62b0 1443 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 128:9bcdf88f62b0 1444 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 128:9bcdf88f62b0 1445 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 128:9bcdf88f62b0 1446 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 128:9bcdf88f62b0 1447 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 128:9bcdf88f62b0 1448 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 128:9bcdf88f62b0 1449 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 128:9bcdf88f62b0 1450 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 128:9bcdf88f62b0 1451 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 128:9bcdf88f62b0 1452 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 128:9bcdf88f62b0 1453 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 128:9bcdf88f62b0 1454 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 128:9bcdf88f62b0 1455 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 128:9bcdf88f62b0 1456
<> 128:9bcdf88f62b0 1457 /****************** Bit definition for EXTI_RTSR register *******************/
<> 128:9bcdf88f62b0 1458 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 128:9bcdf88f62b0 1459 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 128:9bcdf88f62b0 1460 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 128:9bcdf88f62b0 1461 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 128:9bcdf88f62b0 1462 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 128:9bcdf88f62b0 1463 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 128:9bcdf88f62b0 1464 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 128:9bcdf88f62b0 1465 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 128:9bcdf88f62b0 1466 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 128:9bcdf88f62b0 1467 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 128:9bcdf88f62b0 1468 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 128:9bcdf88f62b0 1469 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 128:9bcdf88f62b0 1470 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 128:9bcdf88f62b0 1471 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 128:9bcdf88f62b0 1472 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 128:9bcdf88f62b0 1473 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 128:9bcdf88f62b0 1474 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 128:9bcdf88f62b0 1475 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 128:9bcdf88f62b0 1476 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 128:9bcdf88f62b0 1477 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 128:9bcdf88f62b0 1478 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 128:9bcdf88f62b0 1479 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 128:9bcdf88f62b0 1480 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 1481
<> 128:9bcdf88f62b0 1482 /****************** Bit definition for EXTI_FTSR register *******************/
<> 128:9bcdf88f62b0 1483 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 128:9bcdf88f62b0 1484 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 128:9bcdf88f62b0 1485 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 128:9bcdf88f62b0 1486 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 128:9bcdf88f62b0 1487 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 128:9bcdf88f62b0 1488 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 128:9bcdf88f62b0 1489 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 128:9bcdf88f62b0 1490 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 128:9bcdf88f62b0 1491 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 128:9bcdf88f62b0 1492 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 128:9bcdf88f62b0 1493 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 128:9bcdf88f62b0 1494 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 128:9bcdf88f62b0 1495 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 128:9bcdf88f62b0 1496 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 128:9bcdf88f62b0 1497 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 128:9bcdf88f62b0 1498 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 128:9bcdf88f62b0 1499 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 128:9bcdf88f62b0 1500 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 128:9bcdf88f62b0 1501 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 128:9bcdf88f62b0 1502 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 128:9bcdf88f62b0 1503 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 128:9bcdf88f62b0 1504 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 128:9bcdf88f62b0 1505 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 1506
<> 128:9bcdf88f62b0 1507 /****************** Bit definition for EXTI_SWIER register ******************/
<> 128:9bcdf88f62b0 1508 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 128:9bcdf88f62b0 1509 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 128:9bcdf88f62b0 1510 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 128:9bcdf88f62b0 1511 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 128:9bcdf88f62b0 1512 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 128:9bcdf88f62b0 1513 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 128:9bcdf88f62b0 1514 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 128:9bcdf88f62b0 1515 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 128:9bcdf88f62b0 1516 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 128:9bcdf88f62b0 1517 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 128:9bcdf88f62b0 1518 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 128:9bcdf88f62b0 1519 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 128:9bcdf88f62b0 1520 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 128:9bcdf88f62b0 1521 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 128:9bcdf88f62b0 1522 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 128:9bcdf88f62b0 1523 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 128:9bcdf88f62b0 1524 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 128:9bcdf88f62b0 1525 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 128:9bcdf88f62b0 1526 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 128:9bcdf88f62b0 1527 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 128:9bcdf88f62b0 1528 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 128:9bcdf88f62b0 1529 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 128:9bcdf88f62b0 1530 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 128:9bcdf88f62b0 1531
<> 128:9bcdf88f62b0 1532 /******************* Bit definition for EXTI_PR register ********************/
<> 128:9bcdf88f62b0 1533 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 128:9bcdf88f62b0 1534 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 128:9bcdf88f62b0 1535 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 128:9bcdf88f62b0 1536 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 128:9bcdf88f62b0 1537 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 128:9bcdf88f62b0 1538 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 128:9bcdf88f62b0 1539 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 128:9bcdf88f62b0 1540 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 128:9bcdf88f62b0 1541 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 128:9bcdf88f62b0 1542 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 128:9bcdf88f62b0 1543 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 128:9bcdf88f62b0 1544 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 128:9bcdf88f62b0 1545 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 128:9bcdf88f62b0 1546 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 128:9bcdf88f62b0 1547 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 128:9bcdf88f62b0 1548 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 128:9bcdf88f62b0 1549 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 128:9bcdf88f62b0 1550 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 128:9bcdf88f62b0 1551 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 128:9bcdf88f62b0 1552 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 128:9bcdf88f62b0 1553 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 128:9bcdf88f62b0 1554 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 128:9bcdf88f62b0 1555 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 128:9bcdf88f62b0 1556
<> 128:9bcdf88f62b0 1557 /******************************************************************************/
<> 128:9bcdf88f62b0 1558 /* */
<> 128:9bcdf88f62b0 1559 /* FLASH */
<> 128:9bcdf88f62b0 1560 /* */
<> 128:9bcdf88f62b0 1561 /******************************************************************************/
<> 128:9bcdf88f62b0 1562 /******************* Bits definition for FLASH_ACR register *****************/
<> 128:9bcdf88f62b0 1563 #define FLASH_ACR_LATENCY 0x0000000FU
<> 128:9bcdf88f62b0 1564 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 128:9bcdf88f62b0 1565 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 128:9bcdf88f62b0 1566 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 128:9bcdf88f62b0 1567 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 128:9bcdf88f62b0 1568 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 128:9bcdf88f62b0 1569 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 128:9bcdf88f62b0 1570 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 128:9bcdf88f62b0 1571 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 128:9bcdf88f62b0 1572
<> 128:9bcdf88f62b0 1573 #define FLASH_ACR_PRFTEN 0x00000100U
<> 128:9bcdf88f62b0 1574 #define FLASH_ACR_ICEN 0x00000200U
<> 128:9bcdf88f62b0 1575 #define FLASH_ACR_DCEN 0x00000400U
<> 128:9bcdf88f62b0 1576 #define FLASH_ACR_ICRST 0x00000800U
<> 128:9bcdf88f62b0 1577 #define FLASH_ACR_DCRST 0x00001000U
<> 128:9bcdf88f62b0 1578 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
<> 128:9bcdf88f62b0 1579 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
<> 128:9bcdf88f62b0 1580
<> 128:9bcdf88f62b0 1581 /******************* Bits definition for FLASH_SR register ******************/
<> 128:9bcdf88f62b0 1582 #define FLASH_SR_EOP 0x00000001U
<> 128:9bcdf88f62b0 1583 #define FLASH_SR_SOP 0x00000002U
<> 128:9bcdf88f62b0 1584 #define FLASH_SR_WRPERR 0x00000010U
<> 128:9bcdf88f62b0 1585 #define FLASH_SR_PGAERR 0x00000020U
<> 128:9bcdf88f62b0 1586 #define FLASH_SR_PGPERR 0x00000040U
<> 128:9bcdf88f62b0 1587 #define FLASH_SR_PGSERR 0x00000080U
<> 128:9bcdf88f62b0 1588 #define FLASH_SR_BSY 0x00010000U
<> 128:9bcdf88f62b0 1589
<> 128:9bcdf88f62b0 1590 /******************* Bits definition for FLASH_CR register ******************/
<> 128:9bcdf88f62b0 1591 #define FLASH_CR_PG 0x00000001U
<> 128:9bcdf88f62b0 1592 #define FLASH_CR_SER 0x00000002U
<> 128:9bcdf88f62b0 1593 #define FLASH_CR_MER 0x00000004U
<> 128:9bcdf88f62b0 1594 #define FLASH_CR_SNB 0x000000F8U
<> 128:9bcdf88f62b0 1595 #define FLASH_CR_SNB_0 0x00000008U
<> 128:9bcdf88f62b0 1596 #define FLASH_CR_SNB_1 0x00000010U
<> 128:9bcdf88f62b0 1597 #define FLASH_CR_SNB_2 0x00000020U
<> 128:9bcdf88f62b0 1598 #define FLASH_CR_SNB_3 0x00000040U
<> 128:9bcdf88f62b0 1599 #define FLASH_CR_SNB_4 0x00000080U
<> 128:9bcdf88f62b0 1600 #define FLASH_CR_PSIZE 0x00000300U
<> 128:9bcdf88f62b0 1601 #define FLASH_CR_PSIZE_0 0x00000100U
<> 128:9bcdf88f62b0 1602 #define FLASH_CR_PSIZE_1 0x00000200U
<> 128:9bcdf88f62b0 1603 #define FLASH_CR_STRT 0x00010000U
<> 128:9bcdf88f62b0 1604 #define FLASH_CR_EOPIE 0x01000000U
<> 128:9bcdf88f62b0 1605 #define FLASH_CR_LOCK 0x80000000U
<> 128:9bcdf88f62b0 1606
<> 128:9bcdf88f62b0 1607 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 128:9bcdf88f62b0 1608 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 128:9bcdf88f62b0 1609 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 128:9bcdf88f62b0 1610 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 128:9bcdf88f62b0 1611 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 128:9bcdf88f62b0 1612 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 128:9bcdf88f62b0 1613
<> 128:9bcdf88f62b0 1614 #define FLASH_OPTCR_WDG_SW 0x00000020U
<> 128:9bcdf88f62b0 1615 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 128:9bcdf88f62b0 1616 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 128:9bcdf88f62b0 1617 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 128:9bcdf88f62b0 1618 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 128:9bcdf88f62b0 1619 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 128:9bcdf88f62b0 1620 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 128:9bcdf88f62b0 1621 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 128:9bcdf88f62b0 1622 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 128:9bcdf88f62b0 1623 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 128:9bcdf88f62b0 1624 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 128:9bcdf88f62b0 1625 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 128:9bcdf88f62b0 1626 #define FLASH_OPTCR_nWRP 0x0FFF0000U
<> 128:9bcdf88f62b0 1627 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 128:9bcdf88f62b0 1628 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 128:9bcdf88f62b0 1629 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 128:9bcdf88f62b0 1630 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 128:9bcdf88f62b0 1631 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 128:9bcdf88f62b0 1632 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 128:9bcdf88f62b0 1633 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 128:9bcdf88f62b0 1634 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 128:9bcdf88f62b0 1635 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 128:9bcdf88f62b0 1636 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 128:9bcdf88f62b0 1637 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 128:9bcdf88f62b0 1638 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 128:9bcdf88f62b0 1639
<> 128:9bcdf88f62b0 1640 /****************** Bits definition for FLASH_OPTCR1 register ***************/
<> 128:9bcdf88f62b0 1641 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
<> 128:9bcdf88f62b0 1642 #define FLASH_OPTCR1_nWRP_0 0x00010000U
<> 128:9bcdf88f62b0 1643 #define FLASH_OPTCR1_nWRP_1 0x00020000U
<> 128:9bcdf88f62b0 1644 #define FLASH_OPTCR1_nWRP_2 0x00040000U
<> 128:9bcdf88f62b0 1645 #define FLASH_OPTCR1_nWRP_3 0x00080000U
<> 128:9bcdf88f62b0 1646 #define FLASH_OPTCR1_nWRP_4 0x00100000U
<> 128:9bcdf88f62b0 1647 #define FLASH_OPTCR1_nWRP_5 0x00200000U
<> 128:9bcdf88f62b0 1648 #define FLASH_OPTCR1_nWRP_6 0x00400000U
<> 128:9bcdf88f62b0 1649 #define FLASH_OPTCR1_nWRP_7 0x00800000U
<> 128:9bcdf88f62b0 1650 #define FLASH_OPTCR1_nWRP_8 0x01000000U
<> 128:9bcdf88f62b0 1651 #define FLASH_OPTCR1_nWRP_9 0x02000000U
<> 128:9bcdf88f62b0 1652 #define FLASH_OPTCR1_nWRP_10 0x04000000U
<> 128:9bcdf88f62b0 1653 #define FLASH_OPTCR1_nWRP_11 0x08000000U
<> 128:9bcdf88f62b0 1654
<> 128:9bcdf88f62b0 1655 /******************************************************************************/
<> 128:9bcdf88f62b0 1656 /* */
<> 128:9bcdf88f62b0 1657 /* General Purpose I/O */
<> 128:9bcdf88f62b0 1658 /* */
<> 128:9bcdf88f62b0 1659 /******************************************************************************/
<> 128:9bcdf88f62b0 1660 /****************** Bits definition for GPIO_MODER register *****************/
<> 128:9bcdf88f62b0 1661 #define GPIO_MODER_MODER0 0x00000003U
<> 128:9bcdf88f62b0 1662 #define GPIO_MODER_MODER0_0 0x00000001U
<> 128:9bcdf88f62b0 1663 #define GPIO_MODER_MODER0_1 0x00000002U
<> 128:9bcdf88f62b0 1664
<> 128:9bcdf88f62b0 1665 #define GPIO_MODER_MODER1 0x0000000CU
<> 128:9bcdf88f62b0 1666 #define GPIO_MODER_MODER1_0 0x00000004U
<> 128:9bcdf88f62b0 1667 #define GPIO_MODER_MODER1_1 0x00000008U
<> 128:9bcdf88f62b0 1668
<> 128:9bcdf88f62b0 1669 #define GPIO_MODER_MODER2 0x00000030U
<> 128:9bcdf88f62b0 1670 #define GPIO_MODER_MODER2_0 0x00000010U
<> 128:9bcdf88f62b0 1671 #define GPIO_MODER_MODER2_1 0x00000020U
<> 128:9bcdf88f62b0 1672
<> 128:9bcdf88f62b0 1673 #define GPIO_MODER_MODER3 0x000000C0U
<> 128:9bcdf88f62b0 1674 #define GPIO_MODER_MODER3_0 0x00000040U
<> 128:9bcdf88f62b0 1675 #define GPIO_MODER_MODER3_1 0x00000080U
<> 128:9bcdf88f62b0 1676
<> 128:9bcdf88f62b0 1677 #define GPIO_MODER_MODER4 0x00000300U
<> 128:9bcdf88f62b0 1678 #define GPIO_MODER_MODER4_0 0x00000100U
<> 128:9bcdf88f62b0 1679 #define GPIO_MODER_MODER4_1 0x00000200U
<> 128:9bcdf88f62b0 1680
<> 128:9bcdf88f62b0 1681 #define GPIO_MODER_MODER5 0x00000C00U
<> 128:9bcdf88f62b0 1682 #define GPIO_MODER_MODER5_0 0x00000400U
<> 128:9bcdf88f62b0 1683 #define GPIO_MODER_MODER5_1 0x00000800U
<> 128:9bcdf88f62b0 1684
<> 128:9bcdf88f62b0 1685 #define GPIO_MODER_MODER6 0x00003000U
<> 128:9bcdf88f62b0 1686 #define GPIO_MODER_MODER6_0 0x00001000U
<> 128:9bcdf88f62b0 1687 #define GPIO_MODER_MODER6_1 0x00002000U
<> 128:9bcdf88f62b0 1688
<> 128:9bcdf88f62b0 1689 #define GPIO_MODER_MODER7 0x0000C000U
<> 128:9bcdf88f62b0 1690 #define GPIO_MODER_MODER7_0 0x00004000U
<> 128:9bcdf88f62b0 1691 #define GPIO_MODER_MODER7_1 0x00008000U
<> 128:9bcdf88f62b0 1692
<> 128:9bcdf88f62b0 1693 #define GPIO_MODER_MODER8 0x00030000U
<> 128:9bcdf88f62b0 1694 #define GPIO_MODER_MODER8_0 0x00010000U
<> 128:9bcdf88f62b0 1695 #define GPIO_MODER_MODER8_1 0x00020000U
<> 128:9bcdf88f62b0 1696
<> 128:9bcdf88f62b0 1697 #define GPIO_MODER_MODER9 0x000C0000U
<> 128:9bcdf88f62b0 1698 #define GPIO_MODER_MODER9_0 0x00040000U
<> 128:9bcdf88f62b0 1699 #define GPIO_MODER_MODER9_1 0x00080000U
<> 128:9bcdf88f62b0 1700
<> 128:9bcdf88f62b0 1701 #define GPIO_MODER_MODER10 0x00300000U
<> 128:9bcdf88f62b0 1702 #define GPIO_MODER_MODER10_0 0x00100000U
<> 128:9bcdf88f62b0 1703 #define GPIO_MODER_MODER10_1 0x00200000U
<> 128:9bcdf88f62b0 1704
<> 128:9bcdf88f62b0 1705 #define GPIO_MODER_MODER11 0x00C00000U
<> 128:9bcdf88f62b0 1706 #define GPIO_MODER_MODER11_0 0x00400000U
<> 128:9bcdf88f62b0 1707 #define GPIO_MODER_MODER11_1 0x00800000U
<> 128:9bcdf88f62b0 1708
<> 128:9bcdf88f62b0 1709 #define GPIO_MODER_MODER12 0x03000000U
<> 128:9bcdf88f62b0 1710 #define GPIO_MODER_MODER12_0 0x01000000U
<> 128:9bcdf88f62b0 1711 #define GPIO_MODER_MODER12_1 0x02000000U
<> 128:9bcdf88f62b0 1712
<> 128:9bcdf88f62b0 1713 #define GPIO_MODER_MODER13 0x0C000000U
<> 128:9bcdf88f62b0 1714 #define GPIO_MODER_MODER13_0 0x04000000U
<> 128:9bcdf88f62b0 1715 #define GPIO_MODER_MODER13_1 0x08000000U
<> 128:9bcdf88f62b0 1716
<> 128:9bcdf88f62b0 1717 #define GPIO_MODER_MODER14 0x30000000U
<> 128:9bcdf88f62b0 1718 #define GPIO_MODER_MODER14_0 0x10000000U
<> 128:9bcdf88f62b0 1719 #define GPIO_MODER_MODER14_1 0x20000000U
<> 128:9bcdf88f62b0 1720
<> 128:9bcdf88f62b0 1721 #define GPIO_MODER_MODER15 0xC0000000U
<> 128:9bcdf88f62b0 1722 #define GPIO_MODER_MODER15_0 0x40000000U
<> 128:9bcdf88f62b0 1723 #define GPIO_MODER_MODER15_1 0x80000000U
<> 128:9bcdf88f62b0 1724
<> 128:9bcdf88f62b0 1725 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 128:9bcdf88f62b0 1726 #define GPIO_OTYPER_OT_0 0x00000001U
<> 128:9bcdf88f62b0 1727 #define GPIO_OTYPER_OT_1 0x00000002U
<> 128:9bcdf88f62b0 1728 #define GPIO_OTYPER_OT_2 0x00000004U
<> 128:9bcdf88f62b0 1729 #define GPIO_OTYPER_OT_3 0x00000008U
<> 128:9bcdf88f62b0 1730 #define GPIO_OTYPER_OT_4 0x00000010U
<> 128:9bcdf88f62b0 1731 #define GPIO_OTYPER_OT_5 0x00000020U
<> 128:9bcdf88f62b0 1732 #define GPIO_OTYPER_OT_6 0x00000040U
<> 128:9bcdf88f62b0 1733 #define GPIO_OTYPER_OT_7 0x00000080U
<> 128:9bcdf88f62b0 1734 #define GPIO_OTYPER_OT_8 0x00000100U
<> 128:9bcdf88f62b0 1735 #define GPIO_OTYPER_OT_9 0x00000200U
<> 128:9bcdf88f62b0 1736 #define GPIO_OTYPER_OT_10 0x00000400U
<> 128:9bcdf88f62b0 1737 #define GPIO_OTYPER_OT_11 0x00000800U
<> 128:9bcdf88f62b0 1738 #define GPIO_OTYPER_OT_12 0x00001000U
<> 128:9bcdf88f62b0 1739 #define GPIO_OTYPER_OT_13 0x00002000U
<> 128:9bcdf88f62b0 1740 #define GPIO_OTYPER_OT_14 0x00004000U
<> 128:9bcdf88f62b0 1741 #define GPIO_OTYPER_OT_15 0x00008000U
<> 128:9bcdf88f62b0 1742
<> 128:9bcdf88f62b0 1743 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 128:9bcdf88f62b0 1744 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
<> 128:9bcdf88f62b0 1745 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
<> 128:9bcdf88f62b0 1746 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
<> 128:9bcdf88f62b0 1747
<> 128:9bcdf88f62b0 1748 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
<> 128:9bcdf88f62b0 1749 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
<> 128:9bcdf88f62b0 1750 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
<> 128:9bcdf88f62b0 1751
<> 128:9bcdf88f62b0 1752 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
<> 128:9bcdf88f62b0 1753 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
<> 128:9bcdf88f62b0 1754 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
<> 128:9bcdf88f62b0 1755
<> 128:9bcdf88f62b0 1756 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
<> 128:9bcdf88f62b0 1757 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
<> 128:9bcdf88f62b0 1758 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
<> 128:9bcdf88f62b0 1759
<> 128:9bcdf88f62b0 1760 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
<> 128:9bcdf88f62b0 1761 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
<> 128:9bcdf88f62b0 1762 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
<> 128:9bcdf88f62b0 1763
<> 128:9bcdf88f62b0 1764 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
<> 128:9bcdf88f62b0 1765 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
<> 128:9bcdf88f62b0 1766 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
<> 128:9bcdf88f62b0 1767
<> 128:9bcdf88f62b0 1768 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
<> 128:9bcdf88f62b0 1769 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
<> 128:9bcdf88f62b0 1770 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
<> 128:9bcdf88f62b0 1771
<> 128:9bcdf88f62b0 1772 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
<> 128:9bcdf88f62b0 1773 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
<> 128:9bcdf88f62b0 1774 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
<> 128:9bcdf88f62b0 1775
<> 128:9bcdf88f62b0 1776 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
<> 128:9bcdf88f62b0 1777 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
<> 128:9bcdf88f62b0 1778 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
<> 128:9bcdf88f62b0 1779
<> 128:9bcdf88f62b0 1780 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
<> 128:9bcdf88f62b0 1781 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
<> 128:9bcdf88f62b0 1782 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
<> 128:9bcdf88f62b0 1783
<> 128:9bcdf88f62b0 1784 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
<> 128:9bcdf88f62b0 1785 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
<> 128:9bcdf88f62b0 1786 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
<> 128:9bcdf88f62b0 1787
<> 128:9bcdf88f62b0 1788 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
<> 128:9bcdf88f62b0 1789 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
<> 128:9bcdf88f62b0 1790 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
<> 128:9bcdf88f62b0 1791
<> 128:9bcdf88f62b0 1792 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
<> 128:9bcdf88f62b0 1793 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
<> 128:9bcdf88f62b0 1794 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
<> 128:9bcdf88f62b0 1795
<> 128:9bcdf88f62b0 1796 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
<> 128:9bcdf88f62b0 1797 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
<> 128:9bcdf88f62b0 1798 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
<> 128:9bcdf88f62b0 1799
<> 128:9bcdf88f62b0 1800 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
<> 128:9bcdf88f62b0 1801 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
<> 128:9bcdf88f62b0 1802 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
<> 128:9bcdf88f62b0 1803
<> 128:9bcdf88f62b0 1804 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
<> 128:9bcdf88f62b0 1805 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
<> 128:9bcdf88f62b0 1806 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
<> 128:9bcdf88f62b0 1807
<> 128:9bcdf88f62b0 1808 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 128:9bcdf88f62b0 1809 #define GPIO_PUPDR_PUPDR0 0x00000003U
<> 128:9bcdf88f62b0 1810 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
<> 128:9bcdf88f62b0 1811 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
<> 128:9bcdf88f62b0 1812
<> 128:9bcdf88f62b0 1813 #define GPIO_PUPDR_PUPDR1 0x0000000CU
<> 128:9bcdf88f62b0 1814 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
<> 128:9bcdf88f62b0 1815 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
<> 128:9bcdf88f62b0 1816
<> 128:9bcdf88f62b0 1817 #define GPIO_PUPDR_PUPDR2 0x00000030U
<> 128:9bcdf88f62b0 1818 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
<> 128:9bcdf88f62b0 1819 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
<> 128:9bcdf88f62b0 1820
<> 128:9bcdf88f62b0 1821 #define GPIO_PUPDR_PUPDR3 0x000000C0U
<> 128:9bcdf88f62b0 1822 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
<> 128:9bcdf88f62b0 1823 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
<> 128:9bcdf88f62b0 1824
<> 128:9bcdf88f62b0 1825 #define GPIO_PUPDR_PUPDR4 0x00000300U
<> 128:9bcdf88f62b0 1826 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
<> 128:9bcdf88f62b0 1827 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
<> 128:9bcdf88f62b0 1828
<> 128:9bcdf88f62b0 1829 #define GPIO_PUPDR_PUPDR5 0x00000C00U
<> 128:9bcdf88f62b0 1830 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
<> 128:9bcdf88f62b0 1831 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
<> 128:9bcdf88f62b0 1832
<> 128:9bcdf88f62b0 1833 #define GPIO_PUPDR_PUPDR6 0x00003000U
<> 128:9bcdf88f62b0 1834 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
<> 128:9bcdf88f62b0 1835 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
<> 128:9bcdf88f62b0 1836
<> 128:9bcdf88f62b0 1837 #define GPIO_PUPDR_PUPDR7 0x0000C000U
<> 128:9bcdf88f62b0 1838 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
<> 128:9bcdf88f62b0 1839 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
<> 128:9bcdf88f62b0 1840
<> 128:9bcdf88f62b0 1841 #define GPIO_PUPDR_PUPDR8 0x00030000U
<> 128:9bcdf88f62b0 1842 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
<> 128:9bcdf88f62b0 1843 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
<> 128:9bcdf88f62b0 1844
<> 128:9bcdf88f62b0 1845 #define GPIO_PUPDR_PUPDR9 0x000C0000U
<> 128:9bcdf88f62b0 1846 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
<> 128:9bcdf88f62b0 1847 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
<> 128:9bcdf88f62b0 1848
<> 128:9bcdf88f62b0 1849 #define GPIO_PUPDR_PUPDR10 0x00300000U
<> 128:9bcdf88f62b0 1850 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
<> 128:9bcdf88f62b0 1851 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
<> 128:9bcdf88f62b0 1852
<> 128:9bcdf88f62b0 1853 #define GPIO_PUPDR_PUPDR11 0x00C00000U
<> 128:9bcdf88f62b0 1854 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
<> 128:9bcdf88f62b0 1855 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
<> 128:9bcdf88f62b0 1856
<> 128:9bcdf88f62b0 1857 #define GPIO_PUPDR_PUPDR12 0x03000000U
<> 128:9bcdf88f62b0 1858 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
<> 128:9bcdf88f62b0 1859 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
<> 128:9bcdf88f62b0 1860
<> 128:9bcdf88f62b0 1861 #define GPIO_PUPDR_PUPDR13 0x0C000000U
<> 128:9bcdf88f62b0 1862 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
<> 128:9bcdf88f62b0 1863 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
<> 128:9bcdf88f62b0 1864
<> 128:9bcdf88f62b0 1865 #define GPIO_PUPDR_PUPDR14 0x30000000U
<> 128:9bcdf88f62b0 1866 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
<> 128:9bcdf88f62b0 1867 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
<> 128:9bcdf88f62b0 1868
<> 128:9bcdf88f62b0 1869 #define GPIO_PUPDR_PUPDR15 0xC0000000U
<> 128:9bcdf88f62b0 1870 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
<> 128:9bcdf88f62b0 1871 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
<> 128:9bcdf88f62b0 1872
<> 128:9bcdf88f62b0 1873 /****************** Bits definition for GPIO_IDR register *******************/
<> 128:9bcdf88f62b0 1874 #define GPIO_IDR_IDR_0 0x00000001U
<> 128:9bcdf88f62b0 1875 #define GPIO_IDR_IDR_1 0x00000002U
<> 128:9bcdf88f62b0 1876 #define GPIO_IDR_IDR_2 0x00000004U
<> 128:9bcdf88f62b0 1877 #define GPIO_IDR_IDR_3 0x00000008U
<> 128:9bcdf88f62b0 1878 #define GPIO_IDR_IDR_4 0x00000010U
<> 128:9bcdf88f62b0 1879 #define GPIO_IDR_IDR_5 0x00000020U
<> 128:9bcdf88f62b0 1880 #define GPIO_IDR_IDR_6 0x00000040U
<> 128:9bcdf88f62b0 1881 #define GPIO_IDR_IDR_7 0x00000080U
<> 128:9bcdf88f62b0 1882 #define GPIO_IDR_IDR_8 0x00000100U
<> 128:9bcdf88f62b0 1883 #define GPIO_IDR_IDR_9 0x00000200U
<> 128:9bcdf88f62b0 1884 #define GPIO_IDR_IDR_10 0x00000400U
<> 128:9bcdf88f62b0 1885 #define GPIO_IDR_IDR_11 0x00000800U
<> 128:9bcdf88f62b0 1886 #define GPIO_IDR_IDR_12 0x00001000U
<> 128:9bcdf88f62b0 1887 #define GPIO_IDR_IDR_13 0x00002000U
<> 128:9bcdf88f62b0 1888 #define GPIO_IDR_IDR_14 0x00004000U
<> 128:9bcdf88f62b0 1889 #define GPIO_IDR_IDR_15 0x00008000U
<> 128:9bcdf88f62b0 1890 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 1891 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
<> 128:9bcdf88f62b0 1892 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
<> 128:9bcdf88f62b0 1893 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
<> 128:9bcdf88f62b0 1894 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
<> 128:9bcdf88f62b0 1895 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
<> 128:9bcdf88f62b0 1896 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
<> 128:9bcdf88f62b0 1897 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
<> 128:9bcdf88f62b0 1898 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
<> 128:9bcdf88f62b0 1899 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
<> 128:9bcdf88f62b0 1900 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
<> 128:9bcdf88f62b0 1901 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
<> 128:9bcdf88f62b0 1902 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
<> 128:9bcdf88f62b0 1903 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
<> 128:9bcdf88f62b0 1904 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
<> 128:9bcdf88f62b0 1905 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
<> 128:9bcdf88f62b0 1906 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
<> 128:9bcdf88f62b0 1907
<> 128:9bcdf88f62b0 1908 /****************** Bits definition for GPIO_ODR register *******************/
<> 128:9bcdf88f62b0 1909 #define GPIO_ODR_ODR_0 0x00000001U
<> 128:9bcdf88f62b0 1910 #define GPIO_ODR_ODR_1 0x00000002U
<> 128:9bcdf88f62b0 1911 #define GPIO_ODR_ODR_2 0x00000004U
<> 128:9bcdf88f62b0 1912 #define GPIO_ODR_ODR_3 0x00000008U
<> 128:9bcdf88f62b0 1913 #define GPIO_ODR_ODR_4 0x00000010U
<> 128:9bcdf88f62b0 1914 #define GPIO_ODR_ODR_5 0x00000020U
<> 128:9bcdf88f62b0 1915 #define GPIO_ODR_ODR_6 0x00000040U
<> 128:9bcdf88f62b0 1916 #define GPIO_ODR_ODR_7 0x00000080U
<> 128:9bcdf88f62b0 1917 #define GPIO_ODR_ODR_8 0x00000100U
<> 128:9bcdf88f62b0 1918 #define GPIO_ODR_ODR_9 0x00000200U
<> 128:9bcdf88f62b0 1919 #define GPIO_ODR_ODR_10 0x00000400U
<> 128:9bcdf88f62b0 1920 #define GPIO_ODR_ODR_11 0x00000800U
<> 128:9bcdf88f62b0 1921 #define GPIO_ODR_ODR_12 0x00001000U
<> 128:9bcdf88f62b0 1922 #define GPIO_ODR_ODR_13 0x00002000U
<> 128:9bcdf88f62b0 1923 #define GPIO_ODR_ODR_14 0x00004000U
<> 128:9bcdf88f62b0 1924 #define GPIO_ODR_ODR_15 0x00008000U
<> 128:9bcdf88f62b0 1925 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 1926 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
<> 128:9bcdf88f62b0 1927 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
<> 128:9bcdf88f62b0 1928 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
<> 128:9bcdf88f62b0 1929 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
<> 128:9bcdf88f62b0 1930 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
<> 128:9bcdf88f62b0 1931 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
<> 128:9bcdf88f62b0 1932 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
<> 128:9bcdf88f62b0 1933 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
<> 128:9bcdf88f62b0 1934 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
<> 128:9bcdf88f62b0 1935 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
<> 128:9bcdf88f62b0 1936 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
<> 128:9bcdf88f62b0 1937 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
<> 128:9bcdf88f62b0 1938 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
<> 128:9bcdf88f62b0 1939 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
<> 128:9bcdf88f62b0 1940 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
<> 128:9bcdf88f62b0 1941 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
<> 128:9bcdf88f62b0 1942
<> 128:9bcdf88f62b0 1943 /****************** Bits definition for GPIO_BSRR register ******************/
<> 128:9bcdf88f62b0 1944 #define GPIO_BSRR_BS_0 0x00000001U
<> 128:9bcdf88f62b0 1945 #define GPIO_BSRR_BS_1 0x00000002U
<> 128:9bcdf88f62b0 1946 #define GPIO_BSRR_BS_2 0x00000004U
<> 128:9bcdf88f62b0 1947 #define GPIO_BSRR_BS_3 0x00000008U
<> 128:9bcdf88f62b0 1948 #define GPIO_BSRR_BS_4 0x00000010U
<> 128:9bcdf88f62b0 1949 #define GPIO_BSRR_BS_5 0x00000020U
<> 128:9bcdf88f62b0 1950 #define GPIO_BSRR_BS_6 0x00000040U
<> 128:9bcdf88f62b0 1951 #define GPIO_BSRR_BS_7 0x00000080U
<> 128:9bcdf88f62b0 1952 #define GPIO_BSRR_BS_8 0x00000100U
<> 128:9bcdf88f62b0 1953 #define GPIO_BSRR_BS_9 0x00000200U
<> 128:9bcdf88f62b0 1954 #define GPIO_BSRR_BS_10 0x00000400U
<> 128:9bcdf88f62b0 1955 #define GPIO_BSRR_BS_11 0x00000800U
<> 128:9bcdf88f62b0 1956 #define GPIO_BSRR_BS_12 0x00001000U
<> 128:9bcdf88f62b0 1957 #define GPIO_BSRR_BS_13 0x00002000U
<> 128:9bcdf88f62b0 1958 #define GPIO_BSRR_BS_14 0x00004000U
<> 128:9bcdf88f62b0 1959 #define GPIO_BSRR_BS_15 0x00008000U
<> 128:9bcdf88f62b0 1960 #define GPIO_BSRR_BR_0 0x00010000U
<> 128:9bcdf88f62b0 1961 #define GPIO_BSRR_BR_1 0x00020000U
<> 128:9bcdf88f62b0 1962 #define GPIO_BSRR_BR_2 0x00040000U
<> 128:9bcdf88f62b0 1963 #define GPIO_BSRR_BR_3 0x00080000U
<> 128:9bcdf88f62b0 1964 #define GPIO_BSRR_BR_4 0x00100000U
<> 128:9bcdf88f62b0 1965 #define GPIO_BSRR_BR_5 0x00200000U
<> 128:9bcdf88f62b0 1966 #define GPIO_BSRR_BR_6 0x00400000U
<> 128:9bcdf88f62b0 1967 #define GPIO_BSRR_BR_7 0x00800000U
<> 128:9bcdf88f62b0 1968 #define GPIO_BSRR_BR_8 0x01000000U
<> 128:9bcdf88f62b0 1969 #define GPIO_BSRR_BR_9 0x02000000U
<> 128:9bcdf88f62b0 1970 #define GPIO_BSRR_BR_10 0x04000000U
<> 128:9bcdf88f62b0 1971 #define GPIO_BSRR_BR_11 0x08000000U
<> 128:9bcdf88f62b0 1972 #define GPIO_BSRR_BR_12 0x10000000U
<> 128:9bcdf88f62b0 1973 #define GPIO_BSRR_BR_13 0x20000000U
<> 128:9bcdf88f62b0 1974 #define GPIO_BSRR_BR_14 0x40000000U
<> 128:9bcdf88f62b0 1975 #define GPIO_BSRR_BR_15 0x80000000U
<> 128:9bcdf88f62b0 1976
<> 128:9bcdf88f62b0 1977 /****************** Bit definition for GPIO_LCKR register ********************/
<> 128:9bcdf88f62b0 1978 #define GPIO_LCKR_LCK0 0x00000001U
<> 128:9bcdf88f62b0 1979 #define GPIO_LCKR_LCK1 0x00000002U
<> 128:9bcdf88f62b0 1980 #define GPIO_LCKR_LCK2 0x00000004U
<> 128:9bcdf88f62b0 1981 #define GPIO_LCKR_LCK3 0x00000008U
<> 128:9bcdf88f62b0 1982 #define GPIO_LCKR_LCK4 0x00000010U
<> 128:9bcdf88f62b0 1983 #define GPIO_LCKR_LCK5 0x00000020U
<> 128:9bcdf88f62b0 1984 #define GPIO_LCKR_LCK6 0x00000040U
<> 128:9bcdf88f62b0 1985 #define GPIO_LCKR_LCK7 0x00000080U
<> 128:9bcdf88f62b0 1986 #define GPIO_LCKR_LCK8 0x00000100U
<> 128:9bcdf88f62b0 1987 #define GPIO_LCKR_LCK9 0x00000200U
<> 128:9bcdf88f62b0 1988 #define GPIO_LCKR_LCK10 0x00000400U
<> 128:9bcdf88f62b0 1989 #define GPIO_LCKR_LCK11 0x00000800U
<> 128:9bcdf88f62b0 1990 #define GPIO_LCKR_LCK12 0x00001000U
<> 128:9bcdf88f62b0 1991 #define GPIO_LCKR_LCK13 0x00002000U
<> 128:9bcdf88f62b0 1992 #define GPIO_LCKR_LCK14 0x00004000U
<> 128:9bcdf88f62b0 1993 #define GPIO_LCKR_LCK15 0x00008000U
<> 128:9bcdf88f62b0 1994 #define GPIO_LCKR_LCKK 0x00010000U
<> 128:9bcdf88f62b0 1995
<> 128:9bcdf88f62b0 1996 /******************************************************************************/
<> 128:9bcdf88f62b0 1997 /* */
<> 128:9bcdf88f62b0 1998 /* Inter-integrated Circuit Interface */
<> 128:9bcdf88f62b0 1999 /* */
<> 128:9bcdf88f62b0 2000 /******************************************************************************/
<> 128:9bcdf88f62b0 2001 /******************* Bit definition for I2C_CR1 register ********************/
<> 128:9bcdf88f62b0 2002 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
<> 128:9bcdf88f62b0 2003 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
<> 128:9bcdf88f62b0 2004 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
<> 128:9bcdf88f62b0 2005 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
<> 128:9bcdf88f62b0 2006 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
<> 128:9bcdf88f62b0 2007 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
<> 128:9bcdf88f62b0 2008 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
<> 128:9bcdf88f62b0 2009 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
<> 128:9bcdf88f62b0 2010 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
<> 128:9bcdf88f62b0 2011 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
<> 128:9bcdf88f62b0 2012 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
<> 128:9bcdf88f62b0 2013 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
<> 128:9bcdf88f62b0 2014 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
<> 128:9bcdf88f62b0 2015 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
<> 128:9bcdf88f62b0 2016
<> 128:9bcdf88f62b0 2017 /******************* Bit definition for I2C_CR2 register ********************/
<> 128:9bcdf88f62b0 2018 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 128:9bcdf88f62b0 2019 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2020 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2021 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 2022 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 2023 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 2024 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 2025
<> 128:9bcdf88f62b0 2026 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
<> 128:9bcdf88f62b0 2027 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
<> 128:9bcdf88f62b0 2028 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
<> 128:9bcdf88f62b0 2029 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
<> 128:9bcdf88f62b0 2030 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
<> 128:9bcdf88f62b0 2031
<> 128:9bcdf88f62b0 2032 /******************* Bit definition for I2C_OAR1 register *******************/
<> 128:9bcdf88f62b0 2033 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
<> 128:9bcdf88f62b0 2034 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
<> 128:9bcdf88f62b0 2035
<> 128:9bcdf88f62b0 2036 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2037 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2038 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 2039 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 2040 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 2041 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 2042 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
<> 128:9bcdf88f62b0 2043 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
<> 128:9bcdf88f62b0 2044 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
<> 128:9bcdf88f62b0 2045 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
<> 128:9bcdf88f62b0 2046
<> 128:9bcdf88f62b0 2047 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
<> 128:9bcdf88f62b0 2048
<> 128:9bcdf88f62b0 2049 /******************* Bit definition for I2C_OAR2 register *******************/
<> 128:9bcdf88f62b0 2050 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
<> 128:9bcdf88f62b0 2051 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
<> 128:9bcdf88f62b0 2052
<> 128:9bcdf88f62b0 2053 /******************** Bit definition for I2C_DR register ********************/
<> 128:9bcdf88f62b0 2054 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
<> 128:9bcdf88f62b0 2055
<> 128:9bcdf88f62b0 2056 /******************* Bit definition for I2C_SR1 register ********************/
<> 128:9bcdf88f62b0 2057 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
<> 128:9bcdf88f62b0 2058 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
<> 128:9bcdf88f62b0 2059 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
<> 128:9bcdf88f62b0 2060 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
<> 128:9bcdf88f62b0 2061 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
<> 128:9bcdf88f62b0 2062 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
<> 128:9bcdf88f62b0 2063 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
<> 128:9bcdf88f62b0 2064 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
<> 128:9bcdf88f62b0 2065 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
<> 128:9bcdf88f62b0 2066 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
<> 128:9bcdf88f62b0 2067 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
<> 128:9bcdf88f62b0 2068 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
<> 128:9bcdf88f62b0 2069 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
<> 128:9bcdf88f62b0 2070 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
<> 128:9bcdf88f62b0 2071
<> 128:9bcdf88f62b0 2072 /******************* Bit definition for I2C_SR2 register ********************/
<> 128:9bcdf88f62b0 2073 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
<> 128:9bcdf88f62b0 2074 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
<> 128:9bcdf88f62b0 2075 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
<> 128:9bcdf88f62b0 2076 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
<> 128:9bcdf88f62b0 2077 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
<> 128:9bcdf88f62b0 2078 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
<> 128:9bcdf88f62b0 2079 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
<> 128:9bcdf88f62b0 2080 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
<> 128:9bcdf88f62b0 2081
<> 128:9bcdf88f62b0 2082 /******************* Bit definition for I2C_CCR register ********************/
<> 128:9bcdf88f62b0 2083 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
<> 128:9bcdf88f62b0 2084 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
<> 128:9bcdf88f62b0 2085 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
<> 128:9bcdf88f62b0 2086
<> 128:9bcdf88f62b0 2087 /****************** Bit definition for I2C_TRISE register *******************/
<> 128:9bcdf88f62b0 2088 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 128:9bcdf88f62b0 2089
<> 128:9bcdf88f62b0 2090 /****************** Bit definition for I2C_FLTR register *******************/
<> 128:9bcdf88f62b0 2091 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
<> 128:9bcdf88f62b0 2092 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
<> 128:9bcdf88f62b0 2093
<> 128:9bcdf88f62b0 2094 /******************************************************************************/
<> 128:9bcdf88f62b0 2095 /* */
<> 128:9bcdf88f62b0 2096 /* Independent WATCHDOG */
<> 128:9bcdf88f62b0 2097 /* */
<> 128:9bcdf88f62b0 2098 /******************************************************************************/
<> 128:9bcdf88f62b0 2099 /******************* Bit definition for IWDG_KR register ********************/
<> 128:9bcdf88f62b0 2100 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
<> 128:9bcdf88f62b0 2101
<> 128:9bcdf88f62b0 2102 /******************* Bit definition for IWDG_PR register ********************/
<> 128:9bcdf88f62b0 2103 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
<> 128:9bcdf88f62b0 2104 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2105 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2106 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
<> 128:9bcdf88f62b0 2107
<> 128:9bcdf88f62b0 2108 /******************* Bit definition for IWDG_RLR register *******************/
<> 128:9bcdf88f62b0 2109 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
<> 128:9bcdf88f62b0 2110
<> 128:9bcdf88f62b0 2111 /******************* Bit definition for IWDG_SR register ********************/
<> 128:9bcdf88f62b0 2112 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
<> 128:9bcdf88f62b0 2113 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
<> 128:9bcdf88f62b0 2114
<> 128:9bcdf88f62b0 2115
<> 128:9bcdf88f62b0 2116 /******************************************************************************/
<> 128:9bcdf88f62b0 2117 /* */
<> 128:9bcdf88f62b0 2118 /* Power Control */
<> 128:9bcdf88f62b0 2119 /* */
<> 128:9bcdf88f62b0 2120 /******************************************************************************/
<> 128:9bcdf88f62b0 2121 /******************** Bit definition for PWR_CR register ********************/
<> 128:9bcdf88f62b0 2122 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 128:9bcdf88f62b0 2123 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 128:9bcdf88f62b0 2124 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
<> 128:9bcdf88f62b0 2125 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 128:9bcdf88f62b0 2126 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 128:9bcdf88f62b0 2127
<> 128:9bcdf88f62b0 2128 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 128:9bcdf88f62b0 2129 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2130 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2131 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
<> 128:9bcdf88f62b0 2132
<> 128:9bcdf88f62b0 2133 /*!< PVD level configuration */
<> 128:9bcdf88f62b0 2134 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 128:9bcdf88f62b0 2135 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 128:9bcdf88f62b0 2136 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 128:9bcdf88f62b0 2137 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 128:9bcdf88f62b0 2138 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 128:9bcdf88f62b0 2139 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 128:9bcdf88f62b0 2140 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 128:9bcdf88f62b0 2141 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 128:9bcdf88f62b0 2142
<> 128:9bcdf88f62b0 2143 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 128:9bcdf88f62b0 2144 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 128:9bcdf88f62b0 2145 #define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
<> 128:9bcdf88f62b0 2146 #define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
<> 128:9bcdf88f62b0 2147 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
<> 128:9bcdf88f62b0 2148 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 128:9bcdf88f62b0 2149 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2150 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2151
<> 128:9bcdf88f62b0 2152 /* Legacy define */
<> 128:9bcdf88f62b0 2153 #define PWR_CR_PMODE PWR_CR_VOS
<> 128:9bcdf88f62b0 2154
<> 128:9bcdf88f62b0 2155 /******************* Bit definition for PWR_CSR register ********************/
<> 128:9bcdf88f62b0 2156 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
<> 128:9bcdf88f62b0 2157 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
<> 128:9bcdf88f62b0 2158 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
<> 128:9bcdf88f62b0 2159 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
<> 128:9bcdf88f62b0 2160 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
<> 128:9bcdf88f62b0 2161 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
<> 128:9bcdf88f62b0 2162 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
<> 128:9bcdf88f62b0 2163
<> 128:9bcdf88f62b0 2164 /* Legacy define */
<> 128:9bcdf88f62b0 2165 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
<> 128:9bcdf88f62b0 2166
<> 128:9bcdf88f62b0 2167 /******************************************************************************/
<> 128:9bcdf88f62b0 2168 /* */
<> 128:9bcdf88f62b0 2169 /* Reset and Clock Control */
<> 128:9bcdf88f62b0 2170 /* */
<> 128:9bcdf88f62b0 2171 /******************************************************************************/
<> 128:9bcdf88f62b0 2172 /******************** Bit definition for RCC_CR register ********************/
<> 128:9bcdf88f62b0 2173 #define RCC_CR_HSION 0x00000001U
<> 128:9bcdf88f62b0 2174 #define RCC_CR_HSIRDY 0x00000002U
<> 128:9bcdf88f62b0 2175
<> 128:9bcdf88f62b0 2176 #define RCC_CR_HSITRIM 0x000000F8U
<> 128:9bcdf88f62b0 2177 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
<> 128:9bcdf88f62b0 2178 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
<> 128:9bcdf88f62b0 2179 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
<> 128:9bcdf88f62b0 2180 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
<> 128:9bcdf88f62b0 2181 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
<> 128:9bcdf88f62b0 2182
<> 128:9bcdf88f62b0 2183 #define RCC_CR_HSICAL 0x0000FF00U
<> 128:9bcdf88f62b0 2184 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
<> 128:9bcdf88f62b0 2185 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
<> 128:9bcdf88f62b0 2186 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
<> 128:9bcdf88f62b0 2187 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
<> 128:9bcdf88f62b0 2188 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
<> 128:9bcdf88f62b0 2189 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
<> 128:9bcdf88f62b0 2190 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
<> 128:9bcdf88f62b0 2191 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
<> 128:9bcdf88f62b0 2192
<> 128:9bcdf88f62b0 2193 #define RCC_CR_HSEON 0x00010000U
<> 128:9bcdf88f62b0 2194 #define RCC_CR_HSERDY 0x00020000U
<> 128:9bcdf88f62b0 2195 #define RCC_CR_HSEBYP 0x00040000U
<> 128:9bcdf88f62b0 2196 #define RCC_CR_CSSON 0x00080000U
<> 128:9bcdf88f62b0 2197 #define RCC_CR_PLLON 0x01000000U
<> 128:9bcdf88f62b0 2198 #define RCC_CR_PLLRDY 0x02000000U
<> 128:9bcdf88f62b0 2199 #define RCC_CR_PLLI2SON 0x04000000U
<> 128:9bcdf88f62b0 2200 #define RCC_CR_PLLI2SRDY 0x08000000U
<> 128:9bcdf88f62b0 2201
<> 128:9bcdf88f62b0 2202 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 128:9bcdf88f62b0 2203 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 128:9bcdf88f62b0 2204 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 128:9bcdf88f62b0 2205 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 128:9bcdf88f62b0 2206 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 128:9bcdf88f62b0 2207 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 128:9bcdf88f62b0 2208 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 128:9bcdf88f62b0 2209 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 128:9bcdf88f62b0 2210
<> 128:9bcdf88f62b0 2211 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 128:9bcdf88f62b0 2212 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 128:9bcdf88f62b0 2213 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 128:9bcdf88f62b0 2214 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 128:9bcdf88f62b0 2215 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 128:9bcdf88f62b0 2216 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 128:9bcdf88f62b0 2217 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 128:9bcdf88f62b0 2218 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 128:9bcdf88f62b0 2219 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 128:9bcdf88f62b0 2220 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 128:9bcdf88f62b0 2221
<> 128:9bcdf88f62b0 2222 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 128:9bcdf88f62b0 2223 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 128:9bcdf88f62b0 2224 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 128:9bcdf88f62b0 2225
<> 128:9bcdf88f62b0 2226 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 128:9bcdf88f62b0 2227 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 128:9bcdf88f62b0 2228 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 128:9bcdf88f62b0 2229
<> 128:9bcdf88f62b0 2230 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 128:9bcdf88f62b0 2231 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 128:9bcdf88f62b0 2232 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 128:9bcdf88f62b0 2233 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 128:9bcdf88f62b0 2234 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
<> 128:9bcdf88f62b0 2235
<> 128:9bcdf88f62b0 2236 /******************** Bit definition for RCC_CFGR register ******************/
<> 128:9bcdf88f62b0 2237 /*!< SW configuration */
<> 128:9bcdf88f62b0 2238 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 128:9bcdf88f62b0 2239 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2240 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2241
<> 128:9bcdf88f62b0 2242 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 128:9bcdf88f62b0 2243 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 128:9bcdf88f62b0 2244 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 128:9bcdf88f62b0 2245
<> 128:9bcdf88f62b0 2246 /*!< SWS configuration */
<> 128:9bcdf88f62b0 2247 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 128:9bcdf88f62b0 2248 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2249 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2250
<> 128:9bcdf88f62b0 2251 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 128:9bcdf88f62b0 2252 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 128:9bcdf88f62b0 2253 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 128:9bcdf88f62b0 2254
<> 128:9bcdf88f62b0 2255 /*!< HPRE configuration */
<> 128:9bcdf88f62b0 2256 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 128:9bcdf88f62b0 2257 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2258 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2259 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 128:9bcdf88f62b0 2260 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 128:9bcdf88f62b0 2261
<> 128:9bcdf88f62b0 2262 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 128:9bcdf88f62b0 2263 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 128:9bcdf88f62b0 2264 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 128:9bcdf88f62b0 2265 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 128:9bcdf88f62b0 2266 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 128:9bcdf88f62b0 2267 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 128:9bcdf88f62b0 2268 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 128:9bcdf88f62b0 2269 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 128:9bcdf88f62b0 2270 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 128:9bcdf88f62b0 2271
<> 128:9bcdf88f62b0 2272 /*!< PPRE1 configuration */
<> 128:9bcdf88f62b0 2273 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 128:9bcdf88f62b0 2274 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2275 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2276 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 128:9bcdf88f62b0 2277
<> 128:9bcdf88f62b0 2278 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 128:9bcdf88f62b0 2279 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 128:9bcdf88f62b0 2280 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 128:9bcdf88f62b0 2281 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 128:9bcdf88f62b0 2282 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 2283
<> 128:9bcdf88f62b0 2284 /*!< PPRE2 configuration */
<> 128:9bcdf88f62b0 2285 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 128:9bcdf88f62b0 2286 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2287 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2288 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 128:9bcdf88f62b0 2289
<> 128:9bcdf88f62b0 2290 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 128:9bcdf88f62b0 2291 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 128:9bcdf88f62b0 2292 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 128:9bcdf88f62b0 2293 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 128:9bcdf88f62b0 2294 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 2295
<> 128:9bcdf88f62b0 2296 /*!< RTCPRE configuration */
<> 128:9bcdf88f62b0 2297 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 128:9bcdf88f62b0 2298 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 128:9bcdf88f62b0 2299 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 128:9bcdf88f62b0 2300 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 128:9bcdf88f62b0 2301 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 128:9bcdf88f62b0 2302 #define RCC_CFGR_RTCPRE_4 0x00100000U
<> 128:9bcdf88f62b0 2303
<> 128:9bcdf88f62b0 2304 /*!< MCO1 configuration */
<> 128:9bcdf88f62b0 2305 #define RCC_CFGR_MCO1 0x00600000U
<> 128:9bcdf88f62b0 2306 #define RCC_CFGR_MCO1_0 0x00200000U
<> 128:9bcdf88f62b0 2307 #define RCC_CFGR_MCO1_1 0x00400000U
<> 128:9bcdf88f62b0 2308
<> 128:9bcdf88f62b0 2309 #define RCC_CFGR_I2SSRC 0x00800000U
<> 128:9bcdf88f62b0 2310
<> 128:9bcdf88f62b0 2311 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 128:9bcdf88f62b0 2312 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 128:9bcdf88f62b0 2313 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 128:9bcdf88f62b0 2314 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 128:9bcdf88f62b0 2315
<> 128:9bcdf88f62b0 2316 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 128:9bcdf88f62b0 2317 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 128:9bcdf88f62b0 2318 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 128:9bcdf88f62b0 2319 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 128:9bcdf88f62b0 2320
<> 128:9bcdf88f62b0 2321 #define RCC_CFGR_MCO2 0xC0000000U
<> 128:9bcdf88f62b0 2322 #define RCC_CFGR_MCO2_0 0x40000000U
<> 128:9bcdf88f62b0 2323 #define RCC_CFGR_MCO2_1 0x80000000U
<> 128:9bcdf88f62b0 2324
<> 128:9bcdf88f62b0 2325 /******************** Bit definition for RCC_CIR register *******************/
<> 128:9bcdf88f62b0 2326 #define RCC_CIR_LSIRDYF 0x00000001U
<> 128:9bcdf88f62b0 2327 #define RCC_CIR_LSERDYF 0x00000002U
<> 128:9bcdf88f62b0 2328 #define RCC_CIR_HSIRDYF 0x00000004U
<> 128:9bcdf88f62b0 2329 #define RCC_CIR_HSERDYF 0x00000008U
<> 128:9bcdf88f62b0 2330 #define RCC_CIR_PLLRDYF 0x00000010U
<> 128:9bcdf88f62b0 2331 #define RCC_CIR_PLLI2SRDYF 0x00000020U
<> 128:9bcdf88f62b0 2332
<> 128:9bcdf88f62b0 2333 #define RCC_CIR_CSSF 0x00000080U
<> 128:9bcdf88f62b0 2334 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 128:9bcdf88f62b0 2335 #define RCC_CIR_LSERDYIE 0x00000200U
<> 128:9bcdf88f62b0 2336 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 128:9bcdf88f62b0 2337 #define RCC_CIR_HSERDYIE 0x00000800U
<> 128:9bcdf88f62b0 2338 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 128:9bcdf88f62b0 2339 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
<> 128:9bcdf88f62b0 2340
<> 128:9bcdf88f62b0 2341 #define RCC_CIR_LSIRDYC 0x00010000U
<> 128:9bcdf88f62b0 2342 #define RCC_CIR_LSERDYC 0x00020000U
<> 128:9bcdf88f62b0 2343 #define RCC_CIR_HSIRDYC 0x00040000U
<> 128:9bcdf88f62b0 2344 #define RCC_CIR_HSERDYC 0x00080000U
<> 128:9bcdf88f62b0 2345 #define RCC_CIR_PLLRDYC 0x00100000U
<> 128:9bcdf88f62b0 2346 #define RCC_CIR_PLLI2SRDYC 0x00200000U
<> 128:9bcdf88f62b0 2347
<> 128:9bcdf88f62b0 2348 #define RCC_CIR_CSSC 0x00800000U
<> 128:9bcdf88f62b0 2349
<> 128:9bcdf88f62b0 2350 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 128:9bcdf88f62b0 2351 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 128:9bcdf88f62b0 2352 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 128:9bcdf88f62b0 2353 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 128:9bcdf88f62b0 2354 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
<> 128:9bcdf88f62b0 2355 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
<> 128:9bcdf88f62b0 2356 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 128:9bcdf88f62b0 2357 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 128:9bcdf88f62b0 2358 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 128:9bcdf88f62b0 2359 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 128:9bcdf88f62b0 2360
<> 128:9bcdf88f62b0 2361 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 128:9bcdf88f62b0 2362 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
<> 128:9bcdf88f62b0 2363
<> 128:9bcdf88f62b0 2364 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 128:9bcdf88f62b0 2365
<> 128:9bcdf88f62b0 2366 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 128:9bcdf88f62b0 2367 #define RCC_APB1RSTR_TIM2RST 0x00000001U
<> 128:9bcdf88f62b0 2368 #define RCC_APB1RSTR_TIM3RST 0x00000002U
<> 128:9bcdf88f62b0 2369 #define RCC_APB1RSTR_TIM4RST 0x00000004U
<> 128:9bcdf88f62b0 2370 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 128:9bcdf88f62b0 2371 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 128:9bcdf88f62b0 2372 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 128:9bcdf88f62b0 2373 #define RCC_APB1RSTR_SPI3RST 0x00008000U
<> 128:9bcdf88f62b0 2374 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 128:9bcdf88f62b0 2375 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 128:9bcdf88f62b0 2376 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 128:9bcdf88f62b0 2377 #define RCC_APB1RSTR_I2C3RST 0x00800000U
<> 128:9bcdf88f62b0 2378 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 128:9bcdf88f62b0 2379
<> 128:9bcdf88f62b0 2380 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 128:9bcdf88f62b0 2381 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 128:9bcdf88f62b0 2382 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 128:9bcdf88f62b0 2383 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 128:9bcdf88f62b0 2384 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 128:9bcdf88f62b0 2385 #define RCC_APB2RSTR_SDIORST 0x00000800U
<> 128:9bcdf88f62b0 2386 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 128:9bcdf88f62b0 2387 #define RCC_APB2RSTR_SPI4RST 0x00002000U
<> 128:9bcdf88f62b0 2388 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 128:9bcdf88f62b0 2389 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 128:9bcdf88f62b0 2390 #define RCC_APB2RSTR_TIM10RST 0x00020000U
<> 128:9bcdf88f62b0 2391 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 128:9bcdf88f62b0 2392
<> 128:9bcdf88f62b0 2393 /* Old SPI1RST bit definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 2394 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
<> 128:9bcdf88f62b0 2395
<> 128:9bcdf88f62b0 2396 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 128:9bcdf88f62b0 2397 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 128:9bcdf88f62b0 2398 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 128:9bcdf88f62b0 2399 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 128:9bcdf88f62b0 2400 #define RCC_AHB1ENR_GPIODEN 0x00000008U
<> 128:9bcdf88f62b0 2401 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
<> 128:9bcdf88f62b0 2402 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 128:9bcdf88f62b0 2403 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 128:9bcdf88f62b0 2404 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
<> 128:9bcdf88f62b0 2405 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 128:9bcdf88f62b0 2406 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 128:9bcdf88f62b0 2407
<> 128:9bcdf88f62b0 2408 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 128:9bcdf88f62b0 2409 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
<> 128:9bcdf88f62b0 2410
<> 128:9bcdf88f62b0 2411 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 128:9bcdf88f62b0 2412
<> 128:9bcdf88f62b0 2413 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 128:9bcdf88f62b0 2414 #define RCC_APB1ENR_TIM2EN 0x00000001U
<> 128:9bcdf88f62b0 2415 #define RCC_APB1ENR_TIM3EN 0x00000002U
<> 128:9bcdf88f62b0 2416 #define RCC_APB1ENR_TIM4EN 0x00000004U
<> 128:9bcdf88f62b0 2417 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 128:9bcdf88f62b0 2418 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 128:9bcdf88f62b0 2419 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 128:9bcdf88f62b0 2420 #define RCC_APB1ENR_SPI3EN 0x00008000U
<> 128:9bcdf88f62b0 2421 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 128:9bcdf88f62b0 2422 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 128:9bcdf88f62b0 2423 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 128:9bcdf88f62b0 2424 #define RCC_APB1ENR_I2C3EN 0x00800000U
<> 128:9bcdf88f62b0 2425 #define RCC_APB1ENR_PWREN 0x10000000U
<> 128:9bcdf88f62b0 2426
<> 128:9bcdf88f62b0 2427 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 128:9bcdf88f62b0 2428 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 128:9bcdf88f62b0 2429 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 128:9bcdf88f62b0 2430 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 128:9bcdf88f62b0 2431 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 128:9bcdf88f62b0 2432 #define RCC_APB2ENR_SDIOEN 0x00000800U
<> 128:9bcdf88f62b0 2433 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 128:9bcdf88f62b0 2434 #define RCC_APB2ENR_SPI4EN 0x00002000U
<> 128:9bcdf88f62b0 2435 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 128:9bcdf88f62b0 2436 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 128:9bcdf88f62b0 2437 #define RCC_APB2ENR_TIM10EN 0x00020000U
<> 128:9bcdf88f62b0 2438 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 128:9bcdf88f62b0 2439
<> 128:9bcdf88f62b0 2440 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 128:9bcdf88f62b0 2441 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 128:9bcdf88f62b0 2442 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 128:9bcdf88f62b0 2443 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 128:9bcdf88f62b0 2444 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
<> 128:9bcdf88f62b0 2445 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
<> 128:9bcdf88f62b0 2446 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 128:9bcdf88f62b0 2447 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 128:9bcdf88f62b0 2448 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 128:9bcdf88f62b0 2449 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 128:9bcdf88f62b0 2450 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
<> 128:9bcdf88f62b0 2451 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
<> 128:9bcdf88f62b0 2452 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 128:9bcdf88f62b0 2453 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 128:9bcdf88f62b0 2454
<> 128:9bcdf88f62b0 2455 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 128:9bcdf88f62b0 2456 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
<> 128:9bcdf88f62b0 2457
<> 128:9bcdf88f62b0 2458 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 128:9bcdf88f62b0 2459
<> 128:9bcdf88f62b0 2460 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 128:9bcdf88f62b0 2461 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
<> 128:9bcdf88f62b0 2462 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
<> 128:9bcdf88f62b0 2463 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
<> 128:9bcdf88f62b0 2464 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 128:9bcdf88f62b0 2465 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 128:9bcdf88f62b0 2466 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 128:9bcdf88f62b0 2467 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
<> 128:9bcdf88f62b0 2468 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 128:9bcdf88f62b0 2469 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 128:9bcdf88f62b0 2470 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 128:9bcdf88f62b0 2471 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
<> 128:9bcdf88f62b0 2472 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 128:9bcdf88f62b0 2473 #define RCC_APB1LPENR_DACLPEN 0x20000000U
<> 128:9bcdf88f62b0 2474
<> 128:9bcdf88f62b0 2475 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 128:9bcdf88f62b0 2476 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 128:9bcdf88f62b0 2477 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 128:9bcdf88f62b0 2478 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 128:9bcdf88f62b0 2479 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 128:9bcdf88f62b0 2480 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
<> 128:9bcdf88f62b0 2481 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 128:9bcdf88f62b0 2482 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
<> 128:9bcdf88f62b0 2483 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 128:9bcdf88f62b0 2484 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 128:9bcdf88f62b0 2485 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
<> 128:9bcdf88f62b0 2486 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 128:9bcdf88f62b0 2487
<> 128:9bcdf88f62b0 2488 /******************** Bit definition for RCC_BDCR register ******************/
<> 128:9bcdf88f62b0 2489 #define RCC_BDCR_LSEON 0x00000001U
<> 128:9bcdf88f62b0 2490 #define RCC_BDCR_LSERDY 0x00000002U
<> 128:9bcdf88f62b0 2491 #define RCC_BDCR_LSEBYP 0x00000004U
<> 128:9bcdf88f62b0 2492
<> 128:9bcdf88f62b0 2493 #define RCC_BDCR_RTCSEL 0x00000300U
<> 128:9bcdf88f62b0 2494 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 128:9bcdf88f62b0 2495 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 128:9bcdf88f62b0 2496
<> 128:9bcdf88f62b0 2497 #define RCC_BDCR_RTCEN 0x00008000U
<> 128:9bcdf88f62b0 2498 #define RCC_BDCR_BDRST 0x00010000U
<> 128:9bcdf88f62b0 2499
<> 128:9bcdf88f62b0 2500 /******************** Bit definition for RCC_CSR register *******************/
<> 128:9bcdf88f62b0 2501 #define RCC_CSR_LSION 0x00000001U
<> 128:9bcdf88f62b0 2502 #define RCC_CSR_LSIRDY 0x00000002U
<> 128:9bcdf88f62b0 2503 #define RCC_CSR_RMVF 0x01000000U
<> 128:9bcdf88f62b0 2504 #define RCC_CSR_BORRSTF 0x02000000U
<> 128:9bcdf88f62b0 2505 #define RCC_CSR_PADRSTF 0x04000000U
<> 128:9bcdf88f62b0 2506 #define RCC_CSR_PORRSTF 0x08000000U
<> 128:9bcdf88f62b0 2507 #define RCC_CSR_SFTRSTF 0x10000000U
<> 128:9bcdf88f62b0 2508 #define RCC_CSR_WDGRSTF 0x20000000U
<> 128:9bcdf88f62b0 2509 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 128:9bcdf88f62b0 2510 #define RCC_CSR_LPWRRSTF 0x80000000U
<> 128:9bcdf88f62b0 2511
<> 128:9bcdf88f62b0 2512 /******************** Bit definition for RCC_SSCGR register *****************/
<> 128:9bcdf88f62b0 2513 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 128:9bcdf88f62b0 2514 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 128:9bcdf88f62b0 2515 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 128:9bcdf88f62b0 2516 #define RCC_SSCGR_SSCGEN 0x80000000U
<> 128:9bcdf88f62b0 2517
<> 128:9bcdf88f62b0 2518 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 128:9bcdf88f62b0 2519 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
<> 128:9bcdf88f62b0 2520 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
<> 128:9bcdf88f62b0 2521 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
<> 128:9bcdf88f62b0 2522 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
<> 128:9bcdf88f62b0 2523 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
<> 128:9bcdf88f62b0 2524 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
<> 128:9bcdf88f62b0 2525 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
<> 128:9bcdf88f62b0 2526 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
<> 128:9bcdf88f62b0 2527 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
<> 128:9bcdf88f62b0 2528 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
<> 128:9bcdf88f62b0 2529
<> 128:9bcdf88f62b0 2530 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
<> 128:9bcdf88f62b0 2531 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
<> 128:9bcdf88f62b0 2532 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
<> 128:9bcdf88f62b0 2533 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
<> 128:9bcdf88f62b0 2534
<> 128:9bcdf88f62b0 2535 /******************** Bit definition for RCC_DCKCFGR register ***************/
<> 128:9bcdf88f62b0 2536 #define RCC_DCKCFGR_TIMPRE 0x01000000U
<> 128:9bcdf88f62b0 2537
<> 128:9bcdf88f62b0 2538 /******************************************************************************/
<> 128:9bcdf88f62b0 2539 /* */
<> 128:9bcdf88f62b0 2540 /* Real-Time Clock (RTC) */
<> 128:9bcdf88f62b0 2541 /* */
<> 128:9bcdf88f62b0 2542 /******************************************************************************/
<> 128:9bcdf88f62b0 2543 /******************** Bits definition for RTC_TR register *******************/
<> 128:9bcdf88f62b0 2544 #define RTC_TR_PM 0x00400000U
<> 128:9bcdf88f62b0 2545 #define RTC_TR_HT 0x00300000U
<> 128:9bcdf88f62b0 2546 #define RTC_TR_HT_0 0x00100000U
<> 128:9bcdf88f62b0 2547 #define RTC_TR_HT_1 0x00200000U
<> 128:9bcdf88f62b0 2548 #define RTC_TR_HU 0x000F0000U
<> 128:9bcdf88f62b0 2549 #define RTC_TR_HU_0 0x00010000U
<> 128:9bcdf88f62b0 2550 #define RTC_TR_HU_1 0x00020000U
<> 128:9bcdf88f62b0 2551 #define RTC_TR_HU_2 0x00040000U
<> 128:9bcdf88f62b0 2552 #define RTC_TR_HU_3 0x00080000U
<> 128:9bcdf88f62b0 2553 #define RTC_TR_MNT 0x00007000U
<> 128:9bcdf88f62b0 2554 #define RTC_TR_MNT_0 0x00001000U
<> 128:9bcdf88f62b0 2555 #define RTC_TR_MNT_1 0x00002000U
<> 128:9bcdf88f62b0 2556 #define RTC_TR_MNT_2 0x00004000U
<> 128:9bcdf88f62b0 2557 #define RTC_TR_MNU 0x00000F00U
<> 128:9bcdf88f62b0 2558 #define RTC_TR_MNU_0 0x00000100U
<> 128:9bcdf88f62b0 2559 #define RTC_TR_MNU_1 0x00000200U
<> 128:9bcdf88f62b0 2560 #define RTC_TR_MNU_2 0x00000400U
<> 128:9bcdf88f62b0 2561 #define RTC_TR_MNU_3 0x00000800U
<> 128:9bcdf88f62b0 2562 #define RTC_TR_ST 0x00000070U
<> 128:9bcdf88f62b0 2563 #define RTC_TR_ST_0 0x00000010U
<> 128:9bcdf88f62b0 2564 #define RTC_TR_ST_1 0x00000020U
<> 128:9bcdf88f62b0 2565 #define RTC_TR_ST_2 0x00000040U
<> 128:9bcdf88f62b0 2566 #define RTC_TR_SU 0x0000000FU
<> 128:9bcdf88f62b0 2567 #define RTC_TR_SU_0 0x00000001U
<> 128:9bcdf88f62b0 2568 #define RTC_TR_SU_1 0x00000002U
<> 128:9bcdf88f62b0 2569 #define RTC_TR_SU_2 0x00000004U
<> 128:9bcdf88f62b0 2570 #define RTC_TR_SU_3 0x00000008U
<> 128:9bcdf88f62b0 2571
<> 128:9bcdf88f62b0 2572 /******************** Bits definition for RTC_DR register *******************/
<> 128:9bcdf88f62b0 2573 #define RTC_DR_YT 0x00F00000U
<> 128:9bcdf88f62b0 2574 #define RTC_DR_YT_0 0x00100000U
<> 128:9bcdf88f62b0 2575 #define RTC_DR_YT_1 0x00200000U
<> 128:9bcdf88f62b0 2576 #define RTC_DR_YT_2 0x00400000U
<> 128:9bcdf88f62b0 2577 #define RTC_DR_YT_3 0x00800000U
<> 128:9bcdf88f62b0 2578 #define RTC_DR_YU 0x000F0000U
<> 128:9bcdf88f62b0 2579 #define RTC_DR_YU_0 0x00010000U
<> 128:9bcdf88f62b0 2580 #define RTC_DR_YU_1 0x00020000U
<> 128:9bcdf88f62b0 2581 #define RTC_DR_YU_2 0x00040000U
<> 128:9bcdf88f62b0 2582 #define RTC_DR_YU_3 0x00080000U
<> 128:9bcdf88f62b0 2583 #define RTC_DR_WDU 0x0000E000U
<> 128:9bcdf88f62b0 2584 #define RTC_DR_WDU_0 0x00002000U
<> 128:9bcdf88f62b0 2585 #define RTC_DR_WDU_1 0x00004000U
<> 128:9bcdf88f62b0 2586 #define RTC_DR_WDU_2 0x00008000U
<> 128:9bcdf88f62b0 2587 #define RTC_DR_MT 0x00001000U
<> 128:9bcdf88f62b0 2588 #define RTC_DR_MU 0x00000F00U
<> 128:9bcdf88f62b0 2589 #define RTC_DR_MU_0 0x00000100U
<> 128:9bcdf88f62b0 2590 #define RTC_DR_MU_1 0x00000200U
<> 128:9bcdf88f62b0 2591 #define RTC_DR_MU_2 0x00000400U
<> 128:9bcdf88f62b0 2592 #define RTC_DR_MU_3 0x00000800U
<> 128:9bcdf88f62b0 2593 #define RTC_DR_DT 0x00000030U
<> 128:9bcdf88f62b0 2594 #define RTC_DR_DT_0 0x00000010U
<> 128:9bcdf88f62b0 2595 #define RTC_DR_DT_1 0x00000020U
<> 128:9bcdf88f62b0 2596 #define RTC_DR_DU 0x0000000FU
<> 128:9bcdf88f62b0 2597 #define RTC_DR_DU_0 0x00000001U
<> 128:9bcdf88f62b0 2598 #define RTC_DR_DU_1 0x00000002U
<> 128:9bcdf88f62b0 2599 #define RTC_DR_DU_2 0x00000004U
<> 128:9bcdf88f62b0 2600 #define RTC_DR_DU_3 0x00000008U
<> 128:9bcdf88f62b0 2601
<> 128:9bcdf88f62b0 2602 /******************** Bits definition for RTC_CR register *******************/
<> 128:9bcdf88f62b0 2603 #define RTC_CR_COE 0x00800000U
<> 128:9bcdf88f62b0 2604 #define RTC_CR_OSEL 0x00600000U
<> 128:9bcdf88f62b0 2605 #define RTC_CR_OSEL_0 0x00200000U
<> 128:9bcdf88f62b0 2606 #define RTC_CR_OSEL_1 0x00400000U
<> 128:9bcdf88f62b0 2607 #define RTC_CR_POL 0x00100000U
<> 128:9bcdf88f62b0 2608 #define RTC_CR_COSEL 0x00080000U
<> 128:9bcdf88f62b0 2609 #define RTC_CR_BCK 0x00040000U
<> 128:9bcdf88f62b0 2610 #define RTC_CR_SUB1H 0x00020000U
<> 128:9bcdf88f62b0 2611 #define RTC_CR_ADD1H 0x00010000U
<> 128:9bcdf88f62b0 2612 #define RTC_CR_TSIE 0x00008000U
<> 128:9bcdf88f62b0 2613 #define RTC_CR_WUTIE 0x00004000U
<> 128:9bcdf88f62b0 2614 #define RTC_CR_ALRBIE 0x00002000U
<> 128:9bcdf88f62b0 2615 #define RTC_CR_ALRAIE 0x00001000U
<> 128:9bcdf88f62b0 2616 #define RTC_CR_TSE 0x00000800U
<> 128:9bcdf88f62b0 2617 #define RTC_CR_WUTE 0x00000400U
<> 128:9bcdf88f62b0 2618 #define RTC_CR_ALRBE 0x00000200U
<> 128:9bcdf88f62b0 2619 #define RTC_CR_ALRAE 0x00000100U
<> 128:9bcdf88f62b0 2620 #define RTC_CR_DCE 0x00000080U
<> 128:9bcdf88f62b0 2621 #define RTC_CR_FMT 0x00000040U
<> 128:9bcdf88f62b0 2622 #define RTC_CR_BYPSHAD 0x00000020U
<> 128:9bcdf88f62b0 2623 #define RTC_CR_REFCKON 0x00000010U
<> 128:9bcdf88f62b0 2624 #define RTC_CR_TSEDGE 0x00000008U
<> 128:9bcdf88f62b0 2625 #define RTC_CR_WUCKSEL 0x00000007U
<> 128:9bcdf88f62b0 2626 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 128:9bcdf88f62b0 2627 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 128:9bcdf88f62b0 2628 #define RTC_CR_WUCKSEL_2 0x00000004U
<> 128:9bcdf88f62b0 2629
<> 128:9bcdf88f62b0 2630 /******************** Bits definition for RTC_ISR register ******************/
<> 128:9bcdf88f62b0 2631 #define RTC_ISR_RECALPF 0x00010000U
<> 128:9bcdf88f62b0 2632 #define RTC_ISR_TAMP1F 0x00002000U
<> 128:9bcdf88f62b0 2633 #define RTC_ISR_TAMP2F 0x00004000U
<> 128:9bcdf88f62b0 2634 #define RTC_ISR_TSOVF 0x00001000U
<> 128:9bcdf88f62b0 2635 #define RTC_ISR_TSF 0x00000800U
<> 128:9bcdf88f62b0 2636 #define RTC_ISR_WUTF 0x00000400U
<> 128:9bcdf88f62b0 2637 #define RTC_ISR_ALRBF 0x00000200U
<> 128:9bcdf88f62b0 2638 #define RTC_ISR_ALRAF 0x00000100U
<> 128:9bcdf88f62b0 2639 #define RTC_ISR_INIT 0x00000080U
<> 128:9bcdf88f62b0 2640 #define RTC_ISR_INITF 0x00000040U
<> 128:9bcdf88f62b0 2641 #define RTC_ISR_RSF 0x00000020U
<> 128:9bcdf88f62b0 2642 #define RTC_ISR_INITS 0x00000010U
<> 128:9bcdf88f62b0 2643 #define RTC_ISR_SHPF 0x00000008U
<> 128:9bcdf88f62b0 2644 #define RTC_ISR_WUTWF 0x00000004U
<> 128:9bcdf88f62b0 2645 #define RTC_ISR_ALRBWF 0x00000002U
<> 128:9bcdf88f62b0 2646 #define RTC_ISR_ALRAWF 0x00000001U
<> 128:9bcdf88f62b0 2647
<> 128:9bcdf88f62b0 2648 /******************** Bits definition for RTC_PRER register *****************/
<> 128:9bcdf88f62b0 2649 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 128:9bcdf88f62b0 2650 #define RTC_PRER_PREDIV_S 0x00007FFFU
<> 128:9bcdf88f62b0 2651
<> 128:9bcdf88f62b0 2652 /******************** Bits definition for RTC_WUTR register *****************/
<> 128:9bcdf88f62b0 2653 #define RTC_WUTR_WUT 0x0000FFFFU
<> 128:9bcdf88f62b0 2654
<> 128:9bcdf88f62b0 2655 /******************** Bits definition for RTC_CALIBR register ***************/
<> 128:9bcdf88f62b0 2656 #define RTC_CALIBR_DCS 0x00000080U
<> 128:9bcdf88f62b0 2657 #define RTC_CALIBR_DC 0x0000001FU
<> 128:9bcdf88f62b0 2658
<> 128:9bcdf88f62b0 2659 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 128:9bcdf88f62b0 2660 #define RTC_ALRMAR_MSK4 0x80000000U
<> 128:9bcdf88f62b0 2661 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 128:9bcdf88f62b0 2662 #define RTC_ALRMAR_DT 0x30000000U
<> 128:9bcdf88f62b0 2663 #define RTC_ALRMAR_DT_0 0x10000000U
<> 128:9bcdf88f62b0 2664 #define RTC_ALRMAR_DT_1 0x20000000U
<> 128:9bcdf88f62b0 2665 #define RTC_ALRMAR_DU 0x0F000000U
<> 128:9bcdf88f62b0 2666 #define RTC_ALRMAR_DU_0 0x01000000U
<> 128:9bcdf88f62b0 2667 #define RTC_ALRMAR_DU_1 0x02000000U
<> 128:9bcdf88f62b0 2668 #define RTC_ALRMAR_DU_2 0x04000000U
<> 128:9bcdf88f62b0 2669 #define RTC_ALRMAR_DU_3 0x08000000U
<> 128:9bcdf88f62b0 2670 #define RTC_ALRMAR_MSK3 0x00800000U
<> 128:9bcdf88f62b0 2671 #define RTC_ALRMAR_PM 0x00400000U
<> 128:9bcdf88f62b0 2672 #define RTC_ALRMAR_HT 0x00300000U
<> 128:9bcdf88f62b0 2673 #define RTC_ALRMAR_HT_0 0x00100000U
<> 128:9bcdf88f62b0 2674 #define RTC_ALRMAR_HT_1 0x00200000U
<> 128:9bcdf88f62b0 2675 #define RTC_ALRMAR_HU 0x000F0000U
<> 128:9bcdf88f62b0 2676 #define RTC_ALRMAR_HU_0 0x00010000U
<> 128:9bcdf88f62b0 2677 #define RTC_ALRMAR_HU_1 0x00020000U
<> 128:9bcdf88f62b0 2678 #define RTC_ALRMAR_HU_2 0x00040000U
<> 128:9bcdf88f62b0 2679 #define RTC_ALRMAR_HU_3 0x00080000U
<> 128:9bcdf88f62b0 2680 #define RTC_ALRMAR_MSK2 0x00008000U
<> 128:9bcdf88f62b0 2681 #define RTC_ALRMAR_MNT 0x00007000U
<> 128:9bcdf88f62b0 2682 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 128:9bcdf88f62b0 2683 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 128:9bcdf88f62b0 2684 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 128:9bcdf88f62b0 2685 #define RTC_ALRMAR_MNU 0x00000F00U
<> 128:9bcdf88f62b0 2686 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 128:9bcdf88f62b0 2687 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 128:9bcdf88f62b0 2688 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 128:9bcdf88f62b0 2689 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 128:9bcdf88f62b0 2690 #define RTC_ALRMAR_MSK1 0x00000080U
<> 128:9bcdf88f62b0 2691 #define RTC_ALRMAR_ST 0x00000070U
<> 128:9bcdf88f62b0 2692 #define RTC_ALRMAR_ST_0 0x00000010U
<> 128:9bcdf88f62b0 2693 #define RTC_ALRMAR_ST_1 0x00000020U
<> 128:9bcdf88f62b0 2694 #define RTC_ALRMAR_ST_2 0x00000040U
<> 128:9bcdf88f62b0 2695 #define RTC_ALRMAR_SU 0x0000000FU
<> 128:9bcdf88f62b0 2696 #define RTC_ALRMAR_SU_0 0x00000001U
<> 128:9bcdf88f62b0 2697 #define RTC_ALRMAR_SU_1 0x00000002U
<> 128:9bcdf88f62b0 2698 #define RTC_ALRMAR_SU_2 0x00000004U
<> 128:9bcdf88f62b0 2699 #define RTC_ALRMAR_SU_3 0x00000008U
<> 128:9bcdf88f62b0 2700
<> 128:9bcdf88f62b0 2701 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 128:9bcdf88f62b0 2702 #define RTC_ALRMBR_MSK4 0x80000000U
<> 128:9bcdf88f62b0 2703 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 128:9bcdf88f62b0 2704 #define RTC_ALRMBR_DT 0x30000000U
<> 128:9bcdf88f62b0 2705 #define RTC_ALRMBR_DT_0 0x10000000U
<> 128:9bcdf88f62b0 2706 #define RTC_ALRMBR_DT_1 0x20000000U
<> 128:9bcdf88f62b0 2707 #define RTC_ALRMBR_DU 0x0F000000U
<> 128:9bcdf88f62b0 2708 #define RTC_ALRMBR_DU_0 0x01000000U
<> 128:9bcdf88f62b0 2709 #define RTC_ALRMBR_DU_1 0x02000000U
<> 128:9bcdf88f62b0 2710 #define RTC_ALRMBR_DU_2 0x04000000U
<> 128:9bcdf88f62b0 2711 #define RTC_ALRMBR_DU_3 0x08000000U
<> 128:9bcdf88f62b0 2712 #define RTC_ALRMBR_MSK3 0x00800000U
<> 128:9bcdf88f62b0 2713 #define RTC_ALRMBR_PM 0x00400000U
<> 128:9bcdf88f62b0 2714 #define RTC_ALRMBR_HT 0x00300000U
<> 128:9bcdf88f62b0 2715 #define RTC_ALRMBR_HT_0 0x00100000U
<> 128:9bcdf88f62b0 2716 #define RTC_ALRMBR_HT_1 0x00200000U
<> 128:9bcdf88f62b0 2717 #define RTC_ALRMBR_HU 0x000F0000U
<> 128:9bcdf88f62b0 2718 #define RTC_ALRMBR_HU_0 0x00010000U
<> 128:9bcdf88f62b0 2719 #define RTC_ALRMBR_HU_1 0x00020000U
<> 128:9bcdf88f62b0 2720 #define RTC_ALRMBR_HU_2 0x00040000U
<> 128:9bcdf88f62b0 2721 #define RTC_ALRMBR_HU_3 0x00080000U
<> 128:9bcdf88f62b0 2722 #define RTC_ALRMBR_MSK2 0x00008000U
<> 128:9bcdf88f62b0 2723 #define RTC_ALRMBR_MNT 0x00007000U
<> 128:9bcdf88f62b0 2724 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 128:9bcdf88f62b0 2725 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 128:9bcdf88f62b0 2726 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 128:9bcdf88f62b0 2727 #define RTC_ALRMBR_MNU 0x00000F00U
<> 128:9bcdf88f62b0 2728 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 128:9bcdf88f62b0 2729 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 128:9bcdf88f62b0 2730 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 128:9bcdf88f62b0 2731 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 128:9bcdf88f62b0 2732 #define RTC_ALRMBR_MSK1 0x00000080U
<> 128:9bcdf88f62b0 2733 #define RTC_ALRMBR_ST 0x00000070U
<> 128:9bcdf88f62b0 2734 #define RTC_ALRMBR_ST_0 0x00000010U
<> 128:9bcdf88f62b0 2735 #define RTC_ALRMBR_ST_1 0x00000020U
<> 128:9bcdf88f62b0 2736 #define RTC_ALRMBR_ST_2 0x00000040U
<> 128:9bcdf88f62b0 2737 #define RTC_ALRMBR_SU 0x0000000FU
<> 128:9bcdf88f62b0 2738 #define RTC_ALRMBR_SU_0 0x00000001U
<> 128:9bcdf88f62b0 2739 #define RTC_ALRMBR_SU_1 0x00000002U
<> 128:9bcdf88f62b0 2740 #define RTC_ALRMBR_SU_2 0x00000004U
<> 128:9bcdf88f62b0 2741 #define RTC_ALRMBR_SU_3 0x00000008U
<> 128:9bcdf88f62b0 2742
<> 128:9bcdf88f62b0 2743 /******************** Bits definition for RTC_WPR register ******************/
<> 128:9bcdf88f62b0 2744 #define RTC_WPR_KEY 0x000000FFU
<> 128:9bcdf88f62b0 2745
<> 128:9bcdf88f62b0 2746 /******************** Bits definition for RTC_SSR register ******************/
<> 128:9bcdf88f62b0 2747 #define RTC_SSR_SS 0x0000FFFFU
<> 128:9bcdf88f62b0 2748
<> 128:9bcdf88f62b0 2749 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 128:9bcdf88f62b0 2750 #define RTC_SHIFTR_SUBFS 0x00007FFFU
<> 128:9bcdf88f62b0 2751 #define RTC_SHIFTR_ADD1S 0x80000000U
<> 128:9bcdf88f62b0 2752
<> 128:9bcdf88f62b0 2753 /******************** Bits definition for RTC_TSTR register *****************/
<> 128:9bcdf88f62b0 2754 #define RTC_TSTR_PM 0x00400000U
<> 128:9bcdf88f62b0 2755 #define RTC_TSTR_HT 0x00300000U
<> 128:9bcdf88f62b0 2756 #define RTC_TSTR_HT_0 0x00100000U
<> 128:9bcdf88f62b0 2757 #define RTC_TSTR_HT_1 0x00200000U
<> 128:9bcdf88f62b0 2758 #define RTC_TSTR_HU 0x000F0000U
<> 128:9bcdf88f62b0 2759 #define RTC_TSTR_HU_0 0x00010000U
<> 128:9bcdf88f62b0 2760 #define RTC_TSTR_HU_1 0x00020000U
<> 128:9bcdf88f62b0 2761 #define RTC_TSTR_HU_2 0x00040000U
<> 128:9bcdf88f62b0 2762 #define RTC_TSTR_HU_3 0x00080000U
<> 128:9bcdf88f62b0 2763 #define RTC_TSTR_MNT 0x00007000U
<> 128:9bcdf88f62b0 2764 #define RTC_TSTR_MNT_0 0x00001000U
<> 128:9bcdf88f62b0 2765 #define RTC_TSTR_MNT_1 0x00002000U
<> 128:9bcdf88f62b0 2766 #define RTC_TSTR_MNT_2 0x00004000U
<> 128:9bcdf88f62b0 2767 #define RTC_TSTR_MNU 0x00000F00U
<> 128:9bcdf88f62b0 2768 #define RTC_TSTR_MNU_0 0x00000100U
<> 128:9bcdf88f62b0 2769 #define RTC_TSTR_MNU_1 0x00000200U
<> 128:9bcdf88f62b0 2770 #define RTC_TSTR_MNU_2 0x00000400U
<> 128:9bcdf88f62b0 2771 #define RTC_TSTR_MNU_3 0x00000800U
<> 128:9bcdf88f62b0 2772 #define RTC_TSTR_ST 0x00000070U
<> 128:9bcdf88f62b0 2773 #define RTC_TSTR_ST_0 0x00000010U
<> 128:9bcdf88f62b0 2774 #define RTC_TSTR_ST_1 0x00000020U
<> 128:9bcdf88f62b0 2775 #define RTC_TSTR_ST_2 0x00000040U
<> 128:9bcdf88f62b0 2776 #define RTC_TSTR_SU 0x0000000FU
<> 128:9bcdf88f62b0 2777 #define RTC_TSTR_SU_0 0x00000001U
<> 128:9bcdf88f62b0 2778 #define RTC_TSTR_SU_1 0x00000002U
<> 128:9bcdf88f62b0 2779 #define RTC_TSTR_SU_2 0x00000004U
<> 128:9bcdf88f62b0 2780 #define RTC_TSTR_SU_3 0x00000008U
<> 128:9bcdf88f62b0 2781
<> 128:9bcdf88f62b0 2782 /******************** Bits definition for RTC_TSDR register *****************/
<> 128:9bcdf88f62b0 2783 #define RTC_TSDR_WDU 0x0000E000U
<> 128:9bcdf88f62b0 2784 #define RTC_TSDR_WDU_0 0x00002000U
<> 128:9bcdf88f62b0 2785 #define RTC_TSDR_WDU_1 0x00004000U
<> 128:9bcdf88f62b0 2786 #define RTC_TSDR_WDU_2 0x00008000U
<> 128:9bcdf88f62b0 2787 #define RTC_TSDR_MT 0x00001000U
<> 128:9bcdf88f62b0 2788 #define RTC_TSDR_MU 0x00000F00U
<> 128:9bcdf88f62b0 2789 #define RTC_TSDR_MU_0 0x00000100U
<> 128:9bcdf88f62b0 2790 #define RTC_TSDR_MU_1 0x00000200U
<> 128:9bcdf88f62b0 2791 #define RTC_TSDR_MU_2 0x00000400U
<> 128:9bcdf88f62b0 2792 #define RTC_TSDR_MU_3 0x00000800U
<> 128:9bcdf88f62b0 2793 #define RTC_TSDR_DT 0x00000030U
<> 128:9bcdf88f62b0 2794 #define RTC_TSDR_DT_0 0x00000010U
<> 128:9bcdf88f62b0 2795 #define RTC_TSDR_DT_1 0x00000020U
<> 128:9bcdf88f62b0 2796 #define RTC_TSDR_DU 0x0000000FU
<> 128:9bcdf88f62b0 2797 #define RTC_TSDR_DU_0 0x00000001U
<> 128:9bcdf88f62b0 2798 #define RTC_TSDR_DU_1 0x00000002U
<> 128:9bcdf88f62b0 2799 #define RTC_TSDR_DU_2 0x00000004U
<> 128:9bcdf88f62b0 2800 #define RTC_TSDR_DU_3 0x00000008U
<> 128:9bcdf88f62b0 2801
<> 128:9bcdf88f62b0 2802 /******************** Bits definition for RTC_TSSSR register ****************/
<> 128:9bcdf88f62b0 2803 #define RTC_TSSSR_SS 0x0000FFFFU
<> 128:9bcdf88f62b0 2804
<> 128:9bcdf88f62b0 2805 /******************** Bits definition for RTC_CAL register *****************/
<> 128:9bcdf88f62b0 2806 #define RTC_CALR_CALP 0x00008000U
<> 128:9bcdf88f62b0 2807 #define RTC_CALR_CALW8 0x00004000U
<> 128:9bcdf88f62b0 2808 #define RTC_CALR_CALW16 0x00002000U
<> 128:9bcdf88f62b0 2809 #define RTC_CALR_CALM 0x000001FFU
<> 128:9bcdf88f62b0 2810 #define RTC_CALR_CALM_0 0x00000001U
<> 128:9bcdf88f62b0 2811 #define RTC_CALR_CALM_1 0x00000002U
<> 128:9bcdf88f62b0 2812 #define RTC_CALR_CALM_2 0x00000004U
<> 128:9bcdf88f62b0 2813 #define RTC_CALR_CALM_3 0x00000008U
<> 128:9bcdf88f62b0 2814 #define RTC_CALR_CALM_4 0x00000010U
<> 128:9bcdf88f62b0 2815 #define RTC_CALR_CALM_5 0x00000020U
<> 128:9bcdf88f62b0 2816 #define RTC_CALR_CALM_6 0x00000040U
<> 128:9bcdf88f62b0 2817 #define RTC_CALR_CALM_7 0x00000080U
<> 128:9bcdf88f62b0 2818 #define RTC_CALR_CALM_8 0x00000100U
<> 128:9bcdf88f62b0 2819
<> 128:9bcdf88f62b0 2820 /******************** Bits definition for RTC_TAFCR register ****************/
<> 128:9bcdf88f62b0 2821 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
<> 128:9bcdf88f62b0 2822 #define RTC_TAFCR_TSINSEL 0x00020000U
<> 128:9bcdf88f62b0 2823 #define RTC_TAFCR_TAMPINSEL 0x00010000U
<> 128:9bcdf88f62b0 2824 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
<> 128:9bcdf88f62b0 2825 #define RTC_TAFCR_TAMPPRCH 0x00006000U
<> 128:9bcdf88f62b0 2826 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
<> 128:9bcdf88f62b0 2827 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
<> 128:9bcdf88f62b0 2828 #define RTC_TAFCR_TAMPFLT 0x00001800U
<> 128:9bcdf88f62b0 2829 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
<> 128:9bcdf88f62b0 2830 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
<> 128:9bcdf88f62b0 2831 #define RTC_TAFCR_TAMPFREQ 0x00000700U
<> 128:9bcdf88f62b0 2832 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
<> 128:9bcdf88f62b0 2833 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
<> 128:9bcdf88f62b0 2834 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
<> 128:9bcdf88f62b0 2835 #define RTC_TAFCR_TAMPTS 0x00000080U
<> 128:9bcdf88f62b0 2836 #define RTC_TAFCR_TAMP2TRG 0x00000010U
<> 128:9bcdf88f62b0 2837 #define RTC_TAFCR_TAMP2E 0x00000008U
<> 128:9bcdf88f62b0 2838 #define RTC_TAFCR_TAMPIE 0x00000004U
<> 128:9bcdf88f62b0 2839 #define RTC_TAFCR_TAMP1TRG 0x00000002U
<> 128:9bcdf88f62b0 2840 #define RTC_TAFCR_TAMP1E 0x00000001U
<> 128:9bcdf88f62b0 2841
<> 128:9bcdf88f62b0 2842 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 128:9bcdf88f62b0 2843 #define RTC_ALRMASSR_MASKSS 0x0F000000U
<> 128:9bcdf88f62b0 2844 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
<> 128:9bcdf88f62b0 2845 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
<> 128:9bcdf88f62b0 2846 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
<> 128:9bcdf88f62b0 2847 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
<> 128:9bcdf88f62b0 2848 #define RTC_ALRMASSR_SS 0x00007FFFU
<> 128:9bcdf88f62b0 2849
<> 128:9bcdf88f62b0 2850 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 128:9bcdf88f62b0 2851 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
<> 128:9bcdf88f62b0 2852 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
<> 128:9bcdf88f62b0 2853 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
<> 128:9bcdf88f62b0 2854 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
<> 128:9bcdf88f62b0 2855 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
<> 128:9bcdf88f62b0 2856 #define RTC_ALRMBSSR_SS 0x00007FFFU
<> 128:9bcdf88f62b0 2857
<> 128:9bcdf88f62b0 2858 /******************** Bits definition for RTC_BKP0R register ****************/
<> 128:9bcdf88f62b0 2859 #define RTC_BKP0R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2860
<> 128:9bcdf88f62b0 2861 /******************** Bits definition for RTC_BKP1R register ****************/
<> 128:9bcdf88f62b0 2862 #define RTC_BKP1R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2863
<> 128:9bcdf88f62b0 2864 /******************** Bits definition for RTC_BKP2R register ****************/
<> 128:9bcdf88f62b0 2865 #define RTC_BKP2R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2866
<> 128:9bcdf88f62b0 2867 /******************** Bits definition for RTC_BKP3R register ****************/
<> 128:9bcdf88f62b0 2868 #define RTC_BKP3R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2869
<> 128:9bcdf88f62b0 2870 /******************** Bits definition for RTC_BKP4R register ****************/
<> 128:9bcdf88f62b0 2871 #define RTC_BKP4R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2872
<> 128:9bcdf88f62b0 2873 /******************** Bits definition for RTC_BKP5R register ****************/
<> 128:9bcdf88f62b0 2874 #define RTC_BKP5R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2875
<> 128:9bcdf88f62b0 2876 /******************** Bits definition for RTC_BKP6R register ****************/
<> 128:9bcdf88f62b0 2877 #define RTC_BKP6R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2878
<> 128:9bcdf88f62b0 2879 /******************** Bits definition for RTC_BKP7R register ****************/
<> 128:9bcdf88f62b0 2880 #define RTC_BKP7R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2881
<> 128:9bcdf88f62b0 2882 /******************** Bits definition for RTC_BKP8R register ****************/
<> 128:9bcdf88f62b0 2883 #define RTC_BKP8R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2884
<> 128:9bcdf88f62b0 2885 /******************** Bits definition for RTC_BKP9R register ****************/
<> 128:9bcdf88f62b0 2886 #define RTC_BKP9R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2887
<> 128:9bcdf88f62b0 2888 /******************** Bits definition for RTC_BKP10R register ***************/
<> 128:9bcdf88f62b0 2889 #define RTC_BKP10R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2890
<> 128:9bcdf88f62b0 2891 /******************** Bits definition for RTC_BKP11R register ***************/
<> 128:9bcdf88f62b0 2892 #define RTC_BKP11R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2893
<> 128:9bcdf88f62b0 2894 /******************** Bits definition for RTC_BKP12R register ***************/
<> 128:9bcdf88f62b0 2895 #define RTC_BKP12R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2896
<> 128:9bcdf88f62b0 2897 /******************** Bits definition for RTC_BKP13R register ***************/
<> 128:9bcdf88f62b0 2898 #define RTC_BKP13R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2899
<> 128:9bcdf88f62b0 2900 /******************** Bits definition for RTC_BKP14R register ***************/
<> 128:9bcdf88f62b0 2901 #define RTC_BKP14R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2902
<> 128:9bcdf88f62b0 2903 /******************** Bits definition for RTC_BKP15R register ***************/
<> 128:9bcdf88f62b0 2904 #define RTC_BKP15R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2905
<> 128:9bcdf88f62b0 2906 /******************** Bits definition for RTC_BKP16R register ***************/
<> 128:9bcdf88f62b0 2907 #define RTC_BKP16R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2908
<> 128:9bcdf88f62b0 2909 /******************** Bits definition for RTC_BKP17R register ***************/
<> 128:9bcdf88f62b0 2910 #define RTC_BKP17R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2911
<> 128:9bcdf88f62b0 2912 /******************** Bits definition for RTC_BKP18R register ***************/
<> 128:9bcdf88f62b0 2913 #define RTC_BKP18R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2914
<> 128:9bcdf88f62b0 2915 /******************** Bits definition for RTC_BKP19R register ***************/
<> 128:9bcdf88f62b0 2916 #define RTC_BKP19R 0xFFFFFFFFU
<> 128:9bcdf88f62b0 2917
<> 128:9bcdf88f62b0 2918
<> 128:9bcdf88f62b0 2919
<> 128:9bcdf88f62b0 2920 /******************************************************************************/
<> 128:9bcdf88f62b0 2921 /* */
<> 128:9bcdf88f62b0 2922 /* SD host Interface */
<> 128:9bcdf88f62b0 2923 /* */
<> 128:9bcdf88f62b0 2924 /******************************************************************************/
<> 128:9bcdf88f62b0 2925 /****************** Bit definition for SDIO_POWER register ******************/
<> 128:9bcdf88f62b0 2926 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 128:9bcdf88f62b0 2927 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2928 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2929
<> 128:9bcdf88f62b0 2930 /****************** Bit definition for SDIO_CLKCR register ******************/
<> 128:9bcdf88f62b0 2931 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
<> 128:9bcdf88f62b0 2932 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
<> 128:9bcdf88f62b0 2933 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
<> 128:9bcdf88f62b0 2934 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
<> 128:9bcdf88f62b0 2935
<> 128:9bcdf88f62b0 2936 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 128:9bcdf88f62b0 2937 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2938 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2939
<> 128:9bcdf88f62b0 2940 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
<> 128:9bcdf88f62b0 2941 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
<> 128:9bcdf88f62b0 2942
<> 128:9bcdf88f62b0 2943 /******************* Bit definition for SDIO_ARG register *******************/
<> 128:9bcdf88f62b0 2944 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
<> 128:9bcdf88f62b0 2945
<> 128:9bcdf88f62b0 2946 /******************* Bit definition for SDIO_CMD register *******************/
<> 128:9bcdf88f62b0 2947 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
<> 128:9bcdf88f62b0 2948
<> 128:9bcdf88f62b0 2949 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 128:9bcdf88f62b0 2950 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
<> 128:9bcdf88f62b0 2951 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
<> 128:9bcdf88f62b0 2952
<> 128:9bcdf88f62b0 2953 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
<> 128:9bcdf88f62b0 2954 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 128:9bcdf88f62b0 2955 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
<> 128:9bcdf88f62b0 2956 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
<> 128:9bcdf88f62b0 2957 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
<> 128:9bcdf88f62b0 2958 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
<> 128:9bcdf88f62b0 2959 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
<> 128:9bcdf88f62b0 2960
<> 128:9bcdf88f62b0 2961 /***************** Bit definition for SDIO_RESPCMD register *****************/
<> 128:9bcdf88f62b0 2962 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
<> 128:9bcdf88f62b0 2963
<> 128:9bcdf88f62b0 2964 /****************** Bit definition for SDIO_RESP0 register ******************/
<> 128:9bcdf88f62b0 2965 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
<> 128:9bcdf88f62b0 2966
<> 128:9bcdf88f62b0 2967 /****************** Bit definition for SDIO_RESP1 register ******************/
<> 128:9bcdf88f62b0 2968 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
<> 128:9bcdf88f62b0 2969
<> 128:9bcdf88f62b0 2970 /****************** Bit definition for SDIO_RESP2 register ******************/
<> 128:9bcdf88f62b0 2971 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
<> 128:9bcdf88f62b0 2972
<> 128:9bcdf88f62b0 2973 /****************** Bit definition for SDIO_RESP3 register ******************/
<> 128:9bcdf88f62b0 2974 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
<> 128:9bcdf88f62b0 2975
<> 128:9bcdf88f62b0 2976 /****************** Bit definition for SDIO_RESP4 register ******************/
<> 128:9bcdf88f62b0 2977 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
<> 128:9bcdf88f62b0 2978
<> 128:9bcdf88f62b0 2979 /****************** Bit definition for SDIO_DTIMER register *****************/
<> 128:9bcdf88f62b0 2980 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
<> 128:9bcdf88f62b0 2981
<> 128:9bcdf88f62b0 2982 /****************** Bit definition for SDIO_DLEN register *******************/
<> 128:9bcdf88f62b0 2983 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
<> 128:9bcdf88f62b0 2984
<> 128:9bcdf88f62b0 2985 /****************** Bit definition for SDIO_DCTRL register ******************/
<> 128:9bcdf88f62b0 2986 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
<> 128:9bcdf88f62b0 2987 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
<> 128:9bcdf88f62b0 2988 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
<> 128:9bcdf88f62b0 2989 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
<> 128:9bcdf88f62b0 2990
<> 128:9bcdf88f62b0 2991 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 128:9bcdf88f62b0 2992 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 2993 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 2994 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 2995 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
<> 128:9bcdf88f62b0 2996
<> 128:9bcdf88f62b0 2997 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
<> 128:9bcdf88f62b0 2998 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
<> 128:9bcdf88f62b0 2999 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
<> 128:9bcdf88f62b0 3000 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
<> 128:9bcdf88f62b0 3001
<> 128:9bcdf88f62b0 3002 /****************** Bit definition for SDIO_DCOUNT register *****************/
<> 128:9bcdf88f62b0 3003 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
<> 128:9bcdf88f62b0 3004
<> 128:9bcdf88f62b0 3005 /****************** Bit definition for SDIO_STA register ********************/
<> 128:9bcdf88f62b0 3006 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
<> 128:9bcdf88f62b0 3007 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
<> 128:9bcdf88f62b0 3008 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
<> 128:9bcdf88f62b0 3009 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
<> 128:9bcdf88f62b0 3010 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
<> 128:9bcdf88f62b0 3011 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
<> 128:9bcdf88f62b0 3012 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
<> 128:9bcdf88f62b0 3013 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
<> 128:9bcdf88f62b0 3014 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 128:9bcdf88f62b0 3015 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
<> 128:9bcdf88f62b0 3016 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
<> 128:9bcdf88f62b0 3017 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
<> 128:9bcdf88f62b0 3018 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
<> 128:9bcdf88f62b0 3019 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
<> 128:9bcdf88f62b0 3020 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 128:9bcdf88f62b0 3021 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 128:9bcdf88f62b0 3022 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
<> 128:9bcdf88f62b0 3023 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
<> 128:9bcdf88f62b0 3024 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
<> 128:9bcdf88f62b0 3025 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
<> 128:9bcdf88f62b0 3026 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
<> 128:9bcdf88f62b0 3027 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
<> 128:9bcdf88f62b0 3028 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
<> 128:9bcdf88f62b0 3029 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
<> 128:9bcdf88f62b0 3030
<> 128:9bcdf88f62b0 3031 /******************* Bit definition for SDIO_ICR register *******************/
<> 128:9bcdf88f62b0 3032 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
<> 128:9bcdf88f62b0 3033 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
<> 128:9bcdf88f62b0 3034 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
<> 128:9bcdf88f62b0 3035 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
<> 128:9bcdf88f62b0 3036 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
<> 128:9bcdf88f62b0 3037 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
<> 128:9bcdf88f62b0 3038 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
<> 128:9bcdf88f62b0 3039 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
<> 128:9bcdf88f62b0 3040 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
<> 128:9bcdf88f62b0 3041 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
<> 128:9bcdf88f62b0 3042 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
<> 128:9bcdf88f62b0 3043 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
<> 128:9bcdf88f62b0 3044 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
<> 128:9bcdf88f62b0 3045
<> 128:9bcdf88f62b0 3046 /****************** Bit definition for SDIO_MASK register *******************/
<> 128:9bcdf88f62b0 3047 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
<> 128:9bcdf88f62b0 3048 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
<> 128:9bcdf88f62b0 3049 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
<> 128:9bcdf88f62b0 3050 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
<> 128:9bcdf88f62b0 3051 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 128:9bcdf88f62b0 3052 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 128:9bcdf88f62b0 3053 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
<> 128:9bcdf88f62b0 3054 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
<> 128:9bcdf88f62b0 3055 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
<> 128:9bcdf88f62b0 3056 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
<> 128:9bcdf88f62b0 3057 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
<> 128:9bcdf88f62b0 3058 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
<> 128:9bcdf88f62b0 3059 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
<> 128:9bcdf88f62b0 3060 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
<> 128:9bcdf88f62b0 3061 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
<> 128:9bcdf88f62b0 3062 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
<> 128:9bcdf88f62b0 3063 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
<> 128:9bcdf88f62b0 3064 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
<> 128:9bcdf88f62b0 3065 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
<> 128:9bcdf88f62b0 3066 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
<> 128:9bcdf88f62b0 3067 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
<> 128:9bcdf88f62b0 3068 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
<> 128:9bcdf88f62b0 3069 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
<> 128:9bcdf88f62b0 3070 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
<> 128:9bcdf88f62b0 3071
<> 128:9bcdf88f62b0 3072 /***************** Bit definition for SDIO_FIFOCNT register *****************/
<> 128:9bcdf88f62b0 3073 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
<> 128:9bcdf88f62b0 3074
<> 128:9bcdf88f62b0 3075 /****************** Bit definition for SDIO_FIFO register *******************/
<> 128:9bcdf88f62b0 3076 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
<> 128:9bcdf88f62b0 3077
<> 128:9bcdf88f62b0 3078 /******************************************************************************/
<> 128:9bcdf88f62b0 3079 /* */
<> 128:9bcdf88f62b0 3080 /* Serial Peripheral Interface */
<> 128:9bcdf88f62b0 3081 /* */
<> 128:9bcdf88f62b0 3082 /******************************************************************************/
<> 128:9bcdf88f62b0 3083 /******************* Bit definition for SPI_CR1 register ********************/
<> 128:9bcdf88f62b0 3084 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
<> 128:9bcdf88f62b0 3085 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
<> 128:9bcdf88f62b0 3086 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
<> 128:9bcdf88f62b0 3087
<> 128:9bcdf88f62b0 3088 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
<> 128:9bcdf88f62b0 3089 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3090 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3091 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3092
<> 128:9bcdf88f62b0 3093 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
<> 128:9bcdf88f62b0 3094 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
<> 128:9bcdf88f62b0 3095 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
<> 128:9bcdf88f62b0 3096 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
<> 128:9bcdf88f62b0 3097 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
<> 128:9bcdf88f62b0 3098 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
<> 128:9bcdf88f62b0 3099 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
<> 128:9bcdf88f62b0 3100 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
<> 128:9bcdf88f62b0 3101 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
<> 128:9bcdf88f62b0 3102 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
<> 128:9bcdf88f62b0 3103
<> 128:9bcdf88f62b0 3104 /******************* Bit definition for SPI_CR2 register ********************/
<> 128:9bcdf88f62b0 3105 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
<> 128:9bcdf88f62b0 3106 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
<> 128:9bcdf88f62b0 3107 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
<> 128:9bcdf88f62b0 3108 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
<> 128:9bcdf88f62b0 3109 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
<> 128:9bcdf88f62b0 3110 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
<> 128:9bcdf88f62b0 3111 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
<> 128:9bcdf88f62b0 3112
<> 128:9bcdf88f62b0 3113 /******************** Bit definition for SPI_SR register ********************/
<> 128:9bcdf88f62b0 3114 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
<> 128:9bcdf88f62b0 3115 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
<> 128:9bcdf88f62b0 3116 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
<> 128:9bcdf88f62b0 3117 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
<> 128:9bcdf88f62b0 3118 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
<> 128:9bcdf88f62b0 3119 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
<> 128:9bcdf88f62b0 3120 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
<> 128:9bcdf88f62b0 3121 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
<> 128:9bcdf88f62b0 3122 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
<> 128:9bcdf88f62b0 3123
<> 128:9bcdf88f62b0 3124 /******************** Bit definition for SPI_DR register ********************/
<> 128:9bcdf88f62b0 3125 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
<> 128:9bcdf88f62b0 3126
<> 128:9bcdf88f62b0 3127 /******************* Bit definition for SPI_CRCPR register ******************/
<> 128:9bcdf88f62b0 3128 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
<> 128:9bcdf88f62b0 3129
<> 128:9bcdf88f62b0 3130 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 128:9bcdf88f62b0 3131 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
<> 128:9bcdf88f62b0 3132
<> 128:9bcdf88f62b0 3133 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 128:9bcdf88f62b0 3134 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
<> 128:9bcdf88f62b0 3135
<> 128:9bcdf88f62b0 3136 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 128:9bcdf88f62b0 3137 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 128:9bcdf88f62b0 3138
<> 128:9bcdf88f62b0 3139 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 128:9bcdf88f62b0 3140 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3141 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3142
<> 128:9bcdf88f62b0 3143 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 128:9bcdf88f62b0 3144
<> 128:9bcdf88f62b0 3145 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 128:9bcdf88f62b0 3146 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3147 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3148
<> 128:9bcdf88f62b0 3149 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 128:9bcdf88f62b0 3150
<> 128:9bcdf88f62b0 3151 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 128:9bcdf88f62b0 3152 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3153 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3154
<> 128:9bcdf88f62b0 3155 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 128:9bcdf88f62b0 3156 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
<> 128:9bcdf88f62b0 3157
<> 128:9bcdf88f62b0 3158 /****************** Bit definition for SPI_I2SPR register *******************/
<> 128:9bcdf88f62b0 3159 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
<> 128:9bcdf88f62b0 3160 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
<> 128:9bcdf88f62b0 3161 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
<> 128:9bcdf88f62b0 3162
<> 128:9bcdf88f62b0 3163 /******************************************************************************/
<> 128:9bcdf88f62b0 3164 /* */
<> 128:9bcdf88f62b0 3165 /* SYSCFG */
<> 128:9bcdf88f62b0 3166 /* */
<> 128:9bcdf88f62b0 3167 /******************************************************************************/
<> 128:9bcdf88f62b0 3168 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 128:9bcdf88f62b0 3169 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
<> 128:9bcdf88f62b0 3170 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
<> 128:9bcdf88f62b0 3171 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
<> 128:9bcdf88f62b0 3172 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
<> 128:9bcdf88f62b0 3173
<> 128:9bcdf88f62b0 3174 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 128:9bcdf88f62b0 3175 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
<> 128:9bcdf88f62b0 3176
<> 128:9bcdf88f62b0 3177 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 128:9bcdf88f62b0 3178 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
<> 128:9bcdf88f62b0 3179 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
<> 128:9bcdf88f62b0 3180 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
<> 128:9bcdf88f62b0 3181 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
<> 128:9bcdf88f62b0 3182 /**
<> 128:9bcdf88f62b0 3183 * @brief EXTI0 configuration
<> 128:9bcdf88f62b0 3184 */
<> 128:9bcdf88f62b0 3185 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 128:9bcdf88f62b0 3186 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 128:9bcdf88f62b0 3187 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 128:9bcdf88f62b0 3188 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
<> 128:9bcdf88f62b0 3189 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
<> 128:9bcdf88f62b0 3190 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
<> 128:9bcdf88f62b0 3191
<> 128:9bcdf88f62b0 3192 /**
<> 128:9bcdf88f62b0 3193 * @brief EXTI1 configuration
<> 128:9bcdf88f62b0 3194 */
<> 128:9bcdf88f62b0 3195 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 128:9bcdf88f62b0 3196 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 128:9bcdf88f62b0 3197 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 128:9bcdf88f62b0 3198 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
<> 128:9bcdf88f62b0 3199 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
<> 128:9bcdf88f62b0 3200 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
<> 128:9bcdf88f62b0 3201
<> 128:9bcdf88f62b0 3202 /**
<> 128:9bcdf88f62b0 3203 * @brief EXTI2 configuration
<> 128:9bcdf88f62b0 3204 */
<> 128:9bcdf88f62b0 3205 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 128:9bcdf88f62b0 3206 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 128:9bcdf88f62b0 3207 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 128:9bcdf88f62b0 3208 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
<> 128:9bcdf88f62b0 3209 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
<> 128:9bcdf88f62b0 3210 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
<> 128:9bcdf88f62b0 3211
<> 128:9bcdf88f62b0 3212 /**
<> 128:9bcdf88f62b0 3213 * @brief EXTI3 configuration
<> 128:9bcdf88f62b0 3214 */
<> 128:9bcdf88f62b0 3215 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 128:9bcdf88f62b0 3216 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 128:9bcdf88f62b0 3217 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 128:9bcdf88f62b0 3218 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
<> 128:9bcdf88f62b0 3219 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
<> 128:9bcdf88f62b0 3220 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 128:9bcdf88f62b0 3221
<> 128:9bcdf88f62b0 3222 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 128:9bcdf88f62b0 3223 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
<> 128:9bcdf88f62b0 3224 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
<> 128:9bcdf88f62b0 3225 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
<> 128:9bcdf88f62b0 3226 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
<> 128:9bcdf88f62b0 3227 /**
<> 128:9bcdf88f62b0 3228 * @brief EXTI4 configuration
<> 128:9bcdf88f62b0 3229 */
<> 128:9bcdf88f62b0 3230 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 128:9bcdf88f62b0 3231 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 128:9bcdf88f62b0 3232 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 128:9bcdf88f62b0 3233 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
<> 128:9bcdf88f62b0 3234 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
<> 128:9bcdf88f62b0 3235 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
<> 128:9bcdf88f62b0 3236
<> 128:9bcdf88f62b0 3237 /**
<> 128:9bcdf88f62b0 3238 * @brief EXTI5 configuration
<> 128:9bcdf88f62b0 3239 */
<> 128:9bcdf88f62b0 3240 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 128:9bcdf88f62b0 3241 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 128:9bcdf88f62b0 3242 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 128:9bcdf88f62b0 3243 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
<> 128:9bcdf88f62b0 3244 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
<> 128:9bcdf88f62b0 3245 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
<> 128:9bcdf88f62b0 3246
<> 128:9bcdf88f62b0 3247 /**
<> 128:9bcdf88f62b0 3248 * @brief EXTI6 configuration
<> 128:9bcdf88f62b0 3249 */
<> 128:9bcdf88f62b0 3250 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 128:9bcdf88f62b0 3251 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 128:9bcdf88f62b0 3252 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 128:9bcdf88f62b0 3253 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
<> 128:9bcdf88f62b0 3254 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
<> 128:9bcdf88f62b0 3255 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
<> 128:9bcdf88f62b0 3256
<> 128:9bcdf88f62b0 3257 /**
<> 128:9bcdf88f62b0 3258 * @brief EXTI7 configuration
<> 128:9bcdf88f62b0 3259 */
<> 128:9bcdf88f62b0 3260 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 128:9bcdf88f62b0 3261 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 128:9bcdf88f62b0 3262 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 128:9bcdf88f62b0 3263 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
<> 128:9bcdf88f62b0 3264 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
<> 128:9bcdf88f62b0 3265 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 128:9bcdf88f62b0 3266
<> 128:9bcdf88f62b0 3267
<> 128:9bcdf88f62b0 3268 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 128:9bcdf88f62b0 3269 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
<> 128:9bcdf88f62b0 3270 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
<> 128:9bcdf88f62b0 3271 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
<> 128:9bcdf88f62b0 3272 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
<> 128:9bcdf88f62b0 3273
<> 128:9bcdf88f62b0 3274 /**
<> 128:9bcdf88f62b0 3275 * @brief EXTI8 configuration
<> 128:9bcdf88f62b0 3276 */
<> 128:9bcdf88f62b0 3277 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 128:9bcdf88f62b0 3278 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 128:9bcdf88f62b0 3279 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 128:9bcdf88f62b0 3280 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
<> 128:9bcdf88f62b0 3281 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
<> 128:9bcdf88f62b0 3282 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
<> 128:9bcdf88f62b0 3283
<> 128:9bcdf88f62b0 3284 /**
<> 128:9bcdf88f62b0 3285 * @brief EXTI9 configuration
<> 128:9bcdf88f62b0 3286 */
<> 128:9bcdf88f62b0 3287 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 128:9bcdf88f62b0 3288 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 128:9bcdf88f62b0 3289 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 128:9bcdf88f62b0 3290 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
<> 128:9bcdf88f62b0 3291 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
<> 128:9bcdf88f62b0 3292 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
<> 128:9bcdf88f62b0 3293
<> 128:9bcdf88f62b0 3294 /**
<> 128:9bcdf88f62b0 3295 * @brief EXTI10 configuration
<> 128:9bcdf88f62b0 3296 */
<> 128:9bcdf88f62b0 3297 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 128:9bcdf88f62b0 3298 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 128:9bcdf88f62b0 3299 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 128:9bcdf88f62b0 3300 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
<> 128:9bcdf88f62b0 3301 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
<> 128:9bcdf88f62b0 3302 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
<> 128:9bcdf88f62b0 3303
<> 128:9bcdf88f62b0 3304 /**
<> 128:9bcdf88f62b0 3305 * @brief EXTI11 configuration
<> 128:9bcdf88f62b0 3306 */
<> 128:9bcdf88f62b0 3307 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 128:9bcdf88f62b0 3308 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 128:9bcdf88f62b0 3309 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 128:9bcdf88f62b0 3310 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
<> 128:9bcdf88f62b0 3311 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
<> 128:9bcdf88f62b0 3312 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 128:9bcdf88f62b0 3313
<> 128:9bcdf88f62b0 3314 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 128:9bcdf88f62b0 3315 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
<> 128:9bcdf88f62b0 3316 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
<> 128:9bcdf88f62b0 3317 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
<> 128:9bcdf88f62b0 3318 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
<> 128:9bcdf88f62b0 3319 /**
<> 128:9bcdf88f62b0 3320 * @brief EXTI12 configuration
<> 128:9bcdf88f62b0 3321 */
<> 128:9bcdf88f62b0 3322 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 128:9bcdf88f62b0 3323 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 128:9bcdf88f62b0 3324 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 128:9bcdf88f62b0 3325 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
<> 128:9bcdf88f62b0 3326 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
<> 128:9bcdf88f62b0 3327 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
<> 128:9bcdf88f62b0 3328
<> 128:9bcdf88f62b0 3329 /**
<> 128:9bcdf88f62b0 3330 * @brief EXTI13 configuration
<> 128:9bcdf88f62b0 3331 */
<> 128:9bcdf88f62b0 3332 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 128:9bcdf88f62b0 3333 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 128:9bcdf88f62b0 3334 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 128:9bcdf88f62b0 3335 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
<> 128:9bcdf88f62b0 3336 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
<> 128:9bcdf88f62b0 3337 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
<> 128:9bcdf88f62b0 3338
<> 128:9bcdf88f62b0 3339 /**
<> 128:9bcdf88f62b0 3340 * @brief EXTI14 configuration
<> 128:9bcdf88f62b0 3341 */
<> 128:9bcdf88f62b0 3342 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 128:9bcdf88f62b0 3343 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 128:9bcdf88f62b0 3344 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 128:9bcdf88f62b0 3345 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
<> 128:9bcdf88f62b0 3346 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
<> 128:9bcdf88f62b0 3347 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
<> 128:9bcdf88f62b0 3348
<> 128:9bcdf88f62b0 3349 /**
<> 128:9bcdf88f62b0 3350 * @brief EXTI15 configuration
<> 128:9bcdf88f62b0 3351 */
<> 128:9bcdf88f62b0 3352 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 128:9bcdf88f62b0 3353 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 128:9bcdf88f62b0 3354 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 128:9bcdf88f62b0 3355 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
<> 128:9bcdf88f62b0 3356 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
<> 128:9bcdf88f62b0 3357 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
<> 128:9bcdf88f62b0 3358
<> 128:9bcdf88f62b0 3359 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 128:9bcdf88f62b0 3360 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
<> 128:9bcdf88f62b0 3361 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
<> 128:9bcdf88f62b0 3362
<> 128:9bcdf88f62b0 3363 /******************************************************************************/
<> 128:9bcdf88f62b0 3364 /* */
<> 128:9bcdf88f62b0 3365 /* TIM */
<> 128:9bcdf88f62b0 3366 /* */
<> 128:9bcdf88f62b0 3367 /******************************************************************************/
<> 128:9bcdf88f62b0 3368 /******************* Bit definition for TIM_CR1 register ********************/
<> 128:9bcdf88f62b0 3369 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
<> 128:9bcdf88f62b0 3370 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
<> 128:9bcdf88f62b0 3371 #define TIM_CR1_URS 0x0004U /*!<Update request source */
<> 128:9bcdf88f62b0 3372 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
<> 128:9bcdf88f62b0 3373 #define TIM_CR1_DIR 0x0010U /*!<Direction */
<> 128:9bcdf88f62b0 3374
<> 128:9bcdf88f62b0 3375 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 128:9bcdf88f62b0 3376 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3377 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3378
<> 128:9bcdf88f62b0 3379 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
<> 128:9bcdf88f62b0 3380
<> 128:9bcdf88f62b0 3381 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
<> 128:9bcdf88f62b0 3382 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3383 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3384
<> 128:9bcdf88f62b0 3385 /******************* Bit definition for TIM_CR2 register ********************/
<> 128:9bcdf88f62b0 3386 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
<> 128:9bcdf88f62b0 3387 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
<> 128:9bcdf88f62b0 3388 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
<> 128:9bcdf88f62b0 3389
<> 128:9bcdf88f62b0 3390 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 128:9bcdf88f62b0 3391 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3392 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3393 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3394
<> 128:9bcdf88f62b0 3395 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
<> 128:9bcdf88f62b0 3396 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
<> 128:9bcdf88f62b0 3397 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
<> 128:9bcdf88f62b0 3398 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
<> 128:9bcdf88f62b0 3399 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
<> 128:9bcdf88f62b0 3400 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
<> 128:9bcdf88f62b0 3401 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
<> 128:9bcdf88f62b0 3402 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
<> 128:9bcdf88f62b0 3403
<> 128:9bcdf88f62b0 3404 /******************* Bit definition for TIM_SMCR register *******************/
<> 128:9bcdf88f62b0 3405 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 128:9bcdf88f62b0 3406 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3407 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3408 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3409
<> 128:9bcdf88f62b0 3410 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
<> 128:9bcdf88f62b0 3411 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3412 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3413 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3414
<> 128:9bcdf88f62b0 3415 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
<> 128:9bcdf88f62b0 3416
<> 128:9bcdf88f62b0 3417 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 128:9bcdf88f62b0 3418 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3419 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3420 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3421 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3422
<> 128:9bcdf88f62b0 3423 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 128:9bcdf88f62b0 3424 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3425 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3426
<> 128:9bcdf88f62b0 3427 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
<> 128:9bcdf88f62b0 3428 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
<> 128:9bcdf88f62b0 3429
<> 128:9bcdf88f62b0 3430 /******************* Bit definition for TIM_DIER register *******************/
<> 128:9bcdf88f62b0 3431 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
<> 128:9bcdf88f62b0 3432 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
<> 128:9bcdf88f62b0 3433 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
<> 128:9bcdf88f62b0 3434 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
<> 128:9bcdf88f62b0 3435 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
<> 128:9bcdf88f62b0 3436 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
<> 128:9bcdf88f62b0 3437 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
<> 128:9bcdf88f62b0 3438 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
<> 128:9bcdf88f62b0 3439 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
<> 128:9bcdf88f62b0 3440 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
<> 128:9bcdf88f62b0 3441 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
<> 128:9bcdf88f62b0 3442 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
<> 128:9bcdf88f62b0 3443 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
<> 128:9bcdf88f62b0 3444 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
<> 128:9bcdf88f62b0 3445 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
<> 128:9bcdf88f62b0 3446
<> 128:9bcdf88f62b0 3447 /******************** Bit definition for TIM_SR register ********************/
<> 128:9bcdf88f62b0 3448 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
<> 128:9bcdf88f62b0 3449 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
<> 128:9bcdf88f62b0 3450 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
<> 128:9bcdf88f62b0 3451 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
<> 128:9bcdf88f62b0 3452 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
<> 128:9bcdf88f62b0 3453 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
<> 128:9bcdf88f62b0 3454 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
<> 128:9bcdf88f62b0 3455 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
<> 128:9bcdf88f62b0 3456 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
<> 128:9bcdf88f62b0 3457 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
<> 128:9bcdf88f62b0 3458 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
<> 128:9bcdf88f62b0 3459 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
<> 128:9bcdf88f62b0 3460
<> 128:9bcdf88f62b0 3461 /******************* Bit definition for TIM_EGR register ********************/
<> 128:9bcdf88f62b0 3462 #define TIM_EGR_UG 0x01U /*!<Update Generation */
<> 128:9bcdf88f62b0 3463 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
<> 128:9bcdf88f62b0 3464 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
<> 128:9bcdf88f62b0 3465 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
<> 128:9bcdf88f62b0 3466 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
<> 128:9bcdf88f62b0 3467 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
<> 128:9bcdf88f62b0 3468 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
<> 128:9bcdf88f62b0 3469 #define TIM_EGR_BG 0x80U /*!<Break Generation */
<> 128:9bcdf88f62b0 3470
<> 128:9bcdf88f62b0 3471 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 128:9bcdf88f62b0 3472 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 128:9bcdf88f62b0 3473 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3474 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3475
<> 128:9bcdf88f62b0 3476 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
<> 128:9bcdf88f62b0 3477 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
<> 128:9bcdf88f62b0 3478
<> 128:9bcdf88f62b0 3479 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 128:9bcdf88f62b0 3480 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3481 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3482 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3483
<> 128:9bcdf88f62b0 3484 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
<> 128:9bcdf88f62b0 3485
<> 128:9bcdf88f62b0 3486 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 128:9bcdf88f62b0 3487 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3488 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3489
<> 128:9bcdf88f62b0 3490 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
<> 128:9bcdf88f62b0 3491 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
<> 128:9bcdf88f62b0 3492
<> 128:9bcdf88f62b0 3493 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 128:9bcdf88f62b0 3494 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3495 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3496 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3497
<> 128:9bcdf88f62b0 3498 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
<> 128:9bcdf88f62b0 3499
<> 128:9bcdf88f62b0 3500 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 3501
<> 128:9bcdf88f62b0 3502 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 128:9bcdf88f62b0 3503 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3504 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3505
<> 128:9bcdf88f62b0 3506 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 128:9bcdf88f62b0 3507 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3508 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3509 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3510 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3511
<> 128:9bcdf88f62b0 3512 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 128:9bcdf88f62b0 3513 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3514 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3515
<> 128:9bcdf88f62b0 3516 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 128:9bcdf88f62b0 3517 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3518 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3519 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3520 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3521
<> 128:9bcdf88f62b0 3522 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 128:9bcdf88f62b0 3523 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 128:9bcdf88f62b0 3524 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3525 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3526
<> 128:9bcdf88f62b0 3527 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
<> 128:9bcdf88f62b0 3528 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
<> 128:9bcdf88f62b0 3529
<> 128:9bcdf88f62b0 3530 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 128:9bcdf88f62b0 3531 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3532 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3533 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3534
<> 128:9bcdf88f62b0 3535 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
<> 128:9bcdf88f62b0 3536
<> 128:9bcdf88f62b0 3537 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 128:9bcdf88f62b0 3538 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3539 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3540
<> 128:9bcdf88f62b0 3541 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
<> 128:9bcdf88f62b0 3542 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
<> 128:9bcdf88f62b0 3543
<> 128:9bcdf88f62b0 3544 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 128:9bcdf88f62b0 3545 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3546 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3547 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3548
<> 128:9bcdf88f62b0 3549 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
<> 128:9bcdf88f62b0 3550
<> 128:9bcdf88f62b0 3551 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 3552
<> 128:9bcdf88f62b0 3553 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 128:9bcdf88f62b0 3554 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3555 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3556
<> 128:9bcdf88f62b0 3557 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 128:9bcdf88f62b0 3558 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3559 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3560 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3561 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3562
<> 128:9bcdf88f62b0 3563 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 128:9bcdf88f62b0 3564 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3565 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3566
<> 128:9bcdf88f62b0 3567 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 128:9bcdf88f62b0 3568 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3569 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3570 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3571 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3572
<> 128:9bcdf88f62b0 3573 /******************* Bit definition for TIM_CCER register *******************/
<> 128:9bcdf88f62b0 3574 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
<> 128:9bcdf88f62b0 3575 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
<> 128:9bcdf88f62b0 3576 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
<> 128:9bcdf88f62b0 3577 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 128:9bcdf88f62b0 3578 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
<> 128:9bcdf88f62b0 3579 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
<> 128:9bcdf88f62b0 3580 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
<> 128:9bcdf88f62b0 3581 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 128:9bcdf88f62b0 3582 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
<> 128:9bcdf88f62b0 3583 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
<> 128:9bcdf88f62b0 3584 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
<> 128:9bcdf88f62b0 3585 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 128:9bcdf88f62b0 3586 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
<> 128:9bcdf88f62b0 3587 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
<> 128:9bcdf88f62b0 3588 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
<> 128:9bcdf88f62b0 3589
<> 128:9bcdf88f62b0 3590 /******************* Bit definition for TIM_CNT register ********************/
<> 128:9bcdf88f62b0 3591 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
<> 128:9bcdf88f62b0 3592
<> 128:9bcdf88f62b0 3593 /******************* Bit definition for TIM_PSC register ********************/
<> 128:9bcdf88f62b0 3594 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
<> 128:9bcdf88f62b0 3595
<> 128:9bcdf88f62b0 3596 /******************* Bit definition for TIM_ARR register ********************/
<> 128:9bcdf88f62b0 3597 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
<> 128:9bcdf88f62b0 3598
<> 128:9bcdf88f62b0 3599 /******************* Bit definition for TIM_RCR register ********************/
<> 128:9bcdf88f62b0 3600 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
<> 128:9bcdf88f62b0 3601
<> 128:9bcdf88f62b0 3602 /******************* Bit definition for TIM_CCR1 register *******************/
<> 128:9bcdf88f62b0 3603 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
<> 128:9bcdf88f62b0 3604
<> 128:9bcdf88f62b0 3605 /******************* Bit definition for TIM_CCR2 register *******************/
<> 128:9bcdf88f62b0 3606 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
<> 128:9bcdf88f62b0 3607
<> 128:9bcdf88f62b0 3608 /******************* Bit definition for TIM_CCR3 register *******************/
<> 128:9bcdf88f62b0 3609 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
<> 128:9bcdf88f62b0 3610
<> 128:9bcdf88f62b0 3611 /******************* Bit definition for TIM_CCR4 register *******************/
<> 128:9bcdf88f62b0 3612 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
<> 128:9bcdf88f62b0 3613
<> 128:9bcdf88f62b0 3614 /******************* Bit definition for TIM_BDTR register *******************/
<> 128:9bcdf88f62b0 3615 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 128:9bcdf88f62b0 3616 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3617 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3618 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3619 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3620 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3621 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 3622 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
<> 128:9bcdf88f62b0 3623 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
<> 128:9bcdf88f62b0 3624
<> 128:9bcdf88f62b0 3625 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 128:9bcdf88f62b0 3626 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3627 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3628
<> 128:9bcdf88f62b0 3629 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
<> 128:9bcdf88f62b0 3630 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
<> 128:9bcdf88f62b0 3631 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
<> 128:9bcdf88f62b0 3632 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
<> 128:9bcdf88f62b0 3633 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
<> 128:9bcdf88f62b0 3634 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
<> 128:9bcdf88f62b0 3635
<> 128:9bcdf88f62b0 3636 /******************* Bit definition for TIM_DCR register ********************/
<> 128:9bcdf88f62b0 3637 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 128:9bcdf88f62b0 3638 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3639 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3640 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3641 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3642 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3643
<> 128:9bcdf88f62b0 3644 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 128:9bcdf88f62b0 3645 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3646 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3647 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3648 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3649 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3650
<> 128:9bcdf88f62b0 3651 /******************* Bit definition for TIM_DMAR register *******************/
<> 128:9bcdf88f62b0 3652 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
<> 128:9bcdf88f62b0 3653
<> 128:9bcdf88f62b0 3654 /******************* Bit definition for TIM_OR register *********************/
<> 128:9bcdf88f62b0 3655 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 128:9bcdf88f62b0 3656 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3657 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3658 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 128:9bcdf88f62b0 3659 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3660 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3661
<> 128:9bcdf88f62b0 3662
<> 128:9bcdf88f62b0 3663 /******************************************************************************/
<> 128:9bcdf88f62b0 3664 /* */
<> 128:9bcdf88f62b0 3665 /* Universal Synchronous Asynchronous Receiver Transmitter */
<> 128:9bcdf88f62b0 3666 /* */
<> 128:9bcdf88f62b0 3667 /******************************************************************************/
<> 128:9bcdf88f62b0 3668 /******************* Bit definition for USART_SR register *******************/
<> 128:9bcdf88f62b0 3669 #define USART_SR_PE 0x0001U /*!<Parity Error */
<> 128:9bcdf88f62b0 3670 #define USART_SR_FE 0x0002U /*!<Framing Error */
<> 128:9bcdf88f62b0 3671 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
<> 128:9bcdf88f62b0 3672 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
<> 128:9bcdf88f62b0 3673 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
<> 128:9bcdf88f62b0 3674 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
<> 128:9bcdf88f62b0 3675 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
<> 128:9bcdf88f62b0 3676 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
<> 128:9bcdf88f62b0 3677 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
<> 128:9bcdf88f62b0 3678 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
<> 128:9bcdf88f62b0 3679
<> 128:9bcdf88f62b0 3680 /******************* Bit definition for USART_DR register *******************/
<> 128:9bcdf88f62b0 3681 #define USART_DR_DR 0x01FFU /*!<Data value */
<> 128:9bcdf88f62b0 3682
<> 128:9bcdf88f62b0 3683 /****************** Bit definition for USART_BRR register *******************/
<> 128:9bcdf88f62b0 3684 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
<> 128:9bcdf88f62b0 3685 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
<> 128:9bcdf88f62b0 3686
<> 128:9bcdf88f62b0 3687 /****************** Bit definition for USART_CR1 register *******************/
<> 128:9bcdf88f62b0 3688 #define USART_CR1_SBK 0x0001U /*!<Send Break */
<> 128:9bcdf88f62b0 3689 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
<> 128:9bcdf88f62b0 3690 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
<> 128:9bcdf88f62b0 3691 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
<> 128:9bcdf88f62b0 3692 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
<> 128:9bcdf88f62b0 3693 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
<> 128:9bcdf88f62b0 3694 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
<> 128:9bcdf88f62b0 3695 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
<> 128:9bcdf88f62b0 3696 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
<> 128:9bcdf88f62b0 3697 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
<> 128:9bcdf88f62b0 3698 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
<> 128:9bcdf88f62b0 3699 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
<> 128:9bcdf88f62b0 3700 #define USART_CR1_M 0x1000U /*!<Word length */
<> 128:9bcdf88f62b0 3701 #define USART_CR1_UE 0x2000U /*!<USART Enable */
<> 128:9bcdf88f62b0 3702 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
<> 128:9bcdf88f62b0 3703
<> 128:9bcdf88f62b0 3704 /****************** Bit definition for USART_CR2 register *******************/
<> 128:9bcdf88f62b0 3705 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
<> 128:9bcdf88f62b0 3706 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
<> 128:9bcdf88f62b0 3707 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
<> 128:9bcdf88f62b0 3708 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
<> 128:9bcdf88f62b0 3709 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
<> 128:9bcdf88f62b0 3710 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
<> 128:9bcdf88f62b0 3711 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
<> 128:9bcdf88f62b0 3712
<> 128:9bcdf88f62b0 3713 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
<> 128:9bcdf88f62b0 3714 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3715 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3716
<> 128:9bcdf88f62b0 3717 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
<> 128:9bcdf88f62b0 3718
<> 128:9bcdf88f62b0 3719 /****************** Bit definition for USART_CR3 register *******************/
<> 128:9bcdf88f62b0 3720 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
<> 128:9bcdf88f62b0 3721 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
<> 128:9bcdf88f62b0 3722 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
<> 128:9bcdf88f62b0 3723 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
<> 128:9bcdf88f62b0 3724 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
<> 128:9bcdf88f62b0 3725 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
<> 128:9bcdf88f62b0 3726 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
<> 128:9bcdf88f62b0 3727 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
<> 128:9bcdf88f62b0 3728 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
<> 128:9bcdf88f62b0 3729 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
<> 128:9bcdf88f62b0 3730 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
<> 128:9bcdf88f62b0 3731 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
<> 128:9bcdf88f62b0 3732
<> 128:9bcdf88f62b0 3733 /****************** Bit definition for USART_GTPR register ******************/
<> 128:9bcdf88f62b0 3734 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
<> 128:9bcdf88f62b0 3735 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3736 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3737 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3738 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3739 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3740 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 3741 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
<> 128:9bcdf88f62b0 3742 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
<> 128:9bcdf88f62b0 3743
<> 128:9bcdf88f62b0 3744 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
<> 128:9bcdf88f62b0 3745
<> 128:9bcdf88f62b0 3746 /******************************************************************************/
<> 128:9bcdf88f62b0 3747 /* */
<> 128:9bcdf88f62b0 3748 /* Window WATCHDOG */
<> 128:9bcdf88f62b0 3749 /* */
<> 128:9bcdf88f62b0 3750 /******************************************************************************/
<> 128:9bcdf88f62b0 3751 /******************* Bit definition for WWDG_CR register ********************/
<> 128:9bcdf88f62b0 3752 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 128:9bcdf88f62b0 3753 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3754 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3755 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3756 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3757 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3758 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
<> 128:9bcdf88f62b0 3759 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
<> 128:9bcdf88f62b0 3760 /* Legacy defines */
<> 128:9bcdf88f62b0 3761 #define WWDG_CR_T0 WWDG_CR_T_0
<> 128:9bcdf88f62b0 3762 #define WWDG_CR_T1 WWDG_CR_T_1
<> 128:9bcdf88f62b0 3763 #define WWDG_CR_T2 WWDG_CR_T_2
<> 128:9bcdf88f62b0 3764 #define WWDG_CR_T3 WWDG_CR_T_3
<> 128:9bcdf88f62b0 3765 #define WWDG_CR_T4 WWDG_CR_T_4
<> 128:9bcdf88f62b0 3766 #define WWDG_CR_T5 WWDG_CR_T_5
<> 128:9bcdf88f62b0 3767 #define WWDG_CR_T6 WWDG_CR_T_6
<> 128:9bcdf88f62b0 3768
<> 128:9bcdf88f62b0 3769 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
<> 128:9bcdf88f62b0 3770
<> 128:9bcdf88f62b0 3771 /******************* Bit definition for WWDG_CFR register *******************/
<> 128:9bcdf88f62b0 3772 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
<> 128:9bcdf88f62b0 3773 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3774 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3775 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3776 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3777 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3778 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 3779 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
<> 128:9bcdf88f62b0 3780 /* Legacy defines */
<> 128:9bcdf88f62b0 3781 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 128:9bcdf88f62b0 3782 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 128:9bcdf88f62b0 3783 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 128:9bcdf88f62b0 3784 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 128:9bcdf88f62b0 3785 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 128:9bcdf88f62b0 3786 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 128:9bcdf88f62b0 3787 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 128:9bcdf88f62b0 3788
<> 128:9bcdf88f62b0 3789 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 128:9bcdf88f62b0 3790 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3791 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3792 /* Legacy defines */
<> 128:9bcdf88f62b0 3793 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 128:9bcdf88f62b0 3794 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 128:9bcdf88f62b0 3795
<> 128:9bcdf88f62b0 3796 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
<> 128:9bcdf88f62b0 3797
<> 128:9bcdf88f62b0 3798 /******************* Bit definition for WWDG_SR register ********************/
<> 128:9bcdf88f62b0 3799 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
<> 128:9bcdf88f62b0 3800
<> 128:9bcdf88f62b0 3801
<> 128:9bcdf88f62b0 3802 /******************************************************************************/
<> 128:9bcdf88f62b0 3803 /* */
<> 128:9bcdf88f62b0 3804 /* DBG */
<> 128:9bcdf88f62b0 3805 /* */
<> 128:9bcdf88f62b0 3806 /******************************************************************************/
<> 128:9bcdf88f62b0 3807 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 128:9bcdf88f62b0 3808 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 128:9bcdf88f62b0 3809 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
<> 128:9bcdf88f62b0 3810
<> 128:9bcdf88f62b0 3811 /******************** Bit definition for DBGMCU_CR register *****************/
<> 128:9bcdf88f62b0 3812 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 128:9bcdf88f62b0 3813 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 128:9bcdf88f62b0 3814 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 128:9bcdf88f62b0 3815 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 128:9bcdf88f62b0 3816
<> 128:9bcdf88f62b0 3817 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 128:9bcdf88f62b0 3818 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
<> 128:9bcdf88f62b0 3819 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
<> 128:9bcdf88f62b0 3820
<> 128:9bcdf88f62b0 3821 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 128:9bcdf88f62b0 3822 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
<> 128:9bcdf88f62b0 3823 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
<> 128:9bcdf88f62b0 3824 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
<> 128:9bcdf88f62b0 3825 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 128:9bcdf88f62b0 3826 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 128:9bcdf88f62b0 3827 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
<> 128:9bcdf88f62b0 3828 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
<> 128:9bcdf88f62b0 3829 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
<> 128:9bcdf88f62b0 3830 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
<> 128:9bcdf88f62b0 3831 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 128:9bcdf88f62b0 3832 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 128:9bcdf88f62b0 3833 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 128:9bcdf88f62b0 3834 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 128:9bcdf88f62b0 3835 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 128:9bcdf88f62b0 3836 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
<> 128:9bcdf88f62b0 3837 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 128:9bcdf88f62b0 3838 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
<> 128:9bcdf88f62b0 3839 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 3840 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
<> 128:9bcdf88f62b0 3841
<> 128:9bcdf88f62b0 3842 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 128:9bcdf88f62b0 3843 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 128:9bcdf88f62b0 3844 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
<> 128:9bcdf88f62b0 3845 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 128:9bcdf88f62b0 3846 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
<> 128:9bcdf88f62b0 3847 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
<> 128:9bcdf88f62b0 3848
<> 128:9bcdf88f62b0 3849 /******************************************************************************/
<> 128:9bcdf88f62b0 3850 /* */
<> 128:9bcdf88f62b0 3851 /* USB_OTG */
<> 128:9bcdf88f62b0 3852 /* */
<> 128:9bcdf88f62b0 3853 /******************************************************************************/
<> 128:9bcdf88f62b0 3854 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
<> 128:9bcdf88f62b0 3855 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
<> 128:9bcdf88f62b0 3856 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
<> 128:9bcdf88f62b0 3857 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
<> 128:9bcdf88f62b0 3858 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
<> 128:9bcdf88f62b0 3859 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
<> 128:9bcdf88f62b0 3860 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
<> 128:9bcdf88f62b0 3861 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
<> 128:9bcdf88f62b0 3862 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
<> 128:9bcdf88f62b0 3863 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
<> 128:9bcdf88f62b0 3864 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
<> 128:9bcdf88f62b0 3865
<> 128:9bcdf88f62b0 3866 /******************** Bit definition forUSB_OTG_HCFG register ********************/
<> 128:9bcdf88f62b0 3867
<> 128:9bcdf88f62b0 3868 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
<> 128:9bcdf88f62b0 3869 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3870 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3871 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
<> 128:9bcdf88f62b0 3872
<> 128:9bcdf88f62b0 3873 /******************** Bit definition forUSB_OTG_DCFG register ********************/
<> 128:9bcdf88f62b0 3874
<> 128:9bcdf88f62b0 3875 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
<> 128:9bcdf88f62b0 3876 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3877 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3878 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
<> 128:9bcdf88f62b0 3879
<> 128:9bcdf88f62b0 3880 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
<> 128:9bcdf88f62b0 3881 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3882 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3883 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3884 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3885 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3886 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
<> 128:9bcdf88f62b0 3887 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
<> 128:9bcdf88f62b0 3888
<> 128:9bcdf88f62b0 3889 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
<> 128:9bcdf88f62b0 3890 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3891 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3892
<> 128:9bcdf88f62b0 3893 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
<> 128:9bcdf88f62b0 3894 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3895 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3896
<> 128:9bcdf88f62b0 3897 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
<> 128:9bcdf88f62b0 3898 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
<> 128:9bcdf88f62b0 3899 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
<> 128:9bcdf88f62b0 3900 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
<> 128:9bcdf88f62b0 3901
<> 128:9bcdf88f62b0 3902 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
<> 128:9bcdf88f62b0 3903 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
<> 128:9bcdf88f62b0 3904 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
<> 128:9bcdf88f62b0 3905 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
<> 128:9bcdf88f62b0 3906 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
<> 128:9bcdf88f62b0 3907 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
<> 128:9bcdf88f62b0 3908 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
<> 128:9bcdf88f62b0 3909
<> 128:9bcdf88f62b0 3910 /******************** Bit definition forUSB_OTG_DCTL register ********************/
<> 128:9bcdf88f62b0 3911 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
<> 128:9bcdf88f62b0 3912 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
<> 128:9bcdf88f62b0 3913 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
<> 128:9bcdf88f62b0 3914 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
<> 128:9bcdf88f62b0 3915
<> 128:9bcdf88f62b0 3916 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
<> 128:9bcdf88f62b0 3917 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3918 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3919 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3920 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
<> 128:9bcdf88f62b0 3921 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
<> 128:9bcdf88f62b0 3922 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
<> 128:9bcdf88f62b0 3923 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
<> 128:9bcdf88f62b0 3924 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
<> 128:9bcdf88f62b0 3925
<> 128:9bcdf88f62b0 3926 /******************** Bit definition forUSB_OTG_HFIR register ********************/
<> 128:9bcdf88f62b0 3927 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
<> 128:9bcdf88f62b0 3928
<> 128:9bcdf88f62b0 3929 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
<> 128:9bcdf88f62b0 3930 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
<> 128:9bcdf88f62b0 3931 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
<> 128:9bcdf88f62b0 3932
<> 128:9bcdf88f62b0 3933 /******************** Bit definition forUSB_OTG_DSTS register ********************/
<> 128:9bcdf88f62b0 3934 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
<> 128:9bcdf88f62b0 3935
<> 128:9bcdf88f62b0 3936 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
<> 128:9bcdf88f62b0 3937 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3938 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3939 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
<> 128:9bcdf88f62b0 3940 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
<> 128:9bcdf88f62b0 3941
<> 128:9bcdf88f62b0 3942 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
<> 128:9bcdf88f62b0 3943 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
<> 128:9bcdf88f62b0 3944
<> 128:9bcdf88f62b0 3945 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
<> 128:9bcdf88f62b0 3946 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3947 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3948 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3949 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3950 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
<> 128:9bcdf88f62b0 3951 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
<> 128:9bcdf88f62b0 3952 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
<> 128:9bcdf88f62b0 3953
<> 128:9bcdf88f62b0 3954 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
<> 128:9bcdf88f62b0 3955
<> 128:9bcdf88f62b0 3956 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
<> 128:9bcdf88f62b0 3957 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3958 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3959 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3960 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 128:9bcdf88f62b0 3961 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
<> 128:9bcdf88f62b0 3962 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
<> 128:9bcdf88f62b0 3963
<> 128:9bcdf88f62b0 3964 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
<> 128:9bcdf88f62b0 3965 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3966 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3967 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3968 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3969 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
<> 128:9bcdf88f62b0 3970 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
<> 128:9bcdf88f62b0 3971 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
<> 128:9bcdf88f62b0 3972 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
<> 128:9bcdf88f62b0 3973 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
<> 128:9bcdf88f62b0 3974 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
<> 128:9bcdf88f62b0 3975 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
<> 128:9bcdf88f62b0 3976 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
<> 128:9bcdf88f62b0 3977 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
<> 128:9bcdf88f62b0 3978 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
<> 128:9bcdf88f62b0 3979 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
<> 128:9bcdf88f62b0 3980 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
<> 128:9bcdf88f62b0 3981 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
<> 128:9bcdf88f62b0 3982
<> 128:9bcdf88f62b0 3983 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
<> 128:9bcdf88f62b0 3984 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
<> 128:9bcdf88f62b0 3985 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
<> 128:9bcdf88f62b0 3986 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
<> 128:9bcdf88f62b0 3987 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
<> 128:9bcdf88f62b0 3988 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
<> 128:9bcdf88f62b0 3989
<> 128:9bcdf88f62b0 3990 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
<> 128:9bcdf88f62b0 3991 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
<> 128:9bcdf88f62b0 3992 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
<> 128:9bcdf88f62b0 3993 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
<> 128:9bcdf88f62b0 3994 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
<> 128:9bcdf88f62b0 3995 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
<> 128:9bcdf88f62b0 3996 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
<> 128:9bcdf88f62b0 3997 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
<> 128:9bcdf88f62b0 3998
<> 128:9bcdf88f62b0 3999 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
<> 128:9bcdf88f62b0 4000 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 4001 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 4002 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 128:9bcdf88f62b0 4003 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 4004 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 4005 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 4006 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 128:9bcdf88f62b0 4007 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 4008
<> 128:9bcdf88f62b0 4009 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
<> 128:9bcdf88f62b0 4010 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
<> 128:9bcdf88f62b0 4011
<> 128:9bcdf88f62b0 4012 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
<> 128:9bcdf88f62b0 4013 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4014 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4015 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4016 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4017 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4018 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4019 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4020 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
<> 128:9bcdf88f62b0 4021
<> 128:9bcdf88f62b0 4022 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
<> 128:9bcdf88f62b0 4023 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4024 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4025 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4026 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4027 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4028 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4029 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4030 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
<> 128:9bcdf88f62b0 4031
<> 128:9bcdf88f62b0 4032 /******************** Bit definition forUSB_OTG_HAINT register ********************/
<> 128:9bcdf88f62b0 4033 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
<> 128:9bcdf88f62b0 4034
<> 128:9bcdf88f62b0 4035 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
<> 128:9bcdf88f62b0 4036 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 4037 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 4038 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
<> 128:9bcdf88f62b0 4039 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
<> 128:9bcdf88f62b0 4040 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
<> 128:9bcdf88f62b0 4041 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
<> 128:9bcdf88f62b0 4042 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 4043
<> 128:9bcdf88f62b0 4044 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
<> 128:9bcdf88f62b0 4045 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
<> 128:9bcdf88f62b0 4046 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
<> 128:9bcdf88f62b0 4047 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
<> 128:9bcdf88f62b0 4048 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
<> 128:9bcdf88f62b0 4049 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
<> 128:9bcdf88f62b0 4050 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
<> 128:9bcdf88f62b0 4051 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
<> 128:9bcdf88f62b0 4052 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
<> 128:9bcdf88f62b0 4053 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
<> 128:9bcdf88f62b0 4054 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
<> 128:9bcdf88f62b0 4055 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
<> 128:9bcdf88f62b0 4056 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
<> 128:9bcdf88f62b0 4057 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
<> 128:9bcdf88f62b0 4058 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
<> 128:9bcdf88f62b0 4059 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
<> 128:9bcdf88f62b0 4060 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
<> 128:9bcdf88f62b0 4061 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
<> 128:9bcdf88f62b0 4062 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
<> 128:9bcdf88f62b0 4063 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
<> 128:9bcdf88f62b0 4064 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
<> 128:9bcdf88f62b0 4065 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
<> 128:9bcdf88f62b0 4066 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
<> 128:9bcdf88f62b0 4067 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
<> 128:9bcdf88f62b0 4068 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
<> 128:9bcdf88f62b0 4069 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
<> 128:9bcdf88f62b0 4070 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
<> 128:9bcdf88f62b0 4071
<> 128:9bcdf88f62b0 4072 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
<> 128:9bcdf88f62b0 4073 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
<> 128:9bcdf88f62b0 4074 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
<> 128:9bcdf88f62b0 4075 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
<> 128:9bcdf88f62b0 4076 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
<> 128:9bcdf88f62b0 4077 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
<> 128:9bcdf88f62b0 4078 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
<> 128:9bcdf88f62b0 4079 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
<> 128:9bcdf88f62b0 4080 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
<> 128:9bcdf88f62b0 4081 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
<> 128:9bcdf88f62b0 4082 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
<> 128:9bcdf88f62b0 4083 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
<> 128:9bcdf88f62b0 4084 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
<> 128:9bcdf88f62b0 4085 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
<> 128:9bcdf88f62b0 4086 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
<> 128:9bcdf88f62b0 4087 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
<> 128:9bcdf88f62b0 4088 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
<> 128:9bcdf88f62b0 4089 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
<> 128:9bcdf88f62b0 4090 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
<> 128:9bcdf88f62b0 4091 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
<> 128:9bcdf88f62b0 4092 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
<> 128:9bcdf88f62b0 4093 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
<> 128:9bcdf88f62b0 4094 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
<> 128:9bcdf88f62b0 4095 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
<> 128:9bcdf88f62b0 4096 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
<> 128:9bcdf88f62b0 4097 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
<> 128:9bcdf88f62b0 4098 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
<> 128:9bcdf88f62b0 4099
<> 128:9bcdf88f62b0 4100 /******************** Bit definition forUSB_OTG_DAINT register ********************/
<> 128:9bcdf88f62b0 4101 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
<> 128:9bcdf88f62b0 4102 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
<> 128:9bcdf88f62b0 4103
<> 128:9bcdf88f62b0 4104 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
<> 128:9bcdf88f62b0 4105 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
<> 128:9bcdf88f62b0 4106
<> 128:9bcdf88f62b0 4107 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 128:9bcdf88f62b0 4108 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
<> 128:9bcdf88f62b0 4109 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 4110 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 4111 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 4112
<> 128:9bcdf88f62b0 4113 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
<> 128:9bcdf88f62b0 4114 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
<> 128:9bcdf88f62b0 4115 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 4116
<> 128:9bcdf88f62b0 4117 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 4118
<> 128:9bcdf88f62b0 4119 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 128:9bcdf88f62b0 4120 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4121 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4122 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4123 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4124 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 128:9bcdf88f62b0 4125
<> 128:9bcdf88f62b0 4126 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 128:9bcdf88f62b0 4127 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4128 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4129
<> 128:9bcdf88f62b0 4130 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 128:9bcdf88f62b0 4131 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4132 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4133 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4134 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4135
<> 128:9bcdf88f62b0 4136 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 128:9bcdf88f62b0 4137 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4138 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4139 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4140 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4141
<> 128:9bcdf88f62b0 4142 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 128:9bcdf88f62b0 4143 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4144 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4145 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4146 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4147
<> 128:9bcdf88f62b0 4148 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 4149
<> 128:9bcdf88f62b0 4150 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 128:9bcdf88f62b0 4151 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4152 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4153 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4154 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4155 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 128:9bcdf88f62b0 4156
<> 128:9bcdf88f62b0 4157 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 128:9bcdf88f62b0 4158 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4159 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4160
<> 128:9bcdf88f62b0 4161 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 128:9bcdf88f62b0 4162 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4163 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4164 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4165 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4166
<> 128:9bcdf88f62b0 4167 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 128:9bcdf88f62b0 4168 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4169 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4170 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4171 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4172
<> 128:9bcdf88f62b0 4173 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 128:9bcdf88f62b0 4174 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4175 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4176 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4177 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4178
<> 128:9bcdf88f62b0 4179 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
<> 128:9bcdf88f62b0 4180 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
<> 128:9bcdf88f62b0 4181
<> 128:9bcdf88f62b0 4182 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
<> 128:9bcdf88f62b0 4183 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
<> 128:9bcdf88f62b0 4184
<> 128:9bcdf88f62b0 4185 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 4186 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
<> 128:9bcdf88f62b0 4187 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
<> 128:9bcdf88f62b0 4188 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
<> 128:9bcdf88f62b0 4189 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
<> 128:9bcdf88f62b0 4190
<> 128:9bcdf88f62b0 4191 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
<> 128:9bcdf88f62b0 4192 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
<> 128:9bcdf88f62b0 4193
<> 128:9bcdf88f62b0 4194 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
<> 128:9bcdf88f62b0 4195 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
<> 128:9bcdf88f62b0 4196
<> 128:9bcdf88f62b0 4197 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
<> 128:9bcdf88f62b0 4198 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4199 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4200 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4201 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4202 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4203 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4204 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4205 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
<> 128:9bcdf88f62b0 4206
<> 128:9bcdf88f62b0 4207 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
<> 128:9bcdf88f62b0 4208 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4209 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4210 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4211 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4212 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4213 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4214 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4215
<> 128:9bcdf88f62b0 4216 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
<> 128:9bcdf88f62b0 4217 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
<> 128:9bcdf88f62b0 4218 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
<> 128:9bcdf88f62b0 4219
<> 128:9bcdf88f62b0 4220 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
<> 128:9bcdf88f62b0 4221 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4222 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4223 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4224 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4225 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4226 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4227 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4228 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
<> 128:9bcdf88f62b0 4229 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
<> 128:9bcdf88f62b0 4230 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
<> 128:9bcdf88f62b0 4231
<> 128:9bcdf88f62b0 4232 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
<> 128:9bcdf88f62b0 4233 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4234 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4235 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4236 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4237 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4238 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4239 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4240 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
<> 128:9bcdf88f62b0 4241 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
<> 128:9bcdf88f62b0 4242 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
<> 128:9bcdf88f62b0 4243
<> 128:9bcdf88f62b0 4244 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
<> 128:9bcdf88f62b0 4245 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 128:9bcdf88f62b0 4246
<> 128:9bcdf88f62b0 4247 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
<> 128:9bcdf88f62b0 4248 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
<> 128:9bcdf88f62b0 4249 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
<> 128:9bcdf88f62b0 4250
<> 128:9bcdf88f62b0 4251 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
<> 128:9bcdf88f62b0 4252 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
<> 128:9bcdf88f62b0 4253 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
<> 128:9bcdf88f62b0 4254 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
<> 128:9bcdf88f62b0 4255 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
<> 128:9bcdf88f62b0 4256 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
<> 128:9bcdf88f62b0 4257 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
<> 128:9bcdf88f62b0 4258
<> 128:9bcdf88f62b0 4259 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
<> 128:9bcdf88f62b0 4260 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
<> 128:9bcdf88f62b0 4261 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
<> 128:9bcdf88f62b0 4262
<> 128:9bcdf88f62b0 4263 /******************** Bit definition forUSB_OTG_CID register ********************/
<> 128:9bcdf88f62b0 4264 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
<> 128:9bcdf88f62b0 4265
<> 128:9bcdf88f62b0 4266 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
<> 128:9bcdf88f62b0 4267 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 4268 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 4269 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 128:9bcdf88f62b0 4270 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 4271 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 4272 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 4273 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 128:9bcdf88f62b0 4274 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 4275 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 128:9bcdf88f62b0 4276
<> 128:9bcdf88f62b0 4277 /******************** Bit definition forUSB_OTG_HPRT register ********************/
<> 128:9bcdf88f62b0 4278 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
<> 128:9bcdf88f62b0 4279 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
<> 128:9bcdf88f62b0 4280 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
<> 128:9bcdf88f62b0 4281 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
<> 128:9bcdf88f62b0 4282 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
<> 128:9bcdf88f62b0 4283 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
<> 128:9bcdf88f62b0 4284 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
<> 128:9bcdf88f62b0 4285 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
<> 128:9bcdf88f62b0 4286 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
<> 128:9bcdf88f62b0 4287
<> 128:9bcdf88f62b0 4288 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
<> 128:9bcdf88f62b0 4289 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4290 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4291 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
<> 128:9bcdf88f62b0 4292
<> 128:9bcdf88f62b0 4293 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
<> 128:9bcdf88f62b0 4294 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4295 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4296 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4297 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4298
<> 128:9bcdf88f62b0 4299 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
<> 128:9bcdf88f62b0 4300 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4301 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4302
<> 128:9bcdf88f62b0 4303 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
<> 128:9bcdf88f62b0 4304 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 4305 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 4306 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
<> 128:9bcdf88f62b0 4307 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 4308 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 4309 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 4310 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
<> 128:9bcdf88f62b0 4311 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 4312 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
<> 128:9bcdf88f62b0 4313 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 128:9bcdf88f62b0 4314 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
<> 128:9bcdf88f62b0 4315
<> 128:9bcdf88f62b0 4316 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
<> 128:9bcdf88f62b0 4317 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
<> 128:9bcdf88f62b0 4318 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
<> 128:9bcdf88f62b0 4319
<> 128:9bcdf88f62b0 4320 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
<> 128:9bcdf88f62b0 4321 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 128:9bcdf88f62b0 4322 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 128:9bcdf88f62b0 4323 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
<> 128:9bcdf88f62b0 4324 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 128:9bcdf88f62b0 4325
<> 128:9bcdf88f62b0 4326 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 128:9bcdf88f62b0 4327 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4328 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4329 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 128:9bcdf88f62b0 4330
<> 128:9bcdf88f62b0 4331 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
<> 128:9bcdf88f62b0 4332 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4333 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4334 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4335 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4336 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 128:9bcdf88f62b0 4337 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 128:9bcdf88f62b0 4338 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 128:9bcdf88f62b0 4339 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 128:9bcdf88f62b0 4340 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 128:9bcdf88f62b0 4341 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 128:9bcdf88f62b0 4342
<> 128:9bcdf88f62b0 4343 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
<> 128:9bcdf88f62b0 4344 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 128:9bcdf88f62b0 4345
<> 128:9bcdf88f62b0 4346 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
<> 128:9bcdf88f62b0 4347 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4348 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4349 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4350 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4351 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
<> 128:9bcdf88f62b0 4352 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
<> 128:9bcdf88f62b0 4353
<> 128:9bcdf88f62b0 4354 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
<> 128:9bcdf88f62b0 4355 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4356 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4357
<> 128:9bcdf88f62b0 4358 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
<> 128:9bcdf88f62b0 4359 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4360 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4361
<> 128:9bcdf88f62b0 4362 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
<> 128:9bcdf88f62b0 4363 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4364 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4365 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4366 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4367 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4368 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4369 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4370 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
<> 128:9bcdf88f62b0 4371 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
<> 128:9bcdf88f62b0 4372 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
<> 128:9bcdf88f62b0 4373
<> 128:9bcdf88f62b0 4374 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
<> 128:9bcdf88f62b0 4375
<> 128:9bcdf88f62b0 4376 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
<> 128:9bcdf88f62b0 4377 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4378 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4379 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4380 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4381 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4382 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4383 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4384
<> 128:9bcdf88f62b0 4385 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
<> 128:9bcdf88f62b0 4386 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4387 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4388 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
<> 128:9bcdf88f62b0 4389 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
<> 128:9bcdf88f62b0 4390 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
<> 128:9bcdf88f62b0 4391 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
<> 128:9bcdf88f62b0 4392 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
<> 128:9bcdf88f62b0 4393
<> 128:9bcdf88f62b0 4394 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
<> 128:9bcdf88f62b0 4395 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4396 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4397 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
<> 128:9bcdf88f62b0 4398 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
<> 128:9bcdf88f62b0 4399
<> 128:9bcdf88f62b0 4400 /******************** Bit definition forUSB_OTG_HCINT register ********************/
<> 128:9bcdf88f62b0 4401 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
<> 128:9bcdf88f62b0 4402 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
<> 128:9bcdf88f62b0 4403 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
<> 128:9bcdf88f62b0 4404 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
<> 128:9bcdf88f62b0 4405 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
<> 128:9bcdf88f62b0 4406 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
<> 128:9bcdf88f62b0 4407 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
<> 128:9bcdf88f62b0 4408 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
<> 128:9bcdf88f62b0 4409 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
<> 128:9bcdf88f62b0 4410 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
<> 128:9bcdf88f62b0 4411 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
<> 128:9bcdf88f62b0 4412
<> 128:9bcdf88f62b0 4413 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
<> 128:9bcdf88f62b0 4414 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 128:9bcdf88f62b0 4415 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 128:9bcdf88f62b0 4416 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
<> 128:9bcdf88f62b0 4417 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
<> 128:9bcdf88f62b0 4418 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
<> 128:9bcdf88f62b0 4419 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
<> 128:9bcdf88f62b0 4420 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
<> 128:9bcdf88f62b0 4421 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
<> 128:9bcdf88f62b0 4422 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
<> 128:9bcdf88f62b0 4423 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
<> 128:9bcdf88f62b0 4424 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
<> 128:9bcdf88f62b0 4425
<> 128:9bcdf88f62b0 4426 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
<> 128:9bcdf88f62b0 4427 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
<> 128:9bcdf88f62b0 4428 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
<> 128:9bcdf88f62b0 4429 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
<> 128:9bcdf88f62b0 4430 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
<> 128:9bcdf88f62b0 4431 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
<> 128:9bcdf88f62b0 4432 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
<> 128:9bcdf88f62b0 4433 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
<> 128:9bcdf88f62b0 4434 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
<> 128:9bcdf88f62b0 4435 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
<> 128:9bcdf88f62b0 4436 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
<> 128:9bcdf88f62b0 4437 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
<> 128:9bcdf88f62b0 4438
<> 128:9bcdf88f62b0 4439 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 128:9bcdf88f62b0 4440
<> 128:9bcdf88f62b0 4441 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 128:9bcdf88f62b0 4442 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 128:9bcdf88f62b0 4443 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
<> 128:9bcdf88f62b0 4444 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
<> 128:9bcdf88f62b0 4445 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 128:9bcdf88f62b0 4446 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 128:9bcdf88f62b0 4447 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
<> 128:9bcdf88f62b0 4448 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
<> 128:9bcdf88f62b0 4449 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4450 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4451
<> 128:9bcdf88f62b0 4452 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
<> 128:9bcdf88f62b0 4453 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 128:9bcdf88f62b0 4454
<> 128:9bcdf88f62b0 4455 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
<> 128:9bcdf88f62b0 4456 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 128:9bcdf88f62b0 4457
<> 128:9bcdf88f62b0 4458 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
<> 128:9bcdf88f62b0 4459 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
<> 128:9bcdf88f62b0 4460
<> 128:9bcdf88f62b0 4461 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
<> 128:9bcdf88f62b0 4462 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
<> 128:9bcdf88f62b0 4463 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
<> 128:9bcdf88f62b0 4464
<> 128:9bcdf88f62b0 4465 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
<> 128:9bcdf88f62b0 4466
<> 128:9bcdf88f62b0 4467 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
<> 128:9bcdf88f62b0 4468 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 128:9bcdf88f62b0 4469 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 128:9bcdf88f62b0 4470 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 128:9bcdf88f62b0 4471 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 128:9bcdf88f62b0 4472 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 128:9bcdf88f62b0 4473 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4474 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4475 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
<> 128:9bcdf88f62b0 4476 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 128:9bcdf88f62b0 4477 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 128:9bcdf88f62b0 4478 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 128:9bcdf88f62b0 4479 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 128:9bcdf88f62b0 4480 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 128:9bcdf88f62b0 4481
<> 128:9bcdf88f62b0 4482 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
<> 128:9bcdf88f62b0 4483 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 128:9bcdf88f62b0 4484 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 128:9bcdf88f62b0 4485 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
<> 128:9bcdf88f62b0 4486 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
<> 128:9bcdf88f62b0 4487 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
<> 128:9bcdf88f62b0 4488 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
<> 128:9bcdf88f62b0 4489
<> 128:9bcdf88f62b0 4490 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
<> 128:9bcdf88f62b0 4491
<> 128:9bcdf88f62b0 4492 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 128:9bcdf88f62b0 4493 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 128:9bcdf88f62b0 4494
<> 128:9bcdf88f62b0 4495 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
<> 128:9bcdf88f62b0 4496 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4497 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4498
<> 128:9bcdf88f62b0 4499 /******************** Bit definition for PCGCCTL register ********************/
<> 128:9bcdf88f62b0 4500 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
<> 128:9bcdf88f62b0 4501 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
<> 128:9bcdf88f62b0 4502 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
<> 128:9bcdf88f62b0 4503
<> 128:9bcdf88f62b0 4504 /**
<> 128:9bcdf88f62b0 4505 * @}
<> 128:9bcdf88f62b0 4506 */
<> 128:9bcdf88f62b0 4507
<> 128:9bcdf88f62b0 4508 /**
<> 128:9bcdf88f62b0 4509 * @}
<> 128:9bcdf88f62b0 4510 */
<> 128:9bcdf88f62b0 4511
<> 128:9bcdf88f62b0 4512 /** @addtogroup Exported_macros
<> 128:9bcdf88f62b0 4513 * @{
<> 128:9bcdf88f62b0 4514 */
<> 128:9bcdf88f62b0 4515
<> 128:9bcdf88f62b0 4516 /******************************* ADC Instances ********************************/
<> 128:9bcdf88f62b0 4517 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 128:9bcdf88f62b0 4518
<> 128:9bcdf88f62b0 4519 /******************************* CRC Instances ********************************/
<> 128:9bcdf88f62b0 4520 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 128:9bcdf88f62b0 4521
<> 128:9bcdf88f62b0 4522 /******************************** DMA Instances *******************************/
<> 128:9bcdf88f62b0 4523 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
<> 128:9bcdf88f62b0 4524 ((INSTANCE) == DMA1_Stream1) || \
<> 128:9bcdf88f62b0 4525 ((INSTANCE) == DMA1_Stream2) || \
<> 128:9bcdf88f62b0 4526 ((INSTANCE) == DMA1_Stream3) || \
<> 128:9bcdf88f62b0 4527 ((INSTANCE) == DMA1_Stream4) || \
<> 128:9bcdf88f62b0 4528 ((INSTANCE) == DMA1_Stream5) || \
<> 128:9bcdf88f62b0 4529 ((INSTANCE) == DMA1_Stream6) || \
<> 128:9bcdf88f62b0 4530 ((INSTANCE) == DMA1_Stream7) || \
<> 128:9bcdf88f62b0 4531 ((INSTANCE) == DMA2_Stream0) || \
<> 128:9bcdf88f62b0 4532 ((INSTANCE) == DMA2_Stream1) || \
<> 128:9bcdf88f62b0 4533 ((INSTANCE) == DMA2_Stream2) || \
<> 128:9bcdf88f62b0 4534 ((INSTANCE) == DMA2_Stream3) || \
<> 128:9bcdf88f62b0 4535 ((INSTANCE) == DMA2_Stream4) || \
<> 128:9bcdf88f62b0 4536 ((INSTANCE) == DMA2_Stream5) || \
<> 128:9bcdf88f62b0 4537 ((INSTANCE) == DMA2_Stream6) || \
<> 128:9bcdf88f62b0 4538 ((INSTANCE) == DMA2_Stream7))
<> 128:9bcdf88f62b0 4539
<> 128:9bcdf88f62b0 4540 /******************************* GPIO Instances *******************************/
<> 128:9bcdf88f62b0 4541 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 128:9bcdf88f62b0 4542 ((INSTANCE) == GPIOB) || \
<> 128:9bcdf88f62b0 4543 ((INSTANCE) == GPIOC) || \
<> 128:9bcdf88f62b0 4544 ((INSTANCE) == GPIOD) || \
<> 128:9bcdf88f62b0 4545 ((INSTANCE) == GPIOE) || \
<> 128:9bcdf88f62b0 4546 ((INSTANCE) == GPIOH))
<> 128:9bcdf88f62b0 4547
<> 128:9bcdf88f62b0 4548 /******************************** I2C Instances *******************************/
<> 128:9bcdf88f62b0 4549 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 128:9bcdf88f62b0 4550 ((INSTANCE) == I2C2) || \
<> 128:9bcdf88f62b0 4551 ((INSTANCE) == I2C3))
<> 128:9bcdf88f62b0 4552
<> 128:9bcdf88f62b0 4553 /******************************** I2S Instances *******************************/
<> 128:9bcdf88f62b0 4554 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 4555 ((INSTANCE) == SPI3))
<> 128:9bcdf88f62b0 4556
<> 128:9bcdf88f62b0 4557 /*************************** I2S Extended Instances ***************************/
<> 128:9bcdf88f62b0 4558 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 4559 ((INSTANCE) == SPI3) || \
<> 128:9bcdf88f62b0 4560 ((INSTANCE) == I2S2ext) || \
<> 128:9bcdf88f62b0 4561 ((INSTANCE) == I2S3ext))
<> 128:9bcdf88f62b0 4562
<> 128:9bcdf88f62b0 4563 /****************************** RTC Instances *********************************/
<> 128:9bcdf88f62b0 4564 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 128:9bcdf88f62b0 4565
<> 128:9bcdf88f62b0 4566 /******************************** SPI Instances *******************************/
<> 128:9bcdf88f62b0 4567 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 128:9bcdf88f62b0 4568 ((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 4569 ((INSTANCE) == SPI3) || \
<> 128:9bcdf88f62b0 4570 ((INSTANCE) == SPI4))
<> 128:9bcdf88f62b0 4571
<> 128:9bcdf88f62b0 4572 /*************************** SPI Extended Instances ***************************/
<> 128:9bcdf88f62b0 4573 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
<> 128:9bcdf88f62b0 4574 ((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 4575 ((INSTANCE) == SPI3) || \
<> 128:9bcdf88f62b0 4576 ((INSTANCE) == I2S2ext) || \
<> 128:9bcdf88f62b0 4577 ((INSTANCE) == I2S3ext))
<> 128:9bcdf88f62b0 4578
<> 128:9bcdf88f62b0 4579 /****************** TIM Instances : All supported instances *******************/
<> 128:9bcdf88f62b0 4580 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4581 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4582 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4583 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4584 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4585 ((INSTANCE) == TIM9) || \
<> 128:9bcdf88f62b0 4586 ((INSTANCE) == TIM10) || \
<> 128:9bcdf88f62b0 4587 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 4588
<> 128:9bcdf88f62b0 4589 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 128:9bcdf88f62b0 4590 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4591 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4592 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4593 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4594 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4595 ((INSTANCE) == TIM9) || \
<> 128:9bcdf88f62b0 4596 ((INSTANCE) == TIM10) || \
<> 128:9bcdf88f62b0 4597 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 4598
<> 128:9bcdf88f62b0 4599 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 128:9bcdf88f62b0 4600 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4601 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4602 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4603 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4604 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4605 ((INSTANCE) == TIM9))
<> 128:9bcdf88f62b0 4606
<> 128:9bcdf88f62b0 4607 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 128:9bcdf88f62b0 4608 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4609 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4610 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4611 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4612 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4613
<> 128:9bcdf88f62b0 4614 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 128:9bcdf88f62b0 4615 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4616 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4617 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4618 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4619 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4620
<> 128:9bcdf88f62b0 4621 /******************** TIM Instances : Advanced-control timers *****************/
<> 128:9bcdf88f62b0 4622 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
<> 128:9bcdf88f62b0 4623
<> 128:9bcdf88f62b0 4624 /******************* TIM Instances : Timer input XOR function *****************/
<> 128:9bcdf88f62b0 4625 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4626 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4627 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4628 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4629 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4630
<> 128:9bcdf88f62b0 4631 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 128:9bcdf88f62b0 4632 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4633 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4634 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4635 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4636 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4637
<> 128:9bcdf88f62b0 4638 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 128:9bcdf88f62b0 4639 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4640 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4641 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4642 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4643 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4644
<> 128:9bcdf88f62b0 4645 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 128:9bcdf88f62b0 4646 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4647 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4648 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4649 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4650 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4651
<> 128:9bcdf88f62b0 4652 /******************** TIM Instances : DMA burst feature ***********************/
<> 128:9bcdf88f62b0 4653 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4654 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4655 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4656 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4657 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4658
<> 128:9bcdf88f62b0 4659 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 128:9bcdf88f62b0 4660 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4661 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4662 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4663 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4664 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4665 ((INSTANCE) == TIM9))
<> 128:9bcdf88f62b0 4666
<> 128:9bcdf88f62b0 4667 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 128:9bcdf88f62b0 4668 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4669 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4670 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4671 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4672 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4673 ((INSTANCE) == TIM9))
<> 128:9bcdf88f62b0 4674
<> 128:9bcdf88f62b0 4675 /********************** TIM Instances : 32 bit Counter ************************/
<> 128:9bcdf88f62b0 4676 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4677 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4678
<> 128:9bcdf88f62b0 4679 /***************** TIM Instances : external trigger input availabe ************/
<> 128:9bcdf88f62b0 4680 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 4681 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4682 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 4683 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 4684 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 4685
<> 128:9bcdf88f62b0 4686 /****************** TIM Instances : remapping capability **********************/
<> 128:9bcdf88f62b0 4687 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 4688 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 4689 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 4690
<> 128:9bcdf88f62b0 4691 /******************* TIM Instances : output(s) available **********************/
<> 128:9bcdf88f62b0 4692 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 4693 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 4694 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4695 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4696 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 4697 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 4698 || \
<> 128:9bcdf88f62b0 4699 (((INSTANCE) == TIM2) && \
<> 128:9bcdf88f62b0 4700 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4701 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4702 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 4703 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 4704 || \
<> 128:9bcdf88f62b0 4705 (((INSTANCE) == TIM3) && \
<> 128:9bcdf88f62b0 4706 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4707 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4708 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 4709 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 4710 || \
<> 128:9bcdf88f62b0 4711 (((INSTANCE) == TIM4) && \
<> 128:9bcdf88f62b0 4712 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4713 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4714 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 4715 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 4716 || \
<> 128:9bcdf88f62b0 4717 (((INSTANCE) == TIM5) && \
<> 128:9bcdf88f62b0 4718 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4719 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4720 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 4721 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 4722 || \
<> 128:9bcdf88f62b0 4723 (((INSTANCE) == TIM9) && \
<> 128:9bcdf88f62b0 4724 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4725 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 128:9bcdf88f62b0 4726 || \
<> 128:9bcdf88f62b0 4727 (((INSTANCE) == TIM10) && \
<> 128:9bcdf88f62b0 4728 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 128:9bcdf88f62b0 4729 || \
<> 128:9bcdf88f62b0 4730 (((INSTANCE) == TIM11) && \
<> 128:9bcdf88f62b0 4731 (((CHANNEL) == TIM_CHANNEL_1))))
<> 128:9bcdf88f62b0 4732
<> 128:9bcdf88f62b0 4733 /************ TIM Instances : complementary output(s) available ***************/
<> 128:9bcdf88f62b0 4734 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 4735 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 4736 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 4737 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 4738 ((CHANNEL) == TIM_CHANNEL_3))))
<> 128:9bcdf88f62b0 4739
<> 128:9bcdf88f62b0 4740 /******************** USART Instances : Synchronous mode **********************/
<> 128:9bcdf88f62b0 4741 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 4742 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 4743 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 4744
<> 128:9bcdf88f62b0 4745 /******************** UART Instances : Asynchronous mode **********************/
<> 128:9bcdf88f62b0 4746 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 4747 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 4748 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 4749
<> 128:9bcdf88f62b0 4750 /****************** UART Instances : Hardware Flow control ********************/
<> 128:9bcdf88f62b0 4751 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 4752 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 4753 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 4754
<> 128:9bcdf88f62b0 4755 /********************* UART Instances : Smard card mode ***********************/
<> 128:9bcdf88f62b0 4756 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 4757 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 4758 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 4759
<> 128:9bcdf88f62b0 4760 /*********************** UART Instances : IRDA mode ***************************/
<> 128:9bcdf88f62b0 4761 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 4762 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 4763 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 4764
<> 128:9bcdf88f62b0 4765
<> 128:9bcdf88f62b0 4766 /*********************** PCD Instances ****************************************/
<> 128:9bcdf88f62b0 4767 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 128:9bcdf88f62b0 4768
<> 128:9bcdf88f62b0 4769 /*********************** HCD Instances ****************************************/
<> 128:9bcdf88f62b0 4770 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 128:9bcdf88f62b0 4771
<> 128:9bcdf88f62b0 4772 /****************************** IWDG Instances ********************************/
<> 128:9bcdf88f62b0 4773 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 128:9bcdf88f62b0 4774
<> 128:9bcdf88f62b0 4775 /****************************** WWDG Instances ********************************/
<> 128:9bcdf88f62b0 4776 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 128:9bcdf88f62b0 4777
<> 128:9bcdf88f62b0 4778 /****************************** SDIO Instances ********************************/
<> 128:9bcdf88f62b0 4779 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
<> 128:9bcdf88f62b0 4780
<> 128:9bcdf88f62b0 4781 /****************************** USB Exported Constants ************************/
<> 128:9bcdf88f62b0 4782 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
<> 128:9bcdf88f62b0 4783 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
<> 128:9bcdf88f62b0 4784 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
<> 128:9bcdf88f62b0 4785 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
<> 128:9bcdf88f62b0 4786
<> 128:9bcdf88f62b0 4787 /**
<> 128:9bcdf88f62b0 4788 * @}
<> 128:9bcdf88f62b0 4789 */
<> 128:9bcdf88f62b0 4790
<> 128:9bcdf88f62b0 4791 /**
<> 128:9bcdf88f62b0 4792 * @}
<> 128:9bcdf88f62b0 4793 */
<> 128:9bcdf88f62b0 4794
<> 128:9bcdf88f62b0 4795 /**
<> 128:9bcdf88f62b0 4796 * @}
<> 128:9bcdf88f62b0 4797 */
<> 128:9bcdf88f62b0 4798
<> 128:9bcdf88f62b0 4799 #ifdef __cplusplus
<> 128:9bcdf88f62b0 4800 }
<> 128:9bcdf88f62b0 4801 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 4802
<> 128:9bcdf88f62b0 4803 #endif /* __STM32F401xE_H */
<> 128:9bcdf88f62b0 4804
<> 128:9bcdf88f62b0 4805
<> 128:9bcdf88f62b0 4806
<> 128:9bcdf88f62b0 4807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/