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TARGET_NUCLEO_F401RE/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
136:ef9c61f8c49f 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32f401xe.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V2.6.1
AnnaBridge 145:64910690c574 6 * @date 14-February-2017
AnnaBridge 145:64910690c574 7 * @brief CMSIS STM32F401xE Device Peripheral Access Layer Header File.
<> 128:9bcdf88f62b0 8 *
<> 128:9bcdf88f62b0 9 * This file contains:
<> 128:9bcdf88f62b0 10 * - Data structures and the address mapping for all peripherals
<> 128:9bcdf88f62b0 11 * - peripherals registers declarations and bits definition
<> 128:9bcdf88f62b0 12 * - Macros to access peripheral's registers hardware
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 ******************************************************************************
<> 128:9bcdf88f62b0 15 * @attention
<> 128:9bcdf88f62b0 16 *
AnnaBridge 145:64910690c574 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 18 *
<> 128:9bcdf88f62b0 19 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 20 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 22 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 24 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 25 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 27 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 28 * without specific prior written permission.
<> 128:9bcdf88f62b0 29 *
<> 128:9bcdf88f62b0 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 40 *
<> 128:9bcdf88f62b0 41 ******************************************************************************
<> 128:9bcdf88f62b0 42 */
<> 128:9bcdf88f62b0 43
AnnaBridge 145:64910690c574 44 /** @addtogroup CMSIS_Device
<> 128:9bcdf88f62b0 45 * @{
<> 128:9bcdf88f62b0 46 */
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /** @addtogroup stm32f401xe
<> 128:9bcdf88f62b0 49 * @{
<> 128:9bcdf88f62b0 50 */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #ifndef __STM32F401xE_H
<> 128:9bcdf88f62b0 53 #define __STM32F401xE_H
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 #ifdef __cplusplus
<> 128:9bcdf88f62b0 56 extern "C" {
<> 128:9bcdf88f62b0 57 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /** @addtogroup Configuration_section_for_CMSIS
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /**
<> 128:9bcdf88f62b0 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 128:9bcdf88f62b0 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
<> 128:9bcdf88f62b0 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
<> 128:9bcdf88f62b0 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 128:9bcdf88f62b0 70 #ifndef __FPU_PRESENT
<> 128:9bcdf88f62b0 71 #define __FPU_PRESENT 1U /*!< FPU present */
<> 128:9bcdf88f62b0 72 #endif /* __FPU_PRESENT */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 /**
<> 128:9bcdf88f62b0 75 * @}
<> 128:9bcdf88f62b0 76 */
AnnaBridge 145:64910690c574 77
<> 128:9bcdf88f62b0 78 /** @addtogroup Peripheral_interrupt_number_definition
<> 128:9bcdf88f62b0 79 * @{
<> 128:9bcdf88f62b0 80 */
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 /**
<> 128:9bcdf88f62b0 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
<> 128:9bcdf88f62b0 84 * in @ref Library_configuration_section
<> 128:9bcdf88f62b0 85 */
<> 128:9bcdf88f62b0 86 typedef enum
<> 128:9bcdf88f62b0 87 {
<> 128:9bcdf88f62b0 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 128:9bcdf88f62b0 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 128:9bcdf88f62b0 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 128:9bcdf88f62b0 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 128:9bcdf88f62b0 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 128:9bcdf88f62b0 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 128:9bcdf88f62b0 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 128:9bcdf88f62b0 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 128:9bcdf88f62b0 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 128:9bcdf88f62b0 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 128:9bcdf88f62b0 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 128:9bcdf88f62b0 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 128:9bcdf88f62b0 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 128:9bcdf88f62b0 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 128:9bcdf88f62b0 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 128:9bcdf88f62b0 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 128:9bcdf88f62b0 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 128:9bcdf88f62b0 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 128:9bcdf88f62b0 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 128:9bcdf88f62b0 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 128:9bcdf88f62b0 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 128:9bcdf88f62b0 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 128:9bcdf88f62b0 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 128:9bcdf88f62b0 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 128:9bcdf88f62b0 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 128:9bcdf88f62b0 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 128:9bcdf88f62b0 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 128:9bcdf88f62b0 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 128:9bcdf88f62b0 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 128:9bcdf88f62b0 117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 128:9bcdf88f62b0 118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 128:9bcdf88f62b0 119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 128:9bcdf88f62b0 120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 128:9bcdf88f62b0 121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 128:9bcdf88f62b0 122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 128:9bcdf88f62b0 123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 128:9bcdf88f62b0 124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 128:9bcdf88f62b0 125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 128:9bcdf88f62b0 126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 128:9bcdf88f62b0 127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 145:64910690c574 128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 128:9bcdf88f62b0 129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 128:9bcdf88f62b0 130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 128:9bcdf88f62b0 131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 128:9bcdf88f62b0 132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 128:9bcdf88f62b0 133 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 128:9bcdf88f62b0 134 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 145:64910690c574 135 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 128:9bcdf88f62b0 136 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 128:9bcdf88f62b0 137 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
<> 128:9bcdf88f62b0 138 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 128:9bcdf88f62b0 139 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 128:9bcdf88f62b0 140 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 128:9bcdf88f62b0 141 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 128:9bcdf88f62b0 142 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 128:9bcdf88f62b0 143 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 128:9bcdf88f62b0 144 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 128:9bcdf88f62b0 145 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 128:9bcdf88f62b0 146 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 128:9bcdf88f62b0 147 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 128:9bcdf88f62b0 148 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 128:9bcdf88f62b0 149 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 128:9bcdf88f62b0 150 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 128:9bcdf88f62b0 151 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 145:64910690c574 152 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 145:64910690c574 153 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
<> 128:9bcdf88f62b0 154 } IRQn_Type;
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /**
<> 128:9bcdf88f62b0 157 * @}
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 128:9bcdf88f62b0 161 #include "system_stm32f4xx.h"
<> 128:9bcdf88f62b0 162 #include <stdint.h>
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** @addtogroup Peripheral_registers_structures
<> 128:9bcdf88f62b0 165 * @{
<> 128:9bcdf88f62b0 166 */
<> 128:9bcdf88f62b0 167
<> 128:9bcdf88f62b0 168 /**
<> 128:9bcdf88f62b0 169 * @brief Analog to Digital Converter
<> 128:9bcdf88f62b0 170 */
<> 128:9bcdf88f62b0 171
<> 128:9bcdf88f62b0 172 typedef struct
<> 128:9bcdf88f62b0 173 {
<> 128:9bcdf88f62b0 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 145:64910690c574 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 128:9bcdf88f62b0 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 128:9bcdf88f62b0 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 128:9bcdf88f62b0 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 128:9bcdf88f62b0 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 128:9bcdf88f62b0 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 128:9bcdf88f62b0 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 128:9bcdf88f62b0 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 128:9bcdf88f62b0 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 128:9bcdf88f62b0 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 128:9bcdf88f62b0 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 128:9bcdf88f62b0 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 128:9bcdf88f62b0 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 128:9bcdf88f62b0 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 194 } ADC_TypeDef;
<> 128:9bcdf88f62b0 195
<> 128:9bcdf88f62b0 196 typedef struct
<> 128:9bcdf88f62b0 197 {
<> 128:9bcdf88f62b0 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 128:9bcdf88f62b0 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 128:9bcdf88f62b0 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 128:9bcdf88f62b0 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 128:9bcdf88f62b0 202 } ADC_Common_TypeDef;
<> 128:9bcdf88f62b0 203
<> 128:9bcdf88f62b0 204 /**
<> 128:9bcdf88f62b0 205 * @brief CRC calculation unit
<> 128:9bcdf88f62b0 206 */
<> 128:9bcdf88f62b0 207
<> 128:9bcdf88f62b0 208 typedef struct
<> 128:9bcdf88f62b0 209 {
<> 128:9bcdf88f62b0 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 128:9bcdf88f62b0 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 128:9bcdf88f62b0 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 215 } CRC_TypeDef;
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 /**
<> 128:9bcdf88f62b0 218 * @brief Debug MCU
<> 128:9bcdf88f62b0 219 */
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 typedef struct
<> 128:9bcdf88f62b0 222 {
<> 128:9bcdf88f62b0 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 128:9bcdf88f62b0 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 227 }DBGMCU_TypeDef;
<> 128:9bcdf88f62b0 228
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 /**
<> 128:9bcdf88f62b0 231 * @brief DMA Controller
<> 128:9bcdf88f62b0 232 */
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 typedef struct
<> 128:9bcdf88f62b0 235 {
<> 128:9bcdf88f62b0 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 128:9bcdf88f62b0 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 128:9bcdf88f62b0 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 128:9bcdf88f62b0 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 128:9bcdf88f62b0 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 128:9bcdf88f62b0 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 128:9bcdf88f62b0 242 } DMA_Stream_TypeDef;
<> 128:9bcdf88f62b0 243
<> 128:9bcdf88f62b0 244 typedef struct
<> 128:9bcdf88f62b0 245 {
<> 128:9bcdf88f62b0 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 250 } DMA_TypeDef;
<> 128:9bcdf88f62b0 251
<> 128:9bcdf88f62b0 252 /**
<> 128:9bcdf88f62b0 253 * @brief External Interrupt/Event Controller
<> 128:9bcdf88f62b0 254 */
<> 128:9bcdf88f62b0 255
<> 128:9bcdf88f62b0 256 typedef struct
<> 128:9bcdf88f62b0 257 {
<> 128:9bcdf88f62b0 258 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 259 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 260 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 261 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 262 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 263 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 264 } EXTI_TypeDef;
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 /**
<> 128:9bcdf88f62b0 267 * @brief FLASH Registers
<> 128:9bcdf88f62b0 268 */
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 typedef struct
<> 128:9bcdf88f62b0 271 {
<> 128:9bcdf88f62b0 272 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 273 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 274 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 275 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 276 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 277 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 128:9bcdf88f62b0 278 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 279 } FLASH_TypeDef;
<> 128:9bcdf88f62b0 280
<> 128:9bcdf88f62b0 281 /**
<> 128:9bcdf88f62b0 282 * @brief General Purpose I/O
<> 128:9bcdf88f62b0 283 */
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 typedef struct
<> 128:9bcdf88f62b0 286 {
<> 128:9bcdf88f62b0 287 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 288 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 289 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 290 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 291 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 292 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 293 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 294 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 295 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 128:9bcdf88f62b0 296 } GPIO_TypeDef;
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 /**
<> 128:9bcdf88f62b0 299 * @brief System configuration controller
<> 128:9bcdf88f62b0 300 */
AnnaBridge 145:64910690c574 301
<> 128:9bcdf88f62b0 302 typedef struct
<> 128:9bcdf88f62b0 303 {
<> 128:9bcdf88f62b0 304 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 305 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 306 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 145:64910690c574 307 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
<> 128:9bcdf88f62b0 308 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 309 } SYSCFG_TypeDef;
<> 128:9bcdf88f62b0 310
<> 128:9bcdf88f62b0 311 /**
<> 128:9bcdf88f62b0 312 * @brief Inter-integrated Circuit Interface
<> 128:9bcdf88f62b0 313 */
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 typedef struct
<> 128:9bcdf88f62b0 316 {
<> 128:9bcdf88f62b0 317 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 318 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 319 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 128:9bcdf88f62b0 320 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 128:9bcdf88f62b0 321 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 322 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 323 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 324 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 325 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 326 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 327 } I2C_TypeDef;
<> 128:9bcdf88f62b0 328
<> 128:9bcdf88f62b0 329 /**
<> 128:9bcdf88f62b0 330 * @brief Independent WATCHDOG
<> 128:9bcdf88f62b0 331 */
<> 128:9bcdf88f62b0 332
<> 128:9bcdf88f62b0 333 typedef struct
<> 128:9bcdf88f62b0 334 {
<> 128:9bcdf88f62b0 335 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 336 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 337 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 338 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 339 } IWDG_TypeDef;
<> 128:9bcdf88f62b0 340
AnnaBridge 145:64910690c574 341
<> 128:9bcdf88f62b0 342 /**
<> 128:9bcdf88f62b0 343 * @brief Power Control
<> 128:9bcdf88f62b0 344 */
<> 128:9bcdf88f62b0 345
<> 128:9bcdf88f62b0 346 typedef struct
<> 128:9bcdf88f62b0 347 {
<> 128:9bcdf88f62b0 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 350 } PWR_TypeDef;
<> 128:9bcdf88f62b0 351
<> 128:9bcdf88f62b0 352 /**
<> 128:9bcdf88f62b0 353 * @brief Reset and Clock Control
<> 128:9bcdf88f62b0 354 */
<> 128:9bcdf88f62b0 355
<> 128:9bcdf88f62b0 356 typedef struct
<> 128:9bcdf88f62b0 357 {
<> 128:9bcdf88f62b0 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 128:9bcdf88f62b0 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 128:9bcdf88f62b0 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 128:9bcdf88f62b0 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 128:9bcdf88f62b0 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 128:9bcdf88f62b0 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 128:9bcdf88f62b0 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 128:9bcdf88f62b0 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 128:9bcdf88f62b0 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 128:9bcdf88f62b0 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 128:9bcdf88f62b0 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 128:9bcdf88f62b0 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 128:9bcdf88f62b0 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 128:9bcdf88f62b0 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 128:9bcdf88f62b0 388 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
AnnaBridge 145:64910690c574 389 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
<> 128:9bcdf88f62b0 390 } RCC_TypeDef;
<> 128:9bcdf88f62b0 391
<> 128:9bcdf88f62b0 392 /**
<> 128:9bcdf88f62b0 393 * @brief Real-Time Clock
<> 128:9bcdf88f62b0 394 */
<> 128:9bcdf88f62b0 395
<> 128:9bcdf88f62b0 396 typedef struct
<> 128:9bcdf88f62b0 397 {
<> 128:9bcdf88f62b0 398 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 399 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 400 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 401 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 402 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 403 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 404 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 405 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 406 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 407 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 408 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 409 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 410 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 411 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 412 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 413 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 414 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 415 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 416 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 417 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 128:9bcdf88f62b0 418 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
<> 128:9bcdf88f62b0 419 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 128:9bcdf88f62b0 420 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 128:9bcdf88f62b0 421 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 128:9bcdf88f62b0 422 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 128:9bcdf88f62b0 423 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 128:9bcdf88f62b0 424 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 128:9bcdf88f62b0 425 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 128:9bcdf88f62b0 426 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 128:9bcdf88f62b0 427 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 128:9bcdf88f62b0 428 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 128:9bcdf88f62b0 429 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 128:9bcdf88f62b0 430 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 128:9bcdf88f62b0 431 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 128:9bcdf88f62b0 432 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 128:9bcdf88f62b0 433 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 128:9bcdf88f62b0 434 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 128:9bcdf88f62b0 435 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 128:9bcdf88f62b0 436 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 128:9bcdf88f62b0 437 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 128:9bcdf88f62b0 438 } RTC_TypeDef;
<> 128:9bcdf88f62b0 439
<> 128:9bcdf88f62b0 440 /**
<> 128:9bcdf88f62b0 441 * @brief SD host Interface
<> 128:9bcdf88f62b0 442 */
<> 128:9bcdf88f62b0 443
<> 128:9bcdf88f62b0 444 typedef struct
<> 128:9bcdf88f62b0 445 {
AnnaBridge 145:64910690c574 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 145:64910690c574 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 145:64910690c574 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 145:64910690c574 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 145:64910690c574 450 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 145:64910690c574 451 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 145:64910690c574 452 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 145:64910690c574 453 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 145:64910690c574 454 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 145:64910690c574 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 145:64910690c574 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 145:64910690c574 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 145:64910690c574 458 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 145:64910690c574 459 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 145:64910690c574 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 145:64910690c574 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 145:64910690c574 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 145:64910690c574 463 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 145:64910690c574 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 145:64910690c574 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 466 } SDIO_TypeDef;
<> 128:9bcdf88f62b0 467
<> 128:9bcdf88f62b0 468 /**
<> 128:9bcdf88f62b0 469 * @brief Serial Peripheral Interface
<> 128:9bcdf88f62b0 470 */
<> 128:9bcdf88f62b0 471
<> 128:9bcdf88f62b0 472 typedef struct
<> 128:9bcdf88f62b0 473 {
<> 128:9bcdf88f62b0 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 128:9bcdf88f62b0 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 128:9bcdf88f62b0 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 128:9bcdf88f62b0 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 128:9bcdf88f62b0 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 483 } SPI_TypeDef;
<> 128:9bcdf88f62b0 484
AnnaBridge 145:64910690c574 485
<> 128:9bcdf88f62b0 486 /**
<> 128:9bcdf88f62b0 487 * @brief TIM
<> 128:9bcdf88f62b0 488 */
<> 128:9bcdf88f62b0 489
<> 128:9bcdf88f62b0 490 typedef struct
<> 128:9bcdf88f62b0 491 {
<> 128:9bcdf88f62b0 492 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 493 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 494 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 495 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 496 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 497 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 498 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 499 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 128:9bcdf88f62b0 500 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 501 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 502 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 128:9bcdf88f62b0 503 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 504 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 505 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 128:9bcdf88f62b0 506 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 128:9bcdf88f62b0 507 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 128:9bcdf88f62b0 508 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 128:9bcdf88f62b0 509 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 510 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 511 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 128:9bcdf88f62b0 512 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 513 } TIM_TypeDef;
<> 128:9bcdf88f62b0 514
<> 128:9bcdf88f62b0 515 /**
<> 128:9bcdf88f62b0 516 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 128:9bcdf88f62b0 517 */
<> 128:9bcdf88f62b0 518
<> 128:9bcdf88f62b0 519 typedef struct
<> 128:9bcdf88f62b0 520 {
<> 128:9bcdf88f62b0 521 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 522 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 523 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 524 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 525 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 128:9bcdf88f62b0 526 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 128:9bcdf88f62b0 527 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 528 } USART_TypeDef;
<> 128:9bcdf88f62b0 529
<> 128:9bcdf88f62b0 530 /**
<> 128:9bcdf88f62b0 531 * @brief Window WATCHDOG
<> 128:9bcdf88f62b0 532 */
<> 128:9bcdf88f62b0 533
<> 128:9bcdf88f62b0 534 typedef struct
<> 128:9bcdf88f62b0 535 {
<> 128:9bcdf88f62b0 536 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 537 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 538 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 539 } WWDG_TypeDef;
<> 128:9bcdf88f62b0 540 /**
AnnaBridge 145:64910690c574 541 * @brief USB_OTG_Core_Registers
<> 128:9bcdf88f62b0 542 */
<> 128:9bcdf88f62b0 543 typedef struct
<> 128:9bcdf88f62b0 544 {
AnnaBridge 145:64910690c574 545 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 145:64910690c574 546 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 145:64910690c574 547 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 145:64910690c574 548 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 145:64910690c574 549 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 145:64910690c574 550 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 145:64910690c574 551 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 145:64910690c574 552 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 145:64910690c574 553 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 145:64910690c574 554 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 145:64910690c574 555 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 145:64910690c574 556 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 145:64910690c574 557 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 145:64910690c574 558 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 145:64910690c574 559 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 145:64910690c574 560 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
AnnaBridge 145:64910690c574 561 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 145:64910690c574 562 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 145:64910690c574 563 } USB_OTG_GlobalTypeDef;
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /**
AnnaBridge 145:64910690c574 566 * @brief USB_OTG_device_Registers
<> 128:9bcdf88f62b0 567 */
<> 128:9bcdf88f62b0 568 typedef struct
<> 128:9bcdf88f62b0 569 {
AnnaBridge 145:64910690c574 570 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 145:64910690c574 571 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 145:64910690c574 572 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 145:64910690c574 573 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 145:64910690c574 574 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 145:64910690c574 575 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 145:64910690c574 576 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 145:64910690c574 577 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 145:64910690c574 578 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 145:64910690c574 579 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 145:64910690c574 580 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 145:64910690c574 581 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 145:64910690c574 582 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 145:64910690c574 583 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 145:64910690c574 584 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 145:64910690c574 585 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 145:64910690c574 586 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 145:64910690c574 587 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 145:64910690c574 588 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 145:64910690c574 589 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 145:64910690c574 590 } USB_OTG_DeviceTypeDef;
<> 128:9bcdf88f62b0 591
<> 128:9bcdf88f62b0 592 /**
AnnaBridge 145:64910690c574 593 * @brief USB_OTG_IN_Endpoint-Specific_Register
<> 128:9bcdf88f62b0 594 */
<> 128:9bcdf88f62b0 595 typedef struct
<> 128:9bcdf88f62b0 596 {
AnnaBridge 145:64910690c574 597 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 145:64910690c574 598 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 145:64910690c574 599 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 145:64910690c574 600 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 145:64910690c574 601 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 145:64910690c574 602 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 145:64910690c574 603 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 145:64910690c574 604 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 145:64910690c574 605 } USB_OTG_INEndpointTypeDef;
<> 128:9bcdf88f62b0 606
<> 128:9bcdf88f62b0 607 /**
AnnaBridge 145:64910690c574 608 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
<> 128:9bcdf88f62b0 609 */
<> 128:9bcdf88f62b0 610 typedef struct
<> 128:9bcdf88f62b0 611 {
AnnaBridge 145:64910690c574 612 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 145:64910690c574 613 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 145:64910690c574 614 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 145:64910690c574 615 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 145:64910690c574 616 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 145:64910690c574 617 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 145:64910690c574 618 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 145:64910690c574 619 } USB_OTG_OUTEndpointTypeDef;
<> 128:9bcdf88f62b0 620
<> 128:9bcdf88f62b0 621 /**
AnnaBridge 145:64910690c574 622 * @brief USB_OTG_Host_Mode_Register_Structures
<> 128:9bcdf88f62b0 623 */
<> 128:9bcdf88f62b0 624 typedef struct
<> 128:9bcdf88f62b0 625 {
AnnaBridge 145:64910690c574 626 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 145:64910690c574 627 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 145:64910690c574 628 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 145:64910690c574 629 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 145:64910690c574 630 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 145:64910690c574 631 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 145:64910690c574 632 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 145:64910690c574 633 } USB_OTG_HostTypeDef;
<> 128:9bcdf88f62b0 634
<> 128:9bcdf88f62b0 635 /**
AnnaBridge 145:64910690c574 636 * @brief USB_OTG_Host_Channel_Specific_Registers
<> 128:9bcdf88f62b0 637 */
<> 128:9bcdf88f62b0 638 typedef struct
<> 128:9bcdf88f62b0 639 {
AnnaBridge 145:64910690c574 640 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 145:64910690c574 641 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 145:64910690c574 642 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 145:64910690c574 643 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 145:64910690c574 644 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 145:64910690c574 645 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 145:64910690c574 646 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 145:64910690c574 647 } USB_OTG_HostChannelTypeDef;
AnnaBridge 145:64910690c574 648
AnnaBridge 145:64910690c574 649 /**
AnnaBridge 145:64910690c574 650 * @}
AnnaBridge 145:64910690c574 651 */
AnnaBridge 145:64910690c574 652
AnnaBridge 145:64910690c574 653 /** @addtogroup Peripheral_memory_map
AnnaBridge 145:64910690c574 654 * @{
<> 128:9bcdf88f62b0 655 */
<> 128:9bcdf88f62b0 656 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
AnnaBridge 145:64910690c574 657 #define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */
<> 128:9bcdf88f62b0 658 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 128:9bcdf88f62b0 659 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
AnnaBridge 145:64910690c574 660 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */
<> 128:9bcdf88f62b0 661 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
<> 128:9bcdf88f62b0 662 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
AnnaBridge 145:64910690c574 663 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
AnnaBridge 145:64910690c574 664 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 145:64910690c574 665 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
<> 128:9bcdf88f62b0 666
<> 128:9bcdf88f62b0 667 /* Legacy defines */
<> 128:9bcdf88f62b0 668 #define SRAM_BASE SRAM1_BASE
<> 128:9bcdf88f62b0 669 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 128:9bcdf88f62b0 670
<> 128:9bcdf88f62b0 671 /*!< Peripheral memory map */
<> 128:9bcdf88f62b0 672 #define APB1PERIPH_BASE PERIPH_BASE
<> 128:9bcdf88f62b0 673 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 128:9bcdf88f62b0 674 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 128:9bcdf88f62b0 675 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 128:9bcdf88f62b0 676
<> 128:9bcdf88f62b0 677 /*!< APB1 peripherals */
<> 128:9bcdf88f62b0 678 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 679 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 680 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 681 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 682 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 128:9bcdf88f62b0 683 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 684 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 685 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
<> 128:9bcdf88f62b0 686 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 687 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 688 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 689 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 690 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 128:9bcdf88f62b0 691 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 128:9bcdf88f62b0 692 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 128:9bcdf88f62b0 693 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 128:9bcdf88f62b0 694
<> 128:9bcdf88f62b0 695 /*!< APB2 peripherals */
<> 128:9bcdf88f62b0 696 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 697 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 698 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 128:9bcdf88f62b0 699 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 145:64910690c574 700 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 145:64910690c574 701 /* Legacy define */
AnnaBridge 145:64910690c574 702 #define ADC_BASE ADC1_COMMON_BASE
<> 128:9bcdf88f62b0 703 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 704 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 705 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 128:9bcdf88f62b0 706 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 707 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 708 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 709 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 710 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 128:9bcdf88f62b0 711
<> 128:9bcdf88f62b0 712 /*!< AHB1 peripherals */
<> 128:9bcdf88f62b0 713 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 714 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 715 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 716 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 717 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 718 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 128:9bcdf88f62b0 719 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 720 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 721 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 722 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 128:9bcdf88f62b0 723 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 128:9bcdf88f62b0 724 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 128:9bcdf88f62b0 725 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 128:9bcdf88f62b0 726 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 128:9bcdf88f62b0 727 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 128:9bcdf88f62b0 728 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 128:9bcdf88f62b0 729 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 128:9bcdf88f62b0 730 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 128:9bcdf88f62b0 731 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 128:9bcdf88f62b0 732 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 128:9bcdf88f62b0 733 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 128:9bcdf88f62b0 734 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 128:9bcdf88f62b0 735 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 128:9bcdf88f62b0 736 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 128:9bcdf88f62b0 737 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 128:9bcdf88f62b0 738 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 128:9bcdf88f62b0 739 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 128:9bcdf88f62b0 740
AnnaBridge 145:64910690c574 741
AnnaBridge 145:64910690c574 742 /*!< Debug MCU registers base address */
<> 128:9bcdf88f62b0 743 #define DBGMCU_BASE 0xE0042000U
<> 128:9bcdf88f62b0 744 /*!< USB registers base address */
<> 128:9bcdf88f62b0 745 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 128:9bcdf88f62b0 746
<> 128:9bcdf88f62b0 747 #define USB_OTG_GLOBAL_BASE 0x000U
<> 128:9bcdf88f62b0 748 #define USB_OTG_DEVICE_BASE 0x800U
<> 128:9bcdf88f62b0 749 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 128:9bcdf88f62b0 750 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 128:9bcdf88f62b0 751 #define USB_OTG_EP_REG_SIZE 0x20U
<> 128:9bcdf88f62b0 752 #define USB_OTG_HOST_BASE 0x400U
<> 128:9bcdf88f62b0 753 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 128:9bcdf88f62b0 754 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 128:9bcdf88f62b0 755 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 128:9bcdf88f62b0 756 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 128:9bcdf88f62b0 757 #define USB_OTG_FIFO_BASE 0x1000U
<> 128:9bcdf88f62b0 758 #define USB_OTG_FIFO_SIZE 0x1000U
<> 128:9bcdf88f62b0 759
AnnaBridge 145:64910690c574 760 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 145:64910690c574 761 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 145:64910690c574 762 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
<> 128:9bcdf88f62b0 763 /**
<> 128:9bcdf88f62b0 764 * @}
<> 128:9bcdf88f62b0 765 */
AnnaBridge 145:64910690c574 766
<> 128:9bcdf88f62b0 767 /** @addtogroup Peripheral_declaration
<> 128:9bcdf88f62b0 768 * @{
<> 128:9bcdf88f62b0 769 */
<> 128:9bcdf88f62b0 770 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 128:9bcdf88f62b0 771 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 128:9bcdf88f62b0 772 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 128:9bcdf88f62b0 773 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 128:9bcdf88f62b0 774 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 128:9bcdf88f62b0 775 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 128:9bcdf88f62b0 776 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 128:9bcdf88f62b0 777 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
<> 128:9bcdf88f62b0 778 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 128:9bcdf88f62b0 779 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 128:9bcdf88f62b0 780 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
<> 128:9bcdf88f62b0 781 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 128:9bcdf88f62b0 782 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 128:9bcdf88f62b0 783 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 128:9bcdf88f62b0 784 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 128:9bcdf88f62b0 785 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 128:9bcdf88f62b0 786 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 128:9bcdf88f62b0 787 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 128:9bcdf88f62b0 788 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 128:9bcdf88f62b0 789 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 145:64910690c574 790 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
AnnaBridge 145:64910690c574 791 /* Legacy define */
AnnaBridge 145:64910690c574 792 #define ADC ADC1_COMMON
<> 128:9bcdf88f62b0 793 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
<> 128:9bcdf88f62b0 794 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 145:64910690c574 795 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 128:9bcdf88f62b0 796 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 128:9bcdf88f62b0 797 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 128:9bcdf88f62b0 798 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 128:9bcdf88f62b0 799 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 128:9bcdf88f62b0 800 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 128:9bcdf88f62b0 801 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 128:9bcdf88f62b0 802 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 128:9bcdf88f62b0 803 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 128:9bcdf88f62b0 804 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 128:9bcdf88f62b0 805 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 128:9bcdf88f62b0 806 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 128:9bcdf88f62b0 807 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 128:9bcdf88f62b0 808 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 128:9bcdf88f62b0 809 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 128:9bcdf88f62b0 810 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 128:9bcdf88f62b0 811 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 128:9bcdf88f62b0 812 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 128:9bcdf88f62b0 813 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 128:9bcdf88f62b0 814 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 128:9bcdf88f62b0 815 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 128:9bcdf88f62b0 816 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 128:9bcdf88f62b0 817 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 128:9bcdf88f62b0 818 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 128:9bcdf88f62b0 819 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 128:9bcdf88f62b0 820 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 128:9bcdf88f62b0 821 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 128:9bcdf88f62b0 822 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 128:9bcdf88f62b0 823 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 128:9bcdf88f62b0 824 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 128:9bcdf88f62b0 825 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 128:9bcdf88f62b0 826 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 128:9bcdf88f62b0 827 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 128:9bcdf88f62b0 828 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 128:9bcdf88f62b0 829 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 128:9bcdf88f62b0 830
<> 128:9bcdf88f62b0 831 /**
<> 128:9bcdf88f62b0 832 * @}
<> 128:9bcdf88f62b0 833 */
<> 128:9bcdf88f62b0 834
<> 128:9bcdf88f62b0 835 /** @addtogroup Exported_constants
<> 128:9bcdf88f62b0 836 * @{
<> 128:9bcdf88f62b0 837 */
<> 128:9bcdf88f62b0 838
<> 128:9bcdf88f62b0 839 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 128:9bcdf88f62b0 840 * @{
<> 128:9bcdf88f62b0 841 */
<> 128:9bcdf88f62b0 842
<> 128:9bcdf88f62b0 843 /******************************************************************************/
<> 128:9bcdf88f62b0 844 /* Peripheral Registers_Bits_Definition */
<> 128:9bcdf88f62b0 845 /******************************************************************************/
<> 128:9bcdf88f62b0 846
<> 128:9bcdf88f62b0 847 /******************************************************************************/
<> 128:9bcdf88f62b0 848 /* */
<> 128:9bcdf88f62b0 849 /* Analog to Digital Converter */
<> 128:9bcdf88f62b0 850 /* */
<> 128:9bcdf88f62b0 851 /******************************************************************************/
AnnaBridge 145:64910690c574 852
<> 128:9bcdf88f62b0 853 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 145:64910690c574 854 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 145:64910690c574 855 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 856 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 145:64910690c574 857 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 145:64910690c574 858 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 859 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 145:64910690c574 860 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 145:64910690c574 861 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 862 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 145:64910690c574 863 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 145:64910690c574 864 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 865 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 145:64910690c574 866 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 145:64910690c574 867 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 868 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 145:64910690c574 869 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 145:64910690c574 870 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 871 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
<> 128:9bcdf88f62b0 872
<> 128:9bcdf88f62b0 873 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 145:64910690c574 874 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 145:64910690c574 875 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 876 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 145:64910690c574 877 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 878 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 879 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 880 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 881 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 882 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 145:64910690c574 883 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 884 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 145:64910690c574 885 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 145:64910690c574 886 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 887 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 145:64910690c574 888 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 145:64910690c574 889 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 890 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 145:64910690c574 891 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 145:64910690c574 892 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 893 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 145:64910690c574 894 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 145:64910690c574 895 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 896 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 145:64910690c574 897 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 145:64910690c574 898 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 899 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 145:64910690c574 900 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 145:64910690c574 901 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 902 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 145:64910690c574 903 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 145:64910690c574 904 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 905 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 145:64910690c574 906 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 145:64910690c574 907 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 145:64910690c574 908 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 145:64910690c574 909 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 910 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 911 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 912 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 145:64910690c574 913 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 914 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 145:64910690c574 915 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 145:64910690c574 916 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 917 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 145:64910690c574 918 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 145:64910690c574 919 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 920 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 145:64910690c574 921 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 922 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 923 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 145:64910690c574 924 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 925 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
<> 128:9bcdf88f62b0 926
<> 128:9bcdf88f62b0 927 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 145:64910690c574 928 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 145:64910690c574 929 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 930 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 145:64910690c574 931 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 145:64910690c574 932 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 933 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 145:64910690c574 934 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 145:64910690c574 935 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 936 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 145:64910690c574 937 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 145:64910690c574 938 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 939 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 145:64910690c574 940 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 145:64910690c574 941 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 942 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 145:64910690c574 943 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 145:64910690c574 944 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 945 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 145:64910690c574 946 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 145:64910690c574 947 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 948 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 145:64910690c574 949 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 950 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 951 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 952 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 953 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 145:64910690c574 954 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 955 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 145:64910690c574 956 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 957 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 958 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 145:64910690c574 959 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 960 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 145:64910690c574 961 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 145:64910690c574 962 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 963 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 145:64910690c574 964 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 965 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 966 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 967 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 968 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 145:64910690c574 969 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 970 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 145:64910690c574 971 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 972 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 973 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 145:64910690c574 974 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 975 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
<> 128:9bcdf88f62b0 976
<> 128:9bcdf88f62b0 977 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 145:64910690c574 978 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 145:64910690c574 979 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 980 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 145:64910690c574 981 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 982 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 983 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 984 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 145:64910690c574 985 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 145:64910690c574 986 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 145:64910690c574 987 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 988 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 989 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 990 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 145:64910690c574 991 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 145:64910690c574 992 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 145:64910690c574 993 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 994 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 995 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 996 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 145:64910690c574 997 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 145:64910690c574 998 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 145:64910690c574 999 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1000 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1001 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1002 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 145:64910690c574 1003 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 1004 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 145:64910690c574 1005 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1006 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1007 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1008 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 145:64910690c574 1009 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 145:64910690c574 1010 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 145:64910690c574 1011 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1012 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1013 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1014 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 145:64910690c574 1015 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 145:64910690c574 1016 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 145:64910690c574 1017 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1018 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1019 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1020 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 145:64910690c574 1021 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 145:64910690c574 1022 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 145:64910690c574 1023 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1024 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1025 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1026 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 145:64910690c574 1027 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 145:64910690c574 1028 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 145:64910690c574 1029 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1030 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1031 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 1032
<> 128:9bcdf88f62b0 1033 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 145:64910690c574 1034 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 145:64910690c574 1035 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 1036 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 145:64910690c574 1037 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1038 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1039 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1040 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 145:64910690c574 1041 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 145:64910690c574 1042 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 145:64910690c574 1043 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1044 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1045 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1046 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 145:64910690c574 1047 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 145:64910690c574 1048 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 145:64910690c574 1049 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1050 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1051 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1052 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 145:64910690c574 1053 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 145:64910690c574 1054 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 145:64910690c574 1055 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1056 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1057 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1058 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 145:64910690c574 1059 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 1060 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 145:64910690c574 1061 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1062 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1063 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1064 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 145:64910690c574 1065 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 145:64910690c574 1066 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 145:64910690c574 1067 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1068 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1069 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1070 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 145:64910690c574 1071 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 145:64910690c574 1072 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 145:64910690c574 1073 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1074 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1075 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1076 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 145:64910690c574 1077 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 145:64910690c574 1078 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 145:64910690c574 1079 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1080 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1081 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1082 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 145:64910690c574 1083 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 145:64910690c574 1084 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 145:64910690c574 1085 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1086 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1087 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1088 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 145:64910690c574 1089 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 145:64910690c574 1090 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 145:64910690c574 1091 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1092 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 1093 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1094
<> 128:9bcdf88f62b0 1095 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 145:64910690c574 1096 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 145:64910690c574 1097 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1098 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
<> 128:9bcdf88f62b0 1099
<> 128:9bcdf88f62b0 1100 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 145:64910690c574 1101 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 145:64910690c574 1102 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1103 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
<> 128:9bcdf88f62b0 1104
<> 128:9bcdf88f62b0 1105 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 145:64910690c574 1106 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 145:64910690c574 1107 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1108 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
<> 128:9bcdf88f62b0 1109
<> 128:9bcdf88f62b0 1110 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 145:64910690c574 1111 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 145:64910690c574 1112 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1113 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
<> 128:9bcdf88f62b0 1114
<> 128:9bcdf88f62b0 1115 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 145:64910690c574 1116 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 145:64910690c574 1117 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1118 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
<> 128:9bcdf88f62b0 1119
<> 128:9bcdf88f62b0 1120 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 145:64910690c574 1121 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 145:64910690c574 1122 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 1123 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
<> 128:9bcdf88f62b0 1124
<> 128:9bcdf88f62b0 1125 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 145:64910690c574 1126 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 145:64910690c574 1127 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 1128 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1129 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1130 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1131 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1132 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1133 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1134 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 145:64910690c574 1135 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 145:64910690c574 1136 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1137 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1138 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1139 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1140 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1141 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1142 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 145:64910690c574 1143 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 145:64910690c574 1144 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1145 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1146 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1147 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1148 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1149 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1150 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 145:64910690c574 1151 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 145:64910690c574 1152 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1153 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1154 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1155 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1156 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1157 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1158 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 145:64910690c574 1159 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 145:64910690c574 1160 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 145:64910690c574 1161 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1162 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1163 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1164 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1165
<> 128:9bcdf88f62b0 1166 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 145:64910690c574 1167 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 145:64910690c574 1168 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 1169 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1170 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1171 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1172 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1173 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1174 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1175 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 145:64910690c574 1176 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 145:64910690c574 1177 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1178 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1179 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1180 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1181 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1182 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1183 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 145:64910690c574 1184 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 145:64910690c574 1185 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1186 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1187 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1188 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1189 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1190 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1191 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 145:64910690c574 1192 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 145:64910690c574 1193 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1194 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1195 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1196 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1197 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1198 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1199 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 145:64910690c574 1200 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 145:64910690c574 1201 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1202 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1203 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1204 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1205 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1206 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1207 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 145:64910690c574 1208 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 145:64910690c574 1209 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1210 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1211 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1212 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1213 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 1214 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1215
<> 128:9bcdf88f62b0 1216 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 145:64910690c574 1217 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 145:64910690c574 1218 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 1219 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 145:64910690c574 1220 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1221 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1222 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1223 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1224 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1225 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 145:64910690c574 1226 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 145:64910690c574 1227 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 145:64910690c574 1228 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1229 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1230 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1231 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1232 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1233 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 145:64910690c574 1234 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 145:64910690c574 1235 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 145:64910690c574 1236 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1237 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1238 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1239 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1240 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1241 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 145:64910690c574 1242 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 145:64910690c574 1243 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1244 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1245 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1246 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1247 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1248 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1249 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 145:64910690c574 1250 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 145:64910690c574 1251 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1252 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1253 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1254 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1255 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1256 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1257 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 145:64910690c574 1258 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 145:64910690c574 1259 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 145:64910690c574 1260 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1261 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1262 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1263 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 1264 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1265
<> 128:9bcdf88f62b0 1266 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 145:64910690c574 1267 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 145:64910690c574 1268 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 1269 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 145:64910690c574 1270 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1271 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1272 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1273 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1274 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1275 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 145:64910690c574 1276 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 145:64910690c574 1277 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 145:64910690c574 1278 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1279 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1280 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1281 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1282 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1283 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 145:64910690c574 1284 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 145:64910690c574 1285 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 145:64910690c574 1286 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1287 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1288 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1289 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1290 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1291 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 145:64910690c574 1292 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 145:64910690c574 1293 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 145:64910690c574 1294 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1295 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1296 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1297 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1298 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1299 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 145:64910690c574 1300 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 1301 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 145:64910690c574 1302 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1303 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1304
<> 128:9bcdf88f62b0 1305 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 145:64910690c574 1306 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 145:64910690c574 1307 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1308 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
<> 128:9bcdf88f62b0 1309
<> 128:9bcdf88f62b0 1310 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 145:64910690c574 1311 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 145:64910690c574 1312 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1313 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
<> 128:9bcdf88f62b0 1314
<> 128:9bcdf88f62b0 1315 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 145:64910690c574 1316 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 145:64910690c574 1317 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1318 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
<> 128:9bcdf88f62b0 1319
<> 128:9bcdf88f62b0 1320 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 145:64910690c574 1321 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 145:64910690c574 1322 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1323 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
<> 128:9bcdf88f62b0 1324
<> 128:9bcdf88f62b0 1325 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 145:64910690c574 1326 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 145:64910690c574 1327 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1328 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 145:64910690c574 1329 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 145:64910690c574 1330 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 1331 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
<> 128:9bcdf88f62b0 1332
<> 128:9bcdf88f62b0 1333 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 145:64910690c574 1334 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 145:64910690c574 1335 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1336 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 145:64910690c574 1337 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 145:64910690c574 1338 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1339 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 145:64910690c574 1340 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 145:64910690c574 1341 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1342 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 145:64910690c574 1343 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 145:64910690c574 1344 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1345 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 145:64910690c574 1346 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 145:64910690c574 1347 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1348 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 145:64910690c574 1349 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 145:64910690c574 1350 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1351 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
<> 128:9bcdf88f62b0 1352
<> 128:9bcdf88f62b0 1353 /* Legacy defines */
<> 128:9bcdf88f62b0 1354 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 128:9bcdf88f62b0 1355
<> 128:9bcdf88f62b0 1356 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 145:64910690c574 1357 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 145:64910690c574 1358 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 1359 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 145:64910690c574 1360 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1361 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1362 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1363 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1364 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1365 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 145:64910690c574 1366 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 1367 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 145:64910690c574 1368 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1369 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1370 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1371 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1372 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 145:64910690c574 1373 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1374 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 145:64910690c574 1375 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 145:64910690c574 1376 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 1377 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 145:64910690c574 1378 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1379 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1380 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 145:64910690c574 1381 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 1382 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 145:64910690c574 1383 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1384 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1385 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 145:64910690c574 1386 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1387 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 145:64910690c574 1388 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 145:64910690c574 1389 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1390 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
<> 128:9bcdf88f62b0 1391
<> 128:9bcdf88f62b0 1392 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 145:64910690c574 1393 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 145:64910690c574 1394 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1395 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 145:64910690c574 1396 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 145:64910690c574 1397 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 1398 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 145:64910690c574 1399
AnnaBridge 145:64910690c574 1400 /* Legacy defines */
AnnaBridge 145:64910690c574 1401 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 145:64910690c574 1402 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
<> 128:9bcdf88f62b0 1403
<> 128:9bcdf88f62b0 1404 /******************************************************************************/
<> 128:9bcdf88f62b0 1405 /* */
<> 128:9bcdf88f62b0 1406 /* CRC calculation unit */
<> 128:9bcdf88f62b0 1407 /* */
<> 128:9bcdf88f62b0 1408 /******************************************************************************/
<> 128:9bcdf88f62b0 1409 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 145:64910690c574 1410 #define CRC_DR_DR_Pos (0U)
AnnaBridge 145:64910690c574 1411 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 1412 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 128:9bcdf88f62b0 1413
<> 128:9bcdf88f62b0 1414
<> 128:9bcdf88f62b0 1415 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 145:64910690c574 1416 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 145:64910690c574 1417 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 1418 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
<> 128:9bcdf88f62b0 1419
<> 128:9bcdf88f62b0 1420
<> 128:9bcdf88f62b0 1421 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 145:64910690c574 1422 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 145:64910690c574 1423 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1424 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 145:64910690c574 1425
<> 128:9bcdf88f62b0 1426
<> 128:9bcdf88f62b0 1427 /******************************************************************************/
<> 128:9bcdf88f62b0 1428 /* */
<> 128:9bcdf88f62b0 1429 /* DMA Controller */
<> 128:9bcdf88f62b0 1430 /* */
<> 128:9bcdf88f62b0 1431 /******************************************************************************/
<> 128:9bcdf88f62b0 1432 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 145:64910690c574 1433 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 145:64910690c574 1434 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 145:64910690c574 1435 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 145:64910690c574 1436 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 145:64910690c574 1437 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 145:64910690c574 1438 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 145:64910690c574 1439 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 145:64910690c574 1440 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 145:64910690c574 1441 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 145:64910690c574 1442 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 1443 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1444 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 145:64910690c574 1445 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 145:64910690c574 1446 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 145:64910690c574 1447 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1448 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1449 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 145:64910690c574 1450 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1451 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 145:64910690c574 1452 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 145:64910690c574 1453 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1454 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 145:64910690c574 1455 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 145:64910690c574 1456 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 1457 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 145:64910690c574 1458 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1459 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1460 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 145:64910690c574 1461 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1462 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 145:64910690c574 1463 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 145:64910690c574 1464 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 145:64910690c574 1465 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 145:64910690c574 1466 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1467 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1468 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 145:64910690c574 1469 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 145:64910690c574 1470 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 145:64910690c574 1471 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1472 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1473 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 145:64910690c574 1474 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1475 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 145:64910690c574 1476 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 145:64910690c574 1477 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1478 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 145:64910690c574 1479 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 145:64910690c574 1480 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1481 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 145:64910690c574 1482 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 145:64910690c574 1483 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 1484 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 145:64910690c574 1485 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1486 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1487 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 145:64910690c574 1488 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1489 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 145:64910690c574 1490 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 145:64910690c574 1491 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1492 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 145:64910690c574 1493 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 145:64910690c574 1494 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1495 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 145:64910690c574 1496 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 145:64910690c574 1497 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1498 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 145:64910690c574 1499 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 145:64910690c574 1500 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1501 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 145:64910690c574 1502 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 145:64910690c574 1503 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1504 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
<> 128:9bcdf88f62b0 1505
<> 128:9bcdf88f62b0 1506 /* Legacy defines */
AnnaBridge 145:64910690c574 1507 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 145:64910690c574 1508 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1509 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
<> 128:9bcdf88f62b0 1510
<> 128:9bcdf88f62b0 1511 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 145:64910690c574 1512 #define DMA_SxNDT_Pos (0U)
AnnaBridge 145:64910690c574 1513 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 1514 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 145:64910690c574 1515 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1516 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1517 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1518 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1519 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1520 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1521 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1522 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1523 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1524 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1525 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1526 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1527 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1528 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1529 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1530 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 1531
<> 128:9bcdf88f62b0 1532 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 145:64910690c574 1533 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 145:64910690c574 1534 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1535 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 145:64910690c574 1536 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 145:64910690c574 1537 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 145:64910690c574 1538 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 145:64910690c574 1539 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1540 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1541 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1542 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 145:64910690c574 1543 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1544 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 145:64910690c574 1545 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 145:64910690c574 1546 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 1547 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 145:64910690c574 1548 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1549 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1550
<> 128:9bcdf88f62b0 1551 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 145:64910690c574 1552 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 145:64910690c574 1553 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1554 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 145:64910690c574 1555 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 145:64910690c574 1556 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1557 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 145:64910690c574 1558 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 145:64910690c574 1559 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1560 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 145:64910690c574 1561 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 145:64910690c574 1562 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1563 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 145:64910690c574 1564 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 145:64910690c574 1565 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1566 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 145:64910690c574 1567 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 145:64910690c574 1568 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1569 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 145:64910690c574 1570 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 145:64910690c574 1571 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1572 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 145:64910690c574 1573 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 145:64910690c574 1574 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1575 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 145:64910690c574 1576 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 145:64910690c574 1577 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1578 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 145:64910690c574 1579 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 145:64910690c574 1580 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1581 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 145:64910690c574 1582 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 145:64910690c574 1583 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1584 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 145:64910690c574 1585 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 145:64910690c574 1586 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1587 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 145:64910690c574 1588 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 145:64910690c574 1589 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1590 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 145:64910690c574 1591 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 145:64910690c574 1592 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1593 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 145:64910690c574 1594 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 145:64910690c574 1595 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1596 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 145:64910690c574 1597 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 145:64910690c574 1598 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1599 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 145:64910690c574 1600 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 145:64910690c574 1601 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1602 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 145:64910690c574 1603 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 145:64910690c574 1604 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1605 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 145:64910690c574 1606 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 145:64910690c574 1607 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1608 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 145:64910690c574 1609 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 145:64910690c574 1610 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1611 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
<> 128:9bcdf88f62b0 1612
<> 128:9bcdf88f62b0 1613 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 145:64910690c574 1614 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 145:64910690c574 1615 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1616 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 145:64910690c574 1617 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 145:64910690c574 1618 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1619 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 145:64910690c574 1620 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 145:64910690c574 1621 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1622 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 145:64910690c574 1623 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 145:64910690c574 1624 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1625 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 145:64910690c574 1626 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 145:64910690c574 1627 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1628 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 145:64910690c574 1629 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 145:64910690c574 1630 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1631 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 145:64910690c574 1632 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 145:64910690c574 1633 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1634 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 145:64910690c574 1635 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 145:64910690c574 1636 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1637 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 145:64910690c574 1638 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 145:64910690c574 1639 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1640 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 145:64910690c574 1641 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 145:64910690c574 1642 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1643 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 145:64910690c574 1644 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 145:64910690c574 1645 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1646 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 145:64910690c574 1647 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 145:64910690c574 1648 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1649 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 145:64910690c574 1650 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 145:64910690c574 1651 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1652 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 145:64910690c574 1653 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 145:64910690c574 1654 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1655 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 145:64910690c574 1656 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 145:64910690c574 1657 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1658 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 145:64910690c574 1659 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 145:64910690c574 1660 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1661 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 145:64910690c574 1662 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 145:64910690c574 1663 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1664 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 145:64910690c574 1665 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 145:64910690c574 1666 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1667 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 145:64910690c574 1668 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 145:64910690c574 1669 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1670 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 145:64910690c574 1671 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 145:64910690c574 1672 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1673 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
<> 128:9bcdf88f62b0 1674
<> 128:9bcdf88f62b0 1675 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 145:64910690c574 1676 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 145:64910690c574 1677 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1678 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 145:64910690c574 1679 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 145:64910690c574 1680 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1681 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 145:64910690c574 1682 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 145:64910690c574 1683 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1684 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 145:64910690c574 1685 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 145:64910690c574 1686 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1687 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 145:64910690c574 1688 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 145:64910690c574 1689 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1690 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 145:64910690c574 1691 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 145:64910690c574 1692 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1693 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 145:64910690c574 1694 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 145:64910690c574 1695 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1696 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 145:64910690c574 1697 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 145:64910690c574 1698 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1699 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 145:64910690c574 1700 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 145:64910690c574 1701 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1702 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 145:64910690c574 1703 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 145:64910690c574 1704 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1705 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 145:64910690c574 1706 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 145:64910690c574 1707 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1708 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 145:64910690c574 1709 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 145:64910690c574 1710 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1711 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 145:64910690c574 1712 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 145:64910690c574 1713 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1714 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 145:64910690c574 1715 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 145:64910690c574 1716 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1717 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 145:64910690c574 1718 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 145:64910690c574 1719 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1720 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 145:64910690c574 1721 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 145:64910690c574 1722 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1723 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 145:64910690c574 1724 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 145:64910690c574 1725 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1726 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 145:64910690c574 1727 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 145:64910690c574 1728 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1729 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 145:64910690c574 1730 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 145:64910690c574 1731 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1732 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 145:64910690c574 1733 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 145:64910690c574 1734 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1735 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
<> 128:9bcdf88f62b0 1736
<> 128:9bcdf88f62b0 1737 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 145:64910690c574 1738 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 145:64910690c574 1739 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 1740 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 145:64910690c574 1741 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 145:64910690c574 1742 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 1743 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 145:64910690c574 1744 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 145:64910690c574 1745 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 1746 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 145:64910690c574 1747 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 145:64910690c574 1748 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 1749 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 145:64910690c574 1750 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 145:64910690c574 1751 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1752 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 145:64910690c574 1753 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 145:64910690c574 1754 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1755 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 145:64910690c574 1756 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 145:64910690c574 1757 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1758 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 145:64910690c574 1759 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 145:64910690c574 1760 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1761 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 145:64910690c574 1762 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 145:64910690c574 1763 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1764 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 145:64910690c574 1765 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 145:64910690c574 1766 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1767 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 145:64910690c574 1768 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 145:64910690c574 1769 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1770 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 145:64910690c574 1771 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 145:64910690c574 1772 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1773 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 145:64910690c574 1774 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 145:64910690c574 1775 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1776 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 145:64910690c574 1777 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 145:64910690c574 1778 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1779 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 145:64910690c574 1780 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 145:64910690c574 1781 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1782 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 145:64910690c574 1783 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 145:64910690c574 1784 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1785 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 145:64910690c574 1786 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 145:64910690c574 1787 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1788 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 145:64910690c574 1789 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 145:64910690c574 1790 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1791 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 145:64910690c574 1792 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 145:64910690c574 1793 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1794 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 145:64910690c574 1795 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 145:64910690c574 1796 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1797 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 145:64910690c574 1798
AnnaBridge 145:64910690c574 1799 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 145:64910690c574 1800 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 145:64910690c574 1801 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 1802 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 145:64910690c574 1803
AnnaBridge 145:64910690c574 1804 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 145:64910690c574 1805 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 145:64910690c574 1806 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 1807 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 145:64910690c574 1808
AnnaBridge 145:64910690c574 1809 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 145:64910690c574 1810 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 145:64910690c574 1811 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 1812 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
<> 128:9bcdf88f62b0 1813
<> 128:9bcdf88f62b0 1814
<> 128:9bcdf88f62b0 1815 /******************************************************************************/
<> 128:9bcdf88f62b0 1816 /* */
<> 128:9bcdf88f62b0 1817 /* External Interrupt/Event Controller */
<> 128:9bcdf88f62b0 1818 /* */
<> 128:9bcdf88f62b0 1819 /******************************************************************************/
<> 128:9bcdf88f62b0 1820 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 145:64910690c574 1821 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 145:64910690c574 1822 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1823 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 145:64910690c574 1824 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 145:64910690c574 1825 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1826 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 145:64910690c574 1827 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 145:64910690c574 1828 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1829 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 145:64910690c574 1830 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 145:64910690c574 1831 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1832 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 145:64910690c574 1833 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 145:64910690c574 1834 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1835 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 145:64910690c574 1836 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 145:64910690c574 1837 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1838 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 145:64910690c574 1839 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 145:64910690c574 1840 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1841 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 145:64910690c574 1842 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 145:64910690c574 1843 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1844 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 145:64910690c574 1845 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 145:64910690c574 1846 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1847 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 145:64910690c574 1848 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 145:64910690c574 1849 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1850 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 145:64910690c574 1851 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 145:64910690c574 1852 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1853 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 145:64910690c574 1854 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 145:64910690c574 1855 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1856 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 145:64910690c574 1857 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 145:64910690c574 1858 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1859 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 145:64910690c574 1860 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 145:64910690c574 1861 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1862 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 145:64910690c574 1863 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 145:64910690c574 1864 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1865 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 145:64910690c574 1866 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 145:64910690c574 1867 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1868 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 145:64910690c574 1869 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 145:64910690c574 1870 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1871 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 145:64910690c574 1872 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 145:64910690c574 1873 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1874 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 145:64910690c574 1875 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 145:64910690c574 1876 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1877 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 145:64910690c574 1878 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 145:64910690c574 1879 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1880 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 145:64910690c574 1881 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 145:64910690c574 1882 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1883 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 145:64910690c574 1884 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 145:64910690c574 1885 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1886 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 145:64910690c574 1887 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 145:64910690c574 1888 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1889 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 145:64910690c574 1890
AnnaBridge 145:64910690c574 1891 /* Reference Defines */
AnnaBridge 145:64910690c574 1892 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 145:64910690c574 1893 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 145:64910690c574 1894 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 145:64910690c574 1895 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 145:64910690c574 1896 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 145:64910690c574 1897 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 145:64910690c574 1898 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 145:64910690c574 1899 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 145:64910690c574 1900 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 145:64910690c574 1901 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 145:64910690c574 1902 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 145:64910690c574 1903 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 145:64910690c574 1904 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 145:64910690c574 1905 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 145:64910690c574 1906 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 145:64910690c574 1907 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 145:64910690c574 1908 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 145:64910690c574 1909 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 145:64910690c574 1910 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 145:64910690c574 1911 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 145:64910690c574 1912 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 145:64910690c574 1913 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 145:64910690c574 1914 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 145:64910690c574 1915 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 145:64910690c574 1916 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
AnnaBridge 145:64910690c574 1917 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 128:9bcdf88f62b0 1918
<> 128:9bcdf88f62b0 1919 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 145:64910690c574 1920 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 145:64910690c574 1921 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 1922 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 145:64910690c574 1923 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 145:64910690c574 1924 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 1925 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 145:64910690c574 1926 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 145:64910690c574 1927 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 1928 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 145:64910690c574 1929 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 145:64910690c574 1930 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 1931 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 145:64910690c574 1932 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 145:64910690c574 1933 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 1934 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 145:64910690c574 1935 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 145:64910690c574 1936 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 1937 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 145:64910690c574 1938 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 145:64910690c574 1939 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 1940 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 145:64910690c574 1941 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 145:64910690c574 1942 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 1943 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 145:64910690c574 1944 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 145:64910690c574 1945 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 1946 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 145:64910690c574 1947 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 145:64910690c574 1948 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 1949 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 145:64910690c574 1950 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 145:64910690c574 1951 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 1952 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 145:64910690c574 1953 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 145:64910690c574 1954 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 1955 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 145:64910690c574 1956 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 145:64910690c574 1957 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 1958 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 145:64910690c574 1959 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 145:64910690c574 1960 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 1961 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 145:64910690c574 1962 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 145:64910690c574 1963 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 1964 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 145:64910690c574 1965 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 145:64910690c574 1966 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 1967 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 145:64910690c574 1968 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 145:64910690c574 1969 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 1970 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 145:64910690c574 1971 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 145:64910690c574 1972 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 1973 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 145:64910690c574 1974 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 145:64910690c574 1975 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 1976 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 145:64910690c574 1977 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 145:64910690c574 1978 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 1979 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 145:64910690c574 1980 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 145:64910690c574 1981 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 1982 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 145:64910690c574 1983 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 145:64910690c574 1984 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 1985 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 145:64910690c574 1986 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 145:64910690c574 1987 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 1988 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 145:64910690c574 1989
AnnaBridge 145:64910690c574 1990 /* Reference Defines */
AnnaBridge 145:64910690c574 1991 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 145:64910690c574 1992 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 145:64910690c574 1993 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 145:64910690c574 1994 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 145:64910690c574 1995 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 145:64910690c574 1996 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 145:64910690c574 1997 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 145:64910690c574 1998 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 145:64910690c574 1999 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 145:64910690c574 2000 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 145:64910690c574 2001 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 145:64910690c574 2002 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 145:64910690c574 2003 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 145:64910690c574 2004 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 145:64910690c574 2005 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 145:64910690c574 2006 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 145:64910690c574 2007 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 145:64910690c574 2008 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 145:64910690c574 2009 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 145:64910690c574 2010 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 145:64910690c574 2011 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 145:64910690c574 2012 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 145:64910690c574 2013 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 128:9bcdf88f62b0 2014
<> 128:9bcdf88f62b0 2015 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 145:64910690c574 2016 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 145:64910690c574 2017 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2018 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 145:64910690c574 2019 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 145:64910690c574 2020 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2021 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 145:64910690c574 2022 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 145:64910690c574 2023 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2024 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 145:64910690c574 2025 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 145:64910690c574 2026 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2027 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 145:64910690c574 2028 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 145:64910690c574 2029 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2030 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 145:64910690c574 2031 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 145:64910690c574 2032 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2033 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 145:64910690c574 2034 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 145:64910690c574 2035 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2036 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 145:64910690c574 2037 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 145:64910690c574 2038 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2039 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 145:64910690c574 2040 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 145:64910690c574 2041 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2042 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 145:64910690c574 2043 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 145:64910690c574 2044 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2045 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 145:64910690c574 2046 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 145:64910690c574 2047 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2048 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 145:64910690c574 2049 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 145:64910690c574 2050 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2051 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 145:64910690c574 2052 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 145:64910690c574 2053 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2054 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 145:64910690c574 2055 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 145:64910690c574 2056 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2057 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 145:64910690c574 2058 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 145:64910690c574 2059 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2060 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 145:64910690c574 2061 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 145:64910690c574 2062 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2063 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 145:64910690c574 2064 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 145:64910690c574 2065 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2066 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 145:64910690c574 2067 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 145:64910690c574 2068 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2069 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 145:64910690c574 2070 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 145:64910690c574 2071 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2072 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 145:64910690c574 2073 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 145:64910690c574 2074 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2075 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 145:64910690c574 2076 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 145:64910690c574 2077 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2078 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 145:64910690c574 2079 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 145:64910690c574 2080 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2081 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 145:64910690c574 2082 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 145:64910690c574 2083 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2084 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 2085
<> 128:9bcdf88f62b0 2086 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 145:64910690c574 2087 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 145:64910690c574 2088 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2089 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 145:64910690c574 2090 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 145:64910690c574 2091 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2092 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 145:64910690c574 2093 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 145:64910690c574 2094 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2095 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 145:64910690c574 2096 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 145:64910690c574 2097 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2098 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 145:64910690c574 2099 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 145:64910690c574 2100 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2101 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 145:64910690c574 2102 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 145:64910690c574 2103 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2104 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 145:64910690c574 2105 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 145:64910690c574 2106 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2107 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 145:64910690c574 2108 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 145:64910690c574 2109 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2110 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 145:64910690c574 2111 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 145:64910690c574 2112 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2113 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 145:64910690c574 2114 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 145:64910690c574 2115 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2116 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 145:64910690c574 2117 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 145:64910690c574 2118 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2119 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 145:64910690c574 2120 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 145:64910690c574 2121 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2122 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 145:64910690c574 2123 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 145:64910690c574 2124 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2125 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 145:64910690c574 2126 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 145:64910690c574 2127 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2128 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 145:64910690c574 2129 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 145:64910690c574 2130 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2131 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 145:64910690c574 2132 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 145:64910690c574 2133 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2134 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 145:64910690c574 2135 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 145:64910690c574 2136 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2137 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 145:64910690c574 2138 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 145:64910690c574 2139 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2140 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 145:64910690c574 2141 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 145:64910690c574 2142 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2143 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 145:64910690c574 2144 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 145:64910690c574 2145 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2146 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 145:64910690c574 2147 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 145:64910690c574 2148 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2149 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 145:64910690c574 2150 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 145:64910690c574 2151 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2152 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 145:64910690c574 2153 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 145:64910690c574 2154 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2155 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 2156
<> 128:9bcdf88f62b0 2157 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 145:64910690c574 2158 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 145:64910690c574 2159 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2160 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 145:64910690c574 2161 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 145:64910690c574 2162 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2163 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 145:64910690c574 2164 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 145:64910690c574 2165 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2166 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 145:64910690c574 2167 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 145:64910690c574 2168 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2169 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 145:64910690c574 2170 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 145:64910690c574 2171 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2172 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 145:64910690c574 2173 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 145:64910690c574 2174 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2175 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 145:64910690c574 2176 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 145:64910690c574 2177 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2178 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 145:64910690c574 2179 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 145:64910690c574 2180 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2181 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 145:64910690c574 2182 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 145:64910690c574 2183 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2184 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 145:64910690c574 2185 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 145:64910690c574 2186 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2187 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 145:64910690c574 2188 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 145:64910690c574 2189 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2190 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 145:64910690c574 2191 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 145:64910690c574 2192 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2193 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 145:64910690c574 2194 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 145:64910690c574 2195 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2196 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 145:64910690c574 2197 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 145:64910690c574 2198 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2199 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 145:64910690c574 2200 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 145:64910690c574 2201 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2202 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 145:64910690c574 2203 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 145:64910690c574 2204 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2205 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 145:64910690c574 2206 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 145:64910690c574 2207 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2208 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 145:64910690c574 2209 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 145:64910690c574 2210 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2211 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 145:64910690c574 2212 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 145:64910690c574 2213 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2214 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 145:64910690c574 2215 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 145:64910690c574 2216 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2217 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 145:64910690c574 2218 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 145:64910690c574 2219 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2220 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 145:64910690c574 2221 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 145:64910690c574 2222 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2223 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 145:64910690c574 2224 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 145:64910690c574 2225 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2226 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 128:9bcdf88f62b0 2227
<> 128:9bcdf88f62b0 2228 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 145:64910690c574 2229 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 145:64910690c574 2230 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2231 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 145:64910690c574 2232 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 145:64910690c574 2233 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2234 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 145:64910690c574 2235 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 145:64910690c574 2236 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2237 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 145:64910690c574 2238 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 145:64910690c574 2239 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2240 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 145:64910690c574 2241 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 145:64910690c574 2242 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2243 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 145:64910690c574 2244 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 145:64910690c574 2245 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2246 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 145:64910690c574 2247 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 145:64910690c574 2248 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2249 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 145:64910690c574 2250 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 145:64910690c574 2251 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2252 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 145:64910690c574 2253 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 145:64910690c574 2254 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2255 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 145:64910690c574 2256 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 145:64910690c574 2257 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2258 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 145:64910690c574 2259 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 145:64910690c574 2260 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2261 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 145:64910690c574 2262 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 145:64910690c574 2263 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2264 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 145:64910690c574 2265 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 145:64910690c574 2266 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2267 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 145:64910690c574 2268 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 145:64910690c574 2269 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2270 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 145:64910690c574 2271 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 145:64910690c574 2272 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2273 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 145:64910690c574 2274 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 145:64910690c574 2275 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2276 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 145:64910690c574 2277 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 145:64910690c574 2278 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2279 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 145:64910690c574 2280 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 145:64910690c574 2281 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2282 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 145:64910690c574 2283 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 145:64910690c574 2284 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2285 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 145:64910690c574 2286 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 145:64910690c574 2287 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2288 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 145:64910690c574 2289 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 145:64910690c574 2290 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2291 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 145:64910690c574 2292 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 145:64910690c574 2293 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2294 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 145:64910690c574 2295 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 145:64910690c574 2296 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2297 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 128:9bcdf88f62b0 2298
<> 128:9bcdf88f62b0 2299 /******************************************************************************/
<> 128:9bcdf88f62b0 2300 /* */
<> 128:9bcdf88f62b0 2301 /* FLASH */
<> 128:9bcdf88f62b0 2302 /* */
<> 128:9bcdf88f62b0 2303 /******************************************************************************/
<> 128:9bcdf88f62b0 2304 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 145:64910690c574 2305 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 145:64910690c574 2306 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 2307 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 145:64910690c574 2308 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 145:64910690c574 2309 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 145:64910690c574 2310 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 145:64910690c574 2311 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 145:64910690c574 2312 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 145:64910690c574 2313 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 145:64910690c574 2314 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 145:64910690c574 2315 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 145:64910690c574 2316
AnnaBridge 145:64910690c574 2317 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 145:64910690c574 2318 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2319 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 145:64910690c574 2320 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 145:64910690c574 2321 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2322 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 145:64910690c574 2323 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 145:64910690c574 2324 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2325 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 145:64910690c574 2326 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 145:64910690c574 2327 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2328 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 145:64910690c574 2329 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 145:64910690c574 2330 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2331 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 145:64910690c574 2332 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 145:64910690c574 2333 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 145:64910690c574 2334 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 145:64910690c574 2335 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 145:64910690c574 2336 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 145:64910690c574 2337 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
<> 128:9bcdf88f62b0 2338
<> 128:9bcdf88f62b0 2339 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 145:64910690c574 2340 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 145:64910690c574 2341 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2342 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 145:64910690c574 2343 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 145:64910690c574 2344 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2345 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 145:64910690c574 2346 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 145:64910690c574 2347 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2348 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 145:64910690c574 2349 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 145:64910690c574 2350 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2351 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 145:64910690c574 2352 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 145:64910690c574 2353 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2354 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 145:64910690c574 2355 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 145:64910690c574 2356 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2357 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 145:64910690c574 2358 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 145:64910690c574 2359 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2360 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 145:64910690c574 2361 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 145:64910690c574 2362 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2363 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
<> 128:9bcdf88f62b0 2364
<> 128:9bcdf88f62b0 2365 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 145:64910690c574 2366 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 145:64910690c574 2367 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2368 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 145:64910690c574 2369 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 145:64910690c574 2370 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2371 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 145:64910690c574 2372 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 145:64910690c574 2373 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2374 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 145:64910690c574 2375 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 145:64910690c574 2376 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 145:64910690c574 2377 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 145:64910690c574 2378 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2379 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2380 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2381 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2382 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2383 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 145:64910690c574 2384 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 2385 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 145:64910690c574 2386 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2387 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2388 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 145:64910690c574 2389 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2390 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 145:64910690c574 2391 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 145:64910690c574 2392 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2393 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 145:64910690c574 2394 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 145:64910690c574 2395 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 2396 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
<> 128:9bcdf88f62b0 2397
<> 128:9bcdf88f62b0 2398 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 145:64910690c574 2399 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 145:64910690c574 2400 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2401 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 145:64910690c574 2402 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 145:64910690c574 2403 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2404 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 145:64910690c574 2405
AnnaBridge 145:64910690c574 2406 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 145:64910690c574 2407 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 145:64910690c574 2408 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 145:64910690c574 2409 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 2410 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 145:64910690c574 2411 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 145:64910690c574 2412 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2413 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 145:64910690c574 2414 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 145:64910690c574 2415 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2416 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 145:64910690c574 2417 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 145:64910690c574 2418 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2419 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 145:64910690c574 2420 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 145:64910690c574 2421 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 145:64910690c574 2422 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 145:64910690c574 2423 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2424 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2425 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2426 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2427 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2428 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2429 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2430 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2431 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 145:64910690c574 2432 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 145:64910690c574 2433 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 145:64910690c574 2434 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 145:64910690c574 2435 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 145:64910690c574 2436 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 145:64910690c574 2437 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 145:64910690c574 2438 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 145:64910690c574 2439 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 145:64910690c574 2440 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 145:64910690c574 2441 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 145:64910690c574 2442 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 145:64910690c574 2443 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 145:64910690c574 2444 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 145:64910690c574 2445 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 128:9bcdf88f62b0 2446
<> 128:9bcdf88f62b0 2447 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 145:64910690c574 2448 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 145:64910690c574 2449 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 145:64910690c574 2450 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 145:64910690c574 2451 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2452 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2453 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2454 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2455 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2456 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2457 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2458 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 2459 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2460 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 2461 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 2462 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2463
<> 128:9bcdf88f62b0 2464 /******************************************************************************/
<> 128:9bcdf88f62b0 2465 /* */
<> 128:9bcdf88f62b0 2466 /* General Purpose I/O */
<> 128:9bcdf88f62b0 2467 /* */
<> 128:9bcdf88f62b0 2468 /******************************************************************************/
<> 128:9bcdf88f62b0 2469 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 145:64910690c574 2470 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 145:64910690c574 2471 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 2472 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 145:64910690c574 2473 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2474 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2475 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 145:64910690c574 2476 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 2477 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 145:64910690c574 2478 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2479 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2480 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 145:64910690c574 2481 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 2482 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 145:64910690c574 2483 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2484 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2485 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 145:64910690c574 2486 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 2487 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 145:64910690c574 2488 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2489 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2490 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 145:64910690c574 2491 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 2492 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 145:64910690c574 2493 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2494 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2495 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 145:64910690c574 2496 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 2497 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 145:64910690c574 2498 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2499 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2500 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 145:64910690c574 2501 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 2502 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 145:64910690c574 2503 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2504 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2505 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 145:64910690c574 2506 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 2507 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 145:64910690c574 2508 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2509 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2510 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 145:64910690c574 2511 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 2512 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 145:64910690c574 2513 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2514 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2515 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 145:64910690c574 2516 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 2517 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 145:64910690c574 2518 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2519 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2520 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 145:64910690c574 2521 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 2522 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 145:64910690c574 2523 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2524 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2525 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 145:64910690c574 2526 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 145:64910690c574 2527 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 145:64910690c574 2528 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2529 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 2530 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 145:64910690c574 2531 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 2532 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 145:64910690c574 2533 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2534 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 2535 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 145:64910690c574 2536 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 145:64910690c574 2537 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 145:64910690c574 2538 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 2539 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 2540 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 145:64910690c574 2541 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 2542 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 145:64910690c574 2543 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 2544 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 2545 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 145:64910690c574 2546 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 145:64910690c574 2547 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 145:64910690c574 2548 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 2549 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 2550
AnnaBridge 145:64910690c574 2551 /* Legacy defines */
AnnaBridge 145:64910690c574 2552 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 145:64910690c574 2553 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 2554 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 145:64910690c574 2555 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2556 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2557 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 145:64910690c574 2558 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 2559 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 145:64910690c574 2560 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2561 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2562 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 145:64910690c574 2563 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 2564 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 145:64910690c574 2565 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2566 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2567 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 145:64910690c574 2568 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 2569 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 145:64910690c574 2570 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2571 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2572 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 145:64910690c574 2573 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 2574 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 145:64910690c574 2575 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2576 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2577 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 145:64910690c574 2578 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 2579 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 145:64910690c574 2580 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2581 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2582 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 145:64910690c574 2583 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 2584 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 145:64910690c574 2585 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2586 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2587 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 145:64910690c574 2588 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 2589 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 145:64910690c574 2590 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2591 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2592 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 145:64910690c574 2593 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 2594 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 145:64910690c574 2595 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2596 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2597 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 145:64910690c574 2598 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 2599 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 145:64910690c574 2600 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2601 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2602 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 145:64910690c574 2603 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 2604 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 145:64910690c574 2605 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2606 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2607 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 145:64910690c574 2608 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 145:64910690c574 2609 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 145:64910690c574 2610 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2611 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 2612 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 145:64910690c574 2613 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 2614 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 145:64910690c574 2615 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2616 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 2617 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 145:64910690c574 2618 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 145:64910690c574 2619 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 145:64910690c574 2620 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 2621 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 2622 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 145:64910690c574 2623 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 2624 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 145:64910690c574 2625 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 2626 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 2627 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 145:64910690c574 2628 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 145:64910690c574 2629 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 145:64910690c574 2630 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 2631 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2632
<> 128:9bcdf88f62b0 2633 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 145:64910690c574 2634 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 145:64910690c574 2635 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2636 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 145:64910690c574 2637 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 145:64910690c574 2638 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2639 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 145:64910690c574 2640 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 145:64910690c574 2641 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2642 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 145:64910690c574 2643 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 145:64910690c574 2644 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2645 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 145:64910690c574 2646 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 145:64910690c574 2647 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2648 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 145:64910690c574 2649 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 145:64910690c574 2650 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2651 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 145:64910690c574 2652 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 145:64910690c574 2653 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2654 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 145:64910690c574 2655 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 145:64910690c574 2656 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2657 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 145:64910690c574 2658 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 145:64910690c574 2659 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2660 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 145:64910690c574 2661 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 145:64910690c574 2662 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2663 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 145:64910690c574 2664 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 145:64910690c574 2665 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2666 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 145:64910690c574 2667 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 145:64910690c574 2668 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2669 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 145:64910690c574 2670 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 145:64910690c574 2671 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2672 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 145:64910690c574 2673 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 145:64910690c574 2674 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2675 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 145:64910690c574 2676 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 145:64910690c574 2677 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2678 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 145:64910690c574 2679 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 145:64910690c574 2680 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2681 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 145:64910690c574 2682
AnnaBridge 145:64910690c574 2683 /* Legacy defines */
AnnaBridge 145:64910690c574 2684 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 145:64910690c574 2685 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 145:64910690c574 2686 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 145:64910690c574 2687 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 145:64910690c574 2688 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 145:64910690c574 2689 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 145:64910690c574 2690 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 145:64910690c574 2691 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 145:64910690c574 2692 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 145:64910690c574 2693 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 145:64910690c574 2694 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 145:64910690c574 2695 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 145:64910690c574 2696 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 145:64910690c574 2697 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 145:64910690c574 2698 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 145:64910690c574 2699 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
<> 128:9bcdf88f62b0 2700
<> 128:9bcdf88f62b0 2701 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 145:64910690c574 2702 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 145:64910690c574 2703 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 2704 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 145:64910690c574 2705 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2706 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2707 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 145:64910690c574 2708 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 2709 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 145:64910690c574 2710 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2711 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2712 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 145:64910690c574 2713 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 2714 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 145:64910690c574 2715 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2716 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2717 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 145:64910690c574 2718 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 2719 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 145:64910690c574 2720 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2721 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2722 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 145:64910690c574 2723 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 2724 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 145:64910690c574 2725 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2726 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2727 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 145:64910690c574 2728 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 2729 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 145:64910690c574 2730 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2731 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2732 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 145:64910690c574 2733 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 2734 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 145:64910690c574 2735 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2736 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2737 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 145:64910690c574 2738 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 2739 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 145:64910690c574 2740 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2741 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2742 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 145:64910690c574 2743 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 2744 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 145:64910690c574 2745 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2746 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2747 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 145:64910690c574 2748 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 2749 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 145:64910690c574 2750 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2751 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2752 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 145:64910690c574 2753 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 2754 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 145:64910690c574 2755 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2756 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2757 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 145:64910690c574 2758 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 145:64910690c574 2759 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 145:64910690c574 2760 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2761 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 2762 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 145:64910690c574 2763 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 2764 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 145:64910690c574 2765 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2766 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 2767 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 145:64910690c574 2768 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 145:64910690c574 2769 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 145:64910690c574 2770 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 2771 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 2772 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 145:64910690c574 2773 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 2774 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 145:64910690c574 2775 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 2776 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 2777 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 145:64910690c574 2778 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 145:64910690c574 2779 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 145:64910690c574 2780 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 2781 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 2782
AnnaBridge 145:64910690c574 2783 /* Legacy defines */
AnnaBridge 145:64910690c574 2784 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 145:64910690c574 2785 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 145:64910690c574 2786 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 145:64910690c574 2787 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 145:64910690c574 2788 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 145:64910690c574 2789 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 145:64910690c574 2790 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 145:64910690c574 2791 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 145:64910690c574 2792 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 145:64910690c574 2793 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 145:64910690c574 2794 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 145:64910690c574 2795 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 145:64910690c574 2796 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 145:64910690c574 2797 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 145:64910690c574 2798 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 145:64910690c574 2799 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 145:64910690c574 2800 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 145:64910690c574 2801 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 145:64910690c574 2802 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 145:64910690c574 2803 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 145:64910690c574 2804 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 145:64910690c574 2805 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 145:64910690c574 2806 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 145:64910690c574 2807 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 145:64910690c574 2808 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 145:64910690c574 2809 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 145:64910690c574 2810 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 145:64910690c574 2811 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 145:64910690c574 2812 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 145:64910690c574 2813 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 145:64910690c574 2814 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 145:64910690c574 2815 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 145:64910690c574 2816 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 145:64910690c574 2817 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 145:64910690c574 2818 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 145:64910690c574 2819 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 145:64910690c574 2820 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 145:64910690c574 2821 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 145:64910690c574 2822 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 145:64910690c574 2823 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 145:64910690c574 2824 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 145:64910690c574 2825 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 145:64910690c574 2826 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 145:64910690c574 2827 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 145:64910690c574 2828 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 145:64910690c574 2829 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 145:64910690c574 2830 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 145:64910690c574 2831 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
<> 128:9bcdf88f62b0 2832
<> 128:9bcdf88f62b0 2833 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 145:64910690c574 2834 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 145:64910690c574 2835 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 2836 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 145:64910690c574 2837 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2838 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2839 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 145:64910690c574 2840 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 2841 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 145:64910690c574 2842 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2843 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2844 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 145:64910690c574 2845 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 2846 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 145:64910690c574 2847 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2848 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2849 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 145:64910690c574 2850 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 2851 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 145:64910690c574 2852 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2853 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2854 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 145:64910690c574 2855 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 2856 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 145:64910690c574 2857 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2858 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2859 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 145:64910690c574 2860 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 2861 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 145:64910690c574 2862 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2863 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 2864 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 145:64910690c574 2865 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 2866 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 145:64910690c574 2867 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 2868 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 2869 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 145:64910690c574 2870 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 2871 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 145:64910690c574 2872 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 2873 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 2874 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 145:64910690c574 2875 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 2876 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 145:64910690c574 2877 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 2878 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 2879 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 145:64910690c574 2880 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 2881 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 145:64910690c574 2882 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 2883 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 2884 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 145:64910690c574 2885 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 2886 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 145:64910690c574 2887 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 2888 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 2889 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 145:64910690c574 2890 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 145:64910690c574 2891 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 145:64910690c574 2892 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 2893 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 2894 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 145:64910690c574 2895 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 2896 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 145:64910690c574 2897 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 2898 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 2899 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 145:64910690c574 2900 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 145:64910690c574 2901 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 145:64910690c574 2902 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 2903 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 2904 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 145:64910690c574 2905 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 2906 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 145:64910690c574 2907 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 2908 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 2909 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 145:64910690c574 2910 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 145:64910690c574 2911 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 145:64910690c574 2912 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 2913 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 2914
AnnaBridge 145:64910690c574 2915 /* Legacy defines */
AnnaBridge 145:64910690c574 2916 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 145:64910690c574 2917 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 145:64910690c574 2918 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 145:64910690c574 2919 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 145:64910690c574 2920 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 145:64910690c574 2921 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 145:64910690c574 2922 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 145:64910690c574 2923 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 145:64910690c574 2924 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 145:64910690c574 2925 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 145:64910690c574 2926 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 145:64910690c574 2927 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 145:64910690c574 2928 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 145:64910690c574 2929 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 145:64910690c574 2930 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 145:64910690c574 2931 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 145:64910690c574 2932 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 145:64910690c574 2933 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 145:64910690c574 2934 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 145:64910690c574 2935 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 145:64910690c574 2936 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 145:64910690c574 2937 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 145:64910690c574 2938 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 145:64910690c574 2939 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 145:64910690c574 2940 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 145:64910690c574 2941 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 145:64910690c574 2942 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 145:64910690c574 2943 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 145:64910690c574 2944 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 145:64910690c574 2945 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 145:64910690c574 2946 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 145:64910690c574 2947 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 145:64910690c574 2948 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 145:64910690c574 2949 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 145:64910690c574 2950 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 145:64910690c574 2951 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 145:64910690c574 2952 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 145:64910690c574 2953 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 145:64910690c574 2954 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 145:64910690c574 2955 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 145:64910690c574 2956 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 145:64910690c574 2957 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 145:64910690c574 2958 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 145:64910690c574 2959 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 145:64910690c574 2960 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 145:64910690c574 2961 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 145:64910690c574 2962 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 145:64910690c574 2963 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
<> 128:9bcdf88f62b0 2964
<> 128:9bcdf88f62b0 2965 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 145:64910690c574 2966 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 145:64910690c574 2967 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 2968 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 145:64910690c574 2969 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 145:64910690c574 2970 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 2971 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 145:64910690c574 2972 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 145:64910690c574 2973 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 2974 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 145:64910690c574 2975 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 145:64910690c574 2976 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 2977 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 145:64910690c574 2978 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 145:64910690c574 2979 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 2980 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 145:64910690c574 2981 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 145:64910690c574 2982 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 2983 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 145:64910690c574 2984 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 145:64910690c574 2985 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 2986 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 145:64910690c574 2987 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 145:64910690c574 2988 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 2989 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 145:64910690c574 2990 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 145:64910690c574 2991 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 2992 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 145:64910690c574 2993 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 145:64910690c574 2994 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 2995 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 145:64910690c574 2996 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 145:64910690c574 2997 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 2998 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 145:64910690c574 2999 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 145:64910690c574 3000 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3001 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 145:64910690c574 3002 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 145:64910690c574 3003 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3004 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 145:64910690c574 3005 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 145:64910690c574 3006 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3007 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 145:64910690c574 3008 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 145:64910690c574 3009 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3010 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 145:64910690c574 3011 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 145:64910690c574 3012 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3013 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 145:64910690c574 3014
AnnaBridge 145:64910690c574 3015 /* Legacy defines */
AnnaBridge 145:64910690c574 3016 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 145:64910690c574 3017 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 145:64910690c574 3018 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 145:64910690c574 3019 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 145:64910690c574 3020 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 145:64910690c574 3021 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 145:64910690c574 3022 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 145:64910690c574 3023 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 145:64910690c574 3024 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 145:64910690c574 3025 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 145:64910690c574 3026 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 145:64910690c574 3027 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 145:64910690c574 3028 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 145:64910690c574 3029 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 145:64910690c574 3030 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 145:64910690c574 3031 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
<> 128:9bcdf88f62b0 3032
<> 128:9bcdf88f62b0 3033 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 145:64910690c574 3034 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 145:64910690c574 3035 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3036 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 145:64910690c574 3037 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 145:64910690c574 3038 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3039 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 145:64910690c574 3040 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 145:64910690c574 3041 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3042 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 145:64910690c574 3043 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 145:64910690c574 3044 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3045 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 145:64910690c574 3046 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 145:64910690c574 3047 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3048 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 145:64910690c574 3049 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 145:64910690c574 3050 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3051 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 145:64910690c574 3052 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 145:64910690c574 3053 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3054 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 145:64910690c574 3055 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 145:64910690c574 3056 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3057 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 145:64910690c574 3058 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 145:64910690c574 3059 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3060 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 145:64910690c574 3061 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 145:64910690c574 3062 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3063 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 145:64910690c574 3064 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 145:64910690c574 3065 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3066 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 145:64910690c574 3067 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 145:64910690c574 3068 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3069 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 145:64910690c574 3070 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 145:64910690c574 3071 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3072 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 145:64910690c574 3073 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 145:64910690c574 3074 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3075 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 145:64910690c574 3076 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 145:64910690c574 3077 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3078 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 145:64910690c574 3079 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 145:64910690c574 3080 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3081 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 145:64910690c574 3082 /* Legacy defines */
AnnaBridge 145:64910690c574 3083 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 145:64910690c574 3084 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 145:64910690c574 3085 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 145:64910690c574 3086 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 145:64910690c574 3087 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 145:64910690c574 3088 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 145:64910690c574 3089 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 145:64910690c574 3090 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 145:64910690c574 3091 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 145:64910690c574 3092 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 145:64910690c574 3093 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 145:64910690c574 3094 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 145:64910690c574 3095 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 145:64910690c574 3096 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 145:64910690c574 3097 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 145:64910690c574 3098 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
<> 128:9bcdf88f62b0 3099
<> 128:9bcdf88f62b0 3100 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 145:64910690c574 3101 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 145:64910690c574 3102 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3103 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 145:64910690c574 3104 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 145:64910690c574 3105 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3106 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 145:64910690c574 3107 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 145:64910690c574 3108 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3109 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 145:64910690c574 3110 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 145:64910690c574 3111 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3112 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 145:64910690c574 3113 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 145:64910690c574 3114 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3115 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 145:64910690c574 3116 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 145:64910690c574 3117 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3118 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 145:64910690c574 3119 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 145:64910690c574 3120 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3121 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 145:64910690c574 3122 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 145:64910690c574 3123 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3124 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 145:64910690c574 3125 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 145:64910690c574 3126 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3127 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 145:64910690c574 3128 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 145:64910690c574 3129 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3130 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 145:64910690c574 3131 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 145:64910690c574 3132 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3133 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 145:64910690c574 3134 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 145:64910690c574 3135 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3136 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 145:64910690c574 3137 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 145:64910690c574 3138 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3139 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 145:64910690c574 3140 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 145:64910690c574 3141 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3142 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 145:64910690c574 3143 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 145:64910690c574 3144 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3145 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 145:64910690c574 3146 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 145:64910690c574 3147 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3148 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 145:64910690c574 3149 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 145:64910690c574 3150 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3151 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 145:64910690c574 3152 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 145:64910690c574 3153 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 3154 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 145:64910690c574 3155 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 145:64910690c574 3156 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 3157 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 145:64910690c574 3158 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 145:64910690c574 3159 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 3160 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 145:64910690c574 3161 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 145:64910690c574 3162 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 3163 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 145:64910690c574 3164 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 145:64910690c574 3165 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 3166 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 145:64910690c574 3167 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 145:64910690c574 3168 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 3169 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 145:64910690c574 3170 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 145:64910690c574 3171 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 3172 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 145:64910690c574 3173 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 145:64910690c574 3174 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 3175 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 145:64910690c574 3176 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 145:64910690c574 3177 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 3178 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 145:64910690c574 3179 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 145:64910690c574 3180 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 3181 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 145:64910690c574 3182 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 145:64910690c574 3183 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 3184 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 145:64910690c574 3185 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 145:64910690c574 3186 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 3187 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 145:64910690c574 3188 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 145:64910690c574 3189 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 3190 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 145:64910690c574 3191 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 145:64910690c574 3192 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 3193 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 145:64910690c574 3194 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 145:64910690c574 3195 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 3196 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 145:64910690c574 3197
AnnaBridge 145:64910690c574 3198 /* Legacy defines */
AnnaBridge 145:64910690c574 3199 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 145:64910690c574 3200 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 145:64910690c574 3201 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 145:64910690c574 3202 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 145:64910690c574 3203 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 145:64910690c574 3204 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 145:64910690c574 3205 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 145:64910690c574 3206 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 145:64910690c574 3207 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 145:64910690c574 3208 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 145:64910690c574 3209 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 145:64910690c574 3210 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 145:64910690c574 3211 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 145:64910690c574 3212 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 145:64910690c574 3213 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 145:64910690c574 3214 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 145:64910690c574 3215 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 145:64910690c574 3216 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 145:64910690c574 3217 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 145:64910690c574 3218 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 145:64910690c574 3219 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 145:64910690c574 3220 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 145:64910690c574 3221 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 145:64910690c574 3222 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 145:64910690c574 3223 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 145:64910690c574 3224 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 145:64910690c574 3225 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 145:64910690c574 3226 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 145:64910690c574 3227 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 145:64910690c574 3228 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 145:64910690c574 3229 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 145:64910690c574 3230 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 145:64910690c574 3231 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 145:64910690c574 3232 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 145:64910690c574 3233 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3234 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 145:64910690c574 3235 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 145:64910690c574 3236 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3237 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 145:64910690c574 3238 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 145:64910690c574 3239 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3240 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 145:64910690c574 3241 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 145:64910690c574 3242 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3243 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 145:64910690c574 3244 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 145:64910690c574 3245 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3246 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 145:64910690c574 3247 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 145:64910690c574 3248 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3249 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 145:64910690c574 3250 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 145:64910690c574 3251 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3252 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 145:64910690c574 3253 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 145:64910690c574 3254 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3255 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 145:64910690c574 3256 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 145:64910690c574 3257 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3258 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 145:64910690c574 3259 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 145:64910690c574 3260 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3261 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 145:64910690c574 3262 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 145:64910690c574 3263 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3264 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 145:64910690c574 3265 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 145:64910690c574 3266 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3267 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 145:64910690c574 3268 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 145:64910690c574 3269 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3270 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 145:64910690c574 3271 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 145:64910690c574 3272 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3273 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 145:64910690c574 3274 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 145:64910690c574 3275 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3276 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 145:64910690c574 3277 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 145:64910690c574 3278 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3279 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 145:64910690c574 3280 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 145:64910690c574 3281 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3282 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 145:64910690c574 3283 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 145:64910690c574 3284 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 145:64910690c574 3285 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 3286 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 145:64910690c574 3287 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3288 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3289 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3290 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3291 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 145:64910690c574 3292 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 3293 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 145:64910690c574 3294 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3295 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3296 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3297 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3298 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 145:64910690c574 3299 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 3300 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 145:64910690c574 3301 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3302 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3303 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3304 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3305 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 145:64910690c574 3306 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 3307 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 145:64910690c574 3308 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3309 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3310 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3311 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3312 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 145:64910690c574 3313 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 3314 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 145:64910690c574 3315 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3316 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 3317 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 3318 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 3319 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 145:64910690c574 3320 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 145:64910690c574 3321 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 145:64910690c574 3322 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 3323 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 3324 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 3325 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 3326 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 145:64910690c574 3327 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 3328 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 145:64910690c574 3329 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 3330 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 3331 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 3332 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 3333 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 145:64910690c574 3334 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 145:64910690c574 3335 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 145:64910690c574 3336 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 3337 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 3338 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 3339 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 3340
AnnaBridge 145:64910690c574 3341 /* Legacy defines */
AnnaBridge 145:64910690c574 3342 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 145:64910690c574 3343 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 145:64910690c574 3344 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 145:64910690c574 3345 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 145:64910690c574 3346 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 145:64910690c574 3347 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 145:64910690c574 3348 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 145:64910690c574 3349 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 145:64910690c574 3350 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 145:64910690c574 3351 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 145:64910690c574 3352 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 145:64910690c574 3353 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 145:64910690c574 3354 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 145:64910690c574 3355 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 145:64910690c574 3356 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 145:64910690c574 3357 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 145:64910690c574 3358 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 145:64910690c574 3359 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 145:64910690c574 3360 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 145:64910690c574 3361 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 145:64910690c574 3362 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 145:64910690c574 3363 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 145:64910690c574 3364 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 145:64910690c574 3365 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 145:64910690c574 3366 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 145:64910690c574 3367 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 145:64910690c574 3368 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 145:64910690c574 3369 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 145:64910690c574 3370 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 145:64910690c574 3371 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 145:64910690c574 3372 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 145:64910690c574 3373 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 145:64910690c574 3374 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 145:64910690c574 3375 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 145:64910690c574 3376 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 145:64910690c574 3377 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 145:64910690c574 3378 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 145:64910690c574 3379 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 145:64910690c574 3380 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 145:64910690c574 3381 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 145:64910690c574 3382
AnnaBridge 145:64910690c574 3383 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 145:64910690c574 3384 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 145:64910690c574 3385 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 3386 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 145:64910690c574 3387 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3388 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3389 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3390 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3391 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 145:64910690c574 3392 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 3393 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 145:64910690c574 3394 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3395 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3396 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3397 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3398 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 145:64910690c574 3399 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 3400 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 145:64910690c574 3401 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3402 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3403 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3404 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3405 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 145:64910690c574 3406 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 3407 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 145:64910690c574 3408 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3409 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3410 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3411 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3412 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 145:64910690c574 3413 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 3414 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 145:64910690c574 3415 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3416 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 3417 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 3418 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 3419 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 145:64910690c574 3420 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 145:64910690c574 3421 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 145:64910690c574 3422 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 3423 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 3424 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 3425 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 3426 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 145:64910690c574 3427 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 3428 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 145:64910690c574 3429 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 3430 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 3431 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 3432 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 3433 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 145:64910690c574 3434 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 145:64910690c574 3435 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 145:64910690c574 3436 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 3437 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 3438 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 3439 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 3440
AnnaBridge 145:64910690c574 3441 /* Legacy defines */
AnnaBridge 145:64910690c574 3442 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 145:64910690c574 3443 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 145:64910690c574 3444 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 145:64910690c574 3445 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 145:64910690c574 3446 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 145:64910690c574 3447 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 145:64910690c574 3448 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 145:64910690c574 3449 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 145:64910690c574 3450 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 145:64910690c574 3451 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 145:64910690c574 3452 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 145:64910690c574 3453 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 145:64910690c574 3454 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 145:64910690c574 3455 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 145:64910690c574 3456 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 145:64910690c574 3457 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 145:64910690c574 3458 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 145:64910690c574 3459 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 145:64910690c574 3460 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 145:64910690c574 3461 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 145:64910690c574 3462 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 145:64910690c574 3463 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 145:64910690c574 3464 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 145:64910690c574 3465 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 145:64910690c574 3466 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 145:64910690c574 3467 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 145:64910690c574 3468 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 145:64910690c574 3469 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 145:64910690c574 3470 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 145:64910690c574 3471 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 145:64910690c574 3472 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 145:64910690c574 3473 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 145:64910690c574 3474 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 145:64910690c574 3475 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 145:64910690c574 3476 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 145:64910690c574 3477 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 145:64910690c574 3478 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 145:64910690c574 3479 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 145:64910690c574 3480 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 145:64910690c574 3481 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 145:64910690c574 3482
AnnaBridge 145:64910690c574 3483 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 145:64910690c574 3484 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 145:64910690c574 3485 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3486 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 145:64910690c574 3487 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 145:64910690c574 3488 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3489 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 145:64910690c574 3490 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 145:64910690c574 3491 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3492 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 145:64910690c574 3493 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 145:64910690c574 3494 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3495 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 145:64910690c574 3496 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 145:64910690c574 3497 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3498 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 145:64910690c574 3499 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 145:64910690c574 3500 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3501 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 145:64910690c574 3502 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 145:64910690c574 3503 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3504 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 145:64910690c574 3505 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 145:64910690c574 3506 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3507 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 145:64910690c574 3508 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 145:64910690c574 3509 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3510 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 145:64910690c574 3511 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 145:64910690c574 3512 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3513 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 145:64910690c574 3514 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 145:64910690c574 3515 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3516 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 145:64910690c574 3517 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 145:64910690c574 3518 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3519 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 145:64910690c574 3520 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 145:64910690c574 3521 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3522 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 145:64910690c574 3523 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 145:64910690c574 3524 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3525 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 145:64910690c574 3526 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 145:64910690c574 3527 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3528 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 145:64910690c574 3529 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 145:64910690c574 3530 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3531 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 145:64910690c574 3532
<> 128:9bcdf88f62b0 3533
<> 128:9bcdf88f62b0 3534 /******************************************************************************/
<> 128:9bcdf88f62b0 3535 /* */
<> 128:9bcdf88f62b0 3536 /* Inter-integrated Circuit Interface */
<> 128:9bcdf88f62b0 3537 /* */
<> 128:9bcdf88f62b0 3538 /******************************************************************************/
<> 128:9bcdf88f62b0 3539 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 145:64910690c574 3540 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 145:64910690c574 3541 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3542 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 145:64910690c574 3543 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 145:64910690c574 3544 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3545 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 145:64910690c574 3546 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 145:64910690c574 3547 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3548 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 145:64910690c574 3549 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 145:64910690c574 3550 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3551 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 145:64910690c574 3552 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 145:64910690c574 3553 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3554 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 145:64910690c574 3555 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 145:64910690c574 3556 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3557 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 145:64910690c574 3558 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 145:64910690c574 3559 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3560 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 145:64910690c574 3561 #define I2C_CR1_START_Pos (8U)
AnnaBridge 145:64910690c574 3562 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3563 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 145:64910690c574 3564 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 145:64910690c574 3565 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3566 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 145:64910690c574 3567 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 145:64910690c574 3568 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3569 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 145:64910690c574 3570 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 145:64910690c574 3571 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3572 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 145:64910690c574 3573 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 145:64910690c574 3574 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3575 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 145:64910690c574 3576 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 145:64910690c574 3577 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3578 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 145:64910690c574 3579 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 145:64910690c574 3580 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3581 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
<> 128:9bcdf88f62b0 3582
<> 128:9bcdf88f62b0 3583 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 145:64910690c574 3584 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 145:64910690c574 3585 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 145:64910690c574 3586 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 145:64910690c574 3587 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3588 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3589 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3590 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3591 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3592 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3593
AnnaBridge 145:64910690c574 3594 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 145:64910690c574 3595 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3596 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 145:64910690c574 3597 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 145:64910690c574 3598 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3599 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 145:64910690c574 3600 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 145:64910690c574 3601 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3602 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 145:64910690c574 3603 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 145:64910690c574 3604 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3605 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 145:64910690c574 3606 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 145:64910690c574 3607 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3608 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
<> 128:9bcdf88f62b0 3609
<> 128:9bcdf88f62b0 3610 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 145:64910690c574 3611 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 145:64910690c574 3612 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 145:64910690c574 3613
AnnaBridge 145:64910690c574 3614 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 145:64910690c574 3615 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3616 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 145:64910690c574 3617 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 145:64910690c574 3618 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3619 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 145:64910690c574 3620 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 145:64910690c574 3621 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3622 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 145:64910690c574 3623 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 145:64910690c574 3624 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3625 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 145:64910690c574 3626 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 145:64910690c574 3627 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3628 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 145:64910690c574 3629 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 145:64910690c574 3630 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3631 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 145:64910690c574 3632 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 145:64910690c574 3633 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3634 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 145:64910690c574 3635 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 145:64910690c574 3636 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3637 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 145:64910690c574 3638 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 145:64910690c574 3639 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3640 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 145:64910690c574 3641 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 145:64910690c574 3642 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3643 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 145:64910690c574 3644
AnnaBridge 145:64910690c574 3645 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 145:64910690c574 3646 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3647 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
<> 128:9bcdf88f62b0 3648
<> 128:9bcdf88f62b0 3649 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 145:64910690c574 3650 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 145:64910690c574 3651 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3652 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 145:64910690c574 3653 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 145:64910690c574 3654 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 145:64910690c574 3655 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
<> 128:9bcdf88f62b0 3656
<> 128:9bcdf88f62b0 3657 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 145:64910690c574 3658 #define I2C_DR_DR_Pos (0U)
AnnaBridge 145:64910690c574 3659 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 3660 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
<> 128:9bcdf88f62b0 3661
<> 128:9bcdf88f62b0 3662 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 145:64910690c574 3663 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 145:64910690c574 3664 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3665 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 145:64910690c574 3666 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 145:64910690c574 3667 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3668 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 145:64910690c574 3669 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 145:64910690c574 3670 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3671 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 145:64910690c574 3672 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 145:64910690c574 3673 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3674 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 145:64910690c574 3675 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 145:64910690c574 3676 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3677 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 145:64910690c574 3678 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 145:64910690c574 3679 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3680 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 145:64910690c574 3681 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 145:64910690c574 3682 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3683 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 145:64910690c574 3684 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 145:64910690c574 3685 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3686 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 145:64910690c574 3687 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 145:64910690c574 3688 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3689 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 145:64910690c574 3690 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 145:64910690c574 3691 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3692 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 145:64910690c574 3693 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 145:64910690c574 3694 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3695 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 145:64910690c574 3696 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 145:64910690c574 3697 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3698 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 145:64910690c574 3699 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 145:64910690c574 3700 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3701 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 145:64910690c574 3702 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 145:64910690c574 3703 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3704 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
<> 128:9bcdf88f62b0 3705
<> 128:9bcdf88f62b0 3706 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 145:64910690c574 3707 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 145:64910690c574 3708 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3709 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 145:64910690c574 3710 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 145:64910690c574 3711 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3712 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 145:64910690c574 3713 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 145:64910690c574 3714 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3715 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 145:64910690c574 3716 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 145:64910690c574 3717 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3718 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 145:64910690c574 3719 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 145:64910690c574 3720 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3721 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 145:64910690c574 3722 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 145:64910690c574 3723 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3724 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 145:64910690c574 3725 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 145:64910690c574 3726 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3727 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 145:64910690c574 3728 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 145:64910690c574 3729 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 145:64910690c574 3730 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
<> 128:9bcdf88f62b0 3731
<> 128:9bcdf88f62b0 3732 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 145:64910690c574 3733 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 145:64910690c574 3734 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 3735 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 145:64910690c574 3736 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 145:64910690c574 3737 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3738 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 145:64910690c574 3739 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 145:64910690c574 3740 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3741 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
<> 128:9bcdf88f62b0 3742
<> 128:9bcdf88f62b0 3743 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 145:64910690c574 3744 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 145:64910690c574 3745 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 145:64910690c574 3746 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 128:9bcdf88f62b0 3747
<> 128:9bcdf88f62b0 3748 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 145:64910690c574 3749 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 145:64910690c574 3750 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 3751 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 145:64910690c574 3752 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 145:64910690c574 3753 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3754 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
<> 128:9bcdf88f62b0 3755
<> 128:9bcdf88f62b0 3756 /******************************************************************************/
<> 128:9bcdf88f62b0 3757 /* */
<> 128:9bcdf88f62b0 3758 /* Independent WATCHDOG */
<> 128:9bcdf88f62b0 3759 /* */
<> 128:9bcdf88f62b0 3760 /******************************************************************************/
<> 128:9bcdf88f62b0 3761 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 145:64910690c574 3762 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 145:64910690c574 3763 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 3764 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
<> 128:9bcdf88f62b0 3765
<> 128:9bcdf88f62b0 3766 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 145:64910690c574 3767 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 145:64910690c574 3768 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 3769 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 145:64910690c574 3770 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 145:64910690c574 3771 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 145:64910690c574 3772 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
<> 128:9bcdf88f62b0 3773
<> 128:9bcdf88f62b0 3774 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 145:64910690c574 3775 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 145:64910690c574 3776 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 3777 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
<> 128:9bcdf88f62b0 3778
<> 128:9bcdf88f62b0 3779 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 145:64910690c574 3780 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 145:64910690c574 3781 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3782 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 145:64910690c574 3783 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 145:64910690c574 3784 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3785 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 145:64910690c574 3786
<> 128:9bcdf88f62b0 3787
<> 128:9bcdf88f62b0 3788
<> 128:9bcdf88f62b0 3789 /******************************************************************************/
<> 128:9bcdf88f62b0 3790 /* */
<> 128:9bcdf88f62b0 3791 /* Power Control */
<> 128:9bcdf88f62b0 3792 /* */
<> 128:9bcdf88f62b0 3793 /******************************************************************************/
<> 128:9bcdf88f62b0 3794 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 145:64910690c574 3795 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 145:64910690c574 3796 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3797 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 145:64910690c574 3798 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 145:64910690c574 3799 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3800 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 145:64910690c574 3801 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 145:64910690c574 3802 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3803 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 145:64910690c574 3804 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 145:64910690c574 3805 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3806 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 145:64910690c574 3807 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 145:64910690c574 3808 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3809 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 145:64910690c574 3810
AnnaBridge 145:64910690c574 3811 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 145:64910690c574 3812 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 145:64910690c574 3813 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 145:64910690c574 3814 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3815 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3816 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3817
<> 128:9bcdf88f62b0 3818 /*!< PVD level configuration */
AnnaBridge 145:64910690c574 3819 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 145:64910690c574 3820 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 145:64910690c574 3821 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 145:64910690c574 3822 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 145:64910690c574 3823 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 145:64910690c574 3824 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 145:64910690c574 3825 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 145:64910690c574 3826 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 145:64910690c574 3827 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 145:64910690c574 3828 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3829 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 145:64910690c574 3830 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 145:64910690c574 3831 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3832 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 145:64910690c574 3833 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 145:64910690c574 3834 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3835 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 145:64910690c574 3836 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 145:64910690c574 3837 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3838 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 145:64910690c574 3839 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 145:64910690c574 3840 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3841 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 145:64910690c574 3842 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 145:64910690c574 3843 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 3844 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 145:64910690c574 3845 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 145:64910690c574 3846 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
<> 128:9bcdf88f62b0 3847
<> 128:9bcdf88f62b0 3848 /* Legacy define */
<> 128:9bcdf88f62b0 3849 #define PWR_CR_PMODE PWR_CR_VOS
<> 128:9bcdf88f62b0 3850
<> 128:9bcdf88f62b0 3851 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 145:64910690c574 3852 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 145:64910690c574 3853 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3854 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 145:64910690c574 3855 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 145:64910690c574 3856 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3857 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 145:64910690c574 3858 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 145:64910690c574 3859 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3860 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 145:64910690c574 3861 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 145:64910690c574 3862 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3863 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 145:64910690c574 3864 #define PWR_CSR_EWUP_Pos (8U)
AnnaBridge 145:64910690c574 3865 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3866 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
AnnaBridge 145:64910690c574 3867 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 145:64910690c574 3868 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3869 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 145:64910690c574 3870 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 145:64910690c574 3871 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3872 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
<> 128:9bcdf88f62b0 3873
<> 128:9bcdf88f62b0 3874 /* Legacy define */
<> 128:9bcdf88f62b0 3875 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
<> 128:9bcdf88f62b0 3876
<> 128:9bcdf88f62b0 3877 /******************************************************************************/
<> 128:9bcdf88f62b0 3878 /* */
<> 128:9bcdf88f62b0 3879 /* Reset and Clock Control */
<> 128:9bcdf88f62b0 3880 /* */
<> 128:9bcdf88f62b0 3881 /******************************************************************************/
<> 128:9bcdf88f62b0 3882 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 145:64910690c574 3883 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 145:64910690c574 3884 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3885 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 145:64910690c574 3886 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 145:64910690c574 3887 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3888 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 145:64910690c574 3889
AnnaBridge 145:64910690c574 3890 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 145:64910690c574 3891 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 145:64910690c574 3892 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 145:64910690c574 3893 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3894 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3895 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3896 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3897 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3898
AnnaBridge 145:64910690c574 3899 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 145:64910690c574 3900 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 145:64910690c574 3901 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 145:64910690c574 3902 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3903 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3904 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3905 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3906 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3907 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3908 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3909 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 3910
AnnaBridge 145:64910690c574 3911 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 145:64910690c574 3912 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3913 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 145:64910690c574 3914 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 145:64910690c574 3915 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 3916 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 145:64910690c574 3917 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 145:64910690c574 3918 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 3919 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 145:64910690c574 3920 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 145:64910690c574 3921 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 3922 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 145:64910690c574 3923 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 145:64910690c574 3924 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 3925 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 145:64910690c574 3926 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 145:64910690c574 3927 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 3928 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 145:64910690c574 3929 /*
AnnaBridge 145:64910690c574 3930 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 145:64910690c574 3931 */
AnnaBridge 145:64910690c574 3932 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 145:64910690c574 3933
AnnaBridge 145:64910690c574 3934 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 145:64910690c574 3935 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 3936 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 145:64910690c574 3937 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 145:64910690c574 3938 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 3939 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
<> 128:9bcdf88f62b0 3940
<> 128:9bcdf88f62b0 3941 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 145:64910690c574 3942 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 145:64910690c574 3943 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 145:64910690c574 3944 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 145:64910690c574 3945 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3946 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3947 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 3948 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 3949 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 3950 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 3951
AnnaBridge 145:64910690c574 3952 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 145:64910690c574 3953 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 145:64910690c574 3954 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 145:64910690c574 3955 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 3956 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 3957 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 3958 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 3959 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 3960 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 3961 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 3962 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 3963 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 3964
AnnaBridge 145:64910690c574 3965 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 145:64910690c574 3966 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 145:64910690c574 3967 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 145:64910690c574 3968 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 3969 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 3970
AnnaBridge 145:64910690c574 3971 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 145:64910690c574 3972 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 3973 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 145:64910690c574 3974 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 145:64910690c574 3975 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 3976 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 145:64910690c574 3977 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 145:64910690c574 3978
AnnaBridge 145:64910690c574 3979 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 145:64910690c574 3980 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 3981 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 145:64910690c574 3982 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 3983 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 3984 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 3985 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 3986
<> 128:9bcdf88f62b0 3987
<> 128:9bcdf88f62b0 3988 /******************** Bit definition for RCC_CFGR register ******************/
<> 128:9bcdf88f62b0 3989 /*!< SW configuration */
AnnaBridge 145:64910690c574 3990 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 145:64910690c574 3991 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 3992 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 145:64910690c574 3993 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 3994 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 3995
AnnaBridge 145:64910690c574 3996 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 145:64910690c574 3997 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 145:64910690c574 3998 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 128:9bcdf88f62b0 3999
<> 128:9bcdf88f62b0 4000 /*!< SWS configuration */
AnnaBridge 145:64910690c574 4001 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 145:64910690c574 4002 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 4003 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 145:64910690c574 4004 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4005 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4006
AnnaBridge 145:64910690c574 4007 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 145:64910690c574 4008 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 145:64910690c574 4009 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 128:9bcdf88f62b0 4010
<> 128:9bcdf88f62b0 4011 /*!< HPRE configuration */
AnnaBridge 145:64910690c574 4012 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 145:64910690c574 4013 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 4014 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 145:64910690c574 4015 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4016 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4017 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4018 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4019
AnnaBridge 145:64910690c574 4020 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 145:64910690c574 4021 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 145:64910690c574 4022 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 145:64910690c574 4023 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 145:64910690c574 4024 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 145:64910690c574 4025 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 145:64910690c574 4026 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 145:64910690c574 4027 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 145:64910690c574 4028 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 128:9bcdf88f62b0 4029
<> 128:9bcdf88f62b0 4030 /*!< PPRE1 configuration */
AnnaBridge 145:64910690c574 4031 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 145:64910690c574 4032 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 145:64910690c574 4033 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 145:64910690c574 4034 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4035 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4036 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4037
AnnaBridge 145:64910690c574 4038 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 145:64910690c574 4039 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 145:64910690c574 4040 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 145:64910690c574 4041 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 145:64910690c574 4042 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 4043
<> 128:9bcdf88f62b0 4044 /*!< PPRE2 configuration */
AnnaBridge 145:64910690c574 4045 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 145:64910690c574 4046 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 145:64910690c574 4047 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 145:64910690c574 4048 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4049 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4050 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4051
AnnaBridge 145:64910690c574 4052 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 145:64910690c574 4053 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 145:64910690c574 4054 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 145:64910690c574 4055 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 145:64910690c574 4056 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 4057
<> 128:9bcdf88f62b0 4058 /*!< RTCPRE configuration */
AnnaBridge 145:64910690c574 4059 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 145:64910690c574 4060 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 145:64910690c574 4061 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 145:64910690c574 4062 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4063 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4064 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4065 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4066 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4067
<> 128:9bcdf88f62b0 4068 /*!< MCO1 configuration */
AnnaBridge 145:64910690c574 4069 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 145:64910690c574 4070 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 145:64910690c574 4071 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 145:64910690c574 4072 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4073 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4074
AnnaBridge 145:64910690c574 4075 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 145:64910690c574 4076 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4077 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 145:64910690c574 4078
AnnaBridge 145:64910690c574 4079 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 145:64910690c574 4080 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 145:64910690c574 4081 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 145:64910690c574 4082 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 4083 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 4084 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 4085
AnnaBridge 145:64910690c574 4086 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 145:64910690c574 4087 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 145:64910690c574 4088 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 145:64910690c574 4089 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 4090 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4091 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 4092
AnnaBridge 145:64910690c574 4093 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 145:64910690c574 4094 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 145:64910690c574 4095 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 145:64910690c574 4096 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 4097 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4098
<> 128:9bcdf88f62b0 4099 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 145:64910690c574 4100 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 145:64910690c574 4101 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4102 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 145:64910690c574 4103 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 145:64910690c574 4104 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4105 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 145:64910690c574 4106 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 145:64910690c574 4107 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4108 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 145:64910690c574 4109 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 145:64910690c574 4110 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4111 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 145:64910690c574 4112 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 145:64910690c574 4113 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4114 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 145:64910690c574 4115 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 145:64910690c574 4116 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4117 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 145:64910690c574 4118
AnnaBridge 145:64910690c574 4119 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 145:64910690c574 4120 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4121 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 145:64910690c574 4122 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 145:64910690c574 4123 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4124 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 145:64910690c574 4125 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 145:64910690c574 4126 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4127 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 145:64910690c574 4128 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 145:64910690c574 4129 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4130 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 145:64910690c574 4131 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 145:64910690c574 4132 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4133 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 145:64910690c574 4134 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 145:64910690c574 4135 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4136 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 145:64910690c574 4137 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 145:64910690c574 4138 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4139 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 145:64910690c574 4140
AnnaBridge 145:64910690c574 4141 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 145:64910690c574 4142 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4143 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 145:64910690c574 4144 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 145:64910690c574 4145 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4146 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 145:64910690c574 4147 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 145:64910690c574 4148 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4149 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 145:64910690c574 4150 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 145:64910690c574 4151 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4152 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 145:64910690c574 4153 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 145:64910690c574 4154 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4155 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 145:64910690c574 4156 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 145:64910690c574 4157 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4158 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 145:64910690c574 4159
AnnaBridge 145:64910690c574 4160 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 145:64910690c574 4161 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4162 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
<> 128:9bcdf88f62b0 4163
<> 128:9bcdf88f62b0 4164 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 145:64910690c574 4165 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 145:64910690c574 4166 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4167 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 145:64910690c574 4168 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 145:64910690c574 4169 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4170 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 145:64910690c574 4171 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 145:64910690c574 4172 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4173 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 145:64910690c574 4174 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 145:64910690c574 4175 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4176 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 145:64910690c574 4177 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 145:64910690c574 4178 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4179 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 145:64910690c574 4180 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 145:64910690c574 4181 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4182 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 145:64910690c574 4183 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 145:64910690c574 4184 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4185 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 145:64910690c574 4186 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 145:64910690c574 4187 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4188 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 145:64910690c574 4189 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 145:64910690c574 4190 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4191 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
<> 128:9bcdf88f62b0 4192
<> 128:9bcdf88f62b0 4193 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 145:64910690c574 4194 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 145:64910690c574 4195 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4196 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
<> 128:9bcdf88f62b0 4197 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 128:9bcdf88f62b0 4198
AnnaBridge 145:64910690c574 4199
<> 128:9bcdf88f62b0 4200 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 145:64910690c574 4201 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 145:64910690c574 4202 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4203 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 145:64910690c574 4204 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 145:64910690c574 4205 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4206 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 145:64910690c574 4207 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 145:64910690c574 4208 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4209 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 145:64910690c574 4210 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 145:64910690c574 4211 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4212 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 145:64910690c574 4213 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 145:64910690c574 4214 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4215 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 145:64910690c574 4216 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 145:64910690c574 4217 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4218 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 145:64910690c574 4219 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 145:64910690c574 4220 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4221 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 145:64910690c574 4222 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 145:64910690c574 4223 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4224 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 145:64910690c574 4225 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 145:64910690c574 4226 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4227 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 145:64910690c574 4228 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 145:64910690c574 4229 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4230 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 145:64910690c574 4231 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 145:64910690c574 4232 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4233 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 145:64910690c574 4234 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 145:64910690c574 4235 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4236 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
<> 128:9bcdf88f62b0 4237
<> 128:9bcdf88f62b0 4238 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 145:64910690c574 4239 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 145:64910690c574 4240 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4241 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 145:64910690c574 4242 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 145:64910690c574 4243 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4244 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 145:64910690c574 4245 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 145:64910690c574 4246 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4247 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 145:64910690c574 4248 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 145:64910690c574 4249 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4250 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 145:64910690c574 4251 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 145:64910690c574 4252 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4253 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 145:64910690c574 4254 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 145:64910690c574 4255 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4256 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 145:64910690c574 4257 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 145:64910690c574 4258 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4259 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 145:64910690c574 4260 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 145:64910690c574 4261 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4262 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 145:64910690c574 4263 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 145:64910690c574 4264 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4265 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 145:64910690c574 4266 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 145:64910690c574 4267 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4268 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 145:64910690c574 4269 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 145:64910690c574 4270 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4271 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
<> 128:9bcdf88f62b0 4272
<> 128:9bcdf88f62b0 4273 /* Old SPI1RST bit definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 4274 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
<> 128:9bcdf88f62b0 4275
<> 128:9bcdf88f62b0 4276 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 145:64910690c574 4277 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 145:64910690c574 4278 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4279 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 145:64910690c574 4280 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 145:64910690c574 4281 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4282 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 145:64910690c574 4283 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 145:64910690c574 4284 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4285 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 145:64910690c574 4286 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 145:64910690c574 4287 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4288 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 145:64910690c574 4289 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 145:64910690c574 4290 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4291 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 145:64910690c574 4292 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 145:64910690c574 4293 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4294 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 145:64910690c574 4295 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 145:64910690c574 4296 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4297 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 145:64910690c574 4298 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 145:64910690c574 4299 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4300 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 145:64910690c574 4301 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 145:64910690c574 4302 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4303 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
<> 128:9bcdf88f62b0 4304 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 145:64910690c574 4305 /*
AnnaBridge 145:64910690c574 4306 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 145:64910690c574 4307 */
AnnaBridge 145:64910690c574 4308 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 145:64910690c574 4309
AnnaBridge 145:64910690c574 4310 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 145:64910690c574 4311 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4312 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
<> 128:9bcdf88f62b0 4313
<> 128:9bcdf88f62b0 4314 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 145:64910690c574 4315 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 145:64910690c574 4316 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4317 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 145:64910690c574 4318 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 145:64910690c574 4319 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4320 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 145:64910690c574 4321 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 145:64910690c574 4322 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4323 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 145:64910690c574 4324 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 145:64910690c574 4325 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4326 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 145:64910690c574 4327 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 145:64910690c574 4328 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4329 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 145:64910690c574 4330 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 145:64910690c574 4331 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4332 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 145:64910690c574 4333 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 145:64910690c574 4334 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4335 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 145:64910690c574 4336 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 145:64910690c574 4337 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4338 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 145:64910690c574 4339 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 145:64910690c574 4340 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4341 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 145:64910690c574 4342 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 145:64910690c574 4343 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4344 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 145:64910690c574 4345 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 145:64910690c574 4346 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4347 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 145:64910690c574 4348 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 145:64910690c574 4349 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4350 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
<> 128:9bcdf88f62b0 4351
<> 128:9bcdf88f62b0 4352 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 145:64910690c574 4353 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 145:64910690c574 4354 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4355 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 145:64910690c574 4356 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 145:64910690c574 4357 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4358 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 145:64910690c574 4359 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 145:64910690c574 4360 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4361 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 145:64910690c574 4362 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 145:64910690c574 4363 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4364 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 145:64910690c574 4365 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 145:64910690c574 4366 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4367 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 145:64910690c574 4368 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 145:64910690c574 4369 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4370 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 145:64910690c574 4371 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 145:64910690c574 4372 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4373 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 145:64910690c574 4374 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 145:64910690c574 4375 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4376 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 145:64910690c574 4377 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 145:64910690c574 4378 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4379 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 145:64910690c574 4380 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 145:64910690c574 4381 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4382 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 145:64910690c574 4383 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 145:64910690c574 4384 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4385 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
<> 128:9bcdf88f62b0 4386
<> 128:9bcdf88f62b0 4387 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 145:64910690c574 4388 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 145:64910690c574 4389 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4390 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 145:64910690c574 4391 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 145:64910690c574 4392 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4393 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 145:64910690c574 4394 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 145:64910690c574 4395 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4396 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 145:64910690c574 4397 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 145:64910690c574 4398 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4399 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 145:64910690c574 4400 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 145:64910690c574 4401 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4402 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 145:64910690c574 4403 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 145:64910690c574 4404 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4405 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 145:64910690c574 4406 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 145:64910690c574 4407 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4408 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 145:64910690c574 4409 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 145:64910690c574 4410 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4411 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 145:64910690c574 4412 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 145:64910690c574 4413 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4414 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 145:64910690c574 4415 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 145:64910690c574 4416 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4417 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 145:64910690c574 4418 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 145:64910690c574 4419 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4420 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 145:64910690c574 4421
<> 128:9bcdf88f62b0 4422
<> 128:9bcdf88f62b0 4423 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 145:64910690c574 4424 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 145:64910690c574 4425 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4426 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
<> 128:9bcdf88f62b0 4427
<> 128:9bcdf88f62b0 4428 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 128:9bcdf88f62b0 4429
<> 128:9bcdf88f62b0 4430 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 145:64910690c574 4431 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 145:64910690c574 4432 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4433 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 145:64910690c574 4434 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 145:64910690c574 4435 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4436 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 145:64910690c574 4437 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 145:64910690c574 4438 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4439 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 145:64910690c574 4440 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 145:64910690c574 4441 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4442 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 145:64910690c574 4443 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 145:64910690c574 4444 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4445 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 145:64910690c574 4446 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 145:64910690c574 4447 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4448 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 145:64910690c574 4449 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 145:64910690c574 4450 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4451 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 145:64910690c574 4452 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 145:64910690c574 4453 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4454 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 145:64910690c574 4455 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 145:64910690c574 4456 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4457 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 145:64910690c574 4458 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 145:64910690c574 4459 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4460 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 145:64910690c574 4461 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 145:64910690c574 4462 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4463 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 145:64910690c574 4464 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 145:64910690c574 4465 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4466 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
<> 128:9bcdf88f62b0 4467
<> 128:9bcdf88f62b0 4468 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 145:64910690c574 4469 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 145:64910690c574 4470 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4471 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 145:64910690c574 4472 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 145:64910690c574 4473 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4474 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 145:64910690c574 4475 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 145:64910690c574 4476 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4477 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 145:64910690c574 4478 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 145:64910690c574 4479 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4480 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 145:64910690c574 4481 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 145:64910690c574 4482 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4483 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 145:64910690c574 4484 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 145:64910690c574 4485 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4486 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 145:64910690c574 4487 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 145:64910690c574 4488 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4489 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 145:64910690c574 4490 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 145:64910690c574 4491 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4492 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 145:64910690c574 4493 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 145:64910690c574 4494 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4495 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 145:64910690c574 4496 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 145:64910690c574 4497 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4498 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 145:64910690c574 4499 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 145:64910690c574 4500 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4501 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
<> 128:9bcdf88f62b0 4502
<> 128:9bcdf88f62b0 4503 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 145:64910690c574 4504 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 145:64910690c574 4505 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4506 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 145:64910690c574 4507 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 145:64910690c574 4508 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4509 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 145:64910690c574 4510 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 145:64910690c574 4511 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4512 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 145:64910690c574 4513
AnnaBridge 145:64910690c574 4514 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 145:64910690c574 4515 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 4516 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 145:64910690c574 4517 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4518 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4519
AnnaBridge 145:64910690c574 4520 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 145:64910690c574 4521 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4522 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 145:64910690c574 4523 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 145:64910690c574 4524 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4525 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
<> 128:9bcdf88f62b0 4526
<> 128:9bcdf88f62b0 4527 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 145:64910690c574 4528 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 145:64910690c574 4529 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4530 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 145:64910690c574 4531 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 145:64910690c574 4532 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4533 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 145:64910690c574 4534 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 145:64910690c574 4535 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 4536 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 145:64910690c574 4537 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 145:64910690c574 4538 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 4539 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 145:64910690c574 4540 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 145:64910690c574 4541 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 4542 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 145:64910690c574 4543 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 145:64910690c574 4544 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 4545 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 145:64910690c574 4546 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 145:64910690c574 4547 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4548 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 145:64910690c574 4549 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 145:64910690c574 4550 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 4551 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 145:64910690c574 4552 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 145:64910690c574 4553 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 4554 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 145:64910690c574 4555 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 145:64910690c574 4556 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 4557 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 145:64910690c574 4558 /* Legacy defines */
AnnaBridge 145:64910690c574 4559 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 145:64910690c574 4560 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
<> 128:9bcdf88f62b0 4561
<> 128:9bcdf88f62b0 4562 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 145:64910690c574 4563 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 145:64910690c574 4564 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 145:64910690c574 4565 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 145:64910690c574 4566 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 145:64910690c574 4567 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 145:64910690c574 4568 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 145:64910690c574 4569 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 145:64910690c574 4570 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 4571 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 145:64910690c574 4572 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 145:64910690c574 4573 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 4574 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
<> 128:9bcdf88f62b0 4575
<> 128:9bcdf88f62b0 4576 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 145:64910690c574 4577 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 145:64910690c574 4578 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 145:64910690c574 4579 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 145:64910690c574 4580 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4581 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4582 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4583 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4584 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4585 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4586 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4587 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4588 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4589
AnnaBridge 145:64910690c574 4590 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 145:64910690c574 4591 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 145:64910690c574 4592 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 145:64910690c574 4593 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4594 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 4595 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4596
<> 128:9bcdf88f62b0 4597 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 145:64910690c574 4598
AnnaBridge 145:64910690c574 4599 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 145:64910690c574 4600 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 4601 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
AnnaBridge 145:64910690c574 4602
<> 128:9bcdf88f62b0 4603
<> 128:9bcdf88f62b0 4604 /******************************************************************************/
<> 128:9bcdf88f62b0 4605 /* */
<> 128:9bcdf88f62b0 4606 /* Real-Time Clock (RTC) */
<> 128:9bcdf88f62b0 4607 /* */
<> 128:9bcdf88f62b0 4608 /******************************************************************************/
<> 128:9bcdf88f62b0 4609 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 145:64910690c574 4610 #define RTC_TR_PM_Pos (22U)
AnnaBridge 145:64910690c574 4611 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4612 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 145:64910690c574 4613 #define RTC_TR_HT_Pos (20U)
AnnaBridge 145:64910690c574 4614 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 4615 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 145:64910690c574 4616 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4617 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4618 #define RTC_TR_HU_Pos (16U)
AnnaBridge 145:64910690c574 4619 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 4620 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 145:64910690c574 4621 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4622 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4623 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4624 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4625 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 145:64910690c574 4626 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 4627 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 145:64910690c574 4628 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4629 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4630 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4631 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 145:64910690c574 4632 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 4633 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 145:64910690c574 4634 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4635 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4636 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4637 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4638 #define RTC_TR_ST_Pos (4U)
AnnaBridge 145:64910690c574 4639 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 4640 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 145:64910690c574 4641 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4642 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4643 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4644 #define RTC_TR_SU_Pos (0U)
AnnaBridge 145:64910690c574 4645 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 4646 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 145:64910690c574 4647 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4648 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4649 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4650 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4651
<> 128:9bcdf88f62b0 4652 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 145:64910690c574 4653 #define RTC_DR_YT_Pos (20U)
AnnaBridge 145:64910690c574 4654 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 145:64910690c574 4655 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 145:64910690c574 4656 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4657 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4658 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4659 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4660 #define RTC_DR_YU_Pos (16U)
AnnaBridge 145:64910690c574 4661 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 4662 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 145:64910690c574 4663 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4664 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4665 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4666 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4667 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 145:64910690c574 4668 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 145:64910690c574 4669 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 145:64910690c574 4670 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4671 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4672 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4673 #define RTC_DR_MT_Pos (12U)
AnnaBridge 145:64910690c574 4674 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4675 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 145:64910690c574 4676 #define RTC_DR_MU_Pos (8U)
AnnaBridge 145:64910690c574 4677 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 4678 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 145:64910690c574 4679 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4680 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4681 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4682 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4683 #define RTC_DR_DT_Pos (4U)
AnnaBridge 145:64910690c574 4684 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 4685 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 145:64910690c574 4686 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4687 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4688 #define RTC_DR_DU_Pos (0U)
AnnaBridge 145:64910690c574 4689 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 4690 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 145:64910690c574 4691 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4692 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4693 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4694 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4695
<> 128:9bcdf88f62b0 4696 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 145:64910690c574 4697 #define RTC_CR_COE_Pos (23U)
AnnaBridge 145:64910690c574 4698 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4699 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 145:64910690c574 4700 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 145:64910690c574 4701 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 145:64910690c574 4702 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 145:64910690c574 4703 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4704 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4705 #define RTC_CR_POL_Pos (20U)
AnnaBridge 145:64910690c574 4706 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4707 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 145:64910690c574 4708 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 145:64910690c574 4709 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4710 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 145:64910690c574 4711 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 145:64910690c574 4712 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4713 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 145:64910690c574 4714 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 145:64910690c574 4715 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4716 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 145:64910690c574 4717 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 145:64910690c574 4718 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4719 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 145:64910690c574 4720 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 145:64910690c574 4721 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4722 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 145:64910690c574 4723 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 145:64910690c574 4724 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4725 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 145:64910690c574 4726 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 145:64910690c574 4727 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4728 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 145:64910690c574 4729 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 145:64910690c574 4730 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4731 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 145:64910690c574 4732 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 145:64910690c574 4733 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4734 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 145:64910690c574 4735 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 145:64910690c574 4736 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4737 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 145:64910690c574 4738 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 145:64910690c574 4739 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4740 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 145:64910690c574 4741 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 145:64910690c574 4742 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4743 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 145:64910690c574 4744 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 145:64910690c574 4745 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4746 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 145:64910690c574 4747 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 145:64910690c574 4748 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4749 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 145:64910690c574 4750 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 145:64910690c574 4751 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4752 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 145:64910690c574 4753 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 145:64910690c574 4754 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4755 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 145:64910690c574 4756 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 145:64910690c574 4757 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4758 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 145:64910690c574 4759 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 145:64910690c574 4760 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 4761 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 145:64910690c574 4762 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4763 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4764 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4765
AnnaBridge 145:64910690c574 4766 /* Legacy defines */
AnnaBridge 145:64910690c574 4767 #define RTC_CR_BCK RTC_CR_BKP
<> 128:9bcdf88f62b0 4768
<> 128:9bcdf88f62b0 4769 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 145:64910690c574 4770 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 145:64910690c574 4771 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4772 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 145:64910690c574 4773 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 145:64910690c574 4774 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4775 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 145:64910690c574 4776 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 145:64910690c574 4777 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4778 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 145:64910690c574 4779 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 145:64910690c574 4780 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4781 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 145:64910690c574 4782 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 145:64910690c574 4783 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4784 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 145:64910690c574 4785 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 145:64910690c574 4786 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4787 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 145:64910690c574 4788 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 145:64910690c574 4789 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4790 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 145:64910690c574 4791 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 145:64910690c574 4792 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4793 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 145:64910690c574 4794 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 145:64910690c574 4795 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4796 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 145:64910690c574 4797 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 145:64910690c574 4798 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4799 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 145:64910690c574 4800 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 145:64910690c574 4801 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4802 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 145:64910690c574 4803 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 145:64910690c574 4804 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4805 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 145:64910690c574 4806 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 145:64910690c574 4807 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 4808 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 145:64910690c574 4809 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 145:64910690c574 4810 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4811 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 145:64910690c574 4812 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 145:64910690c574 4813 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4814 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 145:64910690c574 4815 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 145:64910690c574 4816 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4817 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 128:9bcdf88f62b0 4818
<> 128:9bcdf88f62b0 4819 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 145:64910690c574 4820 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 145:64910690c574 4821 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 145:64910690c574 4822 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 145:64910690c574 4823 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 145:64910690c574 4824 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 145:64910690c574 4825 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 128:9bcdf88f62b0 4826
<> 128:9bcdf88f62b0 4827 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 145:64910690c574 4828 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 145:64910690c574 4829 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 4830 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 128:9bcdf88f62b0 4831
<> 128:9bcdf88f62b0 4832 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 145:64910690c574 4833 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 145:64910690c574 4834 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4835 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 145:64910690c574 4836 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 145:64910690c574 4837 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 4838 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
<> 128:9bcdf88f62b0 4839
<> 128:9bcdf88f62b0 4840 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 145:64910690c574 4841 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 145:64910690c574 4842 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 4843 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 145:64910690c574 4844 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 145:64910690c574 4845 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 4846 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 145:64910690c574 4847 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 145:64910690c574 4848 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 4849 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 145:64910690c574 4850 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4851 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 4852 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 145:64910690c574 4853 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 4854 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 145:64910690c574 4855 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 4856 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 4857 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 4858 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 4859 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 145:64910690c574 4860 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4861 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 145:64910690c574 4862 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 145:64910690c574 4863 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4864 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 145:64910690c574 4865 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 145:64910690c574 4866 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 4867 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 145:64910690c574 4868 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4869 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4870 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 145:64910690c574 4871 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 4872 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 145:64910690c574 4873 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4874 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4875 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4876 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4877 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 145:64910690c574 4878 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4879 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 145:64910690c574 4880 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 145:64910690c574 4881 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 4882 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 145:64910690c574 4883 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4884 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4885 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4886 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 145:64910690c574 4887 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 4888 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 145:64910690c574 4889 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4890 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4891 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4892 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4893 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 145:64910690c574 4894 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4895 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 145:64910690c574 4896 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 145:64910690c574 4897 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 4898 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 145:64910690c574 4899 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4900 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4901 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4902 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 145:64910690c574 4903 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 4904 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 145:64910690c574 4905 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4906 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4907 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4908 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4909
<> 128:9bcdf88f62b0 4910 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 145:64910690c574 4911 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 145:64910690c574 4912 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 4913 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 145:64910690c574 4914 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 145:64910690c574 4915 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 4916 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 145:64910690c574 4917 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 145:64910690c574 4918 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 145:64910690c574 4919 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 145:64910690c574 4920 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 4921 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 4922 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 145:64910690c574 4923 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 4924 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 145:64910690c574 4925 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 4926 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 4927 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 4928 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 4929 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 145:64910690c574 4930 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 4931 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 145:64910690c574 4932 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 145:64910690c574 4933 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 4934 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 145:64910690c574 4935 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 145:64910690c574 4936 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 4937 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 145:64910690c574 4938 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 4939 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 4940 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 145:64910690c574 4941 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 4942 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 145:64910690c574 4943 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 4944 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 4945 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 4946 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 4947 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 145:64910690c574 4948 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 4949 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 145:64910690c574 4950 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 145:64910690c574 4951 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 4952 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 145:64910690c574 4953 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 4954 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 4955 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 4956 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 145:64910690c574 4957 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 4958 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 145:64910690c574 4959 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 4960 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 4961 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 4962 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 4963 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 145:64910690c574 4964 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 4965 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 145:64910690c574 4966 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 145:64910690c574 4967 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 4968 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 145:64910690c574 4969 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 4970 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 4971 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 4972 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 145:64910690c574 4973 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 4974 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 145:64910690c574 4975 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 4976 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 4977 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 4978 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4979
<> 128:9bcdf88f62b0 4980 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 145:64910690c574 4981 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 145:64910690c574 4982 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 4983 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 128:9bcdf88f62b0 4984
<> 128:9bcdf88f62b0 4985 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 145:64910690c574 4986 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 145:64910690c574 4987 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 4988 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 128:9bcdf88f62b0 4989
<> 128:9bcdf88f62b0 4990 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 145:64910690c574 4991 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 145:64910690c574 4992 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 145:64910690c574 4993 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 145:64910690c574 4994 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 145:64910690c574 4995 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 4996 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 128:9bcdf88f62b0 4997
<> 128:9bcdf88f62b0 4998 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 145:64910690c574 4999 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 145:64910690c574 5000 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 5001 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 145:64910690c574 5002 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 145:64910690c574 5003 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 5004 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 145:64910690c574 5005 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 5006 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 5007 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 145:64910690c574 5008 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 145:64910690c574 5009 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 145:64910690c574 5010 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 5011 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 5012 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 5013 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 5014 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 145:64910690c574 5015 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 5016 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 145:64910690c574 5017 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5018 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5019 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5020 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 145:64910690c574 5021 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5022 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 145:64910690c574 5023 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5024 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5025 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5026 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5027 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 145:64910690c574 5028 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 5029 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 145:64910690c574 5030 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5031 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5032 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5033 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 145:64910690c574 5034 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5035 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 145:64910690c574 5036 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5037 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5038 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5039 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5040
<> 128:9bcdf88f62b0 5041 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 145:64910690c574 5042 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 145:64910690c574 5043 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 145:64910690c574 5044 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 145:64910690c574 5045 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5046 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5047 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5048 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 145:64910690c574 5049 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5050 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 145:64910690c574 5051 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 145:64910690c574 5052 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5053 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 145:64910690c574 5054 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5055 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5056 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5057 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5058 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 145:64910690c574 5059 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 5060 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 145:64910690c574 5061 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5062 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5063 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 145:64910690c574 5064 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5065 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 145:64910690c574 5066 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5067 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5068 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5069 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5070
<> 128:9bcdf88f62b0 5071 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 145:64910690c574 5072 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 145:64910690c574 5073 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 5074 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 128:9bcdf88f62b0 5075
<> 128:9bcdf88f62b0 5076 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 145:64910690c574 5077 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 145:64910690c574 5078 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5079 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 145:64910690c574 5080 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 145:64910690c574 5081 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5082 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 145:64910690c574 5083 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 145:64910690c574 5084 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5085 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 145:64910690c574 5086 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 145:64910690c574 5087 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 145:64910690c574 5088 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 145:64910690c574 5089 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5090 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5091 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5092 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5093 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5094 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5095 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5096 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5097 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5098
<> 128:9bcdf88f62b0 5099 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 145:64910690c574 5100 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 145:64910690c574 5101 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 5102 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 145:64910690c574 5103 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 145:64910690c574 5104 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 5105 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 145:64910690c574 5106 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 145:64910690c574 5107 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 5108 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 145:64910690c574 5109 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 145:64910690c574 5110 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5111 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 145:64910690c574 5112 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 145:64910690c574 5113 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 145:64910690c574 5114 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 145:64910690c574 5115 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5116 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5117 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 145:64910690c574 5118 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 145:64910690c574 5119 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 145:64910690c574 5120 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5121 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5122 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 145:64910690c574 5123 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 145:64910690c574 5124 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 145:64910690c574 5125 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5126 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5127 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5128 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 145:64910690c574 5129 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5130 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 145:64910690c574 5131 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 145:64910690c574 5132 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5133 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 145:64910690c574 5134 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 145:64910690c574 5135 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5136 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 145:64910690c574 5137 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 145:64910690c574 5138 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5139 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 145:64910690c574 5140 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 145:64910690c574 5141 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5142 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 145:64910690c574 5143 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 145:64910690c574 5144 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5145 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 145:64910690c574 5146
AnnaBridge 145:64910690c574 5147 /* Legacy defines */
AnnaBridge 145:64910690c574 5148 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
<> 128:9bcdf88f62b0 5149
<> 128:9bcdf88f62b0 5150 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 145:64910690c574 5151 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 145:64910690c574 5152 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 5153 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 145:64910690c574 5154 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 5155 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 5156 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 5157 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 5158 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 145:64910690c574 5159 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 145:64910690c574 5160 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 128:9bcdf88f62b0 5161
<> 128:9bcdf88f62b0 5162 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 145:64910690c574 5163 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 145:64910690c574 5164 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 145:64910690c574 5165 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 145:64910690c574 5166 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 5167 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 5168 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 5169 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 5170 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 145:64910690c574 5171 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 145:64910690c574 5172 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 128:9bcdf88f62b0 5173
<> 128:9bcdf88f62b0 5174 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 145:64910690c574 5175 #define RTC_BKP0R_Pos (0U)
AnnaBridge 145:64910690c574 5176 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5177 #define RTC_BKP0R RTC_BKP0R_Msk
<> 128:9bcdf88f62b0 5178
<> 128:9bcdf88f62b0 5179 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 145:64910690c574 5180 #define RTC_BKP1R_Pos (0U)
AnnaBridge 145:64910690c574 5181 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5182 #define RTC_BKP1R RTC_BKP1R_Msk
<> 128:9bcdf88f62b0 5183
<> 128:9bcdf88f62b0 5184 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 145:64910690c574 5185 #define RTC_BKP2R_Pos (0U)
AnnaBridge 145:64910690c574 5186 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5187 #define RTC_BKP2R RTC_BKP2R_Msk
<> 128:9bcdf88f62b0 5188
<> 128:9bcdf88f62b0 5189 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 145:64910690c574 5190 #define RTC_BKP3R_Pos (0U)
AnnaBridge 145:64910690c574 5191 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5192 #define RTC_BKP3R RTC_BKP3R_Msk
<> 128:9bcdf88f62b0 5193
<> 128:9bcdf88f62b0 5194 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 145:64910690c574 5195 #define RTC_BKP4R_Pos (0U)
AnnaBridge 145:64910690c574 5196 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5197 #define RTC_BKP4R RTC_BKP4R_Msk
<> 128:9bcdf88f62b0 5198
<> 128:9bcdf88f62b0 5199 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 145:64910690c574 5200 #define RTC_BKP5R_Pos (0U)
AnnaBridge 145:64910690c574 5201 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5202 #define RTC_BKP5R RTC_BKP5R_Msk
<> 128:9bcdf88f62b0 5203
<> 128:9bcdf88f62b0 5204 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 145:64910690c574 5205 #define RTC_BKP6R_Pos (0U)
AnnaBridge 145:64910690c574 5206 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5207 #define RTC_BKP6R RTC_BKP6R_Msk
<> 128:9bcdf88f62b0 5208
<> 128:9bcdf88f62b0 5209 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 145:64910690c574 5210 #define RTC_BKP7R_Pos (0U)
AnnaBridge 145:64910690c574 5211 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5212 #define RTC_BKP7R RTC_BKP7R_Msk
<> 128:9bcdf88f62b0 5213
<> 128:9bcdf88f62b0 5214 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 145:64910690c574 5215 #define RTC_BKP8R_Pos (0U)
AnnaBridge 145:64910690c574 5216 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5217 #define RTC_BKP8R RTC_BKP8R_Msk
<> 128:9bcdf88f62b0 5218
<> 128:9bcdf88f62b0 5219 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 145:64910690c574 5220 #define RTC_BKP9R_Pos (0U)
AnnaBridge 145:64910690c574 5221 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5222 #define RTC_BKP9R RTC_BKP9R_Msk
<> 128:9bcdf88f62b0 5223
<> 128:9bcdf88f62b0 5224 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 145:64910690c574 5225 #define RTC_BKP10R_Pos (0U)
AnnaBridge 145:64910690c574 5226 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5227 #define RTC_BKP10R RTC_BKP10R_Msk
<> 128:9bcdf88f62b0 5228
<> 128:9bcdf88f62b0 5229 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 145:64910690c574 5230 #define RTC_BKP11R_Pos (0U)
AnnaBridge 145:64910690c574 5231 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5232 #define RTC_BKP11R RTC_BKP11R_Msk
<> 128:9bcdf88f62b0 5233
<> 128:9bcdf88f62b0 5234 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 145:64910690c574 5235 #define RTC_BKP12R_Pos (0U)
AnnaBridge 145:64910690c574 5236 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5237 #define RTC_BKP12R RTC_BKP12R_Msk
<> 128:9bcdf88f62b0 5238
<> 128:9bcdf88f62b0 5239 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 145:64910690c574 5240 #define RTC_BKP13R_Pos (0U)
AnnaBridge 145:64910690c574 5241 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5242 #define RTC_BKP13R RTC_BKP13R_Msk
<> 128:9bcdf88f62b0 5243
<> 128:9bcdf88f62b0 5244 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 145:64910690c574 5245 #define RTC_BKP14R_Pos (0U)
AnnaBridge 145:64910690c574 5246 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5247 #define RTC_BKP14R RTC_BKP14R_Msk
<> 128:9bcdf88f62b0 5248
<> 128:9bcdf88f62b0 5249 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 145:64910690c574 5250 #define RTC_BKP15R_Pos (0U)
AnnaBridge 145:64910690c574 5251 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5252 #define RTC_BKP15R RTC_BKP15R_Msk
<> 128:9bcdf88f62b0 5253
<> 128:9bcdf88f62b0 5254 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 145:64910690c574 5255 #define RTC_BKP16R_Pos (0U)
AnnaBridge 145:64910690c574 5256 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5257 #define RTC_BKP16R RTC_BKP16R_Msk
<> 128:9bcdf88f62b0 5258
<> 128:9bcdf88f62b0 5259 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 145:64910690c574 5260 #define RTC_BKP17R_Pos (0U)
AnnaBridge 145:64910690c574 5261 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5262 #define RTC_BKP17R RTC_BKP17R_Msk
<> 128:9bcdf88f62b0 5263
<> 128:9bcdf88f62b0 5264 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 145:64910690c574 5265 #define RTC_BKP18R_Pos (0U)
AnnaBridge 145:64910690c574 5266 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5267 #define RTC_BKP18R RTC_BKP18R_Msk
<> 128:9bcdf88f62b0 5268
<> 128:9bcdf88f62b0 5269 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 145:64910690c574 5270 #define RTC_BKP19R_Pos (0U)
AnnaBridge 145:64910690c574 5271 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5272 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 145:64910690c574 5273
AnnaBridge 145:64910690c574 5274 /******************** Number of backup registers ******************************/
AnnaBridge 145:64910690c574 5275 #define RTC_BKP_NUMBER 0x000000014U
<> 128:9bcdf88f62b0 5276
<> 128:9bcdf88f62b0 5277
<> 128:9bcdf88f62b0 5278 /******************************************************************************/
<> 128:9bcdf88f62b0 5279 /* */
<> 128:9bcdf88f62b0 5280 /* SD host Interface */
<> 128:9bcdf88f62b0 5281 /* */
<> 128:9bcdf88f62b0 5282 /******************************************************************************/
<> 128:9bcdf88f62b0 5283 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 145:64910690c574 5284 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 145:64910690c574 5285 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 5286 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 145:64910690c574 5287 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 145:64910690c574 5288 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
<> 128:9bcdf88f62b0 5289
<> 128:9bcdf88f62b0 5290 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 145:64910690c574 5291 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 145:64910690c574 5292 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 5293 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 145:64910690c574 5294 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 145:64910690c574 5295 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5296 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 145:64910690c574 5297 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 145:64910690c574 5298 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5299 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 145:64910690c574 5300 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 145:64910690c574 5301 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5302 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 145:64910690c574 5303
AnnaBridge 145:64910690c574 5304 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 145:64910690c574 5305 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 145:64910690c574 5306 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 145:64910690c574 5307 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 145:64910690c574 5308 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 5309
AnnaBridge 145:64910690c574 5310 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 145:64910690c574 5311 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5312 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 145:64910690c574 5313 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 145:64910690c574 5314 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5315 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
<> 128:9bcdf88f62b0 5316
<> 128:9bcdf88f62b0 5317 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 145:64910690c574 5318 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 145:64910690c574 5319 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5320 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
<> 128:9bcdf88f62b0 5321
<> 128:9bcdf88f62b0 5322 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 145:64910690c574 5323 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 145:64910690c574 5324 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 145:64910690c574 5325 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 145:64910690c574 5326
AnnaBridge 145:64910690c574 5327 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 145:64910690c574 5328 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 5329 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 145:64910690c574 5330 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 5331 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 5332
AnnaBridge 145:64910690c574 5333 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 145:64910690c574 5334 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5335 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 145:64910690c574 5336 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 145:64910690c574 5337 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5338 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 145:64910690c574 5339 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 145:64910690c574 5340 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5341 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 145:64910690c574 5342 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 145:64910690c574 5343 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5344 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 145:64910690c574 5345 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
AnnaBridge 145:64910690c574 5346 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5347 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
AnnaBridge 145:64910690c574 5348 #define SDIO_CMD_NIEN_Pos (13U)
AnnaBridge 145:64910690c574 5349 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5350 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
AnnaBridge 145:64910690c574 5351 #define SDIO_CMD_CEATACMD_Pos (14U)
AnnaBridge 145:64910690c574 5352 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5353 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
<> 128:9bcdf88f62b0 5354
<> 128:9bcdf88f62b0 5355 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 145:64910690c574 5356 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 145:64910690c574 5357 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 145:64910690c574 5358 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
<> 128:9bcdf88f62b0 5359
<> 128:9bcdf88f62b0 5360 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 145:64910690c574 5361 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 145:64910690c574 5362 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5363 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 5364
<> 128:9bcdf88f62b0 5365 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 145:64910690c574 5366 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 145:64910690c574 5367 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5368 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 5369
<> 128:9bcdf88f62b0 5370 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 145:64910690c574 5371 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 145:64910690c574 5372 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5373 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 5374
<> 128:9bcdf88f62b0 5375 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 145:64910690c574 5376 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 145:64910690c574 5377 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5378 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 5379
<> 128:9bcdf88f62b0 5380 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 145:64910690c574 5381 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 145:64910690c574 5382 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5383 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 5384
<> 128:9bcdf88f62b0 5385 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 145:64910690c574 5386 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 145:64910690c574 5387 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5388 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
<> 128:9bcdf88f62b0 5389
<> 128:9bcdf88f62b0 5390 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 145:64910690c574 5391 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 145:64910690c574 5392 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 145:64910690c574 5393 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
<> 128:9bcdf88f62b0 5394
<> 128:9bcdf88f62b0 5395 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 145:64910690c574 5396 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 145:64910690c574 5397 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5398 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 145:64910690c574 5399 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 145:64910690c574 5400 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5401 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 145:64910690c574 5402 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 145:64910690c574 5403 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5404 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 145:64910690c574 5405 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 145:64910690c574 5406 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5407 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 145:64910690c574 5408
AnnaBridge 145:64910690c574 5409 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 145:64910690c574 5410 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 5411 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 145:64910690c574 5412 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 5413 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 5414 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 5415 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 5416
AnnaBridge 145:64910690c574 5417 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 145:64910690c574 5418 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5419 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 145:64910690c574 5420 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 145:64910690c574 5421 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5422 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 145:64910690c574 5423 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 145:64910690c574 5424 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5425 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 145:64910690c574 5426 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 145:64910690c574 5427 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5428 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
<> 128:9bcdf88f62b0 5429
<> 128:9bcdf88f62b0 5430 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 145:64910690c574 5431 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 145:64910690c574 5432 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 145:64910690c574 5433 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
<> 128:9bcdf88f62b0 5434
<> 128:9bcdf88f62b0 5435 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 145:64910690c574 5436 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 145:64910690c574 5437 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5438 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 145:64910690c574 5439 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 145:64910690c574 5440 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5441 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 145:64910690c574 5442 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 145:64910690c574 5443 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5444 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 145:64910690c574 5445 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 145:64910690c574 5446 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5447 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 145:64910690c574 5448 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 145:64910690c574 5449 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5450 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 145:64910690c574 5451 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 145:64910690c574 5452 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5453 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 145:64910690c574 5454 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 145:64910690c574 5455 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5456 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 145:64910690c574 5457 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 145:64910690c574 5458 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5459 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 145:64910690c574 5460 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 145:64910690c574 5461 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5462 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 145:64910690c574 5463 #define SDIO_STA_STBITERR_Pos (9U)
AnnaBridge 145:64910690c574 5464 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5465 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
AnnaBridge 145:64910690c574 5466 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 145:64910690c574 5467 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5468 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 145:64910690c574 5469 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 145:64910690c574 5470 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5471 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 145:64910690c574 5472 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 145:64910690c574 5473 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5474 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 145:64910690c574 5475 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 145:64910690c574 5476 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5477 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 145:64910690c574 5478 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 145:64910690c574 5479 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5480 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 145:64910690c574 5481 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 145:64910690c574 5482 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5483 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 145:64910690c574 5484 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 145:64910690c574 5485 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 5486 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 145:64910690c574 5487 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 145:64910690c574 5488 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 5489 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 145:64910690c574 5490 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 145:64910690c574 5491 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 5492 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 145:64910690c574 5493 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 145:64910690c574 5494 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 5495 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 145:64910690c574 5496 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 145:64910690c574 5497 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 5498 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 145:64910690c574 5499 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 145:64910690c574 5500 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 5501 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 145:64910690c574 5502 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 145:64910690c574 5503 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 5504 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 145:64910690c574 5505 #define SDIO_STA_CEATAEND_Pos (23U)
AnnaBridge 145:64910690c574 5506 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 5507 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
<> 128:9bcdf88f62b0 5508
<> 128:9bcdf88f62b0 5509 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 145:64910690c574 5510 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 145:64910690c574 5511 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5512 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 145:64910690c574 5513 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 145:64910690c574 5514 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5515 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 145:64910690c574 5516 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 145:64910690c574 5517 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5518 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 145:64910690c574 5519 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 145:64910690c574 5520 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5521 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 145:64910690c574 5522 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 145:64910690c574 5523 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5524 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 145:64910690c574 5525 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 145:64910690c574 5526 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5527 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 145:64910690c574 5528 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 145:64910690c574 5529 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5530 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 145:64910690c574 5531 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 145:64910690c574 5532 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5533 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 145:64910690c574 5534 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 145:64910690c574 5535 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5536 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 145:64910690c574 5537 #define SDIO_ICR_STBITERRC_Pos (9U)
AnnaBridge 145:64910690c574 5538 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5539 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
AnnaBridge 145:64910690c574 5540 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 145:64910690c574 5541 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5542 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 145:64910690c574 5543 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 145:64910690c574 5544 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 5545 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 145:64910690c574 5546 #define SDIO_ICR_CEATAENDC_Pos (23U)
AnnaBridge 145:64910690c574 5547 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 5548 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
<> 128:9bcdf88f62b0 5549
<> 128:9bcdf88f62b0 5550 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 145:64910690c574 5551 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 145:64910690c574 5552 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5553 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 145:64910690c574 5554 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 145:64910690c574 5555 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5556 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 145:64910690c574 5557 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 145:64910690c574 5558 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5559 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 145:64910690c574 5560 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 145:64910690c574 5561 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5562 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 145:64910690c574 5563 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 145:64910690c574 5564 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5565 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 145:64910690c574 5566 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 145:64910690c574 5567 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5568 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 145:64910690c574 5569 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 145:64910690c574 5570 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5571 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 145:64910690c574 5572 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 145:64910690c574 5573 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5574 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 145:64910690c574 5575 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 145:64910690c574 5576 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5577 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 145:64910690c574 5578 #define SDIO_MASK_STBITERRIE_Pos (9U)
AnnaBridge 145:64910690c574 5579 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5580 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
AnnaBridge 145:64910690c574 5581 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 145:64910690c574 5582 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5583 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 145:64910690c574 5584 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 145:64910690c574 5585 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5586 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 145:64910690c574 5587 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 145:64910690c574 5588 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5589 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 145:64910690c574 5590 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 145:64910690c574 5591 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5592 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 145:64910690c574 5593 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 145:64910690c574 5594 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5595 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 145:64910690c574 5596 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 145:64910690c574 5597 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5598 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 145:64910690c574 5599 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 145:64910690c574 5600 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 5601 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 145:64910690c574 5602 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 145:64910690c574 5603 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 5604 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 145:64910690c574 5605 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 145:64910690c574 5606 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 5607 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 145:64910690c574 5608 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 145:64910690c574 5609 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 5610 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 145:64910690c574 5611 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 145:64910690c574 5612 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 5613 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 145:64910690c574 5614 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 145:64910690c574 5615 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 5616 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 145:64910690c574 5617 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 145:64910690c574 5618 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 5619 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 145:64910690c574 5620 #define SDIO_MASK_CEATAENDIE_Pos (23U)
AnnaBridge 145:64910690c574 5621 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 5622 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
<> 128:9bcdf88f62b0 5623
<> 128:9bcdf88f62b0 5624 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 145:64910690c574 5625 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 145:64910690c574 5626 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 145:64910690c574 5627 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
<> 128:9bcdf88f62b0 5628
<> 128:9bcdf88f62b0 5629 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 145:64910690c574 5630 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 145:64910690c574 5631 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 5632 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
<> 128:9bcdf88f62b0 5633
<> 128:9bcdf88f62b0 5634 /******************************************************************************/
<> 128:9bcdf88f62b0 5635 /* */
<> 128:9bcdf88f62b0 5636 /* Serial Peripheral Interface */
<> 128:9bcdf88f62b0 5637 /* */
<> 128:9bcdf88f62b0 5638 /******************************************************************************/
AnnaBridge 145:64910690c574 5639 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 145:64910690c574 5640
<> 128:9bcdf88f62b0 5641 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 145:64910690c574 5642 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 145:64910690c574 5643 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5644 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 145:64910690c574 5645 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 145:64910690c574 5646 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5647 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 145:64910690c574 5648 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 145:64910690c574 5649 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5650 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 145:64910690c574 5651
AnnaBridge 145:64910690c574 5652 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 145:64910690c574 5653 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 145:64910690c574 5654 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 145:64910690c574 5655 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5656 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5657 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5658
AnnaBridge 145:64910690c574 5659 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 145:64910690c574 5660 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5661 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 145:64910690c574 5662 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 145:64910690c574 5663 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5664 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 145:64910690c574 5665 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 145:64910690c574 5666 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5667 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 145:64910690c574 5668 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 145:64910690c574 5669 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5670 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 145:64910690c574 5671 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 145:64910690c574 5672 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5673 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 145:64910690c574 5674 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 145:64910690c574 5675 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5676 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 145:64910690c574 5677 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 145:64910690c574 5678 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 5679 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 145:64910690c574 5680 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 145:64910690c574 5681 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 5682 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 145:64910690c574 5683 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 145:64910690c574 5684 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 5685 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 145:64910690c574 5686 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 145:64910690c574 5687 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 5688 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
<> 128:9bcdf88f62b0 5689
<> 128:9bcdf88f62b0 5690 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 145:64910690c574 5691 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 145:64910690c574 5692 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5693 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 145:64910690c574 5694 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 145:64910690c574 5695 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5696 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 145:64910690c574 5697 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 145:64910690c574 5698 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5699 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 145:64910690c574 5700 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 145:64910690c574 5701 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5702 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 145:64910690c574 5703 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 145:64910690c574 5704 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5705 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 145:64910690c574 5706 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 145:64910690c574 5707 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5708 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 145:64910690c574 5709 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 145:64910690c574 5710 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5711 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
<> 128:9bcdf88f62b0 5712
<> 128:9bcdf88f62b0 5713 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 145:64910690c574 5714 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 145:64910690c574 5715 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5716 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 145:64910690c574 5717 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 145:64910690c574 5718 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5719 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 145:64910690c574 5720 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 145:64910690c574 5721 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5722 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 145:64910690c574 5723 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 145:64910690c574 5724 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5725 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 145:64910690c574 5726 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 145:64910690c574 5727 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5728 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 145:64910690c574 5729 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 145:64910690c574 5730 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5731 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 145:64910690c574 5732 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 145:64910690c574 5733 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 5734 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 145:64910690c574 5735 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 145:64910690c574 5736 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5737 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 145:64910690c574 5738 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 145:64910690c574 5739 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5740 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
<> 128:9bcdf88f62b0 5741
<> 128:9bcdf88f62b0 5742 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 145:64910690c574 5743 #define SPI_DR_DR_Pos (0U)
AnnaBridge 145:64910690c574 5744 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 5745 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
<> 128:9bcdf88f62b0 5746
<> 128:9bcdf88f62b0 5747 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 145:64910690c574 5748 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 145:64910690c574 5749 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 5750 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
<> 128:9bcdf88f62b0 5751
<> 128:9bcdf88f62b0 5752 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 145:64910690c574 5753 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 145:64910690c574 5754 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 5755 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
<> 128:9bcdf88f62b0 5756
<> 128:9bcdf88f62b0 5757 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 145:64910690c574 5758 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 145:64910690c574 5759 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 5760 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
<> 128:9bcdf88f62b0 5761
<> 128:9bcdf88f62b0 5762 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 145:64910690c574 5763 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 145:64910690c574 5764 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5765 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 145:64910690c574 5766
AnnaBridge 145:64910690c574 5767 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 145:64910690c574 5768 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 145:64910690c574 5769 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 145:64910690c574 5770 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 5771 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 5772
AnnaBridge 145:64910690c574 5773 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 145:64910690c574 5774 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 5775 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 145:64910690c574 5776
AnnaBridge 145:64910690c574 5777 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 145:64910690c574 5778 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 145:64910690c574 5779 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 145:64910690c574 5780 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 5781 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 5782
AnnaBridge 145:64910690c574 5783 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 145:64910690c574 5784 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 5785 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 145:64910690c574 5786
AnnaBridge 145:64910690c574 5787 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 145:64910690c574 5788 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 5789 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 145:64910690c574 5790 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5791 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5792
AnnaBridge 145:64910690c574 5793 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 145:64910690c574 5794 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 5795 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 145:64910690c574 5796 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 145:64910690c574 5797 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 5798 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 128:9bcdf88f62b0 5799
<> 128:9bcdf88f62b0 5800 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 145:64910690c574 5801 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 145:64910690c574 5802 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 5803 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 145:64910690c574 5804 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 145:64910690c574 5805 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 5806 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 145:64910690c574 5807 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 145:64910690c574 5808 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 5809 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 128:9bcdf88f62b0 5810
<> 128:9bcdf88f62b0 5811 /******************************************************************************/
<> 128:9bcdf88f62b0 5812 /* */
<> 128:9bcdf88f62b0 5813 /* SYSCFG */
<> 128:9bcdf88f62b0 5814 /* */
<> 128:9bcdf88f62b0 5815 /******************************************************************************/
AnnaBridge 145:64910690c574 5816 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 145:64910690c574 5817 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 145:64910690c574 5818 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 5819 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 145:64910690c574 5820 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 5821 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5822 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 145:64910690c574 5823 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 145:64910690c574 5824 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 5825 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
<> 128:9bcdf88f62b0 5826
<> 128:9bcdf88f62b0 5827 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 145:64910690c574 5828 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 145:64910690c574 5829 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5830 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 145:64910690c574 5831 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 145:64910690c574 5832 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 5833 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 145:64910690c574 5834 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 145:64910690c574 5835 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5836 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 145:64910690c574 5837 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 145:64910690c574 5838 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 5839 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 145:64910690c574 5840 /**
<> 128:9bcdf88f62b0 5841 * @brief EXTI0 configuration
AnnaBridge 145:64910690c574 5842 */
AnnaBridge 145:64910690c574 5843 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 145:64910690c574 5844 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 145:64910690c574 5845 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 145:64910690c574 5846 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 145:64910690c574 5847 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 145:64910690c574 5848 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 145:64910690c574 5849
AnnaBridge 145:64910690c574 5850 /**
<> 128:9bcdf88f62b0 5851 * @brief EXTI1 configuration
AnnaBridge 145:64910690c574 5852 */
AnnaBridge 145:64910690c574 5853 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 145:64910690c574 5854 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 145:64910690c574 5855 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 145:64910690c574 5856 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 145:64910690c574 5857 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 145:64910690c574 5858 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 145:64910690c574 5859
AnnaBridge 145:64910690c574 5860 /**
<> 128:9bcdf88f62b0 5861 * @brief EXTI2 configuration
AnnaBridge 145:64910690c574 5862 */
AnnaBridge 145:64910690c574 5863 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 145:64910690c574 5864 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 145:64910690c574 5865 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 145:64910690c574 5866 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 145:64910690c574 5867 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 145:64910690c574 5868 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 145:64910690c574 5869
AnnaBridge 145:64910690c574 5870 /**
<> 128:9bcdf88f62b0 5871 * @brief EXTI3 configuration
AnnaBridge 145:64910690c574 5872 */
AnnaBridge 145:64910690c574 5873 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 145:64910690c574 5874 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 145:64910690c574 5875 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 145:64910690c574 5876 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 145:64910690c574 5877 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 145:64910690c574 5878 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 128:9bcdf88f62b0 5879
<> 128:9bcdf88f62b0 5880 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 145:64910690c574 5881 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 145:64910690c574 5882 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5883 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 145:64910690c574 5884 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 145:64910690c574 5885 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 5886 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 145:64910690c574 5887 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 145:64910690c574 5888 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5889 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 145:64910690c574 5890 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 145:64910690c574 5891 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 5892 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 145:64910690c574 5893
AnnaBridge 145:64910690c574 5894 /**
<> 128:9bcdf88f62b0 5895 * @brief EXTI4 configuration
AnnaBridge 145:64910690c574 5896 */
AnnaBridge 145:64910690c574 5897 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 145:64910690c574 5898 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 145:64910690c574 5899 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 145:64910690c574 5900 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 145:64910690c574 5901 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 145:64910690c574 5902 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 145:64910690c574 5903
AnnaBridge 145:64910690c574 5904 /**
<> 128:9bcdf88f62b0 5905 * @brief EXTI5 configuration
AnnaBridge 145:64910690c574 5906 */
AnnaBridge 145:64910690c574 5907 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 145:64910690c574 5908 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 145:64910690c574 5909 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 145:64910690c574 5910 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 145:64910690c574 5911 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 145:64910690c574 5912 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 145:64910690c574 5913
AnnaBridge 145:64910690c574 5914 /**
<> 128:9bcdf88f62b0 5915 * @brief EXTI6 configuration
AnnaBridge 145:64910690c574 5916 */
AnnaBridge 145:64910690c574 5917 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 145:64910690c574 5918 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 145:64910690c574 5919 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 145:64910690c574 5920 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 145:64910690c574 5921 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 145:64910690c574 5922 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 145:64910690c574 5923
AnnaBridge 145:64910690c574 5924 /**
<> 128:9bcdf88f62b0 5925 * @brief EXTI7 configuration
AnnaBridge 145:64910690c574 5926 */
AnnaBridge 145:64910690c574 5927 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 145:64910690c574 5928 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 145:64910690c574 5929 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 145:64910690c574 5930 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 145:64910690c574 5931 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 145:64910690c574 5932 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 128:9bcdf88f62b0 5933
<> 128:9bcdf88f62b0 5934 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 145:64910690c574 5935 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 145:64910690c574 5936 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5937 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 145:64910690c574 5938 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 145:64910690c574 5939 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 5940 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 145:64910690c574 5941 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 145:64910690c574 5942 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5943 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 145:64910690c574 5944 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 145:64910690c574 5945 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 5946 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 145:64910690c574 5947
AnnaBridge 145:64910690c574 5948 /**
<> 128:9bcdf88f62b0 5949 * @brief EXTI8 configuration
AnnaBridge 145:64910690c574 5950 */
AnnaBridge 145:64910690c574 5951 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 145:64910690c574 5952 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 145:64910690c574 5953 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 145:64910690c574 5954 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 145:64910690c574 5955 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 145:64910690c574 5956 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 145:64910690c574 5957
AnnaBridge 145:64910690c574 5958 /**
<> 128:9bcdf88f62b0 5959 * @brief EXTI9 configuration
AnnaBridge 145:64910690c574 5960 */
AnnaBridge 145:64910690c574 5961 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 145:64910690c574 5962 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 145:64910690c574 5963 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 145:64910690c574 5964 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 145:64910690c574 5965 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 145:64910690c574 5966 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 145:64910690c574 5967
AnnaBridge 145:64910690c574 5968 /**
<> 128:9bcdf88f62b0 5969 * @brief EXTI10 configuration
AnnaBridge 145:64910690c574 5970 */
AnnaBridge 145:64910690c574 5971 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 145:64910690c574 5972 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 145:64910690c574 5973 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 145:64910690c574 5974 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 145:64910690c574 5975 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 145:64910690c574 5976 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 145:64910690c574 5977
AnnaBridge 145:64910690c574 5978 /**
<> 128:9bcdf88f62b0 5979 * @brief EXTI11 configuration
AnnaBridge 145:64910690c574 5980 */
AnnaBridge 145:64910690c574 5981 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 145:64910690c574 5982 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 145:64910690c574 5983 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 145:64910690c574 5984 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 145:64910690c574 5985 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 145:64910690c574 5986 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 128:9bcdf88f62b0 5987
<> 128:9bcdf88f62b0 5988 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 145:64910690c574 5989 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 145:64910690c574 5990 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 5991 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 145:64910690c574 5992 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 145:64910690c574 5993 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 5994 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 145:64910690c574 5995 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 145:64910690c574 5996 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 5997 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 145:64910690c574 5998 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 145:64910690c574 5999 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 6000 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 145:64910690c574 6001
AnnaBridge 145:64910690c574 6002 /**
<> 128:9bcdf88f62b0 6003 * @brief EXTI12 configuration
AnnaBridge 145:64910690c574 6004 */
AnnaBridge 145:64910690c574 6005 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 145:64910690c574 6006 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 145:64910690c574 6007 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 145:64910690c574 6008 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 145:64910690c574 6009 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 145:64910690c574 6010 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 145:64910690c574 6011
AnnaBridge 145:64910690c574 6012 /**
<> 128:9bcdf88f62b0 6013 * @brief EXTI13 configuration
AnnaBridge 145:64910690c574 6014 */
AnnaBridge 145:64910690c574 6015 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 145:64910690c574 6016 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 145:64910690c574 6017 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 145:64910690c574 6018 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 145:64910690c574 6019 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 145:64910690c574 6020 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 145:64910690c574 6021
AnnaBridge 145:64910690c574 6022 /**
<> 128:9bcdf88f62b0 6023 * @brief EXTI14 configuration
AnnaBridge 145:64910690c574 6024 */
AnnaBridge 145:64910690c574 6025 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 145:64910690c574 6026 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 145:64910690c574 6027 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 145:64910690c574 6028 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 145:64910690c574 6029 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 145:64910690c574 6030 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 145:64910690c574 6031
AnnaBridge 145:64910690c574 6032 /**
<> 128:9bcdf88f62b0 6033 * @brief EXTI15 configuration
AnnaBridge 145:64910690c574 6034 */
AnnaBridge 145:64910690c574 6035 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 145:64910690c574 6036 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 145:64910690c574 6037 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 145:64910690c574 6038 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 145:64910690c574 6039 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 145:64910690c574 6040 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 145:64910690c574 6041
AnnaBridge 145:64910690c574 6042 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 145:64910690c574 6043 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 145:64910690c574 6044 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6045 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 145:64910690c574 6046 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 145:64910690c574 6047 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6048 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
<> 128:9bcdf88f62b0 6049
<> 128:9bcdf88f62b0 6050 /******************************************************************************/
<> 128:9bcdf88f62b0 6051 /* */
<> 128:9bcdf88f62b0 6052 /* TIM */
<> 128:9bcdf88f62b0 6053 /* */
<> 128:9bcdf88f62b0 6054 /******************************************************************************/
<> 128:9bcdf88f62b0 6055 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 145:64910690c574 6056 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 145:64910690c574 6057 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6058 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 145:64910690c574 6059 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 145:64910690c574 6060 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6061 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 145:64910690c574 6062 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 145:64910690c574 6063 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6064 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 145:64910690c574 6065 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 145:64910690c574 6066 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6067 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 145:64910690c574 6068 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 145:64910690c574 6069 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6070 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 145:64910690c574 6071
AnnaBridge 145:64910690c574 6072 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 145:64910690c574 6073 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 145:64910690c574 6074 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 145:64910690c574 6075 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6076 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6077
AnnaBridge 145:64910690c574 6078 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 145:64910690c574 6079 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6080 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 145:64910690c574 6081
AnnaBridge 145:64910690c574 6082 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 145:64910690c574 6083 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 6084 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 145:64910690c574 6085 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6086 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
<> 128:9bcdf88f62b0 6087
<> 128:9bcdf88f62b0 6088 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 145:64910690c574 6089 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 145:64910690c574 6090 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6091 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 145:64910690c574 6092 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 145:64910690c574 6093 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6094 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 145:64910690c574 6095 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 145:64910690c574 6096 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6097 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 145:64910690c574 6098
AnnaBridge 145:64910690c574 6099 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 145:64910690c574 6100 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 6101 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 145:64910690c574 6102 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6103 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6104 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6105
AnnaBridge 145:64910690c574 6106 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 145:64910690c574 6107 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6108 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 145:64910690c574 6109 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 145:64910690c574 6110 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6111 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 145:64910690c574 6112 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 145:64910690c574 6113 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6114 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 145:64910690c574 6115 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 145:64910690c574 6116 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6117 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 145:64910690c574 6118 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 145:64910690c574 6119 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6120 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 145:64910690c574 6121 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 145:64910690c574 6122 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6123 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 145:64910690c574 6124 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 145:64910690c574 6125 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 6126 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 145:64910690c574 6127 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 145:64910690c574 6128 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 6129 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 128:9bcdf88f62b0 6130
<> 128:9bcdf88f62b0 6131 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 145:64910690c574 6132 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 145:64910690c574 6133 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 6134 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 145:64910690c574 6135 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6136 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6137 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6138
AnnaBridge 145:64910690c574 6139 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 145:64910690c574 6140 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 6141 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 145:64910690c574 6142 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6143 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6144 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6145
AnnaBridge 145:64910690c574 6146 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 145:64910690c574 6147 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6148 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 145:64910690c574 6149
AnnaBridge 145:64910690c574 6150 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 145:64910690c574 6151 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 145:64910690c574 6152 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 145:64910690c574 6153 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6154 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 145:64910690c574 6155 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 145:64910690c574 6156 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 145:64910690c574 6157
AnnaBridge 145:64910690c574 6158 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 145:64910690c574 6159 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 6160 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 145:64910690c574 6161 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6162 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6163
AnnaBridge 145:64910690c574 6164 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 145:64910690c574 6165 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 6166 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 145:64910690c574 6167 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 145:64910690c574 6168 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6169 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 128:9bcdf88f62b0 6170
<> 128:9bcdf88f62b0 6171 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 145:64910690c574 6172 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 145:64910690c574 6173 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6174 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 145:64910690c574 6175 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 145:64910690c574 6176 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6177 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 145:64910690c574 6178 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 145:64910690c574 6179 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6180 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 145:64910690c574 6181 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 145:64910690c574 6182 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6183 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 145:64910690c574 6184 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 145:64910690c574 6185 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6186 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 145:64910690c574 6187 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 145:64910690c574 6188 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6189 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 145:64910690c574 6190 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 145:64910690c574 6191 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6192 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 145:64910690c574 6193 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 145:64910690c574 6194 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6195 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 145:64910690c574 6196 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 145:64910690c574 6197 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6198 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 145:64910690c574 6199 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 145:64910690c574 6200 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6201 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 145:64910690c574 6202 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 145:64910690c574 6203 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6204 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 145:64910690c574 6205 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 145:64910690c574 6206 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6207 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 145:64910690c574 6208 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 145:64910690c574 6209 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6210 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 145:64910690c574 6211 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 145:64910690c574 6212 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 6213 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 145:64910690c574 6214 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 145:64910690c574 6215 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 6216 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 128:9bcdf88f62b0 6217
<> 128:9bcdf88f62b0 6218 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 145:64910690c574 6219 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 145:64910690c574 6220 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6221 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 145:64910690c574 6222 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 145:64910690c574 6223 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6224 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 145:64910690c574 6225 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 145:64910690c574 6226 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6227 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 145:64910690c574 6228 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 145:64910690c574 6229 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6230 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 145:64910690c574 6231 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 145:64910690c574 6232 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6233 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 145:64910690c574 6234 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 145:64910690c574 6235 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6236 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 145:64910690c574 6237 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 145:64910690c574 6238 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6239 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 145:64910690c574 6240 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 145:64910690c574 6241 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6242 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 145:64910690c574 6243 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 145:64910690c574 6244 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6245 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 145:64910690c574 6246 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 145:64910690c574 6247 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6248 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 145:64910690c574 6249 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 145:64910690c574 6250 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6251 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 145:64910690c574 6252 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 145:64910690c574 6253 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6254 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 128:9bcdf88f62b0 6255
<> 128:9bcdf88f62b0 6256 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 145:64910690c574 6257 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 145:64910690c574 6258 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6259 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 145:64910690c574 6260 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 145:64910690c574 6261 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6262 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 145:64910690c574 6263 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 145:64910690c574 6264 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6265 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 145:64910690c574 6266 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 145:64910690c574 6267 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6268 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 145:64910690c574 6269 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 145:64910690c574 6270 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6271 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 145:64910690c574 6272 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 145:64910690c574 6273 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6274 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 145:64910690c574 6275 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 145:64910690c574 6276 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6277 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 145:64910690c574 6278 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 145:64910690c574 6279 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6280 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 128:9bcdf88f62b0 6281
<> 128:9bcdf88f62b0 6282 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 145:64910690c574 6283 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 145:64910690c574 6284 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 6285 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 145:64910690c574 6286 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6287 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6288
AnnaBridge 145:64910690c574 6289 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 145:64910690c574 6290 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6291 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 145:64910690c574 6292 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 145:64910690c574 6293 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6294 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 145:64910690c574 6295
AnnaBridge 145:64910690c574 6296 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 145:64910690c574 6297 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 6298 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 145:64910690c574 6299 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6300 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6301 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6302
AnnaBridge 145:64910690c574 6303 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 145:64910690c574 6304 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6305 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 145:64910690c574 6306
AnnaBridge 145:64910690c574 6307 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 145:64910690c574 6308 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 6309 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 145:64910690c574 6310 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6311 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 145:64910690c574 6312
AnnaBridge 145:64910690c574 6313 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 145:64910690c574 6314 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6315 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 145:64910690c574 6316 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 145:64910690c574 6317 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6318 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 145:64910690c574 6319
AnnaBridge 145:64910690c574 6320 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 145:64910690c574 6321 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 6322 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 145:64910690c574 6323 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6324 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6325 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 145:64910690c574 6326
AnnaBridge 145:64910690c574 6327 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 145:64910690c574 6328 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6329 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 128:9bcdf88f62b0 6330
<> 128:9bcdf88f62b0 6331 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 6332
AnnaBridge 145:64910690c574 6333 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 145:64910690c574 6334 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 6335 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 145:64910690c574 6336 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6337 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6338
AnnaBridge 145:64910690c574 6339 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 145:64910690c574 6340 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 6341 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 145:64910690c574 6342 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6343 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6344 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6345 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6346
AnnaBridge 145:64910690c574 6347 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 145:64910690c574 6348 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 6349 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 145:64910690c574 6350 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 145:64910690c574 6351 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 145:64910690c574 6352
AnnaBridge 145:64910690c574 6353 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 145:64910690c574 6354 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 6355 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 145:64910690c574 6356 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6357 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6358 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 145:64910690c574 6359 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
<> 128:9bcdf88f62b0 6360
<> 128:9bcdf88f62b0 6361 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 145:64910690c574 6362 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 145:64910690c574 6363 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 6364 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 145:64910690c574 6365 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6366 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6367
AnnaBridge 145:64910690c574 6368 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 145:64910690c574 6369 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6370 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 145:64910690c574 6371 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 145:64910690c574 6372 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6373 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 145:64910690c574 6374
AnnaBridge 145:64910690c574 6375 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 145:64910690c574 6376 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 6377 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 145:64910690c574 6378 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6379 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6380 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6381
AnnaBridge 145:64910690c574 6382 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 145:64910690c574 6383 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6384 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 145:64910690c574 6385
AnnaBridge 145:64910690c574 6386 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 145:64910690c574 6387 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 6388 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 145:64910690c574 6389 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6390 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 145:64910690c574 6391
AnnaBridge 145:64910690c574 6392 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 145:64910690c574 6393 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6394 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 145:64910690c574 6395 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 145:64910690c574 6396 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6397 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 145:64910690c574 6398
AnnaBridge 145:64910690c574 6399 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 145:64910690c574 6400 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 145:64910690c574 6401 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 145:64910690c574 6402 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6403 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6404 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 145:64910690c574 6405
AnnaBridge 145:64910690c574 6406 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 145:64910690c574 6407 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6408 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 128:9bcdf88f62b0 6409
<> 128:9bcdf88f62b0 6410 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 6411
AnnaBridge 145:64910690c574 6412 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 145:64910690c574 6413 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 145:64910690c574 6414 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 145:64910690c574 6415 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6416 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6417
AnnaBridge 145:64910690c574 6418 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 145:64910690c574 6419 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 145:64910690c574 6420 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 145:64910690c574 6421 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6422 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6423 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6424 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6425
AnnaBridge 145:64910690c574 6426 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 145:64910690c574 6427 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 6428 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 145:64910690c574 6429 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 145:64910690c574 6430 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 145:64910690c574 6431
AnnaBridge 145:64910690c574 6432 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 145:64910690c574 6433 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 145:64910690c574 6434 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 145:64910690c574 6435 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6436 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6437 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 145:64910690c574 6438 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
<> 128:9bcdf88f62b0 6439
<> 128:9bcdf88f62b0 6440 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 145:64910690c574 6441 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 145:64910690c574 6442 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6443 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 145:64910690c574 6444 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 145:64910690c574 6445 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6446 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 145:64910690c574 6447 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 145:64910690c574 6448 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6449 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 145:64910690c574 6450 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 145:64910690c574 6451 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6452 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 145:64910690c574 6453 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 145:64910690c574 6454 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6455 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 145:64910690c574 6456 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 145:64910690c574 6457 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6458 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 145:64910690c574 6459 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 145:64910690c574 6460 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6461 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 145:64910690c574 6462 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 145:64910690c574 6463 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6464 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 145:64910690c574 6465 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 145:64910690c574 6466 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6467 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 145:64910690c574 6468 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 145:64910690c574 6469 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6470 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 145:64910690c574 6471 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 145:64910690c574 6472 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6473 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 145:64910690c574 6474 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 145:64910690c574 6475 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6476 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 145:64910690c574 6477 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 145:64910690c574 6478 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6479 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 145:64910690c574 6480 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 145:64910690c574 6481 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 6482 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 145:64910690c574 6483 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 145:64910690c574 6484 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6485 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 128:9bcdf88f62b0 6486
<> 128:9bcdf88f62b0 6487 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 145:64910690c574 6488 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 145:64910690c574 6489 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 6490 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 128:9bcdf88f62b0 6491
<> 128:9bcdf88f62b0 6492 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 145:64910690c574 6493 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 145:64910690c574 6494 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6495 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 128:9bcdf88f62b0 6496
<> 128:9bcdf88f62b0 6497 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 145:64910690c574 6498 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 145:64910690c574 6499 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 6500 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 128:9bcdf88f62b0 6501
<> 128:9bcdf88f62b0 6502 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 145:64910690c574 6503 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 145:64910690c574 6504 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 6505 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 128:9bcdf88f62b0 6506
<> 128:9bcdf88f62b0 6507 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 145:64910690c574 6508 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 145:64910690c574 6509 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6510 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 128:9bcdf88f62b0 6511
<> 128:9bcdf88f62b0 6512 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 145:64910690c574 6513 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 145:64910690c574 6514 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6515 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 128:9bcdf88f62b0 6516
<> 128:9bcdf88f62b0 6517 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 145:64910690c574 6518 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 145:64910690c574 6519 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6520 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 128:9bcdf88f62b0 6521
<> 128:9bcdf88f62b0 6522 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 145:64910690c574 6523 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 145:64910690c574 6524 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6525 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 128:9bcdf88f62b0 6526
<> 128:9bcdf88f62b0 6527 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 145:64910690c574 6528 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 145:64910690c574 6529 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 6530 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 145:64910690c574 6531 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6532 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6533 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6534 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6535 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6536 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6537 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6538 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6539
AnnaBridge 145:64910690c574 6540 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 145:64910690c574 6541 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 145:64910690c574 6542 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 145:64910690c574 6543 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6544 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 145:64910690c574 6545
AnnaBridge 145:64910690c574 6546 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 145:64910690c574 6547 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6548 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 145:64910690c574 6549 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 145:64910690c574 6550 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6551 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 145:64910690c574 6552 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 145:64910690c574 6553 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6554 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 145:64910690c574 6555 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 145:64910690c574 6556 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 6557 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 145:64910690c574 6558 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 145:64910690c574 6559 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 6560 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 145:64910690c574 6561 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 145:64910690c574 6562 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6563 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 128:9bcdf88f62b0 6564
<> 128:9bcdf88f62b0 6565 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 145:64910690c574 6566 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 145:64910690c574 6567 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 145:64910690c574 6568 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 145:64910690c574 6569 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6570 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6571 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6572 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6573 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6574
AnnaBridge 145:64910690c574 6575 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 145:64910690c574 6576 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 145:64910690c574 6577 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 145:64910690c574 6578 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 145:64910690c574 6579 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 145:64910690c574 6580 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 145:64910690c574 6581 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 145:64910690c574 6582 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
<> 128:9bcdf88f62b0 6583
<> 128:9bcdf88f62b0 6584 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 145:64910690c574 6585 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 145:64910690c574 6586 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 6587 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 128:9bcdf88f62b0 6588
<> 128:9bcdf88f62b0 6589 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 145:64910690c574 6590 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 145:64910690c574 6591 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 6592 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 145:64910690c574 6593 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6594 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6595
AnnaBridge 145:64910690c574 6596 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 145:64910690c574 6597 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 6598 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 145:64910690c574 6599 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6600 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6601 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 145:64910690c574 6602 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 6603 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 145:64910690c574 6604 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 145:64910690c574 6605 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
<> 128:9bcdf88f62b0 6606
<> 128:9bcdf88f62b0 6607
<> 128:9bcdf88f62b0 6608 /******************************************************************************/
<> 128:9bcdf88f62b0 6609 /* */
<> 128:9bcdf88f62b0 6610 /* Universal Synchronous Asynchronous Receiver Transmitter */
<> 128:9bcdf88f62b0 6611 /* */
<> 128:9bcdf88f62b0 6612 /******************************************************************************/
<> 128:9bcdf88f62b0 6613 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 145:64910690c574 6614 #define USART_SR_PE_Pos (0U)
AnnaBridge 145:64910690c574 6615 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6616 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 145:64910690c574 6617 #define USART_SR_FE_Pos (1U)
AnnaBridge 145:64910690c574 6618 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6619 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 145:64910690c574 6620 #define USART_SR_NE_Pos (2U)
AnnaBridge 145:64910690c574 6621 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6622 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 145:64910690c574 6623 #define USART_SR_ORE_Pos (3U)
AnnaBridge 145:64910690c574 6624 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6625 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 145:64910690c574 6626 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 145:64910690c574 6627 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6628 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 145:64910690c574 6629 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 145:64910690c574 6630 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6631 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 145:64910690c574 6632 #define USART_SR_TC_Pos (6U)
AnnaBridge 145:64910690c574 6633 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6634 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 145:64910690c574 6635 #define USART_SR_TXE_Pos (7U)
AnnaBridge 145:64910690c574 6636 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6637 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 145:64910690c574 6638 #define USART_SR_LBD_Pos (8U)
AnnaBridge 145:64910690c574 6639 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6640 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 145:64910690c574 6641 #define USART_SR_CTS_Pos (9U)
AnnaBridge 145:64910690c574 6642 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6643 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
<> 128:9bcdf88f62b0 6644
<> 128:9bcdf88f62b0 6645 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 145:64910690c574 6646 #define USART_DR_DR_Pos (0U)
AnnaBridge 145:64910690c574 6647 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 145:64910690c574 6648 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
<> 128:9bcdf88f62b0 6649
<> 128:9bcdf88f62b0 6650 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 145:64910690c574 6651 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 145:64910690c574 6652 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 6653 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 145:64910690c574 6654 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 145:64910690c574 6655 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 145:64910690c574 6656 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
<> 128:9bcdf88f62b0 6657
<> 128:9bcdf88f62b0 6658 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 145:64910690c574 6659 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 145:64910690c574 6660 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6661 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 145:64910690c574 6662 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 145:64910690c574 6663 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6664 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 145:64910690c574 6665 #define USART_CR1_RE_Pos (2U)
AnnaBridge 145:64910690c574 6666 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6667 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 145:64910690c574 6668 #define USART_CR1_TE_Pos (3U)
AnnaBridge 145:64910690c574 6669 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6670 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 145:64910690c574 6671 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 145:64910690c574 6672 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6673 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 145:64910690c574 6674 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 145:64910690c574 6675 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6676 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 145:64910690c574 6677 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 145:64910690c574 6678 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6679 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 145:64910690c574 6680 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 145:64910690c574 6681 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6682 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 145:64910690c574 6683 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 145:64910690c574 6684 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6685 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 145:64910690c574 6686 #define USART_CR1_PS_Pos (9U)
AnnaBridge 145:64910690c574 6687 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6688 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 145:64910690c574 6689 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 145:64910690c574 6690 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6691 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 145:64910690c574 6692 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 145:64910690c574 6693 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6694 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 145:64910690c574 6695 #define USART_CR1_M_Pos (12U)
AnnaBridge 145:64910690c574 6696 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6697 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 145:64910690c574 6698 #define USART_CR1_UE_Pos (13U)
AnnaBridge 145:64910690c574 6699 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 6700 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 145:64910690c574 6701 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 145:64910690c574 6702 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 6703 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
<> 128:9bcdf88f62b0 6704
<> 128:9bcdf88f62b0 6705 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 145:64910690c574 6706 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 145:64910690c574 6707 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 6708 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 145:64910690c574 6709 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 145:64910690c574 6710 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6711 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 145:64910690c574 6712 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 145:64910690c574 6713 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6714 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 145:64910690c574 6715 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 145:64910690c574 6716 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6717 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 145:64910690c574 6718 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 145:64910690c574 6719 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6720 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 145:64910690c574 6721 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 145:64910690c574 6722 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6723 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 145:64910690c574 6724 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 145:64910690c574 6725 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6726 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 145:64910690c574 6727
AnnaBridge 145:64910690c574 6728 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 145:64910690c574 6729 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 145:64910690c574 6730 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 145:64910690c574 6731 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 145:64910690c574 6732 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 145:64910690c574 6733
AnnaBridge 145:64910690c574 6734 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 145:64910690c574 6735 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 6736 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
<> 128:9bcdf88f62b0 6737
<> 128:9bcdf88f62b0 6738 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 145:64910690c574 6739 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 145:64910690c574 6740 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6741 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 145:64910690c574 6742 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 145:64910690c574 6743 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6744 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 145:64910690c574 6745 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 145:64910690c574 6746 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6747 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 145:64910690c574 6748 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 145:64910690c574 6749 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6750 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 145:64910690c574 6751 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 145:64910690c574 6752 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 6753 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 145:64910690c574 6754 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 145:64910690c574 6755 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6756 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 145:64910690c574 6757 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 145:64910690c574 6758 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6759 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 145:64910690c574 6760 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 145:64910690c574 6761 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6762 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 145:64910690c574 6763 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 145:64910690c574 6764 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6765 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 145:64910690c574 6766 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 145:64910690c574 6767 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6768 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 145:64910690c574 6769 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 145:64910690c574 6770 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6771 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 145:64910690c574 6772 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 145:64910690c574 6773 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6774 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
<> 128:9bcdf88f62b0 6775
<> 128:9bcdf88f62b0 6776 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 145:64910690c574 6777 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 145:64910690c574 6778 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 145:64910690c574 6779 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 145:64910690c574 6780 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6781 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6782 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6783 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6784 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6785 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6786 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 145:64910690c574 6787 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6788
AnnaBridge 145:64910690c574 6789 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 145:64910690c574 6790 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 145:64910690c574 6791 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
<> 128:9bcdf88f62b0 6792
<> 128:9bcdf88f62b0 6793 /******************************************************************************/
<> 128:9bcdf88f62b0 6794 /* */
<> 128:9bcdf88f62b0 6795 /* Window WATCHDOG */
<> 128:9bcdf88f62b0 6796 /* */
<> 128:9bcdf88f62b0 6797 /******************************************************************************/
<> 128:9bcdf88f62b0 6798 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 145:64910690c574 6799 #define WWDG_CR_T_Pos (0U)
AnnaBridge 145:64910690c574 6800 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 145:64910690c574 6801 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 145:64910690c574 6802 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 145:64910690c574 6803 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 145:64910690c574 6804 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 145:64910690c574 6805 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 145:64910690c574 6806 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 145:64910690c574 6807 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 145:64910690c574 6808 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
<> 128:9bcdf88f62b0 6809 /* Legacy defines */
<> 128:9bcdf88f62b0 6810 #define WWDG_CR_T0 WWDG_CR_T_0
<> 128:9bcdf88f62b0 6811 #define WWDG_CR_T1 WWDG_CR_T_1
<> 128:9bcdf88f62b0 6812 #define WWDG_CR_T2 WWDG_CR_T_2
<> 128:9bcdf88f62b0 6813 #define WWDG_CR_T3 WWDG_CR_T_3
<> 128:9bcdf88f62b0 6814 #define WWDG_CR_T4 WWDG_CR_T_4
<> 128:9bcdf88f62b0 6815 #define WWDG_CR_T5 WWDG_CR_T_5
<> 128:9bcdf88f62b0 6816 #define WWDG_CR_T6 WWDG_CR_T_6
<> 128:9bcdf88f62b0 6817
AnnaBridge 145:64910690c574 6818 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 145:64910690c574 6819 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 6820 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
<> 128:9bcdf88f62b0 6821
<> 128:9bcdf88f62b0 6822 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 145:64910690c574 6823 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 145:64910690c574 6824 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 145:64910690c574 6825 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 145:64910690c574 6826 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 145:64910690c574 6827 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 145:64910690c574 6828 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 145:64910690c574 6829 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 145:64910690c574 6830 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 145:64910690c574 6831 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 145:64910690c574 6832 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
<> 128:9bcdf88f62b0 6833 /* Legacy defines */
<> 128:9bcdf88f62b0 6834 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 128:9bcdf88f62b0 6835 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 128:9bcdf88f62b0 6836 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 128:9bcdf88f62b0 6837 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 128:9bcdf88f62b0 6838 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 128:9bcdf88f62b0 6839 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 128:9bcdf88f62b0 6840 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 128:9bcdf88f62b0 6841
AnnaBridge 145:64910690c574 6842 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 145:64910690c574 6843 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 145:64910690c574 6844 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 145:64910690c574 6845 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 145:64910690c574 6846 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
<> 128:9bcdf88f62b0 6847 /* Legacy defines */
<> 128:9bcdf88f62b0 6848 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 128:9bcdf88f62b0 6849 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 128:9bcdf88f62b0 6850
AnnaBridge 145:64910690c574 6851 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 145:64910690c574 6852 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6853 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
<> 128:9bcdf88f62b0 6854
<> 128:9bcdf88f62b0 6855 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 145:64910690c574 6856 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 145:64910690c574 6857 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6858 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
<> 128:9bcdf88f62b0 6859
<> 128:9bcdf88f62b0 6860
<> 128:9bcdf88f62b0 6861 /******************************************************************************/
<> 128:9bcdf88f62b0 6862 /* */
<> 128:9bcdf88f62b0 6863 /* DBG */
<> 128:9bcdf88f62b0 6864 /* */
<> 128:9bcdf88f62b0 6865 /******************************************************************************/
<> 128:9bcdf88f62b0 6866 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 145:64910690c574 6867 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 145:64910690c574 6868 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 6869 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 145:64910690c574 6870 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 145:64910690c574 6871 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 6872 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
<> 128:9bcdf88f62b0 6873
<> 128:9bcdf88f62b0 6874 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 145:64910690c574 6875 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 145:64910690c574 6876 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6877 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 145:64910690c574 6878 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 145:64910690c574 6879 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6880 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 145:64910690c574 6881 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 145:64910690c574 6882 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6883 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 145:64910690c574 6884 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 145:64910690c574 6885 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 6886 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 145:64910690c574 6887
AnnaBridge 145:64910690c574 6888 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 145:64910690c574 6889 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 145:64910690c574 6890 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 145:64910690c574 6891 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 6892 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6893
<> 128:9bcdf88f62b0 6894 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 145:64910690c574 6895 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 145:64910690c574 6896 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6897 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 145:64910690c574 6898 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 145:64910690c574 6899 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6900 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 145:64910690c574 6901 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 145:64910690c574 6902 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6903 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 145:64910690c574 6904 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 145:64910690c574 6905 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 6906 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 145:64910690c574 6907 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 145:64910690c574 6908 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6909 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 145:64910690c574 6910 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 145:64910690c574 6911 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6912 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 145:64910690c574 6913 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 145:64910690c574 6914 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 6915 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 145:64910690c574 6916 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 145:64910690c574 6917 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 6918 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 145:64910690c574 6919 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 145:64910690c574 6920 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 6921 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 145:64910690c574 6922 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 145:64910690c574 6923 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 6924 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
<> 128:9bcdf88f62b0 6925 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 6926 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
<> 128:9bcdf88f62b0 6927
<> 128:9bcdf88f62b0 6928 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 145:64910690c574 6929 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 145:64910690c574 6930 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6931 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 145:64910690c574 6932 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 145:64910690c574 6933 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 6934 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 145:64910690c574 6935 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 145:64910690c574 6936 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 6937 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 145:64910690c574 6938 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 145:64910690c574 6939 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 6940 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
<> 128:9bcdf88f62b0 6941
<> 128:9bcdf88f62b0 6942 /******************************************************************************/
<> 128:9bcdf88f62b0 6943 /* */
AnnaBridge 145:64910690c574 6944 /* USB_OTG */
<> 128:9bcdf88f62b0 6945 /* */
<> 128:9bcdf88f62b0 6946 /******************************************************************************/
AnnaBridge 145:64910690c574 6947 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 145:64910690c574 6948 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 145:64910690c574 6949 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6950 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 145:64910690c574 6951 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 145:64910690c574 6952 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6953 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 145:64910690c574 6954 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 145:64910690c574 6955 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 6956 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 145:64910690c574 6957 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 145:64910690c574 6958 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 6959 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 145:64910690c574 6960 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 145:64910690c574 6961 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 6962 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 145:64910690c574 6963 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 145:64910690c574 6964 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 6965 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 145:64910690c574 6966 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 145:64910690c574 6967 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 6968 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 145:64910690c574 6969 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 145:64910690c574 6970 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 6971 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 145:64910690c574 6972 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 145:64910690c574 6973 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 6974 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 145:64910690c574 6975 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
AnnaBridge 145:64910690c574 6976 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 6977 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
<> 128:9bcdf88f62b0 6978
<> 128:9bcdf88f62b0 6979 /******************** Bit definition forUSB_OTG_HCFG register ********************/
<> 128:9bcdf88f62b0 6980
AnnaBridge 145:64910690c574 6981 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 145:64910690c574 6982 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 6983 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 145:64910690c574 6984 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6985 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6986 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 145:64910690c574 6987 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6988 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 145:64910690c574 6989
AnnaBridge 145:64910690c574 6990 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 145:64910690c574 6991
AnnaBridge 145:64910690c574 6992 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 145:64910690c574 6993 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 145:64910690c574 6994 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 145:64910690c574 6995 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 6996 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 6997 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 145:64910690c574 6998 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 6999 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 145:64910690c574 7000
AnnaBridge 145:64910690c574 7001 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 145:64910690c574 7002 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 145:64910690c574 7003 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 145:64910690c574 7004 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7005 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7006 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7007 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7008 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7009 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7010 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7011
AnnaBridge 145:64910690c574 7012 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 145:64910690c574 7013 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 145:64910690c574 7014 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 145:64910690c574 7015 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7016 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7017
AnnaBridge 145:64910690c574 7018 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 145:64910690c574 7019 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 145:64910690c574 7020 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 145:64910690c574 7021 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7022 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7023
AnnaBridge 145:64910690c574 7024 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 145:64910690c574 7025 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 145:64910690c574 7026 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7027 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 145:64910690c574 7028 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 145:64910690c574 7029 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7030 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 145:64910690c574 7031 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 145:64910690c574 7032 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7033 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 145:64910690c574 7034
AnnaBridge 145:64910690c574 7035 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 145:64910690c574 7036 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 145:64910690c574 7037 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7038 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 145:64910690c574 7039 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 145:64910690c574 7040 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7041 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 145:64910690c574 7042 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 145:64910690c574 7043 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7044 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 145:64910690c574 7045 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 145:64910690c574 7046 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7047 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 145:64910690c574 7048 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 145:64910690c574 7049 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7050 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 145:64910690c574 7051 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 145:64910690c574 7052 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7053 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 145:64910690c574 7054
AnnaBridge 145:64910690c574 7055 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 145:64910690c574 7056 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 145:64910690c574 7057 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7058 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 145:64910690c574 7059 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 145:64910690c574 7060 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7061 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 145:64910690c574 7062 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 145:64910690c574 7063 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7064 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 145:64910690c574 7065 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 145:64910690c574 7066 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7067 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 145:64910690c574 7068
AnnaBridge 145:64910690c574 7069 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 145:64910690c574 7070 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 145:64910690c574 7071 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 145:64910690c574 7072 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7073 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7074 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7075 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 145:64910690c574 7076 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7077 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 145:64910690c574 7078 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 145:64910690c574 7079 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7080 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 145:64910690c574 7081 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 145:64910690c574 7082 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7083 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 145:64910690c574 7084 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 145:64910690c574 7085 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7086 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 145:64910690c574 7087 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 145:64910690c574 7088 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7089 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 145:64910690c574 7090
AnnaBridge 145:64910690c574 7091 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 145:64910690c574 7092 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 145:64910690c574 7093 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7094 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 145:64910690c574 7095
AnnaBridge 145:64910690c574 7096 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 145:64910690c574 7097 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 145:64910690c574 7098 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7099 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 145:64910690c574 7100 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 145:64910690c574 7101 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7102 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 145:64910690c574 7103
AnnaBridge 145:64910690c574 7104 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 145:64910690c574 7105 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 145:64910690c574 7106 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7107 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 145:64910690c574 7108
AnnaBridge 145:64910690c574 7109 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 145:64910690c574 7110 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 145:64910690c574 7111 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 145:64910690c574 7112 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7113 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7114 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 145:64910690c574 7115 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7116 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 145:64910690c574 7117 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 145:64910690c574 7118 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 145:64910690c574 7119 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 145:64910690c574 7120
AnnaBridge 145:64910690c574 7121 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 145:64910690c574 7122 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 145:64910690c574 7123 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7124 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 145:64910690c574 7125 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 145:64910690c574 7126 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 145:64910690c574 7127 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 145:64910690c574 7128 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 145:64910690c574 7129 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 145:64910690c574 7130 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 145:64910690c574 7131 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 145:64910690c574 7132 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 145:64910690c574 7133 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 145:64910690c574 7134 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7135 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 145:64910690c574 7136 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 145:64910690c574 7137 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7138 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 145:64910690c574 7139 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 145:64910690c574 7140 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7141 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 145:64910690c574 7142
AnnaBridge 145:64910690c574 7143 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 145:64910690c574 7144
AnnaBridge 145:64910690c574 7145 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 145:64910690c574 7146 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 145:64910690c574 7147 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 145:64910690c574 7148 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7149 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7150 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7151 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 145:64910690c574 7152 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7153 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 145:64910690c574 7154 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 145:64910690c574 7155 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7156 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 145:64910690c574 7157 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 145:64910690c574 7158 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7159 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 145:64910690c574 7160 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 145:64910690c574 7161 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 145:64910690c574 7162 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 145:64910690c574 7163 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7164 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7165 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7166 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7167 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 145:64910690c574 7168 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7169 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 145:64910690c574 7170 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 145:64910690c574 7171 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7172 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 145:64910690c574 7173 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 145:64910690c574 7174 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7175 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 145:64910690c574 7176 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 145:64910690c574 7177 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7178 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 145:64910690c574 7179 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 145:64910690c574 7180 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7181 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 145:64910690c574 7182 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 145:64910690c574 7183 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7184 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 145:64910690c574 7185 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 145:64910690c574 7186 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7187 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 145:64910690c574 7188 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 145:64910690c574 7189 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7190 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 145:64910690c574 7191 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 145:64910690c574 7192 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7193 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 145:64910690c574 7194 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 145:64910690c574 7195 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7196 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 145:64910690c574 7197 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 145:64910690c574 7198 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7199 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 145:64910690c574 7200 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 145:64910690c574 7201 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7202 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 145:64910690c574 7203 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 145:64910690c574 7204 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7205 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 145:64910690c574 7206
AnnaBridge 145:64910690c574 7207 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 145:64910690c574 7208 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 145:64910690c574 7209 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7210 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 145:64910690c574 7211 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 145:64910690c574 7212 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7213 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 145:64910690c574 7214 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 145:64910690c574 7215 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7216 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 145:64910690c574 7217 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 145:64910690c574 7218 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7219 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 145:64910690c574 7220 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 145:64910690c574 7221 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7222 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 145:64910690c574 7223
AnnaBridge 145:64910690c574 7224
AnnaBridge 145:64910690c574 7225 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 145:64910690c574 7226 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 145:64910690c574 7227 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 145:64910690c574 7228 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7229 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7230 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7231 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7232 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7233 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 145:64910690c574 7234 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7235 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 145:64910690c574 7236 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 145:64910690c574 7237 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7238 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 145:64910690c574 7239
AnnaBridge 145:64910690c574 7240 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 145:64910690c574 7241 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 145:64910690c574 7242 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7243 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 145:64910690c574 7244 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 145:64910690c574 7245 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7246 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 145:64910690c574 7247 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 145:64910690c574 7248 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7249 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 145:64910690c574 7250 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 145:64910690c574 7251 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7252 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 145:64910690c574 7253 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 145:64910690c574 7254 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7255 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 145:64910690c574 7256 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 145:64910690c574 7257 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7258 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 145:64910690c574 7259 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 145:64910690c574 7260 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7261 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 145:64910690c574 7262 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 145:64910690c574 7263 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7264 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 145:64910690c574 7265
AnnaBridge 145:64910690c574 7266 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 145:64910690c574 7267 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 145:64910690c574 7268 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7269 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 145:64910690c574 7270 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 145:64910690c574 7271 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 145:64910690c574 7272 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 145:64910690c574 7273 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7274 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7275 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7276 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7277 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7278 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7279 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7280 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7281
AnnaBridge 145:64910690c574 7282 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 145:64910690c574 7283 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 145:64910690c574 7284 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 145:64910690c574 7285 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7286 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7287 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7288 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 7289 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7290 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7291 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7292 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7293
AnnaBridge 145:64910690c574 7294 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 145:64910690c574 7295 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 145:64910690c574 7296 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7297 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 145:64910690c574 7298
AnnaBridge 145:64910690c574 7299 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 145:64910690c574 7300 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 145:64910690c574 7301 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7302 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 145:64910690c574 7303 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 145:64910690c574 7304 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7305 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 145:64910690c574 7306 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 145:64910690c574 7307 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7308 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 145:64910690c574 7309 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 145:64910690c574 7310 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7311 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 145:64910690c574 7312 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 145:64910690c574 7313 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7314 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 145:64910690c574 7315 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 145:64910690c574 7316 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7317 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 145:64910690c574 7318 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 145:64910690c574 7319 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7320 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 145:64910690c574 7321
AnnaBridge 145:64910690c574 7322 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 145:64910690c574 7323 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 145:64910690c574 7324 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7325 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 145:64910690c574 7326 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 145:64910690c574 7327 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7328 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 145:64910690c574 7329 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 145:64910690c574 7330 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7331 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 145:64910690c574 7332 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 145:64910690c574 7333 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7334 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 145:64910690c574 7335 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 145:64910690c574 7336 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7337 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 145:64910690c574 7338 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 145:64910690c574 7339 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7340 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 145:64910690c574 7341 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 145:64910690c574 7342 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7343 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 145:64910690c574 7344 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 145:64910690c574 7345 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7346 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 145:64910690c574 7347 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 145:64910690c574 7348 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7349 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 145:64910690c574 7350 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 145:64910690c574 7351 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7352 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 145:64910690c574 7353 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 145:64910690c574 7354 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7355 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 145:64910690c574 7356 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 145:64910690c574 7357 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7358 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 145:64910690c574 7359 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 145:64910690c574 7360 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7361 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 145:64910690c574 7362 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 145:64910690c574 7363 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7364 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 145:64910690c574 7365 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 145:64910690c574 7366 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7367 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 145:64910690c574 7368 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 145:64910690c574 7369 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7370 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 145:64910690c574 7371 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 145:64910690c574 7372 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7373 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 145:64910690c574 7374 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 145:64910690c574 7375 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7376 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 145:64910690c574 7377 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 145:64910690c574 7378 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7379 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 145:64910690c574 7380 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 145:64910690c574 7381 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7382 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 145:64910690c574 7383 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 145:64910690c574 7384 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7385 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 145:64910690c574 7386 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 145:64910690c574 7387 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7388 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 145:64910690c574 7389 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 145:64910690c574 7390 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7391 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 145:64910690c574 7392 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 145:64910690c574 7393 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7394 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 145:64910690c574 7395 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 145:64910690c574 7396 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7397 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 145:64910690c574 7398 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 145:64910690c574 7399 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7400 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 145:64910690c574 7401
AnnaBridge 145:64910690c574 7402 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 145:64910690c574 7403 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 145:64910690c574 7404 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7405 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 145:64910690c574 7406 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 145:64910690c574 7407 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7408 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 145:64910690c574 7409 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 145:64910690c574 7410 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7411 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 145:64910690c574 7412 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 145:64910690c574 7413 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7414 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 145:64910690c574 7415 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 145:64910690c574 7416 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7417 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 145:64910690c574 7418 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 145:64910690c574 7419 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7420 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 145:64910690c574 7421 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 145:64910690c574 7422 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7423 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 145:64910690c574 7424 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 145:64910690c574 7425 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7426 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 145:64910690c574 7427 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 145:64910690c574 7428 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7429 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 145:64910690c574 7430 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 145:64910690c574 7431 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7432 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 145:64910690c574 7433 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 145:64910690c574 7434 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7435 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 145:64910690c574 7436 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 145:64910690c574 7437 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7438 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 145:64910690c574 7439 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 145:64910690c574 7440 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7441 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 145:64910690c574 7442 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 145:64910690c574 7443 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7444 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 145:64910690c574 7445 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 145:64910690c574 7446 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7447 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 145:64910690c574 7448 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 145:64910690c574 7449 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7450 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 145:64910690c574 7451 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 145:64910690c574 7452 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7453 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 145:64910690c574 7454 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 145:64910690c574 7455 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7456 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 145:64910690c574 7457 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 145:64910690c574 7458 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7459 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 145:64910690c574 7460 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 145:64910690c574 7461 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7462 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 145:64910690c574 7463 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 145:64910690c574 7464 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7465 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 145:64910690c574 7466 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 145:64910690c574 7467 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7468 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 145:64910690c574 7469 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 145:64910690c574 7470 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7471 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 145:64910690c574 7472 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 145:64910690c574 7473 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7474 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 145:64910690c574 7475 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 145:64910690c574 7476 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7477 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 145:64910690c574 7478 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 145:64910690c574 7479 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7480 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 145:64910690c574 7481
AnnaBridge 145:64910690c574 7482 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 145:64910690c574 7483 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 145:64910690c574 7484 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7485 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 145:64910690c574 7486 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 145:64910690c574 7487 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7488 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 145:64910690c574 7489
AnnaBridge 145:64910690c574 7490 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 145:64910690c574 7491 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 145:64910690c574 7492 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7493 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
<> 128:9bcdf88f62b0 7494
<> 128:9bcdf88f62b0 7495 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 145:64910690c574 7496 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 145:64910690c574 7497 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 7498 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 145:64910690c574 7499 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 145:64910690c574 7500 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 145:64910690c574 7501 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 145:64910690c574 7502 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 145:64910690c574 7503 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 145:64910690c574 7504 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 145:64910690c574 7505 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 145:64910690c574 7506 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 145:64910690c574 7507 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 145:64910690c574 7508
AnnaBridge 145:64910690c574 7509 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 145:64910690c574 7510 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 145:64910690c574 7511 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7512 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 145:64910690c574 7513 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 145:64910690c574 7514 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7515 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 7516
<> 128:9bcdf88f62b0 7517 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 7518
AnnaBridge 145:64910690c574 7519 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 145:64910690c574 7520 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 7521 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 145:64910690c574 7522 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7523 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7524 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7525 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7526 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 145:64910690c574 7527 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 145:64910690c574 7528 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 145:64910690c574 7529
AnnaBridge 145:64910690c574 7530 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 145:64910690c574 7531 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 145:64910690c574 7532 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 145:64910690c574 7533 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7534 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7535
AnnaBridge 145:64910690c574 7536 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 145:64910690c574 7537 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 145:64910690c574 7538 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 145:64910690c574 7539 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7540 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7541 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7542 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7543
AnnaBridge 145:64910690c574 7544 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 145:64910690c574 7545 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 7546 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 145:64910690c574 7547 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7548 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7549 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7550 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7551
AnnaBridge 145:64910690c574 7552 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 145:64910690c574 7553 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 145:64910690c574 7554 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 145:64910690c574 7555 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7556 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7557 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7558 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7559
<> 128:9bcdf88f62b0 7560 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 7561
AnnaBridge 145:64910690c574 7562 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 145:64910690c574 7563 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 7564 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 145:64910690c574 7565 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7566 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7567 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7568 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7569 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 145:64910690c574 7570 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 145:64910690c574 7571 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 145:64910690c574 7572
AnnaBridge 145:64910690c574 7573 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 145:64910690c574 7574 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 145:64910690c574 7575 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 145:64910690c574 7576 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7577 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7578
AnnaBridge 145:64910690c574 7579 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 145:64910690c574 7580 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 145:64910690c574 7581 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 145:64910690c574 7582 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7583 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7584 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7585 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7586
AnnaBridge 145:64910690c574 7587 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 145:64910690c574 7588 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 145:64910690c574 7589 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 145:64910690c574 7590 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7591 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7592 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7593 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7594
AnnaBridge 145:64910690c574 7595 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 145:64910690c574 7596 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 145:64910690c574 7597 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 145:64910690c574 7598 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7599 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7600 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7601 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7602
AnnaBridge 145:64910690c574 7603 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 145:64910690c574 7604 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 145:64910690c574 7605 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7606 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 145:64910690c574 7607
AnnaBridge 145:64910690c574 7608 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 145:64910690c574 7609 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 145:64910690c574 7610 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7611 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
<> 128:9bcdf88f62b0 7612
<> 128:9bcdf88f62b0 7613 /******************** Bit definition for OTG register ********************/
AnnaBridge 145:64910690c574 7614 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 145:64910690c574 7615 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7616 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 145:64910690c574 7617 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 145:64910690c574 7618 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7619 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 145:64910690c574 7620 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 145:64910690c574 7621 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7622 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 145:64910690c574 7623 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 145:64910690c574 7624 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7625 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
<> 128:9bcdf88f62b0 7626
<> 128:9bcdf88f62b0 7627 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 145:64910690c574 7628 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 145:64910690c574 7629 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 145:64910690c574 7630 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 145:64910690c574 7631
AnnaBridge 145:64910690c574 7632 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 145:64910690c574 7633 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 145:64910690c574 7634 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7635 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 145:64910690c574 7636
AnnaBridge 145:64910690c574 7637 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 145:64910690c574 7638 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 145:64910690c574 7639 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 145:64910690c574 7640 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7641 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7642 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7643 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7644 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7645 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7646 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7647 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7648
AnnaBridge 145:64910690c574 7649 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 145:64910690c574 7650 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 145:64910690c574 7651 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 145:64910690c574 7652 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7653 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7654 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7655 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 7656 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7657 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7658 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7659
AnnaBridge 145:64910690c574 7660 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 145:64910690c574 7661 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 145:64910690c574 7662 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7663 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 145:64910690c574 7664 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 145:64910690c574 7665 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7666 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 145:64910690c574 7667
AnnaBridge 145:64910690c574 7668 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 145:64910690c574 7669 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 145:64910690c574 7670 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 145:64910690c574 7671 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7672 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7673 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7674 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7675 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7676 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7677 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7678 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7679 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7680 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 145:64910690c574 7681 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7682 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 145:64910690c574 7683
AnnaBridge 145:64910690c574 7684 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 145:64910690c574 7685 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 145:64910690c574 7686 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 145:64910690c574 7687 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7688 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7689 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7690 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7691 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7692 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7693 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7694 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7695 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7696 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 145:64910690c574 7697 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 7698 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 145:64910690c574 7699
AnnaBridge 145:64910690c574 7700 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 145:64910690c574 7701 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 145:64910690c574 7702 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7703 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 145:64910690c574 7704
AnnaBridge 145:64910690c574 7705 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 145:64910690c574 7706 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 145:64910690c574 7707 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7708 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 145:64910690c574 7709 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 145:64910690c574 7710 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7711 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 145:64910690c574 7712
AnnaBridge 145:64910690c574 7713 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 145:64910690c574 7714 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 145:64910690c574 7715 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7716 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 145:64910690c574 7717 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
AnnaBridge 145:64910690c574 7718 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7719 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
AnnaBridge 145:64910690c574 7720 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
AnnaBridge 145:64910690c574 7721 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7722 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 145:64910690c574 7723 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
AnnaBridge 145:64910690c574 7724 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7725 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 145:64910690c574 7726 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
AnnaBridge 145:64910690c574 7727 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7728 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
AnnaBridge 145:64910690c574 7729 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
AnnaBridge 145:64910690c574 7730 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7731 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
<> 128:9bcdf88f62b0 7732
<> 128:9bcdf88f62b0 7733 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 145:64910690c574 7734 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 145:64910690c574 7735 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7736 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 145:64910690c574 7737 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 145:64910690c574 7738 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7739 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 145:64910690c574 7740
AnnaBridge 145:64910690c574 7741 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 145:64910690c574 7742 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 145:64910690c574 7743 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 7744 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 145:64910690c574 7745
AnnaBridge 145:64910690c574 7746 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 145:64910690c574 7747 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 145:64910690c574 7748 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7749 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 145:64910690c574 7750 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 145:64910690c574 7751 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7752 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 145:64910690c574 7753 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 145:64910690c574 7754 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7755 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 145:64910690c574 7756 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 145:64910690c574 7757 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7758 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 145:64910690c574 7759 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 145:64910690c574 7760 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7761 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 145:64910690c574 7762 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 145:64910690c574 7763 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7764 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 145:64910690c574 7765 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 145:64910690c574 7766 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7767 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 145:64910690c574 7768 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 145:64910690c574 7769 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7770 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 145:64910690c574 7771 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 145:64910690c574 7772 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7773 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 145:64910690c574 7774
AnnaBridge 145:64910690c574 7775 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 145:64910690c574 7776 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 145:64910690c574 7777 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7778 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 145:64910690c574 7779 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 145:64910690c574 7780 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7781 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 145:64910690c574 7782 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 145:64910690c574 7783 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7784 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 145:64910690c574 7785 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 145:64910690c574 7786 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7787 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 145:64910690c574 7788 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 145:64910690c574 7789 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7790 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 145:64910690c574 7791 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 145:64910690c574 7792 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7793 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 145:64910690c574 7794 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 145:64910690c574 7795 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7796 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 145:64910690c574 7797 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 145:64910690c574 7798 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7799 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 145:64910690c574 7800 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 145:64910690c574 7801 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7802 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 145:64910690c574 7803
AnnaBridge 145:64910690c574 7804 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 145:64910690c574 7805 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 145:64910690c574 7806 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 145:64910690c574 7807 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7808 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7809 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 145:64910690c574 7810 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7811 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 145:64910690c574 7812
AnnaBridge 145:64910690c574 7813 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 145:64910690c574 7814 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 145:64910690c574 7815 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 145:64910690c574 7816 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7817 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7818 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7819 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7820
AnnaBridge 145:64910690c574 7821 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 145:64910690c574 7822 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 145:64910690c574 7823 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 145:64910690c574 7824 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7825 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7826
AnnaBridge 145:64910690c574 7827 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 145:64910690c574 7828 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 145:64910690c574 7829 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7830 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 145:64910690c574 7831 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 145:64910690c574 7832 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7833 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 145:64910690c574 7834 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 145:64910690c574 7835 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7836 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 145:64910690c574 7837 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 145:64910690c574 7838 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7839 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 145:64910690c574 7840 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 145:64910690c574 7841 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7842 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 145:64910690c574 7843 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 145:64910690c574 7844 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7845 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 145:64910690c574 7846 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 145:64910690c574 7847 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7848 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 145:64910690c574 7849 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 145:64910690c574 7850 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7851 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 145:64910690c574 7852 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 145:64910690c574 7853 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7854 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 145:64910690c574 7855 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 145:64910690c574 7856 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7857 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 145:64910690c574 7858 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 145:64910690c574 7859 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7860 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 145:64910690c574 7861
AnnaBridge 145:64910690c574 7862 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 145:64910690c574 7863 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 145:64910690c574 7864 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 7865 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 145:64910690c574 7866 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 145:64910690c574 7867 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 7868 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 145:64910690c574 7869
AnnaBridge 145:64910690c574 7870 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 145:64910690c574 7871 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 145:64910690c574 7872 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 145:64910690c574 7873 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 145:64910690c574 7874 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 145:64910690c574 7875 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7876 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 145:64910690c574 7877 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 145:64910690c574 7878 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 7879 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 145:64910690c574 7880 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 145:64910690c574 7881 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7882 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 145:64910690c574 7883
AnnaBridge 145:64910690c574 7884 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 145:64910690c574 7885 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 7886 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 145:64910690c574 7887 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7888 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7889 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 145:64910690c574 7890 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7891 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 145:64910690c574 7892
AnnaBridge 145:64910690c574 7893 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 145:64910690c574 7894 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 145:64910690c574 7895 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 145:64910690c574 7896 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7897 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7898 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7899 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7900 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 145:64910690c574 7901 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7902 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 145:64910690c574 7903 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 145:64910690c574 7904 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 7905 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 145:64910690c574 7906 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 145:64910690c574 7907 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7908 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 145:64910690c574 7909 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 145:64910690c574 7910 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7911 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 145:64910690c574 7912 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 145:64910690c574 7913 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7914 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 145:64910690c574 7915 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 145:64910690c574 7916 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7917 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 145:64910690c574 7918
AnnaBridge 145:64910690c574 7919 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 145:64910690c574 7920 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 145:64910690c574 7921 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 145:64910690c574 7922 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 145:64910690c574 7923
AnnaBridge 145:64910690c574 7924 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 145:64910690c574 7925 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 145:64910690c574 7926 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 145:64910690c574 7927 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7928 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7929 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7930 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7931 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 145:64910690c574 7932 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7933 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 145:64910690c574 7934 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 145:64910690c574 7935 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 7936 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 145:64910690c574 7937
AnnaBridge 145:64910690c574 7938 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 145:64910690c574 7939 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 7940 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 145:64910690c574 7941 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 7942 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 7943
AnnaBridge 145:64910690c574 7944 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 145:64910690c574 7945 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 145:64910690c574 7946 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 145:64910690c574 7947 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 7948 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 7949
AnnaBridge 145:64910690c574 7950 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 145:64910690c574 7951 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 145:64910690c574 7952 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 145:64910690c574 7953 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 145:64910690c574 7954 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 145:64910690c574 7955 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 145:64910690c574 7956 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 145:64910690c574 7957 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 7958 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 7959 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 7960 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 145:64910690c574 7961 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 7962 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 145:64910690c574 7963 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 145:64910690c574 7964 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 7965 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 145:64910690c574 7966 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 145:64910690c574 7967 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 7968 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 145:64910690c574 7969
AnnaBridge 145:64910690c574 7970 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 145:64910690c574 7971
AnnaBridge 145:64910690c574 7972 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 145:64910690c574 7973 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 145:64910690c574 7974 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 145:64910690c574 7975 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 7976 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 7977 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 7978 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 7979 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 7980 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 7981 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 7982
AnnaBridge 145:64910690c574 7983 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 145:64910690c574 7984 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 145:64910690c574 7985 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 145:64910690c574 7986 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 7987 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 7988 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 7989 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 7990 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 7991 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 7992 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 7993
AnnaBridge 145:64910690c574 7994 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 145:64910690c574 7995 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 145:64910690c574 7996 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 145:64910690c574 7997 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 7998 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 7999 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 145:64910690c574 8000 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 145:64910690c574 8001 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 145:64910690c574 8002 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 145:64910690c574 8003 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 8004 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 145:64910690c574 8005
AnnaBridge 145:64910690c574 8006 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 145:64910690c574 8007 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 145:64910690c574 8008 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 8009 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 145:64910690c574 8010 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 145:64910690c574 8011 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 8012 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 145:64910690c574 8013 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 145:64910690c574 8014 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 8015 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 145:64910690c574 8016 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 145:64910690c574 8017 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 8018 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 145:64910690c574 8019 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 145:64910690c574 8020 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 8021 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 145:64910690c574 8022 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 145:64910690c574 8023 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 8024 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 145:64910690c574 8025 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 145:64910690c574 8026 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 8027 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 145:64910690c574 8028 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 145:64910690c574 8029 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 8030 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 145:64910690c574 8031 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 145:64910690c574 8032 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 8033 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 145:64910690c574 8034 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 145:64910690c574 8035 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 8036 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 145:64910690c574 8037 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 145:64910690c574 8038 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 8039 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 145:64910690c574 8040
AnnaBridge 145:64910690c574 8041 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 145:64910690c574 8042 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 145:64910690c574 8043 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 8044 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 145:64910690c574 8045 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 145:64910690c574 8046 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 8047 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 145:64910690c574 8048 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 145:64910690c574 8049 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 8050 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 145:64910690c574 8051 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 145:64910690c574 8052 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 8053 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 145:64910690c574 8054 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 145:64910690c574 8055 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 8056 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 145:64910690c574 8057 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 145:64910690c574 8058 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 8059 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 145:64910690c574 8060 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 145:64910690c574 8061 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 8062 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 145:64910690c574 8063 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 145:64910690c574 8064 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 8065 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 145:64910690c574 8066 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 145:64910690c574 8067 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 145:64910690c574 8068 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 145:64910690c574 8069 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 145:64910690c574 8070 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 145:64910690c574 8071 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 145:64910690c574 8072 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 145:64910690c574 8073 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 145:64910690c574 8074 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
<> 128:9bcdf88f62b0 8075
<> 128:9bcdf88f62b0 8076 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 145:64910690c574 8077 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 145:64910690c574 8078 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 8079 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 145:64910690c574 8080 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 145:64910690c574 8081 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 8082 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 145:64910690c574 8083 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 145:64910690c574 8084 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 145:64910690c574 8085 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 145:64910690c574 8086 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 145:64910690c574 8087 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 8088 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 145:64910690c574 8089 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 145:64910690c574 8090 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 8091 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 145:64910690c574 8092 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 145:64910690c574 8093 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 145:64910690c574 8094 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 145:64910690c574 8095 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 145:64910690c574 8096 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 8097 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 145:64910690c574 8098 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 145:64910690c574 8099 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 145:64910690c574 8100 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 145:64910690c574 8101 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 145:64910690c574 8102 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 145:64910690c574 8103 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 145:64910690c574 8104 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 145:64910690c574 8105 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 145:64910690c574 8106 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 145:64910690c574 8107 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 145:64910690c574 8108 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 145:64910690c574 8109 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
<> 128:9bcdf88f62b0 8110
<> 128:9bcdf88f62b0 8111 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 128:9bcdf88f62b0 8112
AnnaBridge 145:64910690c574 8113 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 145:64910690c574 8114 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 145:64910690c574 8115 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 145:64910690c574 8116 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 145:64910690c574 8117 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 145:64910690c574 8118 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 145:64910690c574 8119 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 145:64910690c574 8120 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 145:64910690c574 8121 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 145:64910690c574 8122 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 145:64910690c574 8123 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 145:64910690c574 8124 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 145:64910690c574 8125 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 145:64910690c574 8126 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 145:64910690c574 8127 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 145:64910690c574 8128 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 145:64910690c574 8129 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 145:64910690c574 8130 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 8131 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 145:64910690c574 8132 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 145:64910690c574 8133 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 145:64910690c574 8134 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 145:64910690c574 8135 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 8136 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 8137
AnnaBridge 145:64910690c574 8138 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 145:64910690c574 8139 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 145:64910690c574 8140 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 8141 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 145:64910690c574 8142
AnnaBridge 145:64910690c574 8143 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 145:64910690c574 8144 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 145:64910690c574 8145 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 145:64910690c574 8146 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 145:64910690c574 8147
AnnaBridge 145:64910690c574 8148 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 145:64910690c574 8149 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 145:64910690c574 8150 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 8151 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 145:64910690c574 8152
AnnaBridge 145:64910690c574 8153 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 145:64910690c574 8154 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 145:64910690c574 8155 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 145:64910690c574 8156 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 145:64910690c574 8157 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 145:64910690c574 8158 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 145:64910690c574 8159 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 145:64910690c574 8160
AnnaBridge 145:64910690c574 8161 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 145:64910690c574 8162
AnnaBridge 145:64910690c574 8163 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 145:64910690c574 8164 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 145:64910690c574 8165 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 145:64910690c574 8166 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 145:64910690c574 8167 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 145:64910690c574 8168 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 145:64910690c574 8169 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 145:64910690c574 8170 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 145:64910690c574 8171 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 145:64910690c574 8172 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 145:64910690c574 8173 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 145:64910690c574 8174 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 145:64910690c574 8175 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 145:64910690c574 8176 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 8177 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 145:64910690c574 8178 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 145:64910690c574 8179 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 145:64910690c574 8180 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 145:64910690c574 8181 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 145:64910690c574 8182 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 145:64910690c574 8183 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 145:64910690c574 8184 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 145:64910690c574 8185 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 145:64910690c574 8186 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 145:64910690c574 8187 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 145:64910690c574 8188 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 145:64910690c574 8189 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 145:64910690c574 8190 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 145:64910690c574 8191 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 145:64910690c574 8192 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 145:64910690c574 8193 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 145:64910690c574 8194 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 145:64910690c574 8195 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 145:64910690c574 8196 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 145:64910690c574 8197 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 145:64910690c574 8198 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 145:64910690c574 8199 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 145:64910690c574 8200 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 145:64910690c574 8201
AnnaBridge 145:64910690c574 8202 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 145:64910690c574 8203 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 145:64910690c574 8204 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 8205 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 145:64910690c574 8206 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 145:64910690c574 8207 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 8208 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 145:64910690c574 8209 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 145:64910690c574 8210 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 145:64910690c574 8211 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 145:64910690c574 8212 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 145:64910690c574 8213 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 8214 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 145:64910690c574 8215 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 145:64910690c574 8216 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 145:64910690c574 8217 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 145:64910690c574 8218 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 145:64910690c574 8219 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 145:64910690c574 8220 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 145:64910690c574 8221
AnnaBridge 145:64910690c574 8222 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 145:64910690c574 8223
AnnaBridge 145:64910690c574 8224 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 145:64910690c574 8225 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 145:64910690c574 8226 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 145:64910690c574 8227 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 145:64910690c574 8228 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 145:64910690c574 8229 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 145:64910690c574 8230
AnnaBridge 145:64910690c574 8231 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 145:64910690c574 8232 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 145:64910690c574 8233 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 145:64910690c574 8234 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 145:64910690c574 8235 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8236
<> 128:9bcdf88f62b0 8237 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 145:64910690c574 8238 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 145:64910690c574 8239 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 145:64910690c574 8240 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 145:64910690c574 8241 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 145:64910690c574 8242 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 145:64910690c574 8243 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 145:64910690c574 8244 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 145:64910690c574 8245 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 145:64910690c574 8246 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
<> 128:9bcdf88f62b0 8247
<> 128:9bcdf88f62b0 8248 /**
<> 128:9bcdf88f62b0 8249 * @}
<> 128:9bcdf88f62b0 8250 */
<> 128:9bcdf88f62b0 8251
<> 128:9bcdf88f62b0 8252 /**
<> 128:9bcdf88f62b0 8253 * @}
<> 128:9bcdf88f62b0 8254 */
<> 128:9bcdf88f62b0 8255
<> 128:9bcdf88f62b0 8256 /** @addtogroup Exported_macros
<> 128:9bcdf88f62b0 8257 * @{
<> 128:9bcdf88f62b0 8258 */
AnnaBridge 145:64910690c574 8259
<> 128:9bcdf88f62b0 8260 /******************************* ADC Instances ********************************/
<> 128:9bcdf88f62b0 8261 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 145:64910690c574 8262
AnnaBridge 145:64910690c574 8263 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
<> 128:9bcdf88f62b0 8264 /******************************* CRC Instances ********************************/
<> 128:9bcdf88f62b0 8265 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 128:9bcdf88f62b0 8266
AnnaBridge 145:64910690c574 8267
<> 128:9bcdf88f62b0 8268 /******************************** DMA Instances *******************************/
<> 128:9bcdf88f62b0 8269 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
<> 128:9bcdf88f62b0 8270 ((INSTANCE) == DMA1_Stream1) || \
<> 128:9bcdf88f62b0 8271 ((INSTANCE) == DMA1_Stream2) || \
<> 128:9bcdf88f62b0 8272 ((INSTANCE) == DMA1_Stream3) || \
<> 128:9bcdf88f62b0 8273 ((INSTANCE) == DMA1_Stream4) || \
<> 128:9bcdf88f62b0 8274 ((INSTANCE) == DMA1_Stream5) || \
<> 128:9bcdf88f62b0 8275 ((INSTANCE) == DMA1_Stream6) || \
<> 128:9bcdf88f62b0 8276 ((INSTANCE) == DMA1_Stream7) || \
<> 128:9bcdf88f62b0 8277 ((INSTANCE) == DMA2_Stream0) || \
<> 128:9bcdf88f62b0 8278 ((INSTANCE) == DMA2_Stream1) || \
<> 128:9bcdf88f62b0 8279 ((INSTANCE) == DMA2_Stream2) || \
<> 128:9bcdf88f62b0 8280 ((INSTANCE) == DMA2_Stream3) || \
<> 128:9bcdf88f62b0 8281 ((INSTANCE) == DMA2_Stream4) || \
<> 128:9bcdf88f62b0 8282 ((INSTANCE) == DMA2_Stream5) || \
<> 128:9bcdf88f62b0 8283 ((INSTANCE) == DMA2_Stream6) || \
<> 128:9bcdf88f62b0 8284 ((INSTANCE) == DMA2_Stream7))
<> 128:9bcdf88f62b0 8285
<> 128:9bcdf88f62b0 8286 /******************************* GPIO Instances *******************************/
<> 128:9bcdf88f62b0 8287 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 128:9bcdf88f62b0 8288 ((INSTANCE) == GPIOB) || \
<> 128:9bcdf88f62b0 8289 ((INSTANCE) == GPIOC) || \
<> 128:9bcdf88f62b0 8290 ((INSTANCE) == GPIOD) || \
<> 128:9bcdf88f62b0 8291 ((INSTANCE) == GPIOE) || \
<> 128:9bcdf88f62b0 8292 ((INSTANCE) == GPIOH))
<> 128:9bcdf88f62b0 8293
<> 128:9bcdf88f62b0 8294 /******************************** I2C Instances *******************************/
<> 128:9bcdf88f62b0 8295 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 128:9bcdf88f62b0 8296 ((INSTANCE) == I2C2) || \
<> 128:9bcdf88f62b0 8297 ((INSTANCE) == I2C3))
<> 128:9bcdf88f62b0 8298
AnnaBridge 145:64910690c574 8299 /******************************* SMBUS Instances ******************************/
AnnaBridge 145:64910690c574 8300 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 145:64910690c574 8301
<> 128:9bcdf88f62b0 8302 /******************************** I2S Instances *******************************/
AnnaBridge 145:64910690c574 8303
<> 128:9bcdf88f62b0 8304 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 145:64910690c574 8305 ((INSTANCE) == SPI3))
<> 128:9bcdf88f62b0 8306
<> 128:9bcdf88f62b0 8307 /*************************** I2S Extended Instances ***************************/
AnnaBridge 145:64910690c574 8308 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 145:64910690c574 8309 ((INSTANCE) == I2S3ext))
AnnaBridge 145:64910690c574 8310 /* Legacy Defines */
AnnaBridge 145:64910690c574 8311 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
AnnaBridge 145:64910690c574 8312
<> 128:9bcdf88f62b0 8313
<> 128:9bcdf88f62b0 8314 /****************************** RTC Instances *********************************/
<> 128:9bcdf88f62b0 8315 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 128:9bcdf88f62b0 8316
AnnaBridge 145:64910690c574 8317
<> 128:9bcdf88f62b0 8318 /******************************** SPI Instances *******************************/
<> 128:9bcdf88f62b0 8319 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 128:9bcdf88f62b0 8320 ((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 8321 ((INSTANCE) == SPI3) || \
<> 128:9bcdf88f62b0 8322 ((INSTANCE) == SPI4))
<> 128:9bcdf88f62b0 8323
<> 128:9bcdf88f62b0 8324
<> 128:9bcdf88f62b0 8325 /****************** TIM Instances : All supported instances *******************/
<> 128:9bcdf88f62b0 8326 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8327 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8328 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8329 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8330 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 8331 ((INSTANCE) == TIM9) || \
<> 128:9bcdf88f62b0 8332 ((INSTANCE) == TIM10) || \
<> 128:9bcdf88f62b0 8333 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 8334
AnnaBridge 145:64910690c574 8335
<> 128:9bcdf88f62b0 8336 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 128:9bcdf88f62b0 8337 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8338 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8339 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8340 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8341 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 8342 ((INSTANCE) == TIM9) || \
<> 128:9bcdf88f62b0 8343 ((INSTANCE) == TIM10) || \
<> 128:9bcdf88f62b0 8344 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 8345
<> 128:9bcdf88f62b0 8346 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 128:9bcdf88f62b0 8347 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8348 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8349 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8350 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8351 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 8352 ((INSTANCE) == TIM9))
<> 128:9bcdf88f62b0 8353
<> 128:9bcdf88f62b0 8354 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 128:9bcdf88f62b0 8355 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8356 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8357 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8358 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8359 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8360
<> 128:9bcdf88f62b0 8361 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 128:9bcdf88f62b0 8362 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8363 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8364 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8365 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8366 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8367
<> 128:9bcdf88f62b0 8368 /******************** TIM Instances : Advanced-control timers *****************/
<> 128:9bcdf88f62b0 8369 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
<> 128:9bcdf88f62b0 8370
<> 128:9bcdf88f62b0 8371 /******************* TIM Instances : Timer input XOR function *****************/
<> 128:9bcdf88f62b0 8372 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8373 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8374 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8375 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8376 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8377
<> 128:9bcdf88f62b0 8378 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 128:9bcdf88f62b0 8379 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8380 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8381 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8382 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8383 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8384
<> 128:9bcdf88f62b0 8385 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 128:9bcdf88f62b0 8386 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8387 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8388 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8389 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8390 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8391
<> 128:9bcdf88f62b0 8392 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 128:9bcdf88f62b0 8393 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8394 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8395 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8396 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8397 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8398
<> 128:9bcdf88f62b0 8399 /******************** TIM Instances : DMA burst feature ***********************/
<> 128:9bcdf88f62b0 8400 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8401 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8402 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8403 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8404 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8405
<> 128:9bcdf88f62b0 8406 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 128:9bcdf88f62b0 8407 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8408 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8409 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8410 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8411 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8412
<> 128:9bcdf88f62b0 8413 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 128:9bcdf88f62b0 8414 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8415 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8416 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8417 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8418 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 8419 ((INSTANCE) == TIM9))
<> 128:9bcdf88f62b0 8420
<> 128:9bcdf88f62b0 8421 /********************** TIM Instances : 32 bit Counter ************************/
<> 128:9bcdf88f62b0 8422 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8423 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8424
<> 128:9bcdf88f62b0 8425 /***************** TIM Instances : external trigger input availabe ************/
<> 128:9bcdf88f62b0 8426 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 8427 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8428 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 8429 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 8430 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 8431
<> 128:9bcdf88f62b0 8432 /****************** TIM Instances : remapping capability **********************/
<> 128:9bcdf88f62b0 8433 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 8434 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 8435 ((INSTANCE) == TIM11))
<> 128:9bcdf88f62b0 8436
<> 128:9bcdf88f62b0 8437 /******************* TIM Instances : output(s) available **********************/
<> 128:9bcdf88f62b0 8438 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 8439 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 8440 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8441 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8442 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 8443 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 8444 || \
<> 128:9bcdf88f62b0 8445 (((INSTANCE) == TIM2) && \
<> 128:9bcdf88f62b0 8446 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8447 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8448 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 8449 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 8450 || \
<> 128:9bcdf88f62b0 8451 (((INSTANCE) == TIM3) && \
<> 128:9bcdf88f62b0 8452 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8453 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8454 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 8455 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 8456 || \
<> 128:9bcdf88f62b0 8457 (((INSTANCE) == TIM4) && \
<> 128:9bcdf88f62b0 8458 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8459 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8460 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 8461 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 8462 || \
<> 128:9bcdf88f62b0 8463 (((INSTANCE) == TIM5) && \
<> 128:9bcdf88f62b0 8464 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8465 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8466 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 8467 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 8468 || \
<> 128:9bcdf88f62b0 8469 (((INSTANCE) == TIM9) && \
<> 128:9bcdf88f62b0 8470 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8471 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 128:9bcdf88f62b0 8472 || \
<> 128:9bcdf88f62b0 8473 (((INSTANCE) == TIM10) && \
<> 128:9bcdf88f62b0 8474 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 128:9bcdf88f62b0 8475 || \
<> 128:9bcdf88f62b0 8476 (((INSTANCE) == TIM11) && \
<> 128:9bcdf88f62b0 8477 (((CHANNEL) == TIM_CHANNEL_1))))
<> 128:9bcdf88f62b0 8478
<> 128:9bcdf88f62b0 8479 /************ TIM Instances : complementary output(s) available ***************/
<> 128:9bcdf88f62b0 8480 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 8481 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 8482 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 8483 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 8484 ((CHANNEL) == TIM_CHANNEL_3))))
<> 128:9bcdf88f62b0 8485
AnnaBridge 145:64910690c574 8486 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 145:64910690c574 8487 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8488 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8489 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8490 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8491 ((INSTANCE) == TIM5))
AnnaBridge 145:64910690c574 8492
AnnaBridge 145:64910690c574 8493 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 145:64910690c574 8494 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8495 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8496 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8497 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8498 ((INSTANCE) == TIM5) || \
AnnaBridge 145:64910690c574 8499 ((INSTANCE) == TIM9) || \
AnnaBridge 145:64910690c574 8500 ((INSTANCE) == TIM10) || \
AnnaBridge 145:64910690c574 8501 ((INSTANCE) == TIM11))
AnnaBridge 145:64910690c574 8502
AnnaBridge 145:64910690c574 8503
AnnaBridge 145:64910690c574 8504 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 145:64910690c574 8505
AnnaBridge 145:64910690c574 8506 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 145:64910690c574 8507
AnnaBridge 145:64910690c574 8508 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 145:64910690c574 8509 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8510 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8511 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8512 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8513 ((INSTANCE) == TIM5))
AnnaBridge 145:64910690c574 8514
AnnaBridge 145:64910690c574 8515 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 145:64910690c574 8516 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8517 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8518 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8519 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8520 ((INSTANCE) == TIM5) || \
AnnaBridge 145:64910690c574 8521 ((INSTANCE) == TIM9))
AnnaBridge 145:64910690c574 8522
AnnaBridge 145:64910690c574 8523 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 145:64910690c574 8524 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 145:64910690c574 8525 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8526 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8527 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8528 ((INSTANCE) == TIM5))
AnnaBridge 145:64910690c574 8529
AnnaBridge 145:64910690c574 8530 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 145:64910690c574 8531 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 145:64910690c574 8532
AnnaBridge 145:64910690c574 8533 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 145:64910690c574 8534 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8535 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8536 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8537 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8538 ((INSTANCE) == TIM5) || \
AnnaBridge 145:64910690c574 8539 ((INSTANCE) == TIM9))
AnnaBridge 145:64910690c574 8540 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 145:64910690c574 8541 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 145:64910690c574 8542 ((INSTANCE) == TIM2) || \
AnnaBridge 145:64910690c574 8543 ((INSTANCE) == TIM3) || \
AnnaBridge 145:64910690c574 8544 ((INSTANCE) == TIM4) || \
AnnaBridge 145:64910690c574 8545 ((INSTANCE) == TIM5))
AnnaBridge 145:64910690c574 8546 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 145:64910690c574 8547 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 145:64910690c574 8548
<> 128:9bcdf88f62b0 8549 /******************** USART Instances : Synchronous mode **********************/
<> 128:9bcdf88f62b0 8550 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 8551 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 8552 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 8553
AnnaBridge 145:64910690c574 8554 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 145:64910690c574 8555 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 145:64910690c574 8556 ((INSTANCE) == USART2) || \
AnnaBridge 145:64910690c574 8557 ((INSTANCE) == USART6))
AnnaBridge 145:64910690c574 8558
AnnaBridge 145:64910690c574 8559 /* Legacy defines */
AnnaBridge 145:64910690c574 8560 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
<> 128:9bcdf88f62b0 8561
<> 128:9bcdf88f62b0 8562 /****************** UART Instances : Hardware Flow control ********************/
<> 128:9bcdf88f62b0 8563 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 8564 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 8565 ((INSTANCE) == USART6))
AnnaBridge 145:64910690c574 8566 /******************** UART Instances : LIN mode **********************/
AnnaBridge 145:64910690c574 8567 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 145:64910690c574 8568
AnnaBridge 145:64910690c574 8569 /********************* UART Instances : Smart card mode ***********************/
<> 128:9bcdf88f62b0 8570 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 8571 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 8572 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 8573
<> 128:9bcdf88f62b0 8574 /*********************** UART Instances : IRDA mode ***************************/
<> 128:9bcdf88f62b0 8575 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 8576 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 8577 ((INSTANCE) == USART6))
<> 128:9bcdf88f62b0 8578
<> 128:9bcdf88f62b0 8579 /*********************** PCD Instances ****************************************/
<> 128:9bcdf88f62b0 8580 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 128:9bcdf88f62b0 8581
<> 128:9bcdf88f62b0 8582 /*********************** HCD Instances ****************************************/
<> 128:9bcdf88f62b0 8583 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 128:9bcdf88f62b0 8584
AnnaBridge 145:64910690c574 8585 /****************************** SDIO Instances ********************************/
AnnaBridge 145:64910690c574 8586 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
AnnaBridge 145:64910690c574 8587
<> 128:9bcdf88f62b0 8588 /****************************** IWDG Instances ********************************/
<> 128:9bcdf88f62b0 8589 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 128:9bcdf88f62b0 8590
<> 128:9bcdf88f62b0 8591 /****************************** WWDG Instances ********************************/
<> 128:9bcdf88f62b0 8592 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 128:9bcdf88f62b0 8593
<> 128:9bcdf88f62b0 8594 /****************************** USB Exported Constants ************************/
<> 128:9bcdf88f62b0 8595 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
<> 128:9bcdf88f62b0 8596 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
<> 128:9bcdf88f62b0 8597 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
<> 128:9bcdf88f62b0 8598 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
<> 128:9bcdf88f62b0 8599
AnnaBridge 145:64910690c574 8600 /*
AnnaBridge 145:64910690c574 8601 * @brief Specific devices reset values definitions
AnnaBridge 145:64910690c574 8602 */
AnnaBridge 145:64910690c574 8603 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 145:64910690c574 8604 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
AnnaBridge 145:64910690c574 8605
AnnaBridge 145:64910690c574 8606 #define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
AnnaBridge 145:64910690c574 8607 #define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 145:64910690c574 8608 #define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 145:64910690c574 8609 #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 145:64910690c574 8610 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 145:64910690c574 8611 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 145:64910690c574 8612 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 145:64910690c574 8613
AnnaBridge 145:64910690c574 8614 #define RCC_PLLN_MIN_VALUE 192U
AnnaBridge 145:64910690c574 8615 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 145:64910690c574 8616
AnnaBridge 145:64910690c574 8617 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 145:64910690c574 8618 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 145:64910690c574 8619
AnnaBridge 145:64910690c574 8620 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 145:64910690c574 8621 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 145:64910690c574 8622
AnnaBridge 145:64910690c574 8623
<> 128:9bcdf88f62b0 8624 /**
<> 128:9bcdf88f62b0 8625 * @}
AnnaBridge 145:64910690c574 8626 */
<> 128:9bcdf88f62b0 8627
<> 128:9bcdf88f62b0 8628 /**
<> 128:9bcdf88f62b0 8629 * @}
<> 128:9bcdf88f62b0 8630 */
<> 128:9bcdf88f62b0 8631
<> 128:9bcdf88f62b0 8632 /**
<> 128:9bcdf88f62b0 8633 * @}
<> 128:9bcdf88f62b0 8634 */
<> 128:9bcdf88f62b0 8635
<> 128:9bcdf88f62b0 8636 #ifdef __cplusplus
<> 128:9bcdf88f62b0 8637 }
<> 128:9bcdf88f62b0 8638 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 8639
<> 128:9bcdf88f62b0 8640 #endif /* __STM32F401xE_H */
<> 128:9bcdf88f62b0 8641
<> 128:9bcdf88f62b0 8642
<> 128:9bcdf88f62b0 8643
<> 128:9bcdf88f62b0 8644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/