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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_system.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 135:176b8275d35d
Child:: 168:b9e159c1930a

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_system.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
<>	135:176b8275d35d	7	* @brief Header file of SYSTEM LL module.
<>	135:176b8275d35d	8	@verbatim
<>	135:176b8275d35d	9	==============================================================================
<>	135:176b8275d35d	10	##### How to use this driver #####
<>	135:176b8275d35d	11	==============================================================================
<>	135:176b8275d35d	12	[..]
<>	135:176b8275d35d	13	The LL SYSTEM driver contains a set of generic APIs that can be
<>	135:176b8275d35d	14	used by user:
<>	135:176b8275d35d	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
<>	135:176b8275d35d	16	(+) Access to DBGCMU registers
<>	135:176b8275d35d	17	(+) Access to SYSCFG registers
<>	135:176b8275d35d	18
<>	135:176b8275d35d	19	@endverbatim
<>	135:176b8275d35d	20	******************************************************************************
<>	135:176b8275d35d	21	* @attention
<>	135:176b8275d35d	22	*
<>	135:176b8275d35d	23	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	24	*
<>	135:176b8275d35d	25	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	26	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	27	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	28	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	29	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	30	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	31	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	32	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	33	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	34	* without specific prior written permission.
<>	135:176b8275d35d	35	*
<>	135:176b8275d35d	36	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	37	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	38	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	39	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	40	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	41	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	42	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	43	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	44	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	45	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	46	*
<>	135:176b8275d35d	47	******************************************************************************
<>	135:176b8275d35d	48	*/
<>	135:176b8275d35d	49
<>	135:176b8275d35d	50	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	51	#ifndef __STM32F3xx_LL_SYSTEM_H
<>	135:176b8275d35d	52	#define __STM32F3xx_LL_SYSTEM_H
<>	135:176b8275d35d	53
<>	135:176b8275d35d	54	#ifdef __cplusplus
<>	135:176b8275d35d	55	extern "C" {
<>	135:176b8275d35d	56	#endif
<>	135:176b8275d35d	57
<>	135:176b8275d35d	58	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	59	#include "stm32f3xx.h"
<>	135:176b8275d35d	60
<>	135:176b8275d35d	61	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	62	* @{
<>	135:176b8275d35d	63	*/
<>	135:176b8275d35d	64
<>	135:176b8275d35d	65	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
<>	135:176b8275d35d	66
<>	135:176b8275d35d	67	/** @defgroup SYSTEM_LL SYSTEM
<>	135:176b8275d35d	68	* @{
<>	135:176b8275d35d	69	*/
<>	135:176b8275d35d	70
<>	135:176b8275d35d	71	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	72	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	73
<>	135:176b8275d35d	74	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	75	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<>	135:176b8275d35d	76	* @{
<>	135:176b8275d35d	77	*/
<>	135:176b8275d35d	78
<>	135:176b8275d35d	79	/* Defines used for position in the register */
<>	135:176b8275d35d	80	#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
<>	135:176b8275d35d	81
<>	135:176b8275d35d	82	/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
<>	135:176b8275d35d	83	#define SYSCFG_OFFSET_CFGR1 (uint32_t)0x00000000U
<>	135:176b8275d35d	84	#define SYSCFG_OFFSET_CFGR3 (uint32_t)0x00000050U
<>	135:176b8275d35d	85
<>	135:176b8275d35d	86	/* Mask used for TIM breaks functions */
<>	135:176b8275d35d	87	#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<>	135:176b8275d35d	88	#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK)
<>	135:176b8275d35d	89	#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<>	135:176b8275d35d	90	#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK)
<>	135:176b8275d35d	91	#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<>	135:176b8275d35d	92	#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<>	135:176b8275d35d	93	#else
<>	135:176b8275d35d	94	#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
<>	135:176b8275d35d	95	#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<>	135:176b8275d35d	96
<>	135:176b8275d35d	97	/**
<>	135:176b8275d35d	98	* @}
<>	135:176b8275d35d	99	*/
<>	135:176b8275d35d	100
<>	135:176b8275d35d	101	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	102
<>	135:176b8275d35d	103	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	104	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	105	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<>	135:176b8275d35d	106	* @{
<>	135:176b8275d35d	107	*/
<>	135:176b8275d35d	108
<>	135:176b8275d35d	109	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
<>	135:176b8275d35d	110	* @{
<>	135:176b8275d35d	111	*/
<>	135:176b8275d35d	112	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
<>	135:176b8275d35d	113	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
<>	135:176b8275d35d	114	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
<>	135:176b8275d35d	115	#if defined(FMC_BANK1)
<>	135:176b8275d35d	116	#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /<! FMC Bank (Only the first two banks) /
<>	135:176b8275d35d	117	#endif /* FMC_BANK1 */
<>	135:176b8275d35d	118	/**
<>	135:176b8275d35d	119	* @}
<>	135:176b8275d35d	120	*/
<>	135:176b8275d35d	121
<>	135:176b8275d35d	122	#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
<>	135:176b8275d35d	123	/** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
<>	135:176b8275d35d	124	* @{
<>	135:176b8275d35d	125	*/
<>	135:176b8275d35d	126	#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U \| (uint32_t)0x00000000U) /!< SPI1_RX mapped on DMA1 CH2 /
<>	135:176b8275d35d	127	#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U \| SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /!< SPI1_RX mapped on DMA1 CH4 /
<>	135:176b8275d35d	128	#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U \| SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /!< SPI1_RX mapped on DMA1 CH6 /
<>	135:176b8275d35d	129	#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U \| (uint32_t)0x00000000U) /!< SPI1_TX mapped on DMA1 CH3 /
<>	135:176b8275d35d	130	#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U \| SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /!< SPI1_TX mapped on DMA1 CH5 /
<>	135:176b8275d35d	131	#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U \| SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /!< SPI1_TX mapped on DMA1 CH7 /
<>	135:176b8275d35d	132	/**
<>	135:176b8275d35d	133	* @}
<>	135:176b8275d35d	134	*/
<>	135:176b8275d35d	135	#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
<>	135:176b8275d35d	136
<>	135:176b8275d35d	137	#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
<>	135:176b8275d35d	138	/** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
<>	135:176b8275d35d	139	* @{
<>	135:176b8275d35d	140	*/
<>	135:176b8275d35d	141	#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U \| (uint32_t)0x00000000U) /!< I2C1_RX mapped on DMA1 CH7 /
<>	135:176b8275d35d	142	#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U \| SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /!< I2C1_RX mapped on DMA1 CH3 /
<>	135:176b8275d35d	143	#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U \| SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /!< I2C1_RX mapped on DMA1 CH5 /
<>	135:176b8275d35d	144	#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U \| (uint32_t)0x00000000U) /!< I2C1_TX mapped on DMA1 CH6 /
<>	135:176b8275d35d	145	#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U \| SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /!< I2C1_TX mapped on DMA1 CH2 /
<>	135:176b8275d35d	146	#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U \| SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /!< I2C1_TX mapped on DMA1 CH4 /
<>	135:176b8275d35d	147	/**
<>	135:176b8275d35d	148	* @}
<>	135:176b8275d35d	149	*/
<>	135:176b8275d35d	150
<>	135:176b8275d35d	151	#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
<>	135:176b8275d35d	152
<>	135:176b8275d35d	153	#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) \|\| defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
<>	135:176b8275d35d	154	/** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
<>	135:176b8275d35d	155	* @{
<>	135:176b8275d35d	156	*/
<>	135:176b8275d35d	157	#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
<>	135:176b8275d35d	158	#define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U \| SYSCFG_CFGR1_ADC24_DMA_RMP << 8U \| (uint32_t)0x00000000U) /!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 /
<>	135:176b8275d35d	159	#define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U \| SYSCFG_CFGR1_ADC24_DMA_RMP << 8U \| SYSCFG_CFGR1_ADC24_DMA_RMP) /!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 /
<>	135:176b8275d35d	160	#endif /SYSCFG_CFGR1_ADC24_DMA_RMP/
<>	135:176b8275d35d	161	#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
<>	135:176b8275d35d	162	#define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U \| (uint32_t)0x00000000U) /!< ADC2 mapped on DMA1 channel 2 /
<>	135:176b8275d35d	163	#define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U \| SYSCFG_CFGR3_ADC2_DMA_RMP_0) /!< ADC2 mapped on DMA1 channel 4 /
<>	135:176b8275d35d	164	#define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U \| (uint32_t)0x00000000U) /!< ADC2 mapped on DMA2 /
<>	135:176b8275d35d	165	#define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U \| SYSCFG_CFGR3_ADC2_DMA_RMP_1) /!< ADC2 mapped on DMA1 /
<>	135:176b8275d35d	166	#endif /SYSCFG_CFGR3_ADC2_DMA_RMP/
<>	135:176b8275d35d	167	/**
<>	135:176b8275d35d	168	* @}
<>	135:176b8275d35d	169	*/
<>	135:176b8275d35d	170
<>	135:176b8275d35d	171	#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP \|\| SYSCFG_CFGR3_ADC2_DMA_RMP */
<>	135:176b8275d35d	172
<>	135:176b8275d35d	173	/** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
<>	135:176b8275d35d	174	* @{
<>	135:176b8275d35d	175	*/
<>	135:176b8275d35d	176	#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< DAC_CH1 DMA requests mapped on DMA2 channel 3 /
<>	135:176b8275d35d	177	#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /!< DAC_CH1 DMA requests mapped on DMA1 channel 3 /
<>	135:176b8275d35d	178	#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
<>	135:176b8275d35d	179	#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 /
<>	135:176b8275d35d	180	#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 /
<>	135:176b8275d35d	181	#endif /SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP/
<>	135:176b8275d35d	182	#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
<>	135:176b8275d35d	183	#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 /
<>	135:176b8275d35d	184	#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 /
<>	135:176b8275d35d	185	#endif /SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP/
<>	135:176b8275d35d	186	#if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
<>	135:176b8275d35d	187	#define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< No remap /
<>	135:176b8275d35d	188	#define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) \| SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 /
<>	135:176b8275d35d	189	#endif /SYSCFG_CFGR1_DAC2Ch1_DMA_RMP/
<>	135:176b8275d35d	190	/**
<>	135:176b8275d35d	191	* @}
<>	135:176b8275d35d	192	*/
<>	135:176b8275d35d	193
<>	135:176b8275d35d	194	/** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
<>	135:176b8275d35d	195	* @{
<>	135:176b8275d35d	196	*/
<>	135:176b8275d35d	197	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 /
<>	135:176b8275d35d	198	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 /
<>	135:176b8275d35d	199	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 /
<>	135:176b8275d35d	200	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 /
<>	135:176b8275d35d	201	#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM6 DMA requests mapped on DMA2 channel 3 /
<>	135:176b8275d35d	202	#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /!< TIM6 DMA requests mapped on DMA1 channel 3 /
<>	135:176b8275d35d	203	#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
<>	135:176b8275d35d	204	#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM7 DMA requests mapped on DMA2 channel 4 /
<>	135:176b8275d35d	205	#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /!< TIM7 DMA requests mapped on DMA1 channel 4 /
<>	135:176b8275d35d	206	#endif /SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP/
<>	135:176b8275d35d	207	#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
<>	135:176b8275d35d	208	#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM18 DMA requests mapped on DMA2 channel 5 /
<>	135:176b8275d35d	209	#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) \| SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /!< TIM18 DMA requests mapped on DMA1 channel 5 /
<>	135:176b8275d35d	210	#endif /SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP/
<>	135:176b8275d35d	211	/**
<>	135:176b8275d35d	212	* @}
<>	135:176b8275d35d	213	*/
<>	135:176b8275d35d	214
<>	135:176b8275d35d	215	#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) \|\| defined(SYSCFG_CFGR1_ENCODER_MODE)
<>	135:176b8275d35d	216	/** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
<>	135:176b8275d35d	217	* @{
<>	135:176b8275d35d	218	*/
<>	135:176b8275d35d	219	#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
<>	135:176b8275d35d	220	#define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) \| (uint32_t)0x00000000U) /!< TIM1_ITR3 = TIM4_TRGO /
<>	135:176b8275d35d	221	#define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) \| SYSCFG_CFGR1_TIM1_ITR3_RMP) /!< TIM1_ITR3 = TIM17_OC /
<>	135:176b8275d35d	222	#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
<>	135:176b8275d35d	223	#if defined(SYSCFG_CFGR1_ENCODER_MODE)
<>	135:176b8275d35d	224	#define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) \| (uint32_t)0x00000000U) /!< No redirection /
<>	135:176b8275d35d	225	#define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) \| SYSCFG_CFGR1_ENCODER_MODE_0) /!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
<>	135:176b8275d35d	226	#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
<>	135:176b8275d35d	227	#define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) \| SYSCFG_CFGR1_ENCODER_MODE_TIM3) /!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
<>	135:176b8275d35d	228	#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
<>	135:176b8275d35d	229	#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
<>	135:176b8275d35d	230	#define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) \| SYSCFG_CFGR1_ENCODER_MODE_TIM4) /!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
<>	135:176b8275d35d	231	#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
<>	135:176b8275d35d	232	#endif /* SYSCFG_CFGR1_ENCODER_MODE */
<>	135:176b8275d35d	233	/**
<>	135:176b8275d35d	234	* @}
<>	135:176b8275d35d	235	*/
<>	135:176b8275d35d	236
<>	135:176b8275d35d	237	#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP \|\| SYSCFG_CFGR1_ENCODER_MODE */
<>	135:176b8275d35d	238
<>	135:176b8275d35d	239	#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
<>	135:176b8275d35d	240	/** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
<>	135:176b8275d35d	241	* @{
<>	135:176b8275d35d	242	*/
<>	135:176b8275d35d	243	#define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 /
<>	135:176b8275d35d	244	#define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) \| SYSCFG_CFGR4_ADC12_EXT2_RMP) /!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO /
<>	135:176b8275d35d	245	#define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 /
<>	135:176b8275d35d	246	#define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) \| SYSCFG_CFGR4_ADC12_EXT3_RMP) /!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 /
<>	135:176b8275d35d	247	#define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 /
<>	135:176b8275d35d	248	#define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) \| SYSCFG_CFGR4_ADC12_EXT5_RMP) /!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 /
<>	135:176b8275d35d	249	#define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO /
<>	135:176b8275d35d	250	#define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) \| SYSCFG_CFGR4_ADC12_EXT13_RMP) /!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 /
<>	135:176b8275d35d	251	#define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 /
<>	135:176b8275d35d	252	#define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) \| SYSCFG_CFGR4_ADC12_EXT15_RMP) /!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 /
<>	135:176b8275d35d	253	#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 /
<>	135:176b8275d35d	254	#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) \| SYSCFG_CFGR4_ADC12_JEXT3_RMP) /!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO /
<>	135:176b8275d35d	255	#define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 /
<>	135:176b8275d35d	256	#define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) \| SYSCFG_CFGR4_ADC12_JEXT6_RMP) /!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 /
<>	135:176b8275d35d	257	#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 /
<>	135:176b8275d35d	258	#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) \| SYSCFG_CFGR4_ADC12_JEXT13_RMP) /!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 /
<>	135:176b8275d35d	259	#define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 /
<>	135:176b8275d35d	260	#define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) \| SYSCFG_CFGR4_ADC34_EXT5_RMP) /!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO /
<>	135:176b8275d35d	261	#define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 /
<>	135:176b8275d35d	262	#define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) \| SYSCFG_CFGR4_ADC34_EXT6_RMP) /!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 /
<>	135:176b8275d35d	263	#define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 /
<>	135:176b8275d35d	264	#define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) \| SYSCFG_CFGR4_ADC34_EXT15_RMP) /!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 /
<>	135:176b8275d35d	265	#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 /
<>	135:176b8275d35d	266	#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) \| SYSCFG_CFGR4_ADC34_JEXT5_RMP) /!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO /
<>	135:176b8275d35d	267	#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 /
<>	135:176b8275d35d	268	#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) \| SYSCFG_CFGR4_ADC34_JEXT11_RMP) /!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 /
<>	135:176b8275d35d	269	#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) \| (uint32_t)0x00000000U) /!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO /
<>	135:176b8275d35d	270	#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) \| SYSCFG_CFGR4_ADC34_JEXT14_RMP) /!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 /
<>	135:176b8275d35d	271	/**
<>	135:176b8275d35d	272	* @}
<>	135:176b8275d35d	273	*/
<>	135:176b8275d35d	274
<>	135:176b8275d35d	275	#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
<>	135:176b8275d35d	276
<>	135:176b8275d35d	277	#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) \|\| defined(SYSCFG_CFGR3_TRIGGER_RMP)
<>	135:176b8275d35d	278	/** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
<>	135:176b8275d35d	279	* @{
<>	135:176b8275d35d	280	*/
<>	135:176b8275d35d	281	#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
<>	135:176b8275d35d	282	#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U \| SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 \| (uint32_t)0x00000000U) /!< No remap: DAC trigger TRIG1 is TIM8_TRGO /
<>	135:176b8275d35d	283	#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U \| SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 \| SYSCFG_CFGR1_DAC1_TRIG1_RMP) /!< DAC trigger is TIM3_TRGO /
<>	135:176b8275d35d	284	#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
<>	135:176b8275d35d	285	#if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
<>	135:176b8275d35d	286	#define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 \| (uint32_t)0x00000000U) /!< DAC trigger is TIM15_TRGO /
<>	135:176b8275d35d	287	#define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 \| SYSCFG_CFGR3_DAC1_TRG3_RMP) /!< DAC trigger is HRTIM1_DAC1_TRIG1 /
<>	135:176b8275d35d	288	#endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
<>	135:176b8275d35d	289	#if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
<>	135:176b8275d35d	290	#define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 \| (uint32_t)0x00000000U) /!< No remap /
<>	135:176b8275d35d	291	#define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U \| SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 \| SYSCFG_CFGR3_DAC1_TRG5_RMP) /!< DAC trigger is HRTIM1_DAC1_TRIG2 /
<>	135:176b8275d35d	292	#endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
<>	135:176b8275d35d	293	/**
<>	135:176b8275d35d	294	* @}
<>	135:176b8275d35d	295	*/
<>	135:176b8275d35d	296
<>	135:176b8275d35d	297	#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP \|\| SYSCFG_CFGR3_TRIGGER_RMP */
<>	135:176b8275d35d	298
<>	135:176b8275d35d	299	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
<>	135:176b8275d35d	300	* @{
<>	135:176b8275d35d	301	*/
<>	135:176b8275d35d	302	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< I2C PB6 Fast mode plus /
<>	135:176b8275d35d	303	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< I2C PB7 Fast mode plus /
<>	135:176b8275d35d	304	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< I2C PB8 Fast mode plus /
<>	135:176b8275d35d	305	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< I2C PB9 Fast mode plus /
<>	135:176b8275d35d	306	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< I2C1 Fast mode plus /
<>	135:176b8275d35d	307	#if defined(SYSCFG_CFGR1_I2C2_FMP)
<>	135:176b8275d35d	308	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< I2C2 Fast mode plus /
<>	135:176b8275d35d	309	#endif /SYSCFG_CFGR1_I2C2_FMP/
<>	135:176b8275d35d	310	#if defined(SYSCFG_CFGR1_I2C3_FMP)
<>	135:176b8275d35d	311	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< I2C3 Fast mode plus /
<>	135:176b8275d35d	312	#endif /SYSCFG_CFGR1_I2C3_FMP/
<>	135:176b8275d35d	313	/**
<>	135:176b8275d35d	314	* @}
<>	135:176b8275d35d	315	*/
<>	135:176b8275d35d	316
<>	135:176b8275d35d	317	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
<>	135:176b8275d35d	318	* @{
<>	135:176b8275d35d	319	*/
<>	135:176b8275d35d	320	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
<>	135:176b8275d35d	321	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
<>	135:176b8275d35d	322	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
<>	135:176b8275d35d	323	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
<>	135:176b8275d35d	324	#if defined(GPIOE)
<>	135:176b8275d35d	325	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
<>	135:176b8275d35d	326	#endif /* GPIOE */
<>	135:176b8275d35d	327	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
<>	135:176b8275d35d	328	#if defined(GPIOG)
<>	135:176b8275d35d	329	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /!< EXTI PORT G /
<>	135:176b8275d35d	330	#endif /* GPIOG */
<>	135:176b8275d35d	331	#if defined(GPIOH)
<>	135:176b8275d35d	332	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /!< EXTI PORT H /
<>	135:176b8275d35d	333	#endif /* GPIOH */
<>	135:176b8275d35d	334	/**
<>	135:176b8275d35d	335	* @}
<>	135:176b8275d35d	336	*/
<>	135:176b8275d35d	337
<>	135:176b8275d35d	338	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
<>	135:176b8275d35d	339	* @{
<>	135:176b8275d35d	340	*/
<>	135:176b8275d35d	341	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U \| 0U) /* EXTI_POSITION_0 \| EXTICR[0] */
<>	135:176b8275d35d	342	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U \| 0U) /* EXTI_POSITION_4 \| EXTICR[0] */
<>	135:176b8275d35d	343	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U \| 0U) /* EXTI_POSITION_8 \| EXTICR[0] */
<>	135:176b8275d35d	344	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U \| 0U) /* EXTI_POSITION_12 \| EXTICR[0] */
<>	135:176b8275d35d	345	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U \| 1U) /* EXTI_POSITION_0 \| EXTICR[1] */
<>	135:176b8275d35d	346	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U \| 1U) /* EXTI_POSITION_4 \| EXTICR[1] */
<>	135:176b8275d35d	347	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U \| 1U) /* EXTI_POSITION_8 \| EXTICR[1] */
<>	135:176b8275d35d	348	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U \| 1U) /* EXTI_POSITION_12 \| EXTICR[1] */
<>	135:176b8275d35d	349	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U \| 2U) /* EXTI_POSITION_0 \| EXTICR[2] */
<>	135:176b8275d35d	350	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U \| 2U) /* EXTI_POSITION_4 \| EXTICR[2] */
<>	135:176b8275d35d	351	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U \| 2U) /* EXTI_POSITION_8 \| EXTICR[2] */
<>	135:176b8275d35d	352	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U \| 2U) /* EXTI_POSITION_12 \| EXTICR[2] */
<>	135:176b8275d35d	353	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U \| 3U) /* EXTI_POSITION_0 \| EXTICR[3] */
<>	135:176b8275d35d	354	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U \| 3U) /* EXTI_POSITION_4 \| EXTICR[3] */
<>	135:176b8275d35d	355	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U \| 3U) /* EXTI_POSITION_8 \| EXTICR[3] */
<>	135:176b8275d35d	356	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U \| 3U) /* EXTI_POSITION_12 \| EXTICR[3] */
<>	135:176b8275d35d	357	/**
<>	135:176b8275d35d	358	* @}
<>	135:176b8275d35d	359	*/
<>	135:176b8275d35d	360
<>	135:176b8275d35d	361	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
<>	135:176b8275d35d	362	* @{
<>	135:176b8275d35d	363	*/
<>	135:176b8275d35d	364	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	135:176b8275d35d	365	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface /
<>	135:176b8275d35d	366	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	135:176b8275d35d	367	#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<>	135:176b8275d35d	368	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx /
<>	135:176b8275d35d	369	#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<>	135:176b8275d35d	370	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx /
<>	135:176b8275d35d	371	/**
<>	135:176b8275d35d	372	* @}
<>	135:176b8275d35d	373	*/
<>	135:176b8275d35d	374
<>	135:176b8275d35d	375	#if defined(SYSCFG_RCR_PAGE0)
<>	135:176b8275d35d	376	/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
<>	135:176b8275d35d	377	* @{
<>	135:176b8275d35d	378	*/
<>	135:176b8275d35d	379	#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /!< ICODE SRAM Write protection page 0 /
<>	135:176b8275d35d	380	#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /!< ICODE SRAM Write protection page 1 /
<>	135:176b8275d35d	381	#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /!< ICODE SRAM Write protection page 2 /
<>	135:176b8275d35d	382	#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /!< ICODE SRAM Write protection page 3 /
<>	135:176b8275d35d	383	#if defined(SYSCFG_RCR_PAGE4)
<>	135:176b8275d35d	384	#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /!< ICODE SRAM Write protection page 4 /
<>	135:176b8275d35d	385	#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /!< ICODE SRAM Write protection page 5 /
<>	135:176b8275d35d	386	#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /!< ICODE SRAM Write protection page 6 /
<>	135:176b8275d35d	387	#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /!< ICODE SRAM Write protection page 7 /
<>	135:176b8275d35d	388	#endif
<>	135:176b8275d35d	389	#if defined(SYSCFG_RCR_PAGE8)
<>	135:176b8275d35d	390	#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /!< ICODE SRAM Write protection page 8 /
<>	135:176b8275d35d	391	#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /!< ICODE SRAM Write protection page 9 /
<>	135:176b8275d35d	392	#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /!< ICODE SRAM Write protection page 10 /
<>	135:176b8275d35d	393	#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /!< ICODE SRAM Write protection page 11 /
<>	135:176b8275d35d	394	#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /!< ICODE SRAM Write protection page 12 /
<>	135:176b8275d35d	395	#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /!< ICODE SRAM Write protection page 13 /
<>	135:176b8275d35d	396	#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /!< ICODE SRAM Write protection page 14 /
<>	135:176b8275d35d	397	#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /!< ICODE SRAM Write protection page 15 /
<>	135:176b8275d35d	398	#endif
<>	135:176b8275d35d	399	/**
<>	135:176b8275d35d	400	* @}
<>	135:176b8275d35d	401	*/
<>	135:176b8275d35d	402
<>	135:176b8275d35d	403	#endif /* SYSCFG_RCR_PAGE0 */
<>	135:176b8275d35d	404
<>	135:176b8275d35d	405	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
<>	135:176b8275d35d	406	* @{
<>	135:176b8275d35d	407	*/
<>	135:176b8275d35d	408	#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /!< TRACE pins not assigned (default state) /
<>	135:176b8275d35d	409	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
<>	135:176b8275d35d	410	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
<>	135:176b8275d35d	411	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
<>	135:176b8275d35d	412	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
<>	135:176b8275d35d	413	/**
<>	135:176b8275d35d	414	* @}
<>	135:176b8275d35d	415	*/
<>	135:176b8275d35d	416
<>	135:176b8275d35d	417	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<>	135:176b8275d35d	418	* @{
<>	135:176b8275d35d	419	*/
<>	135:176b8275d35d	420	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
<>	135:176b8275d35d	421	#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<>	135:176b8275d35d	422	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
<>	135:176b8275d35d	423	#endif /DBGMCU_APB1_FZ_DBG_TIM3_STOP/
<>	135:176b8275d35d	424	#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<>	135:176b8275d35d	425	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
<>	135:176b8275d35d	426	#endif /DBGMCU_APB1_FZ_DBG_TIM4_STOP/
<>	135:176b8275d35d	427	#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<>	135:176b8275d35d	428	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
<>	135:176b8275d35d	429	#endif /DBGMCU_APB1_FZ_DBG_TIM5_STOP/
<>	135:176b8275d35d	430	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
<>	135:176b8275d35d	431	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<>	135:176b8275d35d	432	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
<>	135:176b8275d35d	433	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
<>	135:176b8275d35d	434	#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
<>	135:176b8275d35d	435	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /!< TIM12 counter stopped when core is halted /
<>	135:176b8275d35d	436	#endif /DBGMCU_APB1_FZ_DBG_TIM12_STOP/
<>	135:176b8275d35d	437	#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
<>	135:176b8275d35d	438	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /!< TIM13 counter stopped when core is halted /
<>	135:176b8275d35d	439	#endif /DBGMCU_APB1_FZ_DBG_TIM13_STOP/
<>	135:176b8275d35d	440	#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
<>	135:176b8275d35d	441	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
<>	135:176b8275d35d	442	#endif /DBGMCU_APB1_FZ_DBG_TIM14_STOP/
<>	135:176b8275d35d	443	#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
<>	135:176b8275d35d	444	#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /!< TIM18 counter stopped when core is halted /
<>	135:176b8275d35d	445	#endif /DBGMCU_APB1_FZ_DBG_TIM18_STOP/
<>	135:176b8275d35d	446	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC counter stopped when core is halted /
<>	135:176b8275d35d	447	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
<>	135:176b8275d35d	448	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
<>	135:176b8275d35d	449	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
<>	135:176b8275d35d	450	#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<>	135:176b8275d35d	451	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
<>	135:176b8275d35d	452	#endif /DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT/
<>	135:176b8275d35d	453	#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
<>	135:176b8275d35d	454	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /!< I2C3 SMBUS timeout mode stopped when Core is halted /
<>	135:176b8275d35d	455	#endif /DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT/
<>	135:176b8275d35d	456	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<>	135:176b8275d35d	457	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
<>	135:176b8275d35d	458	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
<>	135:176b8275d35d	459	/**
<>	135:176b8275d35d	460	* @}
<>	135:176b8275d35d	461	*/
<>	135:176b8275d35d	462
<>	135:176b8275d35d	463	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
<>	135:176b8275d35d	464	* @{
<>	135:176b8275d35d	465	*/
<>	135:176b8275d35d	466	#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
<>	135:176b8275d35d	467	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
<>	135:176b8275d35d	468	#endif /DBGMCU_APB2_FZ_DBG_TIM1_STOP/
<>	135:176b8275d35d	469	#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
<>	135:176b8275d35d	470	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /!< TIM8 counter stopped when core is halted /
<>	135:176b8275d35d	471	#endif /DBGMCU_APB2_FZ_DBG_TIM8_STOP/
<>	135:176b8275d35d	472	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
<>	135:176b8275d35d	473	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
<>	135:176b8275d35d	474	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
<>	135:176b8275d35d	475	#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
<>	135:176b8275d35d	476	#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /!< TIM19 counter stopped when core is halted /
<>	135:176b8275d35d	477	#endif /DBGMCU_APB2_FZ_DBG_TIM19_STOP/
<>	135:176b8275d35d	478	#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
<>	135:176b8275d35d	479	#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /!< TIM20 counter stopped when core is halted /
<>	135:176b8275d35d	480	#endif /DBGMCU_APB2_FZ_DBG_TIM20_STOP/
<>	135:176b8275d35d	481	#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
<>	135:176b8275d35d	482	#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /!< HRTIM1 counter stopped when core is halted /
<>	135:176b8275d35d	483	#endif /DBGMCU_APB2_FZ_DBG_HRTIM1_STOP/
<>	135:176b8275d35d	484	/**
<>	135:176b8275d35d	485	* @}
<>	135:176b8275d35d	486	*/
<>	135:176b8275d35d	487
<>	135:176b8275d35d	488	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<>	135:176b8275d35d	489	* @{
<>	135:176b8275d35d	490	*/
<>	135:176b8275d35d	491	#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /!< FLASH Zero Latency cycle /
<>	135:176b8275d35d	492	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /!< FLASH One Latency cycle /
<>	135:176b8275d35d	493	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /!< FLASH Two Latency cycles /
<>	135:176b8275d35d	494	/**
<>	135:176b8275d35d	495	* @}
<>	135:176b8275d35d	496	*/
<>	135:176b8275d35d	497
<>	135:176b8275d35d	498	/**
<>	135:176b8275d35d	499	* @}
<>	135:176b8275d35d	500	*/
<>	135:176b8275d35d	501
<>	135:176b8275d35d	502	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	503
<>	135:176b8275d35d	504	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	505	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<>	135:176b8275d35d	506	* @{
<>	135:176b8275d35d	507	*/
<>	135:176b8275d35d	508
<>	135:176b8275d35d	509	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
<>	135:176b8275d35d	510	* @{
<>	135:176b8275d35d	511	*/
<>	135:176b8275d35d	512
<>	135:176b8275d35d	513	/**
<>	135:176b8275d35d	514	* @brief Set memory mapping at address 0x00000000
<>	135:176b8275d35d	515	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
<>	135:176b8275d35d	516	* @param Memory This parameter can be one of the following values:
<>	135:176b8275d35d	517	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	135:176b8275d35d	518	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	135:176b8275d35d	519	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	135:176b8275d35d	520	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
<>	135:176b8275d35d	521	*
<>	135:176b8275d35d	522	* (*) value not defined in all devices.
<>	135:176b8275d35d	523	* @retval None
<>	135:176b8275d35d	524	*/
<>	135:176b8275d35d	525	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
<>	135:176b8275d35d	526	{
<>	135:176b8275d35d	527	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
<>	135:176b8275d35d	528	}
<>	135:176b8275d35d	529
<>	135:176b8275d35d	530	/**
<>	135:176b8275d35d	531	* @brief Get memory mapping at address 0x00000000
<>	135:176b8275d35d	532	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
<>	135:176b8275d35d	533	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	534	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	135:176b8275d35d	535	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	135:176b8275d35d	536	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	135:176b8275d35d	537	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
<>	135:176b8275d35d	538	*
<>	135:176b8275d35d	539	* (*) value not defined in all devices.
<>	135:176b8275d35d	540	*/
<>	135:176b8275d35d	541	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
<>	135:176b8275d35d	542	{
<>	135:176b8275d35d	543	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
<>	135:176b8275d35d	544	}
<>	135:176b8275d35d	545
<>	135:176b8275d35d	546	#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
<>	135:176b8275d35d	547	/**
<>	135:176b8275d35d	548	* @brief Set DMA request remapping bits for SPI
<>	135:176b8275d35d	549	* @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
<>	135:176b8275d35d	550	* SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
<>	135:176b8275d35d	551	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	552	* @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
<>	135:176b8275d35d	553	* @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
<>	135:176b8275d35d	554	* @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
<>	135:176b8275d35d	555	* @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
<>	135:176b8275d35d	556	* @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
<>	135:176b8275d35d	557	* @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
<>	135:176b8275d35d	558	* @retval None
<>	135:176b8275d35d	559	*/
<>	135:176b8275d35d	560	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
<>	135:176b8275d35d	561	{
<>	135:176b8275d35d	562	MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
<>	135:176b8275d35d	563	}
<>	135:176b8275d35d	564	#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
<>	135:176b8275d35d	565
<>	135:176b8275d35d	566	#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
<>	135:176b8275d35d	567	/**
<>	135:176b8275d35d	568	* @brief Set DMA request remapping bits for I2C
<>	135:176b8275d35d	569	* @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
<>	135:176b8275d35d	570	* SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
<>	135:176b8275d35d	571	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	572	* @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
<>	135:176b8275d35d	573	* @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
<>	135:176b8275d35d	574	* @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
<>	135:176b8275d35d	575	* @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
<>	135:176b8275d35d	576	* @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
<>	135:176b8275d35d	577	* @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
<>	135:176b8275d35d	578	* @retval None
<>	135:176b8275d35d	579	*/
<>	135:176b8275d35d	580	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
<>	135:176b8275d35d	581	{
<>	135:176b8275d35d	582	MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
<>	135:176b8275d35d	583	}
<>	135:176b8275d35d	584	#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
<>	135:176b8275d35d	585
<>	135:176b8275d35d	586	#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) \|\| defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
<>	135:176b8275d35d	587	/**
<>	135:176b8275d35d	588	* @brief Set DMA request remapping bits for ADC
<>	135:176b8275d35d	589	* @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
<>	135:176b8275d35d	590	* SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
<>	135:176b8275d35d	591	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	592	* @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
<>	135:176b8275d35d	593	* @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
<>	135:176b8275d35d	594	* @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
<>	135:176b8275d35d	595	* @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
<>	135:176b8275d35d	596	* @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
<>	135:176b8275d35d	597	* @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
<>	135:176b8275d35d	598	*
<>	135:176b8275d35d	599	* (*) value not defined in all devices.
<>	135:176b8275d35d	600	* @retval None
<>	135:176b8275d35d	601	*/
<>	135:176b8275d35d	602	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
<>	135:176b8275d35d	603	{
<>	135:176b8275d35d	604	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
<>	135:176b8275d35d	605	MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
<>	135:176b8275d35d	606	}
<>	135:176b8275d35d	607	#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP \|\| SYSCFG_CFGR3_ADC2_DMA_RMP */
<>	135:176b8275d35d	608
<>	135:176b8275d35d	609	/**
<>	135:176b8275d35d	610	* @brief Set DMA request remapping bits for DAC
<>	135:176b8275d35d	611	* @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
<>	135:176b8275d35d	612	* SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
<>	135:176b8275d35d	613	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	614	* @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
<>	135:176b8275d35d	615	* @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
<>	135:176b8275d35d	616	* @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
<>	135:176b8275d35d	617	* @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
<>	135:176b8275d35d	618	* @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
<>	135:176b8275d35d	619	* @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
<>	135:176b8275d35d	620	* @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
<>	135:176b8275d35d	621	* @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
<>	135:176b8275d35d	622	*
<>	135:176b8275d35d	623	* (*) value not defined in all devices.
<>	135:176b8275d35d	624	* @retval None
<>	135:176b8275d35d	625	*/
<>	135:176b8275d35d	626	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
<>	135:176b8275d35d	627	{
<>	135:176b8275d35d	628	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
<>	135:176b8275d35d	629	}
<>	135:176b8275d35d	630
<>	135:176b8275d35d	631	/**
<>	135:176b8275d35d	632	* @brief Set DMA request remapping bits for TIM
<>	135:176b8275d35d	633	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	135:176b8275d35d	634	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	135:176b8275d35d	635	* SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	135:176b8275d35d	636	* SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	135:176b8275d35d	637	* SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
<>	135:176b8275d35d	638	* @param Remap This parameter can be a combination of the following values:
<>	135:176b8275d35d	639	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
<>	135:176b8275d35d	640	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
<>	135:176b8275d35d	641	* @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
<>	135:176b8275d35d	642	* @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
<>	135:176b8275d35d	643	* @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
<>	135:176b8275d35d	644	*
<>	135:176b8275d35d	645	* (*) value not defined in all devices.
<>	135:176b8275d35d	646	* @retval None
<>	135:176b8275d35d	647	*/
<>	135:176b8275d35d	648	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
<>	135:176b8275d35d	649	{
<>	135:176b8275d35d	650	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
<>	135:176b8275d35d	651	}
<>	135:176b8275d35d	652
<>	135:176b8275d35d	653	#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) \|\| defined(SYSCFG_CFGR1_ENCODER_MODE)
<>	135:176b8275d35d	654	/**
<>	135:176b8275d35d	655	* @brief Set Timer input remap
<>	135:176b8275d35d	656	* @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
<>	135:176b8275d35d	657	* SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
<>	135:176b8275d35d	658	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	659	* @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
<>	135:176b8275d35d	660	* @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
<>	135:176b8275d35d	661	* @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
<>	135:176b8275d35d	662	* @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
<>	135:176b8275d35d	663	* @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
<>	135:176b8275d35d	664	* @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
<>	135:176b8275d35d	665	*
<>	135:176b8275d35d	666	* (*) value not defined in all devices.
<>	135:176b8275d35d	667	* @retval None
<>	135:176b8275d35d	668	*/
<>	135:176b8275d35d	669	__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
<>	135:176b8275d35d	670	{
<>	135:176b8275d35d	671	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
<>	135:176b8275d35d	672	}
<>	135:176b8275d35d	673	#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP \|\| SYSCFG_CFGR1_ENCODER_MODE */
<>	135:176b8275d35d	674
<>	135:176b8275d35d	675	#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
<>	135:176b8275d35d	676	/**
<>	135:176b8275d35d	677	* @brief Set ADC Trigger remap
<>	135:176b8275d35d	678	* @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	679	* SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	680	* SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	681	* SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	682	* SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	683	* SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	684	* SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	685	* SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	686	* SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	687	* SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	688	* SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	689	* SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	690	* SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
<>	135:176b8275d35d	691	* SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
<>	135:176b8275d35d	692	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	693	* @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
<>	135:176b8275d35d	694	* @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
<>	135:176b8275d35d	695	* @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
<>	135:176b8275d35d	696	* @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
<>	135:176b8275d35d	697	* @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
<>	135:176b8275d35d	698	* @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
<>	135:176b8275d35d	699	* @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
<>	135:176b8275d35d	700	* @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
<>	135:176b8275d35d	701	* @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
<>	135:176b8275d35d	702	* @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
<>	135:176b8275d35d	703	* @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
<>	135:176b8275d35d	704	* @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
<>	135:176b8275d35d	705	* @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
<>	135:176b8275d35d	706	* @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
<>	135:176b8275d35d	707	* @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
<>	135:176b8275d35d	708	* @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
<>	135:176b8275d35d	709	* @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
<>	135:176b8275d35d	710	* @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
<>	135:176b8275d35d	711	* @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
<>	135:176b8275d35d	712	* @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
<>	135:176b8275d35d	713	* @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
<>	135:176b8275d35d	714	* @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
<>	135:176b8275d35d	715	* @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
<>	135:176b8275d35d	716	* @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
<>	135:176b8275d35d	717	* @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
<>	135:176b8275d35d	718	* @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
<>	135:176b8275d35d	719	* @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
<>	135:176b8275d35d	720	* @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
<>	135:176b8275d35d	721	* @retval None
<>	135:176b8275d35d	722	*/
<>	135:176b8275d35d	723	__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
<>	135:176b8275d35d	724	{
<>	135:176b8275d35d	725	MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
<>	135:176b8275d35d	726	}
<>	135:176b8275d35d	727	#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
<>	135:176b8275d35d	728
<>	135:176b8275d35d	729	#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) \|\| defined(SYSCFG_CFGR3_TRIGGER_RMP)
<>	135:176b8275d35d	730	/**
<>	135:176b8275d35d	731	* @brief Set DAC Trigger remap
<>	135:176b8275d35d	732	* @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
<>	135:176b8275d35d	733	* SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
<>	135:176b8275d35d	734	* SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
<>	135:176b8275d35d	735	* @param Remap This parameter can be one of the following values:
<>	135:176b8275d35d	736	* @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
<>	135:176b8275d35d	737	* @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
<>	135:176b8275d35d	738	* @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
<>	135:176b8275d35d	739	* @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
<>	135:176b8275d35d	740	* @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
<>	135:176b8275d35d	741	* @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
<>	135:176b8275d35d	742	* (*) value not defined in all devices.
<>	135:176b8275d35d	743	* @retval None
<>	135:176b8275d35d	744	*/
<>	135:176b8275d35d	745	__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
<>	135:176b8275d35d	746	{
<>	135:176b8275d35d	747	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
<>	135:176b8275d35d	748	MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
<>	135:176b8275d35d	749	}
<>	135:176b8275d35d	750	#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP \|\| SYSCFG_CFGR3_TRIGGER_RMP */
<>	135:176b8275d35d	751
<>	135:176b8275d35d	752	#if defined(SYSCFG_CFGR1_USB_IT_RMP)
<>	135:176b8275d35d	753	/**
<>	135:176b8275d35d	754	* @brief Enable USB interrupt remap
<>	135:176b8275d35d	755	* @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
<>	135:176b8275d35d	756	* respectively
<>	135:176b8275d35d	757	* @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
<>	135:176b8275d35d	758	* @retval None
<>	135:176b8275d35d	759	*/
<>	135:176b8275d35d	760	__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
<>	135:176b8275d35d	761	{
<>	135:176b8275d35d	762	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
<>	135:176b8275d35d	763	}
<>	135:176b8275d35d	764
<>	135:176b8275d35d	765	/**
<>	135:176b8275d35d	766	* @brief Disable USB interrupt remap
<>	135:176b8275d35d	767	* @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
<>	135:176b8275d35d	768	* @retval None
<>	135:176b8275d35d	769	*/
<>	135:176b8275d35d	770	__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
<>	135:176b8275d35d	771	{
<>	135:176b8275d35d	772	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
<>	135:176b8275d35d	773	}
<>	135:176b8275d35d	774	#endif /* SYSCFG_CFGR1_USB_IT_RMP */
<>	135:176b8275d35d	775
<>	135:176b8275d35d	776	#if defined(SYSCFG_CFGR1_VBAT)
<>	135:176b8275d35d	777	/**
<>	135:176b8275d35d	778	* @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
<>	135:176b8275d35d	779	* @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
<>	135:176b8275d35d	780	* @retval None
<>	135:176b8275d35d	781	*/
<>	135:176b8275d35d	782	__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
<>	135:176b8275d35d	783	{
<>	135:176b8275d35d	784	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<>	135:176b8275d35d	785	}
<>	135:176b8275d35d	786
<>	135:176b8275d35d	787	/**
<>	135:176b8275d35d	788	* @brief Disable VBAT monitoring
<>	135:176b8275d35d	789	* @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
<>	135:176b8275d35d	790	* @retval None
<>	135:176b8275d35d	791	*/
<>	135:176b8275d35d	792	__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
<>	135:176b8275d35d	793	{
<>	135:176b8275d35d	794	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<>	135:176b8275d35d	795	}
<>	135:176b8275d35d	796	#endif /* SYSCFG_CFGR1_VBAT */
<>	135:176b8275d35d	797
<>	135:176b8275d35d	798	/**
<>	135:176b8275d35d	799	* @brief Enable the I2C fast mode plus driving capability.
<>	135:176b8275d35d	800	* @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	801	* SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	802	* SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	803	* SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	804	* SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	805	* SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
<>	135:176b8275d35d	806	* SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
<>	135:176b8275d35d	807	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	135:176b8275d35d	808	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	135:176b8275d35d	809	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	135:176b8275d35d	810	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	135:176b8275d35d	811	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	135:176b8275d35d	812	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<>	135:176b8275d35d	813	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	135:176b8275d35d	814	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
<>	135:176b8275d35d	815	*
<>	135:176b8275d35d	816	* (*) value not defined in all devices.
<>	135:176b8275d35d	817	* @retval None
<>	135:176b8275d35d	818	*/
<>	135:176b8275d35d	819	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
<>	135:176b8275d35d	820	{
<>	135:176b8275d35d	821	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	135:176b8275d35d	822	}
<>	135:176b8275d35d	823
<>	135:176b8275d35d	824	/**
<>	135:176b8275d35d	825	* @brief Disable the I2C fast mode plus driving capability.
<>	135:176b8275d35d	826	* @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	827	* SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	828	* SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	829	* SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	830	* SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	831	* SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
<>	135:176b8275d35d	832	* SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
<>	135:176b8275d35d	833	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	135:176b8275d35d	834	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	135:176b8275d35d	835	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	135:176b8275d35d	836	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	135:176b8275d35d	837	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	135:176b8275d35d	838	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<>	135:176b8275d35d	839	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	135:176b8275d35d	840	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
<>	135:176b8275d35d	841	*
<>	135:176b8275d35d	842	* (*) value not defined in all devices.
<>	135:176b8275d35d	843	* @retval None
<>	135:176b8275d35d	844	*/
<>	135:176b8275d35d	845	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
<>	135:176b8275d35d	846	{
<>	135:176b8275d35d	847	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	135:176b8275d35d	848	}
<>	135:176b8275d35d	849
<>	135:176b8275d35d	850	/**
<>	135:176b8275d35d	851	* @brief Enable Floating Point Unit Invalid operation Interrupt
<>	135:176b8275d35d	852	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
<>	135:176b8275d35d	853	* @retval None
<>	135:176b8275d35d	854	*/
<>	135:176b8275d35d	855	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
<>	135:176b8275d35d	856	{
<>	135:176b8275d35d	857	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
<>	135:176b8275d35d	858	}
<>	135:176b8275d35d	859
<>	135:176b8275d35d	860	/**
<>	135:176b8275d35d	861	* @brief Enable Floating Point Unit Divide-by-zero Interrupt
<>	135:176b8275d35d	862	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
<>	135:176b8275d35d	863	* @retval None
<>	135:176b8275d35d	864	*/
<>	135:176b8275d35d	865	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
<>	135:176b8275d35d	866	{
<>	135:176b8275d35d	867	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
<>	135:176b8275d35d	868	}
<>	135:176b8275d35d	869
<>	135:176b8275d35d	870	/**
<>	135:176b8275d35d	871	* @brief Enable Floating Point Unit Underflow Interrupt
<>	135:176b8275d35d	872	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
<>	135:176b8275d35d	873	* @retval None
<>	135:176b8275d35d	874	*/
<>	135:176b8275d35d	875	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
<>	135:176b8275d35d	876	{
<>	135:176b8275d35d	877	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
<>	135:176b8275d35d	878	}
<>	135:176b8275d35d	879
<>	135:176b8275d35d	880	/**
<>	135:176b8275d35d	881	* @brief Enable Floating Point Unit Overflow Interrupt
<>	135:176b8275d35d	882	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
<>	135:176b8275d35d	883	* @retval None
<>	135:176b8275d35d	884	*/
<>	135:176b8275d35d	885	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
<>	135:176b8275d35d	886	{
<>	135:176b8275d35d	887	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
<>	135:176b8275d35d	888	}
<>	135:176b8275d35d	889
<>	135:176b8275d35d	890	/**
<>	135:176b8275d35d	891	* @brief Enable Floating Point Unit Input denormal Interrupt
<>	135:176b8275d35d	892	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
<>	135:176b8275d35d	893	* @retval None
<>	135:176b8275d35d	894	*/
<>	135:176b8275d35d	895	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
<>	135:176b8275d35d	896	{
<>	135:176b8275d35d	897	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
<>	135:176b8275d35d	898	}
<>	135:176b8275d35d	899
<>	135:176b8275d35d	900	/**
<>	135:176b8275d35d	901	* @brief Enable Floating Point Unit Inexact Interrupt
<>	135:176b8275d35d	902	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
<>	135:176b8275d35d	903	* @retval None
<>	135:176b8275d35d	904	*/
<>	135:176b8275d35d	905	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
<>	135:176b8275d35d	906	{
<>	135:176b8275d35d	907	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
<>	135:176b8275d35d	908	}
<>	135:176b8275d35d	909
<>	135:176b8275d35d	910	/**
<>	135:176b8275d35d	911	* @brief Disable Floating Point Unit Invalid operation Interrupt
<>	135:176b8275d35d	912	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
<>	135:176b8275d35d	913	* @retval None
<>	135:176b8275d35d	914	*/
<>	135:176b8275d35d	915	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
<>	135:176b8275d35d	916	{
<>	135:176b8275d35d	917	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
<>	135:176b8275d35d	918	}
<>	135:176b8275d35d	919
<>	135:176b8275d35d	920	/**
<>	135:176b8275d35d	921	* @brief Disable Floating Point Unit Divide-by-zero Interrupt
<>	135:176b8275d35d	922	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
<>	135:176b8275d35d	923	* @retval None
<>	135:176b8275d35d	924	*/
<>	135:176b8275d35d	925	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
<>	135:176b8275d35d	926	{
<>	135:176b8275d35d	927	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
<>	135:176b8275d35d	928	}
<>	135:176b8275d35d	929
<>	135:176b8275d35d	930	/**
<>	135:176b8275d35d	931	* @brief Disable Floating Point Unit Underflow Interrupt
<>	135:176b8275d35d	932	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
<>	135:176b8275d35d	933	* @retval None
<>	135:176b8275d35d	934	*/
<>	135:176b8275d35d	935	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
<>	135:176b8275d35d	936	{
<>	135:176b8275d35d	937	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
<>	135:176b8275d35d	938	}
<>	135:176b8275d35d	939
<>	135:176b8275d35d	940	/**
<>	135:176b8275d35d	941	* @brief Disable Floating Point Unit Overflow Interrupt
<>	135:176b8275d35d	942	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
<>	135:176b8275d35d	943	* @retval None
<>	135:176b8275d35d	944	*/
<>	135:176b8275d35d	945	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
<>	135:176b8275d35d	946	{
<>	135:176b8275d35d	947	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
<>	135:176b8275d35d	948	}
<>	135:176b8275d35d	949
<>	135:176b8275d35d	950	/**
<>	135:176b8275d35d	951	* @brief Disable Floating Point Unit Input denormal Interrupt
<>	135:176b8275d35d	952	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
<>	135:176b8275d35d	953	* @retval None
<>	135:176b8275d35d	954	*/
<>	135:176b8275d35d	955	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
<>	135:176b8275d35d	956	{
<>	135:176b8275d35d	957	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
<>	135:176b8275d35d	958	}
<>	135:176b8275d35d	959
<>	135:176b8275d35d	960	/**
<>	135:176b8275d35d	961	* @brief Disable Floating Point Unit Inexact Interrupt
<>	135:176b8275d35d	962	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
<>	135:176b8275d35d	963	* @retval None
<>	135:176b8275d35d	964	*/
<>	135:176b8275d35d	965	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
<>	135:176b8275d35d	966	{
<>	135:176b8275d35d	967	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
<>	135:176b8275d35d	968	}
<>	135:176b8275d35d	969
<>	135:176b8275d35d	970	/**
<>	135:176b8275d35d	971	* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
<>	135:176b8275d35d	972	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
<>	135:176b8275d35d	973	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	974	*/
<>	135:176b8275d35d	975	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
<>	135:176b8275d35d	976	{
<>	135:176b8275d35d	977	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
<>	135:176b8275d35d	978	}
<>	135:176b8275d35d	979
<>	135:176b8275d35d	980	/**
<>	135:176b8275d35d	981	* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
<>	135:176b8275d35d	982	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
<>	135:176b8275d35d	983	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	984	*/
<>	135:176b8275d35d	985	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
<>	135:176b8275d35d	986	{
<>	135:176b8275d35d	987	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
<>	135:176b8275d35d	988	}
<>	135:176b8275d35d	989
<>	135:176b8275d35d	990	/**
<>	135:176b8275d35d	991	* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
<>	135:176b8275d35d	992	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
<>	135:176b8275d35d	993	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	994	*/
<>	135:176b8275d35d	995	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
<>	135:176b8275d35d	996	{
<>	135:176b8275d35d	997	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
<>	135:176b8275d35d	998	}
<>	135:176b8275d35d	999
<>	135:176b8275d35d	1000	/**
<>	135:176b8275d35d	1001	* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
<>	135:176b8275d35d	1002	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
<>	135:176b8275d35d	1003	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1004	*/
<>	135:176b8275d35d	1005	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
<>	135:176b8275d35d	1006	{
<>	135:176b8275d35d	1007	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
<>	135:176b8275d35d	1008	}
<>	135:176b8275d35d	1009
<>	135:176b8275d35d	1010	/**
<>	135:176b8275d35d	1011	* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
<>	135:176b8275d35d	1012	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
<>	135:176b8275d35d	1013	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1014	*/
<>	135:176b8275d35d	1015	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
<>	135:176b8275d35d	1016	{
<>	135:176b8275d35d	1017	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
<>	135:176b8275d35d	1018	}
<>	135:176b8275d35d	1019
<>	135:176b8275d35d	1020	/**
<>	135:176b8275d35d	1021	* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
<>	135:176b8275d35d	1022	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
<>	135:176b8275d35d	1023	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1024	*/
<>	135:176b8275d35d	1025	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
<>	135:176b8275d35d	1026	{
<>	135:176b8275d35d	1027	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
<>	135:176b8275d35d	1028	}
<>	135:176b8275d35d	1029
<>	135:176b8275d35d	1030	/**
<>	135:176b8275d35d	1031	* @brief Configure source input for the EXTI external interrupt.
<>	135:176b8275d35d	1032	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1033	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1034	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1035	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1036	* SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1037	* SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1038	* SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1039	* SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1040	* SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1041	* SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1042	* SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1043	* SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1044	* SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1045	* SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1046	* SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1047	* SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1048	* SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1049	* SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1050	* SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1051	* SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1052	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1053	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1054	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1055	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1056	* SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1057	* SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1058	* SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1059	* SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1060	* SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1061	* SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1062	* SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1063	* SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1064	* SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1065	* SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1066	* SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1067	* SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1068	* SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1069	* SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1070	* SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1071	* SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1072	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1073	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1074	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1075	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1076	* SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1077	* SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1078	* SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1079	* SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1080	* SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1081	* SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1082	* SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1083	* SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1084	* SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1085	* SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1086	* SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1087	* SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1088	* SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1089	* SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1090	* SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1091	* SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1092	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1093	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1094	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	135:176b8275d35d	1095	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<>	135:176b8275d35d	1096	* @param Port This parameter can be one of the following values:
<>	135:176b8275d35d	1097	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	135:176b8275d35d	1098	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	135:176b8275d35d	1099	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	135:176b8275d35d	1100	* @arg @ref LL_SYSCFG_EXTI_PORTD
<>	135:176b8275d35d	1101	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	135:176b8275d35d	1102	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	135:176b8275d35d	1103	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
<>	135:176b8275d35d	1104	* @arg @ref LL_SYSCFG_EXTI_PORTH (*)
<>	135:176b8275d35d	1105	*
<>	135:176b8275d35d	1106	* (*) value not defined in all devices.
<>	135:176b8275d35d	1107	* @param Line This parameter can be one of the following values:
<>	135:176b8275d35d	1108	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	135:176b8275d35d	1109	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	135:176b8275d35d	1110	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	135:176b8275d35d	1111	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	135:176b8275d35d	1112	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	135:176b8275d35d	1113	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	135:176b8275d35d	1114	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	135:176b8275d35d	1115	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	135:176b8275d35d	1116	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	135:176b8275d35d	1117	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	135:176b8275d35d	1118	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	135:176b8275d35d	1119	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	135:176b8275d35d	1120	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	135:176b8275d35d	1121	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	135:176b8275d35d	1122	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	135:176b8275d35d	1123	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	135:176b8275d35d	1124	* @retval None
<>	135:176b8275d35d	1125	*/
<>	135:176b8275d35d	1126	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
<>	135:176b8275d35d	1127	{
<>	135:176b8275d35d	1128	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
<>	135:176b8275d35d	1129	}
<>	135:176b8275d35d	1130
<>	135:176b8275d35d	1131	/**
<>	135:176b8275d35d	1132	* @brief Get the configured defined for specific EXTI Line
<>	135:176b8275d35d	1133	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1134	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1135	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1136	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1137	* SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1138	* SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1139	* SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1140	* SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1141	* SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1142	* SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1143	* SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1144	* SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1145	* SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1146	* SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1147	* SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1148	* SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1149	* SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1150	* SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1151	* SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1152	* SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1153	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1154	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1155	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1156	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1157	* SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1158	* SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1159	* SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1160	* SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1161	* SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1162	* SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1163	* SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1164	* SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1165	* SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1166	* SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1167	* SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1168	* SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1169	* SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1170	* SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1171	* SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1172	* SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1173	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1174	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1175	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1176	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1177	* SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1178	* SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1179	* SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1180	* SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1181	* SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1182	* SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1183	* SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1184	* SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1185	* SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1186	* SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1187	* SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1188	* SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1189	* SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1190	* SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1191	* SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1192	* SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1193	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1194	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1195	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
<>	135:176b8275d35d	1196	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
<>	135:176b8275d35d	1197	* @param Line This parameter can be one of the following values:
<>	135:176b8275d35d	1198	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	135:176b8275d35d	1199	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	135:176b8275d35d	1200	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	135:176b8275d35d	1201	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	135:176b8275d35d	1202	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	135:176b8275d35d	1203	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	135:176b8275d35d	1204	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	135:176b8275d35d	1205	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	135:176b8275d35d	1206	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	135:176b8275d35d	1207	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	135:176b8275d35d	1208	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	135:176b8275d35d	1209	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	135:176b8275d35d	1210	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	135:176b8275d35d	1211	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	135:176b8275d35d	1212	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	135:176b8275d35d	1213	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	135:176b8275d35d	1214	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1215	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	135:176b8275d35d	1216	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	135:176b8275d35d	1217	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	135:176b8275d35d	1218	* @arg @ref LL_SYSCFG_EXTI_PORTD
<>	135:176b8275d35d	1219	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	135:176b8275d35d	1220	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	135:176b8275d35d	1221	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
<>	135:176b8275d35d	1222	* @arg @ref LL_SYSCFG_EXTI_PORTH (*)
<>	135:176b8275d35d	1223	*
<>	135:176b8275d35d	1224	* (*) value not defined in all devices.
<>	135:176b8275d35d	1225	*/
<>	135:176b8275d35d	1226	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
<>	135:176b8275d35d	1227	{
<>	135:176b8275d35d	1228	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
<>	135:176b8275d35d	1229	}
<>	135:176b8275d35d	1230
<>	135:176b8275d35d	1231	/**
<>	135:176b8275d35d	1232	* @brief Set connections to TIMx Break inputs
<>	135:176b8275d35d	1233	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	135:176b8275d35d	1234	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	135:176b8275d35d	1235	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
<>	135:176b8275d35d	1236	* @param Break This parameter can be a combination of the following values:
<>	135:176b8275d35d	1237	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	135:176b8275d35d	1238	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
<>	135:176b8275d35d	1239	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	135:176b8275d35d	1240	*
<>	135:176b8275d35d	1241	* (*) value not defined in all devices.
<>	135:176b8275d35d	1242	* @retval None
<>	135:176b8275d35d	1243	*/
<>	135:176b8275d35d	1244	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
<>	135:176b8275d35d	1245	{
<>	135:176b8275d35d	1246	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
<>	135:176b8275d35d	1247	}
<>	135:176b8275d35d	1248
<>	135:176b8275d35d	1249	/**
<>	135:176b8275d35d	1250	* @brief Get connections to TIMx Break inputs
<>	135:176b8275d35d	1251	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	135:176b8275d35d	1252	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	135:176b8275d35d	1253	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
<>	135:176b8275d35d	1254	* @retval Returned value can be can be a combination of the following values:
<>	135:176b8275d35d	1255	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	135:176b8275d35d	1256	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
<>	135:176b8275d35d	1257	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	135:176b8275d35d	1258	*
<>	135:176b8275d35d	1259	* (*) value not defined in all devices.
<>	135:176b8275d35d	1260	*/
<>	135:176b8275d35d	1261	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
<>	135:176b8275d35d	1262	{
<>	135:176b8275d35d	1263	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
<>	135:176b8275d35d	1264	}
<>	135:176b8275d35d	1265
<>	135:176b8275d35d	1266	#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
<>	135:176b8275d35d	1267	/**
<>	135:176b8275d35d	1268	* @brief Disable RAM Parity Check Disable
<>	135:176b8275d35d	1269	* @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
<>	135:176b8275d35d	1270	* @retval None
<>	135:176b8275d35d	1271	*/
<>	135:176b8275d35d	1272	__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
<>	135:176b8275d35d	1273	{
<>	135:176b8275d35d	1274	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
<>	135:176b8275d35d	1275	}
<>	135:176b8275d35d	1276	#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
<>	135:176b8275d35d	1277
<>	135:176b8275d35d	1278	#if defined(SYSCFG_CFGR2_SRAM_PE)
<>	135:176b8275d35d	1279	/**
<>	135:176b8275d35d	1280	* @brief Check if SRAM parity error detected
<>	135:176b8275d35d	1281	* @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
<>	135:176b8275d35d	1282	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1283	*/
<>	135:176b8275d35d	1284	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
<>	135:176b8275d35d	1285	{
<>	135:176b8275d35d	1286	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
<>	135:176b8275d35d	1287	}
<>	135:176b8275d35d	1288
<>	135:176b8275d35d	1289	/**
<>	135:176b8275d35d	1290	* @brief Clear SRAM parity error flag
<>	135:176b8275d35d	1291	* @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
<>	135:176b8275d35d	1292	* @retval None
<>	135:176b8275d35d	1293	*/
<>	135:176b8275d35d	1294	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
<>	135:176b8275d35d	1295	{
<>	135:176b8275d35d	1296	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
<>	135:176b8275d35d	1297	}
<>	135:176b8275d35d	1298	#endif /* SYSCFG_CFGR2_SRAM_PE */
<>	135:176b8275d35d	1299
<>	135:176b8275d35d	1300	#if defined(SYSCFG_RCR_PAGE0)
<>	135:176b8275d35d	1301	/**
<>	135:176b8275d35d	1302	* @brief Enable CCM SRAM page write protection
<>	135:176b8275d35d	1303	* @note Write protection is cleared only by a system reset
<>	135:176b8275d35d	1304	* @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1305	* SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1306	* SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1307	* SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1308	* SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1309	* SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1310	* SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1311	* SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1312	* SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1313	* SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1314	* SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1315	* SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1316	* SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1317	* SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1318	* SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
<>	135:176b8275d35d	1319	* SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
<>	135:176b8275d35d	1320	* @param PageWRP This parameter can be a combination of the following values:
<>	135:176b8275d35d	1321	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
<>	135:176b8275d35d	1322	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
<>	135:176b8275d35d	1323	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
<>	135:176b8275d35d	1324	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
<>	135:176b8275d35d	1325	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
<>	135:176b8275d35d	1326	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
<>	135:176b8275d35d	1327	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
<>	135:176b8275d35d	1328	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
<>	135:176b8275d35d	1329	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
<>	135:176b8275d35d	1330	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
<>	135:176b8275d35d	1331	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
<>	135:176b8275d35d	1332	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
<>	135:176b8275d35d	1333	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
<>	135:176b8275d35d	1334	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
<>	135:176b8275d35d	1335	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
<>	135:176b8275d35d	1336	* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
<>	135:176b8275d35d	1337	*
<>	135:176b8275d35d	1338	* (*) value not defined in all devices.
<>	135:176b8275d35d	1339	* @retval None
<>	135:176b8275d35d	1340	*/
<>	135:176b8275d35d	1341	__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
<>	135:176b8275d35d	1342	{
<>	135:176b8275d35d	1343	SET_BIT(SYSCFG->RCR, PageWRP);
<>	135:176b8275d35d	1344	}
<>	135:176b8275d35d	1345	#endif /* SYSCFG_RCR_PAGE0 */
<>	135:176b8275d35d	1346
<>	135:176b8275d35d	1347	/**
<>	135:176b8275d35d	1348	* @}
<>	135:176b8275d35d	1349	*/
<>	135:176b8275d35d	1350
<>	135:176b8275d35d	1351	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<>	135:176b8275d35d	1352	* @{
<>	135:176b8275d35d	1353	*/
<>	135:176b8275d35d	1354
<>	135:176b8275d35d	1355	/**
<>	135:176b8275d35d	1356	* @brief Return the device identifier
<>	135:176b8275d35d	1357	* @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
<>	135:176b8275d35d	1358	* @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
<>	135:176b8275d35d	1359	* @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
<>	135:176b8275d35d	1360	* @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
<>	135:176b8275d35d	1361	* @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
<>	135:176b8275d35d	1362	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<>	135:176b8275d35d	1363	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<>	135:176b8275d35d	1364	*/
<>	135:176b8275d35d	1365	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<>	135:176b8275d35d	1366	{
<>	135:176b8275d35d	1367	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<>	135:176b8275d35d	1368	}
<>	135:176b8275d35d	1369
<>	135:176b8275d35d	1370	/**
<>	135:176b8275d35d	1371	* @brief Return the device revision identifier
<>	135:176b8275d35d	1372	* @note This field indicates the revision of the device.
<>	135:176b8275d35d	1373	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<>	135:176b8275d35d	1374	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<>	135:176b8275d35d	1375	*/
<>	135:176b8275d35d	1376	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<>	135:176b8275d35d	1377	{
<>	135:176b8275d35d	1378	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
<>	135:176b8275d35d	1379	}
<>	135:176b8275d35d	1380
<>	135:176b8275d35d	1381	/**
<>	135:176b8275d35d	1382	* @brief Enable the Debug Module during SLEEP mode
<>	135:176b8275d35d	1383	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
<>	135:176b8275d35d	1384	* @retval None
<>	135:176b8275d35d	1385	*/
<>	135:176b8275d35d	1386	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
<>	135:176b8275d35d	1387	{
<>	135:176b8275d35d	1388	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<>	135:176b8275d35d	1389	}
<>	135:176b8275d35d	1390
<>	135:176b8275d35d	1391	/**
<>	135:176b8275d35d	1392	* @brief Disable the Debug Module during SLEEP mode
<>	135:176b8275d35d	1393	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
<>	135:176b8275d35d	1394	* @retval None
<>	135:176b8275d35d	1395	*/
<>	135:176b8275d35d	1396	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
<>	135:176b8275d35d	1397	{
<>	135:176b8275d35d	1398	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<>	135:176b8275d35d	1399	}
<>	135:176b8275d35d	1400
<>	135:176b8275d35d	1401	/**
<>	135:176b8275d35d	1402	* @brief Enable the Debug Module during STOP mode
<>	135:176b8275d35d	1403	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<>	135:176b8275d35d	1404	* @retval None
<>	135:176b8275d35d	1405	*/
<>	135:176b8275d35d	1406	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<>	135:176b8275d35d	1407	{
<>	135:176b8275d35d	1408	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	135:176b8275d35d	1409	}
<>	135:176b8275d35d	1410
<>	135:176b8275d35d	1411	/**
<>	135:176b8275d35d	1412	* @brief Disable the Debug Module during STOP mode
<>	135:176b8275d35d	1413	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<>	135:176b8275d35d	1414	* @retval None
<>	135:176b8275d35d	1415	*/
<>	135:176b8275d35d	1416	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<>	135:176b8275d35d	1417	{
<>	135:176b8275d35d	1418	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	135:176b8275d35d	1419	}
<>	135:176b8275d35d	1420
<>	135:176b8275d35d	1421	/**
<>	135:176b8275d35d	1422	* @brief Enable the Debug Module during STANDBY mode
<>	135:176b8275d35d	1423	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<>	135:176b8275d35d	1424	* @retval None
<>	135:176b8275d35d	1425	*/
<>	135:176b8275d35d	1426	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<>	135:176b8275d35d	1427	{
<>	135:176b8275d35d	1428	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	135:176b8275d35d	1429	}
<>	135:176b8275d35d	1430
<>	135:176b8275d35d	1431	/**
<>	135:176b8275d35d	1432	* @brief Disable the Debug Module during STANDBY mode
<>	135:176b8275d35d	1433	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<>	135:176b8275d35d	1434	* @retval None
<>	135:176b8275d35d	1435	*/
<>	135:176b8275d35d	1436	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<>	135:176b8275d35d	1437	{
<>	135:176b8275d35d	1438	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	135:176b8275d35d	1439	}
<>	135:176b8275d35d	1440
<>	135:176b8275d35d	1441	/**
<>	135:176b8275d35d	1442	* @brief Set Trace pin assignment control
<>	135:176b8275d35d	1443	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
<>	135:176b8275d35d	1444	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
<>	135:176b8275d35d	1445	* @param PinAssignment This parameter can be one of the following values:
<>	135:176b8275d35d	1446	* @arg @ref LL_DBGMCU_TRACE_NONE
<>	135:176b8275d35d	1447	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
<>	135:176b8275d35d	1448	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<>	135:176b8275d35d	1449	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<>	135:176b8275d35d	1450	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<>	135:176b8275d35d	1451	* @retval None
<>	135:176b8275d35d	1452	*/
<>	135:176b8275d35d	1453	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
<>	135:176b8275d35d	1454	{
<>	135:176b8275d35d	1455	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
<>	135:176b8275d35d	1456	}
<>	135:176b8275d35d	1457
<>	135:176b8275d35d	1458	/**
<>	135:176b8275d35d	1459	* @brief Get Trace pin assignment control
<>	135:176b8275d35d	1460	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
<>	135:176b8275d35d	1461	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
<>	135:176b8275d35d	1462	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1463	* @arg @ref LL_DBGMCU_TRACE_NONE
<>	135:176b8275d35d	1464	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
<>	135:176b8275d35d	1465	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<>	135:176b8275d35d	1466	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<>	135:176b8275d35d	1467	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<>	135:176b8275d35d	1468	*/
<>	135:176b8275d35d	1469	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
<>	135:176b8275d35d	1470	{
<>	135:176b8275d35d	1471	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
<>	135:176b8275d35d	1472	}
<>	135:176b8275d35d	1473
<>	135:176b8275d35d	1474	/**
<>	135:176b8275d35d	1475	* @brief Freeze APB1 peripherals (group1 peripherals)
<>	135:176b8275d35d	1476	* @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1477	* APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1478	* APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1479	* APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1480	* APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1481	* APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1482	* APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1483	* APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1484	* APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1485	* APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1486	* APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1487	* APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1488	* APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1489	* APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1490	* APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1491	* APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1492	* APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<>	135:176b8275d35d	1493	* @param Periphs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1494	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<>	135:176b8275d35d	1495	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
<>	135:176b8275d35d	1496	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
<>	135:176b8275d35d	1497	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
<>	135:176b8275d35d	1498	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<>	135:176b8275d35d	1499	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	135:176b8275d35d	1500	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
<>	135:176b8275d35d	1501	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
<>	135:176b8275d35d	1502	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
<>	135:176b8275d35d	1503	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
<>	135:176b8275d35d	1504	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	135:176b8275d35d	1505	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	135:176b8275d35d	1506	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	135:176b8275d35d	1507	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	135:176b8275d35d	1508	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<>	135:176b8275d35d	1509	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
<>	135:176b8275d35d	1510	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	135:176b8275d35d	1511	*
<>	135:176b8275d35d	1512	* (*) value not defined in all devices.
<>	135:176b8275d35d	1513	* @retval None
<>	135:176b8275d35d	1514	*/
<>	135:176b8275d35d	1515	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<>	135:176b8275d35d	1516	{
<>	135:176b8275d35d	1517	SET_BIT(DBGMCU->APB1FZ, Periphs);
<>	135:176b8275d35d	1518	}
<>	135:176b8275d35d	1519
<>	135:176b8275d35d	1520	/**
<>	135:176b8275d35d	1521	* @brief Unfreeze APB1 peripherals (group1 peripherals)
<>	135:176b8275d35d	1522	* @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1523	* APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1524	* APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1525	* APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1526	* APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1527	* APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1528	* APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1529	* APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1530	* APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1531	* APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1532	* APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1533	* APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1534	* APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1535	* APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1536	* APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1537	* APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1538	* APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<>	135:176b8275d35d	1539	* @param Periphs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1540	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<>	135:176b8275d35d	1541	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
<>	135:176b8275d35d	1542	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
<>	135:176b8275d35d	1543	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
<>	135:176b8275d35d	1544	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<>	135:176b8275d35d	1545	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	135:176b8275d35d	1546	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
<>	135:176b8275d35d	1547	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
<>	135:176b8275d35d	1548	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
<>	135:176b8275d35d	1549	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
<>	135:176b8275d35d	1550	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	135:176b8275d35d	1551	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	135:176b8275d35d	1552	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	135:176b8275d35d	1553	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	135:176b8275d35d	1554	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<>	135:176b8275d35d	1555	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
<>	135:176b8275d35d	1556	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	135:176b8275d35d	1557	*
<>	135:176b8275d35d	1558	* (*) value not defined in all devices.
<>	135:176b8275d35d	1559	* @retval None
<>	135:176b8275d35d	1560	*/
<>	135:176b8275d35d	1561	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<>	135:176b8275d35d	1562	{
<>	135:176b8275d35d	1563	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
<>	135:176b8275d35d	1564	}
<>	135:176b8275d35d	1565
<>	135:176b8275d35d	1566	/**
<>	135:176b8275d35d	1567	* @brief Freeze APB2 peripherals
<>	135:176b8275d35d	1568	* @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1569	* APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1570	* APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1571	* APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1572	* APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1573	* APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1574	* APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<>	135:176b8275d35d	1575	* APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
<>	135:176b8275d35d	1576	* @param Periphs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1577	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
<>	135:176b8275d35d	1578	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<>	135:176b8275d35d	1579	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
<>	135:176b8275d35d	1580	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
<>	135:176b8275d35d	1581	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
<>	135:176b8275d35d	1582	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
<>	135:176b8275d35d	1583	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
<>	135:176b8275d35d	1584	* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
<>	135:176b8275d35d	1585	*
<>	135:176b8275d35d	1586	* (*) value not defined in all devices.
<>	135:176b8275d35d	1587	* @retval None
<>	135:176b8275d35d	1588	*/
<>	135:176b8275d35d	1589	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
<>	135:176b8275d35d	1590	{
<>	135:176b8275d35d	1591	SET_BIT(DBGMCU->APB2FZ, Periphs);
<>	135:176b8275d35d	1592	}
<>	135:176b8275d35d	1593
<>	135:176b8275d35d	1594	/**
<>	135:176b8275d35d	1595	* @brief Unfreeze APB2 peripherals
<>	135:176b8275d35d	1596	* @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1597	* APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1598	* APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1599	* APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1600	* APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1601	* APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1602	* APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<>	135:176b8275d35d	1603	* APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
<>	135:176b8275d35d	1604	* @param Periphs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1605	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
<>	135:176b8275d35d	1606	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<>	135:176b8275d35d	1607	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
<>	135:176b8275d35d	1608	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
<>	135:176b8275d35d	1609	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
<>	135:176b8275d35d	1610	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
<>	135:176b8275d35d	1611	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
<>	135:176b8275d35d	1612	* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
<>	135:176b8275d35d	1613	*
<>	135:176b8275d35d	1614	* (*) value not defined in all devices.
<>	135:176b8275d35d	1615	* @retval None
<>	135:176b8275d35d	1616	*/
<>	135:176b8275d35d	1617	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
<>	135:176b8275d35d	1618	{
<>	135:176b8275d35d	1619	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
<>	135:176b8275d35d	1620	}
<>	135:176b8275d35d	1621
<>	135:176b8275d35d	1622	/**
<>	135:176b8275d35d	1623	* @}
<>	135:176b8275d35d	1624	*/
<>	135:176b8275d35d	1625
<>	135:176b8275d35d	1626	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
<>	135:176b8275d35d	1627	* @{
<>	135:176b8275d35d	1628	*/
<>	135:176b8275d35d	1629
<>	135:176b8275d35d	1630	/**
<>	135:176b8275d35d	1631	* @brief Set FLASH Latency
<>	135:176b8275d35d	1632	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<>	135:176b8275d35d	1633	* @param Latency This parameter can be one of the following values:
<>	135:176b8275d35d	1634	* @arg @ref LL_FLASH_LATENCY_0
<>	135:176b8275d35d	1635	* @arg @ref LL_FLASH_LATENCY_1
<>	135:176b8275d35d	1636	* @arg @ref LL_FLASH_LATENCY_2
<>	135:176b8275d35d	1637	* @retval None
<>	135:176b8275d35d	1638	*/
<>	135:176b8275d35d	1639	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<>	135:176b8275d35d	1640	{
<>	135:176b8275d35d	1641	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<>	135:176b8275d35d	1642	}
<>	135:176b8275d35d	1643
<>	135:176b8275d35d	1644	/**
<>	135:176b8275d35d	1645	* @brief Get FLASH Latency
<>	135:176b8275d35d	1646	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<>	135:176b8275d35d	1647	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1648	* @arg @ref LL_FLASH_LATENCY_0
<>	135:176b8275d35d	1649	* @arg @ref LL_FLASH_LATENCY_1
<>	135:176b8275d35d	1650	* @arg @ref LL_FLASH_LATENCY_2
<>	135:176b8275d35d	1651	*/
<>	135:176b8275d35d	1652	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<>	135:176b8275d35d	1653	{
<>	135:176b8275d35d	1654	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<>	135:176b8275d35d	1655	}
<>	135:176b8275d35d	1656
<>	135:176b8275d35d	1657	/**
<>	135:176b8275d35d	1658	* @brief Enable Prefetch
<>	135:176b8275d35d	1659	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
<>	135:176b8275d35d	1660	* @retval None
<>	135:176b8275d35d	1661	*/
<>	135:176b8275d35d	1662	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<>	135:176b8275d35d	1663	{
<>	135:176b8275d35d	1664	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
<>	135:176b8275d35d	1665	}
<>	135:176b8275d35d	1666
<>	135:176b8275d35d	1667	/**
<>	135:176b8275d35d	1668	* @brief Disable Prefetch
<>	135:176b8275d35d	1669	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
<>	135:176b8275d35d	1670	* @retval None
<>	135:176b8275d35d	1671	*/
<>	135:176b8275d35d	1672	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<>	135:176b8275d35d	1673	{
<>	135:176b8275d35d	1674	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
<>	135:176b8275d35d	1675	}
<>	135:176b8275d35d	1676
<>	135:176b8275d35d	1677	/**
<>	135:176b8275d35d	1678	* @brief Check if Prefetch buffer is enabled
<>	135:176b8275d35d	1679	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
<>	135:176b8275d35d	1680	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1681	*/
<>	135:176b8275d35d	1682	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<>	135:176b8275d35d	1683	{
<>	135:176b8275d35d	1684	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
<>	135:176b8275d35d	1685	}
<>	135:176b8275d35d	1686
<>	135:176b8275d35d	1687	#if defined(FLASH_ACR_HLFCYA)
<>	135:176b8275d35d	1688	/**
<>	135:176b8275d35d	1689	* @brief Enable Flash Half Cycle Access
<>	135:176b8275d35d	1690	* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
<>	135:176b8275d35d	1691	* @retval None
<>	135:176b8275d35d	1692	*/
<>	135:176b8275d35d	1693	__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
<>	135:176b8275d35d	1694	{
<>	135:176b8275d35d	1695	SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<>	135:176b8275d35d	1696	}
<>	135:176b8275d35d	1697
<>	135:176b8275d35d	1698	/**
<>	135:176b8275d35d	1699	* @brief Disable Flash Half Cycle Access
<>	135:176b8275d35d	1700	* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
<>	135:176b8275d35d	1701	* @retval None
<>	135:176b8275d35d	1702	*/
<>	135:176b8275d35d	1703	__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
<>	135:176b8275d35d	1704	{
<>	135:176b8275d35d	1705	CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<>	135:176b8275d35d	1706	}
<>	135:176b8275d35d	1707
<>	135:176b8275d35d	1708	/**
<>	135:176b8275d35d	1709	* @brief Check if Flash Half Cycle Access is enabled or not
<>	135:176b8275d35d	1710	* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
<>	135:176b8275d35d	1711	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1712	*/
<>	135:176b8275d35d	1713	__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
<>	135:176b8275d35d	1714	{
<>	135:176b8275d35d	1715	return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
<>	135:176b8275d35d	1716	}
<>	135:176b8275d35d	1717	#endif /* FLASH_ACR_HLFCYA */
<>	135:176b8275d35d	1718
<>	135:176b8275d35d	1719
<>	135:176b8275d35d	1720
<>	135:176b8275d35d	1721	/**
<>	135:176b8275d35d	1722	* @}
<>	135:176b8275d35d	1723	*/
<>	135:176b8275d35d	1724
<>	135:176b8275d35d	1725	/**
<>	135:176b8275d35d	1726	* @}
<>	135:176b8275d35d	1727	*/
<>	135:176b8275d35d	1728
<>	135:176b8275d35d	1729	/**
<>	135:176b8275d35d	1730	* @}
<>	135:176b8275d35d	1731	*/
<>	135:176b8275d35d	1732
<>	135:176b8275d35d	1733	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
<>	135:176b8275d35d	1734
<>	135:176b8275d35d	1735	/**
<>	135:176b8275d35d	1736	* @}
<>	135:176b8275d35d	1737	*/
<>	135:176b8275d35d	1738
<>	135:176b8275d35d	1739	#ifdef __cplusplus
<>	135:176b8275d35d	1740	}
<>	135:176b8275d35d	1741	#endif
<>	135:176b8275d35d	1742
<>	135:176b8275d35d	1743	#endif /* __STM32F3xx_LL_SYSTEM_H */
<>	135:176b8275d35d	1744
<>	135:176b8275d35d	1745	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/