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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 14 11:24:20 2017 +0000
- Revision:
- 136:ef9c61f8c49f
- Parent:
- 135:176b8275d35d
- Child:
- 168:b9e159c1930a
Release 136 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 135:176b8275d35d | 1 | /** |
<> | 135:176b8275d35d | 2 | ****************************************************************************** |
<> | 135:176b8275d35d | 3 | * @file stm32f3xx_ll_rcc.h |
<> | 135:176b8275d35d | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
<> | 135:176b8275d35d | 7 | * @brief Header file of RCC LL module. |
<> | 135:176b8275d35d | 8 | ****************************************************************************** |
<> | 135:176b8275d35d | 9 | * @attention |
<> | 135:176b8275d35d | 10 | * |
<> | 135:176b8275d35d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 135:176b8275d35d | 12 | * |
<> | 135:176b8275d35d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 135:176b8275d35d | 14 | * are permitted provided that the following conditions are met: |
<> | 135:176b8275d35d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 135:176b8275d35d | 16 | * this list of conditions and the following disclaimer. |
<> | 135:176b8275d35d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 135:176b8275d35d | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 135:176b8275d35d | 19 | * and/or other materials provided with the distribution. |
<> | 135:176b8275d35d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 135:176b8275d35d | 21 | * may be used to endorse or promote products derived from this software |
<> | 135:176b8275d35d | 22 | * without specific prior written permission. |
<> | 135:176b8275d35d | 23 | * |
<> | 135:176b8275d35d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 135:176b8275d35d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 135:176b8275d35d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 135:176b8275d35d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 135:176b8275d35d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 135:176b8275d35d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 135:176b8275d35d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 135:176b8275d35d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 135:176b8275d35d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 135:176b8275d35d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 135:176b8275d35d | 34 | * |
<> | 135:176b8275d35d | 35 | ****************************************************************************** |
<> | 135:176b8275d35d | 36 | */ |
<> | 135:176b8275d35d | 37 | |
<> | 135:176b8275d35d | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 135:176b8275d35d | 39 | #ifndef __STM32F3xx_LL_RCC_H |
<> | 135:176b8275d35d | 40 | #define __STM32F3xx_LL_RCC_H |
<> | 135:176b8275d35d | 41 | |
<> | 135:176b8275d35d | 42 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 43 | extern "C" { |
<> | 135:176b8275d35d | 44 | #endif |
<> | 135:176b8275d35d | 45 | |
<> | 135:176b8275d35d | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 47 | #include "stm32f3xx.h" |
<> | 135:176b8275d35d | 48 | |
<> | 135:176b8275d35d | 49 | /** @addtogroup STM32F3xx_LL_Driver |
<> | 135:176b8275d35d | 50 | * @{ |
<> | 135:176b8275d35d | 51 | */ |
<> | 135:176b8275d35d | 52 | |
<> | 135:176b8275d35d | 53 | #if defined(RCC) |
<> | 135:176b8275d35d | 54 | |
<> | 135:176b8275d35d | 55 | /** @defgroup RCC_LL RCC |
<> | 135:176b8275d35d | 56 | * @{ |
<> | 135:176b8275d35d | 57 | */ |
<> | 135:176b8275d35d | 58 | |
<> | 135:176b8275d35d | 59 | /* Private types -------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 60 | /* Private variables ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 61 | /** @defgroup RCC_LL_Private_Variables RCC Private Variables |
<> | 135:176b8275d35d | 62 | * @{ |
<> | 135:176b8275d35d | 63 | */ |
<> | 135:176b8275d35d | 64 | |
<> | 135:176b8275d35d | 65 | /** |
<> | 135:176b8275d35d | 66 | * @} |
<> | 135:176b8275d35d | 67 | */ |
<> | 135:176b8275d35d | 68 | |
<> | 135:176b8275d35d | 69 | /* Private constants ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 70 | /** @defgroup RCC_LL_Private_Constants RCC Private Constants |
<> | 135:176b8275d35d | 71 | * @{ |
<> | 135:176b8275d35d | 72 | */ |
<> | 135:176b8275d35d | 73 | /* Defines used for the bit position in the register and perform offsets*/ |
<> | 135:176b8275d35d | 74 | #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ |
<> | 135:176b8275d35d | 75 | #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ |
<> | 135:176b8275d35d | 76 | #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ |
<> | 135:176b8275d35d | 77 | #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ |
<> | 135:176b8275d35d | 78 | #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ |
<> | 135:176b8275d35d | 79 | #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */ |
<> | 135:176b8275d35d | 80 | #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 81 | #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 82 | #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 83 | #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 84 | #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 85 | #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 86 | #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 87 | #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 88 | #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 89 | #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 90 | #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */ |
<> | 135:176b8275d35d | 91 | |
<> | 135:176b8275d35d | 92 | /** |
<> | 135:176b8275d35d | 93 | * @} |
<> | 135:176b8275d35d | 94 | */ |
<> | 135:176b8275d35d | 95 | |
<> | 135:176b8275d35d | 96 | /* Private macros ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 97 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 98 | /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
<> | 135:176b8275d35d | 99 | * @{ |
<> | 135:176b8275d35d | 100 | */ |
<> | 135:176b8275d35d | 101 | /** |
<> | 135:176b8275d35d | 102 | * @} |
<> | 135:176b8275d35d | 103 | */ |
<> | 135:176b8275d35d | 104 | #endif /*USE_FULL_LL_DRIVER*/ |
<> | 135:176b8275d35d | 105 | /* Exported types ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 106 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 107 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
<> | 135:176b8275d35d | 108 | * @{ |
<> | 135:176b8275d35d | 109 | */ |
<> | 135:176b8275d35d | 110 | |
<> | 135:176b8275d35d | 111 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
<> | 135:176b8275d35d | 112 | * @{ |
<> | 135:176b8275d35d | 113 | */ |
<> | 135:176b8275d35d | 114 | |
<> | 135:176b8275d35d | 115 | /** |
<> | 135:176b8275d35d | 116 | * @brief RCC Clocks Frequency Structure |
<> | 135:176b8275d35d | 117 | */ |
<> | 135:176b8275d35d | 118 | typedef struct |
<> | 135:176b8275d35d | 119 | { |
<> | 135:176b8275d35d | 120 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
<> | 135:176b8275d35d | 121 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
<> | 135:176b8275d35d | 122 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
<> | 135:176b8275d35d | 123 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
<> | 135:176b8275d35d | 124 | } LL_RCC_ClocksTypeDef; |
<> | 135:176b8275d35d | 125 | |
<> | 135:176b8275d35d | 126 | /** |
<> | 135:176b8275d35d | 127 | * @} |
<> | 135:176b8275d35d | 128 | */ |
<> | 135:176b8275d35d | 129 | |
<> | 135:176b8275d35d | 130 | /** |
<> | 135:176b8275d35d | 131 | * @} |
<> | 135:176b8275d35d | 132 | */ |
<> | 135:176b8275d35d | 133 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 134 | |
<> | 135:176b8275d35d | 135 | /* Exported constants --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 136 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
<> | 135:176b8275d35d | 137 | * @{ |
<> | 135:176b8275d35d | 138 | */ |
<> | 135:176b8275d35d | 139 | |
<> | 135:176b8275d35d | 140 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
<> | 135:176b8275d35d | 141 | * @brief Defines used to adapt values of different oscillators |
<> | 135:176b8275d35d | 142 | * @note These values could be modified in the user environment according to |
<> | 135:176b8275d35d | 143 | * HW set-up. |
<> | 135:176b8275d35d | 144 | * @{ |
<> | 135:176b8275d35d | 145 | */ |
<> | 135:176b8275d35d | 146 | #if !defined (HSE_VALUE) |
<> | 135:176b8275d35d | 147 | #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ |
<> | 135:176b8275d35d | 148 | #endif /* HSE_VALUE */ |
<> | 135:176b8275d35d | 149 | |
<> | 135:176b8275d35d | 150 | #if !defined (HSI_VALUE) |
<> | 135:176b8275d35d | 151 | #define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */ |
<> | 135:176b8275d35d | 152 | #endif /* HSI_VALUE */ |
<> | 135:176b8275d35d | 153 | |
<> | 135:176b8275d35d | 154 | #if !defined (LSE_VALUE) |
<> | 135:176b8275d35d | 155 | #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ |
<> | 135:176b8275d35d | 156 | #endif /* LSE_VALUE */ |
<> | 135:176b8275d35d | 157 | |
<> | 135:176b8275d35d | 158 | #if !defined (LSI_VALUE) |
<> | 135:176b8275d35d | 159 | #define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ |
<> | 135:176b8275d35d | 160 | #endif /* LSI_VALUE */ |
<> | 135:176b8275d35d | 161 | /** |
<> | 135:176b8275d35d | 162 | * @} |
<> | 135:176b8275d35d | 163 | */ |
<> | 135:176b8275d35d | 164 | |
<> | 135:176b8275d35d | 165 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
<> | 135:176b8275d35d | 166 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
<> | 135:176b8275d35d | 167 | * @{ |
<> | 135:176b8275d35d | 168 | */ |
<> | 135:176b8275d35d | 169 | #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
<> | 135:176b8275d35d | 170 | #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
<> | 135:176b8275d35d | 171 | #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
<> | 135:176b8275d35d | 172 | #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
<> | 135:176b8275d35d | 173 | #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
<> | 135:176b8275d35d | 174 | #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
<> | 135:176b8275d35d | 175 | /** |
<> | 135:176b8275d35d | 176 | * @} |
<> | 135:176b8275d35d | 177 | */ |
<> | 135:176b8275d35d | 178 | |
<> | 135:176b8275d35d | 179 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
<> | 135:176b8275d35d | 180 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
<> | 135:176b8275d35d | 181 | * @{ |
<> | 135:176b8275d35d | 182 | */ |
<> | 135:176b8275d35d | 183 | #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
<> | 135:176b8275d35d | 184 | #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
<> | 135:176b8275d35d | 185 | #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
<> | 135:176b8275d35d | 186 | #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
<> | 135:176b8275d35d | 187 | #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */ |
<> | 135:176b8275d35d | 188 | #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
<> | 135:176b8275d35d | 189 | #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
<> | 135:176b8275d35d | 190 | #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ |
<> | 135:176b8275d35d | 191 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
<> | 135:176b8275d35d | 192 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
<> | 135:176b8275d35d | 193 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
<> | 135:176b8275d35d | 194 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
<> | 135:176b8275d35d | 195 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
<> | 135:176b8275d35d | 196 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
<> | 135:176b8275d35d | 197 | #if defined(RCC_CSR_V18PWRRSTF) |
<> | 135:176b8275d35d | 198 | #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ |
<> | 135:176b8275d35d | 199 | #endif /* RCC_CSR_V18PWRRSTF */ |
<> | 135:176b8275d35d | 200 | /** |
<> | 135:176b8275d35d | 201 | * @} |
<> | 135:176b8275d35d | 202 | */ |
<> | 135:176b8275d35d | 203 | |
<> | 135:176b8275d35d | 204 | /** @defgroup RCC_LL_EC_IT IT Defines |
<> | 135:176b8275d35d | 205 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
<> | 135:176b8275d35d | 206 | * @{ |
<> | 135:176b8275d35d | 207 | */ |
<> | 135:176b8275d35d | 208 | #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
<> | 135:176b8275d35d | 209 | #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
<> | 135:176b8275d35d | 210 | #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
<> | 135:176b8275d35d | 211 | #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
<> | 135:176b8275d35d | 212 | #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
<> | 135:176b8275d35d | 213 | /** |
<> | 135:176b8275d35d | 214 | * @} |
<> | 135:176b8275d35d | 215 | */ |
<> | 135:176b8275d35d | 216 | |
<> | 135:176b8275d35d | 217 | /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability |
<> | 135:176b8275d35d | 218 | * @{ |
<> | 135:176b8275d35d | 219 | */ |
<> | 135:176b8275d35d | 220 | #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ |
<> | 135:176b8275d35d | 221 | #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ |
<> | 135:176b8275d35d | 222 | #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ |
<> | 135:176b8275d35d | 223 | #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ |
<> | 135:176b8275d35d | 224 | /** |
<> | 135:176b8275d35d | 225 | * @} |
<> | 135:176b8275d35d | 226 | */ |
<> | 135:176b8275d35d | 227 | |
<> | 135:176b8275d35d | 228 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
<> | 135:176b8275d35d | 229 | * @{ |
<> | 135:176b8275d35d | 230 | */ |
<> | 135:176b8275d35d | 231 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
<> | 135:176b8275d35d | 232 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
<> | 135:176b8275d35d | 233 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
<> | 135:176b8275d35d | 234 | /** |
<> | 135:176b8275d35d | 235 | * @} |
<> | 135:176b8275d35d | 236 | */ |
<> | 135:176b8275d35d | 237 | |
<> | 135:176b8275d35d | 238 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
<> | 135:176b8275d35d | 239 | * @{ |
<> | 135:176b8275d35d | 240 | */ |
<> | 135:176b8275d35d | 241 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
<> | 135:176b8275d35d | 242 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
<> | 135:176b8275d35d | 243 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
<> | 135:176b8275d35d | 244 | /** |
<> | 135:176b8275d35d | 245 | * @} |
<> | 135:176b8275d35d | 246 | */ |
<> | 135:176b8275d35d | 247 | |
<> | 135:176b8275d35d | 248 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
<> | 135:176b8275d35d | 249 | * @{ |
<> | 135:176b8275d35d | 250 | */ |
<> | 135:176b8275d35d | 251 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
<> | 135:176b8275d35d | 252 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
<> | 135:176b8275d35d | 253 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
<> | 135:176b8275d35d | 254 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
<> | 135:176b8275d35d | 255 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
<> | 135:176b8275d35d | 256 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
<> | 135:176b8275d35d | 257 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
<> | 135:176b8275d35d | 258 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
<> | 135:176b8275d35d | 259 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
<> | 135:176b8275d35d | 260 | /** |
<> | 135:176b8275d35d | 261 | * @} |
<> | 135:176b8275d35d | 262 | */ |
<> | 135:176b8275d35d | 263 | |
<> | 135:176b8275d35d | 264 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
<> | 135:176b8275d35d | 265 | * @{ |
<> | 135:176b8275d35d | 266 | */ |
<> | 135:176b8275d35d | 267 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
<> | 135:176b8275d35d | 268 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
<> | 135:176b8275d35d | 269 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
<> | 135:176b8275d35d | 270 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
<> | 135:176b8275d35d | 271 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
<> | 135:176b8275d35d | 272 | /** |
<> | 135:176b8275d35d | 273 | * @} |
<> | 135:176b8275d35d | 274 | */ |
<> | 135:176b8275d35d | 275 | |
<> | 135:176b8275d35d | 276 | /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
<> | 135:176b8275d35d | 277 | * @{ |
<> | 135:176b8275d35d | 278 | */ |
<> | 135:176b8275d35d | 279 | #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
<> | 135:176b8275d35d | 280 | #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
<> | 135:176b8275d35d | 281 | #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
<> | 135:176b8275d35d | 282 | #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
<> | 135:176b8275d35d | 283 | #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
<> | 135:176b8275d35d | 284 | /** |
<> | 135:176b8275d35d | 285 | * @} |
<> | 135:176b8275d35d | 286 | */ |
<> | 135:176b8275d35d | 287 | |
<> | 135:176b8275d35d | 288 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
<> | 135:176b8275d35d | 289 | * @{ |
<> | 135:176b8275d35d | 290 | */ |
<> | 135:176b8275d35d | 291 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
<> | 135:176b8275d35d | 292 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
<> | 135:176b8275d35d | 293 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
<> | 135:176b8275d35d | 294 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
<> | 135:176b8275d35d | 295 | #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ |
<> | 135:176b8275d35d | 296 | #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ |
<> | 135:176b8275d35d | 297 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ |
<> | 135:176b8275d35d | 298 | #if defined(RCC_CFGR_PLLNODIV) |
<> | 135:176b8275d35d | 299 | #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ |
<> | 135:176b8275d35d | 300 | #endif /* RCC_CFGR_PLLNODIV */ |
<> | 135:176b8275d35d | 301 | /** |
<> | 135:176b8275d35d | 302 | * @} |
<> | 135:176b8275d35d | 303 | */ |
<> | 135:176b8275d35d | 304 | |
<> | 135:176b8275d35d | 305 | /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler |
<> | 135:176b8275d35d | 306 | * @{ |
<> | 135:176b8275d35d | 307 | */ |
<> | 135:176b8275d35d | 308 | #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ |
<> | 135:176b8275d35d | 309 | #if defined(RCC_CFGR_MCOPRE) |
<> | 135:176b8275d35d | 310 | #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ |
<> | 135:176b8275d35d | 311 | #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ |
<> | 135:176b8275d35d | 312 | #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ |
<> | 135:176b8275d35d | 313 | #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ |
<> | 135:176b8275d35d | 314 | #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ |
<> | 135:176b8275d35d | 315 | #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ |
<> | 135:176b8275d35d | 316 | #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ |
<> | 135:176b8275d35d | 317 | #endif /* RCC_CFGR_MCOPRE */ |
<> | 135:176b8275d35d | 318 | /** |
<> | 135:176b8275d35d | 319 | * @} |
<> | 135:176b8275d35d | 320 | */ |
<> | 135:176b8275d35d | 321 | |
<> | 135:176b8275d35d | 322 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 323 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
<> | 135:176b8275d35d | 324 | * @{ |
<> | 135:176b8275d35d | 325 | */ |
<> | 135:176b8275d35d | 326 | #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ |
<> | 135:176b8275d35d | 327 | #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
<> | 135:176b8275d35d | 328 | /** |
<> | 135:176b8275d35d | 329 | * @} |
<> | 135:176b8275d35d | 330 | */ |
<> | 135:176b8275d35d | 331 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 332 | |
<> | 135:176b8275d35d | 333 | /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection |
<> | 135:176b8275d35d | 334 | * @{ |
<> | 135:176b8275d35d | 335 | */ |
<> | 135:176b8275d35d | 336 | #if defined(RCC_CFGR3_USART1SW_PCLK1) |
<> | 135:176b8275d35d | 337 | #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */ |
<> | 135:176b8275d35d | 338 | #else |
<> | 135:176b8275d35d | 339 | #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */ |
<> | 135:176b8275d35d | 340 | #endif /*RCC_CFGR3_USART1SW_PCLK1*/ |
<> | 135:176b8275d35d | 341 | #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ |
<> | 135:176b8275d35d | 342 | #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ |
<> | 135:176b8275d35d | 343 | #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ |
<> | 135:176b8275d35d | 344 | #if defined(RCC_CFGR3_USART2SW) |
<> | 135:176b8275d35d | 345 | #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ |
<> | 135:176b8275d35d | 346 | #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ |
<> | 135:176b8275d35d | 347 | #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ |
<> | 135:176b8275d35d | 348 | #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ |
<> | 135:176b8275d35d | 349 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 135:176b8275d35d | 350 | #if defined(RCC_CFGR3_USART3SW) |
<> | 135:176b8275d35d | 351 | #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ |
<> | 135:176b8275d35d | 352 | #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ |
<> | 135:176b8275d35d | 353 | #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ |
<> | 135:176b8275d35d | 354 | #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ |
<> | 135:176b8275d35d | 355 | #endif /* RCC_CFGR3_USART3SW */ |
<> | 135:176b8275d35d | 356 | /** |
<> | 135:176b8275d35d | 357 | * @} |
<> | 135:176b8275d35d | 358 | */ |
<> | 135:176b8275d35d | 359 | |
<> | 135:176b8275d35d | 360 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
<> | 135:176b8275d35d | 361 | /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection |
<> | 135:176b8275d35d | 362 | * @{ |
<> | 135:176b8275d35d | 363 | */ |
<> | 135:176b8275d35d | 364 | #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */ |
<> | 135:176b8275d35d | 365 | #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */ |
<> | 135:176b8275d35d | 366 | #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */ |
<> | 135:176b8275d35d | 367 | #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */ |
<> | 135:176b8275d35d | 368 | #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */ |
<> | 135:176b8275d35d | 369 | #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */ |
<> | 135:176b8275d35d | 370 | #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */ |
<> | 135:176b8275d35d | 371 | #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */ |
<> | 135:176b8275d35d | 372 | /** |
<> | 135:176b8275d35d | 373 | * @} |
<> | 135:176b8275d35d | 374 | */ |
<> | 135:176b8275d35d | 375 | |
<> | 135:176b8275d35d | 376 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
<> | 135:176b8275d35d | 377 | |
<> | 135:176b8275d35d | 378 | /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection |
<> | 135:176b8275d35d | 379 | * @{ |
<> | 135:176b8275d35d | 380 | */ |
<> | 135:176b8275d35d | 381 | #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */ |
<> | 135:176b8275d35d | 382 | #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */ |
<> | 135:176b8275d35d | 383 | #if defined(RCC_CFGR3_I2C2SW) |
<> | 135:176b8275d35d | 384 | #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */ |
<> | 135:176b8275d35d | 385 | #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */ |
<> | 135:176b8275d35d | 386 | #endif /*RCC_CFGR3_I2C2SW*/ |
<> | 135:176b8275d35d | 387 | #if defined(RCC_CFGR3_I2C3SW) |
<> | 135:176b8275d35d | 388 | #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */ |
<> | 135:176b8275d35d | 389 | #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */ |
<> | 135:176b8275d35d | 390 | #endif /*RCC_CFGR3_I2C3SW*/ |
<> | 135:176b8275d35d | 391 | /** |
<> | 135:176b8275d35d | 392 | * @} |
<> | 135:176b8275d35d | 393 | */ |
<> | 135:176b8275d35d | 394 | |
<> | 135:176b8275d35d | 395 | #if defined(RCC_CFGR_I2SSRC) |
<> | 135:176b8275d35d | 396 | /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection |
<> | 135:176b8275d35d | 397 | * @{ |
<> | 135:176b8275d35d | 398 | */ |
<> | 135:176b8275d35d | 399 | #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */ |
<> | 135:176b8275d35d | 400 | #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */ |
<> | 135:176b8275d35d | 401 | /** |
<> | 135:176b8275d35d | 402 | * @} |
<> | 135:176b8275d35d | 403 | */ |
<> | 135:176b8275d35d | 404 | |
<> | 135:176b8275d35d | 405 | #endif /* RCC_CFGR_I2SSRC */ |
<> | 135:176b8275d35d | 406 | |
<> | 135:176b8275d35d | 407 | #if defined(RCC_CFGR3_TIMSW) |
<> | 135:176b8275d35d | 408 | /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection |
<> | 135:176b8275d35d | 409 | * @{ |
<> | 135:176b8275d35d | 410 | */ |
<> | 135:176b8275d35d | 411 | #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */ |
<> | 135:176b8275d35d | 412 | #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */ |
<> | 135:176b8275d35d | 413 | #if defined(RCC_CFGR3_TIM8SW) |
<> | 135:176b8275d35d | 414 | #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */ |
<> | 135:176b8275d35d | 415 | #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */ |
<> | 135:176b8275d35d | 416 | #endif /*RCC_CFGR3_TIM8SW*/ |
<> | 135:176b8275d35d | 417 | #if defined(RCC_CFGR3_TIM15SW) |
<> | 135:176b8275d35d | 418 | #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */ |
<> | 135:176b8275d35d | 419 | #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */ |
<> | 135:176b8275d35d | 420 | #endif /*RCC_CFGR3_TIM15SW*/ |
<> | 135:176b8275d35d | 421 | #if defined(RCC_CFGR3_TIM16SW) |
<> | 135:176b8275d35d | 422 | #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */ |
<> | 135:176b8275d35d | 423 | #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */ |
<> | 135:176b8275d35d | 424 | #endif /*RCC_CFGR3_TIM16SW*/ |
<> | 135:176b8275d35d | 425 | #if defined(RCC_CFGR3_TIM17SW) |
<> | 135:176b8275d35d | 426 | #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */ |
<> | 135:176b8275d35d | 427 | #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */ |
<> | 135:176b8275d35d | 428 | #endif /*RCC_CFGR3_TIM17SW*/ |
<> | 135:176b8275d35d | 429 | #if defined(RCC_CFGR3_TIM20SW) |
<> | 135:176b8275d35d | 430 | #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */ |
<> | 135:176b8275d35d | 431 | #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */ |
<> | 135:176b8275d35d | 432 | #endif /*RCC_CFGR3_TIM20SW*/ |
<> | 135:176b8275d35d | 433 | #if defined(RCC_CFGR3_TIM2SW) |
<> | 135:176b8275d35d | 434 | #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */ |
<> | 135:176b8275d35d | 435 | #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */ |
<> | 135:176b8275d35d | 436 | #endif /*RCC_CFGR3_TIM2SW*/ |
<> | 135:176b8275d35d | 437 | #if defined(RCC_CFGR3_TIM34SW) |
<> | 135:176b8275d35d | 438 | #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */ |
<> | 135:176b8275d35d | 439 | #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */ |
<> | 135:176b8275d35d | 440 | #endif /*RCC_CFGR3_TIM34SW*/ |
<> | 135:176b8275d35d | 441 | /** |
<> | 135:176b8275d35d | 442 | * @} |
<> | 135:176b8275d35d | 443 | */ |
<> | 135:176b8275d35d | 444 | |
<> | 135:176b8275d35d | 445 | #endif /* RCC_CFGR3_TIMSW */ |
<> | 135:176b8275d35d | 446 | |
<> | 135:176b8275d35d | 447 | #if defined(HRTIM1) |
<> | 135:176b8275d35d | 448 | /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection |
<> | 135:176b8275d35d | 449 | * @{ |
<> | 135:176b8275d35d | 450 | */ |
<> | 135:176b8275d35d | 451 | #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */ |
<> | 135:176b8275d35d | 452 | #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */ |
<> | 135:176b8275d35d | 453 | /** |
<> | 135:176b8275d35d | 454 | * @} |
<> | 135:176b8275d35d | 455 | */ |
<> | 135:176b8275d35d | 456 | |
<> | 135:176b8275d35d | 457 | #endif /* HRTIM1 */ |
<> | 135:176b8275d35d | 458 | |
<> | 135:176b8275d35d | 459 | #if defined(CEC) |
<> | 135:176b8275d35d | 460 | /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection |
<> | 135:176b8275d35d | 461 | * @{ |
<> | 135:176b8275d35d | 462 | */ |
<> | 135:176b8275d35d | 463 | #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ |
<> | 135:176b8275d35d | 464 | #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ |
<> | 135:176b8275d35d | 465 | /** |
<> | 135:176b8275d35d | 466 | * @} |
<> | 135:176b8275d35d | 467 | */ |
<> | 135:176b8275d35d | 468 | |
<> | 135:176b8275d35d | 469 | #endif /* CEC */ |
<> | 135:176b8275d35d | 470 | |
<> | 135:176b8275d35d | 471 | #if defined(USB) |
<> | 135:176b8275d35d | 472 | /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection |
<> | 135:176b8275d35d | 473 | * @{ |
<> | 135:176b8275d35d | 474 | */ |
<> | 135:176b8275d35d | 475 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */ |
<> | 135:176b8275d35d | 476 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */ |
<> | 135:176b8275d35d | 477 | /** |
<> | 135:176b8275d35d | 478 | * @} |
<> | 135:176b8275d35d | 479 | */ |
<> | 135:176b8275d35d | 480 | |
<> | 135:176b8275d35d | 481 | #endif /* USB */ |
<> | 135:176b8275d35d | 482 | |
<> | 135:176b8275d35d | 483 | #if defined(RCC_CFGR_ADCPRE) |
<> | 135:176b8275d35d | 484 | /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection |
<> | 135:176b8275d35d | 485 | * @{ |
<> | 135:176b8275d35d | 486 | */ |
<> | 135:176b8275d35d | 487 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */ |
<> | 135:176b8275d35d | 488 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */ |
<> | 135:176b8275d35d | 489 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */ |
<> | 135:176b8275d35d | 490 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */ |
<> | 135:176b8275d35d | 491 | /** |
<> | 135:176b8275d35d | 492 | * @} |
<> | 135:176b8275d35d | 493 | */ |
<> | 135:176b8275d35d | 494 | |
<> | 135:176b8275d35d | 495 | #elif defined(RCC_CFGR2_ADC1PRES) |
<> | 135:176b8275d35d | 496 | /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection |
<> | 135:176b8275d35d | 497 | * @{ |
<> | 135:176b8275d35d | 498 | */ |
<> | 135:176b8275d35d | 499 | #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */ |
<> | 135:176b8275d35d | 500 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */ |
<> | 135:176b8275d35d | 501 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */ |
<> | 135:176b8275d35d | 502 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */ |
<> | 135:176b8275d35d | 503 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */ |
<> | 135:176b8275d35d | 504 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */ |
<> | 135:176b8275d35d | 505 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */ |
<> | 135:176b8275d35d | 506 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */ |
<> | 135:176b8275d35d | 507 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */ |
<> | 135:176b8275d35d | 508 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */ |
<> | 135:176b8275d35d | 509 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */ |
<> | 135:176b8275d35d | 510 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */ |
<> | 135:176b8275d35d | 511 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */ |
<> | 135:176b8275d35d | 512 | /** |
<> | 135:176b8275d35d | 513 | * @} |
<> | 135:176b8275d35d | 514 | */ |
<> | 135:176b8275d35d | 515 | |
<> | 135:176b8275d35d | 516 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 517 | #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 518 | /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection |
<> | 135:176b8275d35d | 519 | * @{ |
<> | 135:176b8275d35d | 520 | */ |
<> | 135:176b8275d35d | 521 | #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
<> | 135:176b8275d35d | 522 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */ |
<> | 135:176b8275d35d | 523 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */ |
<> | 135:176b8275d35d | 524 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */ |
<> | 135:176b8275d35d | 525 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */ |
<> | 135:176b8275d35d | 526 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */ |
<> | 135:176b8275d35d | 527 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */ |
<> | 135:176b8275d35d | 528 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */ |
<> | 135:176b8275d35d | 529 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */ |
<> | 135:176b8275d35d | 530 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */ |
<> | 135:176b8275d35d | 531 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */ |
<> | 135:176b8275d35d | 532 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */ |
<> | 135:176b8275d35d | 533 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */ |
<> | 135:176b8275d35d | 534 | /** |
<> | 135:176b8275d35d | 535 | * @} |
<> | 135:176b8275d35d | 536 | */ |
<> | 135:176b8275d35d | 537 | |
<> | 135:176b8275d35d | 538 | /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection |
<> | 135:176b8275d35d | 539 | * @{ |
<> | 135:176b8275d35d | 540 | */ |
<> | 135:176b8275d35d | 541 | #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ |
<> | 135:176b8275d35d | 542 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */ |
<> | 135:176b8275d35d | 543 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */ |
<> | 135:176b8275d35d | 544 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */ |
<> | 135:176b8275d35d | 545 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */ |
<> | 135:176b8275d35d | 546 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */ |
<> | 135:176b8275d35d | 547 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */ |
<> | 135:176b8275d35d | 548 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */ |
<> | 135:176b8275d35d | 549 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */ |
<> | 135:176b8275d35d | 550 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */ |
<> | 135:176b8275d35d | 551 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */ |
<> | 135:176b8275d35d | 552 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */ |
<> | 135:176b8275d35d | 553 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */ |
<> | 135:176b8275d35d | 554 | /** |
<> | 135:176b8275d35d | 555 | * @} |
<> | 135:176b8275d35d | 556 | */ |
<> | 135:176b8275d35d | 557 | |
<> | 135:176b8275d35d | 558 | #else |
<> | 135:176b8275d35d | 559 | /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection |
<> | 135:176b8275d35d | 560 | * @{ |
<> | 135:176b8275d35d | 561 | */ |
<> | 135:176b8275d35d | 562 | #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
<> | 135:176b8275d35d | 563 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */ |
<> | 135:176b8275d35d | 564 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */ |
<> | 135:176b8275d35d | 565 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */ |
<> | 135:176b8275d35d | 566 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */ |
<> | 135:176b8275d35d | 567 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */ |
<> | 135:176b8275d35d | 568 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */ |
<> | 135:176b8275d35d | 569 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */ |
<> | 135:176b8275d35d | 570 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */ |
<> | 135:176b8275d35d | 571 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */ |
<> | 135:176b8275d35d | 572 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */ |
<> | 135:176b8275d35d | 573 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */ |
<> | 135:176b8275d35d | 574 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */ |
<> | 135:176b8275d35d | 575 | /** |
<> | 135:176b8275d35d | 576 | * @} |
<> | 135:176b8275d35d | 577 | */ |
<> | 135:176b8275d35d | 578 | |
<> | 135:176b8275d35d | 579 | #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */ |
<> | 135:176b8275d35d | 580 | |
<> | 135:176b8275d35d | 581 | #endif /* RCC_CFGR_ADCPRE */ |
<> | 135:176b8275d35d | 582 | |
<> | 135:176b8275d35d | 583 | #if defined(RCC_CFGR_SDPRE) |
<> | 135:176b8275d35d | 584 | /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection |
<> | 135:176b8275d35d | 585 | * @{ |
<> | 135:176b8275d35d | 586 | */ |
<> | 135:176b8275d35d | 587 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */ |
<> | 135:176b8275d35d | 588 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */ |
<> | 135:176b8275d35d | 589 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */ |
<> | 135:176b8275d35d | 590 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */ |
<> | 135:176b8275d35d | 591 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */ |
<> | 135:176b8275d35d | 592 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */ |
<> | 135:176b8275d35d | 593 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */ |
<> | 135:176b8275d35d | 594 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */ |
<> | 135:176b8275d35d | 595 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */ |
<> | 135:176b8275d35d | 596 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */ |
<> | 135:176b8275d35d | 597 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */ |
<> | 135:176b8275d35d | 598 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */ |
<> | 135:176b8275d35d | 599 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */ |
<> | 135:176b8275d35d | 600 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */ |
<> | 135:176b8275d35d | 601 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */ |
<> | 135:176b8275d35d | 602 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */ |
<> | 135:176b8275d35d | 603 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */ |
<> | 135:176b8275d35d | 604 | /** |
<> | 135:176b8275d35d | 605 | * @} |
<> | 135:176b8275d35d | 606 | */ |
<> | 135:176b8275d35d | 607 | |
<> | 135:176b8275d35d | 608 | #endif /* RCC_CFGR_SDPRE */ |
<> | 135:176b8275d35d | 609 | |
<> | 135:176b8275d35d | 610 | /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source |
<> | 135:176b8275d35d | 611 | * @{ |
<> | 135:176b8275d35d | 612 | */ |
<> | 135:176b8275d35d | 613 | #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ |
<> | 135:176b8275d35d | 614 | #if defined(RCC_CFGR3_USART2SW) |
<> | 135:176b8275d35d | 615 | #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ |
<> | 135:176b8275d35d | 616 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 135:176b8275d35d | 617 | #if defined(RCC_CFGR3_USART3SW) |
<> | 135:176b8275d35d | 618 | #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ |
<> | 135:176b8275d35d | 619 | #endif /* RCC_CFGR3_USART3SW */ |
<> | 135:176b8275d35d | 620 | /** |
<> | 135:176b8275d35d | 621 | * @} |
<> | 135:176b8275d35d | 622 | */ |
<> | 135:176b8275d35d | 623 | |
<> | 135:176b8275d35d | 624 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
<> | 135:176b8275d35d | 625 | /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source |
<> | 135:176b8275d35d | 626 | * @{ |
<> | 135:176b8275d35d | 627 | */ |
<> | 135:176b8275d35d | 628 | #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */ |
<> | 135:176b8275d35d | 629 | #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */ |
<> | 135:176b8275d35d | 630 | /** |
<> | 135:176b8275d35d | 631 | * @} |
<> | 135:176b8275d35d | 632 | */ |
<> | 135:176b8275d35d | 633 | |
<> | 135:176b8275d35d | 634 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
<> | 135:176b8275d35d | 635 | |
<> | 135:176b8275d35d | 636 | /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source |
<> | 135:176b8275d35d | 637 | * @{ |
<> | 135:176b8275d35d | 638 | */ |
<> | 135:176b8275d35d | 639 | #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ |
<> | 135:176b8275d35d | 640 | #if defined(RCC_CFGR3_I2C2SW) |
<> | 135:176b8275d35d | 641 | #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */ |
<> | 135:176b8275d35d | 642 | #endif /*RCC_CFGR3_I2C2SW*/ |
<> | 135:176b8275d35d | 643 | #if defined(RCC_CFGR3_I2C3SW) |
<> | 135:176b8275d35d | 644 | #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */ |
<> | 135:176b8275d35d | 645 | #endif /*RCC_CFGR3_I2C3SW*/ |
<> | 135:176b8275d35d | 646 | /** |
<> | 135:176b8275d35d | 647 | * @} |
<> | 135:176b8275d35d | 648 | */ |
<> | 135:176b8275d35d | 649 | |
<> | 135:176b8275d35d | 650 | #if defined(RCC_CFGR_I2SSRC) |
<> | 135:176b8275d35d | 651 | /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source |
<> | 135:176b8275d35d | 652 | * @{ |
<> | 135:176b8275d35d | 653 | */ |
<> | 135:176b8275d35d | 654 | #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ |
<> | 135:176b8275d35d | 655 | /** |
<> | 135:176b8275d35d | 656 | * @} |
<> | 135:176b8275d35d | 657 | */ |
<> | 135:176b8275d35d | 658 | |
<> | 135:176b8275d35d | 659 | #endif /* RCC_CFGR_I2SSRC */ |
<> | 135:176b8275d35d | 660 | |
<> | 135:176b8275d35d | 661 | #if defined(RCC_CFGR3_TIMSW) |
<> | 135:176b8275d35d | 662 | /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source |
<> | 135:176b8275d35d | 663 | * @{ |
<> | 135:176b8275d35d | 664 | */ |
<> | 135:176b8275d35d | 665 | #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */ |
<> | 135:176b8275d35d | 666 | #if defined(RCC_CFGR3_TIM2SW) |
<> | 135:176b8275d35d | 667 | #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */ |
<> | 135:176b8275d35d | 668 | #endif /*RCC_CFGR3_TIM2SW*/ |
<> | 135:176b8275d35d | 669 | #if defined(RCC_CFGR3_TIM8SW) |
<> | 135:176b8275d35d | 670 | #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */ |
<> | 135:176b8275d35d | 671 | #endif /*RCC_CFGR3_TIM8SW*/ |
<> | 135:176b8275d35d | 672 | #if defined(RCC_CFGR3_TIM15SW) |
<> | 135:176b8275d35d | 673 | #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */ |
<> | 135:176b8275d35d | 674 | #endif /*RCC_CFGR3_TIM15SW*/ |
<> | 135:176b8275d35d | 675 | #if defined(RCC_CFGR3_TIM16SW) |
<> | 135:176b8275d35d | 676 | #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */ |
<> | 135:176b8275d35d | 677 | #endif /*RCC_CFGR3_TIM16SW*/ |
<> | 135:176b8275d35d | 678 | #if defined(RCC_CFGR3_TIM17SW) |
<> | 135:176b8275d35d | 679 | #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */ |
<> | 135:176b8275d35d | 680 | #endif /*RCC_CFGR3_TIM17SW*/ |
<> | 135:176b8275d35d | 681 | #if defined(RCC_CFGR3_TIM20SW) |
<> | 135:176b8275d35d | 682 | #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */ |
<> | 135:176b8275d35d | 683 | #endif /*RCC_CFGR3_TIM20SW*/ |
<> | 135:176b8275d35d | 684 | #if defined(RCC_CFGR3_TIM34SW) |
<> | 135:176b8275d35d | 685 | #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */ |
<> | 135:176b8275d35d | 686 | #endif /*RCC_CFGR3_TIM34SW*/ |
<> | 135:176b8275d35d | 687 | /** |
<> | 135:176b8275d35d | 688 | * @} |
<> | 135:176b8275d35d | 689 | */ |
<> | 135:176b8275d35d | 690 | |
<> | 135:176b8275d35d | 691 | #endif /* RCC_CFGR3_TIMSW */ |
<> | 135:176b8275d35d | 692 | |
<> | 135:176b8275d35d | 693 | #if defined(HRTIM1) |
<> | 135:176b8275d35d | 694 | /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source |
<> | 135:176b8275d35d | 695 | * @{ |
<> | 135:176b8275d35d | 696 | */ |
<> | 135:176b8275d35d | 697 | #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */ |
<> | 135:176b8275d35d | 698 | /** |
<> | 135:176b8275d35d | 699 | * @} |
<> | 135:176b8275d35d | 700 | */ |
<> | 135:176b8275d35d | 701 | |
<> | 135:176b8275d35d | 702 | #endif /* HRTIM1 */ |
<> | 135:176b8275d35d | 703 | |
<> | 135:176b8275d35d | 704 | #if defined(CEC) |
<> | 135:176b8275d35d | 705 | /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source |
<> | 135:176b8275d35d | 706 | * @{ |
<> | 135:176b8275d35d | 707 | */ |
<> | 135:176b8275d35d | 708 | #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ |
<> | 135:176b8275d35d | 709 | /** |
<> | 135:176b8275d35d | 710 | * @} |
<> | 135:176b8275d35d | 711 | */ |
<> | 135:176b8275d35d | 712 | |
<> | 135:176b8275d35d | 713 | #endif /* CEC */ |
<> | 135:176b8275d35d | 714 | |
<> | 135:176b8275d35d | 715 | #if defined(USB) |
<> | 135:176b8275d35d | 716 | /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source |
<> | 135:176b8275d35d | 717 | * @{ |
<> | 135:176b8275d35d | 718 | */ |
<> | 135:176b8275d35d | 719 | #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */ |
<> | 135:176b8275d35d | 720 | /** |
<> | 135:176b8275d35d | 721 | * @} |
<> | 135:176b8275d35d | 722 | */ |
<> | 135:176b8275d35d | 723 | |
<> | 135:176b8275d35d | 724 | #endif /* USB */ |
<> | 135:176b8275d35d | 725 | |
<> | 135:176b8275d35d | 726 | #if defined(RCC_CFGR_ADCPRE) |
<> | 135:176b8275d35d | 727 | /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source |
<> | 135:176b8275d35d | 728 | * @{ |
<> | 135:176b8275d35d | 729 | */ |
<> | 135:176b8275d35d | 730 | #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ |
<> | 135:176b8275d35d | 731 | /** |
<> | 135:176b8275d35d | 732 | * @} |
<> | 135:176b8275d35d | 733 | */ |
<> | 135:176b8275d35d | 734 | |
<> | 135:176b8275d35d | 735 | #endif /* RCC_CFGR_ADCPRE */ |
<> | 135:176b8275d35d | 736 | |
<> | 135:176b8275d35d | 737 | #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 738 | /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source |
<> | 135:176b8275d35d | 739 | * @{ |
<> | 135:176b8275d35d | 740 | */ |
<> | 135:176b8275d35d | 741 | #if defined(RCC_CFGR2_ADC1PRES) |
<> | 135:176b8275d35d | 742 | #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */ |
<> | 135:176b8275d35d | 743 | #else |
<> | 135:176b8275d35d | 744 | #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */ |
<> | 135:176b8275d35d | 745 | #if defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 746 | #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */ |
<> | 135:176b8275d35d | 747 | #endif /*RCC_CFGR2_ADCPRE34*/ |
<> | 135:176b8275d35d | 748 | #endif /*RCC_CFGR2_ADC1PRES*/ |
<> | 135:176b8275d35d | 749 | /** |
<> | 135:176b8275d35d | 750 | * @} |
<> | 135:176b8275d35d | 751 | */ |
<> | 135:176b8275d35d | 752 | |
<> | 135:176b8275d35d | 753 | #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ |
<> | 135:176b8275d35d | 754 | |
<> | 135:176b8275d35d | 755 | #if defined(RCC_CFGR_SDPRE) |
<> | 135:176b8275d35d | 756 | /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source |
<> | 135:176b8275d35d | 757 | * @{ |
<> | 135:176b8275d35d | 758 | */ |
<> | 135:176b8275d35d | 759 | #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */ |
<> | 135:176b8275d35d | 760 | /** |
<> | 135:176b8275d35d | 761 | * @} |
<> | 135:176b8275d35d | 762 | */ |
<> | 135:176b8275d35d | 763 | |
<> | 135:176b8275d35d | 764 | #endif /* RCC_CFGR_SDPRE */ |
<> | 135:176b8275d35d | 765 | |
<> | 135:176b8275d35d | 766 | |
<> | 135:176b8275d35d | 767 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
<> | 135:176b8275d35d | 768 | * @{ |
<> | 135:176b8275d35d | 769 | */ |
<> | 135:176b8275d35d | 770 | #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ |
<> | 135:176b8275d35d | 771 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
<> | 135:176b8275d35d | 772 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
<> | 135:176b8275d35d | 773 | #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
<> | 135:176b8275d35d | 774 | /** |
<> | 135:176b8275d35d | 775 | * @} |
<> | 135:176b8275d35d | 776 | */ |
<> | 135:176b8275d35d | 777 | |
<> | 135:176b8275d35d | 778 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
<> | 135:176b8275d35d | 779 | * @{ |
<> | 135:176b8275d35d | 780 | */ |
<> | 135:176b8275d35d | 781 | #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ |
<> | 135:176b8275d35d | 782 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ |
<> | 135:176b8275d35d | 783 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ |
<> | 135:176b8275d35d | 784 | #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ |
<> | 135:176b8275d35d | 785 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ |
<> | 135:176b8275d35d | 786 | #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ |
<> | 135:176b8275d35d | 787 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ |
<> | 135:176b8275d35d | 788 | #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ |
<> | 135:176b8275d35d | 789 | #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ |
<> | 135:176b8275d35d | 790 | #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ |
<> | 135:176b8275d35d | 791 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ |
<> | 135:176b8275d35d | 792 | #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ |
<> | 135:176b8275d35d | 793 | #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ |
<> | 135:176b8275d35d | 794 | #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ |
<> | 135:176b8275d35d | 795 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ |
<> | 135:176b8275d35d | 796 | /** |
<> | 135:176b8275d35d | 797 | * @} |
<> | 135:176b8275d35d | 798 | */ |
<> | 135:176b8275d35d | 799 | |
<> | 135:176b8275d35d | 800 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
<> | 135:176b8275d35d | 801 | * @{ |
<> | 135:176b8275d35d | 802 | */ |
<> | 135:176b8275d35d | 803 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 804 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 135:176b8275d35d | 805 | #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 806 | #else |
<> | 135:176b8275d35d | 807 | #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 808 | #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 809 | #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 810 | #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 811 | #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 812 | #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 813 | #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 814 | #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 815 | #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 816 | #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 817 | #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 818 | #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 819 | #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 820 | #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 821 | #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 822 | #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 823 | #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ |
<> | 135:176b8275d35d | 824 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 135:176b8275d35d | 825 | /** |
<> | 135:176b8275d35d | 826 | * @} |
<> | 135:176b8275d35d | 827 | */ |
<> | 135:176b8275d35d | 828 | |
<> | 135:176b8275d35d | 829 | /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor |
<> | 135:176b8275d35d | 830 | * @{ |
<> | 135:176b8275d35d | 831 | */ |
<> | 135:176b8275d35d | 832 | #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ |
<> | 135:176b8275d35d | 833 | #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ |
<> | 135:176b8275d35d | 834 | #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ |
<> | 135:176b8275d35d | 835 | #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ |
<> | 135:176b8275d35d | 836 | #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ |
<> | 135:176b8275d35d | 837 | #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ |
<> | 135:176b8275d35d | 838 | #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ |
<> | 135:176b8275d35d | 839 | #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ |
<> | 135:176b8275d35d | 840 | #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ |
<> | 135:176b8275d35d | 841 | #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ |
<> | 135:176b8275d35d | 842 | #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ |
<> | 135:176b8275d35d | 843 | #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ |
<> | 135:176b8275d35d | 844 | #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ |
<> | 135:176b8275d35d | 845 | #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ |
<> | 135:176b8275d35d | 846 | #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ |
<> | 135:176b8275d35d | 847 | #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ |
<> | 135:176b8275d35d | 848 | /** |
<> | 135:176b8275d35d | 849 | * @} |
<> | 135:176b8275d35d | 850 | */ |
<> | 135:176b8275d35d | 851 | |
<> | 135:176b8275d35d | 852 | /** |
<> | 135:176b8275d35d | 853 | * @} |
<> | 135:176b8275d35d | 854 | */ |
<> | 135:176b8275d35d | 855 | |
<> | 135:176b8275d35d | 856 | /* Exported macro ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 857 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
<> | 135:176b8275d35d | 858 | * @{ |
<> | 135:176b8275d35d | 859 | */ |
<> | 135:176b8275d35d | 860 | |
<> | 135:176b8275d35d | 861 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
<> | 135:176b8275d35d | 862 | * @{ |
<> | 135:176b8275d35d | 863 | */ |
<> | 135:176b8275d35d | 864 | |
<> | 135:176b8275d35d | 865 | /** |
<> | 135:176b8275d35d | 866 | * @brief Write a value in RCC register |
<> | 135:176b8275d35d | 867 | * @param __REG__ Register to be written |
<> | 135:176b8275d35d | 868 | * @param __VALUE__ Value to be written in the register |
<> | 135:176b8275d35d | 869 | * @retval None |
<> | 135:176b8275d35d | 870 | */ |
<> | 135:176b8275d35d | 871 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
<> | 135:176b8275d35d | 872 | |
<> | 135:176b8275d35d | 873 | /** |
<> | 135:176b8275d35d | 874 | * @brief Read a value in RCC register |
<> | 135:176b8275d35d | 875 | * @param __REG__ Register to be read |
<> | 135:176b8275d35d | 876 | * @retval Register value |
<> | 135:176b8275d35d | 877 | */ |
<> | 135:176b8275d35d | 878 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
<> | 135:176b8275d35d | 879 | /** |
<> | 135:176b8275d35d | 880 | * @} |
<> | 135:176b8275d35d | 881 | */ |
<> | 135:176b8275d35d | 882 | |
<> | 135:176b8275d35d | 883 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
<> | 135:176b8275d35d | 884 | * @{ |
<> | 135:176b8275d35d | 885 | */ |
<> | 135:176b8275d35d | 886 | |
<> | 135:176b8275d35d | 887 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 135:176b8275d35d | 888 | /** |
<> | 135:176b8275d35d | 889 | * @brief Helper macro to calculate the PLLCLK frequency |
<> | 135:176b8275d35d | 890 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() |
<> | 135:176b8275d35d | 891 | * , @ref LL_RCC_PLL_GetPrediv()); |
<> | 135:176b8275d35d | 892 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) |
<> | 135:176b8275d35d | 893 | * @param __PLLMUL__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 894 | * @arg @ref LL_RCC_PLL_MUL_2 |
<> | 135:176b8275d35d | 895 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 135:176b8275d35d | 896 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 135:176b8275d35d | 897 | * @arg @ref LL_RCC_PLL_MUL_5 |
<> | 135:176b8275d35d | 898 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 135:176b8275d35d | 899 | * @arg @ref LL_RCC_PLL_MUL_7 |
<> | 135:176b8275d35d | 900 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 135:176b8275d35d | 901 | * @arg @ref LL_RCC_PLL_MUL_9 |
<> | 135:176b8275d35d | 902 | * @arg @ref LL_RCC_PLL_MUL_10 |
<> | 135:176b8275d35d | 903 | * @arg @ref LL_RCC_PLL_MUL_11 |
<> | 135:176b8275d35d | 904 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 135:176b8275d35d | 905 | * @arg @ref LL_RCC_PLL_MUL_13 |
<> | 135:176b8275d35d | 906 | * @arg @ref LL_RCC_PLL_MUL_14 |
<> | 135:176b8275d35d | 907 | * @arg @ref LL_RCC_PLL_MUL_15 |
<> | 135:176b8275d35d | 908 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 135:176b8275d35d | 909 | * @param __PLLPREDIV__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 910 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
<> | 135:176b8275d35d | 911 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
<> | 135:176b8275d35d | 912 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
<> | 135:176b8275d35d | 913 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
<> | 135:176b8275d35d | 914 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
<> | 135:176b8275d35d | 915 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
<> | 135:176b8275d35d | 916 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
<> | 135:176b8275d35d | 917 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
<> | 135:176b8275d35d | 918 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
<> | 135:176b8275d35d | 919 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
<> | 135:176b8275d35d | 920 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
<> | 135:176b8275d35d | 921 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
<> | 135:176b8275d35d | 922 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
<> | 135:176b8275d35d | 923 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
<> | 135:176b8275d35d | 924 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
<> | 135:176b8275d35d | 925 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
<> | 135:176b8275d35d | 926 | * @retval PLL clock frequency (in Hz) |
<> | 135:176b8275d35d | 927 | */ |
<> | 135:176b8275d35d | 928 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ |
<> | 135:176b8275d35d | 929 | (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
<> | 135:176b8275d35d | 930 | |
<> | 135:176b8275d35d | 931 | #else |
<> | 135:176b8275d35d | 932 | /** |
<> | 135:176b8275d35d | 933 | * @brief Helper macro to calculate the PLLCLK frequency |
<> | 135:176b8275d35d | 934 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); |
<> | 135:176b8275d35d | 935 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) |
<> | 135:176b8275d35d | 936 | * @param __PLLMUL__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 937 | * @arg @ref LL_RCC_PLL_MUL_2 |
<> | 135:176b8275d35d | 938 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 135:176b8275d35d | 939 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 135:176b8275d35d | 940 | * @arg @ref LL_RCC_PLL_MUL_5 |
<> | 135:176b8275d35d | 941 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 135:176b8275d35d | 942 | * @arg @ref LL_RCC_PLL_MUL_7 |
<> | 135:176b8275d35d | 943 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 135:176b8275d35d | 944 | * @arg @ref LL_RCC_PLL_MUL_9 |
<> | 135:176b8275d35d | 945 | * @arg @ref LL_RCC_PLL_MUL_10 |
<> | 135:176b8275d35d | 946 | * @arg @ref LL_RCC_PLL_MUL_11 |
<> | 135:176b8275d35d | 947 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 135:176b8275d35d | 948 | * @arg @ref LL_RCC_PLL_MUL_13 |
<> | 135:176b8275d35d | 949 | * @arg @ref LL_RCC_PLL_MUL_14 |
<> | 135:176b8275d35d | 950 | * @arg @ref LL_RCC_PLL_MUL_15 |
<> | 135:176b8275d35d | 951 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 135:176b8275d35d | 952 | * @retval PLL clock frequency (in Hz) |
<> | 135:176b8275d35d | 953 | */ |
<> | 135:176b8275d35d | 954 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ |
<> | 135:176b8275d35d | 955 | ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
<> | 135:176b8275d35d | 956 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 135:176b8275d35d | 957 | /** |
<> | 135:176b8275d35d | 958 | * @brief Helper macro to calculate the HCLK frequency |
<> | 135:176b8275d35d | 959 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
<> | 135:176b8275d35d | 960 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
<> | 135:176b8275d35d | 961 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) |
<> | 135:176b8275d35d | 962 | * @param __AHBPRESCALER__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 963 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 135:176b8275d35d | 964 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 135:176b8275d35d | 965 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 135:176b8275d35d | 966 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 135:176b8275d35d | 967 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 135:176b8275d35d | 968 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 135:176b8275d35d | 969 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 135:176b8275d35d | 970 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 135:176b8275d35d | 971 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 135:176b8275d35d | 972 | * @retval HCLK clock frequency (in Hz) |
<> | 135:176b8275d35d | 973 | */ |
<> | 135:176b8275d35d | 974 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) |
<> | 135:176b8275d35d | 975 | |
<> | 135:176b8275d35d | 976 | /** |
<> | 135:176b8275d35d | 977 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
<> | 135:176b8275d35d | 978 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
<> | 135:176b8275d35d | 979 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
<> | 135:176b8275d35d | 980 | * @param __HCLKFREQ__ HCLK frequency |
<> | 135:176b8275d35d | 981 | * @param __APB1PRESCALER__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 982 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 135:176b8275d35d | 983 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 135:176b8275d35d | 984 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 135:176b8275d35d | 985 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 135:176b8275d35d | 986 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 135:176b8275d35d | 987 | * @retval PCLK1 clock frequency (in Hz) |
<> | 135:176b8275d35d | 988 | */ |
<> | 135:176b8275d35d | 989 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) |
<> | 135:176b8275d35d | 990 | |
<> | 135:176b8275d35d | 991 | /** |
<> | 135:176b8275d35d | 992 | * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
<> | 135:176b8275d35d | 993 | * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler |
<> | 135:176b8275d35d | 994 | * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) |
<> | 135:176b8275d35d | 995 | * @param __HCLKFREQ__ HCLK frequency |
<> | 135:176b8275d35d | 996 | * @param __APB2PRESCALER__: This parameter can be one of the following values: |
<> | 135:176b8275d35d | 997 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 135:176b8275d35d | 998 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 135:176b8275d35d | 999 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 135:176b8275d35d | 1000 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 135:176b8275d35d | 1001 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 135:176b8275d35d | 1002 | * @retval PCLK2 clock frequency (in Hz) |
<> | 135:176b8275d35d | 1003 | */ |
<> | 135:176b8275d35d | 1004 | #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) |
<> | 135:176b8275d35d | 1005 | |
<> | 135:176b8275d35d | 1006 | /** |
<> | 135:176b8275d35d | 1007 | * @} |
<> | 135:176b8275d35d | 1008 | */ |
<> | 135:176b8275d35d | 1009 | |
<> | 135:176b8275d35d | 1010 | /** |
<> | 135:176b8275d35d | 1011 | * @} |
<> | 135:176b8275d35d | 1012 | */ |
<> | 135:176b8275d35d | 1013 | |
<> | 135:176b8275d35d | 1014 | /* Exported functions --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 1015 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
<> | 135:176b8275d35d | 1016 | * @{ |
<> | 135:176b8275d35d | 1017 | */ |
<> | 135:176b8275d35d | 1018 | |
<> | 135:176b8275d35d | 1019 | /** @defgroup RCC_LL_EF_HSE HSE |
<> | 135:176b8275d35d | 1020 | * @{ |
<> | 135:176b8275d35d | 1021 | */ |
<> | 135:176b8275d35d | 1022 | |
<> | 135:176b8275d35d | 1023 | /** |
<> | 135:176b8275d35d | 1024 | * @brief Enable the Clock Security System. |
<> | 135:176b8275d35d | 1025 | * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
<> | 135:176b8275d35d | 1026 | * @retval None |
<> | 135:176b8275d35d | 1027 | */ |
<> | 135:176b8275d35d | 1028 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
<> | 135:176b8275d35d | 1029 | { |
<> | 135:176b8275d35d | 1030 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
<> | 135:176b8275d35d | 1031 | } |
<> | 135:176b8275d35d | 1032 | |
<> | 135:176b8275d35d | 1033 | /** |
<> | 135:176b8275d35d | 1034 | * @brief Disable the Clock Security System. |
<> | 135:176b8275d35d | 1035 | * @note Cannot be disabled in HSE is ready (only by hardware) |
<> | 135:176b8275d35d | 1036 | * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS |
<> | 135:176b8275d35d | 1037 | * @retval None |
<> | 135:176b8275d35d | 1038 | */ |
<> | 135:176b8275d35d | 1039 | __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) |
<> | 135:176b8275d35d | 1040 | { |
<> | 135:176b8275d35d | 1041 | CLEAR_BIT(RCC->CR, RCC_CR_CSSON); |
<> | 135:176b8275d35d | 1042 | } |
<> | 135:176b8275d35d | 1043 | |
<> | 135:176b8275d35d | 1044 | /** |
<> | 135:176b8275d35d | 1045 | * @brief Enable HSE external oscillator (HSE Bypass) |
<> | 135:176b8275d35d | 1046 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
<> | 135:176b8275d35d | 1047 | * @retval None |
<> | 135:176b8275d35d | 1048 | */ |
<> | 135:176b8275d35d | 1049 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
<> | 135:176b8275d35d | 1050 | { |
<> | 135:176b8275d35d | 1051 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
<> | 135:176b8275d35d | 1052 | } |
<> | 135:176b8275d35d | 1053 | |
<> | 135:176b8275d35d | 1054 | /** |
<> | 135:176b8275d35d | 1055 | * @brief Disable HSE external oscillator (HSE Bypass) |
<> | 135:176b8275d35d | 1056 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
<> | 135:176b8275d35d | 1057 | * @retval None |
<> | 135:176b8275d35d | 1058 | */ |
<> | 135:176b8275d35d | 1059 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
<> | 135:176b8275d35d | 1060 | { |
<> | 135:176b8275d35d | 1061 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
<> | 135:176b8275d35d | 1062 | } |
<> | 135:176b8275d35d | 1063 | |
<> | 135:176b8275d35d | 1064 | /** |
<> | 135:176b8275d35d | 1065 | * @brief Enable HSE crystal oscillator (HSE ON) |
<> | 135:176b8275d35d | 1066 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
<> | 135:176b8275d35d | 1067 | * @retval None |
<> | 135:176b8275d35d | 1068 | */ |
<> | 135:176b8275d35d | 1069 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
<> | 135:176b8275d35d | 1070 | { |
<> | 135:176b8275d35d | 1071 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
<> | 135:176b8275d35d | 1072 | } |
<> | 135:176b8275d35d | 1073 | |
<> | 135:176b8275d35d | 1074 | /** |
<> | 135:176b8275d35d | 1075 | * @brief Disable HSE crystal oscillator (HSE ON) |
<> | 135:176b8275d35d | 1076 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
<> | 135:176b8275d35d | 1077 | * @retval None |
<> | 135:176b8275d35d | 1078 | */ |
<> | 135:176b8275d35d | 1079 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
<> | 135:176b8275d35d | 1080 | { |
<> | 135:176b8275d35d | 1081 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
<> | 135:176b8275d35d | 1082 | } |
<> | 135:176b8275d35d | 1083 | |
<> | 135:176b8275d35d | 1084 | /** |
<> | 135:176b8275d35d | 1085 | * @brief Check if HSE oscillator Ready |
<> | 135:176b8275d35d | 1086 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
<> | 135:176b8275d35d | 1087 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1088 | */ |
<> | 135:176b8275d35d | 1089 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
<> | 135:176b8275d35d | 1090 | { |
<> | 135:176b8275d35d | 1091 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
<> | 135:176b8275d35d | 1092 | } |
<> | 135:176b8275d35d | 1093 | |
<> | 135:176b8275d35d | 1094 | /** |
<> | 135:176b8275d35d | 1095 | * @} |
<> | 135:176b8275d35d | 1096 | */ |
<> | 135:176b8275d35d | 1097 | |
<> | 135:176b8275d35d | 1098 | /** @defgroup RCC_LL_EF_HSI HSI |
<> | 135:176b8275d35d | 1099 | * @{ |
<> | 135:176b8275d35d | 1100 | */ |
<> | 135:176b8275d35d | 1101 | |
<> | 135:176b8275d35d | 1102 | /** |
<> | 135:176b8275d35d | 1103 | * @brief Enable HSI oscillator |
<> | 135:176b8275d35d | 1104 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
<> | 135:176b8275d35d | 1105 | * @retval None |
<> | 135:176b8275d35d | 1106 | */ |
<> | 135:176b8275d35d | 1107 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
<> | 135:176b8275d35d | 1108 | { |
<> | 135:176b8275d35d | 1109 | SET_BIT(RCC->CR, RCC_CR_HSION); |
<> | 135:176b8275d35d | 1110 | } |
<> | 135:176b8275d35d | 1111 | |
<> | 135:176b8275d35d | 1112 | /** |
<> | 135:176b8275d35d | 1113 | * @brief Disable HSI oscillator |
<> | 135:176b8275d35d | 1114 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
<> | 135:176b8275d35d | 1115 | * @retval None |
<> | 135:176b8275d35d | 1116 | */ |
<> | 135:176b8275d35d | 1117 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
<> | 135:176b8275d35d | 1118 | { |
<> | 135:176b8275d35d | 1119 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
<> | 135:176b8275d35d | 1120 | } |
<> | 135:176b8275d35d | 1121 | |
<> | 135:176b8275d35d | 1122 | /** |
<> | 135:176b8275d35d | 1123 | * @brief Check if HSI clock is ready |
<> | 135:176b8275d35d | 1124 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
<> | 135:176b8275d35d | 1125 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1126 | */ |
<> | 135:176b8275d35d | 1127 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
<> | 135:176b8275d35d | 1128 | { |
<> | 135:176b8275d35d | 1129 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
<> | 135:176b8275d35d | 1130 | } |
<> | 135:176b8275d35d | 1131 | |
<> | 135:176b8275d35d | 1132 | /** |
<> | 135:176b8275d35d | 1133 | * @brief Get HSI Calibration value |
<> | 135:176b8275d35d | 1134 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
<> | 135:176b8275d35d | 1135 | * HSITRIM and the factory trim value |
<> | 135:176b8275d35d | 1136 | * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration |
<> | 135:176b8275d35d | 1137 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
<> | 135:176b8275d35d | 1138 | */ |
<> | 135:176b8275d35d | 1139 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
<> | 135:176b8275d35d | 1140 | { |
<> | 135:176b8275d35d | 1141 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL); |
<> | 135:176b8275d35d | 1142 | } |
<> | 135:176b8275d35d | 1143 | |
<> | 135:176b8275d35d | 1144 | /** |
<> | 135:176b8275d35d | 1145 | * @brief Set HSI Calibration trimming |
<> | 135:176b8275d35d | 1146 | * @note user-programmable trimming value that is added to the HSICAL |
<> | 135:176b8275d35d | 1147 | * @note Default value is 16, which, when added to the HSICAL value, |
<> | 135:176b8275d35d | 1148 | * should trim the HSI to 16 MHz +/- 1 % |
<> | 135:176b8275d35d | 1149 | * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming |
<> | 135:176b8275d35d | 1150 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
<> | 135:176b8275d35d | 1151 | * @retval None |
<> | 135:176b8275d35d | 1152 | */ |
<> | 135:176b8275d35d | 1153 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
<> | 135:176b8275d35d | 1154 | { |
<> | 135:176b8275d35d | 1155 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM); |
<> | 135:176b8275d35d | 1156 | } |
<> | 135:176b8275d35d | 1157 | |
<> | 135:176b8275d35d | 1158 | /** |
<> | 135:176b8275d35d | 1159 | * @brief Get HSI Calibration trimming |
<> | 135:176b8275d35d | 1160 | * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming |
<> | 135:176b8275d35d | 1161 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
<> | 135:176b8275d35d | 1162 | */ |
<> | 135:176b8275d35d | 1163 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
<> | 135:176b8275d35d | 1164 | { |
<> | 135:176b8275d35d | 1165 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM); |
<> | 135:176b8275d35d | 1166 | } |
<> | 135:176b8275d35d | 1167 | |
<> | 135:176b8275d35d | 1168 | /** |
<> | 135:176b8275d35d | 1169 | * @} |
<> | 135:176b8275d35d | 1170 | */ |
<> | 135:176b8275d35d | 1171 | |
<> | 135:176b8275d35d | 1172 | /** @defgroup RCC_LL_EF_LSE LSE |
<> | 135:176b8275d35d | 1173 | * @{ |
<> | 135:176b8275d35d | 1174 | */ |
<> | 135:176b8275d35d | 1175 | |
<> | 135:176b8275d35d | 1176 | /** |
<> | 135:176b8275d35d | 1177 | * @brief Enable Low Speed External (LSE) crystal. |
<> | 135:176b8275d35d | 1178 | * @rmtoll BDCR LSEON LL_RCC_LSE_Enable |
<> | 135:176b8275d35d | 1179 | * @retval None |
<> | 135:176b8275d35d | 1180 | */ |
<> | 135:176b8275d35d | 1181 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
<> | 135:176b8275d35d | 1182 | { |
<> | 135:176b8275d35d | 1183 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
<> | 135:176b8275d35d | 1184 | } |
<> | 135:176b8275d35d | 1185 | |
<> | 135:176b8275d35d | 1186 | /** |
<> | 135:176b8275d35d | 1187 | * @brief Disable Low Speed External (LSE) crystal. |
<> | 135:176b8275d35d | 1188 | * @rmtoll BDCR LSEON LL_RCC_LSE_Disable |
<> | 135:176b8275d35d | 1189 | * @retval None |
<> | 135:176b8275d35d | 1190 | */ |
<> | 135:176b8275d35d | 1191 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
<> | 135:176b8275d35d | 1192 | { |
<> | 135:176b8275d35d | 1193 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
<> | 135:176b8275d35d | 1194 | } |
<> | 135:176b8275d35d | 1195 | |
<> | 135:176b8275d35d | 1196 | /** |
<> | 135:176b8275d35d | 1197 | * @brief Enable external clock source (LSE bypass). |
<> | 135:176b8275d35d | 1198 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass |
<> | 135:176b8275d35d | 1199 | * @retval None |
<> | 135:176b8275d35d | 1200 | */ |
<> | 135:176b8275d35d | 1201 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
<> | 135:176b8275d35d | 1202 | { |
<> | 135:176b8275d35d | 1203 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
<> | 135:176b8275d35d | 1204 | } |
<> | 135:176b8275d35d | 1205 | |
<> | 135:176b8275d35d | 1206 | /** |
<> | 135:176b8275d35d | 1207 | * @brief Disable external clock source (LSE bypass). |
<> | 135:176b8275d35d | 1208 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass |
<> | 135:176b8275d35d | 1209 | * @retval None |
<> | 135:176b8275d35d | 1210 | */ |
<> | 135:176b8275d35d | 1211 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
<> | 135:176b8275d35d | 1212 | { |
<> | 135:176b8275d35d | 1213 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
<> | 135:176b8275d35d | 1214 | } |
<> | 135:176b8275d35d | 1215 | |
<> | 135:176b8275d35d | 1216 | /** |
<> | 135:176b8275d35d | 1217 | * @brief Set LSE oscillator drive capability |
<> | 135:176b8275d35d | 1218 | * @note The oscillator is in Xtal mode when it is not in bypass mode. |
<> | 135:176b8275d35d | 1219 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability |
<> | 135:176b8275d35d | 1220 | * @param LSEDrive This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1221 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
<> | 135:176b8275d35d | 1222 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
<> | 135:176b8275d35d | 1223 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
<> | 135:176b8275d35d | 1224 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
<> | 135:176b8275d35d | 1225 | * @retval None |
<> | 135:176b8275d35d | 1226 | */ |
<> | 135:176b8275d35d | 1227 | __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) |
<> | 135:176b8275d35d | 1228 | { |
<> | 135:176b8275d35d | 1229 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); |
<> | 135:176b8275d35d | 1230 | } |
<> | 135:176b8275d35d | 1231 | |
<> | 135:176b8275d35d | 1232 | /** |
<> | 135:176b8275d35d | 1233 | * @brief Get LSE oscillator drive capability |
<> | 135:176b8275d35d | 1234 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability |
<> | 135:176b8275d35d | 1235 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1236 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
<> | 135:176b8275d35d | 1237 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
<> | 135:176b8275d35d | 1238 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
<> | 135:176b8275d35d | 1239 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
<> | 135:176b8275d35d | 1240 | */ |
<> | 135:176b8275d35d | 1241 | __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) |
<> | 135:176b8275d35d | 1242 | { |
<> | 135:176b8275d35d | 1243 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); |
<> | 135:176b8275d35d | 1244 | } |
<> | 135:176b8275d35d | 1245 | |
<> | 135:176b8275d35d | 1246 | /** |
<> | 135:176b8275d35d | 1247 | * @brief Check if LSE oscillator Ready |
<> | 135:176b8275d35d | 1248 | * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady |
<> | 135:176b8275d35d | 1249 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1250 | */ |
<> | 135:176b8275d35d | 1251 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
<> | 135:176b8275d35d | 1252 | { |
<> | 135:176b8275d35d | 1253 | return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); |
<> | 135:176b8275d35d | 1254 | } |
<> | 135:176b8275d35d | 1255 | |
<> | 135:176b8275d35d | 1256 | /** |
<> | 135:176b8275d35d | 1257 | * @} |
<> | 135:176b8275d35d | 1258 | */ |
<> | 135:176b8275d35d | 1259 | |
<> | 135:176b8275d35d | 1260 | /** @defgroup RCC_LL_EF_LSI LSI |
<> | 135:176b8275d35d | 1261 | * @{ |
<> | 135:176b8275d35d | 1262 | */ |
<> | 135:176b8275d35d | 1263 | |
<> | 135:176b8275d35d | 1264 | /** |
<> | 135:176b8275d35d | 1265 | * @brief Enable LSI Oscillator |
<> | 135:176b8275d35d | 1266 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
<> | 135:176b8275d35d | 1267 | * @retval None |
<> | 135:176b8275d35d | 1268 | */ |
<> | 135:176b8275d35d | 1269 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
<> | 135:176b8275d35d | 1270 | { |
<> | 135:176b8275d35d | 1271 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
<> | 135:176b8275d35d | 1272 | } |
<> | 135:176b8275d35d | 1273 | |
<> | 135:176b8275d35d | 1274 | /** |
<> | 135:176b8275d35d | 1275 | * @brief Disable LSI Oscillator |
<> | 135:176b8275d35d | 1276 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
<> | 135:176b8275d35d | 1277 | * @retval None |
<> | 135:176b8275d35d | 1278 | */ |
<> | 135:176b8275d35d | 1279 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
<> | 135:176b8275d35d | 1280 | { |
<> | 135:176b8275d35d | 1281 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
<> | 135:176b8275d35d | 1282 | } |
<> | 135:176b8275d35d | 1283 | |
<> | 135:176b8275d35d | 1284 | /** |
<> | 135:176b8275d35d | 1285 | * @brief Check if LSI is Ready |
<> | 135:176b8275d35d | 1286 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
<> | 135:176b8275d35d | 1287 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1288 | */ |
<> | 135:176b8275d35d | 1289 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
<> | 135:176b8275d35d | 1290 | { |
<> | 135:176b8275d35d | 1291 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
<> | 135:176b8275d35d | 1292 | } |
<> | 135:176b8275d35d | 1293 | |
<> | 135:176b8275d35d | 1294 | /** |
<> | 135:176b8275d35d | 1295 | * @} |
<> | 135:176b8275d35d | 1296 | */ |
<> | 135:176b8275d35d | 1297 | |
<> | 135:176b8275d35d | 1298 | /** @defgroup RCC_LL_EF_System System |
<> | 135:176b8275d35d | 1299 | * @{ |
<> | 135:176b8275d35d | 1300 | */ |
<> | 135:176b8275d35d | 1301 | |
<> | 135:176b8275d35d | 1302 | /** |
<> | 135:176b8275d35d | 1303 | * @brief Configure the system clock source |
<> | 135:176b8275d35d | 1304 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
<> | 135:176b8275d35d | 1305 | * @param Source This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1306 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1307 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
<> | 135:176b8275d35d | 1308 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1309 | * @retval None |
<> | 135:176b8275d35d | 1310 | */ |
<> | 135:176b8275d35d | 1311 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
<> | 135:176b8275d35d | 1312 | { |
<> | 135:176b8275d35d | 1313 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
<> | 135:176b8275d35d | 1314 | } |
<> | 135:176b8275d35d | 1315 | |
<> | 135:176b8275d35d | 1316 | /** |
<> | 135:176b8275d35d | 1317 | * @brief Get the system clock source |
<> | 135:176b8275d35d | 1318 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
<> | 135:176b8275d35d | 1319 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1320 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
<> | 135:176b8275d35d | 1321 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
<> | 135:176b8275d35d | 1322 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
<> | 135:176b8275d35d | 1323 | */ |
<> | 135:176b8275d35d | 1324 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
<> | 135:176b8275d35d | 1325 | { |
<> | 135:176b8275d35d | 1326 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
<> | 135:176b8275d35d | 1327 | } |
<> | 135:176b8275d35d | 1328 | |
<> | 135:176b8275d35d | 1329 | /** |
<> | 135:176b8275d35d | 1330 | * @brief Set AHB prescaler |
<> | 135:176b8275d35d | 1331 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
<> | 135:176b8275d35d | 1332 | * @param Prescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1333 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 135:176b8275d35d | 1334 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 135:176b8275d35d | 1335 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 135:176b8275d35d | 1336 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 135:176b8275d35d | 1337 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 135:176b8275d35d | 1338 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 135:176b8275d35d | 1339 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 135:176b8275d35d | 1340 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 135:176b8275d35d | 1341 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 135:176b8275d35d | 1342 | * @retval None |
<> | 135:176b8275d35d | 1343 | */ |
<> | 135:176b8275d35d | 1344 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
<> | 135:176b8275d35d | 1345 | { |
<> | 135:176b8275d35d | 1346 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
<> | 135:176b8275d35d | 1347 | } |
<> | 135:176b8275d35d | 1348 | |
<> | 135:176b8275d35d | 1349 | /** |
<> | 135:176b8275d35d | 1350 | * @brief Set APB1 prescaler |
<> | 135:176b8275d35d | 1351 | * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
<> | 135:176b8275d35d | 1352 | * @param Prescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1353 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 135:176b8275d35d | 1354 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 135:176b8275d35d | 1355 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 135:176b8275d35d | 1356 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 135:176b8275d35d | 1357 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 135:176b8275d35d | 1358 | * @retval None |
<> | 135:176b8275d35d | 1359 | */ |
<> | 135:176b8275d35d | 1360 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
<> | 135:176b8275d35d | 1361 | { |
<> | 135:176b8275d35d | 1362 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
<> | 135:176b8275d35d | 1363 | } |
<> | 135:176b8275d35d | 1364 | |
<> | 135:176b8275d35d | 1365 | /** |
<> | 135:176b8275d35d | 1366 | * @brief Set APB2 prescaler |
<> | 135:176b8275d35d | 1367 | * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
<> | 135:176b8275d35d | 1368 | * @param Prescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1369 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 135:176b8275d35d | 1370 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 135:176b8275d35d | 1371 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 135:176b8275d35d | 1372 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 135:176b8275d35d | 1373 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 135:176b8275d35d | 1374 | * @retval None |
<> | 135:176b8275d35d | 1375 | */ |
<> | 135:176b8275d35d | 1376 | __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
<> | 135:176b8275d35d | 1377 | { |
<> | 135:176b8275d35d | 1378 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
<> | 135:176b8275d35d | 1379 | } |
<> | 135:176b8275d35d | 1380 | |
<> | 135:176b8275d35d | 1381 | /** |
<> | 135:176b8275d35d | 1382 | * @brief Get AHB prescaler |
<> | 135:176b8275d35d | 1383 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
<> | 135:176b8275d35d | 1384 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1385 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 135:176b8275d35d | 1386 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 135:176b8275d35d | 1387 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 135:176b8275d35d | 1388 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 135:176b8275d35d | 1389 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 135:176b8275d35d | 1390 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 135:176b8275d35d | 1391 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 135:176b8275d35d | 1392 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 135:176b8275d35d | 1393 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 135:176b8275d35d | 1394 | */ |
<> | 135:176b8275d35d | 1395 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
<> | 135:176b8275d35d | 1396 | { |
<> | 135:176b8275d35d | 1397 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
<> | 135:176b8275d35d | 1398 | } |
<> | 135:176b8275d35d | 1399 | |
<> | 135:176b8275d35d | 1400 | /** |
<> | 135:176b8275d35d | 1401 | * @brief Get APB1 prescaler |
<> | 135:176b8275d35d | 1402 | * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
<> | 135:176b8275d35d | 1403 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1404 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 135:176b8275d35d | 1405 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 135:176b8275d35d | 1406 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 135:176b8275d35d | 1407 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 135:176b8275d35d | 1408 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 135:176b8275d35d | 1409 | */ |
<> | 135:176b8275d35d | 1410 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
<> | 135:176b8275d35d | 1411 | { |
<> | 135:176b8275d35d | 1412 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
<> | 135:176b8275d35d | 1413 | } |
<> | 135:176b8275d35d | 1414 | |
<> | 135:176b8275d35d | 1415 | /** |
<> | 135:176b8275d35d | 1416 | * @brief Get APB2 prescaler |
<> | 135:176b8275d35d | 1417 | * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
<> | 135:176b8275d35d | 1418 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1419 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 135:176b8275d35d | 1420 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 135:176b8275d35d | 1421 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 135:176b8275d35d | 1422 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 135:176b8275d35d | 1423 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 135:176b8275d35d | 1424 | */ |
<> | 135:176b8275d35d | 1425 | __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
<> | 135:176b8275d35d | 1426 | { |
<> | 135:176b8275d35d | 1427 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
<> | 135:176b8275d35d | 1428 | } |
<> | 135:176b8275d35d | 1429 | |
<> | 135:176b8275d35d | 1430 | /** |
<> | 135:176b8275d35d | 1431 | * @} |
<> | 135:176b8275d35d | 1432 | */ |
<> | 135:176b8275d35d | 1433 | |
<> | 135:176b8275d35d | 1434 | /** @defgroup RCC_LL_EF_MCO MCO |
<> | 135:176b8275d35d | 1435 | * @{ |
<> | 135:176b8275d35d | 1436 | */ |
<> | 135:176b8275d35d | 1437 | |
<> | 135:176b8275d35d | 1438 | /** |
<> | 135:176b8275d35d | 1439 | * @brief Configure MCOx |
<> | 135:176b8275d35d | 1440 | * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n |
<> | 135:176b8275d35d | 1441 | * CFGR MCOPRE LL_RCC_ConfigMCO\n |
<> | 135:176b8275d35d | 1442 | * CFGR PLLNODIV LL_RCC_ConfigMCO |
<> | 135:176b8275d35d | 1443 | * @param MCOxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1444 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
<> | 135:176b8275d35d | 1445 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
<> | 135:176b8275d35d | 1446 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
<> | 135:176b8275d35d | 1447 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
<> | 135:176b8275d35d | 1448 | * @arg @ref LL_RCC_MCO1SOURCE_LSI |
<> | 135:176b8275d35d | 1449 | * @arg @ref LL_RCC_MCO1SOURCE_LSE |
<> | 135:176b8275d35d | 1450 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) |
<> | 135:176b8275d35d | 1451 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 |
<> | 135:176b8275d35d | 1452 | * |
<> | 135:176b8275d35d | 1453 | * (*) value not defined in all devices |
<> | 135:176b8275d35d | 1454 | * @param MCOxPrescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1455 | * @arg @ref LL_RCC_MCO1_DIV_1 |
<> | 135:176b8275d35d | 1456 | * @arg @ref LL_RCC_MCO1_DIV_2 (*) |
<> | 135:176b8275d35d | 1457 | * @arg @ref LL_RCC_MCO1_DIV_4 (*) |
<> | 135:176b8275d35d | 1458 | * @arg @ref LL_RCC_MCO1_DIV_8 (*) |
<> | 135:176b8275d35d | 1459 | * @arg @ref LL_RCC_MCO1_DIV_16 (*) |
<> | 135:176b8275d35d | 1460 | * @arg @ref LL_RCC_MCO1_DIV_32 (*) |
<> | 135:176b8275d35d | 1461 | * @arg @ref LL_RCC_MCO1_DIV_64 (*) |
<> | 135:176b8275d35d | 1462 | * @arg @ref LL_RCC_MCO1_DIV_128 (*) |
<> | 135:176b8275d35d | 1463 | * |
<> | 135:176b8275d35d | 1464 | * (*) value not defined in all devices |
<> | 135:176b8275d35d | 1465 | * @retval None |
<> | 135:176b8275d35d | 1466 | */ |
<> | 135:176b8275d35d | 1467 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
<> | 135:176b8275d35d | 1468 | { |
<> | 135:176b8275d35d | 1469 | #if defined(RCC_CFGR_MCOPRE) |
<> | 135:176b8275d35d | 1470 | #if defined(RCC_CFGR_PLLNODIV) |
<> | 135:176b8275d35d | 1471 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); |
<> | 135:176b8275d35d | 1472 | #else |
<> | 135:176b8275d35d | 1473 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); |
<> | 135:176b8275d35d | 1474 | #endif /* RCC_CFGR_PLLNODIV */ |
<> | 135:176b8275d35d | 1475 | #else |
<> | 135:176b8275d35d | 1476 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); |
<> | 135:176b8275d35d | 1477 | #endif /* RCC_CFGR_MCOPRE */ |
<> | 135:176b8275d35d | 1478 | } |
<> | 135:176b8275d35d | 1479 | |
<> | 135:176b8275d35d | 1480 | /** |
<> | 135:176b8275d35d | 1481 | * @} |
<> | 135:176b8275d35d | 1482 | */ |
<> | 135:176b8275d35d | 1483 | |
<> | 135:176b8275d35d | 1484 | /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
<> | 135:176b8275d35d | 1485 | * @{ |
<> | 135:176b8275d35d | 1486 | */ |
<> | 135:176b8275d35d | 1487 | |
<> | 135:176b8275d35d | 1488 | /** |
<> | 135:176b8275d35d | 1489 | * @brief Configure USARTx clock source |
<> | 135:176b8275d35d | 1490 | * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n |
<> | 135:176b8275d35d | 1491 | * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n |
<> | 135:176b8275d35d | 1492 | * CFGR3 USART3SW LL_RCC_SetUSARTClockSource |
<> | 135:176b8275d35d | 1493 | * @param USARTxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1494 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1495 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1496 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1497 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1498 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1499 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1500 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1501 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
<> | 135:176b8275d35d | 1502 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1503 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1504 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1505 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
<> | 135:176b8275d35d | 1506 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1507 | * |
<> | 135:176b8275d35d | 1508 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1509 | * @retval None |
<> | 135:176b8275d35d | 1510 | */ |
<> | 135:176b8275d35d | 1511 | __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) |
<> | 135:176b8275d35d | 1512 | { |
<> | 135:176b8275d35d | 1513 | MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); |
<> | 135:176b8275d35d | 1514 | } |
<> | 135:176b8275d35d | 1515 | |
<> | 135:176b8275d35d | 1516 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
<> | 135:176b8275d35d | 1517 | /** |
<> | 135:176b8275d35d | 1518 | * @brief Configure UARTx clock source |
<> | 135:176b8275d35d | 1519 | * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n |
<> | 135:176b8275d35d | 1520 | * CFGR3 UART5SW LL_RCC_SetUARTClockSource |
<> | 135:176b8275d35d | 1521 | * @param UARTxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1522 | * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 |
<> | 135:176b8275d35d | 1523 | * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1524 | * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1525 | * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1526 | * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 |
<> | 135:176b8275d35d | 1527 | * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1528 | * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1529 | * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1530 | * @retval None |
<> | 135:176b8275d35d | 1531 | */ |
<> | 135:176b8275d35d | 1532 | __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) |
<> | 135:176b8275d35d | 1533 | { |
<> | 135:176b8275d35d | 1534 | MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW))); |
<> | 135:176b8275d35d | 1535 | } |
<> | 135:176b8275d35d | 1536 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
<> | 135:176b8275d35d | 1537 | |
<> | 135:176b8275d35d | 1538 | /** |
<> | 135:176b8275d35d | 1539 | * @brief Configure I2Cx clock source |
<> | 135:176b8275d35d | 1540 | * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n |
<> | 135:176b8275d35d | 1541 | * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n |
<> | 135:176b8275d35d | 1542 | * CFGR3 I2C3SW LL_RCC_SetI2CClockSource |
<> | 135:176b8275d35d | 1543 | * @param I2CxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1544 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1545 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1546 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1547 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1548 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1549 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1550 | * |
<> | 135:176b8275d35d | 1551 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1552 | * @retval None |
<> | 135:176b8275d35d | 1553 | */ |
<> | 135:176b8275d35d | 1554 | __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) |
<> | 135:176b8275d35d | 1555 | { |
<> | 135:176b8275d35d | 1556 | MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU)); |
<> | 135:176b8275d35d | 1557 | } |
<> | 135:176b8275d35d | 1558 | |
<> | 135:176b8275d35d | 1559 | #if defined(RCC_CFGR_I2SSRC) |
<> | 135:176b8275d35d | 1560 | /** |
<> | 135:176b8275d35d | 1561 | * @brief Configure I2Sx clock source |
<> | 135:176b8275d35d | 1562 | * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource |
<> | 135:176b8275d35d | 1563 | * @param I2SxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1564 | * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1565 | * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN |
<> | 135:176b8275d35d | 1566 | * @retval None |
<> | 135:176b8275d35d | 1567 | */ |
<> | 135:176b8275d35d | 1568 | __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) |
<> | 135:176b8275d35d | 1569 | { |
<> | 135:176b8275d35d | 1570 | MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource); |
<> | 135:176b8275d35d | 1571 | } |
<> | 135:176b8275d35d | 1572 | #endif /* RCC_CFGR_I2SSRC */ |
<> | 135:176b8275d35d | 1573 | |
<> | 135:176b8275d35d | 1574 | #if defined(RCC_CFGR3_TIMSW) |
<> | 135:176b8275d35d | 1575 | /** |
<> | 135:176b8275d35d | 1576 | * @brief Configure TIMx clock source |
<> | 135:176b8275d35d | 1577 | * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1578 | * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1579 | * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1580 | * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1581 | * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1582 | * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1583 | * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n |
<> | 135:176b8275d35d | 1584 | * CFGR3 TIM34SW LL_RCC_SetTIMClockSource |
<> | 135:176b8275d35d | 1585 | * @param TIMxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1586 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 |
<> | 135:176b8275d35d | 1587 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1588 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1589 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1590 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1591 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1592 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1593 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1594 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1595 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1596 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1597 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1598 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1599 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1600 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1601 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1602 | * |
<> | 135:176b8275d35d | 1603 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1604 | * @retval None |
<> | 135:176b8275d35d | 1605 | */ |
<> | 135:176b8275d35d | 1606 | __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) |
<> | 135:176b8275d35d | 1607 | { |
<> | 135:176b8275d35d | 1608 | MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU)); |
<> | 135:176b8275d35d | 1609 | } |
<> | 135:176b8275d35d | 1610 | #endif /* RCC_CFGR3_TIMSW */ |
<> | 135:176b8275d35d | 1611 | |
<> | 135:176b8275d35d | 1612 | #if defined(HRTIM1) |
<> | 135:176b8275d35d | 1613 | /** |
<> | 135:176b8275d35d | 1614 | * @brief Configure HRTIMx clock source |
<> | 135:176b8275d35d | 1615 | * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource |
<> | 135:176b8275d35d | 1616 | * @param HRTIMxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1617 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 |
<> | 135:176b8275d35d | 1618 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1619 | * @retval None |
<> | 135:176b8275d35d | 1620 | */ |
<> | 135:176b8275d35d | 1621 | __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource) |
<> | 135:176b8275d35d | 1622 | { |
<> | 135:176b8275d35d | 1623 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource); |
<> | 135:176b8275d35d | 1624 | } |
<> | 135:176b8275d35d | 1625 | #endif /* HRTIM1 */ |
<> | 135:176b8275d35d | 1626 | |
<> | 135:176b8275d35d | 1627 | #if defined(CEC) |
<> | 135:176b8275d35d | 1628 | /** |
<> | 135:176b8275d35d | 1629 | * @brief Configure CEC clock source |
<> | 135:176b8275d35d | 1630 | * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource |
<> | 135:176b8275d35d | 1631 | * @param CECxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1632 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
<> | 135:176b8275d35d | 1633 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1634 | * @retval None |
<> | 135:176b8275d35d | 1635 | */ |
<> | 135:176b8275d35d | 1636 | __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) |
<> | 135:176b8275d35d | 1637 | { |
<> | 135:176b8275d35d | 1638 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); |
<> | 135:176b8275d35d | 1639 | } |
<> | 135:176b8275d35d | 1640 | #endif /* CEC */ |
<> | 135:176b8275d35d | 1641 | |
<> | 135:176b8275d35d | 1642 | #if defined(USB) |
<> | 135:176b8275d35d | 1643 | /** |
<> | 135:176b8275d35d | 1644 | * @brief Configure USB clock source |
<> | 135:176b8275d35d | 1645 | * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource |
<> | 135:176b8275d35d | 1646 | * @param USBxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1647 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1648 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 |
<> | 135:176b8275d35d | 1649 | * @retval None |
<> | 135:176b8275d35d | 1650 | */ |
<> | 135:176b8275d35d | 1651 | __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) |
<> | 135:176b8275d35d | 1652 | { |
<> | 135:176b8275d35d | 1653 | MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); |
<> | 135:176b8275d35d | 1654 | } |
<> | 135:176b8275d35d | 1655 | #endif /* USB */ |
<> | 135:176b8275d35d | 1656 | |
<> | 135:176b8275d35d | 1657 | #if defined(RCC_CFGR_ADCPRE) |
<> | 135:176b8275d35d | 1658 | /** |
<> | 135:176b8275d35d | 1659 | * @brief Configure ADC clock source |
<> | 135:176b8275d35d | 1660 | * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource |
<> | 135:176b8275d35d | 1661 | * @param ADCxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1662 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
<> | 135:176b8275d35d | 1663 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
<> | 135:176b8275d35d | 1664 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
<> | 135:176b8275d35d | 1665 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
<> | 135:176b8275d35d | 1666 | * @retval None |
<> | 135:176b8275d35d | 1667 | */ |
<> | 135:176b8275d35d | 1668 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
<> | 135:176b8275d35d | 1669 | { |
<> | 135:176b8275d35d | 1670 | MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); |
<> | 135:176b8275d35d | 1671 | } |
<> | 135:176b8275d35d | 1672 | |
<> | 135:176b8275d35d | 1673 | #elif defined(RCC_CFGR2_ADC1PRES) |
<> | 135:176b8275d35d | 1674 | /** |
<> | 135:176b8275d35d | 1675 | * @brief Configure ADC clock source |
<> | 135:176b8275d35d | 1676 | * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource |
<> | 135:176b8275d35d | 1677 | * @param ADCxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1678 | * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK |
<> | 135:176b8275d35d | 1679 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 |
<> | 135:176b8275d35d | 1680 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 |
<> | 135:176b8275d35d | 1681 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 |
<> | 135:176b8275d35d | 1682 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 |
<> | 135:176b8275d35d | 1683 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 |
<> | 135:176b8275d35d | 1684 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 |
<> | 135:176b8275d35d | 1685 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 |
<> | 135:176b8275d35d | 1686 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 |
<> | 135:176b8275d35d | 1687 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 |
<> | 135:176b8275d35d | 1688 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 |
<> | 135:176b8275d35d | 1689 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 |
<> | 135:176b8275d35d | 1690 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 |
<> | 135:176b8275d35d | 1691 | * @retval None |
<> | 135:176b8275d35d | 1692 | */ |
<> | 135:176b8275d35d | 1693 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
<> | 135:176b8275d35d | 1694 | { |
<> | 135:176b8275d35d | 1695 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); |
<> | 135:176b8275d35d | 1696 | } |
<> | 135:176b8275d35d | 1697 | |
<> | 135:176b8275d35d | 1698 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 1699 | /** |
<> | 135:176b8275d35d | 1700 | * @brief Configure ADC clock source |
<> | 135:176b8275d35d | 1701 | * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n |
<> | 135:176b8275d35d | 1702 | * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource |
<> | 135:176b8275d35d | 1703 | * @param ADCxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1704 | * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK |
<> | 135:176b8275d35d | 1705 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 |
<> | 135:176b8275d35d | 1706 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 |
<> | 135:176b8275d35d | 1707 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 |
<> | 135:176b8275d35d | 1708 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 |
<> | 135:176b8275d35d | 1709 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 |
<> | 135:176b8275d35d | 1710 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 |
<> | 135:176b8275d35d | 1711 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 |
<> | 135:176b8275d35d | 1712 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 |
<> | 135:176b8275d35d | 1713 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 |
<> | 135:176b8275d35d | 1714 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 |
<> | 135:176b8275d35d | 1715 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 |
<> | 135:176b8275d35d | 1716 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 |
<> | 135:176b8275d35d | 1717 | * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) |
<> | 135:176b8275d35d | 1718 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) |
<> | 135:176b8275d35d | 1719 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) |
<> | 135:176b8275d35d | 1720 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) |
<> | 135:176b8275d35d | 1721 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) |
<> | 135:176b8275d35d | 1722 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) |
<> | 135:176b8275d35d | 1723 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) |
<> | 135:176b8275d35d | 1724 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) |
<> | 135:176b8275d35d | 1725 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) |
<> | 135:176b8275d35d | 1726 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) |
<> | 135:176b8275d35d | 1727 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) |
<> | 135:176b8275d35d | 1728 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) |
<> | 135:176b8275d35d | 1729 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) |
<> | 135:176b8275d35d | 1730 | * |
<> | 135:176b8275d35d | 1731 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1732 | * @retval None |
<> | 135:176b8275d35d | 1733 | */ |
<> | 135:176b8275d35d | 1734 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
<> | 135:176b8275d35d | 1735 | { |
<> | 135:176b8275d35d | 1736 | #if defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 1737 | MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); |
<> | 135:176b8275d35d | 1738 | #else |
<> | 135:176b8275d35d | 1739 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); |
<> | 135:176b8275d35d | 1740 | #endif /* RCC_CFGR2_ADCPRE34 */ |
<> | 135:176b8275d35d | 1741 | } |
<> | 135:176b8275d35d | 1742 | #endif /* RCC_CFGR_ADCPRE */ |
<> | 135:176b8275d35d | 1743 | |
<> | 135:176b8275d35d | 1744 | #if defined(RCC_CFGR_SDPRE) |
<> | 135:176b8275d35d | 1745 | /** |
<> | 135:176b8275d35d | 1746 | * @brief Configure SDADCx clock source |
<> | 135:176b8275d35d | 1747 | * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource |
<> | 135:176b8275d35d | 1748 | * @param SDADCxSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1749 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 |
<> | 135:176b8275d35d | 1750 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 |
<> | 135:176b8275d35d | 1751 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 |
<> | 135:176b8275d35d | 1752 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 |
<> | 135:176b8275d35d | 1753 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 |
<> | 135:176b8275d35d | 1754 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 |
<> | 135:176b8275d35d | 1755 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 |
<> | 135:176b8275d35d | 1756 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 |
<> | 135:176b8275d35d | 1757 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 |
<> | 135:176b8275d35d | 1758 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 |
<> | 135:176b8275d35d | 1759 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 |
<> | 135:176b8275d35d | 1760 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 |
<> | 135:176b8275d35d | 1761 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 |
<> | 135:176b8275d35d | 1762 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 |
<> | 135:176b8275d35d | 1763 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 |
<> | 135:176b8275d35d | 1764 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 |
<> | 135:176b8275d35d | 1765 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 |
<> | 135:176b8275d35d | 1766 | * @retval None |
<> | 135:176b8275d35d | 1767 | */ |
<> | 135:176b8275d35d | 1768 | __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource) |
<> | 135:176b8275d35d | 1769 | { |
<> | 135:176b8275d35d | 1770 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource); |
<> | 135:176b8275d35d | 1771 | } |
<> | 135:176b8275d35d | 1772 | #endif /* RCC_CFGR_SDPRE */ |
<> | 135:176b8275d35d | 1773 | |
<> | 135:176b8275d35d | 1774 | /** |
<> | 135:176b8275d35d | 1775 | * @brief Get USARTx clock source |
<> | 135:176b8275d35d | 1776 | * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n |
<> | 135:176b8275d35d | 1777 | * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n |
<> | 135:176b8275d35d | 1778 | * CFGR3 USART3SW LL_RCC_GetUSARTClockSource |
<> | 135:176b8275d35d | 1779 | * @param USARTx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1780 | * @arg @ref LL_RCC_USART1_CLKSOURCE |
<> | 135:176b8275d35d | 1781 | * @arg @ref LL_RCC_USART2_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1782 | * @arg @ref LL_RCC_USART3_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1783 | * |
<> | 135:176b8275d35d | 1784 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1785 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1786 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1787 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1788 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1789 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1790 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1791 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1792 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1793 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
<> | 135:176b8275d35d | 1794 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1795 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1796 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1797 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
<> | 135:176b8275d35d | 1798 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1799 | * |
<> | 135:176b8275d35d | 1800 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1801 | */ |
<> | 135:176b8275d35d | 1802 | __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) |
<> | 135:176b8275d35d | 1803 | { |
<> | 135:176b8275d35d | 1804 | return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); |
<> | 135:176b8275d35d | 1805 | } |
<> | 135:176b8275d35d | 1806 | |
<> | 135:176b8275d35d | 1807 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
<> | 135:176b8275d35d | 1808 | /** |
<> | 135:176b8275d35d | 1809 | * @brief Get UARTx clock source |
<> | 135:176b8275d35d | 1810 | * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n |
<> | 135:176b8275d35d | 1811 | * CFGR3 UART5SW LL_RCC_GetUARTClockSource |
<> | 135:176b8275d35d | 1812 | * @param UARTx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1813 | * @arg @ref LL_RCC_UART4_CLKSOURCE |
<> | 135:176b8275d35d | 1814 | * @arg @ref LL_RCC_UART5_CLKSOURCE |
<> | 135:176b8275d35d | 1815 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1816 | * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 |
<> | 135:176b8275d35d | 1817 | * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1818 | * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1819 | * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1820 | * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 |
<> | 135:176b8275d35d | 1821 | * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1822 | * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1823 | * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1824 | */ |
<> | 135:176b8275d35d | 1825 | __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) |
<> | 135:176b8275d35d | 1826 | { |
<> | 135:176b8275d35d | 1827 | return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U)); |
<> | 135:176b8275d35d | 1828 | } |
<> | 135:176b8275d35d | 1829 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
<> | 135:176b8275d35d | 1830 | |
<> | 135:176b8275d35d | 1831 | /** |
<> | 135:176b8275d35d | 1832 | * @brief Get I2Cx clock source |
<> | 135:176b8275d35d | 1833 | * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n |
<> | 135:176b8275d35d | 1834 | * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n |
<> | 135:176b8275d35d | 1835 | * CFGR3 I2C3SW LL_RCC_GetI2CClockSource |
<> | 135:176b8275d35d | 1836 | * @param I2Cx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1837 | * @arg @ref LL_RCC_I2C1_CLKSOURCE |
<> | 135:176b8275d35d | 1838 | * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1839 | * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1840 | * |
<> | 135:176b8275d35d | 1841 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1842 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1843 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
<> | 135:176b8275d35d | 1844 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1845 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1846 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1847 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
<> | 135:176b8275d35d | 1848 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
<> | 135:176b8275d35d | 1849 | * |
<> | 135:176b8275d35d | 1850 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1851 | */ |
<> | 135:176b8275d35d | 1852 | __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) |
<> | 135:176b8275d35d | 1853 | { |
<> | 135:176b8275d35d | 1854 | return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U)); |
<> | 135:176b8275d35d | 1855 | } |
<> | 135:176b8275d35d | 1856 | |
<> | 135:176b8275d35d | 1857 | #if defined(RCC_CFGR_I2SSRC) |
<> | 135:176b8275d35d | 1858 | /** |
<> | 135:176b8275d35d | 1859 | * @brief Get I2Sx clock source |
<> | 135:176b8275d35d | 1860 | * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource |
<> | 135:176b8275d35d | 1861 | * @param I2Sx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1862 | * @arg @ref LL_RCC_I2S_CLKSOURCE |
<> | 135:176b8275d35d | 1863 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1864 | * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK |
<> | 135:176b8275d35d | 1865 | * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN |
<> | 135:176b8275d35d | 1866 | */ |
<> | 135:176b8275d35d | 1867 | __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) |
<> | 135:176b8275d35d | 1868 | { |
<> | 135:176b8275d35d | 1869 | return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); |
<> | 135:176b8275d35d | 1870 | } |
<> | 135:176b8275d35d | 1871 | #endif /* RCC_CFGR_I2SSRC */ |
<> | 135:176b8275d35d | 1872 | |
<> | 135:176b8275d35d | 1873 | #if defined(RCC_CFGR3_TIMSW) |
<> | 135:176b8275d35d | 1874 | /** |
<> | 135:176b8275d35d | 1875 | * @brief Get TIMx clock source |
<> | 135:176b8275d35d | 1876 | * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1877 | * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1878 | * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1879 | * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1880 | * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1881 | * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1882 | * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n |
<> | 135:176b8275d35d | 1883 | * CFGR3 TIM34SW LL_RCC_GetTIMClockSource |
<> | 135:176b8275d35d | 1884 | * @param TIMx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1885 | * @arg @ref LL_RCC_TIM1_CLKSOURCE |
<> | 135:176b8275d35d | 1886 | * @arg @ref LL_RCC_TIM2_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1887 | * @arg @ref LL_RCC_TIM8_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1888 | * @arg @ref LL_RCC_TIM15_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1889 | * @arg @ref LL_RCC_TIM16_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1890 | * @arg @ref LL_RCC_TIM17_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1891 | * @arg @ref LL_RCC_TIM20_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1892 | * @arg @ref LL_RCC_TIM34_CLKSOURCE (*) |
<> | 135:176b8275d35d | 1893 | * |
<> | 135:176b8275d35d | 1894 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1895 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1896 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 |
<> | 135:176b8275d35d | 1897 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1898 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1899 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1900 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1901 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1902 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1903 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1904 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1905 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1906 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) |
<> | 135:176b8275d35d | 1907 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1908 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1909 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1910 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) |
<> | 135:176b8275d35d | 1911 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) |
<> | 135:176b8275d35d | 1912 | * |
<> | 135:176b8275d35d | 1913 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1914 | */ |
<> | 135:176b8275d35d | 1915 | __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) |
<> | 135:176b8275d35d | 1916 | { |
<> | 135:176b8275d35d | 1917 | return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U)); |
<> | 135:176b8275d35d | 1918 | } |
<> | 135:176b8275d35d | 1919 | #endif /* RCC_CFGR3_TIMSW */ |
<> | 135:176b8275d35d | 1920 | |
<> | 135:176b8275d35d | 1921 | #if defined(HRTIM1) |
<> | 135:176b8275d35d | 1922 | /** |
<> | 135:176b8275d35d | 1923 | * @brief Get HRTIMx clock source |
<> | 135:176b8275d35d | 1924 | * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource |
<> | 135:176b8275d35d | 1925 | * @param HRTIMx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1926 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE |
<> | 135:176b8275d35d | 1927 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1928 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 |
<> | 135:176b8275d35d | 1929 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1930 | */ |
<> | 135:176b8275d35d | 1931 | __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx) |
<> | 135:176b8275d35d | 1932 | { |
<> | 135:176b8275d35d | 1933 | return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx)); |
<> | 135:176b8275d35d | 1934 | } |
<> | 135:176b8275d35d | 1935 | #endif /* HRTIM1 */ |
<> | 135:176b8275d35d | 1936 | |
<> | 135:176b8275d35d | 1937 | #if defined(CEC) |
<> | 135:176b8275d35d | 1938 | /** |
<> | 135:176b8275d35d | 1939 | * @brief Get CEC clock source |
<> | 135:176b8275d35d | 1940 | * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource |
<> | 135:176b8275d35d | 1941 | * @param CECx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1942 | * @arg @ref LL_RCC_CEC_CLKSOURCE |
<> | 135:176b8275d35d | 1943 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1944 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
<> | 135:176b8275d35d | 1945 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 1946 | */ |
<> | 135:176b8275d35d | 1947 | __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) |
<> | 135:176b8275d35d | 1948 | { |
<> | 135:176b8275d35d | 1949 | return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); |
<> | 135:176b8275d35d | 1950 | } |
<> | 135:176b8275d35d | 1951 | #endif /* CEC */ |
<> | 135:176b8275d35d | 1952 | |
<> | 135:176b8275d35d | 1953 | #if defined(USB) |
<> | 135:176b8275d35d | 1954 | /** |
<> | 135:176b8275d35d | 1955 | * @brief Get USBx clock source |
<> | 135:176b8275d35d | 1956 | * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource |
<> | 135:176b8275d35d | 1957 | * @param USBx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1958 | * @arg @ref LL_RCC_USB_CLKSOURCE |
<> | 135:176b8275d35d | 1959 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1960 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
<> | 135:176b8275d35d | 1961 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 |
<> | 135:176b8275d35d | 1962 | */ |
<> | 135:176b8275d35d | 1963 | __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) |
<> | 135:176b8275d35d | 1964 | { |
<> | 135:176b8275d35d | 1965 | return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); |
<> | 135:176b8275d35d | 1966 | } |
<> | 135:176b8275d35d | 1967 | #endif /* USB */ |
<> | 135:176b8275d35d | 1968 | |
<> | 135:176b8275d35d | 1969 | #if defined(RCC_CFGR_ADCPRE) |
<> | 135:176b8275d35d | 1970 | /** |
<> | 135:176b8275d35d | 1971 | * @brief Get ADCx clock source |
<> | 135:176b8275d35d | 1972 | * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource |
<> | 135:176b8275d35d | 1973 | * @param ADCx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1974 | * @arg @ref LL_RCC_ADC_CLKSOURCE |
<> | 135:176b8275d35d | 1975 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1976 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
<> | 135:176b8275d35d | 1977 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
<> | 135:176b8275d35d | 1978 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
<> | 135:176b8275d35d | 1979 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
<> | 135:176b8275d35d | 1980 | */ |
<> | 135:176b8275d35d | 1981 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
<> | 135:176b8275d35d | 1982 | { |
<> | 135:176b8275d35d | 1983 | return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); |
<> | 135:176b8275d35d | 1984 | } |
<> | 135:176b8275d35d | 1985 | |
<> | 135:176b8275d35d | 1986 | #elif defined(RCC_CFGR2_ADC1PRES) |
<> | 135:176b8275d35d | 1987 | /** |
<> | 135:176b8275d35d | 1988 | * @brief Get ADCx clock source |
<> | 135:176b8275d35d | 1989 | * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource |
<> | 135:176b8275d35d | 1990 | * @param ADCx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1991 | * @arg @ref LL_RCC_ADC1_CLKSOURCE |
<> | 135:176b8275d35d | 1992 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1993 | * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK |
<> | 135:176b8275d35d | 1994 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 |
<> | 135:176b8275d35d | 1995 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 |
<> | 135:176b8275d35d | 1996 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 |
<> | 135:176b8275d35d | 1997 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 |
<> | 135:176b8275d35d | 1998 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 |
<> | 135:176b8275d35d | 1999 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 |
<> | 135:176b8275d35d | 2000 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 |
<> | 135:176b8275d35d | 2001 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 |
<> | 135:176b8275d35d | 2002 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 |
<> | 135:176b8275d35d | 2003 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 |
<> | 135:176b8275d35d | 2004 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 |
<> | 135:176b8275d35d | 2005 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 |
<> | 135:176b8275d35d | 2006 | */ |
<> | 135:176b8275d35d | 2007 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
<> | 135:176b8275d35d | 2008 | { |
<> | 135:176b8275d35d | 2009 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); |
<> | 135:176b8275d35d | 2010 | } |
<> | 135:176b8275d35d | 2011 | |
<> | 135:176b8275d35d | 2012 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 2013 | /** |
<> | 135:176b8275d35d | 2014 | * @brief Get ADCx clock source |
<> | 135:176b8275d35d | 2015 | * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n |
<> | 135:176b8275d35d | 2016 | * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource |
<> | 135:176b8275d35d | 2017 | * @param ADCx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2018 | * @arg @ref LL_RCC_ADC12_CLKSOURCE |
<> | 135:176b8275d35d | 2019 | * @arg @ref LL_RCC_ADC34_CLKSOURCE (*) |
<> | 135:176b8275d35d | 2020 | * |
<> | 135:176b8275d35d | 2021 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 2022 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2023 | * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK |
<> | 135:176b8275d35d | 2024 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 |
<> | 135:176b8275d35d | 2025 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 |
<> | 135:176b8275d35d | 2026 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 |
<> | 135:176b8275d35d | 2027 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 |
<> | 135:176b8275d35d | 2028 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 |
<> | 135:176b8275d35d | 2029 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 |
<> | 135:176b8275d35d | 2030 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 |
<> | 135:176b8275d35d | 2031 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 |
<> | 135:176b8275d35d | 2032 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 |
<> | 135:176b8275d35d | 2033 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 |
<> | 135:176b8275d35d | 2034 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 |
<> | 135:176b8275d35d | 2035 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 |
<> | 135:176b8275d35d | 2036 | * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) |
<> | 135:176b8275d35d | 2037 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) |
<> | 135:176b8275d35d | 2038 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) |
<> | 135:176b8275d35d | 2039 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) |
<> | 135:176b8275d35d | 2040 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) |
<> | 135:176b8275d35d | 2041 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) |
<> | 135:176b8275d35d | 2042 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) |
<> | 135:176b8275d35d | 2043 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) |
<> | 135:176b8275d35d | 2044 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) |
<> | 135:176b8275d35d | 2045 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) |
<> | 135:176b8275d35d | 2046 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) |
<> | 135:176b8275d35d | 2047 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) |
<> | 135:176b8275d35d | 2048 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) |
<> | 135:176b8275d35d | 2049 | * |
<> | 135:176b8275d35d | 2050 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 2051 | */ |
<> | 135:176b8275d35d | 2052 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
<> | 135:176b8275d35d | 2053 | { |
<> | 135:176b8275d35d | 2054 | #if defined(RCC_CFGR2_ADCPRE34) |
<> | 135:176b8275d35d | 2055 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); |
<> | 135:176b8275d35d | 2056 | #else |
<> | 135:176b8275d35d | 2057 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); |
<> | 135:176b8275d35d | 2058 | #endif /*RCC_CFGR2_ADCPRE34*/ |
<> | 135:176b8275d35d | 2059 | } |
<> | 135:176b8275d35d | 2060 | #endif /* RCC_CFGR_ADCPRE */ |
<> | 135:176b8275d35d | 2061 | |
<> | 135:176b8275d35d | 2062 | #if defined(RCC_CFGR_SDPRE) |
<> | 135:176b8275d35d | 2063 | /** |
<> | 135:176b8275d35d | 2064 | * @brief Get SDADCx clock source |
<> | 135:176b8275d35d | 2065 | * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource |
<> | 135:176b8275d35d | 2066 | * @param SDADCx This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2067 | * @arg @ref LL_RCC_SDADC_CLKSOURCE |
<> | 135:176b8275d35d | 2068 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2069 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 |
<> | 135:176b8275d35d | 2070 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 |
<> | 135:176b8275d35d | 2071 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 |
<> | 135:176b8275d35d | 2072 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 |
<> | 135:176b8275d35d | 2073 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 |
<> | 135:176b8275d35d | 2074 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 |
<> | 135:176b8275d35d | 2075 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 |
<> | 135:176b8275d35d | 2076 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 |
<> | 135:176b8275d35d | 2077 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 |
<> | 135:176b8275d35d | 2078 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 |
<> | 135:176b8275d35d | 2079 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 |
<> | 135:176b8275d35d | 2080 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 |
<> | 135:176b8275d35d | 2081 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 |
<> | 135:176b8275d35d | 2082 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 |
<> | 135:176b8275d35d | 2083 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 |
<> | 135:176b8275d35d | 2084 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 |
<> | 135:176b8275d35d | 2085 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 |
<> | 135:176b8275d35d | 2086 | */ |
<> | 135:176b8275d35d | 2087 | __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx) |
<> | 135:176b8275d35d | 2088 | { |
<> | 135:176b8275d35d | 2089 | return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx)); |
<> | 135:176b8275d35d | 2090 | } |
<> | 135:176b8275d35d | 2091 | #endif /* RCC_CFGR_SDPRE */ |
<> | 135:176b8275d35d | 2092 | |
<> | 135:176b8275d35d | 2093 | /** |
<> | 135:176b8275d35d | 2094 | * @} |
<> | 135:176b8275d35d | 2095 | */ |
<> | 135:176b8275d35d | 2096 | |
<> | 135:176b8275d35d | 2097 | /** @defgroup RCC_LL_EF_RTC RTC |
<> | 135:176b8275d35d | 2098 | * @{ |
<> | 135:176b8275d35d | 2099 | */ |
<> | 135:176b8275d35d | 2100 | |
<> | 135:176b8275d35d | 2101 | /** |
<> | 135:176b8275d35d | 2102 | * @brief Set RTC Clock Source |
<> | 135:176b8275d35d | 2103 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
<> | 135:176b8275d35d | 2104 | * the Backup domain is reset. The BDRST bit can be used to reset them. |
<> | 135:176b8275d35d | 2105 | * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource |
<> | 135:176b8275d35d | 2106 | * @param Source This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2107 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
<> | 135:176b8275d35d | 2108 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 2109 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
<> | 135:176b8275d35d | 2110 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
<> | 135:176b8275d35d | 2111 | * @retval None |
<> | 135:176b8275d35d | 2112 | */ |
<> | 135:176b8275d35d | 2113 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
<> | 135:176b8275d35d | 2114 | { |
<> | 135:176b8275d35d | 2115 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); |
<> | 135:176b8275d35d | 2116 | } |
<> | 135:176b8275d35d | 2117 | |
<> | 135:176b8275d35d | 2118 | /** |
<> | 135:176b8275d35d | 2119 | * @brief Get RTC Clock Source |
<> | 135:176b8275d35d | 2120 | * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource |
<> | 135:176b8275d35d | 2121 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2122 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
<> | 135:176b8275d35d | 2123 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
<> | 135:176b8275d35d | 2124 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
<> | 135:176b8275d35d | 2125 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
<> | 135:176b8275d35d | 2126 | */ |
<> | 135:176b8275d35d | 2127 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
<> | 135:176b8275d35d | 2128 | { |
<> | 135:176b8275d35d | 2129 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); |
<> | 135:176b8275d35d | 2130 | } |
<> | 135:176b8275d35d | 2131 | |
<> | 135:176b8275d35d | 2132 | /** |
<> | 135:176b8275d35d | 2133 | * @brief Enable RTC |
<> | 135:176b8275d35d | 2134 | * @rmtoll BDCR RTCEN LL_RCC_EnableRTC |
<> | 135:176b8275d35d | 2135 | * @retval None |
<> | 135:176b8275d35d | 2136 | */ |
<> | 135:176b8275d35d | 2137 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
<> | 135:176b8275d35d | 2138 | { |
<> | 135:176b8275d35d | 2139 | SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
<> | 135:176b8275d35d | 2140 | } |
<> | 135:176b8275d35d | 2141 | |
<> | 135:176b8275d35d | 2142 | /** |
<> | 135:176b8275d35d | 2143 | * @brief Disable RTC |
<> | 135:176b8275d35d | 2144 | * @rmtoll BDCR RTCEN LL_RCC_DisableRTC |
<> | 135:176b8275d35d | 2145 | * @retval None |
<> | 135:176b8275d35d | 2146 | */ |
<> | 135:176b8275d35d | 2147 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
<> | 135:176b8275d35d | 2148 | { |
<> | 135:176b8275d35d | 2149 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
<> | 135:176b8275d35d | 2150 | } |
<> | 135:176b8275d35d | 2151 | |
<> | 135:176b8275d35d | 2152 | /** |
<> | 135:176b8275d35d | 2153 | * @brief Check if RTC has been enabled or not |
<> | 135:176b8275d35d | 2154 | * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC |
<> | 135:176b8275d35d | 2155 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2156 | */ |
<> | 135:176b8275d35d | 2157 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
<> | 135:176b8275d35d | 2158 | { |
<> | 135:176b8275d35d | 2159 | return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); |
<> | 135:176b8275d35d | 2160 | } |
<> | 135:176b8275d35d | 2161 | |
<> | 135:176b8275d35d | 2162 | /** |
<> | 135:176b8275d35d | 2163 | * @brief Force the Backup domain reset |
<> | 135:176b8275d35d | 2164 | * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset |
<> | 135:176b8275d35d | 2165 | * @retval None |
<> | 135:176b8275d35d | 2166 | */ |
<> | 135:176b8275d35d | 2167 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
<> | 135:176b8275d35d | 2168 | { |
<> | 135:176b8275d35d | 2169 | SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
<> | 135:176b8275d35d | 2170 | } |
<> | 135:176b8275d35d | 2171 | |
<> | 135:176b8275d35d | 2172 | /** |
<> | 135:176b8275d35d | 2173 | * @brief Release the Backup domain reset |
<> | 135:176b8275d35d | 2174 | * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset |
<> | 135:176b8275d35d | 2175 | * @retval None |
<> | 135:176b8275d35d | 2176 | */ |
<> | 135:176b8275d35d | 2177 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
<> | 135:176b8275d35d | 2178 | { |
<> | 135:176b8275d35d | 2179 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
<> | 135:176b8275d35d | 2180 | } |
<> | 135:176b8275d35d | 2181 | |
<> | 135:176b8275d35d | 2182 | /** |
<> | 135:176b8275d35d | 2183 | * @} |
<> | 135:176b8275d35d | 2184 | */ |
<> | 135:176b8275d35d | 2185 | |
<> | 135:176b8275d35d | 2186 | /** @defgroup RCC_LL_EF_PLL PLL |
<> | 135:176b8275d35d | 2187 | * @{ |
<> | 135:176b8275d35d | 2188 | */ |
<> | 135:176b8275d35d | 2189 | |
<> | 135:176b8275d35d | 2190 | /** |
<> | 135:176b8275d35d | 2191 | * @brief Enable PLL |
<> | 135:176b8275d35d | 2192 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
<> | 135:176b8275d35d | 2193 | * @retval None |
<> | 135:176b8275d35d | 2194 | */ |
<> | 135:176b8275d35d | 2195 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
<> | 135:176b8275d35d | 2196 | { |
<> | 135:176b8275d35d | 2197 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
<> | 135:176b8275d35d | 2198 | } |
<> | 135:176b8275d35d | 2199 | |
<> | 135:176b8275d35d | 2200 | /** |
<> | 135:176b8275d35d | 2201 | * @brief Disable PLL |
<> | 135:176b8275d35d | 2202 | * @note Cannot be disabled if the PLL clock is used as the system clock |
<> | 135:176b8275d35d | 2203 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
<> | 135:176b8275d35d | 2204 | * @retval None |
<> | 135:176b8275d35d | 2205 | */ |
<> | 135:176b8275d35d | 2206 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
<> | 135:176b8275d35d | 2207 | { |
<> | 135:176b8275d35d | 2208 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
<> | 135:176b8275d35d | 2209 | } |
<> | 135:176b8275d35d | 2210 | |
<> | 135:176b8275d35d | 2211 | /** |
<> | 135:176b8275d35d | 2212 | * @brief Check if PLL Ready |
<> | 135:176b8275d35d | 2213 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
<> | 135:176b8275d35d | 2214 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2215 | */ |
<> | 135:176b8275d35d | 2216 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
<> | 135:176b8275d35d | 2217 | { |
<> | 135:176b8275d35d | 2218 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
<> | 135:176b8275d35d | 2219 | } |
<> | 135:176b8275d35d | 2220 | |
<> | 135:176b8275d35d | 2221 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 135:176b8275d35d | 2222 | /** |
<> | 135:176b8275d35d | 2223 | * @brief Configure PLL used for SYSCLK Domain |
<> | 135:176b8275d35d | 2224 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 135:176b8275d35d | 2225 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 135:176b8275d35d | 2226 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
<> | 135:176b8275d35d | 2227 | * @param Source This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2228 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
<> | 135:176b8275d35d | 2229 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
<> | 135:176b8275d35d | 2230 | * @param PLLMul This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2231 | * @arg @ref LL_RCC_PLL_MUL_2 |
<> | 135:176b8275d35d | 2232 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 135:176b8275d35d | 2233 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 135:176b8275d35d | 2234 | * @arg @ref LL_RCC_PLL_MUL_5 |
<> | 135:176b8275d35d | 2235 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 135:176b8275d35d | 2236 | * @arg @ref LL_RCC_PLL_MUL_7 |
<> | 135:176b8275d35d | 2237 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 135:176b8275d35d | 2238 | * @arg @ref LL_RCC_PLL_MUL_9 |
<> | 135:176b8275d35d | 2239 | * @arg @ref LL_RCC_PLL_MUL_10 |
<> | 135:176b8275d35d | 2240 | * @arg @ref LL_RCC_PLL_MUL_11 |
<> | 135:176b8275d35d | 2241 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 135:176b8275d35d | 2242 | * @arg @ref LL_RCC_PLL_MUL_13 |
<> | 135:176b8275d35d | 2243 | * @arg @ref LL_RCC_PLL_MUL_14 |
<> | 135:176b8275d35d | 2244 | * @arg @ref LL_RCC_PLL_MUL_15 |
<> | 135:176b8275d35d | 2245 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 135:176b8275d35d | 2246 | * @param PLLDiv This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2247 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
<> | 135:176b8275d35d | 2248 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
<> | 135:176b8275d35d | 2249 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
<> | 135:176b8275d35d | 2250 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
<> | 135:176b8275d35d | 2251 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
<> | 135:176b8275d35d | 2252 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
<> | 135:176b8275d35d | 2253 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
<> | 135:176b8275d35d | 2254 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
<> | 135:176b8275d35d | 2255 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
<> | 135:176b8275d35d | 2256 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
<> | 135:176b8275d35d | 2257 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
<> | 135:176b8275d35d | 2258 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
<> | 135:176b8275d35d | 2259 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
<> | 135:176b8275d35d | 2260 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
<> | 135:176b8275d35d | 2261 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
<> | 135:176b8275d35d | 2262 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
<> | 135:176b8275d35d | 2263 | * @retval None |
<> | 135:176b8275d35d | 2264 | */ |
<> | 135:176b8275d35d | 2265 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) |
<> | 135:176b8275d35d | 2266 | { |
<> | 135:176b8275d35d | 2267 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); |
<> | 135:176b8275d35d | 2268 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); |
<> | 135:176b8275d35d | 2269 | } |
<> | 135:176b8275d35d | 2270 | |
<> | 135:176b8275d35d | 2271 | #else |
<> | 135:176b8275d35d | 2272 | |
<> | 135:176b8275d35d | 2273 | /** |
<> | 135:176b8275d35d | 2274 | * @brief Configure PLL used for SYSCLK Domain |
<> | 135:176b8275d35d | 2275 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 135:176b8275d35d | 2276 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 135:176b8275d35d | 2277 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
<> | 135:176b8275d35d | 2278 | * @param Source This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2279 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
<> | 135:176b8275d35d | 2280 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 |
<> | 135:176b8275d35d | 2281 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 |
<> | 135:176b8275d35d | 2282 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 |
<> | 135:176b8275d35d | 2283 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 |
<> | 135:176b8275d35d | 2284 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 |
<> | 135:176b8275d35d | 2285 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 |
<> | 135:176b8275d35d | 2286 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 |
<> | 135:176b8275d35d | 2287 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 |
<> | 135:176b8275d35d | 2288 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 |
<> | 135:176b8275d35d | 2289 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 |
<> | 135:176b8275d35d | 2290 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 |
<> | 135:176b8275d35d | 2291 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 |
<> | 135:176b8275d35d | 2292 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 |
<> | 135:176b8275d35d | 2293 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 |
<> | 135:176b8275d35d | 2294 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 |
<> | 135:176b8275d35d | 2295 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 |
<> | 135:176b8275d35d | 2296 | * @param PLLMul This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2297 | * @arg @ref LL_RCC_PLL_MUL_2 |
<> | 135:176b8275d35d | 2298 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 135:176b8275d35d | 2299 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 135:176b8275d35d | 2300 | * @arg @ref LL_RCC_PLL_MUL_5 |
<> | 135:176b8275d35d | 2301 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 135:176b8275d35d | 2302 | * @arg @ref LL_RCC_PLL_MUL_7 |
<> | 135:176b8275d35d | 2303 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 135:176b8275d35d | 2304 | * @arg @ref LL_RCC_PLL_MUL_9 |
<> | 135:176b8275d35d | 2305 | * @arg @ref LL_RCC_PLL_MUL_10 |
<> | 135:176b8275d35d | 2306 | * @arg @ref LL_RCC_PLL_MUL_11 |
<> | 135:176b8275d35d | 2307 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 135:176b8275d35d | 2308 | * @arg @ref LL_RCC_PLL_MUL_13 |
<> | 135:176b8275d35d | 2309 | * @arg @ref LL_RCC_PLL_MUL_14 |
<> | 135:176b8275d35d | 2310 | * @arg @ref LL_RCC_PLL_MUL_15 |
<> | 135:176b8275d35d | 2311 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 135:176b8275d35d | 2312 | * @retval None |
<> | 135:176b8275d35d | 2313 | */ |
<> | 135:176b8275d35d | 2314 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) |
<> | 135:176b8275d35d | 2315 | { |
<> | 135:176b8275d35d | 2316 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); |
<> | 135:176b8275d35d | 2317 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); |
<> | 135:176b8275d35d | 2318 | } |
<> | 135:176b8275d35d | 2319 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 135:176b8275d35d | 2320 | |
<> | 135:176b8275d35d | 2321 | /** |
<> | 135:176b8275d35d | 2322 | * @brief Get the oscillator used as PLL clock source. |
<> | 135:176b8275d35d | 2323 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource |
<> | 135:176b8275d35d | 2324 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2325 | * @arg @ref LL_RCC_PLLSOURCE_HSI (*) |
<> | 135:176b8275d35d | 2326 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) |
<> | 135:176b8275d35d | 2327 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
<> | 135:176b8275d35d | 2328 | * |
<> | 135:176b8275d35d | 2329 | * (*) value not defined in all devices |
<> | 135:176b8275d35d | 2330 | */ |
<> | 135:176b8275d35d | 2331 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
<> | 135:176b8275d35d | 2332 | { |
<> | 135:176b8275d35d | 2333 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
<> | 135:176b8275d35d | 2334 | } |
<> | 135:176b8275d35d | 2335 | |
<> | 135:176b8275d35d | 2336 | /** |
<> | 135:176b8275d35d | 2337 | * @brief Get PLL multiplication Factor |
<> | 135:176b8275d35d | 2338 | * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator |
<> | 135:176b8275d35d | 2339 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2340 | * @arg @ref LL_RCC_PLL_MUL_2 |
<> | 135:176b8275d35d | 2341 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 135:176b8275d35d | 2342 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 135:176b8275d35d | 2343 | * @arg @ref LL_RCC_PLL_MUL_5 |
<> | 135:176b8275d35d | 2344 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 135:176b8275d35d | 2345 | * @arg @ref LL_RCC_PLL_MUL_7 |
<> | 135:176b8275d35d | 2346 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 135:176b8275d35d | 2347 | * @arg @ref LL_RCC_PLL_MUL_9 |
<> | 135:176b8275d35d | 2348 | * @arg @ref LL_RCC_PLL_MUL_10 |
<> | 135:176b8275d35d | 2349 | * @arg @ref LL_RCC_PLL_MUL_11 |
<> | 135:176b8275d35d | 2350 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 135:176b8275d35d | 2351 | * @arg @ref LL_RCC_PLL_MUL_13 |
<> | 135:176b8275d35d | 2352 | * @arg @ref LL_RCC_PLL_MUL_14 |
<> | 135:176b8275d35d | 2353 | * @arg @ref LL_RCC_PLL_MUL_15 |
<> | 135:176b8275d35d | 2354 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 135:176b8275d35d | 2355 | */ |
<> | 135:176b8275d35d | 2356 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
<> | 135:176b8275d35d | 2357 | { |
<> | 135:176b8275d35d | 2358 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); |
<> | 135:176b8275d35d | 2359 | } |
<> | 135:176b8275d35d | 2360 | |
<> | 135:176b8275d35d | 2361 | /** |
<> | 135:176b8275d35d | 2362 | * @brief Get PREDIV division factor for the main PLL |
<> | 135:176b8275d35d | 2363 | * @note They can be written only when the PLL is disabled |
<> | 135:176b8275d35d | 2364 | * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv |
<> | 135:176b8275d35d | 2365 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2366 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
<> | 135:176b8275d35d | 2367 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
<> | 135:176b8275d35d | 2368 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
<> | 135:176b8275d35d | 2369 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
<> | 135:176b8275d35d | 2370 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
<> | 135:176b8275d35d | 2371 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
<> | 135:176b8275d35d | 2372 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
<> | 135:176b8275d35d | 2373 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
<> | 135:176b8275d35d | 2374 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
<> | 135:176b8275d35d | 2375 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
<> | 135:176b8275d35d | 2376 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
<> | 135:176b8275d35d | 2377 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
<> | 135:176b8275d35d | 2378 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
<> | 135:176b8275d35d | 2379 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
<> | 135:176b8275d35d | 2380 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
<> | 135:176b8275d35d | 2381 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
<> | 135:176b8275d35d | 2382 | */ |
<> | 135:176b8275d35d | 2383 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) |
<> | 135:176b8275d35d | 2384 | { |
<> | 135:176b8275d35d | 2385 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); |
<> | 135:176b8275d35d | 2386 | } |
<> | 135:176b8275d35d | 2387 | |
<> | 135:176b8275d35d | 2388 | /** |
<> | 135:176b8275d35d | 2389 | * @} |
<> | 135:176b8275d35d | 2390 | */ |
<> | 135:176b8275d35d | 2391 | |
<> | 135:176b8275d35d | 2392 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
<> | 135:176b8275d35d | 2393 | * @{ |
<> | 135:176b8275d35d | 2394 | */ |
<> | 135:176b8275d35d | 2395 | |
<> | 135:176b8275d35d | 2396 | /** |
<> | 135:176b8275d35d | 2397 | * @brief Clear LSI ready interrupt flag |
<> | 135:176b8275d35d | 2398 | * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
<> | 135:176b8275d35d | 2399 | * @retval None |
<> | 135:176b8275d35d | 2400 | */ |
<> | 135:176b8275d35d | 2401 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
<> | 135:176b8275d35d | 2402 | { |
<> | 135:176b8275d35d | 2403 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
<> | 135:176b8275d35d | 2404 | } |
<> | 135:176b8275d35d | 2405 | |
<> | 135:176b8275d35d | 2406 | /** |
<> | 135:176b8275d35d | 2407 | * @brief Clear LSE ready interrupt flag |
<> | 135:176b8275d35d | 2408 | * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
<> | 135:176b8275d35d | 2409 | * @retval None |
<> | 135:176b8275d35d | 2410 | */ |
<> | 135:176b8275d35d | 2411 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
<> | 135:176b8275d35d | 2412 | { |
<> | 135:176b8275d35d | 2413 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
<> | 135:176b8275d35d | 2414 | } |
<> | 135:176b8275d35d | 2415 | |
<> | 135:176b8275d35d | 2416 | /** |
<> | 135:176b8275d35d | 2417 | * @brief Clear HSI ready interrupt flag |
<> | 135:176b8275d35d | 2418 | * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
<> | 135:176b8275d35d | 2419 | * @retval None |
<> | 135:176b8275d35d | 2420 | */ |
<> | 135:176b8275d35d | 2421 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
<> | 135:176b8275d35d | 2422 | { |
<> | 135:176b8275d35d | 2423 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
<> | 135:176b8275d35d | 2424 | } |
<> | 135:176b8275d35d | 2425 | |
<> | 135:176b8275d35d | 2426 | /** |
<> | 135:176b8275d35d | 2427 | * @brief Clear HSE ready interrupt flag |
<> | 135:176b8275d35d | 2428 | * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
<> | 135:176b8275d35d | 2429 | * @retval None |
<> | 135:176b8275d35d | 2430 | */ |
<> | 135:176b8275d35d | 2431 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
<> | 135:176b8275d35d | 2432 | { |
<> | 135:176b8275d35d | 2433 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
<> | 135:176b8275d35d | 2434 | } |
<> | 135:176b8275d35d | 2435 | |
<> | 135:176b8275d35d | 2436 | /** |
<> | 135:176b8275d35d | 2437 | * @brief Clear PLL ready interrupt flag |
<> | 135:176b8275d35d | 2438 | * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
<> | 135:176b8275d35d | 2439 | * @retval None |
<> | 135:176b8275d35d | 2440 | */ |
<> | 135:176b8275d35d | 2441 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
<> | 135:176b8275d35d | 2442 | { |
<> | 135:176b8275d35d | 2443 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
<> | 135:176b8275d35d | 2444 | } |
<> | 135:176b8275d35d | 2445 | |
<> | 135:176b8275d35d | 2446 | /** |
<> | 135:176b8275d35d | 2447 | * @brief Clear Clock security system interrupt flag |
<> | 135:176b8275d35d | 2448 | * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
<> | 135:176b8275d35d | 2449 | * @retval None |
<> | 135:176b8275d35d | 2450 | */ |
<> | 135:176b8275d35d | 2451 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
<> | 135:176b8275d35d | 2452 | { |
<> | 135:176b8275d35d | 2453 | SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
<> | 135:176b8275d35d | 2454 | } |
<> | 135:176b8275d35d | 2455 | |
<> | 135:176b8275d35d | 2456 | /** |
<> | 135:176b8275d35d | 2457 | * @brief Check if LSI ready interrupt occurred or not |
<> | 135:176b8275d35d | 2458 | * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
<> | 135:176b8275d35d | 2459 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2460 | */ |
<> | 135:176b8275d35d | 2461 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
<> | 135:176b8275d35d | 2462 | { |
<> | 135:176b8275d35d | 2463 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
<> | 135:176b8275d35d | 2464 | } |
<> | 135:176b8275d35d | 2465 | |
<> | 135:176b8275d35d | 2466 | /** |
<> | 135:176b8275d35d | 2467 | * @brief Check if LSE ready interrupt occurred or not |
<> | 135:176b8275d35d | 2468 | * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
<> | 135:176b8275d35d | 2469 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2470 | */ |
<> | 135:176b8275d35d | 2471 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
<> | 135:176b8275d35d | 2472 | { |
<> | 135:176b8275d35d | 2473 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
<> | 135:176b8275d35d | 2474 | } |
<> | 135:176b8275d35d | 2475 | |
<> | 135:176b8275d35d | 2476 | /** |
<> | 135:176b8275d35d | 2477 | * @brief Check if HSI ready interrupt occurred or not |
<> | 135:176b8275d35d | 2478 | * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
<> | 135:176b8275d35d | 2479 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2480 | */ |
<> | 135:176b8275d35d | 2481 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
<> | 135:176b8275d35d | 2482 | { |
<> | 135:176b8275d35d | 2483 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
<> | 135:176b8275d35d | 2484 | } |
<> | 135:176b8275d35d | 2485 | |
<> | 135:176b8275d35d | 2486 | /** |
<> | 135:176b8275d35d | 2487 | * @brief Check if HSE ready interrupt occurred or not |
<> | 135:176b8275d35d | 2488 | * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
<> | 135:176b8275d35d | 2489 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2490 | */ |
<> | 135:176b8275d35d | 2491 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
<> | 135:176b8275d35d | 2492 | { |
<> | 135:176b8275d35d | 2493 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
<> | 135:176b8275d35d | 2494 | } |
<> | 135:176b8275d35d | 2495 | |
<> | 135:176b8275d35d | 2496 | #if defined(RCC_CFGR_MCOF) |
<> | 135:176b8275d35d | 2497 | /** |
<> | 135:176b8275d35d | 2498 | * @brief Check if switch to new MCO source is effective or not |
<> | 135:176b8275d35d | 2499 | * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1 |
<> | 135:176b8275d35d | 2500 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2501 | */ |
<> | 135:176b8275d35d | 2502 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void) |
<> | 135:176b8275d35d | 2503 | { |
<> | 135:176b8275d35d | 2504 | return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF)); |
<> | 135:176b8275d35d | 2505 | } |
<> | 135:176b8275d35d | 2506 | #endif /* RCC_CFGR_MCOF */ |
<> | 135:176b8275d35d | 2507 | |
<> | 135:176b8275d35d | 2508 | /** |
<> | 135:176b8275d35d | 2509 | * @brief Check if PLL ready interrupt occurred or not |
<> | 135:176b8275d35d | 2510 | * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
<> | 135:176b8275d35d | 2511 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2512 | */ |
<> | 135:176b8275d35d | 2513 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
<> | 135:176b8275d35d | 2514 | { |
<> | 135:176b8275d35d | 2515 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
<> | 135:176b8275d35d | 2516 | } |
<> | 135:176b8275d35d | 2517 | |
<> | 135:176b8275d35d | 2518 | /** |
<> | 135:176b8275d35d | 2519 | * @brief Check if Clock security system interrupt occurred or not |
<> | 135:176b8275d35d | 2520 | * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
<> | 135:176b8275d35d | 2521 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2522 | */ |
<> | 135:176b8275d35d | 2523 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
<> | 135:176b8275d35d | 2524 | { |
<> | 135:176b8275d35d | 2525 | return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
<> | 135:176b8275d35d | 2526 | } |
<> | 135:176b8275d35d | 2527 | |
<> | 135:176b8275d35d | 2528 | /** |
<> | 135:176b8275d35d | 2529 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
<> | 135:176b8275d35d | 2530 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
<> | 135:176b8275d35d | 2531 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2532 | */ |
<> | 135:176b8275d35d | 2533 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
<> | 135:176b8275d35d | 2534 | { |
<> | 135:176b8275d35d | 2535 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
<> | 135:176b8275d35d | 2536 | } |
<> | 135:176b8275d35d | 2537 | |
<> | 135:176b8275d35d | 2538 | /** |
<> | 135:176b8275d35d | 2539 | * @brief Check if RCC flag Low Power reset is set or not. |
<> | 135:176b8275d35d | 2540 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
<> | 135:176b8275d35d | 2541 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2542 | */ |
<> | 135:176b8275d35d | 2543 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
<> | 135:176b8275d35d | 2544 | { |
<> | 135:176b8275d35d | 2545 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
<> | 135:176b8275d35d | 2546 | } |
<> | 135:176b8275d35d | 2547 | |
<> | 135:176b8275d35d | 2548 | /** |
<> | 135:176b8275d35d | 2549 | * @brief Check if RCC flag is set or not. |
<> | 135:176b8275d35d | 2550 | * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST |
<> | 135:176b8275d35d | 2551 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2552 | */ |
<> | 135:176b8275d35d | 2553 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) |
<> | 135:176b8275d35d | 2554 | { |
<> | 135:176b8275d35d | 2555 | return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); |
<> | 135:176b8275d35d | 2556 | } |
<> | 135:176b8275d35d | 2557 | |
<> | 135:176b8275d35d | 2558 | /** |
<> | 135:176b8275d35d | 2559 | * @brief Check if RCC flag Pin reset is set or not. |
<> | 135:176b8275d35d | 2560 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
<> | 135:176b8275d35d | 2561 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2562 | */ |
<> | 135:176b8275d35d | 2563 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
<> | 135:176b8275d35d | 2564 | { |
<> | 135:176b8275d35d | 2565 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
<> | 135:176b8275d35d | 2566 | } |
<> | 135:176b8275d35d | 2567 | |
<> | 135:176b8275d35d | 2568 | /** |
<> | 135:176b8275d35d | 2569 | * @brief Check if RCC flag POR/PDR reset is set or not. |
<> | 135:176b8275d35d | 2570 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
<> | 135:176b8275d35d | 2571 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2572 | */ |
<> | 135:176b8275d35d | 2573 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
<> | 135:176b8275d35d | 2574 | { |
<> | 135:176b8275d35d | 2575 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
<> | 135:176b8275d35d | 2576 | } |
<> | 135:176b8275d35d | 2577 | |
<> | 135:176b8275d35d | 2578 | /** |
<> | 135:176b8275d35d | 2579 | * @brief Check if RCC flag Software reset is set or not. |
<> | 135:176b8275d35d | 2580 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
<> | 135:176b8275d35d | 2581 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2582 | */ |
<> | 135:176b8275d35d | 2583 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
<> | 135:176b8275d35d | 2584 | { |
<> | 135:176b8275d35d | 2585 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
<> | 135:176b8275d35d | 2586 | } |
<> | 135:176b8275d35d | 2587 | |
<> | 135:176b8275d35d | 2588 | /** |
<> | 135:176b8275d35d | 2589 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
<> | 135:176b8275d35d | 2590 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
<> | 135:176b8275d35d | 2591 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2592 | */ |
<> | 135:176b8275d35d | 2593 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
<> | 135:176b8275d35d | 2594 | { |
<> | 135:176b8275d35d | 2595 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
<> | 135:176b8275d35d | 2596 | } |
<> | 135:176b8275d35d | 2597 | |
<> | 135:176b8275d35d | 2598 | #if defined(RCC_CSR_V18PWRRSTF) |
<> | 135:176b8275d35d | 2599 | /** |
<> | 135:176b8275d35d | 2600 | * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. |
<> | 135:176b8275d35d | 2601 | * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST |
<> | 135:176b8275d35d | 2602 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2603 | */ |
<> | 135:176b8275d35d | 2604 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) |
<> | 135:176b8275d35d | 2605 | { |
<> | 135:176b8275d35d | 2606 | return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); |
<> | 135:176b8275d35d | 2607 | } |
<> | 135:176b8275d35d | 2608 | #endif /* RCC_CSR_V18PWRRSTF */ |
<> | 135:176b8275d35d | 2609 | |
<> | 135:176b8275d35d | 2610 | /** |
<> | 135:176b8275d35d | 2611 | * @brief Set RMVF bit to clear the reset flags. |
<> | 135:176b8275d35d | 2612 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
<> | 135:176b8275d35d | 2613 | * @retval None |
<> | 135:176b8275d35d | 2614 | */ |
<> | 135:176b8275d35d | 2615 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
<> | 135:176b8275d35d | 2616 | { |
<> | 135:176b8275d35d | 2617 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
<> | 135:176b8275d35d | 2618 | } |
<> | 135:176b8275d35d | 2619 | |
<> | 135:176b8275d35d | 2620 | /** |
<> | 135:176b8275d35d | 2621 | * @} |
<> | 135:176b8275d35d | 2622 | */ |
<> | 135:176b8275d35d | 2623 | |
<> | 135:176b8275d35d | 2624 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
<> | 135:176b8275d35d | 2625 | * @{ |
<> | 135:176b8275d35d | 2626 | */ |
<> | 135:176b8275d35d | 2627 | |
<> | 135:176b8275d35d | 2628 | /** |
<> | 135:176b8275d35d | 2629 | * @brief Enable LSI ready interrupt |
<> | 135:176b8275d35d | 2630 | * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
<> | 135:176b8275d35d | 2631 | * @retval None |
<> | 135:176b8275d35d | 2632 | */ |
<> | 135:176b8275d35d | 2633 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
<> | 135:176b8275d35d | 2634 | { |
<> | 135:176b8275d35d | 2635 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
<> | 135:176b8275d35d | 2636 | } |
<> | 135:176b8275d35d | 2637 | |
<> | 135:176b8275d35d | 2638 | /** |
<> | 135:176b8275d35d | 2639 | * @brief Enable LSE ready interrupt |
<> | 135:176b8275d35d | 2640 | * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
<> | 135:176b8275d35d | 2641 | * @retval None |
<> | 135:176b8275d35d | 2642 | */ |
<> | 135:176b8275d35d | 2643 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
<> | 135:176b8275d35d | 2644 | { |
<> | 135:176b8275d35d | 2645 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
<> | 135:176b8275d35d | 2646 | } |
<> | 135:176b8275d35d | 2647 | |
<> | 135:176b8275d35d | 2648 | /** |
<> | 135:176b8275d35d | 2649 | * @brief Enable HSI ready interrupt |
<> | 135:176b8275d35d | 2650 | * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
<> | 135:176b8275d35d | 2651 | * @retval None |
<> | 135:176b8275d35d | 2652 | */ |
<> | 135:176b8275d35d | 2653 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
<> | 135:176b8275d35d | 2654 | { |
<> | 135:176b8275d35d | 2655 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
<> | 135:176b8275d35d | 2656 | } |
<> | 135:176b8275d35d | 2657 | |
<> | 135:176b8275d35d | 2658 | /** |
<> | 135:176b8275d35d | 2659 | * @brief Enable HSE ready interrupt |
<> | 135:176b8275d35d | 2660 | * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
<> | 135:176b8275d35d | 2661 | * @retval None |
<> | 135:176b8275d35d | 2662 | */ |
<> | 135:176b8275d35d | 2663 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
<> | 135:176b8275d35d | 2664 | { |
<> | 135:176b8275d35d | 2665 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
<> | 135:176b8275d35d | 2666 | } |
<> | 135:176b8275d35d | 2667 | |
<> | 135:176b8275d35d | 2668 | /** |
<> | 135:176b8275d35d | 2669 | * @brief Enable PLL ready interrupt |
<> | 135:176b8275d35d | 2670 | * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
<> | 135:176b8275d35d | 2671 | * @retval None |
<> | 135:176b8275d35d | 2672 | */ |
<> | 135:176b8275d35d | 2673 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
<> | 135:176b8275d35d | 2674 | { |
<> | 135:176b8275d35d | 2675 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
<> | 135:176b8275d35d | 2676 | } |
<> | 135:176b8275d35d | 2677 | |
<> | 135:176b8275d35d | 2678 | /** |
<> | 135:176b8275d35d | 2679 | * @brief Disable LSI ready interrupt |
<> | 135:176b8275d35d | 2680 | * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
<> | 135:176b8275d35d | 2681 | * @retval None |
<> | 135:176b8275d35d | 2682 | */ |
<> | 135:176b8275d35d | 2683 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
<> | 135:176b8275d35d | 2684 | { |
<> | 135:176b8275d35d | 2685 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
<> | 135:176b8275d35d | 2686 | } |
<> | 135:176b8275d35d | 2687 | |
<> | 135:176b8275d35d | 2688 | /** |
<> | 135:176b8275d35d | 2689 | * @brief Disable LSE ready interrupt |
<> | 135:176b8275d35d | 2690 | * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
<> | 135:176b8275d35d | 2691 | * @retval None |
<> | 135:176b8275d35d | 2692 | */ |
<> | 135:176b8275d35d | 2693 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
<> | 135:176b8275d35d | 2694 | { |
<> | 135:176b8275d35d | 2695 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
<> | 135:176b8275d35d | 2696 | } |
<> | 135:176b8275d35d | 2697 | |
<> | 135:176b8275d35d | 2698 | /** |
<> | 135:176b8275d35d | 2699 | * @brief Disable HSI ready interrupt |
<> | 135:176b8275d35d | 2700 | * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
<> | 135:176b8275d35d | 2701 | * @retval None |
<> | 135:176b8275d35d | 2702 | */ |
<> | 135:176b8275d35d | 2703 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
<> | 135:176b8275d35d | 2704 | { |
<> | 135:176b8275d35d | 2705 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
<> | 135:176b8275d35d | 2706 | } |
<> | 135:176b8275d35d | 2707 | |
<> | 135:176b8275d35d | 2708 | /** |
<> | 135:176b8275d35d | 2709 | * @brief Disable HSE ready interrupt |
<> | 135:176b8275d35d | 2710 | * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
<> | 135:176b8275d35d | 2711 | * @retval None |
<> | 135:176b8275d35d | 2712 | */ |
<> | 135:176b8275d35d | 2713 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
<> | 135:176b8275d35d | 2714 | { |
<> | 135:176b8275d35d | 2715 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
<> | 135:176b8275d35d | 2716 | } |
<> | 135:176b8275d35d | 2717 | |
<> | 135:176b8275d35d | 2718 | /** |
<> | 135:176b8275d35d | 2719 | * @brief Disable PLL ready interrupt |
<> | 135:176b8275d35d | 2720 | * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
<> | 135:176b8275d35d | 2721 | * @retval None |
<> | 135:176b8275d35d | 2722 | */ |
<> | 135:176b8275d35d | 2723 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
<> | 135:176b8275d35d | 2724 | { |
<> | 135:176b8275d35d | 2725 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
<> | 135:176b8275d35d | 2726 | } |
<> | 135:176b8275d35d | 2727 | |
<> | 135:176b8275d35d | 2728 | /** |
<> | 135:176b8275d35d | 2729 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
<> | 135:176b8275d35d | 2730 | * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
<> | 135:176b8275d35d | 2731 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2732 | */ |
<> | 135:176b8275d35d | 2733 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
<> | 135:176b8275d35d | 2734 | { |
<> | 135:176b8275d35d | 2735 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
<> | 135:176b8275d35d | 2736 | } |
<> | 135:176b8275d35d | 2737 | |
<> | 135:176b8275d35d | 2738 | /** |
<> | 135:176b8275d35d | 2739 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
<> | 135:176b8275d35d | 2740 | * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
<> | 135:176b8275d35d | 2741 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2742 | */ |
<> | 135:176b8275d35d | 2743 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
<> | 135:176b8275d35d | 2744 | { |
<> | 135:176b8275d35d | 2745 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
<> | 135:176b8275d35d | 2746 | } |
<> | 135:176b8275d35d | 2747 | |
<> | 135:176b8275d35d | 2748 | /** |
<> | 135:176b8275d35d | 2749 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
<> | 135:176b8275d35d | 2750 | * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
<> | 135:176b8275d35d | 2751 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2752 | */ |
<> | 135:176b8275d35d | 2753 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
<> | 135:176b8275d35d | 2754 | { |
<> | 135:176b8275d35d | 2755 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
<> | 135:176b8275d35d | 2756 | } |
<> | 135:176b8275d35d | 2757 | |
<> | 135:176b8275d35d | 2758 | /** |
<> | 135:176b8275d35d | 2759 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
<> | 135:176b8275d35d | 2760 | * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
<> | 135:176b8275d35d | 2761 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2762 | */ |
<> | 135:176b8275d35d | 2763 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
<> | 135:176b8275d35d | 2764 | { |
<> | 135:176b8275d35d | 2765 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
<> | 135:176b8275d35d | 2766 | } |
<> | 135:176b8275d35d | 2767 | |
<> | 135:176b8275d35d | 2768 | /** |
<> | 135:176b8275d35d | 2769 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
<> | 135:176b8275d35d | 2770 | * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
<> | 135:176b8275d35d | 2771 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2772 | */ |
<> | 135:176b8275d35d | 2773 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
<> | 135:176b8275d35d | 2774 | { |
<> | 135:176b8275d35d | 2775 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
<> | 135:176b8275d35d | 2776 | } |
<> | 135:176b8275d35d | 2777 | |
<> | 135:176b8275d35d | 2778 | /** |
<> | 135:176b8275d35d | 2779 | * @} |
<> | 135:176b8275d35d | 2780 | */ |
<> | 135:176b8275d35d | 2781 | |
<> | 135:176b8275d35d | 2782 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 2783 | /** @defgroup RCC_LL_EF_Init De-initialization function |
<> | 135:176b8275d35d | 2784 | * @{ |
<> | 135:176b8275d35d | 2785 | */ |
<> | 135:176b8275d35d | 2786 | ErrorStatus LL_RCC_DeInit(void); |
<> | 135:176b8275d35d | 2787 | /** |
<> | 135:176b8275d35d | 2788 | * @} |
<> | 135:176b8275d35d | 2789 | */ |
<> | 135:176b8275d35d | 2790 | |
<> | 135:176b8275d35d | 2791 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
<> | 135:176b8275d35d | 2792 | * @{ |
<> | 135:176b8275d35d | 2793 | */ |
<> | 135:176b8275d35d | 2794 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
<> | 135:176b8275d35d | 2795 | uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); |
<> | 135:176b8275d35d | 2796 | #if defined(UART4) || defined(UART5) |
<> | 135:176b8275d35d | 2797 | uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); |
<> | 135:176b8275d35d | 2798 | #endif /* UART4 || UART5 */ |
<> | 135:176b8275d35d | 2799 | uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); |
<> | 135:176b8275d35d | 2800 | #if defined(RCC_CFGR_I2SSRC) |
<> | 135:176b8275d35d | 2801 | uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); |
<> | 135:176b8275d35d | 2802 | #endif /* RCC_CFGR_I2SSRC */ |
<> | 135:176b8275d35d | 2803 | #if defined(USB_OTG_FS) || defined(USB) |
<> | 135:176b8275d35d | 2804 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); |
<> | 135:176b8275d35d | 2805 | #endif /* USB_OTG_FS || USB */ |
<> | 135:176b8275d35d | 2806 | #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)) |
<> | 135:176b8275d35d | 2807 | uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); |
<> | 135:176b8275d35d | 2808 | #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ |
<> | 135:176b8275d35d | 2809 | #if defined(RCC_CFGR_SDPRE) |
<> | 135:176b8275d35d | 2810 | uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource); |
<> | 135:176b8275d35d | 2811 | #endif /*RCC_CFGR_SDPRE */ |
<> | 135:176b8275d35d | 2812 | #if defined(CEC) |
<> | 135:176b8275d35d | 2813 | uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); |
<> | 135:176b8275d35d | 2814 | #endif /* CEC */ |
<> | 135:176b8275d35d | 2815 | #if defined(RCC_CFGR3_TIMSW) |
<> | 135:176b8275d35d | 2816 | uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); |
<> | 135:176b8275d35d | 2817 | #endif /*RCC_CFGR3_TIMSW*/ |
<> | 135:176b8275d35d | 2818 | uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource); |
<> | 135:176b8275d35d | 2819 | /** |
<> | 135:176b8275d35d | 2820 | * @} |
<> | 135:176b8275d35d | 2821 | */ |
<> | 135:176b8275d35d | 2822 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 2823 | |
<> | 135:176b8275d35d | 2824 | /** |
<> | 135:176b8275d35d | 2825 | * @} |
<> | 135:176b8275d35d | 2826 | */ |
<> | 135:176b8275d35d | 2827 | |
<> | 135:176b8275d35d | 2828 | /** |
<> | 135:176b8275d35d | 2829 | * @} |
<> | 135:176b8275d35d | 2830 | */ |
<> | 135:176b8275d35d | 2831 | |
<> | 135:176b8275d35d | 2832 | #endif /* RCC */ |
<> | 135:176b8275d35d | 2833 | |
<> | 135:176b8275d35d | 2834 | /** |
<> | 135:176b8275d35d | 2835 | * @} |
<> | 135:176b8275d35d | 2836 | */ |
<> | 135:176b8275d35d | 2837 | |
<> | 135:176b8275d35d | 2838 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 2839 | } |
<> | 135:176b8275d35d | 2840 | #endif |
<> | 135:176b8275d35d | 2841 | |
<> | 135:176b8275d35d | 2842 | #endif /* __STM32F3xx_LL_RCC_H */ |
<> | 135:176b8275d35d | 2843 | |
<> | 135:176b8275d35d | 2844 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |