mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_hrtim.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 135:176b8275d35d
Child:: 168:b9e159c1930a

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_hrtim.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
<>	135:176b8275d35d	7	* @brief Header file of HRTIM LL module.
<>	135:176b8275d35d	8	******************************************************************************
<>	135:176b8275d35d	9	* @attention
<>	135:176b8275d35d	10	*
<>	135:176b8275d35d	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	12	*
<>	135:176b8275d35d	13	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	14	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	16	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	18	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	19	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	21	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	22	* without specific prior written permission.
<>	135:176b8275d35d	23	*
<>	135:176b8275d35d	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	34	*
<>	135:176b8275d35d	35	******************************************************************************
<>	135:176b8275d35d	36	*/
<>	135:176b8275d35d	37
<>	135:176b8275d35d	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	39	#ifndef __STM32F3xx_LL_HRTIM_H
<>	135:176b8275d35d	40	#define __STM32F3xx_LL_HRTIM_H
<>	135:176b8275d35d	41
<>	135:176b8275d35d	42	#ifdef __cplusplus
<>	135:176b8275d35d	43	extern "C" {
<>	135:176b8275d35d	44	#endif
<>	135:176b8275d35d	45
<>	135:176b8275d35d	46	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	47	#include "stm32f3xx.h"
<>	135:176b8275d35d	48
<>	135:176b8275d35d	49	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	50	* @{
<>	135:176b8275d35d	51	*/
<>	135:176b8275d35d	52
<>	135:176b8275d35d	53	#if defined (HRTIM1)
<>	135:176b8275d35d	54
<>	135:176b8275d35d	55	/** @defgroup HRTIM_LL HRTIM
<>	135:176b8275d35d	56	* @{
<>	135:176b8275d35d	57	*/
<>	135:176b8275d35d	58
<>	135:176b8275d35d	59	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	60	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	61	/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
<>	135:176b8275d35d	62	* @{
<>	135:176b8275d35d	63	*/
<>	135:176b8275d35d	64	static const uint16_t REG_OFFSET_TAB_TIMER[] =
<>	135:176b8275d35d	65	{
<>	135:176b8275d35d	66	0x00U, /* 0: MASTER */
<>	135:176b8275d35d	67	0x80U, /* 1: TIMER A */
<>	135:176b8275d35d	68	0x100U, /* 2: TIMER B */
<>	135:176b8275d35d	69	0x180U, /* 3: TIMER C */
<>	135:176b8275d35d	70	0x200U, /* 4: TIMER D */
<>	135:176b8275d35d	71	0x280U, /* 5: TIMER E */
<>	135:176b8275d35d	72	};
<>	135:176b8275d35d	73
<>	135:176b8275d35d	74	static const uint8_t REG_OFFSET_TAB_ADCxR[] =
<>	135:176b8275d35d	75	{
<>	135:176b8275d35d	76	0x00U, /* 0: HRTIM_ADC1R */
<>	135:176b8275d35d	77	0x04U, /* 1: HRTIM_ADC2R */
<>	135:176b8275d35d	78	0x08U, /* 2: HRTIM_ADC3R */
<>	135:176b8275d35d	79	0x0CU, /* 3: HRTIM_ADC4R */
<>	135:176b8275d35d	80	};
<>	135:176b8275d35d	81
<>	135:176b8275d35d	82	static const uint16_t REG_OFFSET_TAB_SETxR[] =
<>	135:176b8275d35d	83	{
<>	135:176b8275d35d	84	0x00U, /* 0: TA1 */
<>	135:176b8275d35d	85	0x08U, /* 1: TA2 */
<>	135:176b8275d35d	86	0x80U, /* 2: TB1 */
<>	135:176b8275d35d	87	0x88U, /* 3: TB2 */
<>	135:176b8275d35d	88	0x100U, /* 4: TC1 */
<>	135:176b8275d35d	89	0x108U, /* 5: TC2 */
<>	135:176b8275d35d	90	0x180U, /* 6: TD1 */
<>	135:176b8275d35d	91	0x188U, /* 7: TD2 */
<>	135:176b8275d35d	92	0x200U, /* 8: TE1 */
<>	135:176b8275d35d	93	0x208U /* 9: TE2 */
<>	135:176b8275d35d	94	};
<>	135:176b8275d35d	95
<>	135:176b8275d35d	96	static const uint16_t REG_OFFSET_TAB_OUTxR[] =
<>	135:176b8275d35d	97	{
<>	135:176b8275d35d	98	0x00U, /* 0: TA1 */
<>	135:176b8275d35d	99	0x00U, /* 1: TA2 */
<>	135:176b8275d35d	100	0x80U, /* 2: TB1 */
<>	135:176b8275d35d	101	0x80U, /* 3: TB2 */
<>	135:176b8275d35d	102	0x100U, /* 4: TC1 */
<>	135:176b8275d35d	103	0x100U, /* 5: TC2 */
<>	135:176b8275d35d	104	0x180U, /* 6: TD1 */
<>	135:176b8275d35d	105	0x180U, /* 7: TD2 */
<>	135:176b8275d35d	106	0x200U, /* 8: TE1 */
<>	135:176b8275d35d	107	0x200U /* 9: TE2 */
<>	135:176b8275d35d	108	};
<>	135:176b8275d35d	109
<>	135:176b8275d35d	110
<>	135:176b8275d35d	111	static const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
<>	135:176b8275d35d	112	{
<>	135:176b8275d35d	113	0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
<>	135:176b8275d35d	114	0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
<>	135:176b8275d35d	115	};
<>	135:176b8275d35d	116
<>	135:176b8275d35d	117	static const uint8_t REG_OFFSET_TAB_EECR[] =
<>	135:176b8275d35d	118	{
<>	135:176b8275d35d	119	0x00U, /* LL_HRTIM_EVENT_1 */
<>	135:176b8275d35d	120	0x00U, /* LL_HRTIM_EVENT_2 */
<>	135:176b8275d35d	121	0x00U, /* LL_HRTIM_EVENT_3 */
<>	135:176b8275d35d	122	0x00U, /* LL_HRTIM_EVENT_4 */
<>	135:176b8275d35d	123	0x00U, /* LL_HRTIM_EVENT_5 */
<>	135:176b8275d35d	124	0x04U, /* LL_HRTIM_EVENT_6 */
<>	135:176b8275d35d	125	0x04U, /* LL_HRTIM_EVENT_7 */
<>	135:176b8275d35d	126	0x04U, /* LL_HRTIM_EVENT_8 */
<>	135:176b8275d35d	127	0x04U, /* LL_HRTIM_EVENT_9 */
<>	135:176b8275d35d	128	0x04U /* LL_HRTIM_EVENT_10 */
<>	135:176b8275d35d	129	};
<>	135:176b8275d35d	130
<>	135:176b8275d35d	131	static const uint8_t REG_OFFSET_TAB_FLTINR[] =
<>	135:176b8275d35d	132	{
<>	135:176b8275d35d	133	0x00U, /* LL_HRTIM_FAULT_1 */
<>	135:176b8275d35d	134	0x00U, /* LL_HRTIM_FAULT_2 */
<>	135:176b8275d35d	135	0x00U, /* LL_HRTIM_FAULT_3 */
<>	135:176b8275d35d	136	0x00U, /* LL_HRTIM_FAULT_4 */
<>	135:176b8275d35d	137	0x04U /* LL_HRTIM_FAULT_5 */
<>	135:176b8275d35d	138	};
<>	135:176b8275d35d	139
<>	135:176b8275d35d	140	static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
<>	135:176b8275d35d	141	{
<>	135:176b8275d35d	142	0x20000000U, /* 0: MASTER */
<>	135:176b8275d35d	143	0x01FE0000U, /* 1: TIMER A */
<>	135:176b8275d35d	144	0x01FE0000U, /* 2: TIMER B */
<>	135:176b8275d35d	145	0x01FE0000U, /* 3: TIMER C */
<>	135:176b8275d35d	146	0x01FE0000U, /* 4: TIMER D */
<>	135:176b8275d35d	147	0x01FE0000U, /* 5: TIMER E */
<>	135:176b8275d35d	148	};
<>	135:176b8275d35d	149
<>	135:176b8275d35d	150	static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
<>	135:176b8275d35d	151	{
<>	135:176b8275d35d	152	12U, /* 0: MASTER */
<>	135:176b8275d35d	153	0U, /* 1: TIMER A */
<>	135:176b8275d35d	154	0U, /* 2: TIMER B */
<>	135:176b8275d35d	155	0U, /* 3: TIMER C */
<>	135:176b8275d35d	156	0U, /* 4: TIMER D */
<>	135:176b8275d35d	157	0U, /* 5: TIMER E */
<>	135:176b8275d35d	158	};
<>	135:176b8275d35d	159
<>	135:176b8275d35d	160	static const uint8_t REG_SHIFT_TAB_EExSRC[] =
<>	135:176b8275d35d	161	{
<>	135:176b8275d35d	162	0U, /* LL_HRTIM_EVENT_1 */
<>	135:176b8275d35d	163	6U, /* LL_HRTIM_EVENT_2 */
<>	135:176b8275d35d	164	12U, /* LL_HRTIM_EVENT_3 */
<>	135:176b8275d35d	165	18U, /* LL_HRTIM_EVENT_4 */
<>	135:176b8275d35d	166	24U, /* LL_HRTIM_EVENT_5 */
<>	135:176b8275d35d	167	0U, /* LL_HRTIM_EVENT_6 */
<>	135:176b8275d35d	168	6U, /* LL_HRTIM_EVENT_7 */
<>	135:176b8275d35d	169	12U, /* LL_HRTIM_EVENT_8 */
<>	135:176b8275d35d	170	18U, /* LL_HRTIM_EVENT_9 */
<>	135:176b8275d35d	171	24U /* LL_HRTIM_EVENT_10 */
<>	135:176b8275d35d	172	};
<>	135:176b8275d35d	173
<>	135:176b8275d35d	174	static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
<>	135:176b8275d35d	175	{
<>	135:176b8275d35d	176	HRTIM_MCR_BRSTDMA, /* 0: MASTER */
<>	135:176b8275d35d	177	HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
<>	135:176b8275d35d	178	HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
<>	135:176b8275d35d	179	HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
<>	135:176b8275d35d	180	HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
<>	135:176b8275d35d	181	HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
<>	135:176b8275d35d	182	};
<>	135:176b8275d35d	183
<>	135:176b8275d35d	184	static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
<>	135:176b8275d35d	185	{
<>	135:176b8275d35d	186	2U, /* 0: MASTER */
<>	135:176b8275d35d	187	0U, /* 1: TIMER A */
<>	135:176b8275d35d	188	0U, /* 2: TIMER B */
<>	135:176b8275d35d	189	0U, /* 3: TIMER C */
<>	135:176b8275d35d	190	0U, /* 4: TIMER D */
<>	135:176b8275d35d	191	0U, /* 5: TIMER E */
<>	135:176b8275d35d	192	};
<>	135:176b8275d35d	193
<>	135:176b8275d35d	194	static const uint8_t REG_SHIFT_TAB_OUTxR[] =
<>	135:176b8275d35d	195	{
<>	135:176b8275d35d	196	0U, /* 0: TA1 */
<>	135:176b8275d35d	197	16U, /* 1: TA2 */
<>	135:176b8275d35d	198	0U, /* 2: TB1 */
<>	135:176b8275d35d	199	16U, /* 3: TB2 */
<>	135:176b8275d35d	200	0U, /* 4: TC1 */
<>	135:176b8275d35d	201	16U, /* 5: TC2 */
<>	135:176b8275d35d	202	0U, /* 6: TD1 */
<>	135:176b8275d35d	203	16U, /* 7: TD2 */
<>	135:176b8275d35d	204	0U, /* 8: TE1 */
<>	135:176b8275d35d	205	16U /* 9: TE2 */
<>	135:176b8275d35d	206	};
<>	135:176b8275d35d	207
<>	135:176b8275d35d	208	static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
<>	135:176b8275d35d	209	{
<>	135:176b8275d35d	210	0U, /* 0: TA1 */
<>	135:176b8275d35d	211	1U, /* 1: TA2 */
<>	135:176b8275d35d	212	0U, /* 2: TB1 */
<>	135:176b8275d35d	213	1U, /* 3: TB2 */
<>	135:176b8275d35d	214	0U, /* 4: TC1 */
<>	135:176b8275d35d	215	1U, /* 5: TC2 */
<>	135:176b8275d35d	216	0U, /* 6: TD1 */
<>	135:176b8275d35d	217	1U, /* 7: TD2 */
<>	135:176b8275d35d	218	0U, /* 8: TE1 */
<>	135:176b8275d35d	219	1U /* 9: TE2 */
<>	135:176b8275d35d	220	};
<>	135:176b8275d35d	221
<>	135:176b8275d35d	222	static const uint8_t REG_SHIFT_TAB_FLTxE[] =
<>	135:176b8275d35d	223	{
<>	135:176b8275d35d	224	0U, /* LL_HRTIM_FAULT_1 */
<>	135:176b8275d35d	225	8U, /* LL_HRTIM_FAULT_2 */
<>	135:176b8275d35d	226	16U, /* LL_HRTIM_FAULT_3 */
<>	135:176b8275d35d	227	24U, /* LL_HRTIM_FAULT_4 */
<>	135:176b8275d35d	228	0U /* LL_HRTIM_FAULT_5 */
<>	135:176b8275d35d	229	};
<>	135:176b8275d35d	230
<>	135:176b8275d35d	231	/**
<>	135:176b8275d35d	232	* @}
<>	135:176b8275d35d	233	*/
<>	135:176b8275d35d	234
<>	135:176b8275d35d	235
<>	135:176b8275d35d	236	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	237	/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
<>	135:176b8275d35d	238	* @{
<>	135:176b8275d35d	239	*/
<>	135:176b8275d35d	240	#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS \|\
<>	135:176b8275d35d	241	HRTIM_CR1_TAUDIS \|\
<>	135:176b8275d35d	242	HRTIM_CR1_TBUDIS \|\
<>	135:176b8275d35d	243	HRTIM_CR1_TCUDIS \|\
<>	135:176b8275d35d	244	HRTIM_CR1_TDUDIS \|\
<>	135:176b8275d35d	245	HRTIM_CR1_TEUDIS))
<>	135:176b8275d35d	246
<>	135:176b8275d35d	247	#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU \|\
<>	135:176b8275d35d	248	HRTIM_CR2_TASWU \|\
<>	135:176b8275d35d	249	HRTIM_CR2_TBSWU \|\
<>	135:176b8275d35d	250	HRTIM_CR2_TCSWU \|\
<>	135:176b8275d35d	251	HRTIM_CR2_TDSWU \|\
<>	135:176b8275d35d	252	HRTIM_CR2_TESWU))
<>	135:176b8275d35d	253
<>	135:176b8275d35d	254	#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST \|\
<>	135:176b8275d35d	255	HRTIM_CR2_TARST \|\
<>	135:176b8275d35d	256	HRTIM_CR2_TBRST \|\
<>	135:176b8275d35d	257	HRTIM_CR2_TCRST \|\
<>	135:176b8275d35d	258	HRTIM_CR2_TDRST \|\
<>	135:176b8275d35d	259	HRTIM_CR2_TERST))
<>	135:176b8275d35d	260
<>	135:176b8275d35d	261	#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN \|\
<>	135:176b8275d35d	262	HRTIM_OENR_TA2OEN \|\
<>	135:176b8275d35d	263	HRTIM_OENR_TB1OEN \|\
<>	135:176b8275d35d	264	HRTIM_OENR_TB2OEN \|\
<>	135:176b8275d35d	265	HRTIM_OENR_TC1OEN \|\
<>	135:176b8275d35d	266	HRTIM_OENR_TC2OEN \|\
<>	135:176b8275d35d	267	HRTIM_OENR_TD1OEN \|\
<>	135:176b8275d35d	268	HRTIM_OENR_TD2OEN \|\
<>	135:176b8275d35d	269	HRTIM_OENR_TE1OEN \|\
<>	135:176b8275d35d	270	HRTIM_OENR_TE2OEN))
<>	135:176b8275d35d	271
<>	135:176b8275d35d	272	#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS \|\
<>	135:176b8275d35d	273	HRTIM_ODISR_TA2ODIS \|\
<>	135:176b8275d35d	274	HRTIM_ODISR_TB1ODIS \|\
<>	135:176b8275d35d	275	HRTIM_ODISR_TB2ODIS \|\
<>	135:176b8275d35d	276	HRTIM_ODISR_TC1ODIS \|\
<>	135:176b8275d35d	277	HRTIM_ODISR_TC2ODIS \|\
<>	135:176b8275d35d	278	HRTIM_ODISR_TD1ODIS \|\
<>	135:176b8275d35d	279	HRTIM_ODISR_TD2ODIS \|\
<>	135:176b8275d35d	280	HRTIM_ODISR_TE1ODIS \|\
<>	135:176b8275d35d	281	HRTIM_ODISR_TE2ODIS))
<>	135:176b8275d35d	282
<>	135:176b8275d35d	283	#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 \|\
<>	135:176b8275d35d	284	HRTIM_OUTR_IDLM1 \|\
<>	135:176b8275d35d	285	HRTIM_OUTR_IDLES1 \|\
<>	135:176b8275d35d	286	HRTIM_OUTR_FAULT1 \|\
<>	135:176b8275d35d	287	HRTIM_OUTR_CHP1 \|\
<>	135:176b8275d35d	288	HRTIM_OUTR_DIDL1))
<>	135:176b8275d35d	289
<>	135:176b8275d35d	290	#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC \|\
<>	135:176b8275d35d	291	HRTIM_EECR1_EE1POL \|\
<>	135:176b8275d35d	292	HRTIM_EECR1_EE1SNS \|\
<>	135:176b8275d35d	293	HRTIM_EECR1_EE1FAST))
<>	135:176b8275d35d	294
<>	135:176b8275d35d	295	#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P \|\
<>	135:176b8275d35d	296	HRTIM_FLTINR1_FLT1SRC))
<>	135:176b8275d35d	297
<>	135:176b8275d35d	298	#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC \|\
<>	135:176b8275d35d	299	HRTIM_BMCR_BMCLK \|\
<>	135:176b8275d35d	300	HRTIM_BMCR_BMOM))
<>	135:176b8275d35d	301
<>	135:176b8275d35d	302	/**
<>	135:176b8275d35d	303	* @}
<>	135:176b8275d35d	304	*/
<>	135:176b8275d35d	305
<>	135:176b8275d35d	306
<>	135:176b8275d35d	307	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	308	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	309	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	310	/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
<>	135:176b8275d35d	311	* @{
<>	135:176b8275d35d	312	*/
<>	135:176b8275d35d	313	/* TO BE COMPLETED */
<>	135:176b8275d35d	314	/**
<>	135:176b8275d35d	315	* @}
<>	135:176b8275d35d	316	*/
<>	135:176b8275d35d	317	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	318
<>	135:176b8275d35d	319	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	320	/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
<>	135:176b8275d35d	321	* @{
<>	135:176b8275d35d	322	*/
<>	135:176b8275d35d	323
<>	135:176b8275d35d	324	/** @defgroup HRTIM_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	325	* @brief Flags defines which can be used with LL_HRTIM_ReadReg function
<>	135:176b8275d35d	326	* @{
<>	135:176b8275d35d	327	*/
<>	135:176b8275d35d	328	#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
<>	135:176b8275d35d	329	#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
<>	135:176b8275d35d	330	#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
<>	135:176b8275d35d	331	#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
<>	135:176b8275d35d	332	#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
<>	135:176b8275d35d	333	#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
<>	135:176b8275d35d	334	#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
<>	135:176b8275d35d	335	#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
<>	135:176b8275d35d	336
<>	135:176b8275d35d	337	#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
<>	135:176b8275d35d	338	#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
<>	135:176b8275d35d	339	#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
<>	135:176b8275d35d	340	#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
<>	135:176b8275d35d	341	#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
<>	135:176b8275d35d	342	#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
<>	135:176b8275d35d	343	#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
<>	135:176b8275d35d	344
<>	135:176b8275d35d	345	#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
<>	135:176b8275d35d	346	#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
<>	135:176b8275d35d	347	#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
<>	135:176b8275d35d	348	#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
<>	135:176b8275d35d	349	#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
<>	135:176b8275d35d	350	#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
<>	135:176b8275d35d	351	#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
<>	135:176b8275d35d	352	#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
<>	135:176b8275d35d	353	#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
<>	135:176b8275d35d	354	#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
<>	135:176b8275d35d	355	#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
<>	135:176b8275d35d	356	#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
<>	135:176b8275d35d	357	#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
<>	135:176b8275d35d	358	#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
<>	135:176b8275d35d	359	/**
<>	135:176b8275d35d	360	* @}
<>	135:176b8275d35d	361	*/
<>	135:176b8275d35d	362
<>	135:176b8275d35d	363	/** @defgroup HRTIM_EC_IT IT Defines
<>	135:176b8275d35d	364	* @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
<>	135:176b8275d35d	365	* @{
<>	135:176b8275d35d	366	*/
<>	135:176b8275d35d	367	#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
<>	135:176b8275d35d	368	#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
<>	135:176b8275d35d	369	#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
<>	135:176b8275d35d	370	#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
<>	135:176b8275d35d	371	#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
<>	135:176b8275d35d	372	#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
<>	135:176b8275d35d	373	#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
<>	135:176b8275d35d	374	#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
<>	135:176b8275d35d	375
<>	135:176b8275d35d	376	#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
<>	135:176b8275d35d	377	#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
<>	135:176b8275d35d	378	#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
<>	135:176b8275d35d	379	#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
<>	135:176b8275d35d	380	#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
<>	135:176b8275d35d	381	#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
<>	135:176b8275d35d	382	#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
<>	135:176b8275d35d	383
<>	135:176b8275d35d	384
<>	135:176b8275d35d	385	#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
<>	135:176b8275d35d	386	#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
<>	135:176b8275d35d	387	#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
<>	135:176b8275d35d	388	#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
<>	135:176b8275d35d	389	#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
<>	135:176b8275d35d	390	#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
<>	135:176b8275d35d	391	#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
<>	135:176b8275d35d	392	#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
<>	135:176b8275d35d	393	#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
<>	135:176b8275d35d	394	#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
<>	135:176b8275d35d	395	#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
<>	135:176b8275d35d	396	#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
<>	135:176b8275d35d	397	#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
<>	135:176b8275d35d	398	#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
<>	135:176b8275d35d	399	/**
<>	135:176b8275d35d	400	* @}
<>	135:176b8275d35d	401	*/
<>	135:176b8275d35d	402
<>	135:176b8275d35d	403	/** @defgroup HRTIM_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
<>	135:176b8275d35d	404	* @{
<>	135:176b8275d35d	405	* @brief Constants defining defining the synchronization input source.
<>	135:176b8275d35d	406	*/
<>	135:176b8275d35d	407	#define LL_HRTIM_SYNCIN_SRC_NONE ((uint32_t)0x00000000U) /!< HRTIM is not synchronized and runs in standalone mode /
<>	135:176b8275d35d	408	#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /!< The HRTIM is synchronized with the on-chip timer /
<>	135:176b8275d35d	409	#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 \| HRTIM_MCR_SYNC_IN_0) /!< A positive pulse on SYNCIN input triggers the HRTIM /
<>	135:176b8275d35d	410	/**
<>	135:176b8275d35d	411	* @}
<>	135:176b8275d35d	412	*/
<>	135:176b8275d35d	413
<>	135:176b8275d35d	414	/** @defgroup HRTIM_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
<>	135:176b8275d35d	415	* @{
<>	135:176b8275d35d	416	* @brief Constants defining the source and event to be sent on the synchronization output.
<>	135:176b8275d35d	417	*/
<>	135:176b8275d35d	418	#define LL_HRTIM_SYNCOUT_SRC_MASTER_START ((uint32_t)0x00000000U) /!< A pulse is sent on the SYNCOUT output upon master timer start event /
<>	135:176b8275d35d	419	#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event/
<>	135:176b8275d35d	420	#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /!< A pulse is sent on the SYNCOUT output upon timer A start or reset events /
<>	135:176b8275d35d	421	#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 \| HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event /
<>	135:176b8275d35d	422	/**
<>	135:176b8275d35d	423	* @}
<>	135:176b8275d35d	424	*/
<>	135:176b8275d35d	425
<>	135:176b8275d35d	426	/** @defgroup HRTIM_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
<>	135:176b8275d35d	427	* @{
<>	135:176b8275d35d	428	* @brief Constants defining the routing and conditioning of the synchronization output event.
<>	135:176b8275d35d	429	*/
<>	135:176b8275d35d	430	#define LL_HRTIM_SYNCOUT_DISABLED ((uint32_t)0x00000000U) /!< Synchronization output event is disabled /
<>	135:176b8275d35d	431	#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization /
<>	135:176b8275d35d	432	#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 \| HRTIM_MCR_SYNC_OUT_0) /!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization /
<>	135:176b8275d35d	433	/**
<>	135:176b8275d35d	434	* @}
<>	135:176b8275d35d	435	*/
<>	135:176b8275d35d	436
<>	135:176b8275d35d	437	/** @defgroup HRTIM_EC_TIMER TIMER ID
<>	135:176b8275d35d	438	* @{
<>	135:176b8275d35d	439	* @brief Constants identifying a timing unit.
<>	135:176b8275d35d	440	*/
<>	135:176b8275d35d	441	#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /!< Master timer identifier /
<>	135:176b8275d35d	442	#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /!< Timer A identifier /
<>	135:176b8275d35d	443	#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /!< Timer B identifier /
<>	135:176b8275d35d	444	#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /!< Timer C identifier /
<>	135:176b8275d35d	445	#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /!< Timer D identifier /
<>	135:176b8275d35d	446	#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /!< Timer E identifier /
<>	135:176b8275d35d	447	/**
<>	135:176b8275d35d	448	* @}
<>	135:176b8275d35d	449	*/
<>	135:176b8275d35d	450
<>	135:176b8275d35d	451	/** @defgroup HRTIM_EC_OUTPUT OUTPUT ID
<>	135:176b8275d35d	452	* @{
<>	135:176b8275d35d	453	* @brief Constants identifying an HRTIM output.
<>	135:176b8275d35d	454	*/
<>	135:176b8275d35d	455	#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /!< Timer A - Output 1 identifier /
<>	135:176b8275d35d	456	#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /!< Timer A - Output 2 identifier /
<>	135:176b8275d35d	457	#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /!< Timer B - Output 1 identifier /
<>	135:176b8275d35d	458	#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /!< Timer B - Output 2 identifier /
<>	135:176b8275d35d	459	#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /!< Timer C - Output 1 identifier /
<>	135:176b8275d35d	460	#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /!< Timer C - Output 2 identifier /
<>	135:176b8275d35d	461	#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /!< Timer D - Output 1 identifier /
<>	135:176b8275d35d	462	#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /!< Timer D - Output 2 identifier /
<>	135:176b8275d35d	463	#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /!< Timer E - Output 1 identifier /
<>	135:176b8275d35d	464	#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /!< Timer E - Output 2 identifier /
<>	135:176b8275d35d	465	/**
<>	135:176b8275d35d	466	* @}
<>	135:176b8275d35d	467	*/
<>	135:176b8275d35d	468
<>	135:176b8275d35d	469	/** @defgroup HRTIM_EC_COMPAREUNIT COMPARE UNIT ID
<>	135:176b8275d35d	470	* @{
<>	135:176b8275d35d	471	* @brief Constants identifying a compare unit.
<>	135:176b8275d35d	472	*/
<>	135:176b8275d35d	473	#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /!< Compare unit 2 identifier /
<>	135:176b8275d35d	474	#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /!< Compare unit 4 identifier /
<>	135:176b8275d35d	475	/**
<>	135:176b8275d35d	476	* @}
<>	135:176b8275d35d	477	*/
<>	135:176b8275d35d	478
<>	135:176b8275d35d	479	/** @defgroup HRTIM_EC_CAPTUREUNIT CAPTURE UNIT ID
<>	135:176b8275d35d	480	* @{
<>	135:176b8275d35d	481	* @brief Constants identifying a capture unit.
<>	135:176b8275d35d	482	*/
<>	135:176b8275d35d	483	#define LL_HRTIM_CAPTUREUNIT_1 0 /!< Capture unit 1 identifier /
<>	135:176b8275d35d	484	#define LL_HRTIM_CAPTUREUNIT_2 1 /!< Capture unit 2 identifier /
<>	135:176b8275d35d	485	/**
<>	135:176b8275d35d	486	* @}
<>	135:176b8275d35d	487	*/
<>	135:176b8275d35d	488
<>	135:176b8275d35d	489	/** @defgroup HRTIM_EC_FAULT FAULT ID
<>	135:176b8275d35d	490	* @{
<>	135:176b8275d35d	491	* @brief Constants identifying a fault channel.
<>	135:176b8275d35d	492	*/
<>	135:176b8275d35d	493	#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /!< Fault channel 1 identifier /
<>	135:176b8275d35d	494	#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /!< Fault channel 2 identifier /
<>	135:176b8275d35d	495	#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /!< Fault channel 3 identifier /
<>	135:176b8275d35d	496	#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /!< Fault channel 4 identifier /
<>	135:176b8275d35d	497	#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /!< Fault channel 5 identifier /
<>	135:176b8275d35d	498	/**
<>	135:176b8275d35d	499	* @}
<>	135:176b8275d35d	500	*/
<>	135:176b8275d35d	501
<>	135:176b8275d35d	502	/** @defgroup HRTIM_EC_EVENT EXTERNAL EVENT ID
<>	135:176b8275d35d	503	* @{
<>	135:176b8275d35d	504	* @brief Constants identifying an external event channel.
<>	135:176b8275d35d	505	*/
<>	135:176b8275d35d	506	#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /!< External event channel 1 identifier /
<>	135:176b8275d35d	507	#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /!< External event channel 2 identifier /
<>	135:176b8275d35d	508	#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /!< External event channel 3 identifier /
<>	135:176b8275d35d	509	#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /!< External event channel 4 identifier /
<>	135:176b8275d35d	510	#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /!< External event channel 5 identifier /
<>	135:176b8275d35d	511	#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /!< External event channel 6 identifier /
<>	135:176b8275d35d	512	#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /!< External event channel 7 identifier /
<>	135:176b8275d35d	513	#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /!< External event channel 8 identifier /
<>	135:176b8275d35d	514	#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /!< External event channel 9 identifier /
<>	135:176b8275d35d	515	#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /!< External event channel 10 identifier /
<>	135:176b8275d35d	516	/**
<>	135:176b8275d35d	517	* @}
<>	135:176b8275d35d	518	*/
<>	135:176b8275d35d	519
<>	135:176b8275d35d	520	/** @defgroup HRTIM_EC_OUTPUTSTATE OUTPUT STATE
<>	135:176b8275d35d	521	* @{
<>	135:176b8275d35d	522	* @brief Constants defining the state of an HRTIM output.
<>	135:176b8275d35d	523	*/
<>	135:176b8275d35d	524	#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit /
<>	135:176b8275d35d	525	#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) /
<>	135:176b8275d35d	526	#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /!< Safety state, entered in case of a shut-down request on FAULTx inputs /
<>	135:176b8275d35d	527	/**
<>	135:176b8275d35d	528	* @}
<>	135:176b8275d35d	529	*/
<>	135:176b8275d35d	530
<>	135:176b8275d35d	531	/** @defgroup HRTIM_EC_ADCTRIG ADC TRIGGER
<>	135:176b8275d35d	532	* @{
<>	135:176b8275d35d	533	* @brief Constants identifying an ADC trigger.
<>	135:176b8275d35d	534	*/
<>	135:176b8275d35d	535	#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /!< ADC trigger 1 identifier /
<>	135:176b8275d35d	536	#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /!< ADC trigger 2 identifier /
<>	135:176b8275d35d	537	#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /!< ADC trigger 3 identifier /
<>	135:176b8275d35d	538	#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /!< ADC trigger 4 identifier /
<>	135:176b8275d35d	539	/**
<>	135:176b8275d35d	540	* @}
<>	135:176b8275d35d	541	*/
<>	135:176b8275d35d	542
<>	135:176b8275d35d	543	/** @defgroup HRTIM_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
<>	135:176b8275d35d	544	* @{
<>	135:176b8275d35d	545	* @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
<>	135:176b8275d35d	546	*/
<>	135:176b8275d35d	547	#define LL_HRTIM_ADCTRIG_UPDATE_MASTER ((uint32_t)0x00000000U) /!< HRTIM_ADCxR register update is triggered by the Master timer /
<>	135:176b8275d35d	548	#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /!< HRTIM_ADCxR register update is triggered by the Timer A /
<>	135:176b8275d35d	549	#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /!< HRTIM_ADCxR register update is triggered by the Timer B /
<>	135:176b8275d35d	550	#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 \| HRTIM_CR1_ADC1USRC_0) /!< HRTIM_ADCxR register update is triggered by the Timer C /
<>	135:176b8275d35d	551	#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /!< HRTIM_ADCxR register update is triggered by the Timer D /
<>	135:176b8275d35d	552	#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 \| HRTIM_CR1_ADC1USRC_0) /!< HRTIM_ADCxR register update is triggered by the Timer E /
<>	135:176b8275d35d	553	/**
<>	135:176b8275d35d	554	* @}
<>	135:176b8275d35d	555	*/
<>	135:176b8275d35d	556
<>	135:176b8275d35d	557	/** @defgroup HRTIM_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
<>	135:176b8275d35d	558	* @{
<>	135:176b8275d35d	559	* @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
<>	135:176b8275d35d	560	*/
<>	135:176b8275d35d	561	#define LL_HRTIM_ADCTRIG_SRC13_NONE ((uint32_t)0x00000000U) /!< No ADC trigger event /
<>	135:176b8275d35d	562	#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /!< ADC Trigger on master compare 1 /
<>	135:176b8275d35d	563	#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /!< ADC Trigger on master compare 2 /
<>	135:176b8275d35d	564	#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /!< ADC Trigger on master compare 3 /
<>	135:176b8275d35d	565	#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /!< ADC Trigger on master compare 4 /
<>	135:176b8275d35d	566	#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /!< ADC Trigger on master period /
<>	135:176b8275d35d	567	#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /!< ADC Trigger on external event 1 /
<>	135:176b8275d35d	568	#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /!< ADC Trigger on external event 2 /
<>	135:176b8275d35d	569	#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /!< ADC Trigger on external event 3 /
<>	135:176b8275d35d	570	#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /!< ADC Trigger on external event 4 /
<>	135:176b8275d35d	571	#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /!< ADC Trigger on external event 5 /
<>	135:176b8275d35d	572	#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /!< ADC Trigger on Timer A compare 2 /
<>	135:176b8275d35d	573	#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /!< ADC Trigger on Timer A compare 3 /
<>	135:176b8275d35d	574	#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /!< ADC Trigger on Timer A compare 4 /
<>	135:176b8275d35d	575	#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /!< ADC Trigger on Timer A period /
<>	135:176b8275d35d	576	#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /!< ADC Trigger on Timer A reset /
<>	135:176b8275d35d	577	#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /!< ADC Trigger on Timer B compare 2 /
<>	135:176b8275d35d	578	#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /!< ADC Trigger on Timer B compare 3 /
<>	135:176b8275d35d	579	#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /!< ADC Trigger on Timer B compare 4 /
<>	135:176b8275d35d	580	#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /!< ADC Trigger on Timer B period /
<>	135:176b8275d35d	581	#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /!< ADC Trigger on Timer B reset /
<>	135:176b8275d35d	582	#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /!< ADC Trigger on Timer C compare 2 /
<>	135:176b8275d35d	583	#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /!< ADC Trigger on Timer C compare 3 /
<>	135:176b8275d35d	584	#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /!< ADC Trigger on Timer C compare 4 /
<>	135:176b8275d35d	585	#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /!< ADC Trigger on Timer C period /
<>	135:176b8275d35d	586	#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /!< ADC Trigger on Timer D compare 2 /
<>	135:176b8275d35d	587	#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /!< ADC Trigger on Timer D compare 3 /
<>	135:176b8275d35d	588	#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /!< ADC Trigger on Timer D compare 4 /
<>	135:176b8275d35d	589	#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /!< ADC Trigger on Timer D period /
<>	135:176b8275d35d	590	#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /!< ADC Trigger on Timer E compare 2 /
<>	135:176b8275d35d	591	#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /!< ADC Trigger on Timer E compare 3 /
<>	135:176b8275d35d	592	#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /!< ADC Trigger on Timer E compare 4 /
<>	135:176b8275d35d	593	#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /!< ADC Trigger on Timer E period /
<>	135:176b8275d35d	594	/**
<>	135:176b8275d35d	595	* @}
<>	135:176b8275d35d	596	*/
<>	135:176b8275d35d	597
<>	135:176b8275d35d	598	/** @defgroup HRTIM_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
<>	135:176b8275d35d	599	* @{
<>	135:176b8275d35d	600	* @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
<>	135:176b8275d35d	601	*/
<>	135:176b8275d35d	602	#define LL_HRTIM_ADCTRIG_SRC24_NONE ((uint32_t)0x00000000U)/!< No ADC trigger event /
<>	135:176b8275d35d	603	#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /!< ADC Trigger on master compare 1 /
<>	135:176b8275d35d	604	#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /!< ADC Trigger on master compare 2 /
<>	135:176b8275d35d	605	#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /!< ADC Trigger on master compare 3 /
<>	135:176b8275d35d	606	#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /!< ADC Trigger on master compare 4 /
<>	135:176b8275d35d	607	#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /!< ADC Trigger on master period /
<>	135:176b8275d35d	608	#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /!< ADC Trigger on external event 6 /
<>	135:176b8275d35d	609	#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /!< ADC Trigger on external event 7 /
<>	135:176b8275d35d	610	#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /!< ADC Trigger on external event 8 /
<>	135:176b8275d35d	611	#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /!< ADC Trigger on external event 9 /
<>	135:176b8275d35d	612	#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /!< ADC Trigger on external event 10 /
<>	135:176b8275d35d	613	#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /!< ADC Trigger on Timer A compare 2 /
<>	135:176b8275d35d	614	#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /!< ADC Trigger on Timer A compare 3 /
<>	135:176b8275d35d	615	#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /!< ADC Trigger on Timer A compare 4 /
<>	135:176b8275d35d	616	#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /!< ADC Trigger on Timer A period /
<>	135:176b8275d35d	617	#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /!< ADC Trigger on Timer B compare 2 /
<>	135:176b8275d35d	618	#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /!< ADC Trigger on Timer B compare 3 /
<>	135:176b8275d35d	619	#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /!< ADC Trigger on Timer B compare 4 /
<>	135:176b8275d35d	620	#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /!< ADC Trigger on Timer B period /
<>	135:176b8275d35d	621	#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /!< ADC Trigger on Timer C compare 2 /
<>	135:176b8275d35d	622	#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /!< ADC Trigger on Timer C compare 3 /
<>	135:176b8275d35d	623	#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /!< ADC Trigger on Timer C compare 4 /
<>	135:176b8275d35d	624	#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /!< ADC Trigger on Timer C period /
<>	135:176b8275d35d	625	#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /!< ADC Trigger on Timer C reset /
<>	135:176b8275d35d	626	#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /!< ADC Trigger on Timer D compare 2 /
<>	135:176b8275d35d	627	#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /!< ADC Trigger on Timer D compare 3 /
<>	135:176b8275d35d	628	#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /!< ADC Trigger on Timer D compare 4 /
<>	135:176b8275d35d	629	#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /!< ADC Trigger on Timer D period /
<>	135:176b8275d35d	630	#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /!< ADC Trigger on Timer D reset /
<>	135:176b8275d35d	631	#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /!< ADC Trigger on Timer E compare 2 /
<>	135:176b8275d35d	632	#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /!< ADC Trigger on Timer E compare 3 /
<>	135:176b8275d35d	633	#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /!< ADC Trigger on Timer E compare 4 /
<>	135:176b8275d35d	634	#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /!< ADC Trigger on Timer E reset /
<>	135:176b8275d35d	635	/**
<>	135:176b8275d35d	636	* @}
<>	135:176b8275d35d	637	*/
<>	135:176b8275d35d	638
<>	135:176b8275d35d	639	/** @defgroup HRTIM_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
<>	135:176b8275d35d	640	* @{
<>	135:176b8275d35d	641	* @brief Constants defining the DLL calibration mode.
<>	135:176b8275d35d	642	*/
<>	135:176b8275d35d	643	#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT ((uint32_t)0x00000000U)/!<Calibration is perfomed only once /
<>	135:176b8275d35d	644	#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /!<Calibration is performed periodically /
<>	135:176b8275d35d	645	/**
<>	135:176b8275d35d	646	* @}
<>	135:176b8275d35d	647	*/
<>	135:176b8275d35d	648
<>	135:176b8275d35d	649	/** @defgroup HRTIM_EC_CALIBRATIONRATE DLL CALIBRATION RATE
<>	135:176b8275d35d	650	* @{
<>	135:176b8275d35d	651	* @brief Constants defining the DLL calibration periods (in micro seconds).
<>	135:176b8275d35d	652	*/
<>	135:176b8275d35d	653	#define LL_HRTIM_DLLCALIBRATION_RATE_7300 ((uint32_t)0x00000000U) /!< Periodic DLL calibration: T = 1048576 tHRTIM (7.3 ms) */
<>	135:176b8275d35d	654	#define LL_HRTIM_DLLCALIBRATION_RATE_910 (HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 131072 tHRTIM (910 ms) */
<>	135:176b8275d35d	655	#define LL_HRTIM_DLLCALIBRATION_RATE_114 (HRTIM_DLLCR_CALRTE_1) /!< Periodic DLL calibration: T = 16384 tHRTIM (114 ms) */
<>	135:176b8275d35d	656	#define LL_HRTIM_DLLCALIBRATION_RATE_14 (HRTIM_DLLCR_CALRTE_1 \| HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 2048 tHRTIM (14 ms) */
<>	135:176b8275d35d	657	/**
<>	135:176b8275d35d	658	* @}
<>	135:176b8275d35d	659	*/
<>	135:176b8275d35d	660
<>	135:176b8275d35d	661	/** @defgroup HRTIM_EC_PRESCALERRATIO PRESCALER RATIO
<>	135:176b8275d35d	662	* @{
<>	135:176b8275d35d	663	* @brief Constants defining timer high-resolution clock prescaler ratio.
<>	135:176b8275d35d	664	*/
<>	135:176b8275d35d	665	#define LL_HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U) /!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	666	#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	667	#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	668	#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	669	#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	670	#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	671	#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) /
<>	135:176b8275d35d	672	#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) /
<>	135:176b8275d35d	673	/**
<>	135:176b8275d35d	674	* @}
<>	135:176b8275d35d	675	*/
<>	135:176b8275d35d	676
<>	135:176b8275d35d	677	/** @defgroup HRTIM_EC_MODE COUNTER MODE
<>	135:176b8275d35d	678	* @{
<>	135:176b8275d35d	679	* @brief Constants defining timer counter operating mode.
<>	135:176b8275d35d	680	*/
<>	135:176b8275d35d	681	#define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /!< The timer operates in continuous (free-running) mode /
<>	135:176b8275d35d	682	#define LL_HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /!< The timer operates in non retriggerable single-shot mode /
<>	135:176b8275d35d	683	#define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /!< The timer operates in retriggerable single-shot mode /
<>	135:176b8275d35d	684	/**
<>	135:176b8275d35d	685	* @}
<>	135:176b8275d35d	686	*/
<>	135:176b8275d35d	687
<>	135:176b8275d35d	688	/** @defgroup HRTIM_EC_DACTRIG DAC TRIGGER
<>	135:176b8275d35d	689	* @{
<>	135:176b8275d35d	690	* @brief Constants defining on which output the DAC synchronization event is sent.
<>	135:176b8275d35d	691	*/
<>	135:176b8275d35d	692	#define LL_HRTIM_DACTRIG_NONE ((uint32_t)0x00000000U) /!< No DAC synchronization event generated /
<>	135:176b8275d35d	693	#define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut1 output upon timer update /
<>	135:176b8275d35d	694	#define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /!< DAC synchronization event generated on DACTrigOut2 output upon timer update /
<>	135:176b8275d35d	695	#define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 \| HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut3 output upon timer update /
<>	135:176b8275d35d	696	/**
<>	135:176b8275d35d	697	* @}
<>	135:176b8275d35d	698	*/
<>	135:176b8275d35d	699
<>	135:176b8275d35d	700	/** @defgroup HRTIM_EC_UPDATETRIG UPDATE TRIGGER
<>	135:176b8275d35d	701	* @{
<>	135:176b8275d35d	702	* @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
<>	135:176b8275d35d	703	*/
<>	135:176b8275d35d	704	#define LL_HRTIM_UPDATETRIG_NONE ((uint32_t)0x00000000U)/!< Register update is disabled /
<>	135:176b8275d35d	705	#define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /!< Register update is triggered by the master timer update /
<>	135:176b8275d35d	706	#define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /!< Register update is triggered by the timer A update /
<>	135:176b8275d35d	707	#define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /!< Register update is triggered by the timer B update /
<>	135:176b8275d35d	708	#define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /!< Register update is triggered by the timer C update/
<>	135:176b8275d35d	709	#define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /!< Register update is triggered by the timer D update /
<>	135:176b8275d35d	710	#define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /!< Register update is triggered by the timer E update /
<>	135:176b8275d35d	711	#define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0/
<>	135:176b8275d35d	712	#define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode /
<>	135:176b8275d35d	713	/**
<>	135:176b8275d35d	714	* @}
<>	135:176b8275d35d	715	*/
<>	135:176b8275d35d	716
<>	135:176b8275d35d	717	/** @defgroup HRTIM_EC_UPDATEGATING UPDATE GATING
<>	135:176b8275d35d	718	* @{
<>	135:176b8275d35d	719	* @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
<>	135:176b8275d35d	720	*/
<>	135:176b8275d35d	721	#define LL_HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U) /!< Update done independently from the DMA burst transfer completion /
<>	135:176b8275d35d	722	#define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /!< Update done when the DMA burst transfer is completed /
<>	135:176b8275d35d	723	#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /!< Update done on timer roll-over following a DMA burst transfer completion/
<>	135:176b8275d35d	724	#define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 /
<>	135:176b8275d35d	725	#define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 /
<>	135:176b8275d35d	726	#define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 /
<>	135:176b8275d35d	727	#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 /
<>	135:176b8275d35d	728	#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 /
<>	135:176b8275d35d	729	#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 /
<>	135:176b8275d35d	730	/**
<>	135:176b8275d35d	731	* @}
<>	135:176b8275d35d	732	*/
<>	135:176b8275d35d	733
<>	135:176b8275d35d	734	/** @defgroup HRTIM_EC_COMPAREMODE COMPARE MODE
<>	135:176b8275d35d	735	* @{
<>	135:176b8275d35d	736	* @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
<>	135:176b8275d35d	737	*/
<>	135:176b8275d35d	738	#define LL_HRTIM_COMPAREMODE_REGULAR ((uint32_t)0x00000000U) /!< standard compare mode /
<>	135:176b8275d35d	739	#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated only if a capture has occurred /
<>	135:176b8275d35d	740	#define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) /
<>	135:176b8275d35d	741	#define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 \| HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) /
<>	135:176b8275d35d	742	/**
<>	135:176b8275d35d	743	* @}
<>	135:176b8275d35d	744	*/
<>	135:176b8275d35d	745
<>	135:176b8275d35d	746	/** @defgroup HRTIM_EC_RESETTRIG RESET TRIGGER
<>	135:176b8275d35d	747	* @{
<>	135:176b8275d35d	748	* @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
<>	135:176b8275d35d	749	*/
<>	135:176b8275d35d	750	#define LL_HRTIM_RESETTRIG_NONE ((uint32_t)0x00000000U)/!< No counter reset trigger /
<>	135:176b8275d35d	751	#define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /!< The timer counter is reset upon update event /
<>	135:176b8275d35d	752	#define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /!< The timer counter is reset upon Timer Compare 2 event /
<>	135:176b8275d35d	753	#define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /!< The timer counter is reset upon Timer Compare 4 event /
<>	135:176b8275d35d	754	#define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /!< The timer counter is reset upon master timer period event /
<>	135:176b8275d35d	755	#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /!< The timer counter is reset upon master timer Compare 1 event /
<>	135:176b8275d35d	756	#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /!< The timer counter is reset upon master timer Compare 2 event /
<>	135:176b8275d35d	757	#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /!< The timer counter is reset upon master timer Compare 3 event /
<>	135:176b8275d35d	758	#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /!< The timer counter is reset upon master timer Compare 4 event /
<>	135:176b8275d35d	759	#define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /!< The timer counter is reset upon external event 1 /
<>	135:176b8275d35d	760	#define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /!< The timer counter is reset upon external event 2 /
<>	135:176b8275d35d	761	#define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /!< The timer counter is reset upon external event 3 /
<>	135:176b8275d35d	762	#define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /!< The timer counter is reset upon external event 4 /
<>	135:176b8275d35d	763	#define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /!< The timer counter is reset upon external event 5 /
<>	135:176b8275d35d	764	#define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /!< The timer counter is reset upon external event 6 /
<>	135:176b8275d35d	765	#define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /!< The timer counter is reset upon external event 7 /
<>	135:176b8275d35d	766	#define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /!< The timer counter is reset upon external event 8 /
<>	135:176b8275d35d	767	#define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /!< The timer counter is reset upon external event 9 /
<>	135:176b8275d35d	768	#define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /!< The timer counter is reset upon external event 10 /
<>	135:176b8275d35d	769	#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /!< The timer counter is reset upon other timer Compare 1 event /
<>	135:176b8275d35d	770	#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /!< The timer counter is reset upon other timer Compare 2 event /
<>	135:176b8275d35d	771	#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /!< The timer counter is reset upon other timer Compare 4 event /
<>	135:176b8275d35d	772	#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /!< The timer counter is reset upon other timer Compare 1 event /
<>	135:176b8275d35d	773	#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /!< The timer counter is reset upon other timer Compare 2 event /
<>	135:176b8275d35d	774	#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /!< The timer counter is reset upon other timer Compare 4 event /
<>	135:176b8275d35d	775	#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /!< The timer counter is reset upon other timer Compare 1 event /
<>	135:176b8275d35d	776	#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /!< The timer counter is reset upon other timer Compare 2 event /
<>	135:176b8275d35d	777	#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /!< The timer counter is reset upon other timer Compare 4 event /
<>	135:176b8275d35d	778	#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /!< The timer counter is reset upon other timer Compare 1 event /
<>	135:176b8275d35d	779	#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /!< The timer counter is reset upon other timer Compare 2 event /
<>	135:176b8275d35d	780	#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /!< The timer counter is reset upon other timer Compare 4 event /
<>	135:176b8275d35d	781	/**
<>	135:176b8275d35d	782	* @}
<>	135:176b8275d35d	783	*/
<>	135:176b8275d35d	784
<>	135:176b8275d35d	785	/** @defgroup HRTIM_EC_CAPTURETRIG CAPTURE TRIGGER
<>	135:176b8275d35d	786	* @{
<>	135:176b8275d35d	787	* @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
<>	135:176b8275d35d	788	*/
<>	135:176b8275d35d	789	#define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/!< Capture trigger is disabled /
<>	135:176b8275d35d	790	#define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /!< The update event triggers the Capture /
<>	135:176b8275d35d	791	#define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /!< The External event 1 triggers the Capture /
<>	135:176b8275d35d	792	#define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /!< The External event 2 triggers the Capture /
<>	135:176b8275d35d	793	#define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /!< The External event 3 triggers the Capture /
<>	135:176b8275d35d	794	#define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /!< The External event 4 triggers the Capture /
<>	135:176b8275d35d	795	#define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /!< The External event 5 triggers the Capture /
<>	135:176b8275d35d	796	#define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /!< The External event 6 triggers the Capture /
<>	135:176b8275d35d	797	#define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /!< The External event 7 triggers the Capture /
<>	135:176b8275d35d	798	#define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /!< The External event 8 triggers the Capture /
<>	135:176b8275d35d	799	#define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /!< The External event 9 triggers the Capture /
<>	135:176b8275d35d	800	#define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /!< The External event 10 triggers the Capture /
<>	135:176b8275d35d	801	#define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /!< Capture is triggered by TA1 output inactive to active transition /
<>	135:176b8275d35d	802	#define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /!< Capture is triggered by TA1 output active to inactive transition /
<>	135:176b8275d35d	803	#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /!< Timer A Compare 1 triggers Capture /
<>	135:176b8275d35d	804	#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /!< Timer A Compare 2 triggers Capture /
<>	135:176b8275d35d	805	#define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /!< Capture is triggered by TB1 output inactive to active transition /
<>	135:176b8275d35d	806	#define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /!< Capture is triggered by TB1 output active to inactive transition /
<>	135:176b8275d35d	807	#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /!< Timer B Compare 1 triggers Capture /
<>	135:176b8275d35d	808	#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /!< Timer B Compare 2 triggers Capture /
<>	135:176b8275d35d	809	#define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /!< Capture is triggered by TC1 output inactive to active transition /
<>	135:176b8275d35d	810	#define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /!< Capture is triggered by TC1 output active to inactive transition /
<>	135:176b8275d35d	811	#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /!< Timer C Compare 1 triggers Capture /
<>	135:176b8275d35d	812	#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /!< Timer C Compare 2 triggers Capture /
<>	135:176b8275d35d	813	#define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /!< Capture is triggered by TD1 output inactive to active transition /
<>	135:176b8275d35d	814	#define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /!< Capture is triggered by TD1 output active to inactive transition /
<>	135:176b8275d35d	815	#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /!< Timer D Compare 1 triggers Capture /
<>	135:176b8275d35d	816	#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /!< Timer D Compare 2 triggers Capture /
<>	135:176b8275d35d	817	#define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /!< Capture is triggered by TE1 output inactive to active transition /
<>	135:176b8275d35d	818	#define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /!< Capture is triggered by TE1 output active to inactive transition /
<>	135:176b8275d35d	819	#define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /!< Timer E Compare 1 triggers Capture /
<>	135:176b8275d35d	820	#define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /!< Timer E Compare 2 triggers Capture /
<>	135:176b8275d35d	821	/**
<>	135:176b8275d35d	822	* @}
<>	135:176b8275d35d	823	*/
<>	135:176b8275d35d	824
<>	135:176b8275d35d	825	/** @defgroup HRTIM_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
<>	135:176b8275d35d	826	* @{
<>	135:176b8275d35d	827	* @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
<>	135:176b8275d35d	828	*/
<>	135:176b8275d35d	829	#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 ((uint32_t)0x00000000U) /!< Timers A, B, C: Output 1 delayed Idle on external Event 6 /
<>	135:176b8275d35d	830	#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /!< Timers A, B, C: Output 2 delayed Idle on external Event 6 /
<>	135:176b8275d35d	831	#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 /
<>	135:176b8275d35d	832	#define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0) /!< Timers A, B, C: Balanced Idle on external Event 6 /
<>	135:176b8275d35d	833	#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /!< Timers A, B, C: Output 1 delayed Idle on external Event 7 /
<>	135:176b8275d35d	834	#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0) /!< Timers A, B, C: Output 2 delayed Idle on external Event 7 /
<>	135:176b8275d35d	835	#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1) /!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 /
<>	135:176b8275d35d	836	#define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0) /!< Timers A, B, C: Balanced Idle on external Event 7 /
<>	135:176b8275d35d	837
<>	135:176b8275d35d	838	#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 ((uint32_t)0x00000000U) /!< Timers D, E: Output 1 delayed Idle on external Event 8 /
<>	135:176b8275d35d	839	#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /!< Timers D, E: Output 2 delayed Idle on external Event 8 /
<>	135:176b8275d35d	840	#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 /
<>	135:176b8275d35d	841	#define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0) /!< Timers D, E: Balanced Idle on external Event 8 /
<>	135:176b8275d35d	842	#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /!< Timers D, E: Output 1 delayed Idle on external Event 9 /
<>	135:176b8275d35d	843	#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0) /!< Timers D, E: Output 2 delayed Idle on external Event 9 /
<>	135:176b8275d35d	844	#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1) /!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 /
<>	135:176b8275d35d	845	#define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0) /!< Timers D, E: Balanced Idle on external Event 9 /
<>	135:176b8275d35d	846	/**
<>	135:176b8275d35d	847	* @}
<>	135:176b8275d35d	848	*/
<>	135:176b8275d35d	849
<>	135:176b8275d35d	850	/** @defgroup HRTIM_EC_BURSTMODE BURST MODE
<>	135:176b8275d35d	851	* @{
<>	135:176b8275d35d	852	* @brief Constants defining how the timer behaves during a burst mode operation.
<>	135:176b8275d35d	853	*/
<>	135:176b8275d35d	854	#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /!< Timer counter clock is maintained and the timer operates normally /
<>	135:176b8275d35d	855	#define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /!< Timer counter clock is stopped and the counter is reset /
<>	135:176b8275d35d	856	/**
<>	135:176b8275d35d	857	* @}
<>	135:176b8275d35d	858	*/
<>	135:176b8275d35d	859
<>	135:176b8275d35d	860	/** @defgroup HRTIM_EC_BURSTDMA BURST DMA
<>	135:176b8275d35d	861	* @{
<>	135:176b8275d35d	862	* @brief Constants defining the registers that can be written during a burst DMA operation.
<>	135:176b8275d35d	863	*/
<>	135:176b8275d35d	864	#define LL_HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U) /!< No register is updated by Burst DMA accesses /
<>	135:176b8275d35d	865
<>	135:176b8275d35d	866	#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /!< MCR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	867	#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /!< MICR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	868	#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /!< MDIER register is updated by Burst DMA accesses /
<>	135:176b8275d35d	869	#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /!< MCNTR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	870	#define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /!< MPER register is updated by Burst DMA accesses /
<>	135:176b8275d35d	871	#define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /!< MREPR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	872	#define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /!< MCMP1R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	873	#define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /!< MCMP2R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	874	#define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /!< MCMP3R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	875	#define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /!< MCMP4R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	876
<>	135:176b8275d35d	877	#define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /!< TIMxCR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	878	#define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /!< TIMxICR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	879	#define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /!< TIMxDIER register is updated by Burst DMA accesses /
<>	135:176b8275d35d	880	#define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /!< CNTxCR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	881	#define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /!< PERxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	882	#define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /!< REPxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	883	#define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /!< CMP1xR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	884	#define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /!< CMP2xR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	885	#define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /!< CMP3xR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	886	#define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /!< CMP4xR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	887	#define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /!< DTxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	888	#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /!< SET1R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	889	#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /!< RST1R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	890	#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /!< SET2R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	891	#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /!< RST1R register is updated by Burst DMA accesses /
<>	135:176b8275d35d	892	#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /!< EEFxR1 register is updated by Burst DMA accesses /
<>	135:176b8275d35d	893	#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /!< EEFxR2 register is updated by Burst DMA accesses /
<>	135:176b8275d35d	894	#define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /!< RSTxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	895	#define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /!< CHPxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	896	#define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /!< OUTxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	897	#define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /!< FLTxR register is updated by Burst DMA accesses /
<>	135:176b8275d35d	898	/**
<>	135:176b8275d35d	899	* @}
<>	135:176b8275d35d	900	*/
<>	135:176b8275d35d	901
<>	135:176b8275d35d	902	/** @defgroup HRTIM_EC_CPPSTAT CURRENT PUSH-PULL STATUS
<>	135:176b8275d35d	903	* @{
<>	135:176b8275d35d	904	* @brief Constants defining on which output the signal is currently applied in push-pull mode.
<>	135:176b8275d35d	905	*/
<>	135:176b8275d35d	906	#define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /!< Signal applied on output 1 and output 2 forced inactive /
<>	135:176b8275d35d	907	#define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /!< Signal applied on output 2 and output 1 forced inactive /
<>	135:176b8275d35d	908	/**
<>	135:176b8275d35d	909	* @}
<>	135:176b8275d35d	910	*/
<>	135:176b8275d35d	911
<>	135:176b8275d35d	912	/** @defgroup HRTIM_EC_IPPSTAT IDLE PUSH-PULL STATUS
<>	135:176b8275d35d	913	* @{
<>	135:176b8275d35d	914	* @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
<>	135:176b8275d35d	915	*/
<>	135:176b8275d35d	916	#define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /!< Protection occurred when the output 1 was active and output 2 forced inactive /
<>	135:176b8275d35d	917	#define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /!< Protection occurred when the output 2 was active and output 1 forced inactive /
<>	135:176b8275d35d	918	/**
<>	135:176b8275d35d	919	* @}
<>	135:176b8275d35d	920	*/
<>	135:176b8275d35d	921
<>	135:176b8275d35d	922	/** @defgroup HRTIM_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
<>	135:176b8275d35d	923	* @{
<>	135:176b8275d35d	924	* @brief Constants defining the event filtering applied to external events by a timer.
<>	135:176b8275d35d	925	*/
<>	135:176b8275d35d	926	#define LL_HRTIM_EEFLTR_NONE ((uint32_t)0x00000000U)
<>	135:176b8275d35d	927	#define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 1 /
<>	135:176b8275d35d	928	#define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from counter reset/roll-over to Compare 2 /
<>	135:176b8275d35d	929	#define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 3 /
<>	135:176b8275d35d	930	#define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from counter reset/roll-over to Compare 4 /
<>	135:176b8275d35d	931	#define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR1 source /
<>	135:176b8275d35d	932	#define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR2 source /
<>	135:176b8275d35d	933	#define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR3 source /
<>	135:176b8275d35d	934	#define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /!< Blanking from another timing unit: TIMFLTR4 source /
<>	135:176b8275d35d	935	#define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR5 source /
<>	135:176b8275d35d	936	#define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR6 source /
<>	135:176b8275d35d	937	#define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR7 source /
<>	135:176b8275d35d	938	#define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from another timing unit: TIMFLTR8 source /
<>	135:176b8275d35d	939	#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from counter reset/roll-over to Compare 2 /
<>	135:176b8275d35d	940	#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Windowing from counter reset/roll-over to Compare 3 /
<>	135:176b8275d35d	941	#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from another timing unit: TIMWIN source /
<>	135:176b8275d35d	942	/**
<>	135:176b8275d35d	943	* @}
<>	135:176b8275d35d	944	*/
<>	135:176b8275d35d	945
<>	135:176b8275d35d	946	/** @defgroup HRTIM_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
<>	135:176b8275d35d	947	* @{
<>	135:176b8275d35d	948	* @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
<>	135:176b8275d35d	949	*/
<>	135:176b8275d35d	950	#define LL_HRTIM_EELATCH_DISABLED ((uint32_t)0x00000000U) /!< Event is ignored if it happens during a blank, or passed through during a window /
<>	135:176b8275d35d	951	#define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /!< Event is latched and delayed till the end of the blanking or windowing period /
<>	135:176b8275d35d	952	/**
<>	135:176b8275d35d	953	* @}
<>	135:176b8275d35d	954	*/
<>	135:176b8275d35d	955
<>	135:176b8275d35d	956	/** @defgroup HRTIM_EC_DT_PRESCALER DEADTIME PRESCALER
<>	135:176b8275d35d	957	* @{
<>	135:176b8275d35d	958	* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
<>	135:176b8275d35d	959	*/
<>	135:176b8275d35d	960	#define LL_HRTIM_DT_PRESCALER_MUL8 ((uint32_t)0x00000000U) /!< fDTG = fHRTIM 8 */
<>	135:176b8275d35d	961	#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM 4 */
<>	135:176b8275d35d	962	#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM 2 */
<>	135:176b8275d35d	963	#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM /
<>	135:176b8275d35d	964	#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /!< fDTG = fHRTIM / 2 /
<>	135:176b8275d35d	965	#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 4 /
<>	135:176b8275d35d	966	#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM / 8 /
<>	135:176b8275d35d	967	#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 16 /
<>	135:176b8275d35d	968	/**
<>	135:176b8275d35d	969	* @}
<>	135:176b8275d35d	970	*/
<>	135:176b8275d35d	971
<>	135:176b8275d35d	972	/** @defgroup HRTIM_EC_DT_RISING_SIGN DEADTIME RISING SIGN
<>	135:176b8275d35d	973	* @{
<>	135:176b8275d35d	974	* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
<>	135:176b8275d35d	975	*/
<>	135:176b8275d35d	976	#define LL_HRTIM_DT_RISING_POSITIVE ((uint32_t)0x00000000U) /!< Positive deadtime on rising edge /
<>	135:176b8275d35d	977	#define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /!< Negative deadtime on rising edge /
<>	135:176b8275d35d	978	/**
<>	135:176b8275d35d	979	* @}
<>	135:176b8275d35d	980	*/
<>	135:176b8275d35d	981
<>	135:176b8275d35d	982	/** @defgroup HRTIM_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
<>	135:176b8275d35d	983	* @{
<>	135:176b8275d35d	984	* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
<>	135:176b8275d35d	985	*/
<>	135:176b8275d35d	986	#define LL_HRTIM_DT_FALLING_POSITIVE ((uint32_t)0x00000000U) /!< Positive deadtime on falling edge /
<>	135:176b8275d35d	987	#define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /!< Negative deadtime on falling edge /
<>	135:176b8275d35d	988	/**
<>	135:176b8275d35d	989	* @}
<>	135:176b8275d35d	990	*/
<>	135:176b8275d35d	991
<>	135:176b8275d35d	992	/** @defgroup HRTIM_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
<>	135:176b8275d35d	993	* @{
<>	135:176b8275d35d	994	* @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
<>	135:176b8275d35d	995	*/
<>	135:176b8275d35d	996	#define LL_HRTIM_CHP_PRESCALER_DIV16 ((uint32_t)0x00000000U) /!< fCHPFRQ = fHRTIM / 16 /
<>	135:176b8275d35d	997	#define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 32 /
<>	135:176b8275d35d	998	#define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 48 /
<>	135:176b8275d35d	999	#define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 64 /
<>	135:176b8275d35d	1000	#define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 80 /
<>	135:176b8275d35d	1001	#define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 96 /
<>	135:176b8275d35d	1002	#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 112 /
<>	135:176b8275d35d	1003	#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 128 /
<>	135:176b8275d35d	1004	#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /!< fCHPFRQ = fHRTIM / 144 /
<>	135:176b8275d35d	1005	#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 160 /
<>	135:176b8275d35d	1006	#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 176 /
<>	135:176b8275d35d	1007	#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 192 /
<>	135:176b8275d35d	1008	#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 208 /
<>	135:176b8275d35d	1009	#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 224 /
<>	135:176b8275d35d	1010	#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 240 /
<>	135:176b8275d35d	1011	#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 256 /
<>	135:176b8275d35d	1012	/**
<>	135:176b8275d35d	1013	* @}
<>	135:176b8275d35d	1014	*/
<>	135:176b8275d35d	1015
<>	135:176b8275d35d	1016	/** @defgroup HRTIM_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
<>	135:176b8275d35d	1017	* @{
<>	135:176b8275d35d	1018	* @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
<>	135:176b8275d35d	1019	*/
<>	135:176b8275d35d	1020	#define LL_HRTIM_CHP_DUTYCYCLE_0 ((uint32_t)0x00000000U) /!< Only 1st pulse is present /
<>	135:176b8275d35d	1021	#define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 12.5 % /
<>	135:176b8275d35d	1022	#define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 25 % /
<>	135:176b8275d35d	1023	#define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 37.5 % /
<>	135:176b8275d35d	1024	#define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /!< Duty cycle of the carrier signal is 50 % /
<>	135:176b8275d35d	1025	#define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 62.5 % /
<>	135:176b8275d35d	1026	#define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 75 % /
<>	135:176b8275d35d	1027	#define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 87.5 % /
<>	135:176b8275d35d	1028	/**
<>	135:176b8275d35d	1029	* @}
<>	135:176b8275d35d	1030	*/
<>	135:176b8275d35d	1031
<>	135:176b8275d35d	1032	/** @defgroup HRTIM_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
<>	135:176b8275d35d	1033	* @{
<>	135:176b8275d35d	1034	* @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
<>	135:176b8275d35d	1035	*/
<>	135:176b8275d35d	1036	#define LL_HRTIM_CHP_PULSEWIDTH_16 ((uint32_t)0x00000000U) /!< tSTPW = tHRTIM x 16 /
<>	135:176b8275d35d	1037	#define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 32 /
<>	135:176b8275d35d	1038	#define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 48 /
<>	135:176b8275d35d	1039	#define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 64 /
<>	135:176b8275d35d	1040	#define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 80 /
<>	135:176b8275d35d	1041	#define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 96 /
<>	135:176b8275d35d	1042	#define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 112 /
<>	135:176b8275d35d	1043	#define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 128 /
<>	135:176b8275d35d	1044	#define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /!< tSTPW = tHRTIM x 144 /
<>	135:176b8275d35d	1045	#define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 160 /
<>	135:176b8275d35d	1046	#define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 176 /
<>	135:176b8275d35d	1047	#define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 192 /
<>	135:176b8275d35d	1048	#define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 208 /
<>	135:176b8275d35d	1049	#define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 224 /
<>	135:176b8275d35d	1050	#define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 240 /
<>	135:176b8275d35d	1051	#define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 256 /
<>	135:176b8275d35d	1052	/**
<>	135:176b8275d35d	1053	* @}
<>	135:176b8275d35d	1054	*/
<>	135:176b8275d35d	1055
<>	135:176b8275d35d	1056	/** @defgroup HRTIM_EC_CROSSBAR_INPUT CROSSBAR INPUT
<>	135:176b8275d35d	1057	* @{
<>	135:176b8275d35d	1058	* @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
<>	135:176b8275d35d	1059	*/
<>	135:176b8275d35d	1060	#define LL_HRTIM_CROSSBAR_NONE ((uint32_t)0x00000000U) /!< Reset the output set crossbar /
<>	135:176b8275d35d	1061	#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces an output level transision /
<>	135:176b8275d35d	1062	#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /!< Timer period event forces an output level transision /
<>	135:176b8275d35d	1063	#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /!< Timer compare 1 event forces an output level transision /
<>	135:176b8275d35d	1064	#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /!< Timer compare 2 event forces an output level transision /
<>	135:176b8275d35d	1065	#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /!< Timer compare 3 event forces an output level transision /
<>	135:176b8275d35d	1066	#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /!< Timer compare 4 event forces an output level transision /
<>	135:176b8275d35d	1067	#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /!< The master timer period event forces an output level transision /
<>	135:176b8275d35d	1068	#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /!< Master Timer compare 1 event forces an output level transision /
<>	135:176b8275d35d	1069	#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /!< Master Timer compare 2 event forces an output level transision /
<>	135:176b8275d35d	1070	#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /!< Master Timer compare 3 event forces an output level transision /
<>	135:176b8275d35d	1071	#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /!< Master Timer compare 4 event forces an output level transision /
<>	135:176b8275d35d	1072	#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces an output level transision /
<>	135:176b8275d35d	1073	#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces an output level transision /
<>	135:176b8275d35d	1074	#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces an output level transision /
<>	135:176b8275d35d	1075	#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces an output level transision /
<>	135:176b8275d35d	1076	#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces an output level transision /
<>	135:176b8275d35d	1077	#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces an output level transision /
<>	135:176b8275d35d	1078	#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces an output level transision /
<>	135:176b8275d35d	1079	#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces an output level transision /
<>	135:176b8275d35d	1080	#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces an output level transision /
<>	135:176b8275d35d	1081	#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /!< External event 1 forces an output level transision /
<>	135:176b8275d35d	1082	#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /!< External event 2 forces an output level transision /
<>	135:176b8275d35d	1083	#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /!< External event 3 forces an output level transision /
<>	135:176b8275d35d	1084	#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /!< External event 4 forces an output level transision /
<>	135:176b8275d35d	1085	#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /!< External event 5 forces an output level transision /
<>	135:176b8275d35d	1086	#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /!< External event 6 forces an output level transision /
<>	135:176b8275d35d	1087	#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /!< External event 7 forces an output level transision /
<>	135:176b8275d35d	1088	#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /!< External event 8 forces an output level transision /
<>	135:176b8275d35d	1089	#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /!< External event 9 forces an output level transision /
<>	135:176b8275d35d	1090	#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /!< External event 10 forces an output level transision /
<>	135:176b8275d35d	1091	#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /!< Timer register update event forces an output level transision /
<>	135:176b8275d35d	1092	/**
<>	135:176b8275d35d	1093	* @}
<>	135:176b8275d35d	1094	*/
<>	135:176b8275d35d	1095
<>	135:176b8275d35d	1096	/** @defgroup HRTIM_EC_OUT_POLARITY OUPUT_POLARITY
<>	135:176b8275d35d	1097	* @{
<>	135:176b8275d35d	1098	* @brief Constants defining the polarity of a timer output.
<>	135:176b8275d35d	1099	*/
<>	135:176b8275d35d	1100	#define LL_HRTIM_OUT_POSITIVE_POLARITY ((uint32_t)0x00000000U) /!< Output is acitve HIGH /
<>	135:176b8275d35d	1101	#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /!< Output is active LOW /
<>	135:176b8275d35d	1102	/**
<>	135:176b8275d35d	1103	* @}
<>	135:176b8275d35d	1104	*/
<>	135:176b8275d35d	1105
<>	135:176b8275d35d	1106	/** @defgroup HRTIM_EC_OUT_IDLEMODE OUTPUT IDLE MODE
<>	135:176b8275d35d	1107	* @{
<>	135:176b8275d35d	1108	* @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
<>	135:176b8275d35d	1109	*/
<>	135:176b8275d35d	1110	#define LL_HRTIM_OUT_NO_IDLE ((uint32_t)0x00000000U)/!< The output is not affected by the burst mode operation /
<>	135:176b8275d35d	1111	#define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /!< The output is in idle state when requested by the burst mode controller /
<>	135:176b8275d35d	1112	/**
<>	135:176b8275d35d	1113	* @}
<>	135:176b8275d35d	1114	*/
<>	135:176b8275d35d	1115
<>	135:176b8275d35d	1116	/** @defgroup HRTIM_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
<>	135:176b8275d35d	1117	* @{
<>	135:176b8275d35d	1118	* @brief Constants defining the output level when output is in IDLE state
<>	135:176b8275d35d	1119	*/
<>	135:176b8275d35d	1120	#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE ((uint32_t)0x00000000U)/!< Output at inactive level when in IDLE state /
<>	135:176b8275d35d	1121	#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /!< Output at active level when in IDLE state /
<>	135:176b8275d35d	1122	/**
<>	135:176b8275d35d	1123	* @}
<>	135:176b8275d35d	1124	*/
<>	135:176b8275d35d	1125
<>	135:176b8275d35d	1126	/** @defgroup HRTIM_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
<>	135:176b8275d35d	1127	* @{
<>	135:176b8275d35d	1128	* @brief Constants defining the output level when output is in FAULT state.
<>	135:176b8275d35d	1129	*/
<>	135:176b8275d35d	1130	#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION ((uint32_t)0x00000000U) /!< The output is not affected by the fault input /
<>	135:176b8275d35d	1131	#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /!< Output at active level when in FAULT state /
<>	135:176b8275d35d	1132	#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /!< Output at inactive level when in FAULT state /
<>	135:176b8275d35d	1133	#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 \| HRTIM_OUTR_FAULT1_0) /!< Output is tri-stated when in FAULT state /
<>	135:176b8275d35d	1134	/**
<>	135:176b8275d35d	1135	* @}
<>	135:176b8275d35d	1136	*/
<>	135:176b8275d35d	1137
<>	135:176b8275d35d	1138	/** @defgroup HRTIM_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
<>	135:176b8275d35d	1139	* @{
<>	135:176b8275d35d	1140	* @brief Constants defining whether or not chopper mode is enabled for a timer output.
<>	135:176b8275d35d	1141	*/
<>	135:176b8275d35d	1142	#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED ((uint32_t)0x00000000U) /!< Output signal is not altered /
<>	135:176b8275d35d	1143	#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /!< Output signal is chopped by a carrier signal /
<>	135:176b8275d35d	1144	/**
<>	135:176b8275d35d	1145	* @}
<>	135:176b8275d35d	1146	*/
<>	135:176b8275d35d	1147
<>	135:176b8275d35d	1148	/** @defgroup HRTIM_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
<>	135:176b8275d35d	1149	* @{
<>	135:176b8275d35d	1150	* @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
<>	135:176b8275d35d	1151	during a programmable period before the output takes its idle state.
<>	135:176b8275d35d	1152	*/
<>	135:176b8275d35d	1153	#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR ((uint32_t)0x00000000U)/!< The programmed Idle state is applied immediately to the Output /
<>	135:176b8275d35d	1154	#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /!< Deadtime is inserted on output before entering the idle mode /
<>	135:176b8275d35d	1155	/**
<>	135:176b8275d35d	1156	* @}
<>	135:176b8275d35d	1157	*/
<>	135:176b8275d35d	1158	/** @defgroup HRTIM_EC_OUT_LEVEL OUTPUT LEVEL
<>	135:176b8275d35d	1159	* @{
<>	135:176b8275d35d	1160	* @brief Constants defining the level of a timer output.
<>	135:176b8275d35d	1161	*/
<>	135:176b8275d35d	1162	#define LL_HRTIM_OUT_LEVEL_INACTIVE ((uint32_t)0x00000000U)/!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) /
<>	135:176b8275d35d	1163	#define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) /
<>	135:176b8275d35d	1164	/**
<>	135:176b8275d35d	1165	* @}
<>	135:176b8275d35d	1166	*/
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168	/** @defgroup HRTIM_EC_EE_SRC EXTERNAL EVENT SOURCE
<>	135:176b8275d35d	1169	* @{
<>	135:176b8275d35d	1170	* @brief Constants defining available sources associated to external events.
<>	135:176b8275d35d	1171	*/
<>	135:176b8275d35d	1172	#define LL_HRTIM_EE_SRC_1 ((uint32_t)0x00000000U) /!< External event source 1 (EExSrc1)/
<>	135:176b8275d35d	1173	#define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /!< External event source 2 (EExSrc2) /
<>	135:176b8275d35d	1174	#define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /!< External event source 3 (EExSrc3) /
<>	135:176b8275d35d	1175	#define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 \| HRTIM_EECR1_EE1SRC_0) /!< External event source 4 (EExSrc4) /
<>	135:176b8275d35d	1176	/**
<>	135:176b8275d35d	1177	* @}
<>	135:176b8275d35d	1178	*/
<>	135:176b8275d35d	1179	/** @defgroup HRTIM_EC_EE_POLARITY EXTERNAL EVENT POLARITY
<>	135:176b8275d35d	1180	* @{
<>	135:176b8275d35d	1181	* @brief Constants defining the polarity of an external event.
<>	135:176b8275d35d	1182	*/
<>	135:176b8275d35d	1183	#define LL_HRTIM_EE_POLARITY_HIGH ((uint32_t)0x00000000U) /!< External event is active high /
<>	135:176b8275d35d	1184	#define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /!< External event is active low /
<>	135:176b8275d35d	1185	/**
<>	135:176b8275d35d	1186	* @}
<>	135:176b8275d35d	1187	*/
<>	135:176b8275d35d	1188
<>	135:176b8275d35d	1189	/** @defgroup HRTIM_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
<>	135:176b8275d35d	1190	* @{
<>	135:176b8275d35d	1191	* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
<>	135:176b8275d35d	1192	*/
<>	135:176b8275d35d	1193	#define LL_HRTIM_EE_SENSITIVITY_LEVEL ((uint32_t)0x00000000U) /!< External event is active on level /
<>	135:176b8275d35d	1194	#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising edge /
<>	135:176b8275d35d	1195	#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /!< External event is active on Falling edge /
<>	135:176b8275d35d	1196	#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 \| HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising and Falling edges /
<>	135:176b8275d35d	1197	/**
<>	135:176b8275d35d	1198	* @}
<>	135:176b8275d35d	1199	*/
<>	135:176b8275d35d	1200
<>	135:176b8275d35d	1201	/** @defgroup HRTIM_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
<>	135:176b8275d35d	1202	* @{
<>	135:176b8275d35d	1203	* @brief Constants defining whether or not an external event is programmed in fast mode.
<>	135:176b8275d35d	1204	*/
<>	135:176b8275d35d	1205	#define LL_HRTIM_EE_FASTMODE_DISABLE ((uint32_t)0x00000000U) /!< External Event is re-synchronized by the HRTIM logic before acting on outputs /
<>	135:176b8275d35d	1206	#define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /!< External Event is acting asynchronously on outputs (low latency mode) /
<>	135:176b8275d35d	1207	/**
<>	135:176b8275d35d	1208	* @}
<>	135:176b8275d35d	1209	*/
<>	135:176b8275d35d	1210
<>	135:176b8275d35d	1211	/** @defgroup HRTIM_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
<>	135:176b8275d35d	1212	* @{
<>	135:176b8275d35d	1213	* @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
<>	135:176b8275d35d	1214	*/
<>	135:176b8275d35d	1215	#define LL_HRTIM_EE_FILTER_NONE ((uint32_t)0x00000000U) /!< Filter disabled /
<>	135:176b8275d35d	1216	#define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fHRTIM, N=2 /
<>	135:176b8275d35d	1217	#define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /!< fSAMPLING = fHRTIM, N=4 /
<>	135:176b8275d35d	1218	#define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fHRTIM, N=8 /
<>	135:176b8275d35d	1219	#define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /!< fSAMPLING = fEEVS/2, N=6 /
<>	135:176b8275d35d	1220	#define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/2, N=8 /
<>	135:176b8275d35d	1221	#define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING = fEEVS/4, N=6 /
<>	135:176b8275d35d	1222	#define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/4, N=8 /
<>	135:176b8275d35d	1223	#define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /!< fSAMPLING = fEEVS/8, N=6 /
<>	135:176b8275d35d	1224	#define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/8, N=8 /
<>	135:176b8275d35d	1225	#define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING = fEEVS/16, N=5 /
<>	135:176b8275d35d	1226	#define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/16, N=6 /
<>	135:176b8275d35d	1227	#define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2) /!< fSAMPLING = fEEVS/16, N=8 /
<>	135:176b8275d35d	1228	#define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/32, N=5 /
<>	135:176b8275d35d	1229	#define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING = fEEVS/32, N=6 /
<>	135:176b8275d35d	1230	#define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING = fEEVS/32, N=8 /
<>	135:176b8275d35d	1231	/**
<>	135:176b8275d35d	1232	* @}
<>	135:176b8275d35d	1233	*/
<>	135:176b8275d35d	1234
<>	135:176b8275d35d	1235	/** @defgroup HRTIM_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
<>	135:176b8275d35d	1236	* @{
<>	135:176b8275d35d	1237	* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
<>	135:176b8275d35d	1238	*/
<>	135:176b8275d35d	1239	#define LL_HRTIM_EE_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< fEEVS = fHRTIM /
<>	135:176b8275d35d	1240	#define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /!< fEEVS = fHRTIM / 2 /
<>	135:176b8275d35d	1241	#define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /!< fEEVS = fHRTIM / 4 /
<>	135:176b8275d35d	1242	#define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 \| HRTIM_EECR3_EEVSD_0) /!< fEEVS = fHRTIM / 8 /
<>	135:176b8275d35d	1243	/**
<>	135:176b8275d35d	1244	* @}
<>	135:176b8275d35d	1245	*/
<>	135:176b8275d35d	1246
<>	135:176b8275d35d	1247	/** @defgroup HRTIM_EC_FLT_SRC FAULT SOURCE
<>	135:176b8275d35d	1248	* @{
<>	135:176b8275d35d	1249	* @brief Constants defining whether a faults is be triggered by any external or internal fault source.
<>	135:176b8275d35d	1250	*/
<>	135:176b8275d35d	1251	#define LL_HRTIM_FLT_SRC_DIGITALINPUT ((uint32_t)0x00000000U) /!< Fault input is FLT input pin /
<>	135:176b8275d35d	1252	#define LL_HRTIM_FLT_SRC_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /!< Fault input is FLT_Int signal (e.g. internal comparator) /
<>	135:176b8275d35d	1253	/**
<>	135:176b8275d35d	1254	* @}
<>	135:176b8275d35d	1255	*/
<>	135:176b8275d35d	1256
<>	135:176b8275d35d	1257	/** @defgroup HRTIM_EC_FLT_POLARITY FAULT POLARITY
<>	135:176b8275d35d	1258	* @{
<>	135:176b8275d35d	1259	* @brief Constants defining the polarity of a fault event.
<>	135:176b8275d35d	1260	*/
<>	135:176b8275d35d	1261	#define LL_HRTIM_FLT_POLARITY_LOW ((uint32_t)0x00000000U) /!< Fault input is active low /
<>	135:176b8275d35d	1262	#define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /!< Fault input is active high /
<>	135:176b8275d35d	1263	/**
<>	135:176b8275d35d	1264	* @}
<>	135:176b8275d35d	1265	*/
<>	135:176b8275d35d	1266
<>	135:176b8275d35d	1267	/** @defgroup HRTIM_EC_FLT_FILTER FAULT DIGITAL FILTER
<>	135:176b8275d35d	1268	* @{
<>	135:176b8275d35d	1269	* @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
<>	135:176b8275d35d	1270	*/
<>	135:176b8275d35d	1271	#define LL_HRTIM_FLT_FILTER_NONE ((uint32_t)0x00000000U) /!< Filter disabled /
<>	135:176b8275d35d	1272	#define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=2 /
<>	135:176b8275d35d	1273	#define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fHRTIM, N=4 /
<>	135:176b8275d35d	1274	#define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=8 /
<>	135:176b8275d35d	1275	#define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/2, N=6 /
<>	135:176b8275d35d	1276	#define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/2, N=8 /
<>	135:176b8275d35d	1277	#define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/4, N=6 /
<>	135:176b8275d35d	1278	#define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/4, N=8 /
<>	135:176b8275d35d	1279	#define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /!< fSAMPLING= fFLTS/8, N=6 /
<>	135:176b8275d35d	1280	#define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/8, N=8 /
<>	135:176b8275d35d	1281	#define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/16, N=5 /
<>	135:176b8275d35d	1282	#define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/16, N=6 /
<>	135:176b8275d35d	1283	#define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/16, N=8 /
<>	135:176b8275d35d	1284	#define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=5 /
<>	135:176b8275d35d	1285	#define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/32, N=6 /
<>	135:176b8275d35d	1286	#define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=8 /
<>	135:176b8275d35d	1287	/**
<>	135:176b8275d35d	1288	* @}
<>	135:176b8275d35d	1289	*/
<>	135:176b8275d35d	1290
<>	135:176b8275d35d	1291	/** @defgroup HRTIM_EC_FLT_PRESCALER BURST FAULT PRESCALER
<>	135:176b8275d35d	1292	* @{
<>	135:176b8275d35d	1293	* @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
<>	135:176b8275d35d	1294	*/
<>	135:176b8275d35d	1295	#define LL_HRTIM_FLT_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< fFLTS = fHRTIM /
<>	135:176b8275d35d	1296	#define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /!< fFLTS = fHRTIM / 2 /
<>	135:176b8275d35d	1297	#define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /!< fFLTS = fHRTIM / 4 /
<>	135:176b8275d35d	1298	#define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 \| HRTIM_FLTINR2_FLTSD_0) /!< fFLTS = fHRTIM / 8 /
<>	135:176b8275d35d	1299	/**
<>	135:176b8275d35d	1300	* @}
<>	135:176b8275d35d	1301	*/
<>	135:176b8275d35d	1302
<>	135:176b8275d35d	1303	/** @defgroup HRTIM_EC_BM_MODE BURST MODE OPERATING MODE
<>	135:176b8275d35d	1304	* @{
<>	135:176b8275d35d	1305	* @brief Constants defining if the burst mode is entered once or if it is continuously operating.
<>	135:176b8275d35d	1306	*/
<>	135:176b8275d35d	1307	#define LL_HRTIM_BM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /!< Burst mode operates in single shot mode /
<>	135:176b8275d35d	1308	#define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /!< Burst mode operates in continuous mode /
<>	135:176b8275d35d	1309	/**
<>	135:176b8275d35d	1310	* @}
<>	135:176b8275d35d	1311	*/
<>	135:176b8275d35d	1312
<>	135:176b8275d35d	1313	/** @defgroup HRTIM_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
<>	135:176b8275d35d	1314	* @{
<>	135:176b8275d35d	1315	* @brief Constants defining the clock source for the burst mode counter.
<>	135:176b8275d35d	1316	*/
<>	135:176b8275d35d	1317	#define LL_HRTIM_BM_CLKSRC_MASTER ((uint32_t)0x00000000U) /!< Master timer counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1318	#define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /!< Timer A counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1319	#define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /!< Timer B counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1320	#define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< Timer C counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1321	#define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /!< Timer D counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1322	#define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_0) /!< Timer E counter reset/roll-over is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1323	#define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1) /!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock /
<>	135:176b8275d35d	1324	#define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock /
<>	135:176b8275d35d	1325	#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock /
<>	135:176b8275d35d	1326	#define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_1) /!< Prescaled fHRTIM clock is used as clock source for the burst mode counter /
<>	135:176b8275d35d	1327	/**
<>	135:176b8275d35d	1328	* @}
<>	135:176b8275d35d	1329	*/
<>	135:176b8275d35d	1330
<>	135:176b8275d35d	1331	/** @defgroup HRTIM_EC_BM_PRESCALER BURST MODE PRESCALER
<>	135:176b8275d35d	1332	* @{
<>	135:176b8275d35d	1333	* @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
<>	135:176b8275d35d	1334	*/
<>	135:176b8275d35d	1335	#define LL_HRTIM_BM_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< fBRST = fHRTIM /
<>	135:176b8275d35d	1336	#define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2 /
<>	135:176b8275d35d	1337	#define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/4 /
<>	135:176b8275d35d	1338	#define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8 /
<>	135:176b8275d35d	1339	#define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/16 /
<>	135:176b8275d35d	1340	#define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32 /
<>	135:176b8275d35d	1341	#define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/64 /
<>	135:176b8275d35d	1342	#define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/128 /
<>	135:176b8275d35d	1343	#define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /!< fBRST = fHRTIM/256 /
<>	135:176b8275d35d	1344	#define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/512 /
<>	135:176b8275d35d	1345	#define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/1024 /
<>	135:176b8275d35d	1346	#define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2048/
<>	135:176b8275d35d	1347	#define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/4096 /
<>	135:176b8275d35d	1348	#define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8192 /
<>	135:176b8275d35d	1349	#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/16384 /
<>	135:176b8275d35d	1350	#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32768 /
<>	135:176b8275d35d	1351	/**
<>	135:176b8275d35d	1352	* @}
<>	135:176b8275d35d	1353	*/
<>	135:176b8275d35d	1354
<>	135:176b8275d35d	1355	/** @defgroup HRTIM_EC_BM_TRIG HRTIM BURST MODE TRIGGER
<>	135:176b8275d35d	1356	* @{
<>	135:176b8275d35d	1357	* @brief Constants defining the events that can be used to trig the burst mode operation.
<>	135:176b8275d35d	1358	*/
<>	135:176b8275d35d	1359	#define LL_HRTIM_BM_TRIG_NONE (uint32_t)0x00000000 /!< No trigger /
<>	135:176b8275d35d	1360	#define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /!< Master timer reset event is starting the burst mode operation /
<>	135:176b8275d35d	1361	#define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /!< Master timer repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1362	#define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /!< Master timer compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1363	#define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /!< Master timer compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1364	#define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /!< Master timer compare 3 event is starting the burst mode operation /
<>	135:176b8275d35d	1365	#define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /!< Master timer compare 4 event is starting the burst mode operation /
<>	135:176b8275d35d	1366	#define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /!< Timer A reset event is starting the burst mode operation /
<>	135:176b8275d35d	1367	#define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /!< Timer A repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1368	#define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /!< Timer A compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1369	#define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /!< Timer A compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1370	#define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /!< Timer B reset event is starting the burst mode operation /
<>	135:176b8275d35d	1371	#define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /!< Timer B repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1372	#define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /!< Timer B compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1373	#define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /!< Timer B compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1374	#define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /!< Timer C resetevent is starting the burst mode operation /
<>	135:176b8275d35d	1375	#define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /!< Timer C repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1376	#define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /!< Timer C compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1377	#define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /!< Timer C compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1378	#define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /!< Timer D reset event is starting the burst mode operation /
<>	135:176b8275d35d	1379	#define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /!< Timer D repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1380	#define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /!< Timer D compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1381	#define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /!< Timer D compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1382	#define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /!< Timer E reset event is starting the burst mode operation /
<>	135:176b8275d35d	1383	#define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /!< Timer E repetition event is starting the burst mode operation /
<>	135:176b8275d35d	1384	#define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /!< Timer E compare 1 event is starting the burst mode operation /
<>	135:176b8275d35d	1385	#define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /!< Timer E compare 2 event is starting the burst mode operation /
<>	135:176b8275d35d	1386	#define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst
<>	135:176b8275d35d	1387	mode operation */
<>	135:176b8275d35d	1388	#define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst
<>	135:176b8275d35d	1389	mode operation */
<>	135:176b8275d35d	1390	#define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /!< External event 7 conditioned by TIMA filters is starting the burst mode operation /
<>	135:176b8275d35d	1391	#define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /!< External event 8 conditioned by TIMD filters is starting the burst mode operation /
<>	135:176b8275d35d	1392	#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode
<>	135:176b8275d35d	1393	operation */
<>	135:176b8275d35d	1394	/**
<>	135:176b8275d35d	1395	* @}
<>	135:176b8275d35d	1396	*/
<>	135:176b8275d35d	1397
<>	135:176b8275d35d	1398	/** @defgroup HRTIM_EC_BM_STATUS HRTIM BURST MODE STATUS
<>	135:176b8275d35d	1399	* @{
<>	135:176b8275d35d	1400	* @brief Constants defining the operating state of the burst mode controller.
<>	135:176b8275d35d	1401	*/
<>	135:176b8275d35d	1402	#define LL_HRTIM_BM_STATUS_NORMAL ((uint32_t) 0x00000000U) /!< Normal operation /
<>	135:176b8275d35d	1403	#define LL_HRTIM_BM_STATUS_BURST_ONGOING (HRTIM_BMCR_BMSTAT) /!< Burst operation on-going /
<>	135:176b8275d35d	1404	/**
<>	135:176b8275d35d	1405	* @}
<>	135:176b8275d35d	1406	*/
<>	135:176b8275d35d	1407
<>	135:176b8275d35d	1408	/**
<>	135:176b8275d35d	1409	* @}
<>	135:176b8275d35d	1410	*/
<>	135:176b8275d35d	1411
<>	135:176b8275d35d	1412	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	1413	/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
<>	135:176b8275d35d	1414	* @{
<>	135:176b8275d35d	1415	*/
<>	135:176b8275d35d	1416
<>	135:176b8275d35d	1417	/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	135:176b8275d35d	1418	* @{
<>	135:176b8275d35d	1419	*/
<>	135:176b8275d35d	1420
<>	135:176b8275d35d	1421	/**
<>	135:176b8275d35d	1422	* @brief Write a value in HRTIM register
<>	135:176b8275d35d	1423	* @param __INSTANCE__ HRTIM Instance
<>	135:176b8275d35d	1424	* @param __REG__ Register to be written
<>	135:176b8275d35d	1425	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	1426	* @retval None
<>	135:176b8275d35d	1427	*/
<>	135:176b8275d35d	1428	#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	1429
<>	135:176b8275d35d	1430	/**
<>	135:176b8275d35d	1431	* @brief Read a value in HRTIM register
<>	135:176b8275d35d	1432	* @param __INSTANCE__ HRTIM Instance
<>	135:176b8275d35d	1433	* @param __REG__ Register to be read
<>	135:176b8275d35d	1434	* @retval Register value
<>	135:176b8275d35d	1435	*/
<>	135:176b8275d35d	1436	#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	1437	/**
<>	135:176b8275d35d	1438	* @}
<>	135:176b8275d35d	1439	*/
<>	135:176b8275d35d	1440
<>	135:176b8275d35d	1441	/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
<>	135:176b8275d35d	1442	* @{
<>	135:176b8275d35d	1443	*/
<>	135:176b8275d35d	1444	/**
<>	135:176b8275d35d	1445	* @brief HELPER macro returning the output state from output enable/disable status
<>	135:176b8275d35d	1446	* @param __OUTPUT_STATUS_EN__ output enable status
<>	135:176b8275d35d	1447	* @param __OUTPUT_STATUS_DIS__ output Disable status
<>	135:176b8275d35d	1448	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1449	* @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
<>	135:176b8275d35d	1450	* @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
<>	135:176b8275d35d	1451	* @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
<>	135:176b8275d35d	1452	*/
<>	135:176b8275d35d	1453	#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
<>	135:176b8275d35d	1454	(((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
<>	135:176b8275d35d	1455	((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
<>	135:176b8275d35d	1456	/**
<>	135:176b8275d35d	1457	* @}
<>	135:176b8275d35d	1458	*/
<>	135:176b8275d35d	1459
<>	135:176b8275d35d	1460
<>	135:176b8275d35d	1461	/**
<>	135:176b8275d35d	1462	* @}
<>	135:176b8275d35d	1463	*/
<>	135:176b8275d35d	1464
<>	135:176b8275d35d	1465	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	1466	/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
<>	135:176b8275d35d	1467	* @{
<>	135:176b8275d35d	1468	*/
<>	135:176b8275d35d	1469	/** @defgroup HRTIM_EF_HRTIM_Control HRTIM_Control
<>	135:176b8275d35d	1470	* @{
<>	135:176b8275d35d	1471	*/
<>	135:176b8275d35d	1472
<>	135:176b8275d35d	1473	/**
<>	135:176b8275d35d	1474	* @brief Select the HRTIM synchronization input source.
<>	135:176b8275d35d	1475	* @note This function must not be called when the concerned timer(s) is (are) enabled .
<>	135:176b8275d35d	1476	* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
<>	135:176b8275d35d	1477	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1478	* @param SyncInSrc This parameter can be one of the following values:
<>	135:176b8275d35d	1479	* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
<>	135:176b8275d35d	1480	* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
<>	135:176b8275d35d	1481	* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
<>	135:176b8275d35d	1482	* @retval None
<>	135:176b8275d35d	1483	*/
<>	135:176b8275d35d	1484	__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
<>	135:176b8275d35d	1485	{
<>	135:176b8275d35d	1486	MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
<>	135:176b8275d35d	1487	}
<>	135:176b8275d35d	1488
<>	135:176b8275d35d	1489	/**
<>	135:176b8275d35d	1490	* @brief Get actual HRTIM synchronization input source.
<>	135:176b8275d35d	1491	* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
<>	135:176b8275d35d	1492	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1493	* @retval SyncInSrc Returned value can be one of the following values:
<>	135:176b8275d35d	1494	* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
<>	135:176b8275d35d	1495	* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
<>	135:176b8275d35d	1496	* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
<>	135:176b8275d35d	1497	*/
<>	135:176b8275d35d	1498	__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	1499	{
<>	135:176b8275d35d	1500	return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
<>	135:176b8275d35d	1501	}
<>	135:176b8275d35d	1502
<>	135:176b8275d35d	1503	/**
<>	135:176b8275d35d	1504	* @brief Configure the HRTIM synchronization output.
<>	135:176b8275d35d	1505	* @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
<>	135:176b8275d35d	1506	* MCR SYNCOUT LL_HRTIM_ConfigSyncOut
<>	135:176b8275d35d	1507	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1508	* @param Config This parameter can be one of the following values:
<>	135:176b8275d35d	1509	* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
<>	135:176b8275d35d	1510	* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
<>	135:176b8275d35d	1511	* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
<>	135:176b8275d35d	1512	* @param Src This parameter can be one of the following values:
<>	135:176b8275d35d	1513	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
<>	135:176b8275d35d	1514	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
<>	135:176b8275d35d	1515	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
<>	135:176b8275d35d	1516	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
<>	135:176b8275d35d	1517	* @retval None
<>	135:176b8275d35d	1518	*/
<>	135:176b8275d35d	1519	__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
<>	135:176b8275d35d	1520	{
<>	135:176b8275d35d	1521	MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT \| HRTIM_MCR_SYNC_SRC), (Config \| Src));
<>	135:176b8275d35d	1522	}
<>	135:176b8275d35d	1523
<>	135:176b8275d35d	1524	/**
<>	135:176b8275d35d	1525	* @brief Set the routing and conditioning of the synchronization output event.
<>	135:176b8275d35d	1526	* @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
<>	135:176b8275d35d	1527	* @note This function can be called only when the master timer is enabled.
<>	135:176b8275d35d	1528	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1529	* @param SyncOutConfig This parameter can be one of the following values:
<>	135:176b8275d35d	1530	* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
<>	135:176b8275d35d	1531	* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
<>	135:176b8275d35d	1532	* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
<>	135:176b8275d35d	1533	* @retval None
<>	135:176b8275d35d	1534	*/
<>	135:176b8275d35d	1535	__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
<>	135:176b8275d35d	1536	{
<>	135:176b8275d35d	1537	MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
<>	135:176b8275d35d	1538	}
<>	135:176b8275d35d	1539
<>	135:176b8275d35d	1540	/**
<>	135:176b8275d35d	1541	* @brief Get actual routing and conditioning of the synchronization output event.
<>	135:176b8275d35d	1542	* @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
<>	135:176b8275d35d	1543	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1544	* @retval SyncOutConfig Returned value can be one of the following values:
<>	135:176b8275d35d	1545	* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
<>	135:176b8275d35d	1546	* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
<>	135:176b8275d35d	1547	* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
<>	135:176b8275d35d	1548	*/
<>	135:176b8275d35d	1549	__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	1550	{
<>	135:176b8275d35d	1551	return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
<>	135:176b8275d35d	1552	}
<>	135:176b8275d35d	1553
<>	135:176b8275d35d	1554	/**
<>	135:176b8275d35d	1555	* @brief Set the source and event to be sent on the HRTIM synchronization output.
<>	135:176b8275d35d	1556	* @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
<>	135:176b8275d35d	1557	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1558	* @param SyncOutSrc This parameter can be one of the following values:
<>	135:176b8275d35d	1559	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
<>	135:176b8275d35d	1560	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
<>	135:176b8275d35d	1561	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
<>	135:176b8275d35d	1562	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
<>	135:176b8275d35d	1563	* @retval None
<>	135:176b8275d35d	1564	*/
<>	135:176b8275d35d	1565	__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
<>	135:176b8275d35d	1566	{
<>	135:176b8275d35d	1567	MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
<>	135:176b8275d35d	1568	}
<>	135:176b8275d35d	1569
<>	135:176b8275d35d	1570	/**
<>	135:176b8275d35d	1571	* @brief Get actual source and event sent on the HRTIM synchronization output.
<>	135:176b8275d35d	1572	* @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
<>	135:176b8275d35d	1573	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1574	* @retval SyncOutSrc Returned value can be one of the following values:
<>	135:176b8275d35d	1575	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
<>	135:176b8275d35d	1576	* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
<>	135:176b8275d35d	1577	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
<>	135:176b8275d35d	1578	* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
<>	135:176b8275d35d	1579	*/
<>	135:176b8275d35d	1580	__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	1581	{
<>	135:176b8275d35d	1582	return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
<>	135:176b8275d35d	1583	}
<>	135:176b8275d35d	1584
<>	135:176b8275d35d	1585	/**
<>	135:176b8275d35d	1586	* @brief Disable (temporarily) update event generation.
<>	135:176b8275d35d	1587	* @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
<>	135:176b8275d35d	1588	* CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
<>	135:176b8275d35d	1589	* CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
<>	135:176b8275d35d	1590	* CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
<>	135:176b8275d35d	1591	* CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
<>	135:176b8275d35d	1592	* CR1 TEUDIS LL_HRTIM_SuspendUpdate
<>	135:176b8275d35d	1593	* @note Allow to temporarily disable the transfer from preload to active
<>	135:176b8275d35d	1594	* registers, whatever the selected update event. This allows to modify
<>	135:176b8275d35d	1595	* several registers in multiple timers.
<>	135:176b8275d35d	1596	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1597	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	1598	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	1599	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	1600	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	1601	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	1602	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	1603	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	1604	* @retval None
<>	135:176b8275d35d	1605	*/
<>	135:176b8275d35d	1606	__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	1607	{
<>	135:176b8275d35d	1608	SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
<>	135:176b8275d35d	1609	}
<>	135:176b8275d35d	1610
<>	135:176b8275d35d	1611	/**
<>	135:176b8275d35d	1612	* @brief Enable update event generation.
<>	135:176b8275d35d	1613	* @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
<>	135:176b8275d35d	1614	* CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
<>	135:176b8275d35d	1615	* CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
<>	135:176b8275d35d	1616	* CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
<>	135:176b8275d35d	1617	* CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
<>	135:176b8275d35d	1618	* CR1 TEUDIS LL_HRTIM_ResumeUpdate
<>	135:176b8275d35d	1619	* @note The regular update event takes place.
<>	135:176b8275d35d	1620	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1621	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	1622	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	1623	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	1624	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	1625	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	1626	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	1627	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	1628	* @retval None
<>	135:176b8275d35d	1629	*/
<>	135:176b8275d35d	1630	__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	1631	{
<>	135:176b8275d35d	1632	CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
<>	135:176b8275d35d	1633	}
<>	135:176b8275d35d	1634
<>	135:176b8275d35d	1635	/**
<>	135:176b8275d35d	1636	* @brief Force an immediate transfer from the preload to the active register .
<>	135:176b8275d35d	1637	* @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
<>	135:176b8275d35d	1638	* CR2 TASWU LL_HRTIM_ForceUpdate\n
<>	135:176b8275d35d	1639	* CR2 TBSWU LL_HRTIM_ForceUpdate\n
<>	135:176b8275d35d	1640	* CR2 TCSWU LL_HRTIM_ForceUpdate\n
<>	135:176b8275d35d	1641	* CR2 TDSWU LL_HRTIM_ForceUpdate\n
<>	135:176b8275d35d	1642	* CR2 TESWU LL_HRTIM_ForceUpdate
<>	135:176b8275d35d	1643	* @note Any pending update request is cancelled.
<>	135:176b8275d35d	1644	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1645	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	1646	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	1647	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	1648	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	1649	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	1650	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	1651	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	1652	* @retval None
<>	135:176b8275d35d	1653	*/
<>	135:176b8275d35d	1654	__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	1655	{
<>	135:176b8275d35d	1656	SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
<>	135:176b8275d35d	1657	}
<>	135:176b8275d35d	1658
<>	135:176b8275d35d	1659	/**
<>	135:176b8275d35d	1660	* @brief Reset the HRTIM timer(s) counter.
<>	135:176b8275d35d	1661	* @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
<>	135:176b8275d35d	1662	* CR2 TARST LL_HRTIM_CounterReset\n
<>	135:176b8275d35d	1663	* CR2 TBRST LL_HRTIM_CounterReset\n
<>	135:176b8275d35d	1664	* CR2 TCRST LL_HRTIM_CounterReset\n
<>	135:176b8275d35d	1665	* CR2 TDRST LL_HRTIM_CounterReset\n
<>	135:176b8275d35d	1666	* CR2 TERST LL_HRTIM_CounterReset
<>	135:176b8275d35d	1667	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1668	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	1669	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	1670	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	1671	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	1672	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	1673	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	1674	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	1675	* @retval None
<>	135:176b8275d35d	1676	*/
<>	135:176b8275d35d	1677	__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	1678	{
<>	135:176b8275d35d	1679	SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
<>	135:176b8275d35d	1680	}
<>	135:176b8275d35d	1681
<>	135:176b8275d35d	1682	/**
<>	135:176b8275d35d	1683	* @brief Enable the HRTIM timer(s) output(s) .
<>	135:176b8275d35d	1684	* @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1685	* OENR TA2OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1686	* OENR TB1OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1687	* OENR TB2OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1688	* OENR TC1OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1689	* OENR TC2OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1690	* OENR TD1OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1691	* OENR TD2OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1692	* OENR TE1OEN LL_HRTIM_EnableOutput\n
<>	135:176b8275d35d	1693	* OENR TE2OEN LL_HRTIM_EnableOutput
<>	135:176b8275d35d	1694	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1695	* @param Outputs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1696	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	1697	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	1698	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	1699	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	1700	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	1701	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	1702	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	1703	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	1704	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	1705	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	1706	* @retval None
<>	135:176b8275d35d	1707	*/
<>	135:176b8275d35d	1708	__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
<>	135:176b8275d35d	1709	{
<>	135:176b8275d35d	1710	SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
<>	135:176b8275d35d	1711	}
<>	135:176b8275d35d	1712
<>	135:176b8275d35d	1713	/**
<>	135:176b8275d35d	1714	* @brief Disable the HRTIM timer(s) output(s) .
<>	135:176b8275d35d	1715	* @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1716	* OENR TA2OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1717	* OENR TB1OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1718	* OENR TB2OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1719	* OENR TC1OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1720	* OENR TC2OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1721	* OENR TD1OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1722	* OENR TD2OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1723	* OENR TE1OEN LL_HRTIM_DisableOutput\n
<>	135:176b8275d35d	1724	* OENR TE2OEN LL_HRTIM_DisableOutput
<>	135:176b8275d35d	1725	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1726	* @param Outputs This parameter can be a combination of the following values:
<>	135:176b8275d35d	1727	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	1728	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	1729	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	1730	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	1731	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	1732	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	1733	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	1734	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	1735	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	1736	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	1737	* @retval None
<>	135:176b8275d35d	1738	*/
<>	135:176b8275d35d	1739	__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
<>	135:176b8275d35d	1740	{
<>	135:176b8275d35d	1741	SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
<>	135:176b8275d35d	1742	}
<>	135:176b8275d35d	1743
<>	135:176b8275d35d	1744	/**
<>	135:176b8275d35d	1745	* @brief Indicates whether the HRTIM timer output is enabled.
<>	135:176b8275d35d	1746	* @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1747	* OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1748	* OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1749	* OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1750	* OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1751	* OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1752	* OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1753	* OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1754	* OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
<>	135:176b8275d35d	1755	* OENR TE2OEN LL_HRTIM_IsEnabledOutput
<>	135:176b8275d35d	1756	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1757	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	1758	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	1759	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	1760	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	1761	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	1762	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	1763	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	1764	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	1765	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	1766	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	1767	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	1768	* @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
<>	135:176b8275d35d	1769	*/
<>	135:176b8275d35d	1770	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	1771	{
<>	135:176b8275d35d	1772	return (READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output);
<>	135:176b8275d35d	1773	}
<>	135:176b8275d35d	1774
<>	135:176b8275d35d	1775	/**
<>	135:176b8275d35d	1776	* @brief Indicates whether the HRTIM timer output is disabled.
<>	135:176b8275d35d	1777	* @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1778	* ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1779	* ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1780	* ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1781	* ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1782	* ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1783	* ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1784	* ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1785	* ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
<>	135:176b8275d35d	1786	* ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
<>	135:176b8275d35d	1787	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1788	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	1789	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	1790	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	1791	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	1792	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	1793	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	1794	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	1795	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	1796	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	1797	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	1798	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	1799	* @retval State of TxyODS bit in HRTIM_ODSR register (1 or 0).
<>	135:176b8275d35d	1800	*/
<>	135:176b8275d35d	1801	__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	1802	{
<>	135:176b8275d35d	1803	return (READ_BIT(HRTIMx->sCommonRegs.ODISR, Output) == Output);
<>	135:176b8275d35d	1804	}
<>	135:176b8275d35d	1805
<>	135:176b8275d35d	1806	/**
<>	135:176b8275d35d	1807	* @brief Configure an ADC trigger.
<>	135:176b8275d35d	1808	* @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1809	* CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1810	* CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1811	* CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1812	* ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1813	* ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1814	* ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1815	* ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1816	* ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1817	* ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1818	* ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1819	* ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1820	* ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1821	* ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1822	* ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1823	* ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1824	* ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1825	* ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1826	* ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1827	* ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1828	* ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1829	* ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1830	* ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1831	* ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1832	* ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1833	* ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1834	* ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1835	* ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1836	* ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1837	* ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1838	* ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1839	* ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1840	* ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1841	* ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1842	* ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1843	* ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1844	* ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1845	* ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1846	* ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1847	* ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1848	* ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1849	* ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1850	* ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1851	* ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1852	* ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1853	* ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1854	* ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1855	* ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1856	* ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1857	* ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1858	* ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1859	* ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1860	* ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1861	* ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1862	* ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1863	* ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1864	* ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1865	* ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1866	* ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1867	* ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1868	* ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1869	* ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1870	* ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1871	* ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1872	* ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1873	* ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1874	* ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1875	* ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1876	* ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1877	* ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1878	* ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1879	* ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1880	* ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1881	* ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1882	* ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1883	* ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1884	* ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1885	* ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1886	* ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1887	* ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1888	* ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1889	* ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1890	* ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1891	* ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1892	* ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1893	* ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1894	* ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1895	* ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1896	* ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1897	* ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1898	* ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1899	* ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1900	* ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1901	* ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1902	* ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1903	* ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1904	* ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1905	* ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1906	* ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1907	* ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1908	* ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1909	* ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1910	* ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1911	* ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1912	* ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1913	* ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1914	* ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1915	* ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1916	* ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1917	* ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1918	* ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1919	* ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1920	* ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1921	* ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1922	* ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1923	* ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1924	* ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1925	* ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1926	* ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1927	* ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1928	* ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1929	* ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1930	* ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1931	* ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1932	* ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1933	* ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1934	* ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1935	* ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
<>	135:176b8275d35d	1936	* ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
<>	135:176b8275d35d	1937	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	1938	* @param ADCTrig This parameter can be one of the following values:
<>	135:176b8275d35d	1939	* @arg @ref LL_HRTIM_ADCTRIG_1
<>	135:176b8275d35d	1940	* @arg @ref LL_HRTIM_ADCTRIG_2
<>	135:176b8275d35d	1941	* @arg @ref LL_HRTIM_ADCTRIG_3
<>	135:176b8275d35d	1942	* @arg @ref LL_HRTIM_ADCTRIG_4
<>	135:176b8275d35d	1943	* @param Update This parameter can be one of the following values:
<>	135:176b8275d35d	1944	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
<>	135:176b8275d35d	1945	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
<>	135:176b8275d35d	1946	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
<>	135:176b8275d35d	1947	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
<>	135:176b8275d35d	1948	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
<>	135:176b8275d35d	1949	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
<>	135:176b8275d35d	1950	* @param Src This parameter can be a combination of the following values:
<>	135:176b8275d35d	1951	*
<>	135:176b8275d35d	1952	* For ADC trigger 1 and ADC trigger 3:
<>	135:176b8275d35d	1953	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
<>	135:176b8275d35d	1954	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
<>	135:176b8275d35d	1955	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
<>	135:176b8275d35d	1956	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
<>	135:176b8275d35d	1957	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
<>	135:176b8275d35d	1958	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
<>	135:176b8275d35d	1959	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
<>	135:176b8275d35d	1960	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
<>	135:176b8275d35d	1961	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
<>	135:176b8275d35d	1962	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
<>	135:176b8275d35d	1963	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
<>	135:176b8275d35d	1964	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
<>	135:176b8275d35d	1965	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
<>	135:176b8275d35d	1966	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
<>	135:176b8275d35d	1967	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
<>	135:176b8275d35d	1968	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
<>	135:176b8275d35d	1969	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
<>	135:176b8275d35d	1970	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
<>	135:176b8275d35d	1971	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
<>	135:176b8275d35d	1972	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
<>	135:176b8275d35d	1973	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
<>	135:176b8275d35d	1974	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
<>	135:176b8275d35d	1975	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
<>	135:176b8275d35d	1976	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
<>	135:176b8275d35d	1977	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
<>	135:176b8275d35d	1978	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
<>	135:176b8275d35d	1979	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
<>	135:176b8275d35d	1980	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
<>	135:176b8275d35d	1981	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
<>	135:176b8275d35d	1982	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
<>	135:176b8275d35d	1983	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
<>	135:176b8275d35d	1984	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
<>	135:176b8275d35d	1985	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
<>	135:176b8275d35d	1986	*
<>	135:176b8275d35d	1987	* For ADC trigger 2 and ADC trigger 4:
<>	135:176b8275d35d	1988	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
<>	135:176b8275d35d	1989	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
<>	135:176b8275d35d	1990	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
<>	135:176b8275d35d	1991	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
<>	135:176b8275d35d	1992	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
<>	135:176b8275d35d	1993	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
<>	135:176b8275d35d	1994	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
<>	135:176b8275d35d	1995	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
<>	135:176b8275d35d	1996	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
<>	135:176b8275d35d	1997	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
<>	135:176b8275d35d	1998	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
<>	135:176b8275d35d	1999	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
<>	135:176b8275d35d	2000	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
<>	135:176b8275d35d	2001	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
<>	135:176b8275d35d	2002	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
<>	135:176b8275d35d	2003	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
<>	135:176b8275d35d	2004	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
<>	135:176b8275d35d	2005	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
<>	135:176b8275d35d	2006	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
<>	135:176b8275d35d	2007	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
<>	135:176b8275d35d	2008	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
<>	135:176b8275d35d	2009	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
<>	135:176b8275d35d	2010	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
<>	135:176b8275d35d	2011	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
<>	135:176b8275d35d	2012	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
<>	135:176b8275d35d	2013	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
<>	135:176b8275d35d	2014	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
<>	135:176b8275d35d	2015	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
<>	135:176b8275d35d	2016	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
<>	135:176b8275d35d	2017	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
<>	135:176b8275d35d	2018	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
<>	135:176b8275d35d	2019	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
<>	135:176b8275d35d	2020	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
<>	135:176b8275d35d	2021	* @retval None
<>	135:176b8275d35d	2022	*/
<>	135:176b8275d35d	2023	__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
<>	135:176b8275d35d	2024	{
<>	135:176b8275d35d	2025	register uint32_t shift = 3 * ADCTrig;
<>	135:176b8275d35d	2026	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
<>	135:176b8275d35d	2027	REG_OFFSET_TAB_ADCxR[ADCTrig]));
<>	135:176b8275d35d	2028	MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
<>	135:176b8275d35d	2029	WRITE_REG(*pReg, Src);
<>	135:176b8275d35d	2030	}
<>	135:176b8275d35d	2031
<>	135:176b8275d35d	2032	/**
<>	135:176b8275d35d	2033	* @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
<>	135:176b8275d35d	2034	* @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
<>	135:176b8275d35d	2035	* CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
<>	135:176b8275d35d	2036	* CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
<>	135:176b8275d35d	2037	* CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate
<>	135:176b8275d35d	2038	* @note When the preload is disabled in the source timer, the HRTIM_ADCxR
<>	135:176b8275d35d	2039	* registers are not preloaded either: a write access will result in an
<>	135:176b8275d35d	2040	* immediate update of the trigger source.
<>	135:176b8275d35d	2041	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2042	* @param ADCTrig This parameter can be one of the following values:
<>	135:176b8275d35d	2043	* @arg @ref LL_HRTIM_ADCTRIG_1
<>	135:176b8275d35d	2044	* @arg @ref LL_HRTIM_ADCTRIG_2
<>	135:176b8275d35d	2045	* @arg @ref LL_HRTIM_ADCTRIG_3
<>	135:176b8275d35d	2046	* @arg @ref LL_HRTIM_ADCTRIG_4
<>	135:176b8275d35d	2047	* @param Update This parameter can be one of the following values:
<>	135:176b8275d35d	2048	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
<>	135:176b8275d35d	2049	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
<>	135:176b8275d35d	2050	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
<>	135:176b8275d35d	2051	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
<>	135:176b8275d35d	2052	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
<>	135:176b8275d35d	2053	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
<>	135:176b8275d35d	2054	* @retval None
<>	135:176b8275d35d	2055	*/
<>	135:176b8275d35d	2056	__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
<>	135:176b8275d35d	2057	{
<>	135:176b8275d35d	2058	register uint32_t shift = 3 * ADCTrig;
<>	135:176b8275d35d	2059	MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
<>	135:176b8275d35d	2060	}
<>	135:176b8275d35d	2061
<>	135:176b8275d35d	2062	/**
<>	135:176b8275d35d	2063	* @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
<>	135:176b8275d35d	2064	* @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
<>	135:176b8275d35d	2065	* CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
<>	135:176b8275d35d	2066	* CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
<>	135:176b8275d35d	2067	* CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate
<>	135:176b8275d35d	2068	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2069	* @param ADCTrig This parameter can be one of the following values:
<>	135:176b8275d35d	2070	* @arg @ref LL_HRTIM_ADCTRIG_1
<>	135:176b8275d35d	2071	* @arg @ref LL_HRTIM_ADCTRIG_2
<>	135:176b8275d35d	2072	* @arg @ref LL_HRTIM_ADCTRIG_3
<>	135:176b8275d35d	2073	* @arg @ref LL_HRTIM_ADCTRIG_4
<>	135:176b8275d35d	2074	* @retval Update Returned value can be one of the following values:
<>	135:176b8275d35d	2075	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
<>	135:176b8275d35d	2076	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
<>	135:176b8275d35d	2077	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
<>	135:176b8275d35d	2078	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
<>	135:176b8275d35d	2079	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
<>	135:176b8275d35d	2080	* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
<>	135:176b8275d35d	2081	*/
<>	135:176b8275d35d	2082	__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
<>	135:176b8275d35d	2083	{
<>	135:176b8275d35d	2084	register uint32_t shift = 3 * ADCTrig;
<>	135:176b8275d35d	2085	return (READ_BIT(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift)) >> shift);
<>	135:176b8275d35d	2086	}
<>	135:176b8275d35d	2087
<>	135:176b8275d35d	2088	/**
<>	135:176b8275d35d	2089	* @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
<>	135:176b8275d35d	2090	* @rmtoll ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2091	* ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2092	* ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2093	* ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2094	* ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2095	* ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2096	* ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2097	* ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2098	* ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2099	* ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2100	* ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2101	* ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2102	* ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2103	* ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2104	* ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2105	* ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2106	* ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2107	* ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2108	* ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2109	* ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2110	* ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2111	* ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2112	* ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2113	* ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2114	* ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2115	* ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2116	* ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2117	* ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2118	* ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2119	* ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2120	* ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2121	* ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2122	* ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2123	* ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2124	* ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2125	* ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2126	* ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2127	* ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2128	* ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2129	* ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2130	* ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2131	* ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2132	* ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2133	* ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2134	* ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2135	* ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2136	* ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2137	* ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2138	* ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2139	* ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2140	* ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2141	* ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2142	* ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2143	* ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2144	* ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2145	* ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2146	* ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2147	* ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2148	* ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2149	* ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2150	* ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2151	* ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2152	* ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2153	* ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2154	* ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2155	* ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2156	* ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2157	* ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2158	* ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2159	* ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2160	* ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2161	* ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2162	* ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2163	* ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2164	* ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2165	* ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2166	* ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2167	* ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2168	* ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2169	* ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2170	* ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2171	* ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2172	* ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2173	* ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2174	* ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2175	* ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2176	* ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2177	* ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2178	* ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2179	* ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2180	* ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2181	* ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2182	* ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2183	* ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2184	* ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2185	* ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2186	* ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2187	* ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2188	* ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2189	* ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2190	* ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2191	* ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2192	* ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2193	* ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2194	* ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2195	* ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2196	* ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2197	* ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2198	* ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2199	* ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2200	* ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2201	* ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2202	* ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2203	* ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2204	* ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2205	* ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2206	* ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2207	* ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2208	* ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2209	* ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2210	* ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2211	* ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2212	* ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2213	* ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
<>	135:176b8275d35d	2214	* ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc
<>	135:176b8275d35d	2215	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2216	* @param ADCTrig This parameter can be one of the following values:
<>	135:176b8275d35d	2217	* @arg @ref LL_HRTIM_ADCTRIG_1
<>	135:176b8275d35d	2218	* @arg @ref LL_HRTIM_ADCTRIG_2
<>	135:176b8275d35d	2219	* @arg @ref LL_HRTIM_ADCTRIG_3
<>	135:176b8275d35d	2220	* @arg @ref LL_HRTIM_ADCTRIG_4
<>	135:176b8275d35d	2221	* @param Src This parameter can be a combination of the following values:
<>	135:176b8275d35d	2222	*
<>	135:176b8275d35d	2223	* For ADC trigger 1 and ADC trigger 3:
<>	135:176b8275d35d	2224	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
<>	135:176b8275d35d	2225	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
<>	135:176b8275d35d	2226	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
<>	135:176b8275d35d	2227	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
<>	135:176b8275d35d	2228	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
<>	135:176b8275d35d	2229	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
<>	135:176b8275d35d	2230	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
<>	135:176b8275d35d	2231	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
<>	135:176b8275d35d	2232	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
<>	135:176b8275d35d	2233	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
<>	135:176b8275d35d	2234	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
<>	135:176b8275d35d	2235	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
<>	135:176b8275d35d	2236	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
<>	135:176b8275d35d	2237	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
<>	135:176b8275d35d	2238	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
<>	135:176b8275d35d	2239	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
<>	135:176b8275d35d	2240	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
<>	135:176b8275d35d	2241	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
<>	135:176b8275d35d	2242	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
<>	135:176b8275d35d	2243	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
<>	135:176b8275d35d	2244	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
<>	135:176b8275d35d	2245	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
<>	135:176b8275d35d	2246	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
<>	135:176b8275d35d	2247	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
<>	135:176b8275d35d	2248	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
<>	135:176b8275d35d	2249	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
<>	135:176b8275d35d	2250	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
<>	135:176b8275d35d	2251	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
<>	135:176b8275d35d	2252	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
<>	135:176b8275d35d	2253	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
<>	135:176b8275d35d	2254	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
<>	135:176b8275d35d	2255	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
<>	135:176b8275d35d	2256	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
<>	135:176b8275d35d	2257	*
<>	135:176b8275d35d	2258	* For ADC trigger 2 and ADC trigger 4:
<>	135:176b8275d35d	2259	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
<>	135:176b8275d35d	2260	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
<>	135:176b8275d35d	2261	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
<>	135:176b8275d35d	2262	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
<>	135:176b8275d35d	2263	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
<>	135:176b8275d35d	2264	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
<>	135:176b8275d35d	2265	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
<>	135:176b8275d35d	2266	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
<>	135:176b8275d35d	2267	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
<>	135:176b8275d35d	2268	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
<>	135:176b8275d35d	2269	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
<>	135:176b8275d35d	2270	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
<>	135:176b8275d35d	2271	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
<>	135:176b8275d35d	2272	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
<>	135:176b8275d35d	2273	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
<>	135:176b8275d35d	2274	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
<>	135:176b8275d35d	2275	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
<>	135:176b8275d35d	2276	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
<>	135:176b8275d35d	2277	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
<>	135:176b8275d35d	2278	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
<>	135:176b8275d35d	2279	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
<>	135:176b8275d35d	2280	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
<>	135:176b8275d35d	2281	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
<>	135:176b8275d35d	2282	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
<>	135:176b8275d35d	2283	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
<>	135:176b8275d35d	2284	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
<>	135:176b8275d35d	2285	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
<>	135:176b8275d35d	2286	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
<>	135:176b8275d35d	2287	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
<>	135:176b8275d35d	2288	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
<>	135:176b8275d35d	2289	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
<>	135:176b8275d35d	2290	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
<>	135:176b8275d35d	2291	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
<>	135:176b8275d35d	2292	* @retval None
<>	135:176b8275d35d	2293	*/
<>	135:176b8275d35d	2294	__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
<>	135:176b8275d35d	2295	{
<>	135:176b8275d35d	2296	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
<>	135:176b8275d35d	2297	REG_OFFSET_TAB_ADCxR[ADCTrig]));
<>	135:176b8275d35d	2298	WRITE_REG(*pReg, Src);
<>	135:176b8275d35d	2299	}
<>	135:176b8275d35d	2300
<>	135:176b8275d35d	2301	/**
<>	135:176b8275d35d	2302	* @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
<>	135:176b8275d35d	2303	* @rmtoll ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2304	* ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2305	* ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2306	* ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2307	* ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2308	* ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2309	* ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2310	* ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2311	* ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2312	* ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2313	* ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2314	* ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2315	* ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2316	* ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2317	* ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2318	* ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2319	* ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2320	* ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2321	* ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2322	* ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2323	* ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2324	* ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2325	* ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2326	* ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2327	* ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2328	* ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2329	* ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2330	* ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2331	* ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2332	* ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2333	* ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2334	* ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2335	* ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2336	* ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2337	* ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2338	* ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2339	* ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2340	* ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2341	* ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2342	* ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2343	* ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2344	* ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2345	* ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2346	* ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2347	* ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2348	* ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2349	* ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2350	* ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2351	* ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2352	* ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2353	* ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2354	* ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2355	* ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2356	* ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2357	* ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2358	* ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2359	* ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2360	* ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2361	* ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2362	* ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2363	* ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2364	* ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2365	* ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2366	* ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2367	* ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2368	* ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2369	* ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2370	* ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2371	* ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2372	* ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2373	* ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2374	* ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2375	* ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2376	* ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2377	* ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2378	* ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2379	* ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2380	* ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2381	* ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2382	* ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2383	* ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2384	* ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2385	* ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2386	* ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2387	* ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2388	* ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2389	* ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2390	* ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2391	* ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2392	* ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2393	* ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2394	* ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2395	* ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2396	* ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2397	* ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2398	* ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2399	* ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2400	* ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2401	* ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2402	* ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2403	* ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2404	* ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2405	* ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2406	* ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2407	* ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2408	* ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2409	* ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2410	* ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2411	* ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2412	* ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2413	* ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2414	* ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2415	* ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2416	* ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2417	* ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2418	* ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2419	* ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2420	* ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2421	* ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2422	* ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2423	* ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2424	* ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2425	* ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2426	* ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
<>	135:176b8275d35d	2427	* ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
<>	135:176b8275d35d	2428	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2429	* @param ADCTrig This parameter can be one of the following values:
<>	135:176b8275d35d	2430	* @arg @ref LL_HRTIM_ADCTRIG_1
<>	135:176b8275d35d	2431	* @arg @ref LL_HRTIM_ADCTRIG_2
<>	135:176b8275d35d	2432	* @arg @ref LL_HRTIM_ADCTRIG_3
<>	135:176b8275d35d	2433	* @arg @ref LL_HRTIM_ADCTRIG_4
<>	135:176b8275d35d	2434	* @retval Src This parameter can be a combination of the following values:
<>	135:176b8275d35d	2435	*
<>	135:176b8275d35d	2436	* For ADC trigger 1 and ADC trigger 3:
<>	135:176b8275d35d	2437	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
<>	135:176b8275d35d	2438	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
<>	135:176b8275d35d	2439	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
<>	135:176b8275d35d	2440	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
<>	135:176b8275d35d	2441	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
<>	135:176b8275d35d	2442	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
<>	135:176b8275d35d	2443	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
<>	135:176b8275d35d	2444	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
<>	135:176b8275d35d	2445	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
<>	135:176b8275d35d	2446	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
<>	135:176b8275d35d	2447	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
<>	135:176b8275d35d	2448	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
<>	135:176b8275d35d	2449	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
<>	135:176b8275d35d	2450	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
<>	135:176b8275d35d	2451	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
<>	135:176b8275d35d	2452	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
<>	135:176b8275d35d	2453	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
<>	135:176b8275d35d	2454	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
<>	135:176b8275d35d	2455	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
<>	135:176b8275d35d	2456	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
<>	135:176b8275d35d	2457	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
<>	135:176b8275d35d	2458	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
<>	135:176b8275d35d	2459	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
<>	135:176b8275d35d	2460	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
<>	135:176b8275d35d	2461	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
<>	135:176b8275d35d	2462	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
<>	135:176b8275d35d	2463	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
<>	135:176b8275d35d	2464	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
<>	135:176b8275d35d	2465	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
<>	135:176b8275d35d	2466	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
<>	135:176b8275d35d	2467	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
<>	135:176b8275d35d	2468	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
<>	135:176b8275d35d	2469	* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
<>	135:176b8275d35d	2470	*
<>	135:176b8275d35d	2471	* For ADC trigger 2 and ADC trigger 4:
<>	135:176b8275d35d	2472	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
<>	135:176b8275d35d	2473	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
<>	135:176b8275d35d	2474	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
<>	135:176b8275d35d	2475	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
<>	135:176b8275d35d	2476	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
<>	135:176b8275d35d	2477	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
<>	135:176b8275d35d	2478	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
<>	135:176b8275d35d	2479	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
<>	135:176b8275d35d	2480	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
<>	135:176b8275d35d	2481	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
<>	135:176b8275d35d	2482	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
<>	135:176b8275d35d	2483	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
<>	135:176b8275d35d	2484	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
<>	135:176b8275d35d	2485	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
<>	135:176b8275d35d	2486	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
<>	135:176b8275d35d	2487	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
<>	135:176b8275d35d	2488	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
<>	135:176b8275d35d	2489	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
<>	135:176b8275d35d	2490	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
<>	135:176b8275d35d	2491	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
<>	135:176b8275d35d	2492	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
<>	135:176b8275d35d	2493	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
<>	135:176b8275d35d	2494	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
<>	135:176b8275d35d	2495	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
<>	135:176b8275d35d	2496	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
<>	135:176b8275d35d	2497	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
<>	135:176b8275d35d	2498	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
<>	135:176b8275d35d	2499	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
<>	135:176b8275d35d	2500	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
<>	135:176b8275d35d	2501	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
<>	135:176b8275d35d	2502	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
<>	135:176b8275d35d	2503	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
<>	135:176b8275d35d	2504	* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
<>	135:176b8275d35d	2505	*/
<>	135:176b8275d35d	2506	__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
<>	135:176b8275d35d	2507	{
<>	135:176b8275d35d	2508	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
<>	135:176b8275d35d	2509	REG_OFFSET_TAB_ADCxR[ADCTrig]));
<>	135:176b8275d35d	2510	return (*pReg);
<>	135:176b8275d35d	2511	}
<>	135:176b8275d35d	2512
<>	135:176b8275d35d	2513	/**
<>	135:176b8275d35d	2514	* @brief Configure the DLL calibration mode.
<>	135:176b8275d35d	2515	* @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
<>	135:176b8275d35d	2516	* DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
<>	135:176b8275d35d	2517	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2518	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	2519	* @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
<>	135:176b8275d35d	2520	* @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
<>	135:176b8275d35d	2521	* @param Period This parameter can be one of the following values:
<>	135:176b8275d35d	2522	* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_7300
<>	135:176b8275d35d	2523	* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_910
<>	135:176b8275d35d	2524	* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_114
<>	135:176b8275d35d	2525	* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_14
<>	135:176b8275d35d	2526	* @retval None
<>	135:176b8275d35d	2527	*/
<>	135:176b8275d35d	2528	__STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
<>	135:176b8275d35d	2529	{
<>	135:176b8275d35d	2530	MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN \| HRTIM_DLLCR_CALRTE), (Mode \| Period));
<>	135:176b8275d35d	2531	}
<>	135:176b8275d35d	2532
<>	135:176b8275d35d	2533	/**
<>	135:176b8275d35d	2534	* @brief Launch DLL calibration
<>	135:176b8275d35d	2535	* @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
<>	135:176b8275d35d	2536	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2537	* @retval None
<>	135:176b8275d35d	2538	*/
<>	135:176b8275d35d	2539	__STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	2540	{
<>	135:176b8275d35d	2541	SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
<>	135:176b8275d35d	2542	}
<>	135:176b8275d35d	2543
<>	135:176b8275d35d	2544	/**
<>	135:176b8275d35d	2545	* @}
<>	135:176b8275d35d	2546	*/
<>	135:176b8275d35d	2547
<>	135:176b8275d35d	2548	/** @defgroup HRTIM_EF_HRTIM_Timer_Control HRTIM_Timer_Control
<>	135:176b8275d35d	2549	* @{
<>	135:176b8275d35d	2550	*/
<>	135:176b8275d35d	2551
<>	135:176b8275d35d	2552	/**
<>	135:176b8275d35d	2553	* @brief Enable timer(s) counter.
<>	135:176b8275d35d	2554	* @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
<>	135:176b8275d35d	2555	* MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
<>	135:176b8275d35d	2556	* MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
<>	135:176b8275d35d	2557	* MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
<>	135:176b8275d35d	2558	* MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
<>	135:176b8275d35d	2559	* MDIER MCEN LL_HRTIM_TIM_CounterEnable
<>	135:176b8275d35d	2560	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2561	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	2562	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2563	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2564	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2565	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2566	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2567	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2568	* @retval None
<>	135:176b8275d35d	2569	*/
<>	135:176b8275d35d	2570	__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	2571	{
<>	135:176b8275d35d	2572	SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
<>	135:176b8275d35d	2573	}
<>	135:176b8275d35d	2574
<>	135:176b8275d35d	2575	/**
<>	135:176b8275d35d	2576	* @brief Disable timer(s) counter.
<>	135:176b8275d35d	2577	* @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
<>	135:176b8275d35d	2578	* MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
<>	135:176b8275d35d	2579	* MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
<>	135:176b8275d35d	2580	* MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
<>	135:176b8275d35d	2581	* MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
<>	135:176b8275d35d	2582	* MDIER MCEN LL_HRTIM_TIM_CounterDisable
<>	135:176b8275d35d	2583	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2584	* @param Timers This parameter can be a combination of the following values:
<>	135:176b8275d35d	2585	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2586	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2587	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2588	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2589	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2590	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2591	* @retval None
<>	135:176b8275d35d	2592	*/
<>	135:176b8275d35d	2593	__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
<>	135:176b8275d35d	2594	{
<>	135:176b8275d35d	2595	CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
<>	135:176b8275d35d	2596	}
<>	135:176b8275d35d	2597
<>	135:176b8275d35d	2598	/**
<>	135:176b8275d35d	2599	* @brief Indicate whether the timer counter is enabled.
<>	135:176b8275d35d	2600	* @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
<>	135:176b8275d35d	2601	* MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
<>	135:176b8275d35d	2602	* MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
<>	135:176b8275d35d	2603	* MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
<>	135:176b8275d35d	2604	* MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
<>	135:176b8275d35d	2605	* MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
<>	135:176b8275d35d	2606	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2607	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2608	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2609	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2610	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2611	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2612	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2613	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2614	* @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
<>	135:176b8275d35d	2615	*/
<>	135:176b8275d35d	2616	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2617	{
<>	135:176b8275d35d	2618	return (READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer));
<>	135:176b8275d35d	2619	}
<>	135:176b8275d35d	2620
<>	135:176b8275d35d	2621	/**
<>	135:176b8275d35d	2622	* @brief Set the timer clock prescaler ratio.
<>	135:176b8275d35d	2623	* @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
<>	135:176b8275d35d	2624	* TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
<>	135:176b8275d35d	2625	* @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
<>	135:176b8275d35d	2626	* @note The prescaling ratio cannot be modified once the timer counter is enabled.
<>	135:176b8275d35d	2627	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2628	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2629	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2630	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2631	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2632	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2633	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2634	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2635	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	2636	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
<>	135:176b8275d35d	2637	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
<>	135:176b8275d35d	2638	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
<>	135:176b8275d35d	2639	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
<>	135:176b8275d35d	2640	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
<>	135:176b8275d35d	2641	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
<>	135:176b8275d35d	2642	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
<>	135:176b8275d35d	2643	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
<>	135:176b8275d35d	2644	* @retval None
<>	135:176b8275d35d	2645	*/
<>	135:176b8275d35d	2646	__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
<>	135:176b8275d35d	2647	{
<>	135:176b8275d35d	2648	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2649	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2650	MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
<>	135:176b8275d35d	2651	}
<>	135:176b8275d35d	2652
<>	135:176b8275d35d	2653	/**
<>	135:176b8275d35d	2654	* @brief Get the timer clock prescaler ratio
<>	135:176b8275d35d	2655	* @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
<>	135:176b8275d35d	2656	* TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
<>	135:176b8275d35d	2657	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2658	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2659	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2660	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2661	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2662	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2663	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2664	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2665	* @retval Prescaler Returned value can be one of the following values:
<>	135:176b8275d35d	2666	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
<>	135:176b8275d35d	2667	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
<>	135:176b8275d35d	2668	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
<>	135:176b8275d35d	2669	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
<>	135:176b8275d35d	2670	* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
<>	135:176b8275d35d	2671	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
<>	135:176b8275d35d	2672	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
<>	135:176b8275d35d	2673	* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
<>	135:176b8275d35d	2674	*/
<>	135:176b8275d35d	2675	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2676	{
<>	135:176b8275d35d	2677	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2678	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2679	return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
<>	135:176b8275d35d	2680	}
<>	135:176b8275d35d	2681
<>	135:176b8275d35d	2682	/**
<>	135:176b8275d35d	2683	* @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
<>	135:176b8275d35d	2684	* @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
<>	135:176b8275d35d	2685	* MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
<>	135:176b8275d35d	2686	* TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
<>	135:176b8275d35d	2687	* TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
<>	135:176b8275d35d	2688	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2689	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2690	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2691	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2692	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2693	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2694	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2695	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2696	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	2697	* @arg @ref LL_HRTIM_MODE_CONTINUOUS
<>	135:176b8275d35d	2698	* @arg @ref LL_HRTIM_MODE_SINGLESHOT
<>	135:176b8275d35d	2699	* @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
<>	135:176b8275d35d	2700	* @retval None
<>	135:176b8275d35d	2701	*/
<>	135:176b8275d35d	2702	__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
<>	135:176b8275d35d	2703	{
<>	135:176b8275d35d	2704	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2705	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2706	MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG \| HRTIM_MCR_CONT), Mode);
<>	135:176b8275d35d	2707	}
<>	135:176b8275d35d	2708
<>	135:176b8275d35d	2709	/**
<>	135:176b8275d35d	2710	* @brief Get the counter operating mode mode
<>	135:176b8275d35d	2711	* @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
<>	135:176b8275d35d	2712	* MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
<>	135:176b8275d35d	2713	* TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
<>	135:176b8275d35d	2714	* TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
<>	135:176b8275d35d	2715	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2716	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2717	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2718	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2719	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2720	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2721	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2722	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2723	* @retval Mode Returned value can be one of the following values:
<>	135:176b8275d35d	2724	* @arg @ref LL_HRTIM_MODE_CONTINUOUS
<>	135:176b8275d35d	2725	* @arg @ref LL_HRTIM_MODE_SINGLESHOT
<>	135:176b8275d35d	2726	* @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
<>	135:176b8275d35d	2727	*/
<>	135:176b8275d35d	2728	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2729	{
<>	135:176b8275d35d	2730	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2731	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2732	return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG \| HRTIM_MCR_CONT)));
<>	135:176b8275d35d	2733	}
<>	135:176b8275d35d	2734
<>	135:176b8275d35d	2735	/**
<>	135:176b8275d35d	2736	* @brief Enable the half duty-cycle mode.
<>	135:176b8275d35d	2737	* @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
<>	135:176b8275d35d	2738	* TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
<>	135:176b8275d35d	2739	* @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
<>	135:176b8275d35d	2740	* active register is automatically updated with HRTIM_MPER/2
<>	135:176b8275d35d	2741	* (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
<>	135:176b8275d35d	2742	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2743	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2744	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2745	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2746	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2747	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2748	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2749	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2750	* @retval None
<>	135:176b8275d35d	2751	*/
<>	135:176b8275d35d	2752	__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2753	{
<>	135:176b8275d35d	2754	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2755	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2756	SET_BIT(*pReg, HRTIM_MCR_HALF);
<>	135:176b8275d35d	2757	}
<>	135:176b8275d35d	2758
<>	135:176b8275d35d	2759	/**
<>	135:176b8275d35d	2760	* @brief Disable the half duty-cycle mode.
<>	135:176b8275d35d	2761	* @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
<>	135:176b8275d35d	2762	* TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
<>	135:176b8275d35d	2763	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2764	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2765	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2766	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2767	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2768	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2769	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2770	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2771	* @retval None
<>	135:176b8275d35d	2772	*/
<>	135:176b8275d35d	2773	__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2774	{
<>	135:176b8275d35d	2775	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2776	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2777	CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
<>	135:176b8275d35d	2778	}
<>	135:176b8275d35d	2779
<>	135:176b8275d35d	2780	/**
<>	135:176b8275d35d	2781	* @brief Indicate whether half duty-cycle mode is enabled for a given timer.
<>	135:176b8275d35d	2782	* @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
<>	135:176b8275d35d	2783	* TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
<>	135:176b8275d35d	2784	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2785	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2786	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2787	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2788	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2789	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2790	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2791	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2792	* @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
<>	135:176b8275d35d	2793	*/
<>	135:176b8275d35d	2794	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2795	{
<>	135:176b8275d35d	2796	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2797	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2798	return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF);
<>	135:176b8275d35d	2799	}
<>	135:176b8275d35d	2800
<>	135:176b8275d35d	2801	/**
<>	135:176b8275d35d	2802	* @brief Enable the timer start when receiving a synchronization input event.
<>	135:176b8275d35d	2803	* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
<>	135:176b8275d35d	2804	* TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
<>	135:176b8275d35d	2805	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2806	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2807	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2808	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2809	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2810	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2811	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2812	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2813	* @retval None
<>	135:176b8275d35d	2814	*/
<>	135:176b8275d35d	2815	__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2816	{
<>	135:176b8275d35d	2817	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2818	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2819	SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
<>	135:176b8275d35d	2820	}
<>	135:176b8275d35d	2821
<>	135:176b8275d35d	2822	/**
<>	135:176b8275d35d	2823	* @brief Disable the timer start when receiving a synchronization input event.
<>	135:176b8275d35d	2824	* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
<>	135:176b8275d35d	2825	* TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
<>	135:176b8275d35d	2826	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2827	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2828	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2829	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2830	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2831	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2832	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2833	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2834	* @retval None
<>	135:176b8275d35d	2835	*/
<>	135:176b8275d35d	2836	__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2837	{
<>	135:176b8275d35d	2838	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2839	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2840	CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
<>	135:176b8275d35d	2841	}
<>	135:176b8275d35d	2842
<>	135:176b8275d35d	2843	/**
<>	135:176b8275d35d	2844	* @brief Indicate whether the timer start when receiving a synchronization input event.
<>	135:176b8275d35d	2845	* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
<>	135:176b8275d35d	2846	* TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
<>	135:176b8275d35d	2847	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2848	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2849	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2850	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2851	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2852	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2853	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2854	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2855	* @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
<>	135:176b8275d35d	2856	*/
<>	135:176b8275d35d	2857	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2858	{
<>	135:176b8275d35d	2859	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2860	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2861	return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM);
<>	135:176b8275d35d	2862	}
<>	135:176b8275d35d	2863
<>	135:176b8275d35d	2864	/**
<>	135:176b8275d35d	2865	* @brief Enable the timer reset when receiving a synchronization input event.
<>	135:176b8275d35d	2866	* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
<>	135:176b8275d35d	2867	* TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
<>	135:176b8275d35d	2868	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2869	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2870	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2871	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2872	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2873	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2874	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2875	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2876	* @retval None
<>	135:176b8275d35d	2877	*/
<>	135:176b8275d35d	2878	__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2879	{
<>	135:176b8275d35d	2880	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2881	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2882	SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
<>	135:176b8275d35d	2883	}
<>	135:176b8275d35d	2884
<>	135:176b8275d35d	2885	/**
<>	135:176b8275d35d	2886	* @brief Disable the timer reset when receiving a synchronization input event.
<>	135:176b8275d35d	2887	* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
<>	135:176b8275d35d	2888	* TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
<>	135:176b8275d35d	2889	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2890	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2891	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2892	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2893	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2894	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2895	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2896	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2897	* @retval None
<>	135:176b8275d35d	2898	*/
<>	135:176b8275d35d	2899	__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2900	{
<>	135:176b8275d35d	2901	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2902	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2903	CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
<>	135:176b8275d35d	2904	}
<>	135:176b8275d35d	2905
<>	135:176b8275d35d	2906	/**
<>	135:176b8275d35d	2907	* @brief Indicate whether the timer reset when receiving a synchronization input event.
<>	135:176b8275d35d	2908	* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
<>	135:176b8275d35d	2909	* TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
<>	135:176b8275d35d	2910	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2911	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2912	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2913	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2914	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2915	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2916	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2917	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2918	* @retval None
<>	135:176b8275d35d	2919	*/
<>	135:176b8275d35d	2920	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2921	{
<>	135:176b8275d35d	2922	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2923	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2924	return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM);
<>	135:176b8275d35d	2925	}
<>	135:176b8275d35d	2926
<>	135:176b8275d35d	2927	/**
<>	135:176b8275d35d	2928	* @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
<>	135:176b8275d35d	2929	* @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
<>	135:176b8275d35d	2930	* TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
<>	135:176b8275d35d	2931	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2932	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2933	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2934	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2935	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2936	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2937	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2938	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2939	* @param DACTrig This parameter can be one of the following values:
<>	135:176b8275d35d	2940	* @arg @ref LL_HRTIM_DACTRIG_NONE
<>	135:176b8275d35d	2941	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
<>	135:176b8275d35d	2942	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
<>	135:176b8275d35d	2943	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
<>	135:176b8275d35d	2944	* @retval None
<>	135:176b8275d35d	2945	*/
<>	135:176b8275d35d	2946	__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
<>	135:176b8275d35d	2947	{
<>	135:176b8275d35d	2948	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2949	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2950	MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
<>	135:176b8275d35d	2951	}
<>	135:176b8275d35d	2952
<>	135:176b8275d35d	2953	/**
<>	135:176b8275d35d	2954	* @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
<>	135:176b8275d35d	2955	* @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
<>	135:176b8275d35d	2956	* TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
<>	135:176b8275d35d	2957	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2958	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2959	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2960	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2961	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2962	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2963	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2964	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2965	* @retval DACTrig Returned value can be one of the following values:
<>	135:176b8275d35d	2966	* @arg @ref LL_HRTIM_DACTRIG_NONE
<>	135:176b8275d35d	2967	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
<>	135:176b8275d35d	2968	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
<>	135:176b8275d35d	2969	* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
<>	135:176b8275d35d	2970	*/
<>	135:176b8275d35d	2971	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2972	{
<>	135:176b8275d35d	2973	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2974	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2975	return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
<>	135:176b8275d35d	2976	}
<>	135:176b8275d35d	2977
<>	135:176b8275d35d	2978	/**
<>	135:176b8275d35d	2979	* @brief Enable the timer registers preload mechanism.
<>	135:176b8275d35d	2980	* @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
<>	135:176b8275d35d	2981	* TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
<>	135:176b8275d35d	2982	* @note When the preload mode is enabled, accessed registers are shadow registers.
<>	135:176b8275d35d	2983	* Their content is transferred into the active register after an update request,
<>	135:176b8275d35d	2984	* either software or synchronized with an event.
<>	135:176b8275d35d	2985	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	2986	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	2987	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	2988	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	2989	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	2990	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	2991	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	2992	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	2993	* @retval None
<>	135:176b8275d35d	2994	*/
<>	135:176b8275d35d	2995	__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	2996	{
<>	135:176b8275d35d	2997	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	2998	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	2999	SET_BIT(*pReg, HRTIM_MCR_PREEN);
<>	135:176b8275d35d	3000	}
<>	135:176b8275d35d	3001
<>	135:176b8275d35d	3002	/**
<>	135:176b8275d35d	3003	* @brief Disable the timer registers preload mechanism.
<>	135:176b8275d35d	3004	* @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
<>	135:176b8275d35d	3005	* TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
<>	135:176b8275d35d	3006	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3007	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3008	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3009	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3010	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3011	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3012	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3013	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3014	* @retval None
<>	135:176b8275d35d	3015	*/
<>	135:176b8275d35d	3016	__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3017	{
<>	135:176b8275d35d	3018	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3019	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3020	CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
<>	135:176b8275d35d	3021	}
<>	135:176b8275d35d	3022
<>	135:176b8275d35d	3023	/**
<>	135:176b8275d35d	3024	* @brief Indicate whether the timer registers preload mechanism is enabled.
<>	135:176b8275d35d	3025	* @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
<>	135:176b8275d35d	3026	* TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
<>	135:176b8275d35d	3027	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3028	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3029	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3030	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3031	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3032	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3033	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3034	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3035	* @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
<>	135:176b8275d35d	3036	*/
<>	135:176b8275d35d	3037	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3038	{
<>	135:176b8275d35d	3039	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3040	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3041	return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN);
<>	135:176b8275d35d	3042	}
<>	135:176b8275d35d	3043
<>	135:176b8275d35d	3044	/**
<>	135:176b8275d35d	3045	* @brief Set the timer register update trigger.
<>	135:176b8275d35d	3046	* @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3047	* TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3048	* TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3049	* TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3050	* TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3051	* TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
<>	135:176b8275d35d	3052	* TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
<>	135:176b8275d35d	3053	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3054	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3055	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3056	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3057	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3058	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3059	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3060	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3061	* @param UpdateTrig This parameter can be one of the following values:
<>	135:176b8275d35d	3062	*
<>	135:176b8275d35d	3063	* For the master timer this parameter can be one of the following values:
<>	135:176b8275d35d	3064	* @arg @ref LL_HRTIM_UPDATETRIG_NONE
<>	135:176b8275d35d	3065	* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
<>	135:176b8275d35d	3066	*
<>	135:176b8275d35d	3067	* For timer A..E this parameter can be:
<>	135:176b8275d35d	3068	* @arg @ref LL_HRTIM_UPDATETRIG_NONE
<>	135:176b8275d35d	3069	* or a combination of the following values:
<>	135:176b8275d35d	3070	* @arg @ref LL_HRTIM_UPDATETRIG_MASTER
<>	135:176b8275d35d	3071	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
<>	135:176b8275d35d	3072	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
<>	135:176b8275d35d	3073	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
<>	135:176b8275d35d	3074	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
<>	135:176b8275d35d	3075	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
<>	135:176b8275d35d	3076	* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
<>	135:176b8275d35d	3077	* @arg @ref LL_HRTIM_UPDATETRIG_RESET
<>	135:176b8275d35d	3078	* @retval None
<>	135:176b8275d35d	3079	*/
<>	135:176b8275d35d	3080	__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
<>	135:176b8275d35d	3081	{
<>	135:176b8275d35d	3082	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3083	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3084	MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
<>	135:176b8275d35d	3085	}
<>	135:176b8275d35d	3086
<>	135:176b8275d35d	3087	/**
<>	135:176b8275d35d	3088	* @brief Set the timer register update trigger.
<>	135:176b8275d35d	3089	* @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
<>	135:176b8275d35d	3090	* TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
<>	135:176b8275d35d	3091	* TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
<>	135:176b8275d35d	3092	* TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
<>	135:176b8275d35d	3093	* TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
<>	135:176b8275d35d	3094	* TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
<>	135:176b8275d35d	3095	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3096	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3097	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3098	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3099	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3100	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3101	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3102	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3103	* @retval UpdateTrig Returned value can be one of the following values:
<>	135:176b8275d35d	3104	*
<>	135:176b8275d35d	3105	* For the master timer this parameter can be one of the following values:
<>	135:176b8275d35d	3106	* @arg @ref LL_HRTIM_UPDATETRIG_NONE
<>	135:176b8275d35d	3107	* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
<>	135:176b8275d35d	3108	*
<>	135:176b8275d35d	3109	* For timer A..E this parameter can be:
<>	135:176b8275d35d	3110	* @arg @ref LL_HRTIM_UPDATETRIG_NONE
<>	135:176b8275d35d	3111	* or a combination of the following values:
<>	135:176b8275d35d	3112	* @arg @ref LL_HRTIM_UPDATETRIG_MASTER
<>	135:176b8275d35d	3113	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
<>	135:176b8275d35d	3114	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
<>	135:176b8275d35d	3115	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
<>	135:176b8275d35d	3116	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
<>	135:176b8275d35d	3117	* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
<>	135:176b8275d35d	3118	* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
<>	135:176b8275d35d	3119	* @arg @ref LL_HRTIM_UPDATETRIG_RESET
<>	135:176b8275d35d	3120	*/
<>	135:176b8275d35d	3121	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3122	{
<>	135:176b8275d35d	3123	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3124	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3125	return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
<>	135:176b8275d35d	3126	}
<>	135:176b8275d35d	3127
<>	135:176b8275d35d	3128	/**
<>	135:176b8275d35d	3129	* @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
<>	135:176b8275d35d	3130	* @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
<>	135:176b8275d35d	3131	* TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
<>	135:176b8275d35d	3132	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3133	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3134	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3135	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3136	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3137	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3138	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3139	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3140	* @param UpdateGating This parameter can be one of the following values:
<>	135:176b8275d35d	3141	*
<>	135:176b8275d35d	3142	* For the master timer this parameter can be one of the following values:
<>	135:176b8275d35d	3143	* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
<>	135:176b8275d35d	3144	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
<>	135:176b8275d35d	3145	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
<>	135:176b8275d35d	3146	*
<>	135:176b8275d35d	3147	* For the timer A..E this parameter can be one of the following values:
<>	135:176b8275d35d	3148	* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
<>	135:176b8275d35d	3149	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
<>	135:176b8275d35d	3150	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
<>	135:176b8275d35d	3151	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
<>	135:176b8275d35d	3152	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
<>	135:176b8275d35d	3153	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
<>	135:176b8275d35d	3154	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
<>	135:176b8275d35d	3155	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
<>	135:176b8275d35d	3156	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
<>	135:176b8275d35d	3157	* @retval None
<>	135:176b8275d35d	3158	*/
<>	135:176b8275d35d	3159	__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
<>	135:176b8275d35d	3160	{
<>	135:176b8275d35d	3161	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3162	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3163	MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
<>	135:176b8275d35d	3164	}
<>	135:176b8275d35d	3165
<>	135:176b8275d35d	3166	/**
<>	135:176b8275d35d	3167	* @brief Get the timer registers update condition.
<>	135:176b8275d35d	3168	* @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
<>	135:176b8275d35d	3169	* TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
<>	135:176b8275d35d	3170	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3171	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3172	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3173	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3174	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3175	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3176	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3177	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3178	* @retval UpdateGating Returned value can be one of the following values:
<>	135:176b8275d35d	3179	*
<>	135:176b8275d35d	3180	* For the master timer this parameter can be one of the following values:
<>	135:176b8275d35d	3181	* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
<>	135:176b8275d35d	3182	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
<>	135:176b8275d35d	3183	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
<>	135:176b8275d35d	3184	*
<>	135:176b8275d35d	3185	* For the timer A..E this parameter can be one of the following values:
<>	135:176b8275d35d	3186	* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
<>	135:176b8275d35d	3187	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
<>	135:176b8275d35d	3188	* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
<>	135:176b8275d35d	3189	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
<>	135:176b8275d35d	3190	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
<>	135:176b8275d35d	3191	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
<>	135:176b8275d35d	3192	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
<>	135:176b8275d35d	3193	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
<>	135:176b8275d35d	3194	* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
<>	135:176b8275d35d	3195	*/
<>	135:176b8275d35d	3196	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3197	{
<>	135:176b8275d35d	3198	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3199	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3200	return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
<>	135:176b8275d35d	3201	}
<>	135:176b8275d35d	3202
<>	135:176b8275d35d	3203	/**
<>	135:176b8275d35d	3204	* @brief Enable the push-pull mode.
<>	135:176b8275d35d	3205	* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
<>	135:176b8275d35d	3206	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3207	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3208	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3209	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3210	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3211	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3212	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3213	* @retval None
<>	135:176b8275d35d	3214	*/
<>	135:176b8275d35d	3215	__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3216	{
<>	135:176b8275d35d	3217	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3218	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
<>	135:176b8275d35d	3219	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3220	SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
<>	135:176b8275d35d	3221	}
<>	135:176b8275d35d	3222
<>	135:176b8275d35d	3223	/**
<>	135:176b8275d35d	3224	* @brief Disable the push-pull mode.
<>	135:176b8275d35d	3225	* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
<>	135:176b8275d35d	3226	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3227	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3228	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3229	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3230	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3231	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3232	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3233	* @retval None
<>	135:176b8275d35d	3234	*/
<>	135:176b8275d35d	3235	__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3236	{
<>	135:176b8275d35d	3237	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3238	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
<>	135:176b8275d35d	3239	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3240	CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
<>	135:176b8275d35d	3241	}
<>	135:176b8275d35d	3242
<>	135:176b8275d35d	3243	/**
<>	135:176b8275d35d	3244	* @brief Indicate whether the push-pull mode is enabled.
<>	135:176b8275d35d	3245	* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
<>	135:176b8275d35d	3246	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3247	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3248	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3249	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3250	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3251	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3252	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3253	* @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
<>	135:176b8275d35d	3254	*/
<>	135:176b8275d35d	3255	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3256	{
<>	135:176b8275d35d	3257	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3258	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
<>	135:176b8275d35d	3259	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3260	return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL);
<>	135:176b8275d35d	3261	}
<>	135:176b8275d35d	3262
<>	135:176b8275d35d	3263	/**
<>	135:176b8275d35d	3264	* @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
<>	135:176b8275d35d	3265	* @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
<>	135:176b8275d35d	3266	* TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
<>	135:176b8275d35d	3267	* @note In auto-delayed mode the compare match occurs independently from the timer counter value.
<>	135:176b8275d35d	3268	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3269	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3270	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3271	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3272	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3273	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3274	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3275	* @param CompareUnit This parameter can be one of the following values:
<>	135:176b8275d35d	3276	* @arg @ref LL_HRTIM_COMPAREUNIT_2
<>	135:176b8275d35d	3277	* @arg @ref LL_HRTIM_COMPAREUNIT_4
<>	135:176b8275d35d	3278	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	3279	* @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
<>	135:176b8275d35d	3280	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
<>	135:176b8275d35d	3281	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
<>	135:176b8275d35d	3282	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
<>	135:176b8275d35d	3283	* @retval None
<>	135:176b8275d35d	3284	*/
<>	135:176b8275d35d	3285	__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
<>	135:176b8275d35d	3286	uint32_t Mode)
<>	135:176b8275d35d	3287	{
<>	135:176b8275d35d	3288	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3289	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
<>	135:176b8275d35d	3290	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3291	register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
<>	135:176b8275d35d	3292	MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
<>	135:176b8275d35d	3293	}
<>	135:176b8275d35d	3294
<>	135:176b8275d35d	3295	/**
<>	135:176b8275d35d	3296	* @brief Get the functioning mode of the compare unit.
<>	135:176b8275d35d	3297	* @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
<>	135:176b8275d35d	3298	* TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
<>	135:176b8275d35d	3299	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3300	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3301	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3302	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3303	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3304	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3305	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3306	* @param CompareUnit This parameter can be one of the following values:
<>	135:176b8275d35d	3307	* @arg @ref LL_HRTIM_COMPAREUNIT_2
<>	135:176b8275d35d	3308	* @arg @ref LL_HRTIM_COMPAREUNIT_4
<>	135:176b8275d35d	3309	* @retval Mode Returned value can be one of the following values:
<>	135:176b8275d35d	3310	* @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
<>	135:176b8275d35d	3311	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
<>	135:176b8275d35d	3312	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
<>	135:176b8275d35d	3313	* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
<>	135:176b8275d35d	3314	*/
<>	135:176b8275d35d	3315	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
<>	135:176b8275d35d	3316	{
<>	135:176b8275d35d	3317	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3318	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
<>	135:176b8275d35d	3319	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3320	register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
<>	135:176b8275d35d	3321	return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
<>	135:176b8275d35d	3322	}
<>	135:176b8275d35d	3323
<>	135:176b8275d35d	3324	/**
<>	135:176b8275d35d	3325	* @brief Set the timer counter value.
<>	135:176b8275d35d	3326	* @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
<>	135:176b8275d35d	3327	* CNTxR CNTx LL_HRTIM_TIM_SetCounter
<>	135:176b8275d35d	3328	* @note This function can only be called when the timer is stopped.
<>	135:176b8275d35d	3329	* @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
<>	135:176b8275d35d	3330	* significant bits of the counter are not significant. They cannot be
<>	135:176b8275d35d	3331	* written and return 0 when read.
<>	135:176b8275d35d	3332	* @note The timer behavior is not guaranteed if the counter value is set above
<>	135:176b8275d35d	3333	* the period.
<>	135:176b8275d35d	3334	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3335	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3336	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3337	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3338	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3339	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3340	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3341	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3342	* @param Counter Value between 0 and 0xFFFF
<>	135:176b8275d35d	3343	* @retval None
<>	135:176b8275d35d	3344	*/
<>	135:176b8275d35d	3345	__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
<>	135:176b8275d35d	3346	{
<>	135:176b8275d35d	3347	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3348	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
<>	135:176b8275d35d	3349	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3350	MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
<>	135:176b8275d35d	3351	}
<>	135:176b8275d35d	3352
<>	135:176b8275d35d	3353	/**
<>	135:176b8275d35d	3354	* @brief Get actual timer counter value.
<>	135:176b8275d35d	3355	* @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
<>	135:176b8275d35d	3356	* CNTxR CNTx LL_HRTIM_TIM_GetCounter
<>	135:176b8275d35d	3357	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3358	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3359	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3360	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3361	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3362	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3363	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3364	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3365	* @retval Counter Value between 0 and 0xFFFF
<>	135:176b8275d35d	3366	*/
<>	135:176b8275d35d	3367	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3368	{
<>	135:176b8275d35d	3369	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3370	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
<>	135:176b8275d35d	3371	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3372	return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
<>	135:176b8275d35d	3373	}
<>	135:176b8275d35d	3374
<>	135:176b8275d35d	3375	/**
<>	135:176b8275d35d	3376	* @brief Set the timer period value.
<>	135:176b8275d35d	3377	* @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
<>	135:176b8275d35d	3378	* PERxR PERx LL_HRTIM_TIM_SetPeriod
<>	135:176b8275d35d	3379	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3380	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3381	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3382	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3383	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3384	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3385	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3386	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3387	* @param Period Value between 0 and 0xFFFF
<>	135:176b8275d35d	3388	* @retval None
<>	135:176b8275d35d	3389	*/
<>	135:176b8275d35d	3390	__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
<>	135:176b8275d35d	3391	{
<>	135:176b8275d35d	3392	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3393	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
<>	135:176b8275d35d	3394	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3395	MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
<>	135:176b8275d35d	3396	}
<>	135:176b8275d35d	3397
<>	135:176b8275d35d	3398	/**
<>	135:176b8275d35d	3399	* @brief Get actual timer period value.
<>	135:176b8275d35d	3400	* @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
<>	135:176b8275d35d	3401	* PERxR PERx LL_HRTIM_TIM_GetPeriod
<>	135:176b8275d35d	3402	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3403	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3404	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3405	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3406	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3407	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3408	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3409	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3410	* @retval Period Value between 0 and 0xFFFF
<>	135:176b8275d35d	3411	*/
<>	135:176b8275d35d	3412	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3413	{
<>	135:176b8275d35d	3414	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3415	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
<>	135:176b8275d35d	3416	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3417	return (READ_BIT(*pReg, HRTIM_MPER_MPER));
<>	135:176b8275d35d	3418	}
<>	135:176b8275d35d	3419
<>	135:176b8275d35d	3420	/**
<>	135:176b8275d35d	3421	* @brief Set the timer repetition period value.
<>	135:176b8275d35d	3422	* @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
<>	135:176b8275d35d	3423	* REPxR REPx LL_HRTIM_TIM_SetRepetition
<>	135:176b8275d35d	3424	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3425	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3426	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3427	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3428	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3429	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3430	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3431	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3432	* @param Repetition Value between 0 and 0xFF
<>	135:176b8275d35d	3433	* @retval None
<>	135:176b8275d35d	3434	*/
<>	135:176b8275d35d	3435	__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
<>	135:176b8275d35d	3436	{
<>	135:176b8275d35d	3437	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3438	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
<>	135:176b8275d35d	3439	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3440	MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
<>	135:176b8275d35d	3441	}
<>	135:176b8275d35d	3442
<>	135:176b8275d35d	3443	/**
<>	135:176b8275d35d	3444	* @brief Get actual timer repetition period value.
<>	135:176b8275d35d	3445	* @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
<>	135:176b8275d35d	3446	* REPxR REPx LL_HRTIM_TIM_GetRepetition
<>	135:176b8275d35d	3447	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3448	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3449	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3450	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3451	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3452	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3453	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3454	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3455	* @retval Repetition Value between 0 and 0xFF
<>	135:176b8275d35d	3456	*/
<>	135:176b8275d35d	3457	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3458	{
<>	135:176b8275d35d	3459	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3460	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
<>	135:176b8275d35d	3461	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3462	return (READ_BIT(*pReg, HRTIM_MREP_MREP));
<>	135:176b8275d35d	3463	}
<>	135:176b8275d35d	3464
<>	135:176b8275d35d	3465	/**
<>	135:176b8275d35d	3466	* @brief Set the compare value of the compare unit 1.
<>	135:176b8275d35d	3467	* @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
<>	135:176b8275d35d	3468	* CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
<>	135:176b8275d35d	3469	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3470	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3471	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3472	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3473	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3474	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3475	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3476	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3477	* @param CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3478	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3479	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3480	* @retval None
<>	135:176b8275d35d	3481	*/
<>	135:176b8275d35d	3482	__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
<>	135:176b8275d35d	3483	{
<>	135:176b8275d35d	3484	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3485	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
<>	135:176b8275d35d	3486	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3487	MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
<>	135:176b8275d35d	3488	}
<>	135:176b8275d35d	3489
<>	135:176b8275d35d	3490	/**
<>	135:176b8275d35d	3491	* @brief Get actual compare value of the compare unit 1.
<>	135:176b8275d35d	3492	* @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
<>	135:176b8275d35d	3493	* CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
<>	135:176b8275d35d	3494	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3495	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3496	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3497	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3498	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3499	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3500	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3501	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3502	* @retval CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3503	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3504	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3505	*/
<>	135:176b8275d35d	3506	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3507	{
<>	135:176b8275d35d	3508	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3509	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
<>	135:176b8275d35d	3510	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3511	return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
<>	135:176b8275d35d	3512	}
<>	135:176b8275d35d	3513
<>	135:176b8275d35d	3514	/**
<>	135:176b8275d35d	3515	* @brief Set the compare value of the compare unit 2.
<>	135:176b8275d35d	3516	* @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
<>	135:176b8275d35d	3517	* CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
<>	135:176b8275d35d	3518	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3519	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3520	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3521	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3522	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3523	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3524	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3525	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3526	* @param CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3527	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3528	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3529	* @retval None
<>	135:176b8275d35d	3530	*/
<>	135:176b8275d35d	3531	__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
<>	135:176b8275d35d	3532	{
<>	135:176b8275d35d	3533	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3534	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
<>	135:176b8275d35d	3535	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3536	MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
<>	135:176b8275d35d	3537	}
<>	135:176b8275d35d	3538
<>	135:176b8275d35d	3539	/**
<>	135:176b8275d35d	3540	* @brief Get actual compare value of the compare unit 2.
<>	135:176b8275d35d	3541	* @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
<>	135:176b8275d35d	3542	* CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
<>	135:176b8275d35d	3543	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3544	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3545	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3546	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3547	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3548	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3549	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3550	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3551	* @retval CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3552	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3553	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3554	*/
<>	135:176b8275d35d	3555	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3556	{
<>	135:176b8275d35d	3557	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3558	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
<>	135:176b8275d35d	3559	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3560	return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
<>	135:176b8275d35d	3561	}
<>	135:176b8275d35d	3562
<>	135:176b8275d35d	3563	/**
<>	135:176b8275d35d	3564	* @brief Set the compare value of the compare unit 3.
<>	135:176b8275d35d	3565	* @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
<>	135:176b8275d35d	3566	* CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
<>	135:176b8275d35d	3567	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3568	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3569	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3570	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3571	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3572	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3573	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3574	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3575	* @param CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3576	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3577	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3578	* @retval None
<>	135:176b8275d35d	3579	*/
<>	135:176b8275d35d	3580	__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
<>	135:176b8275d35d	3581	{
<>	135:176b8275d35d	3582	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3583	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
<>	135:176b8275d35d	3584	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3585	MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
<>	135:176b8275d35d	3586	}
<>	135:176b8275d35d	3587
<>	135:176b8275d35d	3588	/**
<>	135:176b8275d35d	3589	* @brief Get actual compare value of the compare unit 3.
<>	135:176b8275d35d	3590	* @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
<>	135:176b8275d35d	3591	* CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
<>	135:176b8275d35d	3592	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3593	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3594	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3595	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3596	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3597	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3598	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3599	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3600	* @retval CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3601	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3602	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3603	*/
<>	135:176b8275d35d	3604	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3605	{
<>	135:176b8275d35d	3606	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3607	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
<>	135:176b8275d35d	3608	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3609	return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
<>	135:176b8275d35d	3610	}
<>	135:176b8275d35d	3611
<>	135:176b8275d35d	3612	/**
<>	135:176b8275d35d	3613	* @brief Set the compare value of the compare unit 4.
<>	135:176b8275d35d	3614	* @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
<>	135:176b8275d35d	3615	* CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
<>	135:176b8275d35d	3616	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3617	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3618	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3619	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3620	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3621	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3622	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3623	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3624	* @param CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3625	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3626	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3627	* @retval None
<>	135:176b8275d35d	3628	*/
<>	135:176b8275d35d	3629	__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
<>	135:176b8275d35d	3630	{
<>	135:176b8275d35d	3631	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3632	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
<>	135:176b8275d35d	3633	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3634	MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
<>	135:176b8275d35d	3635	}
<>	135:176b8275d35d	3636
<>	135:176b8275d35d	3637	/**
<>	135:176b8275d35d	3638	* @brief Get actual compare value of the compare unit 4.
<>	135:176b8275d35d	3639	* @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
<>	135:176b8275d35d	3640	* CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
<>	135:176b8275d35d	3641	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3642	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3643	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	3644	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3645	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3646	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3647	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3648	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3649	* @retval CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	3650	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	3651	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	3652	*/
<>	135:176b8275d35d	3653	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3654	{
<>	135:176b8275d35d	3655	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	3656	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
<>	135:176b8275d35d	3657	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3658	return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
<>	135:176b8275d35d	3659	}
<>	135:176b8275d35d	3660
<>	135:176b8275d35d	3661	/**
<>	135:176b8275d35d	3662	* @brief Set the reset trigger of a timer counter.
<>	135:176b8275d35d	3663	* @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3664	* RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3665	* RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3666	* RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3667	* RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3668	* RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3669	* RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3670	* RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3671	* RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3672	* RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3673	* RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3674	* RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3675	* RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3676	* RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3677	* RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3678	* RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3679	* RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3680	* RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3681	* RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3682	* RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3683	* RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3684	* RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3685	* RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3686	* RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3687	* RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3688	* RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3689	* RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3690	* RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3691	* RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
<>	135:176b8275d35d	3692	* RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
<>	135:176b8275d35d	3693	* @note The reset of the timer counter can be triggered by up to 30 events
<>	135:176b8275d35d	3694	* that can be selected among the following sources:
<>	135:176b8275d35d	3695	* @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
<>	135:176b8275d35d	3696	* @arg The master timer: Reset and Compare 1..4 (5 events).
<>	135:176b8275d35d	3697	* @arg The external events EXTEVNT1..10 (10 events).
<>	135:176b8275d35d	3698	* @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
<>	135:176b8275d35d	3699	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3700	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3701	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3702	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3703	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3704	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3705	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3706	* @param ResetTrig This parameter can be a combination of the following values:
<>	135:176b8275d35d	3707	* @arg @ref LL_HRTIM_RESETTRIG_NONE
<>	135:176b8275d35d	3708	* @arg @ref LL_HRTIM_RESETTRIG_UPDATE
<>	135:176b8275d35d	3709	* @arg @ref LL_HRTIM_RESETTRIG_CMP2
<>	135:176b8275d35d	3710	* @arg @ref LL_HRTIM_RESETTRIG_CMP4
<>	135:176b8275d35d	3711	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
<>	135:176b8275d35d	3712	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
<>	135:176b8275d35d	3713	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
<>	135:176b8275d35d	3714	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
<>	135:176b8275d35d	3715	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
<>	135:176b8275d35d	3716	* @arg @ref LL_HRTIM_RESETTRIG_EEV_1
<>	135:176b8275d35d	3717	* @arg @ref LL_HRTIM_RESETTRIG_EEV_2
<>	135:176b8275d35d	3718	* @arg @ref LL_HRTIM_RESETTRIG_EEV_3
<>	135:176b8275d35d	3719	* @arg @ref LL_HRTIM_RESETTRIG_EEV_4
<>	135:176b8275d35d	3720	* @arg @ref LL_HRTIM_RESETTRIG_EEV_5
<>	135:176b8275d35d	3721	* @arg @ref LL_HRTIM_RESETTRIG_EEV_6
<>	135:176b8275d35d	3722	* @arg @ref LL_HRTIM_RESETTRIG_EEV_7
<>	135:176b8275d35d	3723	* @arg @ref LL_HRTIM_RESETTRIG_EEV_8
<>	135:176b8275d35d	3724	* @arg @ref LL_HRTIM_RESETTRIG_EEV_9
<>	135:176b8275d35d	3725	* @arg @ref LL_HRTIM_RESETTRIG_EEV_10
<>	135:176b8275d35d	3726	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
<>	135:176b8275d35d	3727	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
<>	135:176b8275d35d	3728	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
<>	135:176b8275d35d	3729	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
<>	135:176b8275d35d	3730	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
<>	135:176b8275d35d	3731	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
<>	135:176b8275d35d	3732	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
<>	135:176b8275d35d	3733	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
<>	135:176b8275d35d	3734	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
<>	135:176b8275d35d	3735	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
<>	135:176b8275d35d	3736	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
<>	135:176b8275d35d	3737	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
<>	135:176b8275d35d	3738	* @retval None
<>	135:176b8275d35d	3739	*/
<>	135:176b8275d35d	3740	__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
<>	135:176b8275d35d	3741	{
<>	135:176b8275d35d	3742	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3743	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
<>	135:176b8275d35d	3744	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3745	WRITE_REG(*pReg, ResetTrig);
<>	135:176b8275d35d	3746	}
<>	135:176b8275d35d	3747
<>	135:176b8275d35d	3748	/**
<>	135:176b8275d35d	3749	* @brief Get actual reset trigger of a timer counter.
<>	135:176b8275d35d	3750	* @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3751	* RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3752	* RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3753	* RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3754	* RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3755	* RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3756	* RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3757	* RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3758	* RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3759	* RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3760	* RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3761	* RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3762	* RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3763	* RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3764	* RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3765	* RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3766	* RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3767	* RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3768	* RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3769	* RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3770	* RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3771	* RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3772	* RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3773	* RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3774	* RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3775	* RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3776	* RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3777	* RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3778	* RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
<>	135:176b8275d35d	3779	* RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
<>	135:176b8275d35d	3780	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3781	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3782	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3783	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3784	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3785	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3786	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3787	* @retval ResetTrig Returned value can be one of the following values:
<>	135:176b8275d35d	3788	* @arg @ref LL_HRTIM_RESETTRIG_NONE
<>	135:176b8275d35d	3789	* @arg @ref LL_HRTIM_RESETTRIG_UPDATE
<>	135:176b8275d35d	3790	* @arg @ref LL_HRTIM_RESETTRIG_CMP2
<>	135:176b8275d35d	3791	* @arg @ref LL_HRTIM_RESETTRIG_CMP4
<>	135:176b8275d35d	3792	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
<>	135:176b8275d35d	3793	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
<>	135:176b8275d35d	3794	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
<>	135:176b8275d35d	3795	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
<>	135:176b8275d35d	3796	* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
<>	135:176b8275d35d	3797	* @arg @ref LL_HRTIM_RESETTRIG_EEV_1
<>	135:176b8275d35d	3798	* @arg @ref LL_HRTIM_RESETTRIG_EEV_2
<>	135:176b8275d35d	3799	* @arg @ref LL_HRTIM_RESETTRIG_EEV_3
<>	135:176b8275d35d	3800	* @arg @ref LL_HRTIM_RESETTRIG_EEV_4
<>	135:176b8275d35d	3801	* @arg @ref LL_HRTIM_RESETTRIG_EEV_5
<>	135:176b8275d35d	3802	* @arg @ref LL_HRTIM_RESETTRIG_EEV_6
<>	135:176b8275d35d	3803	* @arg @ref LL_HRTIM_RESETTRIG_EEV_7
<>	135:176b8275d35d	3804	* @arg @ref LL_HRTIM_RESETTRIG_EEV_8
<>	135:176b8275d35d	3805	* @arg @ref LL_HRTIM_RESETTRIG_EEV_9
<>	135:176b8275d35d	3806	* @arg @ref LL_HRTIM_RESETTRIG_EEV_10
<>	135:176b8275d35d	3807	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
<>	135:176b8275d35d	3808	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
<>	135:176b8275d35d	3809	* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
<>	135:176b8275d35d	3810	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
<>	135:176b8275d35d	3811	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
<>	135:176b8275d35d	3812	* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
<>	135:176b8275d35d	3813	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
<>	135:176b8275d35d	3814	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
<>	135:176b8275d35d	3815	* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
<>	135:176b8275d35d	3816	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
<>	135:176b8275d35d	3817	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
<>	135:176b8275d35d	3818	* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
<>	135:176b8275d35d	3819	*/
<>	135:176b8275d35d	3820	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3821	{
<>	135:176b8275d35d	3822	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3823	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
<>	135:176b8275d35d	3824	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3825	return (READ_REG(*pReg));
<>	135:176b8275d35d	3826	}
<>	135:176b8275d35d	3827
<>	135:176b8275d35d	3828	/**
<>	135:176b8275d35d	3829	* @brief Get captured value for capture unit 1.
<>	135:176b8275d35d	3830	* @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
<>	135:176b8275d35d	3831	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3832	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3833	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3834	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3835	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3836	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3837	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3838	* @retval Captured value
<>	135:176b8275d35d	3839	*/
<>	135:176b8275d35d	3840	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3841	{
<>	135:176b8275d35d	3842	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3843	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
<>	135:176b8275d35d	3844	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3845	return (READ_REG(*pReg));
<>	135:176b8275d35d	3846	}
<>	135:176b8275d35d	3847
<>	135:176b8275d35d	3848	/**
<>	135:176b8275d35d	3849	* @brief Get captured value for capture unit 2.
<>	135:176b8275d35d	3850	* @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
<>	135:176b8275d35d	3851	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3852	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3853	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3854	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3855	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3856	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3857	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3858	* @retval Captured value
<>	135:176b8275d35d	3859	*/
<>	135:176b8275d35d	3860	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	3861	{
<>	135:176b8275d35d	3862	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3863	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
<>	135:176b8275d35d	3864	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	3865	return (READ_REG(*pReg));
<>	135:176b8275d35d	3866	}
<>	135:176b8275d35d	3867
<>	135:176b8275d35d	3868	/**
<>	135:176b8275d35d	3869	* @brief Set the trigger of a capture unit for a given timer.
<>	135:176b8275d35d	3870	* @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3871	* CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3872	* CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3873	* CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3874	* CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3875	* CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3876	* CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3877	* CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3878	* CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3879	* CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3880	* CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3881	* CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3882	* CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3883	* CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3884	* CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3885	* CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3886	* CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3887	* CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3888	* CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3889	* CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3890	* CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3891	* CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3892	* CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3893	* CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3894	* CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3895	* CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3896	* CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3897	* CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3898	* CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3899	* CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3900	* CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
<>	135:176b8275d35d	3901	* CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
<>	135:176b8275d35d	3902	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3903	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3904	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3905	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3906	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3907	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3908	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3909	* @param CaptureUnit This parameter can be one of the following values:
<>	135:176b8275d35d	3910	* @arg @ref LL_HRTIM_CAPTUREUNIT_1
<>	135:176b8275d35d	3911	* @arg @ref LL_HRTIM_CAPTUREUNIT_2
<>	135:176b8275d35d	3912	* @param CaptureTrig This parameter can be a combination of the following values:
<>	135:176b8275d35d	3913	* @arg @ref LL_HRTIM_CAPTURETRIG_NONE
<>	135:176b8275d35d	3914	* @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
<>	135:176b8275d35d	3915	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
<>	135:176b8275d35d	3916	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
<>	135:176b8275d35d	3917	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
<>	135:176b8275d35d	3918	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
<>	135:176b8275d35d	3919	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
<>	135:176b8275d35d	3920	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
<>	135:176b8275d35d	3921	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
<>	135:176b8275d35d	3922	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
<>	135:176b8275d35d	3923	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
<>	135:176b8275d35d	3924	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
<>	135:176b8275d35d	3925	* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
<>	135:176b8275d35d	3926	* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
<>	135:176b8275d35d	3927	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
<>	135:176b8275d35d	3928	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
<>	135:176b8275d35d	3929	* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
<>	135:176b8275d35d	3930	* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
<>	135:176b8275d35d	3931	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
<>	135:176b8275d35d	3932	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
<>	135:176b8275d35d	3933	* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
<>	135:176b8275d35d	3934	* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
<>	135:176b8275d35d	3935	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
<>	135:176b8275d35d	3936	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
<>	135:176b8275d35d	3937	* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
<>	135:176b8275d35d	3938	* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
<>	135:176b8275d35d	3939	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
<>	135:176b8275d35d	3940	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
<>	135:176b8275d35d	3941	* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
<>	135:176b8275d35d	3942	* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
<>	135:176b8275d35d	3943	* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
<>	135:176b8275d35d	3944	* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
<>	135:176b8275d35d	3945	* @retval None
<>	135:176b8275d35d	3946	*/
<>	135:176b8275d35d	3947	__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
<>	135:176b8275d35d	3948	uint32_t CaptureTrig)
<>	135:176b8275d35d	3949	{
<>	135:176b8275d35d	3950	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	3951	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
<>	135:176b8275d35d	3952	REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
<>	135:176b8275d35d	3953	WRITE_REG(*pReg, CaptureTrig);
<>	135:176b8275d35d	3954	}
<>	135:176b8275d35d	3955
<>	135:176b8275d35d	3956	/**
<>	135:176b8275d35d	3957	* @brief Get actual trigger of a capture unit for a given timer.
<>	135:176b8275d35d	3958	* @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3959	* CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3960	* CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3961	* CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3962	* CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3963	* CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3964	* CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3965	* CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3966	* CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3967	* CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3968	* CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3969	* CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3970	* CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3971	* CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3972	* CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3973	* CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3974	* CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3975	* CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3976	* CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3977	* CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3978	* CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3979	* CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3980	* CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3981	* CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3982	* CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3983	* CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3984	* CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3985	* CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3986	* CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3987	* CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3988	* CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
<>	135:176b8275d35d	3989	* CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
<>	135:176b8275d35d	3990	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	3991	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	3992	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	3993	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	3994	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	3995	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	3996	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	3997	* @param CaptureUnit This parameter can be one of the following values:
<>	135:176b8275d35d	3998	* @arg @ref LL_HRTIM_CAPTUREUNIT_1
<>	135:176b8275d35d	3999	* @arg @ref LL_HRTIM_CAPTUREUNIT_2
<>	135:176b8275d35d	4000	* @retval CaptureTrig This parameter can be a combination of the following values:
<>	135:176b8275d35d	4001	* @arg @ref LL_HRTIM_CAPTURETRIG_NONE
<>	135:176b8275d35d	4002	* @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
<>	135:176b8275d35d	4003	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
<>	135:176b8275d35d	4004	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
<>	135:176b8275d35d	4005	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
<>	135:176b8275d35d	4006	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
<>	135:176b8275d35d	4007	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
<>	135:176b8275d35d	4008	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
<>	135:176b8275d35d	4009	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
<>	135:176b8275d35d	4010	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
<>	135:176b8275d35d	4011	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
<>	135:176b8275d35d	4012	* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
<>	135:176b8275d35d	4013	* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
<>	135:176b8275d35d	4014	* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
<>	135:176b8275d35d	4015	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
<>	135:176b8275d35d	4016	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
<>	135:176b8275d35d	4017	* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
<>	135:176b8275d35d	4018	* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
<>	135:176b8275d35d	4019	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
<>	135:176b8275d35d	4020	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
<>	135:176b8275d35d	4021	* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
<>	135:176b8275d35d	4022	* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
<>	135:176b8275d35d	4023	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
<>	135:176b8275d35d	4024	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
<>	135:176b8275d35d	4025	* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
<>	135:176b8275d35d	4026	* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
<>	135:176b8275d35d	4027	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
<>	135:176b8275d35d	4028	* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
<>	135:176b8275d35d	4029	* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
<>	135:176b8275d35d	4030	* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
<>	135:176b8275d35d	4031	* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
<>	135:176b8275d35d	4032	* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
<>	135:176b8275d35d	4033	*/
<>	135:176b8275d35d	4034	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
<>	135:176b8275d35d	4035	{
<>	135:176b8275d35d	4036	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4037	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
<>	135:176b8275d35d	4038	REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
<>	135:176b8275d35d	4039	return (READ_REG(*pReg));
<>	135:176b8275d35d	4040	}
<>	135:176b8275d35d	4041
<>	135:176b8275d35d	4042	/**
<>	135:176b8275d35d	4043	* @brief Enable deadtime insertion for a given timer.
<>	135:176b8275d35d	4044	* @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
<>	135:176b8275d35d	4045	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4046	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4047	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4048	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4049	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4050	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4051	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4052	* @retval None
<>	135:176b8275d35d	4053	*/
<>	135:176b8275d35d	4054	__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4055	{
<>	135:176b8275d35d	4056	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4057	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4058	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4059	SET_BIT(*pReg, HRTIM_OUTR_DTEN);
<>	135:176b8275d35d	4060	}
<>	135:176b8275d35d	4061
<>	135:176b8275d35d	4062	/**
<>	135:176b8275d35d	4063	* @brief Disable deadtime insertion for a given timer.
<>	135:176b8275d35d	4064	* @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
<>	135:176b8275d35d	4065	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4066	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4067	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4068	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4069	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4070	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4071	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4072	* @retval None
<>	135:176b8275d35d	4073	*/
<>	135:176b8275d35d	4074	__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4075	{
<>	135:176b8275d35d	4076	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4077	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4078	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4079	CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
<>	135:176b8275d35d	4080	}
<>	135:176b8275d35d	4081
<>	135:176b8275d35d	4082	/**
<>	135:176b8275d35d	4083	* @brief Indicate whether deadtime insertion is enabled for a given timer.
<>	135:176b8275d35d	4084	* @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
<>	135:176b8275d35d	4085	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4086	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4087	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4088	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4089	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4090	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4091	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4092	* @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
<>	135:176b8275d35d	4093	*/
<>	135:176b8275d35d	4094	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4095	{
<>	135:176b8275d35d	4096	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4097	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4098	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4099	return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN);
<>	135:176b8275d35d	4100	}
<>	135:176b8275d35d	4101
<>	135:176b8275d35d	4102	/**
<>	135:176b8275d35d	4103	* @brief Set the delayed protection (DLYPRT) mode.
<>	135:176b8275d35d	4104	* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
<>	135:176b8275d35d	4105	* OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
<>	135:176b8275d35d	4106	* @note This function must be called prior enabling the delayed protection
<>	135:176b8275d35d	4107	* @note Balanced Idle mode is only available in push-pull mode
<>	135:176b8275d35d	4108	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4109	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4110	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4111	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4112	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4113	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4114	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4115	* @param DLYPRTMode Delayed protection (DLYPRT) mode
<>	135:176b8275d35d	4116	*
<>	135:176b8275d35d	4117	* For timers A, B and C this parameter can be one of the following vallues:
<>	135:176b8275d35d	4118	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
<>	135:176b8275d35d	4119	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
<>	135:176b8275d35d	4120	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
<>	135:176b8275d35d	4121	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
<>	135:176b8275d35d	4122	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
<>	135:176b8275d35d	4123	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
<>	135:176b8275d35d	4124	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
<>	135:176b8275d35d	4125	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
<>	135:176b8275d35d	4126	*
<>	135:176b8275d35d	4127	* For timers D and E this parameter can be one of the following vallues:
<>	135:176b8275d35d	4128	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
<>	135:176b8275d35d	4129	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
<>	135:176b8275d35d	4130	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
<>	135:176b8275d35d	4131	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
<>	135:176b8275d35d	4132	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
<>	135:176b8275d35d	4133	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
<>	135:176b8275d35d	4134	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
<>	135:176b8275d35d	4135	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
<>	135:176b8275d35d	4136	* @retval None
<>	135:176b8275d35d	4137	*/
<>	135:176b8275d35d	4138	__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
<>	135:176b8275d35d	4139	{
<>	135:176b8275d35d	4140	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4141	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4142	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4143	MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
<>	135:176b8275d35d	4144	}
<>	135:176b8275d35d	4145
<>	135:176b8275d35d	4146	/**
<>	135:176b8275d35d	4147	* @brief Get the delayed protection (DLYPRT) mode.
<>	135:176b8275d35d	4148	* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
<>	135:176b8275d35d	4149	* OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
<>	135:176b8275d35d	4150	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4151	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4152	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4153	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4154	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4155	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4156	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4157	* @retval DLYPRTMode Delayed protection (DLYPRT) mode
<>	135:176b8275d35d	4158	*
<>	135:176b8275d35d	4159	* For timers A, B and C this parameter can be one of the following vallues:
<>	135:176b8275d35d	4160	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
<>	135:176b8275d35d	4161	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
<>	135:176b8275d35d	4162	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
<>	135:176b8275d35d	4163	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
<>	135:176b8275d35d	4164	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
<>	135:176b8275d35d	4165	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
<>	135:176b8275d35d	4166	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
<>	135:176b8275d35d	4167	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
<>	135:176b8275d35d	4168	*
<>	135:176b8275d35d	4169	* For timers D and E this parameter can be one of the following vallues:
<>	135:176b8275d35d	4170	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
<>	135:176b8275d35d	4171	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
<>	135:176b8275d35d	4172	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
<>	135:176b8275d35d	4173	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
<>	135:176b8275d35d	4174	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
<>	135:176b8275d35d	4175	* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
<>	135:176b8275d35d	4176	* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
<>	135:176b8275d35d	4177	* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
<>	135:176b8275d35d	4178	*/
<>	135:176b8275d35d	4179	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4180	{
<>	135:176b8275d35d	4181	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4182	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4183	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4184	return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
<>	135:176b8275d35d	4185	}
<>	135:176b8275d35d	4186
<>	135:176b8275d35d	4187	/**
<>	135:176b8275d35d	4188	* @brief Enable delayed protection (DLYPRT) for a given timer.
<>	135:176b8275d35d	4189	* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
<>	135:176b8275d35d	4190	* @note This function must not be called once the concerned timer is enabled
<>	135:176b8275d35d	4191	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4192	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4193	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4194	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4195	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4196	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4197	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4198	* @retval None
<>	135:176b8275d35d	4199	*/
<>	135:176b8275d35d	4200	__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4201	{
<>	135:176b8275d35d	4202	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4203	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4204	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4205	SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
<>	135:176b8275d35d	4206	}
<>	135:176b8275d35d	4207
<>	135:176b8275d35d	4208	/**
<>	135:176b8275d35d	4209	* @brief Disable delayed protection (DLYPRT) for a given timer.
<>	135:176b8275d35d	4210	* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
<>	135:176b8275d35d	4211	* @note This function must not be called once the concerned timer is enabled
<>	135:176b8275d35d	4212	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4213	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4214	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4215	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4216	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4217	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4218	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4219	* @retval None
<>	135:176b8275d35d	4220	*/
<>	135:176b8275d35d	4221	__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4222	{
<>	135:176b8275d35d	4223	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4224	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4225	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4226	CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
<>	135:176b8275d35d	4227	}
<>	135:176b8275d35d	4228
<>	135:176b8275d35d	4229	/**
<>	135:176b8275d35d	4230	* @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
<>	135:176b8275d35d	4231	* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
<>	135:176b8275d35d	4232	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4233	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4234	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4235	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4236	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4237	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4238	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4239	* @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
<>	135:176b8275d35d	4240	*/
<>	135:176b8275d35d	4241	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4242	{
<>	135:176b8275d35d	4243	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4244	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	4245	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4246	return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN);
<>	135:176b8275d35d	4247	}
<>	135:176b8275d35d	4248
<>	135:176b8275d35d	4249	/**
<>	135:176b8275d35d	4250	* @brief Enable the fault channel(s) for a given timer.
<>	135:176b8275d35d	4251	* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
<>	135:176b8275d35d	4252	* FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
<>	135:176b8275d35d	4253	* FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
<>	135:176b8275d35d	4254	* FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
<>	135:176b8275d35d	4255	* FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
<>	135:176b8275d35d	4256	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4257	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4258	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4259	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4260	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4261	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4262	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4263	* @param Faults This parameter can be a combination of the following values:
<>	135:176b8275d35d	4264	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	4265	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	4266	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	4267	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	4268	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	4269	* @retval None
<>	135:176b8275d35d	4270	*/
<>	135:176b8275d35d	4271	__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
<>	135:176b8275d35d	4272	{
<>	135:176b8275d35d	4273	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4274	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
<>	135:176b8275d35d	4275	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4276	SET_BIT(*pReg, Faults);
<>	135:176b8275d35d	4277	}
<>	135:176b8275d35d	4278
<>	135:176b8275d35d	4279	/**
<>	135:176b8275d35d	4280	* @brief Disable the fault channel(s) for a given timer.
<>	135:176b8275d35d	4281	* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
<>	135:176b8275d35d	4282	* FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
<>	135:176b8275d35d	4283	* FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
<>	135:176b8275d35d	4284	* FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
<>	135:176b8275d35d	4285	* FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
<>	135:176b8275d35d	4286	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4287	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4288	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4289	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4290	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4291	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4292	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4293	* @param Faults This parameter can be a combination of the following values:
<>	135:176b8275d35d	4294	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	4295	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	4296	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	4297	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	4298	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	4299	* @retval None
<>	135:176b8275d35d	4300	*/
<>	135:176b8275d35d	4301	__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
<>	135:176b8275d35d	4302	{
<>	135:176b8275d35d	4303	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4304	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
<>	135:176b8275d35d	4305	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4306	CLEAR_BIT(*pReg, Faults);
<>	135:176b8275d35d	4307	}
<>	135:176b8275d35d	4308
<>	135:176b8275d35d	4309	/**
<>	135:176b8275d35d	4310	* @brief Indicate whether the fault channel is enabled for a given timer.
<>	135:176b8275d35d	4311	* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
<>	135:176b8275d35d	4312	* FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
<>	135:176b8275d35d	4313	* FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
<>	135:176b8275d35d	4314	* FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
<>	135:176b8275d35d	4315	* FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
<>	135:176b8275d35d	4316	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4317	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4318	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4319	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4320	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4321	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4322	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4323	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	4324	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	4325	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	4326	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	4327	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	4328	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	4329	* @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
<>	135:176b8275d35d	4330	*/
<>	135:176b8275d35d	4331	__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
<>	135:176b8275d35d	4332	{
<>	135:176b8275d35d	4333	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4334	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
<>	135:176b8275d35d	4335	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4336	return (READ_BIT(*pReg, Fault) == (Fault));
<>	135:176b8275d35d	4337	}
<>	135:176b8275d35d	4338
<>	135:176b8275d35d	4339	/**
<>	135:176b8275d35d	4340	* @brief Lock the fault conditioning set-up for a given timer.
<>	135:176b8275d35d	4341	* @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
<>	135:176b8275d35d	4342	* @note Timer fault-related set-up is frozen until the next HRTIM or system reset
<>	135:176b8275d35d	4343	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4344	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4345	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4346	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4347	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4348	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4349	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4350	* @retval None
<>	135:176b8275d35d	4351	*/
<>	135:176b8275d35d	4352	__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4353	{
<>	135:176b8275d35d	4354	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4355	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
<>	135:176b8275d35d	4356	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4357	SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
<>	135:176b8275d35d	4358	}
<>	135:176b8275d35d	4359
<>	135:176b8275d35d	4360	/**
<>	135:176b8275d35d	4361	* @brief Define how the timer behaves during a burst mode operation.
<>	135:176b8275d35d	4362	* @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
<>	135:176b8275d35d	4363	* BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
<>	135:176b8275d35d	4364	* BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
<>	135:176b8275d35d	4365	* BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
<>	135:176b8275d35d	4366	* BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
<>	135:176b8275d35d	4367	* BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
<>	135:176b8275d35d	4368	* @note This function must not be called when the burst mode is enabled
<>	135:176b8275d35d	4369	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4370	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4371	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	4372	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4373	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4374	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4375	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4376	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4377	* @param BurtsModeOption This parameter can be one of the following values:
<>	135:176b8275d35d	4378	* @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
<>	135:176b8275d35d	4379	* @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
<>	135:176b8275d35d	4380	* @retval None
<>	135:176b8275d35d	4381	*/
<>	135:176b8275d35d	4382	__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
<>	135:176b8275d35d	4383	{
<>	135:176b8275d35d	4384	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	4385	MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
<>	135:176b8275d35d	4386	}
<>	135:176b8275d35d	4387
<>	135:176b8275d35d	4388	/**
<>	135:176b8275d35d	4389	* @brief Retrieve how the timer behaves during a burst mode operation.
<>	135:176b8275d35d	4390	* @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
<>	135:176b8275d35d	4391	* BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
<>	135:176b8275d35d	4392	* BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
<>	135:176b8275d35d	4393	* BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
<>	135:176b8275d35d	4394	* BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
<>	135:176b8275d35d	4395	* BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
<>	135:176b8275d35d	4396	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4397	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4398	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	4399	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4400	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4401	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4402	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4403	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4404	* @retval BurtsMode This parameter can be one of the following values:
<>	135:176b8275d35d	4405	* @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
<>	135:176b8275d35d	4406	* @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
<>	135:176b8275d35d	4407	*/
<>	135:176b8275d35d	4408	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4409	{
<>	135:176b8275d35d	4410	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	4411	return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
<>	135:176b8275d35d	4412	}
<>	135:176b8275d35d	4413
<>	135:176b8275d35d	4414	/**
<>	135:176b8275d35d	4415	* @brief Program which registers are to be written by Burst DMA transfers.
<>	135:176b8275d35d	4416	* @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4417	* BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4418	* BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4419	* BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4420	* BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4421	* BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4422	* BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4423	* BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4424	* BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4425	* BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4426	* BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4427	* BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4428	* BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4429	* BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4430	* BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4431	* BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4432	* BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4433	* BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4434	* BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4435	* BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4436	* BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4437	* BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4438	* BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4439	* BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4440	* BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4441	* BDTxUPDR TIAEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4442	* BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4443	* BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4444	* BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
<>	135:176b8275d35d	4445	* BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
<>	135:176b8275d35d	4446	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4447	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4448	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	4449	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4450	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4451	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4452	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4453	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4454	* @param Registers Registers to be updated by the DMA request
<>	135:176b8275d35d	4455	*
<>	135:176b8275d35d	4456	* For Master timer this parameter can be can be a combination of the following values:
<>	135:176b8275d35d	4457	* @arg @ref LL_HRTIM_BURSTDMA_NONE
<>	135:176b8275d35d	4458	* @arg @ref LL_HRTIM_BURSTDMA_MCR
<>	135:176b8275d35d	4459	* @arg @ref LL_HRTIM_BURSTDMA_MICR
<>	135:176b8275d35d	4460	* @arg @ref LL_HRTIM_BURSTDMA_MDIER
<>	135:176b8275d35d	4461	* @arg @ref LL_HRTIM_BURSTDMA_MCNT
<>	135:176b8275d35d	4462	* @arg @ref LL_HRTIM_BURSTDMA_MPER
<>	135:176b8275d35d	4463	* @arg @ref LL_HRTIM_BURSTDMA_MREP
<>	135:176b8275d35d	4464	* @arg @ref LL_HRTIM_BURSTDMA_MCMP1
<>	135:176b8275d35d	4465	* @arg @ref LL_HRTIM_BURSTDMA_MCMP2
<>	135:176b8275d35d	4466	* @arg @ref LL_HRTIM_BURSTDMA_MCMP3
<>	135:176b8275d35d	4467	* @arg @ref LL_HRTIM_BURSTDMA_MCMP4
<>	135:176b8275d35d	4468	*
<>	135:176b8275d35d	4469	* For Timers A..E this parameter can be can be a combination of the following values:
<>	135:176b8275d35d	4470	* @arg @ref LL_HRTIM_BURSTDMA_NONE
<>	135:176b8275d35d	4471	* @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
<>	135:176b8275d35d	4472	* @arg @ref LL_HRTIM_BURSTDMA_TIMICR
<>	135:176b8275d35d	4473	* @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
<>	135:176b8275d35d	4474	* @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
<>	135:176b8275d35d	4475	* @arg @ref LL_HRTIM_BURSTDMA_TIMPER
<>	135:176b8275d35d	4476	* @arg @ref LL_HRTIM_BURSTDMA_TIMREP
<>	135:176b8275d35d	4477	* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
<>	135:176b8275d35d	4478	* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
<>	135:176b8275d35d	4479	* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
<>	135:176b8275d35d	4480	* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
<>	135:176b8275d35d	4481	* @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
<>	135:176b8275d35d	4482	* @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
<>	135:176b8275d35d	4483	* @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
<>	135:176b8275d35d	4484	* @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
<>	135:176b8275d35d	4485	* @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
<>	135:176b8275d35d	4486	* @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
<>	135:176b8275d35d	4487	* @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
<>	135:176b8275d35d	4488	* @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
<>	135:176b8275d35d	4489	* @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
<>	135:176b8275d35d	4490	* @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
<>	135:176b8275d35d	4491	* @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
<>	135:176b8275d35d	4492	* @retval None
<>	135:176b8275d35d	4493	*/
<>	135:176b8275d35d	4494	__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
<>	135:176b8275d35d	4495	{
<>	135:176b8275d35d	4496	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	4497	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer));
<>	135:176b8275d35d	4498	WRITE_REG(*pReg, Registers);
<>	135:176b8275d35d	4499	}
<>	135:176b8275d35d	4500
<>	135:176b8275d35d	4501	/**
<>	135:176b8275d35d	4502	* @brief Indicate on which output the signal is currently applied.
<>	135:176b8275d35d	4503	* @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
<>	135:176b8275d35d	4504	* @note Only significant when the timer operates in push-pull mode.
<>	135:176b8275d35d	4505	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4506	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4507	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4508	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4509	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4510	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4511	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4512	* @retval CPPSTAT This parameter can be one of the following values:
<>	135:176b8275d35d	4513	* @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
<>	135:176b8275d35d	4514	* @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
<>	135:176b8275d35d	4515	*/
<>	135:176b8275d35d	4516	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4517	{
<>	135:176b8275d35d	4518	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	4519	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	4520	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4521	return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
<>	135:176b8275d35d	4522	}
<>	135:176b8275d35d	4523
<>	135:176b8275d35d	4524	/**
<>	135:176b8275d35d	4525	* @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
<>	135:176b8275d35d	4526	* @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
<>	135:176b8275d35d	4527	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4528	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4529	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4530	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4531	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4532	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4533	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4534	* @retval IPPSTAT This parameter can be one of the following values:
<>	135:176b8275d35d	4535	* @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
<>	135:176b8275d35d	4536	* @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
<>	135:176b8275d35d	4537	*/
<>	135:176b8275d35d	4538	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4539	{
<>	135:176b8275d35d	4540	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	4541	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	4542	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4543	return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
<>	135:176b8275d35d	4544	}
<>	135:176b8275d35d	4545
<>	135:176b8275d35d	4546	/**
<>	135:176b8275d35d	4547	* @brief Set the event filter for a given timer.
<>	135:176b8275d35d	4548	* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4549	* EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4550	* EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4551	* EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4552	* EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4553	* EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4554	* EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4555	* EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4556	* EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
<>	135:176b8275d35d	4557	* EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
<>	135:176b8275d35d	4558	* @note This function must not be called when the timer counter is enabled.
<>	135:176b8275d35d	4559	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4560	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4561	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4562	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4563	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4564	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4565	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4566	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	4567	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	4568	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	4569	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	4570	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	4571	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	4572	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	4573	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	4574	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	4575	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	4576	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	4577	* @param Filter This parameter can be one of the following values:
<>	135:176b8275d35d	4578	* @arg @ref LL_HRTIM_EEFLTR_NONE
<>	135:176b8275d35d	4579	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
<>	135:176b8275d35d	4580	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
<>	135:176b8275d35d	4581	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
<>	135:176b8275d35d	4582	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
<>	135:176b8275d35d	4583	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
<>	135:176b8275d35d	4584	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
<>	135:176b8275d35d	4585	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
<>	135:176b8275d35d	4586	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
<>	135:176b8275d35d	4587	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
<>	135:176b8275d35d	4588	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
<>	135:176b8275d35d	4589	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
<>	135:176b8275d35d	4590	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
<>	135:176b8275d35d	4591	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
<>	135:176b8275d35d	4592	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
<>	135:176b8275d35d	4593	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
<>	135:176b8275d35d	4594	* @retval None
<>	135:176b8275d35d	4595	*/
<>	135:176b8275d35d	4596	__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
<>	135:176b8275d35d	4597	{
<>	135:176b8275d35d	4598	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
<>	135:176b8275d35d	4599	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	4600	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
<>	135:176b8275d35d	4601	REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	4602	MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	4603	}
<>	135:176b8275d35d	4604
<>	135:176b8275d35d	4605	/**
<>	135:176b8275d35d	4606	* @brief Get actual event filter settings for a given timer.
<>	135:176b8275d35d	4607	* @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4608	* EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4609	* EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4610	* EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4611	* EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4612	* EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4613	* EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4614	* EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4615	* EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
<>	135:176b8275d35d	4616	* EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
<>	135:176b8275d35d	4617	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4618	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4619	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4620	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4621	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4622	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4623	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4624	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	4625	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	4626	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	4627	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	4628	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	4629	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	4630	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	4631	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	4632	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	4633	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	4634	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	4635	* @retval Filter This parameter can be one of the following values:
<>	135:176b8275d35d	4636	* @arg @ref LL_HRTIM_EEFLTR_NONE
<>	135:176b8275d35d	4637	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
<>	135:176b8275d35d	4638	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
<>	135:176b8275d35d	4639	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
<>	135:176b8275d35d	4640	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
<>	135:176b8275d35d	4641	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
<>	135:176b8275d35d	4642	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
<>	135:176b8275d35d	4643	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
<>	135:176b8275d35d	4644	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
<>	135:176b8275d35d	4645	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
<>	135:176b8275d35d	4646	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
<>	135:176b8275d35d	4647	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
<>	135:176b8275d35d	4648	* @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
<>	135:176b8275d35d	4649	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
<>	135:176b8275d35d	4650	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
<>	135:176b8275d35d	4651	* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
<>	135:176b8275d35d	4652	*/
<>	135:176b8275d35d	4653	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
<>	135:176b8275d35d	4654	{
<>	135:176b8275d35d	4655	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
<>	135:176b8275d35d	4656	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	4657	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
<>	135:176b8275d35d	4658	REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	4659	return (READ_BIT(*pReg, HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	4660	}
<>	135:176b8275d35d	4661
<>	135:176b8275d35d	4662	/**
<>	135:176b8275d35d	4663	* @brief Enable or disable event latch mechanism for a given timer.
<>	135:176b8275d35d	4664	* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4665	* EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4666	* EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4667	* EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4668	* EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4669	* EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4670	* EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4671	* EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4672	* EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
<>	135:176b8275d35d	4673	* EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
<>	135:176b8275d35d	4674	* @note This function must not be called when the timer counter is enabled.
<>	135:176b8275d35d	4675	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4676	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4677	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4678	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4679	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4680	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4681	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4682	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	4683	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	4684	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	4685	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	4686	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	4687	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	4688	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	4689	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	4690	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	4691	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	4692	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	4693	* @param LatchStatus This parameter can be one of the following values:
<>	135:176b8275d35d	4694	* @arg @ref LL_HRTIM_EELATCH_DISABLED
<>	135:176b8275d35d	4695	* @arg @ref LL_HRTIM_EELATCH_ENABLED
<>	135:176b8275d35d	4696	* @retval None
<>	135:176b8275d35d	4697	*/
<>	135:176b8275d35d	4698	__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
<>	135:176b8275d35d	4699	uint32_t LatchStatus)
<>	135:176b8275d35d	4700	{
<>	135:176b8275d35d	4701	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
<>	135:176b8275d35d	4702	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	4703	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
<>	135:176b8275d35d	4704	REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	4705	MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	4706	}
<>	135:176b8275d35d	4707
<>	135:176b8275d35d	4708	/**
<>	135:176b8275d35d	4709	* @brief Get actual event latch status for a given timer.
<>	135:176b8275d35d	4710	* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4711	* EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4712	* EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4713	* EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4714	* EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4715	* EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4716	* EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4717	* EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4718	* EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
<>	135:176b8275d35d	4719	* EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
<>	135:176b8275d35d	4720	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4721	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4722	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4723	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4724	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4725	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4726	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4727	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	4728	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	4729	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	4730	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	4731	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	4732	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	4733	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	4734	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	4735	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	4736	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	4737	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	4738	* @retval LatchStatus This parameter can be one of the following values:
<>	135:176b8275d35d	4739	* @arg @ref LL_HRTIM_EELATCH_DISABLED
<>	135:176b8275d35d	4740	* @arg @ref LL_HRTIM_EELATCH_ENABLED
<>	135:176b8275d35d	4741	*/
<>	135:176b8275d35d	4742	__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
<>	135:176b8275d35d	4743	{
<>	135:176b8275d35d	4744	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
<>	135:176b8275d35d	4745	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	4746	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
<>	135:176b8275d35d	4747	REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	4748	return (READ_BIT(*pReg, HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	4749	}
<>	135:176b8275d35d	4750
<>	135:176b8275d35d	4751	/**
<>	135:176b8275d35d	4752	* @}
<>	135:176b8275d35d	4753	*/
<>	135:176b8275d35d	4754
<>	135:176b8275d35d	4755	/** @defgroup HRTIM_EF_Dead_Time_Configuration Dead_Time_Configuration
<>	135:176b8275d35d	4756	* @{
<>	135:176b8275d35d	4757	*/
<>	135:176b8275d35d	4758
<>	135:176b8275d35d	4759	/**
<>	135:176b8275d35d	4760	* @brief Configure the dead time insertion feature for a given timer.
<>	135:176b8275d35d	4761	* @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
<>	135:176b8275d35d	4762	* DTxR SDTF LL_HRTIM_DT_Config\n
<>	135:176b8275d35d	4763	* DTxR SDRT LL_HRTIM_DT_Config
<>	135:176b8275d35d	4764	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4765	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4766	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4767	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4768	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4769	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4770	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4771	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	4772	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
<>	135:176b8275d35d	4773	* @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
<>	135:176b8275d35d	4774	* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
<>	135:176b8275d35d	4775	* @retval None
<>	135:176b8275d35d	4776	*/
<>	135:176b8275d35d	4777	__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
<>	135:176b8275d35d	4778	{
<>	135:176b8275d35d	4779	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4780	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4781	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4782	MODIFY_REG(*pReg, HRTIM_DTR_SDTF \| HRTIM_DTR_DTPRSC \| HRTIM_DTR_SDTR, Configuration);
<>	135:176b8275d35d	4783	}
<>	135:176b8275d35d	4784
<>	135:176b8275d35d	4785	/**
<>	135:176b8275d35d	4786	* @brief Set the deadtime prescaler value.
<>	135:176b8275d35d	4787	* @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
<>	135:176b8275d35d	4788	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4789	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4790	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4791	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4792	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4793	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4794	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4795	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	4796	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
<>	135:176b8275d35d	4797	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
<>	135:176b8275d35d	4798	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
<>	135:176b8275d35d	4799	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
<>	135:176b8275d35d	4800	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
<>	135:176b8275d35d	4801	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
<>	135:176b8275d35d	4802	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
<>	135:176b8275d35d	4803	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
<>	135:176b8275d35d	4804	* @retval None
<>	135:176b8275d35d	4805	*/
<>	135:176b8275d35d	4806	__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
<>	135:176b8275d35d	4807	{
<>	135:176b8275d35d	4808	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4809	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4810	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4811	MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
<>	135:176b8275d35d	4812	}
<>	135:176b8275d35d	4813
<>	135:176b8275d35d	4814	/**
<>	135:176b8275d35d	4815	* @brief Get actual deadtime prescaler value.
<>	135:176b8275d35d	4816	* @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
<>	135:176b8275d35d	4817	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4818	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4819	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4820	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4821	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4822	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4823	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4824	* @retval Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	4825	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
<>	135:176b8275d35d	4826	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
<>	135:176b8275d35d	4827	* @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
<>	135:176b8275d35d	4828	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
<>	135:176b8275d35d	4829	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
<>	135:176b8275d35d	4830	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
<>	135:176b8275d35d	4831	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
<>	135:176b8275d35d	4832	* @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
<>	135:176b8275d35d	4833	*/
<>	135:176b8275d35d	4834	__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4835	{
<>	135:176b8275d35d	4836	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4837	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4838	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4839	return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
<>	135:176b8275d35d	4840	}
<>	135:176b8275d35d	4841
<>	135:176b8275d35d	4842	/**
<>	135:176b8275d35d	4843	* @brief Set the deadtime rising value.
<>	135:176b8275d35d	4844	* @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
<>	135:176b8275d35d	4845	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4846	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4847	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4848	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4849	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4850	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4851	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4852	* @param RisingValue Value between 0 and 0x1FF
<>	135:176b8275d35d	4853	* @retval None
<>	135:176b8275d35d	4854	*/
<>	135:176b8275d35d	4855	__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
<>	135:176b8275d35d	4856	{
<>	135:176b8275d35d	4857	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4858	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4859	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4860	MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
<>	135:176b8275d35d	4861	}
<>	135:176b8275d35d	4862
<>	135:176b8275d35d	4863	/**
<>	135:176b8275d35d	4864	* @brief Get actual deadtime rising value.
<>	135:176b8275d35d	4865	* @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
<>	135:176b8275d35d	4866	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4867	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4868	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4869	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4870	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4871	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4872	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4873	* @retval RisingValue Value between 0 and 0x1FF
<>	135:176b8275d35d	4874	*/
<>	135:176b8275d35d	4875	__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4876	{
<>	135:176b8275d35d	4877	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4878	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4879	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4880	return (READ_BIT(*pReg, HRTIM_DTR_DTR));
<>	135:176b8275d35d	4881	}
<>	135:176b8275d35d	4882
<>	135:176b8275d35d	4883	/**
<>	135:176b8275d35d	4884	* @brief Set the deadtime sign on rising edge.
<>	135:176b8275d35d	4885	* @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
<>	135:176b8275d35d	4886	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4887	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4888	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4889	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4890	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4891	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4892	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4893	* @param RisingSign This parameter can be one of the following values:
<>	135:176b8275d35d	4894	* @arg @ref LL_HRTIM_DT_RISING_POSITIVE
<>	135:176b8275d35d	4895	* @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
<>	135:176b8275d35d	4896	* @retval None
<>	135:176b8275d35d	4897	*/
<>	135:176b8275d35d	4898	__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
<>	135:176b8275d35d	4899	{
<>	135:176b8275d35d	4900	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4901	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4902	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4903	MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
<>	135:176b8275d35d	4904	}
<>	135:176b8275d35d	4905
<>	135:176b8275d35d	4906	/**
<>	135:176b8275d35d	4907	* @brief Get actual deadtime sign on rising edge.
<>	135:176b8275d35d	4908	* @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
<>	135:176b8275d35d	4909	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4910	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4911	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4912	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4913	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4914	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4915	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4916	* @retval RisingSign This parameter can be one of the following values:
<>	135:176b8275d35d	4917	* @arg @ref LL_HRTIM_DT_RISING_POSITIVE
<>	135:176b8275d35d	4918	* @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
<>	135:176b8275d35d	4919	*/
<>	135:176b8275d35d	4920	__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4921	{
<>	135:176b8275d35d	4922	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4923	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4924	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4925	return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
<>	135:176b8275d35d	4926	}
<>	135:176b8275d35d	4927
<>	135:176b8275d35d	4928	/**
<>	135:176b8275d35d	4929	* @brief Set the deadime falling value.
<>	135:176b8275d35d	4930	* @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
<>	135:176b8275d35d	4931	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4932	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4933	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4934	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4935	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4936	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4937	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4938	* @param FallingValue Value between 0 and 0x1FF
<>	135:176b8275d35d	4939	* @retval None
<>	135:176b8275d35d	4940	*/
<>	135:176b8275d35d	4941	__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
<>	135:176b8275d35d	4942	{
<>	135:176b8275d35d	4943	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4944	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4945	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4946	MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
<>	135:176b8275d35d	4947	}
<>	135:176b8275d35d	4948
<>	135:176b8275d35d	4949	/**
<>	135:176b8275d35d	4950	* @brief Get actual deadtime falling value
<>	135:176b8275d35d	4951	* @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
<>	135:176b8275d35d	4952	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4953	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4954	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4955	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4956	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4957	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4958	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4959	* @retval FallingValue Value between 0 and 0x1FF
<>	135:176b8275d35d	4960	*/
<>	135:176b8275d35d	4961	__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	4962	{
<>	135:176b8275d35d	4963	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4964	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4965	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4966	return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
<>	135:176b8275d35d	4967	}
<>	135:176b8275d35d	4968
<>	135:176b8275d35d	4969	/**
<>	135:176b8275d35d	4970	* @brief Set the deadtime sign on falling edge.
<>	135:176b8275d35d	4971	* @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
<>	135:176b8275d35d	4972	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4973	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4974	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4975	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4976	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	4977	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	4978	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	4979	* @param FallingSign This parameter can be one of the following values:
<>	135:176b8275d35d	4980	* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
<>	135:176b8275d35d	4981	* @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
<>	135:176b8275d35d	4982	* @retval None
<>	135:176b8275d35d	4983	*/
<>	135:176b8275d35d	4984	__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
<>	135:176b8275d35d	4985	{
<>	135:176b8275d35d	4986	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	4987	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	4988	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	4989	MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
<>	135:176b8275d35d	4990	}
<>	135:176b8275d35d	4991
<>	135:176b8275d35d	4992	/**
<>	135:176b8275d35d	4993	* @brief Get actual deadtime sign on falling edge.
<>	135:176b8275d35d	4994	* @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
<>	135:176b8275d35d	4995	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	4996	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	4997	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	4998	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	4999	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5000	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5001	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5002	* @retval FallingSign This parameter can be one of the following values:
<>	135:176b8275d35d	5003	* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
<>	135:176b8275d35d	5004	* @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
<>	135:176b8275d35d	5005	*/
<>	135:176b8275d35d	5006	__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5007	{
<>	135:176b8275d35d	5008	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5009	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	5010	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5011	return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
<>	135:176b8275d35d	5012	}
<>	135:176b8275d35d	5013
<>	135:176b8275d35d	5014	/**
<>	135:176b8275d35d	5015	* @brief Lock the deadtime value and sign on rising edge.
<>	135:176b8275d35d	5016	* @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
<>	135:176b8275d35d	5017	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5018	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5019	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5020	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5021	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5022	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5023	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5024	* @retval None
<>	135:176b8275d35d	5025	*/
<>	135:176b8275d35d	5026	__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5027	{
<>	135:176b8275d35d	5028	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5029	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	5030	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5031	SET_BIT(*pReg, HRTIM_DTR_DTRLK);
<>	135:176b8275d35d	5032	}
<>	135:176b8275d35d	5033
<>	135:176b8275d35d	5034	/**
<>	135:176b8275d35d	5035	* @brief Lock the deadtime sign on rising edge.
<>	135:176b8275d35d	5036	* @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
<>	135:176b8275d35d	5037	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5038	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5039	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5040	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5041	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5042	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5043	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5044	* @retval None
<>	135:176b8275d35d	5045	*/
<>	135:176b8275d35d	5046	__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5047	{
<>	135:176b8275d35d	5048	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5049	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	5050	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5051	SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
<>	135:176b8275d35d	5052	}
<>	135:176b8275d35d	5053
<>	135:176b8275d35d	5054	/**
<>	135:176b8275d35d	5055	* @brief Lock the deadtime value and sign on falling edge.
<>	135:176b8275d35d	5056	* @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
<>	135:176b8275d35d	5057	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5058	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5059	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5060	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5061	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5062	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5063	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5064	* @retval None
<>	135:176b8275d35d	5065	*/
<>	135:176b8275d35d	5066	__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5067	{
<>	135:176b8275d35d	5068	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5069	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	5070	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5071	SET_BIT(*pReg, HRTIM_DTR_DTFLK);
<>	135:176b8275d35d	5072	}
<>	135:176b8275d35d	5073
<>	135:176b8275d35d	5074	/**
<>	135:176b8275d35d	5075	* @brief Lock the deadtime sign on falling edge.
<>	135:176b8275d35d	5076	* @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
<>	135:176b8275d35d	5077	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5078	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5079	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5080	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5081	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5082	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5083	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5084	* @retval None
<>	135:176b8275d35d	5085	*/
<>	135:176b8275d35d	5086	__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5087	{
<>	135:176b8275d35d	5088	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5089	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
<>	135:176b8275d35d	5090	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5091	SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
<>	135:176b8275d35d	5092	}
<>	135:176b8275d35d	5093
<>	135:176b8275d35d	5094	/**
<>	135:176b8275d35d	5095	* @}
<>	135:176b8275d35d	5096	*/
<>	135:176b8275d35d	5097
<>	135:176b8275d35d	5098	/** @defgroup HRTIM_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
<>	135:176b8275d35d	5099	* @{
<>	135:176b8275d35d	5100	*/
<>	135:176b8275d35d	5101
<>	135:176b8275d35d	5102	/**
<>	135:176b8275d35d	5103	* @brief Configure the chopper stage for a given timer.
<>	135:176b8275d35d	5104	* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
<>	135:176b8275d35d	5105	* CHPxR CARDTY LL_HRTIM_CHP_Config\n
<>	135:176b8275d35d	5106	* CHPxR STRTPW LL_HRTIM_CHP_Config
<>	135:176b8275d35d	5107	* @note This function must not be called if the chopper mode is already
<>	135:176b8275d35d	5108	* enabled for one of the timer outputs.
<>	135:176b8275d35d	5109	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5110	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5111	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5112	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5113	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5114	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5115	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5116	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	5117	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
<>	135:176b8275d35d	5118	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
<>	135:176b8275d35d	5119	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
<>	135:176b8275d35d	5120	* @retval None
<>	135:176b8275d35d	5121	*/
<>	135:176b8275d35d	5122	__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
<>	135:176b8275d35d	5123	{
<>	135:176b8275d35d	5124	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5125	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5126	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5127	MODIFY_REG(*pReg, HRTIM_CHPR_STRPW \| HRTIM_CHPR_CARDTY \| HRTIM_CHPR_CARFRQ, Configuration);
<>	135:176b8275d35d	5128	}
<>	135:176b8275d35d	5129
<>	135:176b8275d35d	5130	/**
<>	135:176b8275d35d	5131	* @brief Set prescaler determining the carrier frequency to be added on top
<>	135:176b8275d35d	5132	* of the timer output signals when chopper mode is enabled.
<>	135:176b8275d35d	5133	* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
<>	135:176b8275d35d	5134	* @note This function must not be called if the chopper mode is already
<>	135:176b8275d35d	5135	* enabled for one of the timer outputs.
<>	135:176b8275d35d	5136	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5137	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5138	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5139	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5140	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5141	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5142	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5143	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	5144	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
<>	135:176b8275d35d	5145	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
<>	135:176b8275d35d	5146	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
<>	135:176b8275d35d	5147	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
<>	135:176b8275d35d	5148	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
<>	135:176b8275d35d	5149	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
<>	135:176b8275d35d	5150	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
<>	135:176b8275d35d	5151	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
<>	135:176b8275d35d	5152	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
<>	135:176b8275d35d	5153	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
<>	135:176b8275d35d	5154	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
<>	135:176b8275d35d	5155	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
<>	135:176b8275d35d	5156	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
<>	135:176b8275d35d	5157	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
<>	135:176b8275d35d	5158	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
<>	135:176b8275d35d	5159	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
<>	135:176b8275d35d	5160	* @retval None
<>	135:176b8275d35d	5161	*/
<>	135:176b8275d35d	5162	__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
<>	135:176b8275d35d	5163	{
<>	135:176b8275d35d	5164	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5165	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5166	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5167	MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
<>	135:176b8275d35d	5168	}
<>	135:176b8275d35d	5169
<>	135:176b8275d35d	5170	/**
<>	135:176b8275d35d	5171	* @brief Get actual chopper stage prescaler value.
<>	135:176b8275d35d	5172	* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
<>	135:176b8275d35d	5173	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5174	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5175	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5176	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5177	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5178	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5179	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5180	* @retval Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	5181	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
<>	135:176b8275d35d	5182	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
<>	135:176b8275d35d	5183	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
<>	135:176b8275d35d	5184	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
<>	135:176b8275d35d	5185	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
<>	135:176b8275d35d	5186	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
<>	135:176b8275d35d	5187	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
<>	135:176b8275d35d	5188	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
<>	135:176b8275d35d	5189	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
<>	135:176b8275d35d	5190	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
<>	135:176b8275d35d	5191	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
<>	135:176b8275d35d	5192	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
<>	135:176b8275d35d	5193	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
<>	135:176b8275d35d	5194	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
<>	135:176b8275d35d	5195	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
<>	135:176b8275d35d	5196	* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
<>	135:176b8275d35d	5197	*/
<>	135:176b8275d35d	5198	__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5199	{
<>	135:176b8275d35d	5200	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5201	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5202	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5203	return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
<>	135:176b8275d35d	5204	}
<>	135:176b8275d35d	5205
<>	135:176b8275d35d	5206	/**
<>	135:176b8275d35d	5207	* @brief Set the chopper duty cycle.
<>	135:176b8275d35d	5208	* @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
<>	135:176b8275d35d	5209	* @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
<>	135:176b8275d35d	5210	* @note This function must not be called if the chopper mode is already
<>	135:176b8275d35d	5211	* enabled for one of the timer outputs.
<>	135:176b8275d35d	5212	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5213	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5214	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5215	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5216	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5217	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5218	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5219	* @param DutyCycle This parameter can be one of the following values:
<>	135:176b8275d35d	5220	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
<>	135:176b8275d35d	5221	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
<>	135:176b8275d35d	5222	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
<>	135:176b8275d35d	5223	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
<>	135:176b8275d35d	5224	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
<>	135:176b8275d35d	5225	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
<>	135:176b8275d35d	5226	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
<>	135:176b8275d35d	5227	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
<>	135:176b8275d35d	5228	* @retval None
<>	135:176b8275d35d	5229	*/
<>	135:176b8275d35d	5230	__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
<>	135:176b8275d35d	5231	{
<>	135:176b8275d35d	5232	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5233	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5234	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5235	MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
<>	135:176b8275d35d	5236	}
<>	135:176b8275d35d	5237
<>	135:176b8275d35d	5238	/**
<>	135:176b8275d35d	5239	* @brief Get actual chopper duty cycle.
<>	135:176b8275d35d	5240	* @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
<>	135:176b8275d35d	5241	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5242	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5243	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5244	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5245	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5246	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5247	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5248	* @retval DutyCycle This parameter can be one of the following values:
<>	135:176b8275d35d	5249	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
<>	135:176b8275d35d	5250	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
<>	135:176b8275d35d	5251	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
<>	135:176b8275d35d	5252	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
<>	135:176b8275d35d	5253	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
<>	135:176b8275d35d	5254	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
<>	135:176b8275d35d	5255	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
<>	135:176b8275d35d	5256	* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
<>	135:176b8275d35d	5257	*/
<>	135:176b8275d35d	5258	__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5259	{
<>	135:176b8275d35d	5260	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5261	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5262	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5263	return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
<>	135:176b8275d35d	5264	}
<>	135:176b8275d35d	5265
<>	135:176b8275d35d	5266	/**
<>	135:176b8275d35d	5267	* @brief Set the start pulse width.
<>	135:176b8275d35d	5268	* @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
<>	135:176b8275d35d	5269	* @note This function must not be called if the chopper mode is already
<>	135:176b8275d35d	5270	* enabled for one of the timer outputs.
<>	135:176b8275d35d	5271	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5272	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5273	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5274	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5275	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5276	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5277	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5278	* @param PulseWidth This parameter can be one of the following values:
<>	135:176b8275d35d	5279	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
<>	135:176b8275d35d	5280	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
<>	135:176b8275d35d	5281	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
<>	135:176b8275d35d	5282	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
<>	135:176b8275d35d	5283	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
<>	135:176b8275d35d	5284	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
<>	135:176b8275d35d	5285	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
<>	135:176b8275d35d	5286	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
<>	135:176b8275d35d	5287	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
<>	135:176b8275d35d	5288	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
<>	135:176b8275d35d	5289	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
<>	135:176b8275d35d	5290	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
<>	135:176b8275d35d	5291	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
<>	135:176b8275d35d	5292	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
<>	135:176b8275d35d	5293	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
<>	135:176b8275d35d	5294	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
<>	135:176b8275d35d	5295	* @retval None
<>	135:176b8275d35d	5296	*/
<>	135:176b8275d35d	5297	__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
<>	135:176b8275d35d	5298	{
<>	135:176b8275d35d	5299	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5300	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5301	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5302	MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
<>	135:176b8275d35d	5303	}
<>	135:176b8275d35d	5304
<>	135:176b8275d35d	5305	/**
<>	135:176b8275d35d	5306	* @brief Get actual start pulse width.
<>	135:176b8275d35d	5307	* @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
<>	135:176b8275d35d	5308	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5309	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	5310	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	5311	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	5312	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	5313	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	5314	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	5315	* @retval PulseWidth This parameter can be one of the following values:
<>	135:176b8275d35d	5316	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
<>	135:176b8275d35d	5317	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
<>	135:176b8275d35d	5318	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
<>	135:176b8275d35d	5319	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
<>	135:176b8275d35d	5320	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
<>	135:176b8275d35d	5321	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
<>	135:176b8275d35d	5322	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
<>	135:176b8275d35d	5323	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
<>	135:176b8275d35d	5324	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
<>	135:176b8275d35d	5325	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
<>	135:176b8275d35d	5326	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
<>	135:176b8275d35d	5327	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
<>	135:176b8275d35d	5328	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
<>	135:176b8275d35d	5329	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
<>	135:176b8275d35d	5330	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
<>	135:176b8275d35d	5331	* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
<>	135:176b8275d35d	5332	*/
<>	135:176b8275d35d	5333	__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	5334	{
<>	135:176b8275d35d	5335	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
<>	135:176b8275d35d	5336	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
<>	135:176b8275d35d	5337	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	5338	return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
<>	135:176b8275d35d	5339	}
<>	135:176b8275d35d	5340
<>	135:176b8275d35d	5341	/**
<>	135:176b8275d35d	5342	* @}
<>	135:176b8275d35d	5343	*/
<>	135:176b8275d35d	5344
<>	135:176b8275d35d	5345	/** @defgroup HRTIM_EF_Output_Management Output_Management
<>	135:176b8275d35d	5346	* @{
<>	135:176b8275d35d	5347	*/
<>	135:176b8275d35d	5348
<>	135:176b8275d35d	5349	/**
<>	135:176b8275d35d	5350	* @brief Set the timer output set source.
<>	135:176b8275d35d	5351	* @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5352	* SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5353	* SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5354	* SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5355	* SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5356	* SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5357	* SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5358	* SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5359	* SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5360	* SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5361	* SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5362	* SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5363	* SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5364	* SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5365	* SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5366	* SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5367	* SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5368	* SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5369	* SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5370	* SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5371	* SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5372	* SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5373	* SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5374	* SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5375	* SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5376	* SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5377	* SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5378	* SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5379	* SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5380	* SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5381	* SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5382	* SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5383	* SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5384	* SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5385	* SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5386	* SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5387	* SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5388	* SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5389	* SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5390	* SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5391	* SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5392	* SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5393	* SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5394	* SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5395	* SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5396	* SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5397	* SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5398	* SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5399	* SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5400	* SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5401	* SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5402	* SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5403	* SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5404	* SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5405	* SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5406	* SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5407	* SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5408	* SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5409	* SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5410	* SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5411	* SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5412	* SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5413	* SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
<>	135:176b8275d35d	5414	* SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
<>	135:176b8275d35d	5415	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5416	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5417	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5418	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5419	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5420	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5421	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5422	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5423	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5424	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5425	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5426	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5427	* @param SetSrc This parameter can be a combination of the following values:
<>	135:176b8275d35d	5428	* @arg @ref LL_HRTIM_CROSSBAR_NONE
<>	135:176b8275d35d	5429	* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
<>	135:176b8275d35d	5430	* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
<>	135:176b8275d35d	5431	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
<>	135:176b8275d35d	5432	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
<>	135:176b8275d35d	5433	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
<>	135:176b8275d35d	5434	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
<>	135:176b8275d35d	5435	* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
<>	135:176b8275d35d	5436	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
<>	135:176b8275d35d	5437	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
<>	135:176b8275d35d	5438	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
<>	135:176b8275d35d	5439	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
<>	135:176b8275d35d	5440	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
<>	135:176b8275d35d	5441	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
<>	135:176b8275d35d	5442	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
<>	135:176b8275d35d	5443	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
<>	135:176b8275d35d	5444	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
<>	135:176b8275d35d	5445	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
<>	135:176b8275d35d	5446	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
<>	135:176b8275d35d	5447	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
<>	135:176b8275d35d	5448	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
<>	135:176b8275d35d	5449	* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
<>	135:176b8275d35d	5450	* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
<>	135:176b8275d35d	5451	* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
<>	135:176b8275d35d	5452	* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
<>	135:176b8275d35d	5453	* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
<>	135:176b8275d35d	5454	* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
<>	135:176b8275d35d	5455	* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
<>	135:176b8275d35d	5456	* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
<>	135:176b8275d35d	5457	* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
<>	135:176b8275d35d	5458	* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
<>	135:176b8275d35d	5459	* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
<>	135:176b8275d35d	5460	* @retval None
<>	135:176b8275d35d	5461	*/
<>	135:176b8275d35d	5462	__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
<>	135:176b8275d35d	5463	{
<>	135:176b8275d35d	5464	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5465	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
<>	135:176b8275d35d	5466	REG_OFFSET_TAB_SETxR[iOutput]));
<>	135:176b8275d35d	5467	WRITE_REG(*pReg, SetSrc);
<>	135:176b8275d35d	5468	}
<>	135:176b8275d35d	5469
<>	135:176b8275d35d	5470	/**
<>	135:176b8275d35d	5471	* @brief Get the timer output set source.
<>	135:176b8275d35d	5472	* @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5473	* SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5474	* SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5475	* SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5476	* SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5477	* SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5478	* SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5479	* SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5480	* SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5481	* SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5482	* SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5483	* SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5484	* SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5485	* SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5486	* SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5487	* SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5488	* SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5489	* SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5490	* SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5491	* SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5492	* SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5493	* SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5494	* SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5495	* SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5496	* SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5497	* SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5498	* SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5499	* SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5500	* SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5501	* SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5502	* SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5503	* SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5504	* SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5505	* SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5506	* SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5507	* SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5508	* SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5509	* SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5510	* SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5511	* SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5512	* SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5513	* SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5514	* SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5515	* SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5516	* SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5517	* SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5518	* SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5519	* SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5520	* SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5521	* SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5522	* SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5523	* SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5524	* SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5525	* SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5526	* SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5527	* SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5528	* SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5529	* SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5530	* SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5531	* SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5532	* SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5533	* SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5534	* SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
<>	135:176b8275d35d	5535	* SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
<>	135:176b8275d35d	5536	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5537	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5538	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5539	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5540	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5541	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5542	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5543	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5544	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5545	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5546	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5547	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5548	* @retval SetSrc This parameter can be a combination of the following values:
<>	135:176b8275d35d	5549	* @arg @ref LL_HRTIM_CROSSBAR_NONE
<>	135:176b8275d35d	5550	* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
<>	135:176b8275d35d	5551	* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
<>	135:176b8275d35d	5552	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
<>	135:176b8275d35d	5553	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
<>	135:176b8275d35d	5554	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
<>	135:176b8275d35d	5555	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
<>	135:176b8275d35d	5556	* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
<>	135:176b8275d35d	5557	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
<>	135:176b8275d35d	5558	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
<>	135:176b8275d35d	5559	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
<>	135:176b8275d35d	5560	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
<>	135:176b8275d35d	5561	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
<>	135:176b8275d35d	5562	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
<>	135:176b8275d35d	5563	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
<>	135:176b8275d35d	5564	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
<>	135:176b8275d35d	5565	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
<>	135:176b8275d35d	5566	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
<>	135:176b8275d35d	5567	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
<>	135:176b8275d35d	5568	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
<>	135:176b8275d35d	5569	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
<>	135:176b8275d35d	5570	* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
<>	135:176b8275d35d	5571	* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
<>	135:176b8275d35d	5572	* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
<>	135:176b8275d35d	5573	* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
<>	135:176b8275d35d	5574	* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
<>	135:176b8275d35d	5575	* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
<>	135:176b8275d35d	5576	* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
<>	135:176b8275d35d	5577	* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
<>	135:176b8275d35d	5578	* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
<>	135:176b8275d35d	5579	* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
<>	135:176b8275d35d	5580	* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
<>	135:176b8275d35d	5581	*/
<>	135:176b8275d35d	5582	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	5583	{
<>	135:176b8275d35d	5584	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5585	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
<>	135:176b8275d35d	5586	REG_OFFSET_TAB_SETxR[iOutput]));
<>	135:176b8275d35d	5587	return (uint32_t) READ_REG(*pReg);
<>	135:176b8275d35d	5588	}
<>	135:176b8275d35d	5589
<>	135:176b8275d35d	5590	/**
<>	135:176b8275d35d	5591	* @brief Set the timer output reset source.
<>	135:176b8275d35d	5592	* @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5593	* RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5594	* RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5595	* RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5596	* RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5597	* RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5598	* RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5599	* RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5600	* RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5601	* RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5602	* RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5603	* RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5604	* RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5605	* RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5606	* RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5607	* RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5608	* RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5609	* RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5610	* RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5611	* RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5612	* RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5613	* RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5614	* RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5615	* RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5616	* RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5617	* RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5618	* RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5619	* RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5620	* RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5621	* RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5622	* RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5623	* RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5624	* RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5625	* RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5626	* RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5627	* RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5628	* RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5629	* RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5630	* RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5631	* RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5632	* RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5633	* RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5634	* RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5635	* RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5636	* RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5637	* RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5638	* RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5639	* RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5640	* RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5641	* RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5642	* RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5643	* RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5644	* RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5645	* RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5646	* RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5647	* RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5648	* RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5649	* RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5650	* RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5651	* RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5652	* RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5653	* RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5654	* RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
<>	135:176b8275d35d	5655	* RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
<>	135:176b8275d35d	5656	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5657	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5658	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5659	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5660	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5661	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5662	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5663	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5664	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5665	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5666	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5667	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5668	* @param ResetSrc This parameter can be a combination of the following values:
<>	135:176b8275d35d	5669	* @arg @ref LL_HRTIM_CROSSBAR_NONE
<>	135:176b8275d35d	5670	* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
<>	135:176b8275d35d	5671	* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
<>	135:176b8275d35d	5672	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
<>	135:176b8275d35d	5673	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
<>	135:176b8275d35d	5674	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
<>	135:176b8275d35d	5675	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
<>	135:176b8275d35d	5676	* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
<>	135:176b8275d35d	5677	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
<>	135:176b8275d35d	5678	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
<>	135:176b8275d35d	5679	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
<>	135:176b8275d35d	5680	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
<>	135:176b8275d35d	5681	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
<>	135:176b8275d35d	5682	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
<>	135:176b8275d35d	5683	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
<>	135:176b8275d35d	5684	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
<>	135:176b8275d35d	5685	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
<>	135:176b8275d35d	5686	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
<>	135:176b8275d35d	5687	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
<>	135:176b8275d35d	5688	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
<>	135:176b8275d35d	5689	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
<>	135:176b8275d35d	5690	* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
<>	135:176b8275d35d	5691	* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
<>	135:176b8275d35d	5692	* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
<>	135:176b8275d35d	5693	* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
<>	135:176b8275d35d	5694	* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
<>	135:176b8275d35d	5695	* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
<>	135:176b8275d35d	5696	* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
<>	135:176b8275d35d	5697	* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
<>	135:176b8275d35d	5698	* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
<>	135:176b8275d35d	5699	* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
<>	135:176b8275d35d	5700	* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
<>	135:176b8275d35d	5701	* @retval None
<>	135:176b8275d35d	5702	*/
<>	135:176b8275d35d	5703	__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
<>	135:176b8275d35d	5704	{
<>	135:176b8275d35d	5705	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5706	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
<>	135:176b8275d35d	5707	REG_OFFSET_TAB_SETxR[iOutput]));
<>	135:176b8275d35d	5708	WRITE_REG(*pReg, ResetSrc);
<>	135:176b8275d35d	5709	}
<>	135:176b8275d35d	5710
<>	135:176b8275d35d	5711	/**
<>	135:176b8275d35d	5712	* @brief Get the timer output set source.
<>	135:176b8275d35d	5713	* @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5714	* RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5715	* RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5716	* RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5717	* RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5718	* RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5719	* RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5720	* RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5721	* RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5722	* RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5723	* RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5724	* RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5725	* RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5726	* RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5727	* RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5728	* RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5729	* RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5730	* RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5731	* RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5732	* RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5733	* RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5734	* RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5735	* RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5736	* RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5737	* RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5738	* RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5739	* RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5740	* RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5741	* RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5742	* RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5743	* RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5744	* RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5745	* RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5746	* RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5747	* RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5748	* RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5749	* RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5750	* RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5751	* RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5752	* RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5753	* RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5754	* RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5755	* RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5756	* RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5757	* RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5758	* RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5759	* RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5760	* RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5761	* RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5762	* RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5763	* RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5764	* RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5765	* RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5766	* RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5767	* RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5768	* RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5769	* RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5770	* RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5771	* RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5772	* RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5773	* RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5774	* RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5775	* RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
<>	135:176b8275d35d	5776	* RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
<>	135:176b8275d35d	5777	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5778	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5779	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5780	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5781	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5782	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5783	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5784	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5785	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5786	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5787	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5788	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5789	* @retval ResetSrc This parameter can be a combination of the following values:
<>	135:176b8275d35d	5790	* @arg @ref LL_HRTIM_CROSSBAR_NONE
<>	135:176b8275d35d	5791	* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
<>	135:176b8275d35d	5792	* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
<>	135:176b8275d35d	5793	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
<>	135:176b8275d35d	5794	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
<>	135:176b8275d35d	5795	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
<>	135:176b8275d35d	5796	* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
<>	135:176b8275d35d	5797	* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
<>	135:176b8275d35d	5798	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
<>	135:176b8275d35d	5799	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
<>	135:176b8275d35d	5800	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
<>	135:176b8275d35d	5801	* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
<>	135:176b8275d35d	5802	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
<>	135:176b8275d35d	5803	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
<>	135:176b8275d35d	5804	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
<>	135:176b8275d35d	5805	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
<>	135:176b8275d35d	5806	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
<>	135:176b8275d35d	5807	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
<>	135:176b8275d35d	5808	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
<>	135:176b8275d35d	5809	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
<>	135:176b8275d35d	5810	* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
<>	135:176b8275d35d	5811	* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
<>	135:176b8275d35d	5812	* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
<>	135:176b8275d35d	5813	* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
<>	135:176b8275d35d	5814	* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
<>	135:176b8275d35d	5815	* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
<>	135:176b8275d35d	5816	* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
<>	135:176b8275d35d	5817	* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
<>	135:176b8275d35d	5818	* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
<>	135:176b8275d35d	5819	* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
<>	135:176b8275d35d	5820	* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
<>	135:176b8275d35d	5821	* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
<>	135:176b8275d35d	5822	*/
<>	135:176b8275d35d	5823	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	5824	{
<>	135:176b8275d35d	5825	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5826	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
<>	135:176b8275d35d	5827	REG_OFFSET_TAB_SETxR[iOutput]));
<>	135:176b8275d35d	5828	return (uint32_t) READ_REG(*pReg);
<>	135:176b8275d35d	5829	}
<>	135:176b8275d35d	5830
<>	135:176b8275d35d	5831	/**
<>	135:176b8275d35d	5832	* @brief Configure a timer output.
<>	135:176b8275d35d	5833	* @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5834	* OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5835	* OUTxR IDLES1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5836	* OUTxR FAULT1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5837	* OUTxR CHP1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5838	* OUTxR DIDL1 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5839	* OUTxR POL2 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5840	* OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5841	* OUTxR IDLES2 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5842	* OUTxR FAULT2 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5843	* OUTxR CHP2 LL_HRTIM_OUT_Config\n
<>	135:176b8275d35d	5844	* OUTxR DIDL2 LL_HRTIM_OUT_Config
<>	135:176b8275d35d	5845	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5846	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5847	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5848	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5849	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5850	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5851	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5852	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5853	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5854	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5855	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5856	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5857	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	5858	* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
<>	135:176b8275d35d	5859	* @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
<>	135:176b8275d35d	5860	* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
<>	135:176b8275d35d	5861	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
<>	135:176b8275d35d	5862	* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
<>	135:176b8275d35d	5863	* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
<>	135:176b8275d35d	5864	* @retval None
<>	135:176b8275d35d	5865	*/
<>	135:176b8275d35d	5866	__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
<>	135:176b8275d35d	5867	{
<>	135:176b8275d35d	5868	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5869	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	5870	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5871	MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
<>	135:176b8275d35d	5872	(Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5873	}
<>	135:176b8275d35d	5874
<>	135:176b8275d35d	5875	/**
<>	135:176b8275d35d	5876	* @brief Set the polarity of a timer output.
<>	135:176b8275d35d	5877	* @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
<>	135:176b8275d35d	5878	* OUTxR POL2 LL_HRTIM_OUT_SetPolarity
<>	135:176b8275d35d	5879	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5880	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5881	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5882	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5883	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5884	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5885	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5886	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5887	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5888	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5889	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5890	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5891	* @param Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	5892	* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
<>	135:176b8275d35d	5893	* @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
<>	135:176b8275d35d	5894	* @retval None
<>	135:176b8275d35d	5895	*/
<>	135:176b8275d35d	5896	__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
<>	135:176b8275d35d	5897	{
<>	135:176b8275d35d	5898	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5899	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	5900	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5901	MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5902	}
<>	135:176b8275d35d	5903
<>	135:176b8275d35d	5904	/**
<>	135:176b8275d35d	5905	* @brief Get actual polarity of the timer output.
<>	135:176b8275d35d	5906	* @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
<>	135:176b8275d35d	5907	* OUTxR POL2 LL_HRTIM_OUT_GetPolarity
<>	135:176b8275d35d	5908	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5909	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5910	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5911	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5912	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5913	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5914	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5915	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5916	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5917	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5918	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5919	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5920	* @retval Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	5921	* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
<>	135:176b8275d35d	5922	* @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
<>	135:176b8275d35d	5923	*/
<>	135:176b8275d35d	5924	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	5925	{
<>	135:176b8275d35d	5926	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5927	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	5928	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5929	return (READ_BIT(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	5930	}
<>	135:176b8275d35d	5931
<>	135:176b8275d35d	5932	/**
<>	135:176b8275d35d	5933	* @brief Set the output IDLE mode.
<>	135:176b8275d35d	5934	* @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
<>	135:176b8275d35d	5935	* OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
<>	135:176b8275d35d	5936	* @note This function must not be called when the burst mode is active
<>	135:176b8275d35d	5937	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5938	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5939	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5940	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5941	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5942	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5943	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5944	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5945	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5946	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5947	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5948	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5949	* @param IdleMode This parameter can be one of the following values:
<>	135:176b8275d35d	5950	* @arg @ref LL_HRTIM_OUT_NO_IDLE
<>	135:176b8275d35d	5951	* @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
<>	135:176b8275d35d	5952	* @retval None
<>	135:176b8275d35d	5953	*/
<>	135:176b8275d35d	5954	__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
<>	135:176b8275d35d	5955	{
<>	135:176b8275d35d	5956	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5957	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	5958	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5959	MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleMode << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5960	}
<>	135:176b8275d35d	5961
<>	135:176b8275d35d	5962	/**
<>	135:176b8275d35d	5963	* @brief Get actual output IDLE mode.
<>	135:176b8275d35d	5964	* @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
<>	135:176b8275d35d	5965	* OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
<>	135:176b8275d35d	5966	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5967	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5968	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5969	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	5970	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	5971	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	5972	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	5973	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	5974	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	5975	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	5976	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	5977	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	5978	* @retval IdleMode This parameter can be one of the following values:
<>	135:176b8275d35d	5979	* @arg @ref LL_HRTIM_OUT_NO_IDLE
<>	135:176b8275d35d	5980	* @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
<>	135:176b8275d35d	5981	*/
<>	135:176b8275d35d	5982	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	5983	{
<>	135:176b8275d35d	5984	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	5985	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	5986	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	5987	return (READ_BIT(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	5988	}
<>	135:176b8275d35d	5989
<>	135:176b8275d35d	5990	/**
<>	135:176b8275d35d	5991	* @brief Set the output IDLE level.
<>	135:176b8275d35d	5992	* @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
<>	135:176b8275d35d	5993	* OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
<>	135:176b8275d35d	5994	* @note This function must be called prior enabling the timer.
<>	135:176b8275d35d	5995	* @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
<>	135:176b8275d35d	5996	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	5997	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	5998	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	5999	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6000	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6001	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6002	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6003	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6004	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6005	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6006	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6007	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6008	* @param IdleLevel This parameter can be one of the following values:
<>	135:176b8275d35d	6009	* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
<>	135:176b8275d35d	6010	* @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
<>	135:176b8275d35d	6011	* @retval None
<>	135:176b8275d35d	6012	*/
<>	135:176b8275d35d	6013	__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
<>	135:176b8275d35d	6014	{
<>	135:176b8275d35d	6015	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6016	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6017	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6018	MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6019	}
<>	135:176b8275d35d	6020
<>	135:176b8275d35d	6021	/**
<>	135:176b8275d35d	6022	* @brief Get actual output IDLE level.
<>	135:176b8275d35d	6023	* @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
<>	135:176b8275d35d	6024	* OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
<>	135:176b8275d35d	6025	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6026	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6027	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6028	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6029	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6030	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6031	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6032	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6033	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6034	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6035	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6036	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6037	* @retval IdleLevel This parameter can be one of the following values:
<>	135:176b8275d35d	6038	* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
<>	135:176b8275d35d	6039	* @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
<>	135:176b8275d35d	6040	*/
<>	135:176b8275d35d	6041	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6042	{
<>	135:176b8275d35d	6043	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6044	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6045	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6046	return (READ_BIT(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	6047	}
<>	135:176b8275d35d	6048
<>	135:176b8275d35d	6049	/**
<>	135:176b8275d35d	6050	* @brief Set the output FAULT state.
<>	135:176b8275d35d	6051	* @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
<>	135:176b8275d35d	6052	* OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
<>	135:176b8275d35d	6053	* @note This function must not called when the timer is enabled and a fault
<>	135:176b8275d35d	6054	* channel is enabled at timer level.
<>	135:176b8275d35d	6055	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6056	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6057	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6058	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6059	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6060	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6061	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6062	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6063	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6064	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6065	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6066	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6067	* @param FaultState This parameter can be one of the following values:
<>	135:176b8275d35d	6068	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
<>	135:176b8275d35d	6069	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
<>	135:176b8275d35d	6070	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
<>	135:176b8275d35d	6071	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
<>	135:176b8275d35d	6072	* @retval None
<>	135:176b8275d35d	6073	*/
<>	135:176b8275d35d	6074	__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
<>	135:176b8275d35d	6075	{
<>	135:176b8275d35d	6076	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6077	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6078	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6079	MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6080	}
<>	135:176b8275d35d	6081
<>	135:176b8275d35d	6082	/**
<>	135:176b8275d35d	6083	* @brief Get actual FAULT state.
<>	135:176b8275d35d	6084	* @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
<>	135:176b8275d35d	6085	* OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
<>	135:176b8275d35d	6086	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6087	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6088	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6089	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6090	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6091	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6092	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6093	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6094	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6095	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6096	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6097	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6098	* @retval FaultState This parameter can be one of the following values:
<>	135:176b8275d35d	6099	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
<>	135:176b8275d35d	6100	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
<>	135:176b8275d35d	6101	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
<>	135:176b8275d35d	6102	* @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
<>	135:176b8275d35d	6103	*/
<>	135:176b8275d35d	6104	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6105	{
<>	135:176b8275d35d	6106	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6107	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6108	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6109	return (READ_BIT(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	6110	}
<>	135:176b8275d35d	6111
<>	135:176b8275d35d	6112	/**
<>	135:176b8275d35d	6113	* @brief Set the output chopper mode.
<>	135:176b8275d35d	6114	* @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
<>	135:176b8275d35d	6115	* OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
<>	135:176b8275d35d	6116	* @note This function must not called when the timer is enabled.
<>	135:176b8275d35d	6117	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6118	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6119	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6120	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6121	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6122	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6123	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6124	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6125	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6126	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6127	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6128	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6129	* @param ChopperMode This parameter can be one of the following values:
<>	135:176b8275d35d	6130	* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
<>	135:176b8275d35d	6131	* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
<>	135:176b8275d35d	6132	* @retval None
<>	135:176b8275d35d	6133	*/
<>	135:176b8275d35d	6134	__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
<>	135:176b8275d35d	6135	{
<>	135:176b8275d35d	6136	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6137	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6138	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6139	MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6140	}
<>	135:176b8275d35d	6141
<>	135:176b8275d35d	6142	/**
<>	135:176b8275d35d	6143	* @brief Get actual output chopper mode
<>	135:176b8275d35d	6144	* @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
<>	135:176b8275d35d	6145	* OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
<>	135:176b8275d35d	6146	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6147	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6148	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6149	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6150	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6151	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6152	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6153	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6154	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6155	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6156	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6157	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6158	* @retval ChopperMode This parameter can be one of the following values:
<>	135:176b8275d35d	6159	* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
<>	135:176b8275d35d	6160	* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
<>	135:176b8275d35d	6161	*/
<>	135:176b8275d35d	6162	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6163	{
<>	135:176b8275d35d	6164	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6165	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6166	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6167	return (READ_BIT(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	6168	}
<>	135:176b8275d35d	6169
<>	135:176b8275d35d	6170	/**
<>	135:176b8275d35d	6171	* @brief Set the output burst mode entry mode.
<>	135:176b8275d35d	6172	* @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
<>	135:176b8275d35d	6173	* OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
<>	135:176b8275d35d	6174	* @note This function must not called when the timer is enabled.
<>	135:176b8275d35d	6175	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6176	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6177	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6178	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6179	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6180	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6181	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6182	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6183	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6184	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6185	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6186	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6187	* @param BMEntryMode This parameter can be one of the following values:
<>	135:176b8275d35d	6188	* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
<>	135:176b8275d35d	6189	* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
<>	135:176b8275d35d	6190	* @retval None
<>	135:176b8275d35d	6191	*/
<>	135:176b8275d35d	6192	__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
<>	135:176b8275d35d	6193	{
<>	135:176b8275d35d	6194	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6195	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6196	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6197	MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6198	}
<>	135:176b8275d35d	6199
<>	135:176b8275d35d	6200	/**
<>	135:176b8275d35d	6201	* @brief Get actual output burst mode entry mode.
<>	135:176b8275d35d	6202	* @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
<>	135:176b8275d35d	6203	* OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
<>	135:176b8275d35d	6204	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6205	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6206	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6207	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6208	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6209	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6210	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6211	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6212	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6213	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6214	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6215	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6216	* @retval BMEntryMode This parameter can be one of the following values:
<>	135:176b8275d35d	6217	* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
<>	135:176b8275d35d	6218	* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
<>	135:176b8275d35d	6219	*/
<>	135:176b8275d35d	6220	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6221	{
<>	135:176b8275d35d	6222	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6223	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
<>	135:176b8275d35d	6224	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6225	return (READ_BIT(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
<>	135:176b8275d35d	6226	}
<>	135:176b8275d35d	6227
<>	135:176b8275d35d	6228	/**
<>	135:176b8275d35d	6229	* @brief Get the level (active or inactive) of the designated output when the
<>	135:176b8275d35d	6230	* delayed protection was triggered.
<>	135:176b8275d35d	6231	* @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
<>	135:176b8275d35d	6232	* TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
<>	135:176b8275d35d	6233	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6234	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6235	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6236	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6237	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6238	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6239	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6240	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6241	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6242	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6243	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6244	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6245	* @retval OutputLevel This parameter can be one of the following values:
<>	135:176b8275d35d	6246	* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
<>	135:176b8275d35d	6247	* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
<>	135:176b8275d35d	6248	*/
<>	135:176b8275d35d	6249	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6250	{
<>	135:176b8275d35d	6251	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6252	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
<>	135:176b8275d35d	6253	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6254	return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
<>	135:176b8275d35d	6255	HRTIM_TIMISR_O1STAT_Pos);
<>	135:176b8275d35d	6256	}
<>	135:176b8275d35d	6257
<>	135:176b8275d35d	6258	/**
<>	135:176b8275d35d	6259	* @brief Force the timer output to its active or inactive level.
<>	135:176b8275d35d	6260	* @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
<>	135:176b8275d35d	6261	* RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
<>	135:176b8275d35d	6262	* SETx2R SST LL_HRTIM_OUT_ForceLevel\n
<>	135:176b8275d35d	6263	* RSTx2R SRT LL_HRTIM_OUT_ForceLevel
<>	135:176b8275d35d	6264	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6265	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6266	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6267	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6268	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6269	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6270	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6271	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6272	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6273	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6274	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6275	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6276	* @param OutputLevel This parameter can be one of the following values:
<>	135:176b8275d35d	6277	* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
<>	135:176b8275d35d	6278	* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
<>	135:176b8275d35d	6279	* @retval None
<>	135:176b8275d35d	6280	*/
<>	135:176b8275d35d	6281	__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
<>	135:176b8275d35d	6282	{
<>	135:176b8275d35d	6283	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6284	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
<>	135:176b8275d35d	6285	REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
<>	135:176b8275d35d	6286	SET_BIT(*pReg, HRTIM_SET1R_SST);
<>	135:176b8275d35d	6287	}
<>	135:176b8275d35d	6288
<>	135:176b8275d35d	6289	/**
<>	135:176b8275d35d	6290	* @brief Get actual output level, before the output stage (chopper, polarity).
<>	135:176b8275d35d	6291	* @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
<>	135:176b8275d35d	6292	* TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
<>	135:176b8275d35d	6293	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6294	* @param Output This parameter can be one of the following values:
<>	135:176b8275d35d	6295	* @arg @ref LL_HRTIM_OUTPUT_TA1
<>	135:176b8275d35d	6296	* @arg @ref LL_HRTIM_OUTPUT_TA2
<>	135:176b8275d35d	6297	* @arg @ref LL_HRTIM_OUTPUT_TB1
<>	135:176b8275d35d	6298	* @arg @ref LL_HRTIM_OUTPUT_TB2
<>	135:176b8275d35d	6299	* @arg @ref LL_HRTIM_OUTPUT_TC1
<>	135:176b8275d35d	6300	* @arg @ref LL_HRTIM_OUTPUT_TC2
<>	135:176b8275d35d	6301	* @arg @ref LL_HRTIM_OUTPUT_TD1
<>	135:176b8275d35d	6302	* @arg @ref LL_HRTIM_OUTPUT_TD2
<>	135:176b8275d35d	6303	* @arg @ref LL_HRTIM_OUTPUT_TE1
<>	135:176b8275d35d	6304	* @arg @ref LL_HRTIM_OUTPUT_TE2
<>	135:176b8275d35d	6305	* @retval OutputLevel This parameter can be one of the following values:
<>	135:176b8275d35d	6306	* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
<>	135:176b8275d35d	6307	* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
<>	135:176b8275d35d	6308	*/
<>	135:176b8275d35d	6309	__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
<>	135:176b8275d35d	6310	{
<>	135:176b8275d35d	6311	register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
<>	135:176b8275d35d	6312	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
<>	135:176b8275d35d	6313	REG_OFFSET_TAB_OUTxR[iOutput]));
<>	135:176b8275d35d	6314	return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
<>	135:176b8275d35d	6315	HRTIM_TIMISR_O1CPY_Pos);
<>	135:176b8275d35d	6316	}
<>	135:176b8275d35d	6317
<>	135:176b8275d35d	6318	/**
<>	135:176b8275d35d	6319	* @}
<>	135:176b8275d35d	6320	*/
<>	135:176b8275d35d	6321
<>	135:176b8275d35d	6322	/** @defgroup HRTIM_EF_External_Event_management External_Event_management
<>	135:176b8275d35d	6323	* @{
<>	135:176b8275d35d	6324	*/
<>	135:176b8275d35d	6325
<>	135:176b8275d35d	6326	/**
<>	135:176b8275d35d	6327	* @brief Configure external event conditioning.
<>	135:176b8275d35d	6328	* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6329	* EECR1 EE1POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6330	* EECR1 EE1SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6331	* EECR1 EE1FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6332	* EECR1 EE2SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6333	* EECR1 EE2POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6334	* EECR1 EE2SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6335	* EECR1 EE2FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6336	* EECR1 EE3SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6337	* EECR1 EE3POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6338	* EECR1 EE3SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6339	* EECR1 EE3FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6340	* EECR1 EE4SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6341	* EECR1 EE4POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6342	* EECR1 EE4SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6343	* EECR1 EE4FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6344	* EECR1 EE5SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6345	* EECR1 EE5POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6346	* EECR1 EE5SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6347	* EECR1 EE5FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6348	* EECR2 EE6SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6349	* EECR2 EE6POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6350	* EECR2 EE6SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6351	* EECR2 EE6FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6352	* EECR2 EE7SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6353	* EECR2 EE7POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6354	* EECR2 EE7SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6355	* EECR2 EE7FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6356	* EECR2 EE8SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6357	* EECR2 EE8POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6358	* EECR2 EE8SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6359	* EECR2 EE8FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6360	* EECR2 EE9SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6361	* EECR2 EE9POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6362	* EECR2 EE9SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6363	* EECR2 EE9FAST LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6364	* EECR2 EE10SRC LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6365	* EECR2 EE10POL LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6366	* EECR2 EE10SNS LL_HRTIM_EE_Config\n
<>	135:176b8275d35d	6367	* EECR2 EE10FAST LL_HRTIM_EE_Config
<>	135:176b8275d35d	6368	* @note This function must not be called when the timer counter is enabled.
<>	135:176b8275d35d	6369	* @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
<>	135:176b8275d35d	6370	* @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
<>	135:176b8275d35d	6371	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6372	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6373	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6374	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6375	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6376	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6377	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6378	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6379	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6380	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6381	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6382	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6383	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	6384	* @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4
<>	135:176b8275d35d	6385	* @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
<>	135:176b8275d35d	6386	* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
<>	135:176b8275d35d	6387	* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
<>	135:176b8275d35d	6388	* @retval None
<>	135:176b8275d35d	6389	*/
<>	135:176b8275d35d	6390	__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
<>	135:176b8275d35d	6391	{
<>	135:176b8275d35d	6392	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6393	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6394	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6395	MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
<>	135:176b8275d35d	6396	(Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6397	}
<>	135:176b8275d35d	6398
<>	135:176b8275d35d	6399	/**
<>	135:176b8275d35d	6400	* @brief Set the external event source.
<>	135:176b8275d35d	6401	* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6402	* EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6403	* EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6404	* EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6405	* EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6406	* EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6407	* EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6408	* EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6409	* EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
<>	135:176b8275d35d	6410	* EECR2 EE10SRC LL_HRTIM_EE_SetSrc
<>	135:176b8275d35d	6411	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6412	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6413	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6414	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6415	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6416	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6417	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6418	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6419	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6420	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6421	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6422	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6423	* @param Src This parameter can be one of the following values:
<>	135:176b8275d35d	6424	* @arg @ref LL_HRTIM_EE_SRC_1
<>	135:176b8275d35d	6425	* @arg @ref LL_HRTIM_EE_SRC_2
<>	135:176b8275d35d	6426	* @arg @ref LL_HRTIM_EE_SRC_3
<>	135:176b8275d35d	6427	* @arg @ref LL_HRTIM_EE_SRC_4
<>	135:176b8275d35d	6428	* @retval None
<>	135:176b8275d35d	6429	*/
<>	135:176b8275d35d	6430	__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
<>	135:176b8275d35d	6431	{
<>	135:176b8275d35d	6432	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6433	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6434	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6435	MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6436	}
<>	135:176b8275d35d	6437
<>	135:176b8275d35d	6438	/**
<>	135:176b8275d35d	6439	* @brief Get actual external event source.
<>	135:176b8275d35d	6440	* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6441	* EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6442	* EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6443	* EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6444	* EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6445	* EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6446	* EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6447	* EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6448	* EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
<>	135:176b8275d35d	6449	* EECR2 EE10SRC LL_HRTIM_EE_GetSrc
<>	135:176b8275d35d	6450	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6451	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6452	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6453	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6454	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6455	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6456	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6457	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6458	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6459	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6460	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6461	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6462	* @retval EventSrc This parameter can be one of the following values:
<>	135:176b8275d35d	6463	* @arg @ref LL_HRTIM_EE_SRC_1
<>	135:176b8275d35d	6464	* @arg @ref LL_HRTIM_EE_SRC_2
<>	135:176b8275d35d	6465	* @arg @ref LL_HRTIM_EE_SRC_3
<>	135:176b8275d35d	6466	* @arg @ref LL_HRTIM_EE_SRC_4
<>	135:176b8275d35d	6467	*/
<>	135:176b8275d35d	6468	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
<>	135:176b8275d35d	6469	{
<>	135:176b8275d35d	6470	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6471	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6472	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6473	return (READ_BIT(*pReg, HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	6474	}
<>	135:176b8275d35d	6475
<>	135:176b8275d35d	6476	/**
<>	135:176b8275d35d	6477	* @brief Set the polarity of an external event.
<>	135:176b8275d35d	6478	* @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6479	* EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6480	* EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6481	* EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6482	* EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6483	* EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6484	* EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6485	* EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6486	* EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
<>	135:176b8275d35d	6487	* EECR2 EE10POL LL_HRTIM_EE_SetPolarity
<>	135:176b8275d35d	6488	* @note This function must not be called when the timer counter is enabled.
<>	135:176b8275d35d	6489	* @note Event polarity is only significant when event detection is level-sensitive.
<>	135:176b8275d35d	6490	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6491	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6492	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6493	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6494	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6495	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6496	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6497	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6498	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6499	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6500	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6501	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6502	* @param Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	6503	* @arg @ref LL_HRTIM_EE_POLARITY_HIGH
<>	135:176b8275d35d	6504	* @arg @ref LL_HRTIM_EE_POLARITY_LOW
<>	135:176b8275d35d	6505	* @retval None
<>	135:176b8275d35d	6506	*/
<>	135:176b8275d35d	6507	__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
<>	135:176b8275d35d	6508	{
<>	135:176b8275d35d	6509	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6510	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6511	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6512	MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6513	}
<>	135:176b8275d35d	6514
<>	135:176b8275d35d	6515	/**
<>	135:176b8275d35d	6516	* @brief Get actual polarity setting of an external event.
<>	135:176b8275d35d	6517	* @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6518	* EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6519	* EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6520	* EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6521	* EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6522	* EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6523	* EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6524	* EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6525	* EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
<>	135:176b8275d35d	6526	* EECR2 EE10POL LL_HRTIM_EE_GetPolarity
<>	135:176b8275d35d	6527	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6528	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6529	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6530	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6531	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6532	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6533	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6534	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6535	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6536	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6537	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6538	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6539	* @retval Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	6540	* @arg @ref LL_HRTIM_EE_POLARITY_HIGH
<>	135:176b8275d35d	6541	* @arg @ref LL_HRTIM_EE_POLARITY_LOW
<>	135:176b8275d35d	6542	*/
<>	135:176b8275d35d	6543	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
<>	135:176b8275d35d	6544	{
<>	135:176b8275d35d	6545	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6546	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6547	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6548	return (READ_BIT(*pReg, HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	6549	}
<>	135:176b8275d35d	6550
<>	135:176b8275d35d	6551	/**
<>	135:176b8275d35d	6552	* @brief Set the sensitivity of an external event.
<>	135:176b8275d35d	6553	* @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6554	* EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6555	* EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6556	* EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6557	* EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6558	* EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6559	* EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6560	* EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6561	* EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
<>	135:176b8275d35d	6562	* EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
<>	135:176b8275d35d	6563	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6564	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6565	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6566	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6567	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6568	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6569	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6570	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6571	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6572	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6573	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6574	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6575	* @param Sensitivity This parameter can be one of the following values:
<>	135:176b8275d35d	6576	* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
<>	135:176b8275d35d	6577	* @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
<>	135:176b8275d35d	6578	* @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
<>	135:176b8275d35d	6579	* @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
<>	135:176b8275d35d	6580	* @retval None
<>	135:176b8275d35d	6581	*/
<>	135:176b8275d35d	6582
<>	135:176b8275d35d	6583	__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
<>	135:176b8275d35d	6584	{
<>	135:176b8275d35d	6585	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6586	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6587	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6588	MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6589	}
<>	135:176b8275d35d	6590
<>	135:176b8275d35d	6591	/**
<>	135:176b8275d35d	6592	* @brief Get actual sensitivity setting of an external event.
<>	135:176b8275d35d	6593	* @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6594	* EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6595	* EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6596	* EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6597	* EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6598	* EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6599	* EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6600	* EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6601	* EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
<>	135:176b8275d35d	6602	* EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
<>	135:176b8275d35d	6603	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6604	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6605	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6606	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6607	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6608	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6609	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6610	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6611	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6612	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6613	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6614	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6615	* @retval Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	6616	* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
<>	135:176b8275d35d	6617	* @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
<>	135:176b8275d35d	6618	* @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
<>	135:176b8275d35d	6619	* @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
<>	135:176b8275d35d	6620	*/
<>	135:176b8275d35d	6621	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
<>	135:176b8275d35d	6622	{
<>	135:176b8275d35d	6623	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6624	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6625	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6626	return (READ_BIT(*pReg, HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	6627	}
<>	135:176b8275d35d	6628
<>	135:176b8275d35d	6629	/**
<>	135:176b8275d35d	6630	* @brief Set the fast mode of an external event.
<>	135:176b8275d35d	6631	* @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6632	* EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6633	* EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6634	* EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6635	* EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6636	* EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6637	* EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6638	* EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6639	* EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
<>	135:176b8275d35d	6640	* EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
<>	135:176b8275d35d	6641	* @note This function must not be called when the timer counter is enabled.
<>	135:176b8275d35d	6642	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6643	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6644	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6645	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6646	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6647	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6648	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6649	* @param FastMode This parameter can be one of the following values:
<>	135:176b8275d35d	6650	* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
<>	135:176b8275d35d	6651	* @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
<>	135:176b8275d35d	6652	* @retval None
<>	135:176b8275d35d	6653	*/
<>	135:176b8275d35d	6654	__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
<>	135:176b8275d35d	6655	{
<>	135:176b8275d35d	6656	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6657	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6658	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6659	MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6660	}
<>	135:176b8275d35d	6661
<>	135:176b8275d35d	6662	/**
<>	135:176b8275d35d	6663	* @brief Get actual fast mode setting of an external event.
<>	135:176b8275d35d	6664	* @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6665	* EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6666	* EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6667	* EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6668	* EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6669	* EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6670	* EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6671	* EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6672	* EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
<>	135:176b8275d35d	6673	* EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
<>	135:176b8275d35d	6674	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6675	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6676	* @arg @ref LL_HRTIM_EVENT_1
<>	135:176b8275d35d	6677	* @arg @ref LL_HRTIM_EVENT_2
<>	135:176b8275d35d	6678	* @arg @ref LL_HRTIM_EVENT_3
<>	135:176b8275d35d	6679	* @arg @ref LL_HRTIM_EVENT_4
<>	135:176b8275d35d	6680	* @arg @ref LL_HRTIM_EVENT_5
<>	135:176b8275d35d	6681	* @retval FastMode This parameter can be one of the following values:
<>	135:176b8275d35d	6682	* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
<>	135:176b8275d35d	6683	* @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
<>	135:176b8275d35d	6684	*/
<>	135:176b8275d35d	6685	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
<>	135:176b8275d35d	6686	{
<>	135:176b8275d35d	6687	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6688	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
<>	135:176b8275d35d	6689	REG_OFFSET_TAB_EECR[iEvent]));
<>	135:176b8275d35d	6690	return (READ_BIT(*pReg, HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	6691	}
<>	135:176b8275d35d	6692
<>	135:176b8275d35d	6693	/**
<>	135:176b8275d35d	6694	* @brief Set the digital noise filter of a external event.
<>	135:176b8275d35d	6695	* @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
<>	135:176b8275d35d	6696	* EECR3 EE7F LL_HRTIM_EE_SetFilter\n
<>	135:176b8275d35d	6697	* EECR3 EE8F LL_HRTIM_EE_SetFilter\n
<>	135:176b8275d35d	6698	* EECR3 EE9F LL_HRTIM_EE_SetFilter\n
<>	135:176b8275d35d	6699	* EECR3 EE10F LL_HRTIM_EE_SetFilter
<>	135:176b8275d35d	6700	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6701	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6702	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6703	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6704	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6705	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6706	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6707	* @param Filter This parameter can be one of the following values:
<>	135:176b8275d35d	6708	* @arg @ref LL_HRTIM_EE_FILTER_NONE
<>	135:176b8275d35d	6709	* @arg @ref LL_HRTIM_EE_FILTER_1
<>	135:176b8275d35d	6710	* @arg @ref LL_HRTIM_EE_FILTER_2
<>	135:176b8275d35d	6711	* @arg @ref LL_HRTIM_EE_FILTER_3
<>	135:176b8275d35d	6712	* @arg @ref LL_HRTIM_EE_FILTER_4
<>	135:176b8275d35d	6713	* @arg @ref LL_HRTIM_EE_FILTER_5
<>	135:176b8275d35d	6714	* @arg @ref LL_HRTIM_EE_FILTER_6
<>	135:176b8275d35d	6715	* @arg @ref LL_HRTIM_EE_FILTER_7
<>	135:176b8275d35d	6716	* @arg @ref LL_HRTIM_EE_FILTER_8
<>	135:176b8275d35d	6717	* @arg @ref LL_HRTIM_EE_FILTER_9
<>	135:176b8275d35d	6718	* @arg @ref LL_HRTIM_EE_FILTER_10
<>	135:176b8275d35d	6719	* @arg @ref LL_HRTIM_EE_FILTER_11
<>	135:176b8275d35d	6720	* @arg @ref LL_HRTIM_EE_FILTER_12
<>	135:176b8275d35d	6721	* @arg @ref LL_HRTIM_EE_FILTER_13
<>	135:176b8275d35d	6722	* @arg @ref LL_HRTIM_EE_FILTER_14
<>	135:176b8275d35d	6723	* @arg @ref LL_HRTIM_EE_FILTER_15
<>	135:176b8275d35d	6724	* @retval None
<>	135:176b8275d35d	6725	*/
<>	135:176b8275d35d	6726	__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
<>	135:176b8275d35d	6727	{
<>	135:176b8275d35d	6728	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
<>	135:176b8275d35d	6729	MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
<>	135:176b8275d35d	6730	(Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
<>	135:176b8275d35d	6731	}
<>	135:176b8275d35d	6732
<>	135:176b8275d35d	6733	/**
<>	135:176b8275d35d	6734	* @brief Get actual digital noise filter setting of a external event.
<>	135:176b8275d35d	6735	* @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
<>	135:176b8275d35d	6736	* EECR3 EE7F LL_HRTIM_EE_GetFilter\n
<>	135:176b8275d35d	6737	* EECR3 EE8F LL_HRTIM_EE_GetFilter\n
<>	135:176b8275d35d	6738	* EECR3 EE9F LL_HRTIM_EE_GetFilter\n
<>	135:176b8275d35d	6739	* EECR3 EE10F LL_HRTIM_EE_GetFilter
<>	135:176b8275d35d	6740	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6741	* @param Event This parameter can be one of the following values:
<>	135:176b8275d35d	6742	* @arg @ref LL_HRTIM_EVENT_6
<>	135:176b8275d35d	6743	* @arg @ref LL_HRTIM_EVENT_7
<>	135:176b8275d35d	6744	* @arg @ref LL_HRTIM_EVENT_8
<>	135:176b8275d35d	6745	* @arg @ref LL_HRTIM_EVENT_9
<>	135:176b8275d35d	6746	* @arg @ref LL_HRTIM_EVENT_10
<>	135:176b8275d35d	6747	* @retval Filter This parameter can be one of the following values:
<>	135:176b8275d35d	6748	* @arg @ref LL_HRTIM_EE_FILTER_NONE
<>	135:176b8275d35d	6749	* @arg @ref LL_HRTIM_EE_FILTER_1
<>	135:176b8275d35d	6750	* @arg @ref LL_HRTIM_EE_FILTER_2
<>	135:176b8275d35d	6751	* @arg @ref LL_HRTIM_EE_FILTER_3
<>	135:176b8275d35d	6752	* @arg @ref LL_HRTIM_EE_FILTER_4
<>	135:176b8275d35d	6753	* @arg @ref LL_HRTIM_EE_FILTER_5
<>	135:176b8275d35d	6754	* @arg @ref LL_HRTIM_EE_FILTER_6
<>	135:176b8275d35d	6755	* @arg @ref LL_HRTIM_EE_FILTER_7
<>	135:176b8275d35d	6756	* @arg @ref LL_HRTIM_EE_FILTER_8
<>	135:176b8275d35d	6757	* @arg @ref LL_HRTIM_EE_FILTER_9
<>	135:176b8275d35d	6758	* @arg @ref LL_HRTIM_EE_FILTER_10
<>	135:176b8275d35d	6759	* @arg @ref LL_HRTIM_EE_FILTER_11
<>	135:176b8275d35d	6760	* @arg @ref LL_HRTIM_EE_FILTER_12
<>	135:176b8275d35d	6761	* @arg @ref LL_HRTIM_EE_FILTER_13
<>	135:176b8275d35d	6762	* @arg @ref LL_HRTIM_EE_FILTER_14
<>	135:176b8275d35d	6763	* @arg @ref LL_HRTIM_EE_FILTER_15
<>	135:176b8275d35d	6764	*/
<>	135:176b8275d35d	6765	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
<>	135:176b8275d35d	6766	{
<>	135:176b8275d35d	6767	register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
<>	135:176b8275d35d	6768	return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
<>	135:176b8275d35d	6769	(HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent])) >> REG_SHIFT_TAB_EExSRC[iEvent]);
<>	135:176b8275d35d	6770	}
<>	135:176b8275d35d	6771
<>	135:176b8275d35d	6772	/**
<>	135:176b8275d35d	6773	* @brief Set the external event prescaler.
<>	135:176b8275d35d	6774	* @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
<>	135:176b8275d35d	6775	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6776	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	6777	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
<>	135:176b8275d35d	6778	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
<>	135:176b8275d35d	6779	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
<>	135:176b8275d35d	6780	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
<>	135:176b8275d35d	6781	* @retval None
<>	135:176b8275d35d	6782	*/
<>	135:176b8275d35d	6783
<>	135:176b8275d35d	6784	__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
<>	135:176b8275d35d	6785	{
<>	135:176b8275d35d	6786	MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
<>	135:176b8275d35d	6787	}
<>	135:176b8275d35d	6788
<>	135:176b8275d35d	6789	/**
<>	135:176b8275d35d	6790	* @brief Get actual external event prescaler setting.
<>	135:176b8275d35d	6791	* @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
<>	135:176b8275d35d	6792	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6793	* @retval Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	6794	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
<>	135:176b8275d35d	6795	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
<>	135:176b8275d35d	6796	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
<>	135:176b8275d35d	6797	* @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
<>	135:176b8275d35d	6798	*/
<>	135:176b8275d35d	6799
<>	135:176b8275d35d	6800	__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	6801	{
<>	135:176b8275d35d	6802	return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
<>	135:176b8275d35d	6803	}
<>	135:176b8275d35d	6804
<>	135:176b8275d35d	6805	/**
<>	135:176b8275d35d	6806	* @}
<>	135:176b8275d35d	6807	*/
<>	135:176b8275d35d	6808
<>	135:176b8275d35d	6809	/** @defgroup HRTIM_EF_Fault_management Fault_management
<>	135:176b8275d35d	6810	* @{
<>	135:176b8275d35d	6811	*/
<>	135:176b8275d35d	6812
<>	135:176b8275d35d	6813	/**
<>	135:176b8275d35d	6814	* @brief Configure fault signal conditioning.
<>	135:176b8275d35d	6815	* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6816	* FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6817	* FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6818	* FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6819	* FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6820	* FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6821	* FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6822	* FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6823	* FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
<>	135:176b8275d35d	6824	* FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
<>	135:176b8275d35d	6825	* @note This function must not be called when the fault channel is enabled.
<>	135:176b8275d35d	6826	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6827	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6828	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6829	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6830	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6831	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6832	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6833	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	6834	* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT or @ref LL_HRTIM_FLT_SRC_INTERNAL
<>	135:176b8275d35d	6835	* @arg @ref LL_HRTIM_FLT_POLARITY_LOW or @ref LL_HRTIM_FLT_POLARITY_HIGH
<>	135:176b8275d35d	6836	* @retval None
<>	135:176b8275d35d	6837	*/
<>	135:176b8275d35d	6838	__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
<>	135:176b8275d35d	6839	{
<>	135:176b8275d35d	6840	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6841	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6842	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6843	MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
<>	135:176b8275d35d	6844	(Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	6845	}
<>	135:176b8275d35d	6846
<>	135:176b8275d35d	6847	/**
<>	135:176b8275d35d	6848	* @brief Set the source of a fault signal.
<>	135:176b8275d35d	6849	* @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
<>	135:176b8275d35d	6850	* FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
<>	135:176b8275d35d	6851	* FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
<>	135:176b8275d35d	6852	* FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
<>	135:176b8275d35d	6853	* FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
<>	135:176b8275d35d	6854	* @note This function must not be called when the fault channel is enabled.
<>	135:176b8275d35d	6855	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6856	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6857	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6858	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6859	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6860	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6861	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6862	* @param Src This parameter can be one of the following values:
<>	135:176b8275d35d	6863	* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
<>	135:176b8275d35d	6864	* @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
<>	135:176b8275d35d	6865	* @retval None
<>	135:176b8275d35d	6866	*/
<>	135:176b8275d35d	6867	__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
<>	135:176b8275d35d	6868	{
<>	135:176b8275d35d	6869	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6870	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6871	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6872	MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	6873	}
<>	135:176b8275d35d	6874
<>	135:176b8275d35d	6875	/**
<>	135:176b8275d35d	6876	* @brief Get actual source of a fault signal.
<>	135:176b8275d35d	6877	* @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
<>	135:176b8275d35d	6878	* FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
<>	135:176b8275d35d	6879	* FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
<>	135:176b8275d35d	6880	* FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
<>	135:176b8275d35d	6881	* FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
<>	135:176b8275d35d	6882	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6883	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6884	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6885	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6886	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6887	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6888	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6889	* @retval Src This parameter can be one of the following values:
<>	135:176b8275d35d	6890	* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
<>	135:176b8275d35d	6891	* @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
<>	135:176b8275d35d	6892	*/
<>	135:176b8275d35d	6893	__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	6894	{
<>	135:176b8275d35d	6895	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6896	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6897	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6898	return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
<>	135:176b8275d35d	6899	}
<>	135:176b8275d35d	6900
<>	135:176b8275d35d	6901	/**
<>	135:176b8275d35d	6902	* @brief Set the polarity of a fault signal.
<>	135:176b8275d35d	6903	* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
<>	135:176b8275d35d	6904	* FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
<>	135:176b8275d35d	6905	* FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
<>	135:176b8275d35d	6906	* FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
<>	135:176b8275d35d	6907	* FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
<>	135:176b8275d35d	6908	* @note This function must not be called when the fault channel is enabled.
<>	135:176b8275d35d	6909	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6910	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6911	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6912	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6913	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6914	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6915	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6916	* @param Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	6917	* @arg @ref LL_HRTIM_FLT_POLARITY_LOW
<>	135:176b8275d35d	6918	* @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
<>	135:176b8275d35d	6919	* @retval None
<>	135:176b8275d35d	6920	*/
<>	135:176b8275d35d	6921	__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
<>	135:176b8275d35d	6922	{
<>	135:176b8275d35d	6923	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6924	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6925	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6926	MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	6927	}
<>	135:176b8275d35d	6928
<>	135:176b8275d35d	6929	/**
<>	135:176b8275d35d	6930	* @brief Get actual polarity of a fault signal.
<>	135:176b8275d35d	6931	* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
<>	135:176b8275d35d	6932	* FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
<>	135:176b8275d35d	6933	* FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
<>	135:176b8275d35d	6934	* FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
<>	135:176b8275d35d	6935	* FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
<>	135:176b8275d35d	6936	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6937	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6938	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6939	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6940	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6941	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6942	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6943	* @retval Polarity This parameter can be one of the following values:
<>	135:176b8275d35d	6944	* @arg @ref LL_HRTIM_FLT_POLARITY_LOW
<>	135:176b8275d35d	6945	* @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
<>	135:176b8275d35d	6946	*/
<>	135:176b8275d35d	6947	__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	6948	{
<>	135:176b8275d35d	6949	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6950	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6951	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6952	return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
<>	135:176b8275d35d	6953	}
<>	135:176b8275d35d	6954
<>	135:176b8275d35d	6955	/**
<>	135:176b8275d35d	6956	* @brief Set the digital noise filter of a fault signal.
<>	135:176b8275d35d	6957	* @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
<>	135:176b8275d35d	6958	* FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
<>	135:176b8275d35d	6959	* FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
<>	135:176b8275d35d	6960	* FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
<>	135:176b8275d35d	6961	* FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
<>	135:176b8275d35d	6962	* @note This function must not be called when the fault channel is enabled.
<>	135:176b8275d35d	6963	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	6964	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	6965	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	6966	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	6967	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	6968	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	6969	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	6970	* @param Filter This parameter can be one of the following values:
<>	135:176b8275d35d	6971	* @arg @ref LL_HRTIM_FLT_FILTER_NONE
<>	135:176b8275d35d	6972	* @arg @ref LL_HRTIM_FLT_FILTER_1
<>	135:176b8275d35d	6973	* @arg @ref LL_HRTIM_FLT_FILTER_2
<>	135:176b8275d35d	6974	* @arg @ref LL_HRTIM_FLT_FILTER_3
<>	135:176b8275d35d	6975	* @arg @ref LL_HRTIM_FLT_FILTER_4
<>	135:176b8275d35d	6976	* @arg @ref LL_HRTIM_FLT_FILTER_5
<>	135:176b8275d35d	6977	* @arg @ref LL_HRTIM_FLT_FILTER_6
<>	135:176b8275d35d	6978	* @arg @ref LL_HRTIM_FLT_FILTER_7
<>	135:176b8275d35d	6979	* @arg @ref LL_HRTIM_FLT_FILTER_8
<>	135:176b8275d35d	6980	* @arg @ref LL_HRTIM_FLT_FILTER_9
<>	135:176b8275d35d	6981	* @arg @ref LL_HRTIM_FLT_FILTER_10
<>	135:176b8275d35d	6982	* @arg @ref LL_HRTIM_FLT_FILTER_11
<>	135:176b8275d35d	6983	* @arg @ref LL_HRTIM_FLT_FILTER_12
<>	135:176b8275d35d	6984	* @arg @ref LL_HRTIM_FLT_FILTER_13
<>	135:176b8275d35d	6985	* @arg @ref LL_HRTIM_FLT_FILTER_14
<>	135:176b8275d35d	6986	* @arg @ref LL_HRTIM_FLT_FILTER_15
<>	135:176b8275d35d	6987	* @retval None
<>	135:176b8275d35d	6988	*/
<>	135:176b8275d35d	6989	__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
<>	135:176b8275d35d	6990	{
<>	135:176b8275d35d	6991	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	6992	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	6993	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	6994	MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	6995	}
<>	135:176b8275d35d	6996
<>	135:176b8275d35d	6997	/**
<>	135:176b8275d35d	6998	* @brief Get actual digital noise filter setting of a fault signal.
<>	135:176b8275d35d	6999	* @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
<>	135:176b8275d35d	7000	* FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
<>	135:176b8275d35d	7001	* FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
<>	135:176b8275d35d	7002	* FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
<>	135:176b8275d35d	7003	* FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
<>	135:176b8275d35d	7004	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7005	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	7006	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	7007	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	7008	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	7009	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	7010	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	7011	* @retval Filter This parameter can be one of the following values:
<>	135:176b8275d35d	7012	* @arg @ref LL_HRTIM_FLT_FILTER_NONE
<>	135:176b8275d35d	7013	* @arg @ref LL_HRTIM_FLT_FILTER_1
<>	135:176b8275d35d	7014	* @arg @ref LL_HRTIM_FLT_FILTER_2
<>	135:176b8275d35d	7015	* @arg @ref LL_HRTIM_FLT_FILTER_3
<>	135:176b8275d35d	7016	* @arg @ref LL_HRTIM_FLT_FILTER_4
<>	135:176b8275d35d	7017	* @arg @ref LL_HRTIM_FLT_FILTER_5
<>	135:176b8275d35d	7018	* @arg @ref LL_HRTIM_FLT_FILTER_6
<>	135:176b8275d35d	7019	* @arg @ref LL_HRTIM_FLT_FILTER_7
<>	135:176b8275d35d	7020	* @arg @ref LL_HRTIM_FLT_FILTER_8
<>	135:176b8275d35d	7021	* @arg @ref LL_HRTIM_FLT_FILTER_9
<>	135:176b8275d35d	7022	* @arg @ref LL_HRTIM_FLT_FILTER_10
<>	135:176b8275d35d	7023	* @arg @ref LL_HRTIM_FLT_FILTER_11
<>	135:176b8275d35d	7024	* @arg @ref LL_HRTIM_FLT_FILTER_12
<>	135:176b8275d35d	7025	* @arg @ref LL_HRTIM_FLT_FILTER_13
<>	135:176b8275d35d	7026	* @arg @ref LL_HRTIM_FLT_FILTER_14
<>	135:176b8275d35d	7027	* @arg @ref LL_HRTIM_FLT_FILTER_15
<>	135:176b8275d35d	7028	*/
<>	135:176b8275d35d	7029	__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	7030	{
<>	135:176b8275d35d	7031	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	7032	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	7033	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	7034	return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
<>	135:176b8275d35d	7035	}
<>	135:176b8275d35d	7036
<>	135:176b8275d35d	7037	/**
<>	135:176b8275d35d	7038	* @brief Set the fault circuitry prescaler.
<>	135:176b8275d35d	7039	* @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
<>	135:176b8275d35d	7040	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7041	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	7042	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
<>	135:176b8275d35d	7043	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
<>	135:176b8275d35d	7044	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
<>	135:176b8275d35d	7045	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
<>	135:176b8275d35d	7046	* @retval None
<>	135:176b8275d35d	7047	*/
<>	135:176b8275d35d	7048	__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
<>	135:176b8275d35d	7049	{
<>	135:176b8275d35d	7050	MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
<>	135:176b8275d35d	7051	}
<>	135:176b8275d35d	7052
<>	135:176b8275d35d	7053	/**
<>	135:176b8275d35d	7054	* @brief Get actual fault circuitry prescaler setting.
<>	135:176b8275d35d	7055	* @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
<>	135:176b8275d35d	7056	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7057	* @retval Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	7058	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
<>	135:176b8275d35d	7059	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
<>	135:176b8275d35d	7060	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
<>	135:176b8275d35d	7061	* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
<>	135:176b8275d35d	7062	*/
<>	135:176b8275d35d	7063	__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7064	{
<>	135:176b8275d35d	7065	return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
<>	135:176b8275d35d	7066
<>	135:176b8275d35d	7067	}
<>	135:176b8275d35d	7068
<>	135:176b8275d35d	7069	/**
<>	135:176b8275d35d	7070	* @brief Lock the fault signal conditioning settings.
<>	135:176b8275d35d	7071	* @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
<>	135:176b8275d35d	7072	* FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
<>	135:176b8275d35d	7073	* FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
<>	135:176b8275d35d	7074	* FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
<>	135:176b8275d35d	7075	* FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
<>	135:176b8275d35d	7076	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7077	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	7078	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	7079	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	7080	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	7081	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	7082	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	7083	* @retval None
<>	135:176b8275d35d	7084	*/
<>	135:176b8275d35d	7085	__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	7086	{
<>	135:176b8275d35d	7087	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	7088	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	7089	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	7090	SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	7091	}
<>	135:176b8275d35d	7092
<>	135:176b8275d35d	7093	/**
<>	135:176b8275d35d	7094	* @brief Enable the fault circuitry for the designated fault input.
<>	135:176b8275d35d	7095	* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
<>	135:176b8275d35d	7096	* FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
<>	135:176b8275d35d	7097	* FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
<>	135:176b8275d35d	7098	* FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
<>	135:176b8275d35d	7099	* FLTINR2 FLT5E LL_HRTIM_FLT_Enable
<>	135:176b8275d35d	7100	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7101	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	7102	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	7103	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	7104	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	7105	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	7106	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	7107	* @retval None
<>	135:176b8275d35d	7108	*/
<>	135:176b8275d35d	7109	__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	7110	{
<>	135:176b8275d35d	7111	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	7112	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	7113	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	7114	SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	7115	}
<>	135:176b8275d35d	7116
<>	135:176b8275d35d	7117	/**
<>	135:176b8275d35d	7118	* @brief Disable the fault circuitry for for the designated fault input.
<>	135:176b8275d35d	7119	* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
<>	135:176b8275d35d	7120	* FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
<>	135:176b8275d35d	7121	* FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
<>	135:176b8275d35d	7122	* FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
<>	135:176b8275d35d	7123	* FLTINR2 FLT5E LL_HRTIM_FLT_Disable
<>	135:176b8275d35d	7124	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7125	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	7126	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	7127	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	7128	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	7129	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	7130	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	7131	* @retval None
<>	135:176b8275d35d	7132	*/
<>	135:176b8275d35d	7133	__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	7134	{
<>	135:176b8275d35d	7135	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	7136	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	7137	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	7138	CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
<>	135:176b8275d35d	7139	}
<>	135:176b8275d35d	7140
<>	135:176b8275d35d	7141	/**
<>	135:176b8275d35d	7142	* @brief Indicate whether the fault circuitry is enabled for a given fault input.
<>	135:176b8275d35d	7143	* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
<>	135:176b8275d35d	7144	* FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
<>	135:176b8275d35d	7145	* FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
<>	135:176b8275d35d	7146	* FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
<>	135:176b8275d35d	7147	* FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
<>	135:176b8275d35d	7148	* @param HRTIMx High Resolution Timer instance * @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7149	* @param Fault This parameter can be one of the following values:
<>	135:176b8275d35d	7150	* @arg @ref LL_HRTIM_FAULT_1
<>	135:176b8275d35d	7151	* @arg @ref LL_HRTIM_FAULT_2
<>	135:176b8275d35d	7152	* @arg @ref LL_HRTIM_FAULT_3
<>	135:176b8275d35d	7153	* @arg @ref LL_HRTIM_FAULT_4
<>	135:176b8275d35d	7154	* @arg @ref LL_HRTIM_FAULT_5
<>	135:176b8275d35d	7155	* @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
<>	135:176b8275d35d	7156	*/
<>	135:176b8275d35d	7157	__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
<>	135:176b8275d35d	7158	{
<>	135:176b8275d35d	7159	register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
<>	135:176b8275d35d	7160	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
<>	135:176b8275d35d	7161	REG_OFFSET_TAB_FLTINR[iFault]));
<>	135:176b8275d35d	7162	return ((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
<>	135:176b8275d35d	7163	(HRTIM_IER_FLT1));
<>	135:176b8275d35d	7164	}
<>	135:176b8275d35d	7165
<>	135:176b8275d35d	7166	/**
<>	135:176b8275d35d	7167	* @}
<>	135:176b8275d35d	7168	*/
<>	135:176b8275d35d	7169
<>	135:176b8275d35d	7170	/** @defgroup HRTIM_EF_Burst_Mode_management Burst_Mode_management
<>	135:176b8275d35d	7171	* @{
<>	135:176b8275d35d	7172	*/
<>	135:176b8275d35d	7173
<>	135:176b8275d35d	7174	/**
<>	135:176b8275d35d	7175	* @brief Configure the burst mode controller.
<>	135:176b8275d35d	7176	* @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
<>	135:176b8275d35d	7177	* BMCR BMCLK LL_HRTIM_BM_Config\n
<>	135:176b8275d35d	7178	* BMCR BMPRSC LL_HRTIM_BM_Config
<>	135:176b8275d35d	7179	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7180	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	7181	* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
<>	135:176b8275d35d	7182	* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
<>	135:176b8275d35d	7183	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
<>	135:176b8275d35d	7184	* @retval None
<>	135:176b8275d35d	7185	*/
<>	135:176b8275d35d	7186	__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
<>	135:176b8275d35d	7187	{
<>	135:176b8275d35d	7188	MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
<>	135:176b8275d35d	7189	}
<>	135:176b8275d35d	7190
<>	135:176b8275d35d	7191	/**
<>	135:176b8275d35d	7192	* @brief Set the burst mode controller operating mode.
<>	135:176b8275d35d	7193	* @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
<>	135:176b8275d35d	7194	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7195	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	7196	* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
<>	135:176b8275d35d	7197	* @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
<>	135:176b8275d35d	7198	* @retval None
<>	135:176b8275d35d	7199	*/
<>	135:176b8275d35d	7200	__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
<>	135:176b8275d35d	7201	{
<>	135:176b8275d35d	7202	MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
<>	135:176b8275d35d	7203	}
<>	135:176b8275d35d	7204
<>	135:176b8275d35d	7205	/**
<>	135:176b8275d35d	7206	* @brief Get actual burst mode controller operating mode.
<>	135:176b8275d35d	7207	* @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
<>	135:176b8275d35d	7208	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7209	* @retval Mode This parameter can be one of the following values:
<>	135:176b8275d35d	7210	* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
<>	135:176b8275d35d	7211	* @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
<>	135:176b8275d35d	7212	*/
<>	135:176b8275d35d	7213	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7214	{
<>	135:176b8275d35d	7215	return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
<>	135:176b8275d35d	7216	}
<>	135:176b8275d35d	7217
<>	135:176b8275d35d	7218	/**
<>	135:176b8275d35d	7219	* @brief Set the burst mode controller clock source.
<>	135:176b8275d35d	7220	* @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
<>	135:176b8275d35d	7221	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7222	* @param ClockSrc This parameter can be one of the following values:
<>	135:176b8275d35d	7223	* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
<>	135:176b8275d35d	7224	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
<>	135:176b8275d35d	7225	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
<>	135:176b8275d35d	7226	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
<>	135:176b8275d35d	7227	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
<>	135:176b8275d35d	7228	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
<>	135:176b8275d35d	7229	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
<>	135:176b8275d35d	7230	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
<>	135:176b8275d35d	7231	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
<>	135:176b8275d35d	7232	* @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
<>	135:176b8275d35d	7233	* @retval None
<>	135:176b8275d35d	7234	*/
<>	135:176b8275d35d	7235	__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
<>	135:176b8275d35d	7236	{
<>	135:176b8275d35d	7237	MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
<>	135:176b8275d35d	7238	}
<>	135:176b8275d35d	7239
<>	135:176b8275d35d	7240	/**
<>	135:176b8275d35d	7241	* @brief Get actual burst mode controller clock source.
<>	135:176b8275d35d	7242	* @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
<>	135:176b8275d35d	7243	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7244	* @retval ClockSrc This parameter can be one of the following values:
<>	135:176b8275d35d	7245	* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
<>	135:176b8275d35d	7246	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
<>	135:176b8275d35d	7247	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
<>	135:176b8275d35d	7248	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
<>	135:176b8275d35d	7249	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
<>	135:176b8275d35d	7250	* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
<>	135:176b8275d35d	7251	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
<>	135:176b8275d35d	7252	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
<>	135:176b8275d35d	7253	* @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
<>	135:176b8275d35d	7254	* @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
<>	135:176b8275d35d	7255	*/
<>	135:176b8275d35d	7256	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7257	{
<>	135:176b8275d35d	7258	return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
<>	135:176b8275d35d	7259	}
<>	135:176b8275d35d	7260
<>	135:176b8275d35d	7261	/**
<>	135:176b8275d35d	7262	* @brief Set the burst mode controller prescaler.
<>	135:176b8275d35d	7263	* @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
<>	135:176b8275d35d	7264	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7265	* @param Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	7266	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
<>	135:176b8275d35d	7267	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
<>	135:176b8275d35d	7268	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
<>	135:176b8275d35d	7269	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
<>	135:176b8275d35d	7270	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
<>	135:176b8275d35d	7271	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
<>	135:176b8275d35d	7272	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
<>	135:176b8275d35d	7273	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
<>	135:176b8275d35d	7274	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
<>	135:176b8275d35d	7275	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
<>	135:176b8275d35d	7276	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
<>	135:176b8275d35d	7277	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
<>	135:176b8275d35d	7278	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
<>	135:176b8275d35d	7279	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
<>	135:176b8275d35d	7280	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
<>	135:176b8275d35d	7281	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
<>	135:176b8275d35d	7282	* @retval None
<>	135:176b8275d35d	7283	*/
<>	135:176b8275d35d	7284	__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
<>	135:176b8275d35d	7285	{
<>	135:176b8275d35d	7286	MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
<>	135:176b8275d35d	7287	}
<>	135:176b8275d35d	7288
<>	135:176b8275d35d	7289	/**
<>	135:176b8275d35d	7290	* @brief Get actual burst mode controller prescaler setting.
<>	135:176b8275d35d	7291	* @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
<>	135:176b8275d35d	7292	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7293	* @retval Prescaler This parameter can be one of the following values:
<>	135:176b8275d35d	7294	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
<>	135:176b8275d35d	7295	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
<>	135:176b8275d35d	7296	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
<>	135:176b8275d35d	7297	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
<>	135:176b8275d35d	7298	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
<>	135:176b8275d35d	7299	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
<>	135:176b8275d35d	7300	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
<>	135:176b8275d35d	7301	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
<>	135:176b8275d35d	7302	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
<>	135:176b8275d35d	7303	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
<>	135:176b8275d35d	7304	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
<>	135:176b8275d35d	7305	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
<>	135:176b8275d35d	7306	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
<>	135:176b8275d35d	7307	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
<>	135:176b8275d35d	7308	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
<>	135:176b8275d35d	7309	* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
<>	135:176b8275d35d	7310	*/
<>	135:176b8275d35d	7311	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7312	{
<>	135:176b8275d35d	7313	return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
<>	135:176b8275d35d	7314	}
<>	135:176b8275d35d	7315
<>	135:176b8275d35d	7316	/**
<>	135:176b8275d35d	7317	* @brief Enable burst mode compare and period registers preload.
<>	135:176b8275d35d	7318	* @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
<>	135:176b8275d35d	7319	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7320	* @retval None
<>	135:176b8275d35d	7321	*/
<>	135:176b8275d35d	7322	__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7323	{
<>	135:176b8275d35d	7324	SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
<>	135:176b8275d35d	7325	}
<>	135:176b8275d35d	7326
<>	135:176b8275d35d	7327	/**
<>	135:176b8275d35d	7328	* @brief Disable burst mode compare and period registers preload.
<>	135:176b8275d35d	7329	* @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
<>	135:176b8275d35d	7330	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7331	* @retval None
<>	135:176b8275d35d	7332	*/
<>	135:176b8275d35d	7333	__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7334	{
<>	135:176b8275d35d	7335	CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
<>	135:176b8275d35d	7336	}
<>	135:176b8275d35d	7337
<>	135:176b8275d35d	7338	/**
<>	135:176b8275d35d	7339	* @brief Indicate whether burst mode compare and period registers are preloaded.
<>	135:176b8275d35d	7340	* @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
<>	135:176b8275d35d	7341	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7342	* @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
<>	135:176b8275d35d	7343	*/
<>	135:176b8275d35d	7344	__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7345	{
<>	135:176b8275d35d	7346	return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN) == HRTIM_BMCR_BMPREN);
<>	135:176b8275d35d	7347	}
<>	135:176b8275d35d	7348
<>	135:176b8275d35d	7349	/**
<>	135:176b8275d35d	7350	* @brief Set the burst mode controller trigger
<>	135:176b8275d35d	7351	* @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7352	* BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7353	* BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7354	* BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7355	* BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7356	* BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7357	* BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7358	* BMTRGR TARST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7359	* BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7360	* BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7361	* BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7362	* BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7363	* BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7364	* BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7365	* BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7366	* BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7367	* BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7368	* BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7369	* BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7370	* BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7371	* BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7372	* BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7373	* BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7374	* BMTRGR TERST LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7375	* BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7376	* BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7377	* BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7378	* BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7379	* BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7380	* BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7381	* BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
<>	135:176b8275d35d	7382	* BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
<>	135:176b8275d35d	7383	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7384	* @param Trig This parameter can be a combination of the following values:
<>	135:176b8275d35d	7385	* @arg @ref LL_HRTIM_BM_TRIG_NONE
<>	135:176b8275d35d	7386	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
<>	135:176b8275d35d	7387	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
<>	135:176b8275d35d	7388	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
<>	135:176b8275d35d	7389	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
<>	135:176b8275d35d	7390	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
<>	135:176b8275d35d	7391	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
<>	135:176b8275d35d	7392	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
<>	135:176b8275d35d	7393	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
<>	135:176b8275d35d	7394	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
<>	135:176b8275d35d	7395	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
<>	135:176b8275d35d	7396	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
<>	135:176b8275d35d	7397	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
<>	135:176b8275d35d	7398	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
<>	135:176b8275d35d	7399	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
<>	135:176b8275d35d	7400	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
<>	135:176b8275d35d	7401	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
<>	135:176b8275d35d	7402	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
<>	135:176b8275d35d	7403	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
<>	135:176b8275d35d	7404	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
<>	135:176b8275d35d	7405	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
<>	135:176b8275d35d	7406	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
<>	135:176b8275d35d	7407	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
<>	135:176b8275d35d	7408	* @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
<>	135:176b8275d35d	7409	* @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
<>	135:176b8275d35d	7410	* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
<>	135:176b8275d35d	7411	* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
<>	135:176b8275d35d	7412	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
<>	135:176b8275d35d	7413	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
<>	135:176b8275d35d	7414	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
<>	135:176b8275d35d	7415	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
<>	135:176b8275d35d	7416	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
<>	135:176b8275d35d	7417	* @retval None
<>	135:176b8275d35d	7418	*/
<>	135:176b8275d35d	7419	__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
<>	135:176b8275d35d	7420	{
<>	135:176b8275d35d	7421	WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
<>	135:176b8275d35d	7422	}
<>	135:176b8275d35d	7423
<>	135:176b8275d35d	7424	/**
<>	135:176b8275d35d	7425	* @brief Get actual burst mode controller trigger.
<>	135:176b8275d35d	7426	* @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7427	* BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7428	* BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7429	* BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7430	* BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7431	* BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7432	* BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7433	* BMTRGR TARST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7434	* BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7435	* BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7436	* BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7437	* BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7438	* BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7439	* BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7440	* BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7441	* BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7442	* BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7443	* BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7444	* BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7445	* BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7446	* BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7447	* BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7448	* BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7449	* BMTRGR TERST LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7450	* BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7451	* BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7452	* BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7453	* BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7454	* BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7455	* BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7456	* BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
<>	135:176b8275d35d	7457	* BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
<>	135:176b8275d35d	7458	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7459	* @retval Trig This parameter can be a combination of the following values:
<>	135:176b8275d35d	7460	* @arg @ref LL_HRTIM_BM_TRIG_NONE
<>	135:176b8275d35d	7461	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
<>	135:176b8275d35d	7462	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
<>	135:176b8275d35d	7463	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
<>	135:176b8275d35d	7464	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
<>	135:176b8275d35d	7465	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
<>	135:176b8275d35d	7466	* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
<>	135:176b8275d35d	7467	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
<>	135:176b8275d35d	7468	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
<>	135:176b8275d35d	7469	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
<>	135:176b8275d35d	7470	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
<>	135:176b8275d35d	7471	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
<>	135:176b8275d35d	7472	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
<>	135:176b8275d35d	7473	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
<>	135:176b8275d35d	7474	* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
<>	135:176b8275d35d	7475	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
<>	135:176b8275d35d	7476	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
<>	135:176b8275d35d	7477	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
<>	135:176b8275d35d	7478	* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
<>	135:176b8275d35d	7479	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
<>	135:176b8275d35d	7480	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
<>	135:176b8275d35d	7481	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
<>	135:176b8275d35d	7482	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
<>	135:176b8275d35d	7483	* @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
<>	135:176b8275d35d	7484	* @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
<>	135:176b8275d35d	7485	* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
<>	135:176b8275d35d	7486	* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
<>	135:176b8275d35d	7487	* @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
<>	135:176b8275d35d	7488	* @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
<>	135:176b8275d35d	7489	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
<>	135:176b8275d35d	7490	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
<>	135:176b8275d35d	7491	* @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
<>	135:176b8275d35d	7492	*/
<>	135:176b8275d35d	7493	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7494	{
<>	135:176b8275d35d	7495	return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
<>	135:176b8275d35d	7496	}
<>	135:176b8275d35d	7497
<>	135:176b8275d35d	7498	/**
<>	135:176b8275d35d	7499	* @brief Set the burst mode controller compare value.
<>	135:176b8275d35d	7500	* @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
<>	135:176b8275d35d	7501	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7502	* @param CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	7503	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	7504	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	7505	* @retval None
<>	135:176b8275d35d	7506	*/
<>	135:176b8275d35d	7507	__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
<>	135:176b8275d35d	7508	{
<>	135:176b8275d35d	7509	WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
<>	135:176b8275d35d	7510	}
<>	135:176b8275d35d	7511
<>	135:176b8275d35d	7512	/**
<>	135:176b8275d35d	7513	* @brief Get actual burst mode controller compare value.
<>	135:176b8275d35d	7514	* @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
<>	135:176b8275d35d	7515	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7516	* @retval CompareValue Compare value must be above or equal to 3
<>	135:176b8275d35d	7517	* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
<>	135:176b8275d35d	7518	* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	7519	*/
<>	135:176b8275d35d	7520	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7521	{
<>	135:176b8275d35d	7522	return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
<>	135:176b8275d35d	7523	}
<>	135:176b8275d35d	7524
<>	135:176b8275d35d	7525	/**
<>	135:176b8275d35d	7526	* @brief Set the burst mode controller period.
<>	135:176b8275d35d	7527	* @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
<>	135:176b8275d35d	7528	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7529	* @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
<>	135:176b8275d35d	7530	* that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	7531	* The maximum value is 0x0000 FFDF.
<>	135:176b8275d35d	7532	* @retval None
<>	135:176b8275d35d	7533	*/
<>	135:176b8275d35d	7534	__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
<>	135:176b8275d35d	7535	{
<>	135:176b8275d35d	7536	WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
<>	135:176b8275d35d	7537	}
<>	135:176b8275d35d	7538
<>	135:176b8275d35d	7539	/**
<>	135:176b8275d35d	7540	* @brief Get actual burst mode controller period.
<>	135:176b8275d35d	7541	* @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
<>	135:176b8275d35d	7542	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7543	* @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
<>	135:176b8275d35d	7544	* that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
<>	135:176b8275d35d	7545	* The maximum value is 0x0000 FFDF.
<>	135:176b8275d35d	7546	*/
<>	135:176b8275d35d	7547	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7548	{
<>	135:176b8275d35d	7549	return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
<>	135:176b8275d35d	7550	}
<>	135:176b8275d35d	7551
<>	135:176b8275d35d	7552	/**
<>	135:176b8275d35d	7553	* @brief Enable the burst mode controller
<>	135:176b8275d35d	7554	* @rmtoll BMCR BME LL_HRTIM_BM_Enable
<>	135:176b8275d35d	7555	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7556	* @retval None
<>	135:176b8275d35d	7557	*/
<>	135:176b8275d35d	7558	__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7559	{
<>	135:176b8275d35d	7560	SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
<>	135:176b8275d35d	7561	}
<>	135:176b8275d35d	7562
<>	135:176b8275d35d	7563	/**
<>	135:176b8275d35d	7564	* @brief Disable the burst mode controller
<>	135:176b8275d35d	7565	* @rmtoll BMCR BME LL_HRTIM_BM_Disable
<>	135:176b8275d35d	7566	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7567	* @retval None
<>	135:176b8275d35d	7568	*/
<>	135:176b8275d35d	7569	__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7570	{
<>	135:176b8275d35d	7571	CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
<>	135:176b8275d35d	7572	}
<>	135:176b8275d35d	7573
<>	135:176b8275d35d	7574	/**
<>	135:176b8275d35d	7575	* @brief Indicate whether the burst mode controller is enabled.
<>	135:176b8275d35d	7576	* @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
<>	135:176b8275d35d	7577	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7578	* @retval State of BME bit in HRTIM_BMCR register (1 or 0).
<>	135:176b8275d35d	7579	*/
<>	135:176b8275d35d	7580	__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7581	{
<>	135:176b8275d35d	7582	return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == HRTIM_BMCR_BME);
<>	135:176b8275d35d	7583	}
<>	135:176b8275d35d	7584
<>	135:176b8275d35d	7585	/**
<>	135:176b8275d35d	7586	* @brief Trigger the burst operation (software trigger)
<>	135:176b8275d35d	7587	* @rmtoll BMTRGR SW LL_HRTIM_BM_Start
<>	135:176b8275d35d	7588	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7589	* @retval None
<>	135:176b8275d35d	7590	*/
<>	135:176b8275d35d	7591	__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7592	{
<>	135:176b8275d35d	7593	SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
<>	135:176b8275d35d	7594	}
<>	135:176b8275d35d	7595
<>	135:176b8275d35d	7596	/**
<>	135:176b8275d35d	7597	* @brief Stop the burst mode operation.
<>	135:176b8275d35d	7598	* @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
<>	135:176b8275d35d	7599	* @note Causes a burst mode early termination.
<>	135:176b8275d35d	7600	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7601	* @retval None
<>	135:176b8275d35d	7602	*/
<>	135:176b8275d35d	7603	__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7604	{
<>	135:176b8275d35d	7605	CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
<>	135:176b8275d35d	7606	}
<>	135:176b8275d35d	7607
<>	135:176b8275d35d	7608	/**
<>	135:176b8275d35d	7609	* @brief Get actual burst mode status
<>	135:176b8275d35d	7610	* @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
<>	135:176b8275d35d	7611	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7612	* @retval Status This parameter can be one of the following values:
<>	135:176b8275d35d	7613	* @arg @ref LL_HRTIM_BM_STATUS_NORMAL
<>	135:176b8275d35d	7614	* @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
<>	135:176b8275d35d	7615	*/
<>	135:176b8275d35d	7616	__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7617	{
<>	135:176b8275d35d	7618	return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
<>	135:176b8275d35d	7619	}
<>	135:176b8275d35d	7620
<>	135:176b8275d35d	7621	/**
<>	135:176b8275d35d	7622	* @}
<>	135:176b8275d35d	7623	*/
<>	135:176b8275d35d	7624
<>	135:176b8275d35d	7625	/** @defgroup HRTIM_EF_FLAG_Management FLAG_Management
<>	135:176b8275d35d	7626	* @{
<>	135:176b8275d35d	7627	*/
<>	135:176b8275d35d	7628
<>	135:176b8275d35d	7629	/**
<>	135:176b8275d35d	7630	* @brief Clear the Fault 1 interrupt flag.
<>	135:176b8275d35d	7631	* @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
<>	135:176b8275d35d	7632	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7633	* @retval None
<>	135:176b8275d35d	7634	*/
<>	135:176b8275d35d	7635	__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7636	{
<>	135:176b8275d35d	7637	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
<>	135:176b8275d35d	7638	}
<>	135:176b8275d35d	7639
<>	135:176b8275d35d	7640	/**
<>	135:176b8275d35d	7641	* @brief Indicate whether Fault 1 interrupt occurred.
<>	135:176b8275d35d	7642	* @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
<>	135:176b8275d35d	7643	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7644	* @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7645	*/
<>	135:176b8275d35d	7646	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7647	{
<>	135:176b8275d35d	7648	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1));
<>	135:176b8275d35d	7649	}
<>	135:176b8275d35d	7650
<>	135:176b8275d35d	7651	/**
<>	135:176b8275d35d	7652	* @brief Clear the Fault 2 interrupt flag.
<>	135:176b8275d35d	7653	* @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
<>	135:176b8275d35d	7654	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7655	* @retval None
<>	135:176b8275d35d	7656	*/
<>	135:176b8275d35d	7657	__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7658	{
<>	135:176b8275d35d	7659	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
<>	135:176b8275d35d	7660	}
<>	135:176b8275d35d	7661
<>	135:176b8275d35d	7662	/**
<>	135:176b8275d35d	7663	* @brief Indicate whether Fault 2 interrupt occurred.
<>	135:176b8275d35d	7664	* @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
<>	135:176b8275d35d	7665	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7666	* @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7667	*/
<>	135:176b8275d35d	7668	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7669	{
<>	135:176b8275d35d	7670	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2));
<>	135:176b8275d35d	7671	}
<>	135:176b8275d35d	7672
<>	135:176b8275d35d	7673	/**
<>	135:176b8275d35d	7674	* @brief Clear the Fault 3 interrupt flag.
<>	135:176b8275d35d	7675	* @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
<>	135:176b8275d35d	7676	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7677	* @retval None
<>	135:176b8275d35d	7678	*/
<>	135:176b8275d35d	7679	__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7680	{
<>	135:176b8275d35d	7681	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
<>	135:176b8275d35d	7682	}
<>	135:176b8275d35d	7683
<>	135:176b8275d35d	7684	/**
<>	135:176b8275d35d	7685	* @brief Indicate whether Fault 3 interrupt occurred.
<>	135:176b8275d35d	7686	* @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
<>	135:176b8275d35d	7687	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7688	* @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7689	*/
<>	135:176b8275d35d	7690	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7691	{
<>	135:176b8275d35d	7692	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3));
<>	135:176b8275d35d	7693	}
<>	135:176b8275d35d	7694
<>	135:176b8275d35d	7695	/**
<>	135:176b8275d35d	7696	* @brief Clear the Fault 4 interrupt flag.
<>	135:176b8275d35d	7697	* @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
<>	135:176b8275d35d	7698	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7699	* @retval None
<>	135:176b8275d35d	7700	*/
<>	135:176b8275d35d	7701	__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7702	{
<>	135:176b8275d35d	7703	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
<>	135:176b8275d35d	7704	}
<>	135:176b8275d35d	7705
<>	135:176b8275d35d	7706	/**
<>	135:176b8275d35d	7707	* @brief Indicate whether Fault 4 interrupt occurred.
<>	135:176b8275d35d	7708	* @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
<>	135:176b8275d35d	7709	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7710	* @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7711	*/
<>	135:176b8275d35d	7712	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7713	{
<>	135:176b8275d35d	7714	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4));
<>	135:176b8275d35d	7715	}
<>	135:176b8275d35d	7716
<>	135:176b8275d35d	7717	/**
<>	135:176b8275d35d	7718	* @brief Clear the Fault 5 interrupt flag.
<>	135:176b8275d35d	7719	* @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
<>	135:176b8275d35d	7720	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7721	* @retval None
<>	135:176b8275d35d	7722	*/
<>	135:176b8275d35d	7723	__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7724	{
<>	135:176b8275d35d	7725	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
<>	135:176b8275d35d	7726	}
<>	135:176b8275d35d	7727
<>	135:176b8275d35d	7728	/**
<>	135:176b8275d35d	7729	* @brief Indicate whether Fault 5 interrupt occurred.
<>	135:176b8275d35d	7730	* @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
<>	135:176b8275d35d	7731	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7732	* @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7733	*/
<>	135:176b8275d35d	7734	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7735	{
<>	135:176b8275d35d	7736	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5));
<>	135:176b8275d35d	7737	}
<>	135:176b8275d35d	7738
<>	135:176b8275d35d	7739	/**
<>	135:176b8275d35d	7740	* @brief Clear the System Fault interrupt flag.
<>	135:176b8275d35d	7741	* @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
<>	135:176b8275d35d	7742	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7743	* @retval None
<>	135:176b8275d35d	7744	*/
<>	135:176b8275d35d	7745	__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7746	{
<>	135:176b8275d35d	7747	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
<>	135:176b8275d35d	7748	}
<>	135:176b8275d35d	7749
<>	135:176b8275d35d	7750	/**
<>	135:176b8275d35d	7751	* @brief Indicate whether System Fault interrupt occurred.
<>	135:176b8275d35d	7752	* @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
<>	135:176b8275d35d	7753	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7754	* @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7755	*/
<>	135:176b8275d35d	7756	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7757	{
<>	135:176b8275d35d	7758	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT));
<>	135:176b8275d35d	7759	}
<>	135:176b8275d35d	7760
<>	135:176b8275d35d	7761	/**
<>	135:176b8275d35d	7762	* @brief Clear the DLL ready interrupt flag.
<>	135:176b8275d35d	7763	* @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
<>	135:176b8275d35d	7764	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7765	* @retval None
<>	135:176b8275d35d	7766	*/
<>	135:176b8275d35d	7767	__STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7768	{
<>	135:176b8275d35d	7769	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
<>	135:176b8275d35d	7770	}
<>	135:176b8275d35d	7771
<>	135:176b8275d35d	7772	/**
<>	135:176b8275d35d	7773	* @brief Indicate whether DLL ready interrupt occurred.
<>	135:176b8275d35d	7774	* @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
<>	135:176b8275d35d	7775	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7776	* @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7777	*/
<>	135:176b8275d35d	7778	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7779	{
<>	135:176b8275d35d	7780	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY));
<>	135:176b8275d35d	7781	}
<>	135:176b8275d35d	7782
<>	135:176b8275d35d	7783	/**
<>	135:176b8275d35d	7784	* @brief Clear the Burst Mode period interrupt flag.
<>	135:176b8275d35d	7785	* @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
<>	135:176b8275d35d	7786	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7787	* @retval None
<>	135:176b8275d35d	7788	*/
<>	135:176b8275d35d	7789	__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7790	{
<>	135:176b8275d35d	7791	SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
<>	135:176b8275d35d	7792	}
<>	135:176b8275d35d	7793
<>	135:176b8275d35d	7794	/**
<>	135:176b8275d35d	7795	* @brief Indicate whether Burst Mode period interrupt occurred.
<>	135:176b8275d35d	7796	* @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
<>	135:176b8275d35d	7797	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7798	* @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
<>	135:176b8275d35d	7799	*/
<>	135:176b8275d35d	7800	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7801	{
<>	135:176b8275d35d	7802	return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER));
<>	135:176b8275d35d	7803	}
<>	135:176b8275d35d	7804
<>	135:176b8275d35d	7805	/**
<>	135:176b8275d35d	7806	* @brief Clear the Synchronization Input interrupt flag.
<>	135:176b8275d35d	7807	* @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
<>	135:176b8275d35d	7808	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7809	* @retval None
<>	135:176b8275d35d	7810	*/
<>	135:176b8275d35d	7811	__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7812	{
<>	135:176b8275d35d	7813	SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
<>	135:176b8275d35d	7814	}
<>	135:176b8275d35d	7815
<>	135:176b8275d35d	7816	/**
<>	135:176b8275d35d	7817	* @brief Indicate whether the Synchronization Input interrupt occurred.
<>	135:176b8275d35d	7818	* @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
<>	135:176b8275d35d	7819	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7820	* @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
<>	135:176b8275d35d	7821	*/
<>	135:176b8275d35d	7822	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	7823	{
<>	135:176b8275d35d	7824	return (READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC));
<>	135:176b8275d35d	7825	}
<>	135:176b8275d35d	7826
<>	135:176b8275d35d	7827	/**
<>	135:176b8275d35d	7828	* @brief Clear the update interrupt flag for a given timer (including the master timer) .
<>	135:176b8275d35d	7829	* @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
<>	135:176b8275d35d	7830	* TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
<>	135:176b8275d35d	7831	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7832	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7833	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7834	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7835	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7836	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7837	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7838	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7839	* @retval None
<>	135:176b8275d35d	7840	*/
<>	135:176b8275d35d	7841	__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7842	{
<>	135:176b8275d35d	7843	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7844	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	7845	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7846	SET_BIT(*pReg, HRTIM_MICR_MUPD);
<>	135:176b8275d35d	7847	}
<>	135:176b8275d35d	7848
<>	135:176b8275d35d	7849	/**
<>	135:176b8275d35d	7850	* @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	7851	* @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
<>	135:176b8275d35d	7852	* TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
<>	135:176b8275d35d	7853	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7854	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7855	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7856	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7857	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7858	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7859	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7860	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7861	* @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	7862	*/
<>	135:176b8275d35d	7863	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7864	{
<>	135:176b8275d35d	7865	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7866	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	7867	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7868	return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD));
<>	135:176b8275d35d	7869	}
<>	135:176b8275d35d	7870
<>	135:176b8275d35d	7871	/**
<>	135:176b8275d35d	7872	* @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
<>	135:176b8275d35d	7873	* @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
<>	135:176b8275d35d	7874	* TIMxICR REPC LL_HRTIM_ClearFlag_REP
<>	135:176b8275d35d	7875	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7876	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7877	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7878	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7879	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7880	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7881	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7882	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7883	* @retval None
<>	135:176b8275d35d	7884	*/
<>	135:176b8275d35d	7885	__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7886	{
<>	135:176b8275d35d	7887	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7888	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	7889	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7890	SET_BIT(*pReg, HRTIM_MICR_MREP);
<>	135:176b8275d35d	7891
<>	135:176b8275d35d	7892	}
<>	135:176b8275d35d	7893
<>	135:176b8275d35d	7894	/**
<>	135:176b8275d35d	7895	* @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	7896	* @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
<>	135:176b8275d35d	7897	* TIMxISR REP LL_HRTIM_IsActiveFlag_REP
<>	135:176b8275d35d	7898	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7899	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7900	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7901	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7902	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7903	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7904	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7905	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7906	* @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	7907	*/
<>	135:176b8275d35d	7908	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7909	{
<>	135:176b8275d35d	7910	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7911	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	7912	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7913	return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP));
<>	135:176b8275d35d	7914	}
<>	135:176b8275d35d	7915
<>	135:176b8275d35d	7916	/**
<>	135:176b8275d35d	7917	* @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
<>	135:176b8275d35d	7918	* @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
<>	135:176b8275d35d	7919	* TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
<>	135:176b8275d35d	7920	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7921	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7922	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7923	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7924	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7925	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7926	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7927	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7928	* @retval None
<>	135:176b8275d35d	7929	*/
<>	135:176b8275d35d	7930	__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7931	{
<>	135:176b8275d35d	7932	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7933	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	7934	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7935	SET_BIT(*pReg, HRTIM_MICR_MCMP1);
<>	135:176b8275d35d	7936	}
<>	135:176b8275d35d	7937
<>	135:176b8275d35d	7938	/**
<>	135:176b8275d35d	7939	* @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	7940	* @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
<>	135:176b8275d35d	7941	* TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
<>	135:176b8275d35d	7942	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7943	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7944	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7945	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7946	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7947	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7948	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7949	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7950	* @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	7951	*/
<>	135:176b8275d35d	7952	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7953	{
<>	135:176b8275d35d	7954	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7955	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	7956	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7957	return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1));
<>	135:176b8275d35d	7958	}
<>	135:176b8275d35d	7959
<>	135:176b8275d35d	7960	/**
<>	135:176b8275d35d	7961	* @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
<>	135:176b8275d35d	7962	* @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
<>	135:176b8275d35d	7963	* TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
<>	135:176b8275d35d	7964	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7965	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7966	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7967	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7968	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7969	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7970	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7971	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7972	* @retval None
<>	135:176b8275d35d	7973	*/
<>	135:176b8275d35d	7974	__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7975	{
<>	135:176b8275d35d	7976	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7977	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	7978	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	7979	SET_BIT(*pReg, HRTIM_MICR_MCMP2);
<>	135:176b8275d35d	7980	}
<>	135:176b8275d35d	7981
<>	135:176b8275d35d	7982	/**
<>	135:176b8275d35d	7983	* @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	7984	* @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
<>	135:176b8275d35d	7985	* TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
<>	135:176b8275d35d	7986	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	7987	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	7988	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	7989	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	7990	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	7991	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	7992	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	7993	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	7994	* @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	7995	*/
<>	135:176b8275d35d	7996	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	7997	{
<>	135:176b8275d35d	7998	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	7999	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8000	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8001	return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2));
<>	135:176b8275d35d	8002	}
<>	135:176b8275d35d	8003
<>	135:176b8275d35d	8004	/**
<>	135:176b8275d35d	8005	* @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
<>	135:176b8275d35d	8006	* @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
<>	135:176b8275d35d	8007	* TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
<>	135:176b8275d35d	8008	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8009	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8010	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8011	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8012	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8013	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8014	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8015	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8016	* @retval None
<>	135:176b8275d35d	8017	*/
<>	135:176b8275d35d	8018	__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8019	{
<>	135:176b8275d35d	8020	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8021	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8022	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8023	SET_BIT(*pReg, HRTIM_MICR_MCMP3);
<>	135:176b8275d35d	8024	}
<>	135:176b8275d35d	8025
<>	135:176b8275d35d	8026	/**
<>	135:176b8275d35d	8027	* @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	8028	* @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
<>	135:176b8275d35d	8029	* TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
<>	135:176b8275d35d	8030	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8031	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8032	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8033	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8034	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8035	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8036	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8037	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8038	* @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8039	*/
<>	135:176b8275d35d	8040	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8041	{
<>	135:176b8275d35d	8042	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8043	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8044	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8045	return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3));
<>	135:176b8275d35d	8046	}
<>	135:176b8275d35d	8047
<>	135:176b8275d35d	8048	/**
<>	135:176b8275d35d	8049	* @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
<>	135:176b8275d35d	8050	* @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
<>	135:176b8275d35d	8051	* TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
<>	135:176b8275d35d	8052	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8053	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8054	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8055	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8056	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8057	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8058	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8059	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8060	* @retval None
<>	135:176b8275d35d	8061	*/
<>	135:176b8275d35d	8062	__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8063	{
<>	135:176b8275d35d	8064	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8065	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8066	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8067	SET_BIT(*pReg, HRTIM_MICR_MCMP4);
<>	135:176b8275d35d	8068	}
<>	135:176b8275d35d	8069
<>	135:176b8275d35d	8070	/**
<>	135:176b8275d35d	8071	* @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
<>	135:176b8275d35d	8072	* @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
<>	135:176b8275d35d	8073	* TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
<>	135:176b8275d35d	8074	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8075	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8076	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8077	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8078	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8079	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8080	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8081	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8082	* @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8083	*/
<>	135:176b8275d35d	8084	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8085	{
<>	135:176b8275d35d	8086	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8087	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8088	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8089	return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4));
<>	135:176b8275d35d	8090	}
<>	135:176b8275d35d	8091
<>	135:176b8275d35d	8092	/**
<>	135:176b8275d35d	8093	* @brief Clear the capture 1 interrupt flag for a given timer.
<>	135:176b8275d35d	8094	* @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
<>	135:176b8275d35d	8095	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8096	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8097	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8098	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8099	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8100	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8101	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8102	* @retval None
<>	135:176b8275d35d	8103	*/
<>	135:176b8275d35d	8104	__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8105	{
<>	135:176b8275d35d	8106	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8107	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8108	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8109	SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
<>	135:176b8275d35d	8110	}
<>	135:176b8275d35d	8111
<>	135:176b8275d35d	8112	/**
<>	135:176b8275d35d	8113	* @brief Indicate whether the capture 1 interrupt occurred for a given timer.
<>	135:176b8275d35d	8114	* @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
<>	135:176b8275d35d	8115	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8116	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8117	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8118	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8119	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8120	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8121	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8122	* @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8123	*/
<>	135:176b8275d35d	8124	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8125	{
<>	135:176b8275d35d	8126	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8127	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8128	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8129	return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1));
<>	135:176b8275d35d	8130	}
<>	135:176b8275d35d	8131
<>	135:176b8275d35d	8132	/**
<>	135:176b8275d35d	8133	* @brief Clear the capture 2 interrupt flag for a given timer.
<>	135:176b8275d35d	8134	* @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
<>	135:176b8275d35d	8135	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8136	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8137	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8138	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8139	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8140	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8141	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8142	* @retval None
<>	135:176b8275d35d	8143	*/
<>	135:176b8275d35d	8144	__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8145	{
<>	135:176b8275d35d	8146	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8147	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8148	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8149	SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
<>	135:176b8275d35d	8150	}
<>	135:176b8275d35d	8151
<>	135:176b8275d35d	8152	/**
<>	135:176b8275d35d	8153	* @brief Indicate whether the capture 2 interrupt occurred for a given timer.
<>	135:176b8275d35d	8154	* @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
<>	135:176b8275d35d	8155	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8156	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8157	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8158	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8159	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8160	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8161	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8162	* @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8163	*/
<>	135:176b8275d35d	8164	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8165	{
<>	135:176b8275d35d	8166	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8167	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8168	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8169	return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2));
<>	135:176b8275d35d	8170	}
<>	135:176b8275d35d	8171
<>	135:176b8275d35d	8172	/**
<>	135:176b8275d35d	8173	* @brief Clear the output 1 set interrupt flag for a given timer.
<>	135:176b8275d35d	8174	* @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
<>	135:176b8275d35d	8175	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8176	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8177	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8178	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8179	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8180	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8181	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8182	* @retval None
<>	135:176b8275d35d	8183	*/
<>	135:176b8275d35d	8184	__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8185	{
<>	135:176b8275d35d	8186	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8187	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8188	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8189	SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
<>	135:176b8275d35d	8190	}
<>	135:176b8275d35d	8191
<>	135:176b8275d35d	8192	/**
<>	135:176b8275d35d	8193	* @brief Indicate whether the output 1 set interrupt occurred for a given timer.
<>	135:176b8275d35d	8194	* @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
<>	135:176b8275d35d	8195	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8196	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8197	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8198	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8199	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8200	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8201	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8202	* @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8203	*/
<>	135:176b8275d35d	8204	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8205	{
<>	135:176b8275d35d	8206	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8207	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8208	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8209	return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1));
<>	135:176b8275d35d	8210	}
<>	135:176b8275d35d	8211
<>	135:176b8275d35d	8212	/**
<>	135:176b8275d35d	8213	* @brief Clear the output 1 reset interrupt flag for a given timer.
<>	135:176b8275d35d	8214	* @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
<>	135:176b8275d35d	8215	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8216	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8217	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8218	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8219	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8220	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8221	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8222	* @retval None
<>	135:176b8275d35d	8223	*/
<>	135:176b8275d35d	8224	__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8225	{
<>	135:176b8275d35d	8226	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8227	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8228	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8229	SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
<>	135:176b8275d35d	8230	}
<>	135:176b8275d35d	8231
<>	135:176b8275d35d	8232	/**
<>	135:176b8275d35d	8233	* @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
<>	135:176b8275d35d	8234	* @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
<>	135:176b8275d35d	8235	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8236	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8237	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8238	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8239	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8240	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8241	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8242	* @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8243	*/
<>	135:176b8275d35d	8244	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8245	{
<>	135:176b8275d35d	8246	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8247	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8248	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8249	return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1));
<>	135:176b8275d35d	8250	}
<>	135:176b8275d35d	8251
<>	135:176b8275d35d	8252	/**
<>	135:176b8275d35d	8253	* @brief Clear the output 2 set interrupt flag for a given timer.
<>	135:176b8275d35d	8254	* @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
<>	135:176b8275d35d	8255	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8256	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8257	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8258	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8259	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8260	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8261	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8262	* @retval None
<>	135:176b8275d35d	8263	*/
<>	135:176b8275d35d	8264	__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8265	{
<>	135:176b8275d35d	8266	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8267	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8268	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8269	SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
<>	135:176b8275d35d	8270	}
<>	135:176b8275d35d	8271
<>	135:176b8275d35d	8272	/**
<>	135:176b8275d35d	8273	* @brief Indicate whether the output 2 set interrupt occurred for a given timer.
<>	135:176b8275d35d	8274	* @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
<>	135:176b8275d35d	8275	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8276	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8277	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8278	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8279	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8280	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8281	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8282	* @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8283	*/
<>	135:176b8275d35d	8284	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8285	{
<>	135:176b8275d35d	8286	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8287	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8288	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8289	return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2));
<>	135:176b8275d35d	8290	}
<>	135:176b8275d35d	8291
<>	135:176b8275d35d	8292	/**
<>	135:176b8275d35d	8293	* @brief Clear the output 2reset interrupt flag for a given timer.
<>	135:176b8275d35d	8294	* @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
<>	135:176b8275d35d	8295	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8296	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8297	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8298	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8299	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8300	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8301	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8302	* @retval None
<>	135:176b8275d35d	8303	*/
<>	135:176b8275d35d	8304	__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8305	{
<>	135:176b8275d35d	8306	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8307	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8308	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8309	SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
<>	135:176b8275d35d	8310	}
<>	135:176b8275d35d	8311
<>	135:176b8275d35d	8312	/**
<>	135:176b8275d35d	8313	* @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
<>	135:176b8275d35d	8314	* @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
<>	135:176b8275d35d	8315	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8316	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8317	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8318	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8319	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8320	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8321	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8322	* @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8323	*/
<>	135:176b8275d35d	8324	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8325	{
<>	135:176b8275d35d	8326	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8327	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8328	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8329	return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2));
<>	135:176b8275d35d	8330	}
<>	135:176b8275d35d	8331
<>	135:176b8275d35d	8332	/**
<>	135:176b8275d35d	8333	* @brief Clear the reset and/or roll-over interrupt flag for a given timer.
<>	135:176b8275d35d	8334	* @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
<>	135:176b8275d35d	8335	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8336	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8337	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8338	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8339	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8340	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8341	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8342	* @retval None
<>	135:176b8275d35d	8343	*/
<>	135:176b8275d35d	8344	__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8345	{
<>	135:176b8275d35d	8346	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8347	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8348	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8349	SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
<>	135:176b8275d35d	8350	}
<>	135:176b8275d35d	8351
<>	135:176b8275d35d	8352	/**
<>	135:176b8275d35d	8353	* @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
<>	135:176b8275d35d	8354	* @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
<>	135:176b8275d35d	8355	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8356	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8357	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8358	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8359	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8360	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8361	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8362	* @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8363	*/
<>	135:176b8275d35d	8364	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8365	{
<>	135:176b8275d35d	8366	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8367	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8368	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8369	return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST));
<>	135:176b8275d35d	8370	}
<>	135:176b8275d35d	8371
<>	135:176b8275d35d	8372	/**
<>	135:176b8275d35d	8373	* @brief Clear the delayed protection interrupt flag for a given timer.
<>	135:176b8275d35d	8374	* @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
<>	135:176b8275d35d	8375	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8376	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8377	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8378	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8379	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8380	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8381	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8382	* @retval None
<>	135:176b8275d35d	8383	*/
<>	135:176b8275d35d	8384	__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8385	{
<>	135:176b8275d35d	8386	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8387	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
<>	135:176b8275d35d	8388	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8389	SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C);
<>	135:176b8275d35d	8390	}
<>	135:176b8275d35d	8391
<>	135:176b8275d35d	8392	/**
<>	135:176b8275d35d	8393	* @brief Indicate whether the delayed protection interrupt occurred for a given timer.
<>	135:176b8275d35d	8394	* @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
<>	135:176b8275d35d	8395	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8396	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8397	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8398	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8399	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8400	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8401	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8402	* @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
<>	135:176b8275d35d	8403	*/
<>	135:176b8275d35d	8404	__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8405	{
<>	135:176b8275d35d	8406	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8407	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
<>	135:176b8275d35d	8408	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8409	return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT));
<>	135:176b8275d35d	8410	}
<>	135:176b8275d35d	8411
<>	135:176b8275d35d	8412	/**
<>	135:176b8275d35d	8413	* @}
<>	135:176b8275d35d	8414	*/
<>	135:176b8275d35d	8415
<>	135:176b8275d35d	8416	/** @defgroup HRTIM_EF_IT_Management IT_Management
<>	135:176b8275d35d	8417	* @{
<>	135:176b8275d35d	8418	*/
<>	135:176b8275d35d	8419
<>	135:176b8275d35d	8420	/**
<>	135:176b8275d35d	8421	* @brief Enable the fault 1 interrupt.
<>	135:176b8275d35d	8422	* @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
<>	135:176b8275d35d	8423	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8424	* @retval None
<>	135:176b8275d35d	8425	*/
<>	135:176b8275d35d	8426	__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8427	{
<>	135:176b8275d35d	8428	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
<>	135:176b8275d35d	8429	}
<>	135:176b8275d35d	8430
<>	135:176b8275d35d	8431	/**
<>	135:176b8275d35d	8432	* @brief Disable the fault 1 interrupt.
<>	135:176b8275d35d	8433	* @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
<>	135:176b8275d35d	8434	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8435	* @retval None
<>	135:176b8275d35d	8436	*/
<>	135:176b8275d35d	8437	__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8438	{
<>	135:176b8275d35d	8439	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
<>	135:176b8275d35d	8440	}
<>	135:176b8275d35d	8441
<>	135:176b8275d35d	8442	/**
<>	135:176b8275d35d	8443	* @brief Indicate whether the fault 1 interrupt is enabled.
<>	135:176b8275d35d	8444	* @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
<>	135:176b8275d35d	8445	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8446	* @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8447	*/
<>	135:176b8275d35d	8448	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8449	{
<>	135:176b8275d35d	8450	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1));
<>	135:176b8275d35d	8451	}
<>	135:176b8275d35d	8452
<>	135:176b8275d35d	8453	/**
<>	135:176b8275d35d	8454	* @brief Enable the fault 2 interrupt.
<>	135:176b8275d35d	8455	* @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
<>	135:176b8275d35d	8456	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8457	* @retval None
<>	135:176b8275d35d	8458	*/
<>	135:176b8275d35d	8459	__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8460	{
<>	135:176b8275d35d	8461	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
<>	135:176b8275d35d	8462	}
<>	135:176b8275d35d	8463
<>	135:176b8275d35d	8464	/**
<>	135:176b8275d35d	8465	* @brief Disable the fault 2 interrupt.
<>	135:176b8275d35d	8466	* @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
<>	135:176b8275d35d	8467	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8468	* @retval None
<>	135:176b8275d35d	8469	*/
<>	135:176b8275d35d	8470	__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8471	{
<>	135:176b8275d35d	8472	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
<>	135:176b8275d35d	8473	}
<>	135:176b8275d35d	8474
<>	135:176b8275d35d	8475	/**
<>	135:176b8275d35d	8476	* @brief Indicate whether the fault 2 interrupt is enabled.
<>	135:176b8275d35d	8477	* @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
<>	135:176b8275d35d	8478	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8479	* @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8480	*/
<>	135:176b8275d35d	8481	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8482	{
<>	135:176b8275d35d	8483	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2));
<>	135:176b8275d35d	8484	}
<>	135:176b8275d35d	8485
<>	135:176b8275d35d	8486	/**
<>	135:176b8275d35d	8487	* @brief Enable the fault 3 interrupt.
<>	135:176b8275d35d	8488	* @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
<>	135:176b8275d35d	8489	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8490	* @retval None
<>	135:176b8275d35d	8491	*/
<>	135:176b8275d35d	8492	__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8493	{
<>	135:176b8275d35d	8494	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
<>	135:176b8275d35d	8495	}
<>	135:176b8275d35d	8496
<>	135:176b8275d35d	8497	/**
<>	135:176b8275d35d	8498	* @brief Disable the fault 3 interrupt.
<>	135:176b8275d35d	8499	* @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
<>	135:176b8275d35d	8500	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8501	* @retval None
<>	135:176b8275d35d	8502	*/
<>	135:176b8275d35d	8503	__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8504	{
<>	135:176b8275d35d	8505	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
<>	135:176b8275d35d	8506	}
<>	135:176b8275d35d	8507
<>	135:176b8275d35d	8508	/**
<>	135:176b8275d35d	8509	* @brief Indicate whether the fault 3 interrupt is enabled.
<>	135:176b8275d35d	8510	* @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
<>	135:176b8275d35d	8511	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8512	* @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8513	*/
<>	135:176b8275d35d	8514	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8515	{
<>	135:176b8275d35d	8516	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3));
<>	135:176b8275d35d	8517	}
<>	135:176b8275d35d	8518
<>	135:176b8275d35d	8519	/**
<>	135:176b8275d35d	8520	* @brief Enable the fault 4 interrupt.
<>	135:176b8275d35d	8521	* @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
<>	135:176b8275d35d	8522	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8523	* @retval None
<>	135:176b8275d35d	8524	*/
<>	135:176b8275d35d	8525	__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8526	{
<>	135:176b8275d35d	8527	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
<>	135:176b8275d35d	8528	}
<>	135:176b8275d35d	8529
<>	135:176b8275d35d	8530	/**
<>	135:176b8275d35d	8531	* @brief Disable the fault 4 interrupt.
<>	135:176b8275d35d	8532	* @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
<>	135:176b8275d35d	8533	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8534	* @retval None
<>	135:176b8275d35d	8535	*/
<>	135:176b8275d35d	8536	__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8537	{
<>	135:176b8275d35d	8538	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
<>	135:176b8275d35d	8539	}
<>	135:176b8275d35d	8540
<>	135:176b8275d35d	8541	/**
<>	135:176b8275d35d	8542	* @brief Indicate whether the fault 4 interrupt is enabled.
<>	135:176b8275d35d	8543	* @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
<>	135:176b8275d35d	8544	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8545	* @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8546	*/
<>	135:176b8275d35d	8547	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8548	{
<>	135:176b8275d35d	8549	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4));
<>	135:176b8275d35d	8550	}
<>	135:176b8275d35d	8551
<>	135:176b8275d35d	8552	/**
<>	135:176b8275d35d	8553	* @brief Enable the fault 5 interrupt.
<>	135:176b8275d35d	8554	* @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
<>	135:176b8275d35d	8555	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8556	* @retval None
<>	135:176b8275d35d	8557	*/
<>	135:176b8275d35d	8558	__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8559	{
<>	135:176b8275d35d	8560	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
<>	135:176b8275d35d	8561	}
<>	135:176b8275d35d	8562
<>	135:176b8275d35d	8563	/**
<>	135:176b8275d35d	8564	* @brief Disable the fault 5 interrupt.
<>	135:176b8275d35d	8565	* @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
<>	135:176b8275d35d	8566	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8567	* @retval None
<>	135:176b8275d35d	8568	*/
<>	135:176b8275d35d	8569	__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8570	{
<>	135:176b8275d35d	8571	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
<>	135:176b8275d35d	8572	}
<>	135:176b8275d35d	8573
<>	135:176b8275d35d	8574	/**
<>	135:176b8275d35d	8575	* @brief Indicate whether the fault 5 interrupt is enabled.
<>	135:176b8275d35d	8576	* @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
<>	135:176b8275d35d	8577	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8578	* @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8579	*/
<>	135:176b8275d35d	8580	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8581	{
<>	135:176b8275d35d	8582	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5));
<>	135:176b8275d35d	8583	}
<>	135:176b8275d35d	8584
<>	135:176b8275d35d	8585	/**
<>	135:176b8275d35d	8586	* @brief Enable the system fault interrupt.
<>	135:176b8275d35d	8587	* @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
<>	135:176b8275d35d	8588	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8589	* @retval None
<>	135:176b8275d35d	8590	*/
<>	135:176b8275d35d	8591	__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8592	{
<>	135:176b8275d35d	8593	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
<>	135:176b8275d35d	8594	}
<>	135:176b8275d35d	8595
<>	135:176b8275d35d	8596	/**
<>	135:176b8275d35d	8597	* @brief Disable the system fault interrupt.
<>	135:176b8275d35d	8598	* @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
<>	135:176b8275d35d	8599	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8600	* @retval None
<>	135:176b8275d35d	8601	*/
<>	135:176b8275d35d	8602	__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8603	{
<>	135:176b8275d35d	8604	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
<>	135:176b8275d35d	8605	}
<>	135:176b8275d35d	8606
<>	135:176b8275d35d	8607	/**
<>	135:176b8275d35d	8608	* @brief Indicate whether the system fault interrupt is enabled.
<>	135:176b8275d35d	8609	* @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
<>	135:176b8275d35d	8610	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8611	* @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8612	*/
<>	135:176b8275d35d	8613	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8614	{
<>	135:176b8275d35d	8615	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT));
<>	135:176b8275d35d	8616	}
<>	135:176b8275d35d	8617
<>	135:176b8275d35d	8618	/**
<>	135:176b8275d35d	8619	* @brief Enable the DLL ready interrupt.
<>	135:176b8275d35d	8620	* @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
<>	135:176b8275d35d	8621	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8622	* @retval None
<>	135:176b8275d35d	8623	*/
<>	135:176b8275d35d	8624	__STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8625	{
<>	135:176b8275d35d	8626	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
<>	135:176b8275d35d	8627	}
<>	135:176b8275d35d	8628
<>	135:176b8275d35d	8629	/**
<>	135:176b8275d35d	8630	* @brief Disable the DLL ready interrupt.
<>	135:176b8275d35d	8631	* @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
<>	135:176b8275d35d	8632	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8633	* @retval None
<>	135:176b8275d35d	8634	*/
<>	135:176b8275d35d	8635	__STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8636	{
<>	135:176b8275d35d	8637	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
<>	135:176b8275d35d	8638	}
<>	135:176b8275d35d	8639
<>	135:176b8275d35d	8640	/**
<>	135:176b8275d35d	8641	* @brief Indicate whether the DLL ready interrupt is enabled.
<>	135:176b8275d35d	8642	* @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
<>	135:176b8275d35d	8643	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8644	* @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8645	*/
<>	135:176b8275d35d	8646	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8647	{
<>	135:176b8275d35d	8648	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY));
<>	135:176b8275d35d	8649	}
<>	135:176b8275d35d	8650
<>	135:176b8275d35d	8651	/**
<>	135:176b8275d35d	8652	* @brief Enable the burst mode period interrupt.
<>	135:176b8275d35d	8653	* @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
<>	135:176b8275d35d	8654	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8655	* @retval None
<>	135:176b8275d35d	8656	*/
<>	135:176b8275d35d	8657	__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8658	{
<>	135:176b8275d35d	8659	SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
<>	135:176b8275d35d	8660	}
<>	135:176b8275d35d	8661
<>	135:176b8275d35d	8662	/**
<>	135:176b8275d35d	8663	* @brief Disable the burst mode period interrupt.
<>	135:176b8275d35d	8664	* @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
<>	135:176b8275d35d	8665	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8666	* @retval None
<>	135:176b8275d35d	8667	*/
<>	135:176b8275d35d	8668	__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8669	{
<>	135:176b8275d35d	8670	CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
<>	135:176b8275d35d	8671	}
<>	135:176b8275d35d	8672
<>	135:176b8275d35d	8673	/**
<>	135:176b8275d35d	8674	* @brief Indicate whether the burst mode period interrupt is enabled.
<>	135:176b8275d35d	8675	* @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
<>	135:176b8275d35d	8676	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8677	* @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
<>	135:176b8275d35d	8678	*/
<>	135:176b8275d35d	8679	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8680	{
<>	135:176b8275d35d	8681	return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER));
<>	135:176b8275d35d	8682	}
<>	135:176b8275d35d	8683
<>	135:176b8275d35d	8684	/**
<>	135:176b8275d35d	8685	* @brief Enable the synchronization input interrupt.
<>	135:176b8275d35d	8686	* @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
<>	135:176b8275d35d	8687	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8688	* @retval None
<>	135:176b8275d35d	8689	*/
<>	135:176b8275d35d	8690	__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8691	{
<>	135:176b8275d35d	8692	SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
<>	135:176b8275d35d	8693	}
<>	135:176b8275d35d	8694
<>	135:176b8275d35d	8695	/**
<>	135:176b8275d35d	8696	* @brief Disable the synchronization input interrupt.
<>	135:176b8275d35d	8697	* @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
<>	135:176b8275d35d	8698	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8699	* @retval None
<>	135:176b8275d35d	8700	*/
<>	135:176b8275d35d	8701	__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8702	{
<>	135:176b8275d35d	8703	CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
<>	135:176b8275d35d	8704	}
<>	135:176b8275d35d	8705
<>	135:176b8275d35d	8706	/**
<>	135:176b8275d35d	8707	* @brief Indicate whether the synchronization input interrupt is enabled.
<>	135:176b8275d35d	8708	* @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
<>	135:176b8275d35d	8709	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8710	* @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
<>	135:176b8275d35d	8711	*/
<>	135:176b8275d35d	8712	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	8713	{
<>	135:176b8275d35d	8714	return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE));
<>	135:176b8275d35d	8715	}
<>	135:176b8275d35d	8716
<>	135:176b8275d35d	8717	/**
<>	135:176b8275d35d	8718	* @brief Enable the update interrupt for a given timer.
<>	135:176b8275d35d	8719	* @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
<>	135:176b8275d35d	8720	* TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
<>	135:176b8275d35d	8721	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8722	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8723	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8724	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8725	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8726	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8727	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8728	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8729	* @retval None
<>	135:176b8275d35d	8730	*/
<>	135:176b8275d35d	8731	__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8732	{
<>	135:176b8275d35d	8733	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8734	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8735	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8736	SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
<>	135:176b8275d35d	8737	}
<>	135:176b8275d35d	8738
<>	135:176b8275d35d	8739	/**
<>	135:176b8275d35d	8740	* @brief Disable the update interrupt for a given timer.
<>	135:176b8275d35d	8741	* @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
<>	135:176b8275d35d	8742	* TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
<>	135:176b8275d35d	8743	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8744	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8745	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8746	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8747	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8748	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8749	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8750	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8751	* @retval None
<>	135:176b8275d35d	8752	*/
<>	135:176b8275d35d	8753	__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8754	{
<>	135:176b8275d35d	8755	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8756	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8757	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8758	CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
<>	135:176b8275d35d	8759	}
<>	135:176b8275d35d	8760
<>	135:176b8275d35d	8761	/**
<>	135:176b8275d35d	8762	* @brief Indicate whether the update interrupt is enabled for a given timer.
<>	135:176b8275d35d	8763	* @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
<>	135:176b8275d35d	8764	* TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
<>	135:176b8275d35d	8765	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8766	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8767	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8768	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8769	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8770	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8771	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8772	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8773	* @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	8774	*/
<>	135:176b8275d35d	8775	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8776	{
<>	135:176b8275d35d	8777	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8778	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8779	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8780	return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE));
<>	135:176b8275d35d	8781	}
<>	135:176b8275d35d	8782
<>	135:176b8275d35d	8783	/**
<>	135:176b8275d35d	8784	* @brief Enable the repetition interrupt for a given timer.
<>	135:176b8275d35d	8785	* @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
<>	135:176b8275d35d	8786	* TIMxDIER REPIE LL_HRTIM_EnableIT_REP
<>	135:176b8275d35d	8787	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8788	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8789	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8790	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8791	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8792	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8793	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8794	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8795	* @retval None
<>	135:176b8275d35d	8796	*/
<>	135:176b8275d35d	8797	__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8798	{
<>	135:176b8275d35d	8799	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8800	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8801	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8802	SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
<>	135:176b8275d35d	8803	}
<>	135:176b8275d35d	8804
<>	135:176b8275d35d	8805	/**
<>	135:176b8275d35d	8806	* @brief Disable the repetition interrupt for a given timer.
<>	135:176b8275d35d	8807	* @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
<>	135:176b8275d35d	8808	* TIMxDIER REPIE LL_HRTIM_DisableIT_REP
<>	135:176b8275d35d	8809	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8810	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8811	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8812	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8813	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8814	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8815	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8816	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8817	* @retval None
<>	135:176b8275d35d	8818	*/
<>	135:176b8275d35d	8819	__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8820	{
<>	135:176b8275d35d	8821	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8822	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8823	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8824	CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
<>	135:176b8275d35d	8825	}
<>	135:176b8275d35d	8826
<>	135:176b8275d35d	8827	/**
<>	135:176b8275d35d	8828	* @brief Indicate whether the repetition interrupt is enabled for a given timer.
<>	135:176b8275d35d	8829	* @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
<>	135:176b8275d35d	8830	* TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
<>	135:176b8275d35d	8831	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8832	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8833	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8834	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8835	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8836	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8837	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8838	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8839	* @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	8840	*/
<>	135:176b8275d35d	8841	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8842	{
<>	135:176b8275d35d	8843	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8844	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8845	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8846	return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE));
<>	135:176b8275d35d	8847	}
<>	135:176b8275d35d	8848
<>	135:176b8275d35d	8849	/**
<>	135:176b8275d35d	8850	* @brief Enable the compare 1 interrupt for a given timer.
<>	135:176b8275d35d	8851	* @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
<>	135:176b8275d35d	8852	* TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
<>	135:176b8275d35d	8853	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8854	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8855	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8856	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8857	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8858	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8859	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8860	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8861	* @retval None
<>	135:176b8275d35d	8862	*/
<>	135:176b8275d35d	8863	__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8864	{
<>	135:176b8275d35d	8865	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8866	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8867	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8868	SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
<>	135:176b8275d35d	8869	}
<>	135:176b8275d35d	8870
<>	135:176b8275d35d	8871	/**
<>	135:176b8275d35d	8872	* @brief Disable the compare 1 interrupt for a given timer.
<>	135:176b8275d35d	8873	* @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
<>	135:176b8275d35d	8874	* TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
<>	135:176b8275d35d	8875	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8876	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8877	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8878	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8879	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8880	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8881	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8882	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8883	* @retval None
<>	135:176b8275d35d	8884	*/
<>	135:176b8275d35d	8885	__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8886	{
<>	135:176b8275d35d	8887	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8888	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8889	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8890	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
<>	135:176b8275d35d	8891	}
<>	135:176b8275d35d	8892
<>	135:176b8275d35d	8893	/**
<>	135:176b8275d35d	8894	* @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
<>	135:176b8275d35d	8895	* @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
<>	135:176b8275d35d	8896	* TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
<>	135:176b8275d35d	8897	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8898	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8899	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8900	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8901	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8902	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8903	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8904	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8905	* @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	8906	*/
<>	135:176b8275d35d	8907	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8908	{
<>	135:176b8275d35d	8909	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8910	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8911	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8912	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE));
<>	135:176b8275d35d	8913	}
<>	135:176b8275d35d	8914
<>	135:176b8275d35d	8915	/**
<>	135:176b8275d35d	8916	* @brief Enable the compare 2 interrupt for a given timer.
<>	135:176b8275d35d	8917	* @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
<>	135:176b8275d35d	8918	* TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
<>	135:176b8275d35d	8919	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8920	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8921	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8922	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8923	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8924	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8925	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8926	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8927	* @retval None
<>	135:176b8275d35d	8928	*/
<>	135:176b8275d35d	8929	__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8930	{
<>	135:176b8275d35d	8931	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8932	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8933	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8934	SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
<>	135:176b8275d35d	8935	}
<>	135:176b8275d35d	8936
<>	135:176b8275d35d	8937	/**
<>	135:176b8275d35d	8938	* @brief Disable the compare 2 interrupt for a given timer.
<>	135:176b8275d35d	8939	* @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
<>	135:176b8275d35d	8940	* TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
<>	135:176b8275d35d	8941	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8942	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8943	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8944	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8945	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8946	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8947	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8948	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8949	* @retval None
<>	135:176b8275d35d	8950	*/
<>	135:176b8275d35d	8951	__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8952	{
<>	135:176b8275d35d	8953	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8954	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8955	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8956	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
<>	135:176b8275d35d	8957	}
<>	135:176b8275d35d	8958
<>	135:176b8275d35d	8959	/**
<>	135:176b8275d35d	8960	* @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
<>	135:176b8275d35d	8961	* @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
<>	135:176b8275d35d	8962	* TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
<>	135:176b8275d35d	8963	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8964	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8965	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8966	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8967	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8968	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8969	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8970	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8971	* @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	8972	*/
<>	135:176b8275d35d	8973	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8974	{
<>	135:176b8275d35d	8975	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8976	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8977	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	8978	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE));
<>	135:176b8275d35d	8979	}
<>	135:176b8275d35d	8980
<>	135:176b8275d35d	8981	/**
<>	135:176b8275d35d	8982	* @brief Enable the compare 3 interrupt for a given timer.
<>	135:176b8275d35d	8983	* @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
<>	135:176b8275d35d	8984	* TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
<>	135:176b8275d35d	8985	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	8986	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	8987	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	8988	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	8989	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	8990	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	8991	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	8992	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	8993	* @retval None
<>	135:176b8275d35d	8994	*/
<>	135:176b8275d35d	8995	__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	8996	{
<>	135:176b8275d35d	8997	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	8998	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	8999	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9000	SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
<>	135:176b8275d35d	9001	}
<>	135:176b8275d35d	9002
<>	135:176b8275d35d	9003	/**
<>	135:176b8275d35d	9004	* @brief Disable the compare 3 interrupt for a given timer.
<>	135:176b8275d35d	9005	* @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
<>	135:176b8275d35d	9006	* TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
<>	135:176b8275d35d	9007	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9008	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9009	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9010	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9011	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9012	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9013	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9014	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9015	* @retval None
<>	135:176b8275d35d	9016	*/
<>	135:176b8275d35d	9017	__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9018	{
<>	135:176b8275d35d	9019	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9020	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9021	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9022	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
<>	135:176b8275d35d	9023	}
<>	135:176b8275d35d	9024
<>	135:176b8275d35d	9025	/**
<>	135:176b8275d35d	9026	* @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
<>	135:176b8275d35d	9027	* @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
<>	135:176b8275d35d	9028	* TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
<>	135:176b8275d35d	9029	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9030	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9031	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9032	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9033	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9034	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9035	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9036	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9037	* @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9038	*/
<>	135:176b8275d35d	9039	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9040	{
<>	135:176b8275d35d	9041	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9042	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9043	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9044	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE));
<>	135:176b8275d35d	9045	}
<>	135:176b8275d35d	9046
<>	135:176b8275d35d	9047	/**
<>	135:176b8275d35d	9048	* @brief Enable the compare 4 interrupt for a given timer.
<>	135:176b8275d35d	9049	* @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
<>	135:176b8275d35d	9050	* TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
<>	135:176b8275d35d	9051	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9052	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9053	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9054	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9055	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9056	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9057	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9058	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9059	* @retval None
<>	135:176b8275d35d	9060	*/
<>	135:176b8275d35d	9061	__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9062	{
<>	135:176b8275d35d	9063	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9064	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9065	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9066	SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
<>	135:176b8275d35d	9067	}
<>	135:176b8275d35d	9068
<>	135:176b8275d35d	9069	/**
<>	135:176b8275d35d	9070	* @brief Disable the compare 4 interrupt for a given timer.
<>	135:176b8275d35d	9071	* @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
<>	135:176b8275d35d	9072	* TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
<>	135:176b8275d35d	9073	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9074	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9075	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9076	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9077	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9078	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9079	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9080	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9081	* @retval None
<>	135:176b8275d35d	9082	*/
<>	135:176b8275d35d	9083	__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9084	{
<>	135:176b8275d35d	9085	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9086	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9087	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9088	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
<>	135:176b8275d35d	9089	}
<>	135:176b8275d35d	9090
<>	135:176b8275d35d	9091	/**
<>	135:176b8275d35d	9092	* @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
<>	135:176b8275d35d	9093	* @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
<>	135:176b8275d35d	9094	* TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
<>	135:176b8275d35d	9095	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9096	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9097	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9098	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9099	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9100	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9101	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9102	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9103	* @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9104	*/
<>	135:176b8275d35d	9105	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9106	{
<>	135:176b8275d35d	9107	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9108	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9109	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9110	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE));
<>	135:176b8275d35d	9111	}
<>	135:176b8275d35d	9112
<>	135:176b8275d35d	9113	/**
<>	135:176b8275d35d	9114	* @brief Enable the capture 1 interrupt for a given timer.
<>	135:176b8275d35d	9115	* @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
<>	135:176b8275d35d	9116	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9117	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9118	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9119	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9120	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9121	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9122	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9123	* @retval None
<>	135:176b8275d35d	9124	*/
<>	135:176b8275d35d	9125	__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9126	{
<>	135:176b8275d35d	9127	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9128	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9129	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9130	SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
<>	135:176b8275d35d	9131	}
<>	135:176b8275d35d	9132
<>	135:176b8275d35d	9133	/**
<>	135:176b8275d35d	9134	* @brief Enable the capture 1 interrupt for a given timer.
<>	135:176b8275d35d	9135	* @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
<>	135:176b8275d35d	9136	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9137	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9138	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9139	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9140	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9141	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9142	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9143	* @retval None
<>	135:176b8275d35d	9144	*/
<>	135:176b8275d35d	9145	__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9146	{
<>	135:176b8275d35d	9147	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9148	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9149	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9150	CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
<>	135:176b8275d35d	9151	}
<>	135:176b8275d35d	9152
<>	135:176b8275d35d	9153	/**
<>	135:176b8275d35d	9154	* @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
<>	135:176b8275d35d	9155	* @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
<>	135:176b8275d35d	9156	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9157	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9158	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9159	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9160	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9161	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9162	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9163	* @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9164	*/
<>	135:176b8275d35d	9165	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9166	{
<>	135:176b8275d35d	9167	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9168	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9169	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9170	return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE));
<>	135:176b8275d35d	9171	}
<>	135:176b8275d35d	9172
<>	135:176b8275d35d	9173	/**
<>	135:176b8275d35d	9174	* @brief Enable the capture 2 interrupt for a given timer.
<>	135:176b8275d35d	9175	* @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
<>	135:176b8275d35d	9176	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9177	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9178	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9179	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9180	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9181	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9182	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9183	* @retval None
<>	135:176b8275d35d	9184	*/
<>	135:176b8275d35d	9185	__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9186	{
<>	135:176b8275d35d	9187	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9188	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9189	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9190	SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
<>	135:176b8275d35d	9191	}
<>	135:176b8275d35d	9192
<>	135:176b8275d35d	9193	/**
<>	135:176b8275d35d	9194	* @brief Enable the capture 2 interrupt for a given timer.
<>	135:176b8275d35d	9195	* @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
<>	135:176b8275d35d	9196	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9197	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9198	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9199	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9200	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9201	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9202	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9203	* @retval None
<>	135:176b8275d35d	9204	*/
<>	135:176b8275d35d	9205	__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9206	{
<>	135:176b8275d35d	9207	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9208	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9209	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9210	CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
<>	135:176b8275d35d	9211	}
<>	135:176b8275d35d	9212
<>	135:176b8275d35d	9213	/**
<>	135:176b8275d35d	9214	* @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
<>	135:176b8275d35d	9215	* @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
<>	135:176b8275d35d	9216	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9217	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9218	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9219	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9220	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9221	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9222	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9223	* @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9224	*/
<>	135:176b8275d35d	9225	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9226	{
<>	135:176b8275d35d	9227	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9228	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9229	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9230	return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE));
<>	135:176b8275d35d	9231	}
<>	135:176b8275d35d	9232
<>	135:176b8275d35d	9233	/**
<>	135:176b8275d35d	9234	* @brief Enable the output 1 set interrupt for a given timer.
<>	135:176b8275d35d	9235	* @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
<>	135:176b8275d35d	9236	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9237	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9238	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9239	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9240	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9241	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9242	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9243	* @retval None
<>	135:176b8275d35d	9244	*/
<>	135:176b8275d35d	9245	__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9246	{
<>	135:176b8275d35d	9247	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9248	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9249	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9250	SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
<>	135:176b8275d35d	9251	}
<>	135:176b8275d35d	9252
<>	135:176b8275d35d	9253	/**
<>	135:176b8275d35d	9254	* @brief Disable the output 1 set interrupt for a given timer.
<>	135:176b8275d35d	9255	* @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
<>	135:176b8275d35d	9256	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9257	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9258	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9259	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9260	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9261	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9262	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9263	* @retval None
<>	135:176b8275d35d	9264	*/
<>	135:176b8275d35d	9265	__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9266	{
<>	135:176b8275d35d	9267	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9268	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9269	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9270	CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
<>	135:176b8275d35d	9271	}
<>	135:176b8275d35d	9272
<>	135:176b8275d35d	9273	/**
<>	135:176b8275d35d	9274	* @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
<>	135:176b8275d35d	9275	* @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
<>	135:176b8275d35d	9276	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9277	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9278	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9279	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9280	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9281	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9282	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9283	* @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9284	*/
<>	135:176b8275d35d	9285	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9286	{
<>	135:176b8275d35d	9287	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9288	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9289	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9290	return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE));
<>	135:176b8275d35d	9291	}
<>	135:176b8275d35d	9292
<>	135:176b8275d35d	9293	/**
<>	135:176b8275d35d	9294	* @brief Enable the output 1 reset interrupt for a given timer.
<>	135:176b8275d35d	9295	* @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
<>	135:176b8275d35d	9296	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9297	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9298	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9299	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9300	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9301	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9302	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9303	* @retval None
<>	135:176b8275d35d	9304	*/
<>	135:176b8275d35d	9305	__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9306	{
<>	135:176b8275d35d	9307	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9308	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9309	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9310	SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
<>	135:176b8275d35d	9311	}
<>	135:176b8275d35d	9312
<>	135:176b8275d35d	9313	/**
<>	135:176b8275d35d	9314	* @brief Disable the output 1 reset interrupt for a given timer.
<>	135:176b8275d35d	9315	* @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
<>	135:176b8275d35d	9316	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9317	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9318	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9319	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9320	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9321	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9322	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9323	* @retval None
<>	135:176b8275d35d	9324	*/
<>	135:176b8275d35d	9325	__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9326	{
<>	135:176b8275d35d	9327	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9328	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9329	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9330	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
<>	135:176b8275d35d	9331	}
<>	135:176b8275d35d	9332
<>	135:176b8275d35d	9333	/**
<>	135:176b8275d35d	9334	* @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
<>	135:176b8275d35d	9335	* @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
<>	135:176b8275d35d	9336	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9337	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9338	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9339	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9340	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9341	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9342	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9343	* @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9344	*/
<>	135:176b8275d35d	9345	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9346	{
<>	135:176b8275d35d	9347	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9348	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9349	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9350	return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE));
<>	135:176b8275d35d	9351	}
<>	135:176b8275d35d	9352
<>	135:176b8275d35d	9353	/**
<>	135:176b8275d35d	9354	* @brief Enable the output 2 set interrupt for a given timer.
<>	135:176b8275d35d	9355	* @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
<>	135:176b8275d35d	9356	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9357	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9358	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9359	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9360	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9361	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9362	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9363	* @retval None
<>	135:176b8275d35d	9364	*/
<>	135:176b8275d35d	9365	__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9366	{
<>	135:176b8275d35d	9367	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9368	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9369	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9370	SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
<>	135:176b8275d35d	9371	}
<>	135:176b8275d35d	9372
<>	135:176b8275d35d	9373	/**
<>	135:176b8275d35d	9374	* @brief Disable the output 2 set interrupt for a given timer.
<>	135:176b8275d35d	9375	* @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
<>	135:176b8275d35d	9376	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9377	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9378	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9379	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9380	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9381	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9382	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9383	* @retval None
<>	135:176b8275d35d	9384	*/
<>	135:176b8275d35d	9385	__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9386	{
<>	135:176b8275d35d	9387	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9388	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9389	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9390	CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
<>	135:176b8275d35d	9391	}
<>	135:176b8275d35d	9392
<>	135:176b8275d35d	9393	/**
<>	135:176b8275d35d	9394	* @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
<>	135:176b8275d35d	9395	* @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
<>	135:176b8275d35d	9396	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9397	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9398	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9399	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9400	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9401	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9402	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9403	* @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9404	*/
<>	135:176b8275d35d	9405	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9406	{
<>	135:176b8275d35d	9407	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9408	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9409	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9410	return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE));
<>	135:176b8275d35d	9411	}
<>	135:176b8275d35d	9412
<>	135:176b8275d35d	9413	/**
<>	135:176b8275d35d	9414	* @brief Enable the output 2 reset interrupt for a given timer.
<>	135:176b8275d35d	9415	* @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
<>	135:176b8275d35d	9416	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9417	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9418	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9419	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9420	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9421	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9422	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9423	* @retval None
<>	135:176b8275d35d	9424	*/
<>	135:176b8275d35d	9425	__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9426	{
<>	135:176b8275d35d	9427	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9428	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9429	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9430	SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
<>	135:176b8275d35d	9431	}
<>	135:176b8275d35d	9432
<>	135:176b8275d35d	9433	/**
<>	135:176b8275d35d	9434	* @brief Disable the output 2 reset interrupt for a given timer.
<>	135:176b8275d35d	9435	* @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
<>	135:176b8275d35d	9436	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9437	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9438	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9439	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9440	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9441	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9442	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9443	* @retval None
<>	135:176b8275d35d	9444	*/
<>	135:176b8275d35d	9445	__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9446	{
<>	135:176b8275d35d	9447	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9448	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9449	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9450	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
<>	135:176b8275d35d	9451	}
<>	135:176b8275d35d	9452
<>	135:176b8275d35d	9453	/**
<>	135:176b8275d35d	9454	* @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
<>	135:176b8275d35d	9455	* @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
<>	135:176b8275d35d	9456	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9457	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9458	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9459	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9460	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9461	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9462	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9463	* @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9464	*/
<>	135:176b8275d35d	9465	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9466	{
<>	135:176b8275d35d	9467	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9468	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9469	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9470	return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE));
<>	135:176b8275d35d	9471	}
<>	135:176b8275d35d	9472
<>	135:176b8275d35d	9473	/**
<>	135:176b8275d35d	9474	* @brief Enable the reset/roll-over interrupt for a given timer.
<>	135:176b8275d35d	9475	* @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
<>	135:176b8275d35d	9476	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9477	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9478	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9479	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9480	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9481	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9482	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9483	* @retval None
<>	135:176b8275d35d	9484	*/
<>	135:176b8275d35d	9485	__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9486	{
<>	135:176b8275d35d	9487	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9488	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9489	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9490	SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
<>	135:176b8275d35d	9491	}
<>	135:176b8275d35d	9492
<>	135:176b8275d35d	9493	/**
<>	135:176b8275d35d	9494	* @brief Disable the reset/roll-over interrupt for a given timer.
<>	135:176b8275d35d	9495	* @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
<>	135:176b8275d35d	9496	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9497	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9498	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9499	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9500	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9501	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9502	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9503	* @retval None
<>	135:176b8275d35d	9504	*/
<>	135:176b8275d35d	9505	__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9506	{
<>	135:176b8275d35d	9507	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9508	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9509	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9510	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
<>	135:176b8275d35d	9511	}
<>	135:176b8275d35d	9512
<>	135:176b8275d35d	9513	/**
<>	135:176b8275d35d	9514	* @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
<>	135:176b8275d35d	9515	* @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
<>	135:176b8275d35d	9516	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9517	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9518	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9519	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9520	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9521	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9522	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9523	* @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9524	*/
<>	135:176b8275d35d	9525	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9526	{
<>	135:176b8275d35d	9527	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9528	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9529	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9530	return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE));
<>	135:176b8275d35d	9531	}
<>	135:176b8275d35d	9532
<>	135:176b8275d35d	9533	/**
<>	135:176b8275d35d	9534	* @brief Enable the delayed protection interrupt for a given timer.
<>	135:176b8275d35d	9535	* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
<>	135:176b8275d35d	9536	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9537	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9538	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9539	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9540	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9541	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9542	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9543	* @retval None
<>	135:176b8275d35d	9544	*/
<>	135:176b8275d35d	9545	__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9546	{
<>	135:176b8275d35d	9547	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9548	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9549	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9550	SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
<>	135:176b8275d35d	9551	}
<>	135:176b8275d35d	9552
<>	135:176b8275d35d	9553	/**
<>	135:176b8275d35d	9554	* @brief Disable the delayed protection interrupt for a given timer.
<>	135:176b8275d35d	9555	* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
<>	135:176b8275d35d	9556	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9557	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9558	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9559	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9560	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9561	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9562	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9563	* @retval None
<>	135:176b8275d35d	9564	*/
<>	135:176b8275d35d	9565	__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9566	{
<>	135:176b8275d35d	9567	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9568	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9569	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9570	CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
<>	135:176b8275d35d	9571	}
<>	135:176b8275d35d	9572
<>	135:176b8275d35d	9573	/**
<>	135:176b8275d35d	9574	* @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
<>	135:176b8275d35d	9575	* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
<>	135:176b8275d35d	9576	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9577	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9578	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9579	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9580	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9581	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9582	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9583	* @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9584	*/
<>	135:176b8275d35d	9585	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9586	{
<>	135:176b8275d35d	9587	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9588	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9589	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9590	return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE));
<>	135:176b8275d35d	9591	}
<>	135:176b8275d35d	9592
<>	135:176b8275d35d	9593	/**
<>	135:176b8275d35d	9594	* @}
<>	135:176b8275d35d	9595	*/
<>	135:176b8275d35d	9596
<>	135:176b8275d35d	9597	/** @defgroup HRTIM_EF_DMA_Management DMA_Management
<>	135:176b8275d35d	9598	* @{
<>	135:176b8275d35d	9599	*/
<>	135:176b8275d35d	9600
<>	135:176b8275d35d	9601	/**
<>	135:176b8275d35d	9602	* @brief Enable the synchronization input DMA request.
<>	135:176b8275d35d	9603	* @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
<>	135:176b8275d35d	9604	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9605	* @retval None
<>	135:176b8275d35d	9606	*/
<>	135:176b8275d35d	9607	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	9608	{
<>	135:176b8275d35d	9609	SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
<>	135:176b8275d35d	9610	}
<>	135:176b8275d35d	9611
<>	135:176b8275d35d	9612	/**
<>	135:176b8275d35d	9613	* @brief Disable the synchronization input DMA request
<>	135:176b8275d35d	9614	* @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
<>	135:176b8275d35d	9615	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9616	* @retval None
<>	135:176b8275d35d	9617	*/
<>	135:176b8275d35d	9618	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	9619	{
<>	135:176b8275d35d	9620	CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
<>	135:176b8275d35d	9621	}
<>	135:176b8275d35d	9622
<>	135:176b8275d35d	9623	/**
<>	135:176b8275d35d	9624	* @brief Indicate whether the synchronization input DMA request is enabled.
<>	135:176b8275d35d	9625	* @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
<>	135:176b8275d35d	9626	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9627	* @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
<>	135:176b8275d35d	9628	*/
<>	135:176b8275d35d	9629	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
<>	135:176b8275d35d	9630	{
<>	135:176b8275d35d	9631	return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE));
<>	135:176b8275d35d	9632	}
<>	135:176b8275d35d	9633
<>	135:176b8275d35d	9634	/**
<>	135:176b8275d35d	9635	* @brief Enable the update DMA request for a given timer.
<>	135:176b8275d35d	9636	* @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
<>	135:176b8275d35d	9637	* TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
<>	135:176b8275d35d	9638	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9639	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9640	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9641	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9642	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9643	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9644	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9645	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9646	* @retval None
<>	135:176b8275d35d	9647	*/
<>	135:176b8275d35d	9648	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9649	{
<>	135:176b8275d35d	9650	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9651	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9652	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9653	SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
<>	135:176b8275d35d	9654	}
<>	135:176b8275d35d	9655
<>	135:176b8275d35d	9656	/**
<>	135:176b8275d35d	9657	* @brief Disable the update DMA request for a given timer.
<>	135:176b8275d35d	9658	* @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
<>	135:176b8275d35d	9659	* TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
<>	135:176b8275d35d	9660	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9661	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9662	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9663	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9664	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9665	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9666	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9667	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9668	* @retval None
<>	135:176b8275d35d	9669	*/
<>	135:176b8275d35d	9670	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9671	{
<>	135:176b8275d35d	9672	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9673	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9674	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9675	CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
<>	135:176b8275d35d	9676	}
<>	135:176b8275d35d	9677
<>	135:176b8275d35d	9678	/**
<>	135:176b8275d35d	9679	* @brief Indicate whether the update DMA request is enabled for a given timer.
<>	135:176b8275d35d	9680	* @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
<>	135:176b8275d35d	9681	* TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
<>	135:176b8275d35d	9682	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9683	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9684	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9685	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9686	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9687	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9688	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9689	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9690	* @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9691	*/
<>	135:176b8275d35d	9692	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9693	{
<>	135:176b8275d35d	9694	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9695	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9696	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9697	return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE));
<>	135:176b8275d35d	9698	}
<>	135:176b8275d35d	9699
<>	135:176b8275d35d	9700	/**
<>	135:176b8275d35d	9701	* @brief Enable the repetition DMA request for a given timer.
<>	135:176b8275d35d	9702	* @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
<>	135:176b8275d35d	9703	* TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
<>	135:176b8275d35d	9704	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9705	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9706	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9707	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9708	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9709	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9710	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9711	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9712	* @retval None
<>	135:176b8275d35d	9713	*/
<>	135:176b8275d35d	9714	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9715	{
<>	135:176b8275d35d	9716	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9717	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9718	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9719	SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
<>	135:176b8275d35d	9720	}
<>	135:176b8275d35d	9721
<>	135:176b8275d35d	9722	/**
<>	135:176b8275d35d	9723	* @brief Disable the repetition DMA request for a given timer.
<>	135:176b8275d35d	9724	* @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
<>	135:176b8275d35d	9725	* TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
<>	135:176b8275d35d	9726	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9727	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9728	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9729	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9730	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9731	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9732	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9733	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9734	* @retval None
<>	135:176b8275d35d	9735	*/
<>	135:176b8275d35d	9736	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9737	{
<>	135:176b8275d35d	9738	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9739	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9740	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9741	CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
<>	135:176b8275d35d	9742	}
<>	135:176b8275d35d	9743
<>	135:176b8275d35d	9744	/**
<>	135:176b8275d35d	9745	* @brief Indicate whether the repetition DMA request is enabled for a given timer.
<>	135:176b8275d35d	9746	* @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
<>	135:176b8275d35d	9747	* TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
<>	135:176b8275d35d	9748	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9749	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9750	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9751	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9752	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9753	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9754	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9755	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9756	* @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9757	*/
<>	135:176b8275d35d	9758	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9759	{
<>	135:176b8275d35d	9760	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9761	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9762	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9763	return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE));
<>	135:176b8275d35d	9764	}
<>	135:176b8275d35d	9765
<>	135:176b8275d35d	9766	/**
<>	135:176b8275d35d	9767	* @brief Enable the compare 1 DMA request for a given timer.
<>	135:176b8275d35d	9768	* @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
<>	135:176b8275d35d	9769	* TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
<>	135:176b8275d35d	9770	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9771	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9772	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9773	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9774	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9775	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9776	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9777	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9778	* @retval None
<>	135:176b8275d35d	9779	*/
<>	135:176b8275d35d	9780	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9781	{
<>	135:176b8275d35d	9782	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9783	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9784	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9785	SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
<>	135:176b8275d35d	9786	}
<>	135:176b8275d35d	9787
<>	135:176b8275d35d	9788	/**
<>	135:176b8275d35d	9789	* @brief Disable the compare 1 DMA request for a given timer.
<>	135:176b8275d35d	9790	* @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
<>	135:176b8275d35d	9791	* TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
<>	135:176b8275d35d	9792	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9793	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9794	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9795	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9796	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9797	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9798	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9799	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9800	* @retval None
<>	135:176b8275d35d	9801	*/
<>	135:176b8275d35d	9802	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9803	{
<>	135:176b8275d35d	9804	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9805	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9806	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9807	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
<>	135:176b8275d35d	9808	}
<>	135:176b8275d35d	9809
<>	135:176b8275d35d	9810	/**
<>	135:176b8275d35d	9811	* @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
<>	135:176b8275d35d	9812	* @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
<>	135:176b8275d35d	9813	* TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
<>	135:176b8275d35d	9814	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9815	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9816	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9817	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9818	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9819	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9820	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9821	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9822	* @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9823	*/
<>	135:176b8275d35d	9824	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9825	{
<>	135:176b8275d35d	9826	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9827	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9828	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9829	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE));
<>	135:176b8275d35d	9830	}
<>	135:176b8275d35d	9831
<>	135:176b8275d35d	9832	/**
<>	135:176b8275d35d	9833	* @brief Enable the compare 2 DMA request for a given timer.
<>	135:176b8275d35d	9834	* @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
<>	135:176b8275d35d	9835	* TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
<>	135:176b8275d35d	9836	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9837	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9838	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9839	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9840	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9841	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9842	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9843	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9844	* @retval None
<>	135:176b8275d35d	9845	*/
<>	135:176b8275d35d	9846	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9847	{
<>	135:176b8275d35d	9848	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9849	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9850	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9851	SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
<>	135:176b8275d35d	9852	}
<>	135:176b8275d35d	9853
<>	135:176b8275d35d	9854	/**
<>	135:176b8275d35d	9855	* @brief Disable the compare 2 DMA request for a given timer.
<>	135:176b8275d35d	9856	* @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
<>	135:176b8275d35d	9857	* TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
<>	135:176b8275d35d	9858	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9859	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9860	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9861	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9862	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9863	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9864	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9865	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9866	* @retval None
<>	135:176b8275d35d	9867	*/
<>	135:176b8275d35d	9868	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9869	{
<>	135:176b8275d35d	9870	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9871	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9872	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9873	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
<>	135:176b8275d35d	9874	}
<>	135:176b8275d35d	9875
<>	135:176b8275d35d	9876	/**
<>	135:176b8275d35d	9877	* @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
<>	135:176b8275d35d	9878	* @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
<>	135:176b8275d35d	9879	* TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
<>	135:176b8275d35d	9880	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9881	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9882	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9883	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9884	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9885	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9886	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9887	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9888	* @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9889	*/
<>	135:176b8275d35d	9890	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9891	{
<>	135:176b8275d35d	9892	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9893	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9894	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9895	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE));
<>	135:176b8275d35d	9896	}
<>	135:176b8275d35d	9897
<>	135:176b8275d35d	9898	/**
<>	135:176b8275d35d	9899	* @brief Enable the compare 3 DMA request for a given timer.
<>	135:176b8275d35d	9900	* @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
<>	135:176b8275d35d	9901	* TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
<>	135:176b8275d35d	9902	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9903	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9904	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9905	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9906	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9907	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9908	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9909	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9910	* @retval None
<>	135:176b8275d35d	9911	*/
<>	135:176b8275d35d	9912	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9913	{
<>	135:176b8275d35d	9914	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9915	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9916	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9917	SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
<>	135:176b8275d35d	9918	}
<>	135:176b8275d35d	9919
<>	135:176b8275d35d	9920	/**
<>	135:176b8275d35d	9921	* @brief Disable the compare 3 DMA request for a given timer.
<>	135:176b8275d35d	9922	* @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
<>	135:176b8275d35d	9923	* TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
<>	135:176b8275d35d	9924	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9925	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9926	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9927	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9928	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9929	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9930	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9931	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9932	* @retval None
<>	135:176b8275d35d	9933	*/
<>	135:176b8275d35d	9934	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9935	{
<>	135:176b8275d35d	9936	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9937	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9938	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9939	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
<>	135:176b8275d35d	9940	}
<>	135:176b8275d35d	9941
<>	135:176b8275d35d	9942	/**
<>	135:176b8275d35d	9943	* @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
<>	135:176b8275d35d	9944	* @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
<>	135:176b8275d35d	9945	* TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
<>	135:176b8275d35d	9946	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9947	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9948	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9949	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9950	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9951	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9952	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9953	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9954	* @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	9955	*/
<>	135:176b8275d35d	9956	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9957	{
<>	135:176b8275d35d	9958	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9959	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9960	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9961	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE));
<>	135:176b8275d35d	9962	}
<>	135:176b8275d35d	9963
<>	135:176b8275d35d	9964	/**
<>	135:176b8275d35d	9965	* @brief Enable the compare 4 DMA request for a given timer.
<>	135:176b8275d35d	9966	* @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
<>	135:176b8275d35d	9967	* TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
<>	135:176b8275d35d	9968	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9969	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9970	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9971	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9972	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9973	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9974	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9975	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9976	* @retval None
<>	135:176b8275d35d	9977	*/
<>	135:176b8275d35d	9978	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	9979	{
<>	135:176b8275d35d	9980	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	9981	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	9982	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	9983	SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
<>	135:176b8275d35d	9984	}
<>	135:176b8275d35d	9985
<>	135:176b8275d35d	9986	/**
<>	135:176b8275d35d	9987	* @brief Disable the compare 4 DMA request for a given timer.
<>	135:176b8275d35d	9988	* @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
<>	135:176b8275d35d	9989	* TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
<>	135:176b8275d35d	9990	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	9991	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	9992	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	9993	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	9994	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	9995	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	9996	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	9997	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	9998	* @retval None
<>	135:176b8275d35d	9999	*/
<>	135:176b8275d35d	10000	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10001	{
<>	135:176b8275d35d	10002	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10003	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10004	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10005	CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
<>	135:176b8275d35d	10006	}
<>	135:176b8275d35d	10007
<>	135:176b8275d35d	10008	/**
<>	135:176b8275d35d	10009	* @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
<>	135:176b8275d35d	10010	* @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
<>	135:176b8275d35d	10011	* TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
<>	135:176b8275d35d	10012	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10013	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10014	* @arg @ref LL_HRTIM_TIMER_MASTER
<>	135:176b8275d35d	10015	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10016	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10017	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10018	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10019	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10020	* @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10021	*/
<>	135:176b8275d35d	10022	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10023	{
<>	135:176b8275d35d	10024	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10025	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10026	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10027	return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE));
<>	135:176b8275d35d	10028	}
<>	135:176b8275d35d	10029
<>	135:176b8275d35d	10030	/**
<>	135:176b8275d35d	10031	* @brief Enable the capture 1 DMA request for a given timer.
<>	135:176b8275d35d	10032	* @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
<>	135:176b8275d35d	10033	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10034	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10035	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10036	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10037	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10038	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10039	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10040	* @retval None
<>	135:176b8275d35d	10041	*/
<>	135:176b8275d35d	10042	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10043	{
<>	135:176b8275d35d	10044	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10045	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10046	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10047	SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
<>	135:176b8275d35d	10048	}
<>	135:176b8275d35d	10049
<>	135:176b8275d35d	10050	/**
<>	135:176b8275d35d	10051	* @brief Disable the capture 1 DMA request for a given timer.
<>	135:176b8275d35d	10052	* @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
<>	135:176b8275d35d	10053	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10054	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10055	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10056	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10057	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10058	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10059	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10060	* @retval None
<>	135:176b8275d35d	10061	*/
<>	135:176b8275d35d	10062	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10063	{
<>	135:176b8275d35d	10064	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10065	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10066	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10067	CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
<>	135:176b8275d35d	10068	}
<>	135:176b8275d35d	10069
<>	135:176b8275d35d	10070	/**
<>	135:176b8275d35d	10071	* @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
<>	135:176b8275d35d	10072	* @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
<>	135:176b8275d35d	10073	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10074	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10075	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10076	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10077	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10078	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10079	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10080	* @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10081	*/
<>	135:176b8275d35d	10082	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10083	{
<>	135:176b8275d35d	10084	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10085	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10086	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10087	return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE));
<>	135:176b8275d35d	10088	}
<>	135:176b8275d35d	10089
<>	135:176b8275d35d	10090	/**
<>	135:176b8275d35d	10091	* @brief Enable the capture 2 DMA request for a given timer.
<>	135:176b8275d35d	10092	* @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
<>	135:176b8275d35d	10093	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10094	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10095	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10096	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10097	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10098	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10099	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10100	* @retval None
<>	135:176b8275d35d	10101	*/
<>	135:176b8275d35d	10102	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10103	{
<>	135:176b8275d35d	10104	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10105	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10106	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10107	SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
<>	135:176b8275d35d	10108	}
<>	135:176b8275d35d	10109
<>	135:176b8275d35d	10110	/**
<>	135:176b8275d35d	10111	* @brief Disable the capture 2 DMA request for a given timer.
<>	135:176b8275d35d	10112	* @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
<>	135:176b8275d35d	10113	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10114	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10115	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10116	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10117	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10118	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10119	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10120	* @retval None
<>	135:176b8275d35d	10121	*/
<>	135:176b8275d35d	10122	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10123	{
<>	135:176b8275d35d	10124	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10125	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10126	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10127	CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
<>	135:176b8275d35d	10128	}
<>	135:176b8275d35d	10129
<>	135:176b8275d35d	10130	/**
<>	135:176b8275d35d	10131	* @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
<>	135:176b8275d35d	10132	* @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
<>	135:176b8275d35d	10133	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10134	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10135	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10136	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10137	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10138	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10139	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10140	* @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10141	*/
<>	135:176b8275d35d	10142	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10143	{
<>	135:176b8275d35d	10144	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10145	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10146	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10147	return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE));
<>	135:176b8275d35d	10148	}
<>	135:176b8275d35d	10149
<>	135:176b8275d35d	10150	/**
<>	135:176b8275d35d	10151	* @brief Enable the output 1 set DMA request for a given timer.
<>	135:176b8275d35d	10152	* @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
<>	135:176b8275d35d	10153	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10154	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10155	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10156	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10157	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10158	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10159	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10160	* @retval None
<>	135:176b8275d35d	10161	*/
<>	135:176b8275d35d	10162	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10163	{
<>	135:176b8275d35d	10164	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10165	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10166	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10167	SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
<>	135:176b8275d35d	10168	}
<>	135:176b8275d35d	10169
<>	135:176b8275d35d	10170	/**
<>	135:176b8275d35d	10171	* @brief Disable the output 1 set DMA request for a given timer.
<>	135:176b8275d35d	10172	* @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
<>	135:176b8275d35d	10173	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10174	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10175	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10176	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10177	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10178	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10179	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10180	* @retval None
<>	135:176b8275d35d	10181	*/
<>	135:176b8275d35d	10182	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10183	{
<>	135:176b8275d35d	10184	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10185	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10186	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10187	CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
<>	135:176b8275d35d	10188	}
<>	135:176b8275d35d	10189
<>	135:176b8275d35d	10190	/**
<>	135:176b8275d35d	10191	* @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
<>	135:176b8275d35d	10192	* @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
<>	135:176b8275d35d	10193	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10194	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10195	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10196	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10197	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10198	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10199	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10200	* @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10201	*/
<>	135:176b8275d35d	10202	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10203	{
<>	135:176b8275d35d	10204	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10205	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10206	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10207	return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE));
<>	135:176b8275d35d	10208	}
<>	135:176b8275d35d	10209
<>	135:176b8275d35d	10210	/**
<>	135:176b8275d35d	10211	* @brief Enable the output 1 reset DMA request for a given timer.
<>	135:176b8275d35d	10212	* @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
<>	135:176b8275d35d	10213	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10214	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10215	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10216	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10217	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10218	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10219	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10220	* @retval None
<>	135:176b8275d35d	10221	*/
<>	135:176b8275d35d	10222	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10223	{
<>	135:176b8275d35d	10224	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10225	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10226	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10227	SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
<>	135:176b8275d35d	10228	}
<>	135:176b8275d35d	10229
<>	135:176b8275d35d	10230	/**
<>	135:176b8275d35d	10231	* @brief Disable the output 1 reset DMA request for a given timer.
<>	135:176b8275d35d	10232	* @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
<>	135:176b8275d35d	10233	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10234	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10235	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10236	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10237	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10238	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10239	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10240	* @retval None
<>	135:176b8275d35d	10241	*/
<>	135:176b8275d35d	10242	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10243	{
<>	135:176b8275d35d	10244	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10245	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10246	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10247	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
<>	135:176b8275d35d	10248	}
<>	135:176b8275d35d	10249
<>	135:176b8275d35d	10250	/**
<>	135:176b8275d35d	10251	* @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
<>	135:176b8275d35d	10252	* @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
<>	135:176b8275d35d	10253	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10254	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10255	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10256	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10257	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10258	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10259	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10260	* @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10261	*/
<>	135:176b8275d35d	10262	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10263	{
<>	135:176b8275d35d	10264	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10265	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10266	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10267	return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE));
<>	135:176b8275d35d	10268	}
<>	135:176b8275d35d	10269
<>	135:176b8275d35d	10270	/**
<>	135:176b8275d35d	10271	* @brief Enable the output 2 set DMA request for a given timer.
<>	135:176b8275d35d	10272	* @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
<>	135:176b8275d35d	10273	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10274	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10275	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10276	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10277	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10278	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10279	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10280	* @retval None
<>	135:176b8275d35d	10281	*/
<>	135:176b8275d35d	10282	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10283	{
<>	135:176b8275d35d	10284	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10285	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10286	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10287	SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
<>	135:176b8275d35d	10288	}
<>	135:176b8275d35d	10289
<>	135:176b8275d35d	10290	/**
<>	135:176b8275d35d	10291	* @brief Disable the output 2 set DMA request for a given timer.
<>	135:176b8275d35d	10292	* @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
<>	135:176b8275d35d	10293	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10294	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10295	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10296	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10297	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10298	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10299	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10300	* @retval None
<>	135:176b8275d35d	10301	*/
<>	135:176b8275d35d	10302	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10303	{
<>	135:176b8275d35d	10304	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10305	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10306	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10307	CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
<>	135:176b8275d35d	10308	}
<>	135:176b8275d35d	10309
<>	135:176b8275d35d	10310	/**
<>	135:176b8275d35d	10311	* @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
<>	135:176b8275d35d	10312	* @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
<>	135:176b8275d35d	10313	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10314	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10315	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10316	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10317	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10318	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10319	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10320	* @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10321	*/
<>	135:176b8275d35d	10322	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10323	{
<>	135:176b8275d35d	10324	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10325	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10326	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10327	return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE));
<>	135:176b8275d35d	10328	}
<>	135:176b8275d35d	10329
<>	135:176b8275d35d	10330	/**
<>	135:176b8275d35d	10331	* @brief Enable the output 2 reset DMA request for a given timer.
<>	135:176b8275d35d	10332	* @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
<>	135:176b8275d35d	10333	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10334	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10335	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10336	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10337	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10338	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10339	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10340	* @retval None
<>	135:176b8275d35d	10341	*/
<>	135:176b8275d35d	10342	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10343	{
<>	135:176b8275d35d	10344	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10345	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10346	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10347	SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
<>	135:176b8275d35d	10348	}
<>	135:176b8275d35d	10349
<>	135:176b8275d35d	10350	/**
<>	135:176b8275d35d	10351	* @brief Disable the output 2 reset DMA request for a given timer.
<>	135:176b8275d35d	10352	* @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
<>	135:176b8275d35d	10353	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10354	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10355	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10356	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10357	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10358	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10359	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10360	* @retval None
<>	135:176b8275d35d	10361	*/
<>	135:176b8275d35d	10362	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10363	{
<>	135:176b8275d35d	10364	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10365	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10366	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10367	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
<>	135:176b8275d35d	10368	}
<>	135:176b8275d35d	10369
<>	135:176b8275d35d	10370	/**
<>	135:176b8275d35d	10371	* @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
<>	135:176b8275d35d	10372	* @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
<>	135:176b8275d35d	10373	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10374	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10375	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10376	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10377	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10378	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10379	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10380	* @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10381	*/
<>	135:176b8275d35d	10382	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10383	{
<>	135:176b8275d35d	10384	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10385	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10386	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10387	return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE));
<>	135:176b8275d35d	10388	}
<>	135:176b8275d35d	10389
<>	135:176b8275d35d	10390	/**
<>	135:176b8275d35d	10391	* @brief Enable the reset/roll-over DMA request for a given timer.
<>	135:176b8275d35d	10392	* @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
<>	135:176b8275d35d	10393	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10394	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10395	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10396	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10397	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10398	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10399	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10400	* @retval None
<>	135:176b8275d35d	10401	*/
<>	135:176b8275d35d	10402	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10403	{
<>	135:176b8275d35d	10404	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10405	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10406	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10407	SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
<>	135:176b8275d35d	10408	}
<>	135:176b8275d35d	10409
<>	135:176b8275d35d	10410	/**
<>	135:176b8275d35d	10411	* @brief Disable the reset/roll-over DMA request for a given timer.
<>	135:176b8275d35d	10412	* @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
<>	135:176b8275d35d	10413	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10414	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10415	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10416	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10417	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10418	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10419	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10420	* @retval None
<>	135:176b8275d35d	10421	*/
<>	135:176b8275d35d	10422	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10423	{
<>	135:176b8275d35d	10424	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10425	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10426	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10427	CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
<>	135:176b8275d35d	10428	}
<>	135:176b8275d35d	10429
<>	135:176b8275d35d	10430	/**
<>	135:176b8275d35d	10431	* @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
<>	135:176b8275d35d	10432	* @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
<>	135:176b8275d35d	10433	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10434	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10435	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10436	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10437	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10438	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10439	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10440	* @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10441	*/
<>	135:176b8275d35d	10442	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10443	{
<>	135:176b8275d35d	10444	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10445	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10446	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10447	return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE));
<>	135:176b8275d35d	10448	}
<>	135:176b8275d35d	10449
<>	135:176b8275d35d	10450	/**
<>	135:176b8275d35d	10451	* @brief Enable the delayed protection DMA request for a given timer.
<>	135:176b8275d35d	10452	* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
<>	135:176b8275d35d	10453	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10454	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10455	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10456	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10457	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10458	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10459	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10460	* @retval None
<>	135:176b8275d35d	10461	*/
<>	135:176b8275d35d	10462	__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10463	{
<>	135:176b8275d35d	10464	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10465	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10466	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10467	SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
<>	135:176b8275d35d	10468	}
<>	135:176b8275d35d	10469
<>	135:176b8275d35d	10470	/**
<>	135:176b8275d35d	10471	* @brief Disable the delayed protection DMA request for a given timer.
<>	135:176b8275d35d	10472	* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
<>	135:176b8275d35d	10473	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10474	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10475	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10476	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10477	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10478	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10479	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10480	* @retval None
<>	135:176b8275d35d	10481	*/
<>	135:176b8275d35d	10482	__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10483	{
<>	135:176b8275d35d	10484	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10485	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10486	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10487	CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
<>	135:176b8275d35d	10488	}
<>	135:176b8275d35d	10489
<>	135:176b8275d35d	10490	/**
<>	135:176b8275d35d	10491	* @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
<>	135:176b8275d35d	10492	* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
<>	135:176b8275d35d	10493	* @param HRTIMx High Resolution Timer instance
<>	135:176b8275d35d	10494	* @param Timer This parameter can be one of the following values:
<>	135:176b8275d35d	10495	* @arg @ref LL_HRTIM_TIMER_A
<>	135:176b8275d35d	10496	* @arg @ref LL_HRTIM_TIMER_B
<>	135:176b8275d35d	10497	* @arg @ref LL_HRTIM_TIMER_C
<>	135:176b8275d35d	10498	* @arg @ref LL_HRTIM_TIMER_D
<>	135:176b8275d35d	10499	* @arg @ref LL_HRTIM_TIMER_E
<>	135:176b8275d35d	10500	* @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
<>	135:176b8275d35d	10501	*/
<>	135:176b8275d35d	10502	__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
<>	135:176b8275d35d	10503	{
<>	135:176b8275d35d	10504	register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
<>	135:176b8275d35d	10505	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
<>	135:176b8275d35d	10506	REG_OFFSET_TAB_TIMER[iTimer]));
<>	135:176b8275d35d	10507	return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE));
<>	135:176b8275d35d	10508	}
<>	135:176b8275d35d	10509
<>	135:176b8275d35d	10510	/**
<>	135:176b8275d35d	10511	* @}
<>	135:176b8275d35d	10512	*/
<>	135:176b8275d35d	10513
<>	135:176b8275d35d	10514	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	10515	/** @defgroup HRTIM_LL_EF_Init Initialisation and deinitialisation functions
<>	135:176b8275d35d	10516	* @{
<>	135:176b8275d35d	10517	*/
<>	135:176b8275d35d	10518	ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
<>	135:176b8275d35d	10519	/**
<>	135:176b8275d35d	10520	* @}
<>	135:176b8275d35d	10521	*/
<>	135:176b8275d35d	10522	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	10523
<>	135:176b8275d35d	10524	/**
<>	135:176b8275d35d	10525	* @}
<>	135:176b8275d35d	10526	*/
<>	135:176b8275d35d	10527
<>	135:176b8275d35d	10528	/**
<>	135:176b8275d35d	10529	* @}
<>	135:176b8275d35d	10530	*/
<>	135:176b8275d35d	10531
<>	135:176b8275d35d	10532	#endif /* HRTIM1 */
<>	135:176b8275d35d	10533
<>	135:176b8275d35d	10534	/**
<>	135:176b8275d35d	10535	* @}
<>	135:176b8275d35d	10536	*/
<>	135:176b8275d35d	10537
<>	135:176b8275d35d	10538	#ifdef __cplusplus
<>	135:176b8275d35d	10539	}
<>	135:176b8275d35d	10540	#endif
<>	135:176b8275d35d	10541
<>	135:176b8275d35d	10542	#endif /* __STM32F3xx_LL_HRTIM_H */
<>	135:176b8275d35d	10543
<>	135:176b8275d35d	10544	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/