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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 135:176b8275d35d
Child:: 168:b9e159c1930a

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_dma.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
<>	135:176b8275d35d	7	* @brief Header file of DMA LL module.
<>	135:176b8275d35d	8	******************************************************************************
<>	135:176b8275d35d	9	* @attention
<>	135:176b8275d35d	10	*
<>	135:176b8275d35d	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	12	*
<>	135:176b8275d35d	13	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	14	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	16	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	18	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	19	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	21	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	22	* without specific prior written permission.
<>	135:176b8275d35d	23	*
<>	135:176b8275d35d	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	34	*
<>	135:176b8275d35d	35	******************************************************************************
<>	135:176b8275d35d	36	*/
<>	135:176b8275d35d	37
<>	135:176b8275d35d	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	39	#ifndef __STM32F3xx_LL_DMA_H
<>	135:176b8275d35d	40	#define __STM32F3xx_LL_DMA_H
<>	135:176b8275d35d	41
<>	135:176b8275d35d	42	#ifdef __cplusplus
<>	135:176b8275d35d	43	extern "C" {
<>	135:176b8275d35d	44	#endif
<>	135:176b8275d35d	45
<>	135:176b8275d35d	46	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	47	#include "stm32f3xx.h"
<>	135:176b8275d35d	48
<>	135:176b8275d35d	49	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	50	* @{
<>	135:176b8275d35d	51	*/
<>	135:176b8275d35d	52
<>	135:176b8275d35d	53	#if defined (DMA1) \|\| defined (DMA2)
<>	135:176b8275d35d	54
<>	135:176b8275d35d	55	/** @defgroup DMA_LL DMA
<>	135:176b8275d35d	56	* @{
<>	135:176b8275d35d	57	*/
<>	135:176b8275d35d	58
<>	135:176b8275d35d	59	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	60	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	135:176b8275d35d	62	* @{
<>	135:176b8275d35d	63	*/
<>	135:176b8275d35d	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	135:176b8275d35d	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	135:176b8275d35d	66	{
<>	135:176b8275d35d	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	135:176b8275d35d	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	135:176b8275d35d	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	135:176b8275d35d	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	135:176b8275d35d	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	135:176b8275d35d	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	135:176b8275d35d	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	135:176b8275d35d	74	};
<>	135:176b8275d35d	75	/**
<>	135:176b8275d35d	76	* @}
<>	135:176b8275d35d	77	*/
<>	135:176b8275d35d	78
<>	135:176b8275d35d	79	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
<>	135:176b8275d35d	81	* @{
<>	135:176b8275d35d	82	*/
<>	135:176b8275d35d	83	/* Define used to get CSELR register offset */
<>	135:176b8275d35d	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<>	135:176b8275d35d	85
<>	135:176b8275d35d	86	/* Defines used for the bit position in the register and perform offsets */
<>	135:176b8275d35d	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
<>	135:176b8275d35d	88	/**
<>	135:176b8275d35d	89	* @}
<>	135:176b8275d35d	90	*/
<>	135:176b8275d35d	91
<>	135:176b8275d35d	92	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	93	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	135:176b8275d35d	95	* @{
<>	135:176b8275d35d	96	*/
<>	135:176b8275d35d	97	/**
<>	135:176b8275d35d	98	* @}
<>	135:176b8275d35d	99	*/
<>	135:176b8275d35d	100	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	101
<>	135:176b8275d35d	102	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	103	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	135:176b8275d35d	105	* @{
<>	135:176b8275d35d	106	*/
<>	135:176b8275d35d	107	typedef struct
<>	135:176b8275d35d	108	{
<>	135:176b8275d35d	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	135:176b8275d35d	110	or as Source base address in case of memory to memory transfer direction.
<>	135:176b8275d35d	111
<>	135:176b8275d35d	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	135:176b8275d35d	113
<>	135:176b8275d35d	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	135:176b8275d35d	115	or as Destination base address in case of memory to memory transfer direction.
<>	135:176b8275d35d	116
<>	135:176b8275d35d	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	135:176b8275d35d	118
<>	135:176b8275d35d	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	135:176b8275d35d	120	from memory to memory or from peripheral to memory.
<>	135:176b8275d35d	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	135:176b8275d35d	122
<>	135:176b8275d35d	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	135:176b8275d35d	124
<>	135:176b8275d35d	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	135:176b8275d35d	126	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	135:176b8275d35d	127	@note: The circular buffer mode cannot be used if the memory to memory
<>	135:176b8275d35d	128	data transfer direction is configured on the selected Channel
<>	135:176b8275d35d	129
<>	135:176b8275d35d	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	135:176b8275d35d	131
<>	135:176b8275d35d	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	135:176b8275d35d	133	is incremented or not.
<>	135:176b8275d35d	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	135:176b8275d35d	135
<>	135:176b8275d35d	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	135:176b8275d35d	137
<>	135:176b8275d35d	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	135:176b8275d35d	139	is incremented or not.
<>	135:176b8275d35d	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	135:176b8275d35d	141
<>	135:176b8275d35d	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	135:176b8275d35d	143
<>	135:176b8275d35d	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	135:176b8275d35d	145	in case of memory to memory transfer direction.
<>	135:176b8275d35d	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	135:176b8275d35d	147
<>	135:176b8275d35d	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	135:176b8275d35d	149
<>	135:176b8275d35d	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	135:176b8275d35d	151	in case of memory to memory transfer direction.
<>	135:176b8275d35d	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	135:176b8275d35d	153
<>	135:176b8275d35d	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	135:176b8275d35d	155
<>	135:176b8275d35d	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	135:176b8275d35d	157	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	135:176b8275d35d	158	or MemorySize parameters depending in the transfer direction.
<>	135:176b8275d35d	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	135:176b8275d35d	160
<>	135:176b8275d35d	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	135:176b8275d35d	162
<>	135:176b8275d35d	163	uint32_t Priority; /*!< Specifies the channel priority level.
<>	135:176b8275d35d	164	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	135:176b8275d35d	165
<>	135:176b8275d35d	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	135:176b8275d35d	167
<>	135:176b8275d35d	168	} LL_DMA_InitTypeDef;
<>	135:176b8275d35d	169	/**
<>	135:176b8275d35d	170	* @}
<>	135:176b8275d35d	171	*/
<>	135:176b8275d35d	172	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	173
<>	135:176b8275d35d	174	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	175	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	135:176b8275d35d	176	* @{
<>	135:176b8275d35d	177	*/
<>	135:176b8275d35d	178	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	135:176b8275d35d	179	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	135:176b8275d35d	180	* @{
<>	135:176b8275d35d	181	*/
<>	135:176b8275d35d	182	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	135:176b8275d35d	183	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	135:176b8275d35d	184	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	135:176b8275d35d	185	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	135:176b8275d35d	186	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	135:176b8275d35d	187	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	135:176b8275d35d	188	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	135:176b8275d35d	189	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	135:176b8275d35d	190	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	135:176b8275d35d	191	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	135:176b8275d35d	192	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	135:176b8275d35d	193	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	135:176b8275d35d	194	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	135:176b8275d35d	195	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	135:176b8275d35d	196	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	135:176b8275d35d	197	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	135:176b8275d35d	198	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	135:176b8275d35d	199	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	135:176b8275d35d	200	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	135:176b8275d35d	201	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	135:176b8275d35d	202	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	135:176b8275d35d	203	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	135:176b8275d35d	204	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	135:176b8275d35d	205	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	135:176b8275d35d	206	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	135:176b8275d35d	207	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	135:176b8275d35d	208	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	135:176b8275d35d	209	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	135:176b8275d35d	210	/**
<>	135:176b8275d35d	211	* @}
<>	135:176b8275d35d	212	*/
<>	135:176b8275d35d	213
<>	135:176b8275d35d	214	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	215	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	135:176b8275d35d	216	* @{
<>	135:176b8275d35d	217	*/
<>	135:176b8275d35d	218	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	135:176b8275d35d	219	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	135:176b8275d35d	220	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	135:176b8275d35d	221	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	135:176b8275d35d	222	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	135:176b8275d35d	223	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	135:176b8275d35d	224	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	135:176b8275d35d	225	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	135:176b8275d35d	226	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	135:176b8275d35d	227	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	135:176b8275d35d	228	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	135:176b8275d35d	229	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	135:176b8275d35d	230	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	135:176b8275d35d	231	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	135:176b8275d35d	232	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	135:176b8275d35d	233	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	135:176b8275d35d	234	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	135:176b8275d35d	235	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	135:176b8275d35d	236	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	135:176b8275d35d	237	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	135:176b8275d35d	238	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	135:176b8275d35d	239	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	135:176b8275d35d	240	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	135:176b8275d35d	241	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	135:176b8275d35d	242	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	135:176b8275d35d	243	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	135:176b8275d35d	244	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	135:176b8275d35d	245	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	135:176b8275d35d	246	/**
<>	135:176b8275d35d	247	* @}
<>	135:176b8275d35d	248	*/
<>	135:176b8275d35d	249
<>	135:176b8275d35d	250	/** @defgroup DMA_LL_EC_IT IT Defines
<>	135:176b8275d35d	251	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	135:176b8275d35d	252	* @{
<>	135:176b8275d35d	253	*/
<>	135:176b8275d35d	254	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	135:176b8275d35d	255	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	135:176b8275d35d	256	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	135:176b8275d35d	257	/**
<>	135:176b8275d35d	258	* @}
<>	135:176b8275d35d	259	*/
<>	135:176b8275d35d	260
<>	135:176b8275d35d	261	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	135:176b8275d35d	262	* @{
<>	135:176b8275d35d	263	*/
<>	135:176b8275d35d	264	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
<>	135:176b8275d35d	265	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
<>	135:176b8275d35d	266	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
<>	135:176b8275d35d	267	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
<>	135:176b8275d35d	268	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
<>	135:176b8275d35d	269	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
<>	135:176b8275d35d	270	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
<>	135:176b8275d35d	271	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	272	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	135:176b8275d35d	273	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	274	/**
<>	135:176b8275d35d	275	* @}
<>	135:176b8275d35d	276	*/
<>	135:176b8275d35d	277
<>	135:176b8275d35d	278	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	135:176b8275d35d	279	* @{
<>	135:176b8275d35d	280	*/
<>	135:176b8275d35d	281	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
<>	135:176b8275d35d	282	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	135:176b8275d35d	283	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	135:176b8275d35d	284	/**
<>	135:176b8275d35d	285	* @}
<>	135:176b8275d35d	286	*/
<>	135:176b8275d35d	287
<>	135:176b8275d35d	288	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	135:176b8275d35d	289	* @{
<>	135:176b8275d35d	290	*/
<>	135:176b8275d35d	291	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
<>	135:176b8275d35d	292	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	135:176b8275d35d	293	/**
<>	135:176b8275d35d	294	* @}
<>	135:176b8275d35d	295	*/
<>	135:176b8275d35d	296
<>	135:176b8275d35d	297	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	135:176b8275d35d	298	* @{
<>	135:176b8275d35d	299	*/
<>	135:176b8275d35d	300	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
<>	135:176b8275d35d	301	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
<>	135:176b8275d35d	302	/**
<>	135:176b8275d35d	303	* @}
<>	135:176b8275d35d	304	*/
<>	135:176b8275d35d	305
<>	135:176b8275d35d	306	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	135:176b8275d35d	307	* @{
<>	135:176b8275d35d	308	*/
<>	135:176b8275d35d	309	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
<>	135:176b8275d35d	310	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
<>	135:176b8275d35d	311	/**
<>	135:176b8275d35d	312	* @}
<>	135:176b8275d35d	313	*/
<>	135:176b8275d35d	314
<>	135:176b8275d35d	315	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	135:176b8275d35d	316	* @{
<>	135:176b8275d35d	317	*/
<>	135:176b8275d35d	318	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
<>	135:176b8275d35d	319	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	135:176b8275d35d	320	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	135:176b8275d35d	321	/**
<>	135:176b8275d35d	322	* @}
<>	135:176b8275d35d	323	*/
<>	135:176b8275d35d	324
<>	135:176b8275d35d	325	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	135:176b8275d35d	326	* @{
<>	135:176b8275d35d	327	*/
<>	135:176b8275d35d	328	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
<>	135:176b8275d35d	329	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	135:176b8275d35d	330	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	135:176b8275d35d	331	/**
<>	135:176b8275d35d	332	* @}
<>	135:176b8275d35d	333	*/
<>	135:176b8275d35d	334
<>	135:176b8275d35d	335	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	135:176b8275d35d	336	* @{
<>	135:176b8275d35d	337	*/
<>	135:176b8275d35d	338	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
<>	135:176b8275d35d	339	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	135:176b8275d35d	340	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	135:176b8275d35d	341	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	135:176b8275d35d	342	/**
<>	135:176b8275d35d	343	* @}
<>	135:176b8275d35d	344	*/
<>	135:176b8275d35d	345
<>	135:176b8275d35d	346
<>	135:176b8275d35d	347	/**
<>	135:176b8275d35d	348	* @}
<>	135:176b8275d35d	349	*/
<>	135:176b8275d35d	350
<>	135:176b8275d35d	351	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	352	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	135:176b8275d35d	353	* @{
<>	135:176b8275d35d	354	*/
<>	135:176b8275d35d	355
<>	135:176b8275d35d	356	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	135:176b8275d35d	357	* @{
<>	135:176b8275d35d	358	*/
<>	135:176b8275d35d	359	/**
<>	135:176b8275d35d	360	* @brief Write a value in DMA register
<>	135:176b8275d35d	361	* @param __INSTANCE__ DMA Instance
<>	135:176b8275d35d	362	* @param __REG__ Register to be written
<>	135:176b8275d35d	363	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	364	* @retval None
<>	135:176b8275d35d	365	*/
<>	135:176b8275d35d	366	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	367
<>	135:176b8275d35d	368	/**
<>	135:176b8275d35d	369	* @brief Read a value in DMA register
<>	135:176b8275d35d	370	* @param __INSTANCE__ DMA Instance
<>	135:176b8275d35d	371	* @param __REG__ Register to be read
<>	135:176b8275d35d	372	* @retval Register value
<>	135:176b8275d35d	373	*/
<>	135:176b8275d35d	374	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	375	/**
<>	135:176b8275d35d	376	* @}
<>	135:176b8275d35d	377	*/
<>	135:176b8275d35d	378
<>	135:176b8275d35d	379	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	135:176b8275d35d	380	* @{
<>	135:176b8275d35d	381	*/
<>	135:176b8275d35d	382	/**
<>	135:176b8275d35d	383	* @brief Convert DMAx_Channely into DMAx
<>	135:176b8275d35d	384	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	135:176b8275d35d	385	* @retval DMAx
<>	135:176b8275d35d	386	*/
<>	135:176b8275d35d	387	#if defined(DMA2)
<>	135:176b8275d35d	388	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	389	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	135:176b8275d35d	390	#else
<>	135:176b8275d35d	391	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	135:176b8275d35d	392	#endif
<>	135:176b8275d35d	393
<>	135:176b8275d35d	394	/**
<>	135:176b8275d35d	395	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	135:176b8275d35d	396	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	135:176b8275d35d	397	* @retval LL_DMA_CHANNEL_y
<>	135:176b8275d35d	398	*/
<>	135:176b8275d35d	399	#if defined (DMA2)
<>	135:176b8275d35d	400	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	135:176b8275d35d	401	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	402	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	403	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	404	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	414	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	415	#else
<>	135:176b8275d35d	416	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	417	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	418	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	419	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	428	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	429	#endif
<>	135:176b8275d35d	430	#else
<>	135:176b8275d35d	431	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	432	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	433	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	434	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	435	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	436	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	438	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	439	#endif
<>	135:176b8275d35d	440
<>	135:176b8275d35d	441	/**
<>	135:176b8275d35d	442	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	135:176b8275d35d	443	* @param __DMA_INSTANCE__ DMAx
<>	135:176b8275d35d	444	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	135:176b8275d35d	445	* @retval DMAx_Channely
<>	135:176b8275d35d	446	*/
<>	135:176b8275d35d	447	#if defined (DMA2)
<>	135:176b8275d35d	448	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	135:176b8275d35d	449	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	450	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	451	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	135:176b8275d35d	452	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	135:176b8275d35d	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	135:176b8275d35d	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	135:176b8275d35d	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	135:176b8275d35d	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	135:176b8275d35d	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	135:176b8275d35d	463	DMA2_Channel7)
<>	135:176b8275d35d	464	#else
<>	135:176b8275d35d	465	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	466	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	135:176b8275d35d	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	135:176b8275d35d	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	135:176b8275d35d	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	135:176b8275d35d	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	135:176b8275d35d	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	477	DMA1_Channel7)
<>	135:176b8275d35d	478	#endif
<>	135:176b8275d35d	479	#else
<>	135:176b8275d35d	480	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	481	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	482	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	483	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	484	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	485	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	487	DMA1_Channel7)
<>	135:176b8275d35d	488	#endif
<>	135:176b8275d35d	489
<>	135:176b8275d35d	490	/**
<>	135:176b8275d35d	491	* @}
<>	135:176b8275d35d	492	*/
<>	135:176b8275d35d	493
<>	135:176b8275d35d	494	/**
<>	135:176b8275d35d	495	* @}
<>	135:176b8275d35d	496	*/
<>	135:176b8275d35d	497
<>	135:176b8275d35d	498	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	499	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	135:176b8275d35d	500	* @{
<>	135:176b8275d35d	501	*/
<>	135:176b8275d35d	502
<>	135:176b8275d35d	503	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	135:176b8275d35d	504	* @{
<>	135:176b8275d35d	505	*/
<>	135:176b8275d35d	506	/**
<>	135:176b8275d35d	507	* @brief Enable DMA channel.
<>	135:176b8275d35d	508	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	135:176b8275d35d	509	* @param DMAx DMAx Instance
<>	135:176b8275d35d	510	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	511	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	512	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	513	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	514	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	515	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	516	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	517	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	518	* @retval None
<>	135:176b8275d35d	519	*/
<>	135:176b8275d35d	520	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	521	{
<>	135:176b8275d35d	522	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	135:176b8275d35d	523	}
<>	135:176b8275d35d	524
<>	135:176b8275d35d	525	/**
<>	135:176b8275d35d	526	* @brief Disable DMA channel.
<>	135:176b8275d35d	527	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	135:176b8275d35d	528	* @param DMAx DMAx Instance
<>	135:176b8275d35d	529	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	530	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	531	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	532	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	533	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	534	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	535	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	536	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	537	* @retval None
<>	135:176b8275d35d	538	*/
<>	135:176b8275d35d	539	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	540	{
<>	135:176b8275d35d	541	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	135:176b8275d35d	542	}
<>	135:176b8275d35d	543
<>	135:176b8275d35d	544	/**
<>	135:176b8275d35d	545	* @brief Check if DMA channel is enabled or disabled.
<>	135:176b8275d35d	546	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	135:176b8275d35d	547	* @param DMAx DMAx Instance
<>	135:176b8275d35d	548	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	549	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	550	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	551	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	552	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	553	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	554	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	555	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	556	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	557	*/
<>	135:176b8275d35d	558	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	559	{
<>	135:176b8275d35d	560	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	561	DMA_CCR_EN) == (DMA_CCR_EN));
<>	135:176b8275d35d	562	}
<>	135:176b8275d35d	563
<>	135:176b8275d35d	564	/**
<>	135:176b8275d35d	565	* @brief Configure all parameters link to DMA transfer.
<>	135:176b8275d35d	566	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	567	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	568	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	569	* CCR PINC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	570	* CCR MINC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	571	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	572	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	573	* CCR PL LL_DMA_ConfigTransfer
<>	135:176b8275d35d	574	* @param DMAx DMAx Instance
<>	135:176b8275d35d	575	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	576	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	577	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	578	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	579	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	580	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	581	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	582	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	583	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	584	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	585	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	586	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	587	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	588	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	589	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	590	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	591	* @retval None
<>	135:176b8275d35d	592	*/
<>	135:176b8275d35d	593	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	135:176b8275d35d	594	{
<>	135:176b8275d35d	595	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	596	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	135:176b8275d35d	597	Configuration);
<>	135:176b8275d35d	598	}
<>	135:176b8275d35d	599
<>	135:176b8275d35d	600	/**
<>	135:176b8275d35d	601	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	135:176b8275d35d	602	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	135:176b8275d35d	603	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	135:176b8275d35d	604	* @param DMAx DMAx Instance
<>	135:176b8275d35d	605	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	606	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	607	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	608	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	609	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	610	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	611	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	612	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	613	* @param Direction This parameter can be one of the following values:
<>	135:176b8275d35d	614	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	615	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	616	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	617	* @retval None
<>	135:176b8275d35d	618	*/
<>	135:176b8275d35d	619	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	135:176b8275d35d	620	{
<>	135:176b8275d35d	621	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	622	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	135:176b8275d35d	623	}
<>	135:176b8275d35d	624
<>	135:176b8275d35d	625	/**
<>	135:176b8275d35d	626	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	135:176b8275d35d	627	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	135:176b8275d35d	628	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	135:176b8275d35d	629	* @param DMAx DMAx Instance
<>	135:176b8275d35d	630	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	631	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	632	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	633	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	634	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	635	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	636	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	637	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	638	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	639	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	640	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	641	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	642	*/
<>	135:176b8275d35d	643	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	644	{
<>	135:176b8275d35d	645	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	646	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	135:176b8275d35d	647	}
<>	135:176b8275d35d	648
<>	135:176b8275d35d	649	/**
<>	135:176b8275d35d	650	* @brief Set DMA mode circular or normal.
<>	135:176b8275d35d	651	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	135:176b8275d35d	652	* data transfer is configured on the selected Channel.
<>	135:176b8275d35d	653	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	135:176b8275d35d	654	* @param DMAx DMAx Instance
<>	135:176b8275d35d	655	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	656	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	657	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	658	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	659	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	660	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	661	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	662	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	663	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	664	* @arg @ref LL_DMA_MODE_NORMAL
<>	135:176b8275d35d	665	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	666	* @retval None
<>	135:176b8275d35d	667	*/
<>	135:176b8275d35d	668	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	135:176b8275d35d	669	{
<>	135:176b8275d35d	670	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	135:176b8275d35d	671	Mode);
<>	135:176b8275d35d	672	}
<>	135:176b8275d35d	673
<>	135:176b8275d35d	674	/**
<>	135:176b8275d35d	675	* @brief Get DMA mode circular or normal.
<>	135:176b8275d35d	676	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	135:176b8275d35d	677	* @param DMAx DMAx Instance
<>	135:176b8275d35d	678	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	679	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	680	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	681	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	682	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	683	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	684	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	685	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	686	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	687	* @arg @ref LL_DMA_MODE_NORMAL
<>	135:176b8275d35d	688	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	689	*/
<>	135:176b8275d35d	690	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	691	{
<>	135:176b8275d35d	692	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	693	DMA_CCR_CIRC));
<>	135:176b8275d35d	694	}
<>	135:176b8275d35d	695
<>	135:176b8275d35d	696	/**
<>	135:176b8275d35d	697	* @brief Set Peripheral increment mode.
<>	135:176b8275d35d	698	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	135:176b8275d35d	699	* @param DMAx DMAx Instance
<>	135:176b8275d35d	700	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	701	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	702	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	703	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	704	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	705	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	706	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	707	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	708	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	135:176b8275d35d	709	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	135:176b8275d35d	710	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	711	* @retval None
<>	135:176b8275d35d	712	*/
<>	135:176b8275d35d	713	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	135:176b8275d35d	714	{
<>	135:176b8275d35d	715	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	135:176b8275d35d	716	PeriphOrM2MSrcIncMode);
<>	135:176b8275d35d	717	}
<>	135:176b8275d35d	718
<>	135:176b8275d35d	719	/**
<>	135:176b8275d35d	720	* @brief Get Peripheral increment mode.
<>	135:176b8275d35d	721	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	135:176b8275d35d	722	* @param DMAx DMAx Instance
<>	135:176b8275d35d	723	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	724	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	725	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	726	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	727	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	728	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	729	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	730	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	731	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	732	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	135:176b8275d35d	733	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	734	*/
<>	135:176b8275d35d	735	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	736	{
<>	135:176b8275d35d	737	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	738	DMA_CCR_PINC));
<>	135:176b8275d35d	739	}
<>	135:176b8275d35d	740
<>	135:176b8275d35d	741	/**
<>	135:176b8275d35d	742	* @brief Set Memory increment mode.
<>	135:176b8275d35d	743	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	135:176b8275d35d	744	* @param DMAx DMAx Instance
<>	135:176b8275d35d	745	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	746	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	747	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	748	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	749	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	750	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	751	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	752	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	753	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	135:176b8275d35d	754	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	135:176b8275d35d	755	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	756	* @retval None
<>	135:176b8275d35d	757	*/
<>	135:176b8275d35d	758	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	135:176b8275d35d	759	{
<>	135:176b8275d35d	760	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	135:176b8275d35d	761	MemoryOrM2MDstIncMode);
<>	135:176b8275d35d	762	}
<>	135:176b8275d35d	763
<>	135:176b8275d35d	764	/**
<>	135:176b8275d35d	765	* @brief Get Memory increment mode.
<>	135:176b8275d35d	766	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	135:176b8275d35d	767	* @param DMAx DMAx Instance
<>	135:176b8275d35d	768	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	769	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	770	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	771	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	772	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	773	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	774	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	775	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	776	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	777	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	135:176b8275d35d	778	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	779	*/
<>	135:176b8275d35d	780	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	781	{
<>	135:176b8275d35d	782	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	783	DMA_CCR_MINC));
<>	135:176b8275d35d	784	}
<>	135:176b8275d35d	785
<>	135:176b8275d35d	786	/**
<>	135:176b8275d35d	787	* @brief Set Peripheral size.
<>	135:176b8275d35d	788	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	135:176b8275d35d	789	* @param DMAx DMAx Instance
<>	135:176b8275d35d	790	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	791	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	792	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	793	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	794	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	795	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	796	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	797	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	798	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	135:176b8275d35d	799	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	135:176b8275d35d	800	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	135:176b8275d35d	801	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	802	* @retval None
<>	135:176b8275d35d	803	*/
<>	135:176b8275d35d	804	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	135:176b8275d35d	805	{
<>	135:176b8275d35d	806	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	135:176b8275d35d	807	PeriphOrM2MSrcDataSize);
<>	135:176b8275d35d	808	}
<>	135:176b8275d35d	809
<>	135:176b8275d35d	810	/**
<>	135:176b8275d35d	811	* @brief Get Peripheral size.
<>	135:176b8275d35d	812	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	135:176b8275d35d	813	* @param DMAx DMAx Instance
<>	135:176b8275d35d	814	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	815	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	816	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	817	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	818	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	819	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	820	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	821	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	822	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	823	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	135:176b8275d35d	824	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	135:176b8275d35d	825	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	826	*/
<>	135:176b8275d35d	827	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	828	{
<>	135:176b8275d35d	829	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	830	DMA_CCR_PSIZE));
<>	135:176b8275d35d	831	}
<>	135:176b8275d35d	832
<>	135:176b8275d35d	833	/**
<>	135:176b8275d35d	834	* @brief Set Memory size.
<>	135:176b8275d35d	835	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	135:176b8275d35d	836	* @param DMAx DMAx Instance
<>	135:176b8275d35d	837	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	838	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	839	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	840	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	841	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	842	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	843	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	844	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	845	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	135:176b8275d35d	846	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	135:176b8275d35d	847	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	135:176b8275d35d	848	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	849	* @retval None
<>	135:176b8275d35d	850	*/
<>	135:176b8275d35d	851	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	135:176b8275d35d	852	{
<>	135:176b8275d35d	853	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	135:176b8275d35d	854	MemoryOrM2MDstDataSize);
<>	135:176b8275d35d	855	}
<>	135:176b8275d35d	856
<>	135:176b8275d35d	857	/**
<>	135:176b8275d35d	858	* @brief Get Memory size.
<>	135:176b8275d35d	859	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	135:176b8275d35d	860	* @param DMAx DMAx Instance
<>	135:176b8275d35d	861	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	862	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	863	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	864	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	865	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	866	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	867	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	868	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	869	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	870	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	135:176b8275d35d	871	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	135:176b8275d35d	872	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	873	*/
<>	135:176b8275d35d	874	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	875	{
<>	135:176b8275d35d	876	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	877	DMA_CCR_MSIZE));
<>	135:176b8275d35d	878	}
<>	135:176b8275d35d	879
<>	135:176b8275d35d	880	/**
<>	135:176b8275d35d	881	* @brief Set Channel priority level.
<>	135:176b8275d35d	882	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	135:176b8275d35d	883	* @param DMAx DMAx Instance
<>	135:176b8275d35d	884	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	885	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	886	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	887	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	888	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	889	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	890	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	891	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	892	* @param Priority This parameter can be one of the following values:
<>	135:176b8275d35d	893	* @arg @ref LL_DMA_PRIORITY_LOW
<>	135:176b8275d35d	894	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	135:176b8275d35d	895	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	135:176b8275d35d	896	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	897	* @retval None
<>	135:176b8275d35d	898	*/
<>	135:176b8275d35d	899	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	135:176b8275d35d	900	{
<>	135:176b8275d35d	901	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	135:176b8275d35d	902	Priority);
<>	135:176b8275d35d	903	}
<>	135:176b8275d35d	904
<>	135:176b8275d35d	905	/**
<>	135:176b8275d35d	906	* @brief Get Channel priority level.
<>	135:176b8275d35d	907	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	135:176b8275d35d	908	* @param DMAx DMAx Instance
<>	135:176b8275d35d	909	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	910	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	911	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	912	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	913	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	914	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	915	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	916	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	917	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	918	* @arg @ref LL_DMA_PRIORITY_LOW
<>	135:176b8275d35d	919	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	135:176b8275d35d	920	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	135:176b8275d35d	921	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	922	*/
<>	135:176b8275d35d	923	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	924	{
<>	135:176b8275d35d	925	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	926	DMA_CCR_PL));
<>	135:176b8275d35d	927	}
<>	135:176b8275d35d	928
<>	135:176b8275d35d	929	/**
<>	135:176b8275d35d	930	* @brief Set Number of data to transfer.
<>	135:176b8275d35d	931	* @note This action has no effect if
<>	135:176b8275d35d	932	* channel is enabled.
<>	135:176b8275d35d	933	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	135:176b8275d35d	934	* @param DMAx DMAx Instance
<>	135:176b8275d35d	935	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	936	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	937	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	938	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	939	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	940	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	941	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	942	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	943	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	135:176b8275d35d	944	* @retval None
<>	135:176b8275d35d	945	*/
<>	135:176b8275d35d	946	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	135:176b8275d35d	947	{
<>	135:176b8275d35d	948	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	135:176b8275d35d	949	DMA_CNDTR_NDT, NbData);
<>	135:176b8275d35d	950	}
<>	135:176b8275d35d	951
<>	135:176b8275d35d	952	/**
<>	135:176b8275d35d	953	* @brief Get Number of data to transfer.
<>	135:176b8275d35d	954	* @note Once the channel is enabled, the return value indicate the
<>	135:176b8275d35d	955	* remaining bytes to be transmitted.
<>	135:176b8275d35d	956	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	135:176b8275d35d	957	* @param DMAx DMAx Instance
<>	135:176b8275d35d	958	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	959	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	960	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	961	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	962	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	963	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	964	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	965	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	966	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	967	*/
<>	135:176b8275d35d	968	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	969	{
<>	135:176b8275d35d	970	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	135:176b8275d35d	971	DMA_CNDTR_NDT));
<>	135:176b8275d35d	972	}
<>	135:176b8275d35d	973
<>	135:176b8275d35d	974	/**
<>	135:176b8275d35d	975	* @brief Configure the Source and Destination addresses.
<>	135:176b8275d35d	976	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<>	135:176b8275d35d	977	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	135:176b8275d35d	978	* CMAR MA LL_DMA_ConfigAddresses
<>	135:176b8275d35d	979	* @param DMAx DMAx Instance
<>	135:176b8275d35d	980	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	981	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	982	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	983	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	984	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	985	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	986	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	987	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	988	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	989	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	990	* @param Direction This parameter can be one of the following values:
<>	135:176b8275d35d	991	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	992	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	993	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	994	* @retval None
<>	135:176b8275d35d	995	*/
<>	135:176b8275d35d	996	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	135:176b8275d35d	997	uint32_t DstAddress, uint32_t Direction)
<>	135:176b8275d35d	998	{
<>	135:176b8275d35d	999	/* Direction Memory to Periph */
<>	135:176b8275d35d	1000	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	135:176b8275d35d	1001	{
<>	135:176b8275d35d	1002	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	135:176b8275d35d	1003	SrcAddress);
<>	135:176b8275d35d	1004	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	135:176b8275d35d	1005	DstAddress);
<>	135:176b8275d35d	1006	}
<>	135:176b8275d35d	1007	/* Direction Periph to Memory and Memory to Memory */
<>	135:176b8275d35d	1008	else
<>	135:176b8275d35d	1009	{
<>	135:176b8275d35d	1010	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	135:176b8275d35d	1011	SrcAddress);
<>	135:176b8275d35d	1012	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	135:176b8275d35d	1013	DstAddress);
<>	135:176b8275d35d	1014	}
<>	135:176b8275d35d	1015	}
<>	135:176b8275d35d	1016
<>	135:176b8275d35d	1017	/**
<>	135:176b8275d35d	1018	* @brief Set the Memory address.
<>	135:176b8275d35d	1019	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1020	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	135:176b8275d35d	1021	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1022	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1023	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1024	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1025	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1026	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1027	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1028	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1029	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1030	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1031	* @retval None
<>	135:176b8275d35d	1032	*/
<>	135:176b8275d35d	1033	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1034	{
<>	135:176b8275d35d	1035	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	135:176b8275d35d	1036	MemoryAddress);
<>	135:176b8275d35d	1037	}
<>	135:176b8275d35d	1038
<>	135:176b8275d35d	1039	/**
<>	135:176b8275d35d	1040	* @brief Set the Peripheral address.
<>	135:176b8275d35d	1041	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1042	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	135:176b8275d35d	1043	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1044	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1045	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1046	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1047	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1048	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1049	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1050	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1051	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1052	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1053	* @retval None
<>	135:176b8275d35d	1054	*/
<>	135:176b8275d35d	1055	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	135:176b8275d35d	1056	{
<>	135:176b8275d35d	1057	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	135:176b8275d35d	1058	PeriphAddress);
<>	135:176b8275d35d	1059	}
<>	135:176b8275d35d	1060
<>	135:176b8275d35d	1061	/**
<>	135:176b8275d35d	1062	* @brief Get Memory address.
<>	135:176b8275d35d	1063	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1064	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	135:176b8275d35d	1065	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1066	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1067	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1068	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1069	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1070	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1071	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1072	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1073	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1074	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1075	*/
<>	135:176b8275d35d	1076	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1077	{
<>	135:176b8275d35d	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	135:176b8275d35d	1079	DMA_CMAR_MA));
<>	135:176b8275d35d	1080	}
<>	135:176b8275d35d	1081
<>	135:176b8275d35d	1082	/**
<>	135:176b8275d35d	1083	* @brief Get Peripheral address.
<>	135:176b8275d35d	1084	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1085	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	135:176b8275d35d	1086	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1087	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1088	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1089	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1090	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1091	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1092	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1093	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1094	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1095	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1096	*/
<>	135:176b8275d35d	1097	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1098	{
<>	135:176b8275d35d	1099	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	135:176b8275d35d	1100	DMA_CPAR_PA));
<>	135:176b8275d35d	1101	}
<>	135:176b8275d35d	1102
<>	135:176b8275d35d	1103	/**
<>	135:176b8275d35d	1104	* @brief Set the Memory to Memory Source address.
<>	135:176b8275d35d	1105	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1106	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	135:176b8275d35d	1107	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1108	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1109	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1110	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1111	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1112	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1113	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1114	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1115	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1116	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1117	* @retval None
<>	135:176b8275d35d	1118	*/
<>	135:176b8275d35d	1119	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1120	{
<>	135:176b8275d35d	1121	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	135:176b8275d35d	1122	MemoryAddress);
<>	135:176b8275d35d	1123	}
<>	135:176b8275d35d	1124
<>	135:176b8275d35d	1125	/**
<>	135:176b8275d35d	1126	* @brief Set the Memory to Memory Destination address.
<>	135:176b8275d35d	1127	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1128	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	135:176b8275d35d	1129	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1130	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1131	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1132	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1133	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1134	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1135	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1136	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1137	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1138	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1139	* @retval None
<>	135:176b8275d35d	1140	*/
<>	135:176b8275d35d	1141	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1142	{
<>	135:176b8275d35d	1143	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	135:176b8275d35d	1144	MemoryAddress);
<>	135:176b8275d35d	1145	}
<>	135:176b8275d35d	1146
<>	135:176b8275d35d	1147	/**
<>	135:176b8275d35d	1148	* @brief Get the Memory to Memory Source address.
<>	135:176b8275d35d	1149	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1150	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	135:176b8275d35d	1151	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1152	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1153	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1154	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1155	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1156	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1157	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1158	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1159	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1160	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1161	*/
<>	135:176b8275d35d	1162	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1163	{
<>	135:176b8275d35d	1164	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	135:176b8275d35d	1165	DMA_CPAR_PA));
<>	135:176b8275d35d	1166	}
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168	/**
<>	135:176b8275d35d	1169	* @brief Get the Memory to Memory Destination address.
<>	135:176b8275d35d	1170	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1171	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	135:176b8275d35d	1172	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1173	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1174	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1175	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1176	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1177	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1178	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1179	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1180	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1181	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1182	*/
<>	135:176b8275d35d	1183	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1184	{
<>	135:176b8275d35d	1185	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	135:176b8275d35d	1186	DMA_CMAR_MA));
<>	135:176b8275d35d	1187	}
<>	135:176b8275d35d	1188
<>	135:176b8275d35d	1189
<>	135:176b8275d35d	1190	/**
<>	135:176b8275d35d	1191	* @}
<>	135:176b8275d35d	1192	*/
<>	135:176b8275d35d	1193
<>	135:176b8275d35d	1194	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	135:176b8275d35d	1195	* @{
<>	135:176b8275d35d	1196	*/
<>	135:176b8275d35d	1197
<>	135:176b8275d35d	1198	/**
<>	135:176b8275d35d	1199	* @brief Get Channel 1 global interrupt flag.
<>	135:176b8275d35d	1200	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	135:176b8275d35d	1201	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1202	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1203	*/
<>	135:176b8275d35d	1204	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1205	{
<>	135:176b8275d35d	1206	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	135:176b8275d35d	1207	}
<>	135:176b8275d35d	1208
<>	135:176b8275d35d	1209	/**
<>	135:176b8275d35d	1210	* @brief Get Channel 2 global interrupt flag.
<>	135:176b8275d35d	1211	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	135:176b8275d35d	1212	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1213	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1214	*/
<>	135:176b8275d35d	1215	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1216	{
<>	135:176b8275d35d	1217	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	135:176b8275d35d	1218	}
<>	135:176b8275d35d	1219
<>	135:176b8275d35d	1220	/**
<>	135:176b8275d35d	1221	* @brief Get Channel 3 global interrupt flag.
<>	135:176b8275d35d	1222	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	135:176b8275d35d	1223	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1224	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1225	*/
<>	135:176b8275d35d	1226	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1227	{
<>	135:176b8275d35d	1228	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	135:176b8275d35d	1229	}
<>	135:176b8275d35d	1230
<>	135:176b8275d35d	1231	/**
<>	135:176b8275d35d	1232	* @brief Get Channel 4 global interrupt flag.
<>	135:176b8275d35d	1233	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	135:176b8275d35d	1234	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1235	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1236	*/
<>	135:176b8275d35d	1237	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1238	{
<>	135:176b8275d35d	1239	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	135:176b8275d35d	1240	}
<>	135:176b8275d35d	1241
<>	135:176b8275d35d	1242	/**
<>	135:176b8275d35d	1243	* @brief Get Channel 5 global interrupt flag.
<>	135:176b8275d35d	1244	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	135:176b8275d35d	1245	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1246	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1247	*/
<>	135:176b8275d35d	1248	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1249	{
<>	135:176b8275d35d	1250	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	135:176b8275d35d	1251	}
<>	135:176b8275d35d	1252
<>	135:176b8275d35d	1253	/**
<>	135:176b8275d35d	1254	* @brief Get Channel 6 global interrupt flag.
<>	135:176b8275d35d	1255	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	135:176b8275d35d	1256	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1257	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1258	*/
<>	135:176b8275d35d	1259	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1260	{
<>	135:176b8275d35d	1261	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	135:176b8275d35d	1262	}
<>	135:176b8275d35d	1263
<>	135:176b8275d35d	1264	/**
<>	135:176b8275d35d	1265	* @brief Get Channel 7 global interrupt flag.
<>	135:176b8275d35d	1266	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	135:176b8275d35d	1267	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1268	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1269	*/
<>	135:176b8275d35d	1270	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1271	{
<>	135:176b8275d35d	1272	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	135:176b8275d35d	1273	}
<>	135:176b8275d35d	1274
<>	135:176b8275d35d	1275	/**
<>	135:176b8275d35d	1276	* @brief Get Channel 1 transfer complete flag.
<>	135:176b8275d35d	1277	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	135:176b8275d35d	1278	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1279	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1280	*/
<>	135:176b8275d35d	1281	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1282	{
<>	135:176b8275d35d	1283	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	135:176b8275d35d	1284	}
<>	135:176b8275d35d	1285
<>	135:176b8275d35d	1286	/**
<>	135:176b8275d35d	1287	* @brief Get Channel 2 transfer complete flag.
<>	135:176b8275d35d	1288	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	135:176b8275d35d	1289	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1290	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1291	*/
<>	135:176b8275d35d	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1293	{
<>	135:176b8275d35d	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	135:176b8275d35d	1295	}
<>	135:176b8275d35d	1296
<>	135:176b8275d35d	1297	/**
<>	135:176b8275d35d	1298	* @brief Get Channel 3 transfer complete flag.
<>	135:176b8275d35d	1299	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	135:176b8275d35d	1300	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1301	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1302	*/
<>	135:176b8275d35d	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1304	{
<>	135:176b8275d35d	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	135:176b8275d35d	1306	}
<>	135:176b8275d35d	1307
<>	135:176b8275d35d	1308	/**
<>	135:176b8275d35d	1309	* @brief Get Channel 4 transfer complete flag.
<>	135:176b8275d35d	1310	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	135:176b8275d35d	1311	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1312	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1313	*/
<>	135:176b8275d35d	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1315	{
<>	135:176b8275d35d	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	135:176b8275d35d	1317	}
<>	135:176b8275d35d	1318
<>	135:176b8275d35d	1319	/**
<>	135:176b8275d35d	1320	* @brief Get Channel 5 transfer complete flag.
<>	135:176b8275d35d	1321	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	135:176b8275d35d	1322	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1323	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1324	*/
<>	135:176b8275d35d	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1326	{
<>	135:176b8275d35d	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	135:176b8275d35d	1328	}
<>	135:176b8275d35d	1329
<>	135:176b8275d35d	1330	/**
<>	135:176b8275d35d	1331	* @brief Get Channel 6 transfer complete flag.
<>	135:176b8275d35d	1332	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	135:176b8275d35d	1333	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1334	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1335	*/
<>	135:176b8275d35d	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1337	{
<>	135:176b8275d35d	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	135:176b8275d35d	1339	}
<>	135:176b8275d35d	1340
<>	135:176b8275d35d	1341	/**
<>	135:176b8275d35d	1342	* @brief Get Channel 7 transfer complete flag.
<>	135:176b8275d35d	1343	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	135:176b8275d35d	1344	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1345	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1346	*/
<>	135:176b8275d35d	1347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1348	{
<>	135:176b8275d35d	1349	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	135:176b8275d35d	1350	}
<>	135:176b8275d35d	1351
<>	135:176b8275d35d	1352	/**
<>	135:176b8275d35d	1353	* @brief Get Channel 1 half transfer flag.
<>	135:176b8275d35d	1354	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	135:176b8275d35d	1355	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1356	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1357	*/
<>	135:176b8275d35d	1358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1359	{
<>	135:176b8275d35d	1360	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	135:176b8275d35d	1361	}
<>	135:176b8275d35d	1362
<>	135:176b8275d35d	1363	/**
<>	135:176b8275d35d	1364	* @brief Get Channel 2 half transfer flag.
<>	135:176b8275d35d	1365	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	135:176b8275d35d	1366	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1367	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1368	*/
<>	135:176b8275d35d	1369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1370	{
<>	135:176b8275d35d	1371	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	135:176b8275d35d	1372	}
<>	135:176b8275d35d	1373
<>	135:176b8275d35d	1374	/**
<>	135:176b8275d35d	1375	* @brief Get Channel 3 half transfer flag.
<>	135:176b8275d35d	1376	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	135:176b8275d35d	1377	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1378	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1379	*/
<>	135:176b8275d35d	1380	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1381	{
<>	135:176b8275d35d	1382	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	135:176b8275d35d	1383	}
<>	135:176b8275d35d	1384
<>	135:176b8275d35d	1385	/**
<>	135:176b8275d35d	1386	* @brief Get Channel 4 half transfer flag.
<>	135:176b8275d35d	1387	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	135:176b8275d35d	1388	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1389	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1390	*/
<>	135:176b8275d35d	1391	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1392	{
<>	135:176b8275d35d	1393	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	135:176b8275d35d	1394	}
<>	135:176b8275d35d	1395
<>	135:176b8275d35d	1396	/**
<>	135:176b8275d35d	1397	* @brief Get Channel 5 half transfer flag.
<>	135:176b8275d35d	1398	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	135:176b8275d35d	1399	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1400	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1401	*/
<>	135:176b8275d35d	1402	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1403	{
<>	135:176b8275d35d	1404	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	135:176b8275d35d	1405	}
<>	135:176b8275d35d	1406
<>	135:176b8275d35d	1407	/**
<>	135:176b8275d35d	1408	* @brief Get Channel 6 half transfer flag.
<>	135:176b8275d35d	1409	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	135:176b8275d35d	1410	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1411	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1412	*/
<>	135:176b8275d35d	1413	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1414	{
<>	135:176b8275d35d	1415	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	135:176b8275d35d	1416	}
<>	135:176b8275d35d	1417
<>	135:176b8275d35d	1418	/**
<>	135:176b8275d35d	1419	* @brief Get Channel 7 half transfer flag.
<>	135:176b8275d35d	1420	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	135:176b8275d35d	1421	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1422	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1423	*/
<>	135:176b8275d35d	1424	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1425	{
<>	135:176b8275d35d	1426	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	135:176b8275d35d	1427	}
<>	135:176b8275d35d	1428
<>	135:176b8275d35d	1429	/**
<>	135:176b8275d35d	1430	* @brief Get Channel 1 transfer error flag.
<>	135:176b8275d35d	1431	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	135:176b8275d35d	1432	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1433	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1434	*/
<>	135:176b8275d35d	1435	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1436	{
<>	135:176b8275d35d	1437	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	135:176b8275d35d	1438	}
<>	135:176b8275d35d	1439
<>	135:176b8275d35d	1440	/**
<>	135:176b8275d35d	1441	* @brief Get Channel 2 transfer error flag.
<>	135:176b8275d35d	1442	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	135:176b8275d35d	1443	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1444	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1445	*/
<>	135:176b8275d35d	1446	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1447	{
<>	135:176b8275d35d	1448	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	135:176b8275d35d	1449	}
<>	135:176b8275d35d	1450
<>	135:176b8275d35d	1451	/**
<>	135:176b8275d35d	1452	* @brief Get Channel 3 transfer error flag.
<>	135:176b8275d35d	1453	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	135:176b8275d35d	1454	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1455	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1456	*/
<>	135:176b8275d35d	1457	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1458	{
<>	135:176b8275d35d	1459	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	135:176b8275d35d	1460	}
<>	135:176b8275d35d	1461
<>	135:176b8275d35d	1462	/**
<>	135:176b8275d35d	1463	* @brief Get Channel 4 transfer error flag.
<>	135:176b8275d35d	1464	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	135:176b8275d35d	1465	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1466	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1467	*/
<>	135:176b8275d35d	1468	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1469	{
<>	135:176b8275d35d	1470	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	135:176b8275d35d	1471	}
<>	135:176b8275d35d	1472
<>	135:176b8275d35d	1473	/**
<>	135:176b8275d35d	1474	* @brief Get Channel 5 transfer error flag.
<>	135:176b8275d35d	1475	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	135:176b8275d35d	1476	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1477	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1478	*/
<>	135:176b8275d35d	1479	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1480	{
<>	135:176b8275d35d	1481	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	135:176b8275d35d	1482	}
<>	135:176b8275d35d	1483
<>	135:176b8275d35d	1484	/**
<>	135:176b8275d35d	1485	* @brief Get Channel 6 transfer error flag.
<>	135:176b8275d35d	1486	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	135:176b8275d35d	1487	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1488	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1489	*/
<>	135:176b8275d35d	1490	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1491	{
<>	135:176b8275d35d	1492	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	135:176b8275d35d	1493	}
<>	135:176b8275d35d	1494
<>	135:176b8275d35d	1495	/**
<>	135:176b8275d35d	1496	* @brief Get Channel 7 transfer error flag.
<>	135:176b8275d35d	1497	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	135:176b8275d35d	1498	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1499	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1500	*/
<>	135:176b8275d35d	1501	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1502	{
<>	135:176b8275d35d	1503	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	135:176b8275d35d	1504	}
<>	135:176b8275d35d	1505
<>	135:176b8275d35d	1506	/**
<>	135:176b8275d35d	1507	* @brief Clear Channel 1 global interrupt flag.
<>	135:176b8275d35d	1508	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	135:176b8275d35d	1509	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1510	* @retval None
<>	135:176b8275d35d	1511	*/
<>	135:176b8275d35d	1512	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1513	{
<>	135:176b8275d35d	1514	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	135:176b8275d35d	1515	}
<>	135:176b8275d35d	1516
<>	135:176b8275d35d	1517	/**
<>	135:176b8275d35d	1518	* @brief Clear Channel 2 global interrupt flag.
<>	135:176b8275d35d	1519	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	135:176b8275d35d	1520	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1521	* @retval None
<>	135:176b8275d35d	1522	*/
<>	135:176b8275d35d	1523	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1524	{
<>	135:176b8275d35d	1525	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	135:176b8275d35d	1526	}
<>	135:176b8275d35d	1527
<>	135:176b8275d35d	1528	/**
<>	135:176b8275d35d	1529	* @brief Clear Channel 3 global interrupt flag.
<>	135:176b8275d35d	1530	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	135:176b8275d35d	1531	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1532	* @retval None
<>	135:176b8275d35d	1533	*/
<>	135:176b8275d35d	1534	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1535	{
<>	135:176b8275d35d	1536	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	135:176b8275d35d	1537	}
<>	135:176b8275d35d	1538
<>	135:176b8275d35d	1539	/**
<>	135:176b8275d35d	1540	* @brief Clear Channel 4 global interrupt flag.
<>	135:176b8275d35d	1541	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	135:176b8275d35d	1542	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1543	* @retval None
<>	135:176b8275d35d	1544	*/
<>	135:176b8275d35d	1545	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1546	{
<>	135:176b8275d35d	1547	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	135:176b8275d35d	1548	}
<>	135:176b8275d35d	1549
<>	135:176b8275d35d	1550	/**
<>	135:176b8275d35d	1551	* @brief Clear Channel 5 global interrupt flag.
<>	135:176b8275d35d	1552	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	135:176b8275d35d	1553	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1554	* @retval None
<>	135:176b8275d35d	1555	*/
<>	135:176b8275d35d	1556	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1557	{
<>	135:176b8275d35d	1558	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	135:176b8275d35d	1559	}
<>	135:176b8275d35d	1560
<>	135:176b8275d35d	1561	/**
<>	135:176b8275d35d	1562	* @brief Clear Channel 6 global interrupt flag.
<>	135:176b8275d35d	1563	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	135:176b8275d35d	1564	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1565	* @retval None
<>	135:176b8275d35d	1566	*/
<>	135:176b8275d35d	1567	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1568	{
<>	135:176b8275d35d	1569	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	135:176b8275d35d	1570	}
<>	135:176b8275d35d	1571
<>	135:176b8275d35d	1572	/**
<>	135:176b8275d35d	1573	* @brief Clear Channel 7 global interrupt flag.
<>	135:176b8275d35d	1574	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	135:176b8275d35d	1575	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1576	* @retval None
<>	135:176b8275d35d	1577	*/
<>	135:176b8275d35d	1578	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1579	{
<>	135:176b8275d35d	1580	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	135:176b8275d35d	1581	}
<>	135:176b8275d35d	1582
<>	135:176b8275d35d	1583	/**
<>	135:176b8275d35d	1584	* @brief Clear Channel 1 transfer complete flag.
<>	135:176b8275d35d	1585	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	135:176b8275d35d	1586	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1587	* @retval None
<>	135:176b8275d35d	1588	*/
<>	135:176b8275d35d	1589	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1590	{
<>	135:176b8275d35d	1591	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	135:176b8275d35d	1592	}
<>	135:176b8275d35d	1593
<>	135:176b8275d35d	1594	/**
<>	135:176b8275d35d	1595	* @brief Clear Channel 2 transfer complete flag.
<>	135:176b8275d35d	1596	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	135:176b8275d35d	1597	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1598	* @retval None
<>	135:176b8275d35d	1599	*/
<>	135:176b8275d35d	1600	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1601	{
<>	135:176b8275d35d	1602	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	135:176b8275d35d	1603	}
<>	135:176b8275d35d	1604
<>	135:176b8275d35d	1605	/**
<>	135:176b8275d35d	1606	* @brief Clear Channel 3 transfer complete flag.
<>	135:176b8275d35d	1607	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	135:176b8275d35d	1608	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1609	* @retval None
<>	135:176b8275d35d	1610	*/
<>	135:176b8275d35d	1611	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1612	{
<>	135:176b8275d35d	1613	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	135:176b8275d35d	1614	}
<>	135:176b8275d35d	1615
<>	135:176b8275d35d	1616	/**
<>	135:176b8275d35d	1617	* @brief Clear Channel 4 transfer complete flag.
<>	135:176b8275d35d	1618	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	135:176b8275d35d	1619	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1620	* @retval None
<>	135:176b8275d35d	1621	*/
<>	135:176b8275d35d	1622	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1623	{
<>	135:176b8275d35d	1624	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	135:176b8275d35d	1625	}
<>	135:176b8275d35d	1626
<>	135:176b8275d35d	1627	/**
<>	135:176b8275d35d	1628	* @brief Clear Channel 5 transfer complete flag.
<>	135:176b8275d35d	1629	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	135:176b8275d35d	1630	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1631	* @retval None
<>	135:176b8275d35d	1632	*/
<>	135:176b8275d35d	1633	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1634	{
<>	135:176b8275d35d	1635	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	135:176b8275d35d	1636	}
<>	135:176b8275d35d	1637
<>	135:176b8275d35d	1638	/**
<>	135:176b8275d35d	1639	* @brief Clear Channel 6 transfer complete flag.
<>	135:176b8275d35d	1640	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	135:176b8275d35d	1641	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1642	* @retval None
<>	135:176b8275d35d	1643	*/
<>	135:176b8275d35d	1644	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1645	{
<>	135:176b8275d35d	1646	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	135:176b8275d35d	1647	}
<>	135:176b8275d35d	1648
<>	135:176b8275d35d	1649	/**
<>	135:176b8275d35d	1650	* @brief Clear Channel 7 transfer complete flag.
<>	135:176b8275d35d	1651	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	135:176b8275d35d	1652	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1653	* @retval None
<>	135:176b8275d35d	1654	*/
<>	135:176b8275d35d	1655	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1656	{
<>	135:176b8275d35d	1657	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	135:176b8275d35d	1658	}
<>	135:176b8275d35d	1659
<>	135:176b8275d35d	1660	/**
<>	135:176b8275d35d	1661	* @brief Clear Channel 1 half transfer flag.
<>	135:176b8275d35d	1662	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	135:176b8275d35d	1663	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1664	* @retval None
<>	135:176b8275d35d	1665	*/
<>	135:176b8275d35d	1666	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1667	{
<>	135:176b8275d35d	1668	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	135:176b8275d35d	1669	}
<>	135:176b8275d35d	1670
<>	135:176b8275d35d	1671	/**
<>	135:176b8275d35d	1672	* @brief Clear Channel 2 half transfer flag.
<>	135:176b8275d35d	1673	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	135:176b8275d35d	1674	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1675	* @retval None
<>	135:176b8275d35d	1676	*/
<>	135:176b8275d35d	1677	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1678	{
<>	135:176b8275d35d	1679	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	135:176b8275d35d	1680	}
<>	135:176b8275d35d	1681
<>	135:176b8275d35d	1682	/**
<>	135:176b8275d35d	1683	* @brief Clear Channel 3 half transfer flag.
<>	135:176b8275d35d	1684	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	135:176b8275d35d	1685	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1686	* @retval None
<>	135:176b8275d35d	1687	*/
<>	135:176b8275d35d	1688	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1689	{
<>	135:176b8275d35d	1690	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	135:176b8275d35d	1691	}
<>	135:176b8275d35d	1692
<>	135:176b8275d35d	1693	/**
<>	135:176b8275d35d	1694	* @brief Clear Channel 4 half transfer flag.
<>	135:176b8275d35d	1695	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	135:176b8275d35d	1696	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1697	* @retval None
<>	135:176b8275d35d	1698	*/
<>	135:176b8275d35d	1699	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1700	{
<>	135:176b8275d35d	1701	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	135:176b8275d35d	1702	}
<>	135:176b8275d35d	1703
<>	135:176b8275d35d	1704	/**
<>	135:176b8275d35d	1705	* @brief Clear Channel 5 half transfer flag.
<>	135:176b8275d35d	1706	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	135:176b8275d35d	1707	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1708	* @retval None
<>	135:176b8275d35d	1709	*/
<>	135:176b8275d35d	1710	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1711	{
<>	135:176b8275d35d	1712	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	135:176b8275d35d	1713	}
<>	135:176b8275d35d	1714
<>	135:176b8275d35d	1715	/**
<>	135:176b8275d35d	1716	* @brief Clear Channel 6 half transfer flag.
<>	135:176b8275d35d	1717	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	135:176b8275d35d	1718	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1719	* @retval None
<>	135:176b8275d35d	1720	*/
<>	135:176b8275d35d	1721	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1722	{
<>	135:176b8275d35d	1723	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	135:176b8275d35d	1724	}
<>	135:176b8275d35d	1725
<>	135:176b8275d35d	1726	/**
<>	135:176b8275d35d	1727	* @brief Clear Channel 7 half transfer flag.
<>	135:176b8275d35d	1728	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	135:176b8275d35d	1729	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1730	* @retval None
<>	135:176b8275d35d	1731	*/
<>	135:176b8275d35d	1732	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1733	{
<>	135:176b8275d35d	1734	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	135:176b8275d35d	1735	}
<>	135:176b8275d35d	1736
<>	135:176b8275d35d	1737	/**
<>	135:176b8275d35d	1738	* @brief Clear Channel 1 transfer error flag.
<>	135:176b8275d35d	1739	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	135:176b8275d35d	1740	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1741	* @retval None
<>	135:176b8275d35d	1742	*/
<>	135:176b8275d35d	1743	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1744	{
<>	135:176b8275d35d	1745	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	135:176b8275d35d	1746	}
<>	135:176b8275d35d	1747
<>	135:176b8275d35d	1748	/**
<>	135:176b8275d35d	1749	* @brief Clear Channel 2 transfer error flag.
<>	135:176b8275d35d	1750	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	135:176b8275d35d	1751	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1752	* @retval None
<>	135:176b8275d35d	1753	*/
<>	135:176b8275d35d	1754	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1755	{
<>	135:176b8275d35d	1756	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	135:176b8275d35d	1757	}
<>	135:176b8275d35d	1758
<>	135:176b8275d35d	1759	/**
<>	135:176b8275d35d	1760	* @brief Clear Channel 3 transfer error flag.
<>	135:176b8275d35d	1761	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	135:176b8275d35d	1762	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1763	* @retval None
<>	135:176b8275d35d	1764	*/
<>	135:176b8275d35d	1765	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1766	{
<>	135:176b8275d35d	1767	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	135:176b8275d35d	1768	}
<>	135:176b8275d35d	1769
<>	135:176b8275d35d	1770	/**
<>	135:176b8275d35d	1771	* @brief Clear Channel 4 transfer error flag.
<>	135:176b8275d35d	1772	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	135:176b8275d35d	1773	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1774	* @retval None
<>	135:176b8275d35d	1775	*/
<>	135:176b8275d35d	1776	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1777	{
<>	135:176b8275d35d	1778	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	135:176b8275d35d	1779	}
<>	135:176b8275d35d	1780
<>	135:176b8275d35d	1781	/**
<>	135:176b8275d35d	1782	* @brief Clear Channel 5 transfer error flag.
<>	135:176b8275d35d	1783	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	135:176b8275d35d	1784	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1785	* @retval None
<>	135:176b8275d35d	1786	*/
<>	135:176b8275d35d	1787	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1788	{
<>	135:176b8275d35d	1789	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	135:176b8275d35d	1790	}
<>	135:176b8275d35d	1791
<>	135:176b8275d35d	1792	/**
<>	135:176b8275d35d	1793	* @brief Clear Channel 6 transfer error flag.
<>	135:176b8275d35d	1794	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	135:176b8275d35d	1795	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1796	* @retval None
<>	135:176b8275d35d	1797	*/
<>	135:176b8275d35d	1798	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1799	{
<>	135:176b8275d35d	1800	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	135:176b8275d35d	1801	}
<>	135:176b8275d35d	1802
<>	135:176b8275d35d	1803	/**
<>	135:176b8275d35d	1804	* @brief Clear Channel 7 transfer error flag.
<>	135:176b8275d35d	1805	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	135:176b8275d35d	1806	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1807	* @retval None
<>	135:176b8275d35d	1808	*/
<>	135:176b8275d35d	1809	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1810	{
<>	135:176b8275d35d	1811	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	135:176b8275d35d	1812	}
<>	135:176b8275d35d	1813
<>	135:176b8275d35d	1814	/**
<>	135:176b8275d35d	1815	* @}
<>	135:176b8275d35d	1816	*/
<>	135:176b8275d35d	1817
<>	135:176b8275d35d	1818	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	135:176b8275d35d	1819	* @{
<>	135:176b8275d35d	1820	*/
<>	135:176b8275d35d	1821	/**
<>	135:176b8275d35d	1822	* @brief Enable Transfer complete interrupt.
<>	135:176b8275d35d	1823	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	135:176b8275d35d	1824	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1825	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1826	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1827	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1828	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1829	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1830	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1831	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1832	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1833	* @retval None
<>	135:176b8275d35d	1834	*/
<>	135:176b8275d35d	1835	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1836	{
<>	135:176b8275d35d	1837	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	135:176b8275d35d	1838	}
<>	135:176b8275d35d	1839
<>	135:176b8275d35d	1840	/**
<>	135:176b8275d35d	1841	* @brief Enable Half transfer interrupt.
<>	135:176b8275d35d	1842	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	135:176b8275d35d	1843	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1844	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1845	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1846	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1847	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1848	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1849	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1850	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1851	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1852	* @retval None
<>	135:176b8275d35d	1853	*/
<>	135:176b8275d35d	1854	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1855	{
<>	135:176b8275d35d	1856	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	135:176b8275d35d	1857	}
<>	135:176b8275d35d	1858
<>	135:176b8275d35d	1859	/**
<>	135:176b8275d35d	1860	* @brief Enable Transfer error interrupt.
<>	135:176b8275d35d	1861	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	135:176b8275d35d	1862	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1863	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1864	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1865	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1866	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1867	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1868	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1869	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1870	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1871	* @retval None
<>	135:176b8275d35d	1872	*/
<>	135:176b8275d35d	1873	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1874	{
<>	135:176b8275d35d	1875	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	135:176b8275d35d	1876	}
<>	135:176b8275d35d	1877
<>	135:176b8275d35d	1878	/**
<>	135:176b8275d35d	1879	* @brief Disable Transfer complete interrupt.
<>	135:176b8275d35d	1880	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	135:176b8275d35d	1881	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1882	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1883	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1884	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1885	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1886	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1887	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1888	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1889	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1890	* @retval None
<>	135:176b8275d35d	1891	*/
<>	135:176b8275d35d	1892	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1893	{
<>	135:176b8275d35d	1894	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	135:176b8275d35d	1895	}
<>	135:176b8275d35d	1896
<>	135:176b8275d35d	1897	/**
<>	135:176b8275d35d	1898	* @brief Disable Half transfer interrupt.
<>	135:176b8275d35d	1899	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	135:176b8275d35d	1900	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1901	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1902	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1903	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1904	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1905	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1906	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1907	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1908	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1909	* @retval None
<>	135:176b8275d35d	1910	*/
<>	135:176b8275d35d	1911	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1912	{
<>	135:176b8275d35d	1913	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	135:176b8275d35d	1914	}
<>	135:176b8275d35d	1915
<>	135:176b8275d35d	1916	/**
<>	135:176b8275d35d	1917	* @brief Disable Transfer error interrupt.
<>	135:176b8275d35d	1918	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	135:176b8275d35d	1919	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1920	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1921	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1922	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1923	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1924	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1925	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1926	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1927	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1928	* @retval None
<>	135:176b8275d35d	1929	*/
<>	135:176b8275d35d	1930	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1931	{
<>	135:176b8275d35d	1932	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	135:176b8275d35d	1933	}
<>	135:176b8275d35d	1934
<>	135:176b8275d35d	1935	/**
<>	135:176b8275d35d	1936	* @brief Check if Transfer complete Interrupt is enabled.
<>	135:176b8275d35d	1937	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	135:176b8275d35d	1938	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1939	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1940	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1941	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1942	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1943	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1944	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1945	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1946	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1947	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1948	*/
<>	135:176b8275d35d	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1950	{
<>	135:176b8275d35d	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1952	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	135:176b8275d35d	1953	}
<>	135:176b8275d35d	1954
<>	135:176b8275d35d	1955	/**
<>	135:176b8275d35d	1956	* @brief Check if Half transfer Interrupt is enabled.
<>	135:176b8275d35d	1957	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	135:176b8275d35d	1958	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1959	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1960	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1961	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1962	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1963	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1964	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1965	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1966	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1967	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1968	*/
<>	135:176b8275d35d	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1970	{
<>	135:176b8275d35d	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1972	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	135:176b8275d35d	1973	}
<>	135:176b8275d35d	1974
<>	135:176b8275d35d	1975	/**
<>	135:176b8275d35d	1976	* @brief Check if Transfer error Interrupt is enabled.
<>	135:176b8275d35d	1977	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	135:176b8275d35d	1978	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1979	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1980	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1981	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1982	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1983	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1984	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1985	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1986	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1987	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1988	*/
<>	135:176b8275d35d	1989	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1990	{
<>	135:176b8275d35d	1991	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1992	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	135:176b8275d35d	1993	}
<>	135:176b8275d35d	1994
<>	135:176b8275d35d	1995	/**
<>	135:176b8275d35d	1996	* @}
<>	135:176b8275d35d	1997	*/
<>	135:176b8275d35d	1998
<>	135:176b8275d35d	1999	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	2000	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	135:176b8275d35d	2001	* @{
<>	135:176b8275d35d	2002	*/
<>	135:176b8275d35d	2003
<>	135:176b8275d35d	2004	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	135:176b8275d35d	2005	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	135:176b8275d35d	2006	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	135:176b8275d35d	2007
<>	135:176b8275d35d	2008	/**
<>	135:176b8275d35d	2009	* @}
<>	135:176b8275d35d	2010	*/
<>	135:176b8275d35d	2011	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	2012
<>	135:176b8275d35d	2013	/**
<>	135:176b8275d35d	2014	* @}
<>	135:176b8275d35d	2015	*/
<>	135:176b8275d35d	2016
<>	135:176b8275d35d	2017	/**
<>	135:176b8275d35d	2018	* @}
<>	135:176b8275d35d	2019	*/
<>	135:176b8275d35d	2020
<>	135:176b8275d35d	2021	#endif /* DMA1 \|\| DMA2 */
<>	135:176b8275d35d	2022
<>	135:176b8275d35d	2023	/**
<>	135:176b8275d35d	2024	* @}
<>	135:176b8275d35d	2025	*/
<>	135:176b8275d35d	2026
<>	135:176b8275d35d	2027	#ifdef __cplusplus
<>	135:176b8275d35d	2028	}
<>	135:176b8275d35d	2029	#endif
<>	135:176b8275d35d	2030
<>	135:176b8275d35d	2031	#endif /* __STM32F3xx_LL_DMA_H */
<>	135:176b8275d35d	2032
<>	135:176b8275d35d	2033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/