mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h@168:b9e159c1930a, 2018-05-24 (annotated)

Committer:: AnnaBridge
Date:: Thu May 24 15:35:55 2018 +0100
Revision:: 168:b9e159c1930a
Parent:: 135:176b8275d35d

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_dma.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @brief Header file of DMA LL module.
<>	135:176b8275d35d	6	******************************************************************************
<>	135:176b8275d35d	7	* @attention
<>	135:176b8275d35d	8	*
<>	135:176b8275d35d	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	10	*
<>	135:176b8275d35d	11	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	12	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	14	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	16	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	17	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	19	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	20	* without specific prior written permission.
<>	135:176b8275d35d	21	*
<>	135:176b8275d35d	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	32	*
<>	135:176b8275d35d	33	******************************************************************************
<>	135:176b8275d35d	34	*/
<>	135:176b8275d35d	35
<>	135:176b8275d35d	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	37	#ifndef __STM32F3xx_LL_DMA_H
<>	135:176b8275d35d	38	#define __STM32F3xx_LL_DMA_H
<>	135:176b8275d35d	39
<>	135:176b8275d35d	40	#ifdef __cplusplus
<>	135:176b8275d35d	41	extern "C" {
<>	135:176b8275d35d	42	#endif
<>	135:176b8275d35d	43
<>	135:176b8275d35d	44	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	45	#include "stm32f3xx.h"
<>	135:176b8275d35d	46
<>	135:176b8275d35d	47	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	48	* @{
<>	135:176b8275d35d	49	*/
<>	135:176b8275d35d	50
<>	135:176b8275d35d	51	#if defined (DMA1) \|\| defined (DMA2)
<>	135:176b8275d35d	52
<>	135:176b8275d35d	53	/** @defgroup DMA_LL DMA
<>	135:176b8275d35d	54	* @{
<>	135:176b8275d35d	55	*/
<>	135:176b8275d35d	56
<>	135:176b8275d35d	57	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	58	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	135:176b8275d35d	60	* @{
<>	135:176b8275d35d	61	*/
<>	135:176b8275d35d	62	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	135:176b8275d35d	63	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	135:176b8275d35d	64	{
<>	135:176b8275d35d	65	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	135:176b8275d35d	66	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	135:176b8275d35d	67	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	135:176b8275d35d	68	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	135:176b8275d35d	69	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	135:176b8275d35d	70	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	135:176b8275d35d	71	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	135:176b8275d35d	72	};
<>	135:176b8275d35d	73	/**
<>	135:176b8275d35d	74	* @}
<>	135:176b8275d35d	75	*/
<>	135:176b8275d35d	76
<>	135:176b8275d35d	77	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	78	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	79	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	80	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	135:176b8275d35d	81	* @{
<>	135:176b8275d35d	82	*/
<>	135:176b8275d35d	83	/**
<>	135:176b8275d35d	84	* @}
<>	135:176b8275d35d	85	*/
<>	135:176b8275d35d	86	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	87
<>	135:176b8275d35d	88	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	89	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	90	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	135:176b8275d35d	91	* @{
<>	135:176b8275d35d	92	*/
<>	135:176b8275d35d	93	typedef struct
<>	135:176b8275d35d	94	{
<>	135:176b8275d35d	95	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	135:176b8275d35d	96	or as Source base address in case of memory to memory transfer direction.
<>	135:176b8275d35d	97
<>	135:176b8275d35d	98	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	135:176b8275d35d	99
<>	135:176b8275d35d	100	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	135:176b8275d35d	101	or as Destination base address in case of memory to memory transfer direction.
<>	135:176b8275d35d	102
<>	135:176b8275d35d	103	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	135:176b8275d35d	104
<>	135:176b8275d35d	105	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	135:176b8275d35d	106	from memory to memory or from peripheral to memory.
<>	135:176b8275d35d	107	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	135:176b8275d35d	108
<>	135:176b8275d35d	109	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	135:176b8275d35d	110
<>	135:176b8275d35d	111	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	135:176b8275d35d	112	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	135:176b8275d35d	113	@note: The circular buffer mode cannot be used if the memory to memory
<>	135:176b8275d35d	114	data transfer direction is configured on the selected Channel
<>	135:176b8275d35d	115
<>	135:176b8275d35d	116	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	135:176b8275d35d	117
<>	135:176b8275d35d	118	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	135:176b8275d35d	119	is incremented or not.
<>	135:176b8275d35d	120	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	135:176b8275d35d	121
<>	135:176b8275d35d	122	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	135:176b8275d35d	123
<>	135:176b8275d35d	124	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	135:176b8275d35d	125	is incremented or not.
<>	135:176b8275d35d	126	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	135:176b8275d35d	127
<>	135:176b8275d35d	128	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	135:176b8275d35d	129
<>	135:176b8275d35d	130	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	135:176b8275d35d	131	in case of memory to memory transfer direction.
<>	135:176b8275d35d	132	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	135:176b8275d35d	133
<>	135:176b8275d35d	134	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	135:176b8275d35d	135
<>	135:176b8275d35d	136	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	135:176b8275d35d	137	in case of memory to memory transfer direction.
<>	135:176b8275d35d	138	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	135:176b8275d35d	139
<>	135:176b8275d35d	140	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	135:176b8275d35d	141
<>	135:176b8275d35d	142	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	135:176b8275d35d	143	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	135:176b8275d35d	144	or MemorySize parameters depending in the transfer direction.
<>	135:176b8275d35d	145	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	135:176b8275d35d	146
<>	135:176b8275d35d	147	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	135:176b8275d35d	148
<>	135:176b8275d35d	149	uint32_t Priority; /*!< Specifies the channel priority level.
<>	135:176b8275d35d	150	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	135:176b8275d35d	151
<>	135:176b8275d35d	152	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	135:176b8275d35d	153
<>	135:176b8275d35d	154	} LL_DMA_InitTypeDef;
<>	135:176b8275d35d	155	/**
<>	135:176b8275d35d	156	* @}
<>	135:176b8275d35d	157	*/
<>	135:176b8275d35d	158	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	159
<>	135:176b8275d35d	160	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	161	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	135:176b8275d35d	162	* @{
<>	135:176b8275d35d	163	*/
<>	135:176b8275d35d	164	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	135:176b8275d35d	165	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	135:176b8275d35d	166	* @{
<>	135:176b8275d35d	167	*/
<>	135:176b8275d35d	168	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	135:176b8275d35d	169	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	135:176b8275d35d	170	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	135:176b8275d35d	171	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	135:176b8275d35d	172	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	135:176b8275d35d	173	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	135:176b8275d35d	174	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	135:176b8275d35d	175	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	135:176b8275d35d	176	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	135:176b8275d35d	177	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	135:176b8275d35d	178	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	135:176b8275d35d	179	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	135:176b8275d35d	180	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	135:176b8275d35d	181	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	135:176b8275d35d	182	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	135:176b8275d35d	183	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	135:176b8275d35d	184	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	135:176b8275d35d	185	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	135:176b8275d35d	186	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	135:176b8275d35d	187	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	135:176b8275d35d	188	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	135:176b8275d35d	189	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	135:176b8275d35d	190	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	135:176b8275d35d	191	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	135:176b8275d35d	192	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	135:176b8275d35d	193	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	135:176b8275d35d	194	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	135:176b8275d35d	195	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	135:176b8275d35d	196	/**
<>	135:176b8275d35d	197	* @}
<>	135:176b8275d35d	198	*/
<>	135:176b8275d35d	199
<>	135:176b8275d35d	200	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	201	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	135:176b8275d35d	202	* @{
<>	135:176b8275d35d	203	*/
<>	135:176b8275d35d	204	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	135:176b8275d35d	205	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	135:176b8275d35d	206	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	135:176b8275d35d	207	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	135:176b8275d35d	208	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	135:176b8275d35d	209	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	135:176b8275d35d	210	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	135:176b8275d35d	211	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	135:176b8275d35d	212	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	135:176b8275d35d	213	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	135:176b8275d35d	214	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	135:176b8275d35d	215	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	135:176b8275d35d	216	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	135:176b8275d35d	217	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	135:176b8275d35d	218	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	135:176b8275d35d	219	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	135:176b8275d35d	220	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	135:176b8275d35d	221	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	135:176b8275d35d	222	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	135:176b8275d35d	223	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	135:176b8275d35d	224	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	135:176b8275d35d	225	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	135:176b8275d35d	226	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	135:176b8275d35d	227	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	135:176b8275d35d	228	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	135:176b8275d35d	229	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	135:176b8275d35d	230	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	135:176b8275d35d	231	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	135:176b8275d35d	232	/**
<>	135:176b8275d35d	233	* @}
<>	135:176b8275d35d	234	*/
<>	135:176b8275d35d	235
<>	135:176b8275d35d	236	/** @defgroup DMA_LL_EC_IT IT Defines
<>	135:176b8275d35d	237	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	135:176b8275d35d	238	* @{
<>	135:176b8275d35d	239	*/
<>	135:176b8275d35d	240	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	135:176b8275d35d	241	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	135:176b8275d35d	242	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	135:176b8275d35d	243	/**
<>	135:176b8275d35d	244	* @}
<>	135:176b8275d35d	245	*/
<>	135:176b8275d35d	246
<>	135:176b8275d35d	247	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	135:176b8275d35d	248	* @{
<>	135:176b8275d35d	249	*/
AnnaBridge	168:b9e159c1930a	250	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	168:b9e159c1930a	251	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	168:b9e159c1930a	252	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	168:b9e159c1930a	253	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	168:b9e159c1930a	254	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	168:b9e159c1930a	255	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	168:b9e159c1930a	256	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
<>	135:176b8275d35d	257	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	168:b9e159c1930a	258	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	135:176b8275d35d	259	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	260	/**
<>	135:176b8275d35d	261	* @}
<>	135:176b8275d35d	262	*/
<>	135:176b8275d35d	263
<>	135:176b8275d35d	264	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	135:176b8275d35d	265	* @{
<>	135:176b8275d35d	266	*/
AnnaBridge	168:b9e159c1930a	267	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
<>	135:176b8275d35d	268	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	135:176b8275d35d	269	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	135:176b8275d35d	270	/**
<>	135:176b8275d35d	271	* @}
<>	135:176b8275d35d	272	*/
<>	135:176b8275d35d	273
<>	135:176b8275d35d	274	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	135:176b8275d35d	275	* @{
<>	135:176b8275d35d	276	*/
AnnaBridge	168:b9e159c1930a	277	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
<>	135:176b8275d35d	278	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	135:176b8275d35d	279	/**
<>	135:176b8275d35d	280	* @}
<>	135:176b8275d35d	281	*/
<>	135:176b8275d35d	282
<>	135:176b8275d35d	283	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	135:176b8275d35d	284	* @{
<>	135:176b8275d35d	285	*/
<>	135:176b8275d35d	286	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	168:b9e159c1930a	287	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
<>	135:176b8275d35d	288	/**
<>	135:176b8275d35d	289	* @}
<>	135:176b8275d35d	290	*/
<>	135:176b8275d35d	291
<>	135:176b8275d35d	292	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	135:176b8275d35d	293	* @{
<>	135:176b8275d35d	294	*/
<>	135:176b8275d35d	295	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	168:b9e159c1930a	296	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
<>	135:176b8275d35d	297	/**
<>	135:176b8275d35d	298	* @}
<>	135:176b8275d35d	299	*/
<>	135:176b8275d35d	300
<>	135:176b8275d35d	301	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	135:176b8275d35d	302	* @{
<>	135:176b8275d35d	303	*/
AnnaBridge	168:b9e159c1930a	304	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
<>	135:176b8275d35d	305	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	135:176b8275d35d	306	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	135:176b8275d35d	307	/**
<>	135:176b8275d35d	308	* @}
<>	135:176b8275d35d	309	*/
<>	135:176b8275d35d	310
<>	135:176b8275d35d	311	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	135:176b8275d35d	312	* @{
<>	135:176b8275d35d	313	*/
AnnaBridge	168:b9e159c1930a	314	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
<>	135:176b8275d35d	315	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	135:176b8275d35d	316	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	135:176b8275d35d	317	/**
<>	135:176b8275d35d	318	* @}
<>	135:176b8275d35d	319	*/
<>	135:176b8275d35d	320
<>	135:176b8275d35d	321	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	135:176b8275d35d	322	* @{
<>	135:176b8275d35d	323	*/
AnnaBridge	168:b9e159c1930a	324	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
<>	135:176b8275d35d	325	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	135:176b8275d35d	326	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	135:176b8275d35d	327	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	135:176b8275d35d	328	/**
<>	135:176b8275d35d	329	* @}
<>	135:176b8275d35d	330	*/
<>	135:176b8275d35d	331
<>	135:176b8275d35d	332
<>	135:176b8275d35d	333	/**
<>	135:176b8275d35d	334	* @}
<>	135:176b8275d35d	335	*/
<>	135:176b8275d35d	336
<>	135:176b8275d35d	337	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	338	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	135:176b8275d35d	339	* @{
<>	135:176b8275d35d	340	*/
<>	135:176b8275d35d	341
<>	135:176b8275d35d	342	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	135:176b8275d35d	343	* @{
<>	135:176b8275d35d	344	*/
<>	135:176b8275d35d	345	/**
<>	135:176b8275d35d	346	* @brief Write a value in DMA register
<>	135:176b8275d35d	347	* @param __INSTANCE__ DMA Instance
<>	135:176b8275d35d	348	* @param __REG__ Register to be written
<>	135:176b8275d35d	349	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	350	* @retval None
<>	135:176b8275d35d	351	*/
<>	135:176b8275d35d	352	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	353
<>	135:176b8275d35d	354	/**
<>	135:176b8275d35d	355	* @brief Read a value in DMA register
<>	135:176b8275d35d	356	* @param __INSTANCE__ DMA Instance
<>	135:176b8275d35d	357	* @param __REG__ Register to be read
<>	135:176b8275d35d	358	* @retval Register value
<>	135:176b8275d35d	359	*/
<>	135:176b8275d35d	360	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	361	/**
<>	135:176b8275d35d	362	* @}
<>	135:176b8275d35d	363	*/
<>	135:176b8275d35d	364
<>	135:176b8275d35d	365	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	135:176b8275d35d	366	* @{
<>	135:176b8275d35d	367	*/
<>	135:176b8275d35d	368	/**
<>	135:176b8275d35d	369	* @brief Convert DMAx_Channely into DMAx
<>	135:176b8275d35d	370	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	135:176b8275d35d	371	* @retval DMAx
<>	135:176b8275d35d	372	*/
<>	135:176b8275d35d	373	#if defined(DMA2)
<>	135:176b8275d35d	374	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	375	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	135:176b8275d35d	376	#else
<>	135:176b8275d35d	377	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	135:176b8275d35d	378	#endif
<>	135:176b8275d35d	379
<>	135:176b8275d35d	380	/**
<>	135:176b8275d35d	381	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	135:176b8275d35d	382	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	135:176b8275d35d	383	* @retval LL_DMA_CHANNEL_y
<>	135:176b8275d35d	384	*/
<>	135:176b8275d35d	385	#if defined (DMA2)
<>	135:176b8275d35d	386	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	135:176b8275d35d	387	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	388	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	389	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	390	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	391	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	392	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	393	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	394	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	395	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	396	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	397	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	398	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	399	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	400	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	401	#else
<>	135:176b8275d35d	402	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	403	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	404	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	414	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	415	#endif
<>	135:176b8275d35d	416	#else
<>	135:176b8275d35d	417	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	135:176b8275d35d	418	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	135:176b8275d35d	419	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	135:176b8275d35d	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	135:176b8275d35d	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	135:176b8275d35d	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	135:176b8275d35d	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	135:176b8275d35d	424	LL_DMA_CHANNEL_7)
<>	135:176b8275d35d	425	#endif
<>	135:176b8275d35d	426
<>	135:176b8275d35d	427	/**
<>	135:176b8275d35d	428	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	135:176b8275d35d	429	* @param __DMA_INSTANCE__ DMAx
<>	135:176b8275d35d	430	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	135:176b8275d35d	431	* @retval DMAx_Channely
<>	135:176b8275d35d	432	*/
<>	135:176b8275d35d	433	#if defined (DMA2)
<>	135:176b8275d35d	434	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	135:176b8275d35d	435	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	436	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	437	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	135:176b8275d35d	438	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	439	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	135:176b8275d35d	440	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	441	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	135:176b8275d35d	442	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	443	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	135:176b8275d35d	444	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	445	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	135:176b8275d35d	446	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	447	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	135:176b8275d35d	448	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	135:176b8275d35d	449	DMA2_Channel7)
<>	135:176b8275d35d	450	#else
<>	135:176b8275d35d	451	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	452	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	135:176b8275d35d	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	135:176b8275d35d	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	135:176b8275d35d	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	135:176b8275d35d	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	135:176b8275d35d	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	463	DMA1_Channel7)
<>	135:176b8275d35d	464	#endif
<>	135:176b8275d35d	465	#else
<>	135:176b8275d35d	466	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	135:176b8275d35d	467	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	135:176b8275d35d	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	135:176b8275d35d	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	135:176b8275d35d	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	135:176b8275d35d	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	135:176b8275d35d	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	135:176b8275d35d	473	DMA1_Channel7)
<>	135:176b8275d35d	474	#endif
<>	135:176b8275d35d	475
<>	135:176b8275d35d	476	/**
<>	135:176b8275d35d	477	* @}
<>	135:176b8275d35d	478	*/
<>	135:176b8275d35d	479
<>	135:176b8275d35d	480	/**
<>	135:176b8275d35d	481	* @}
<>	135:176b8275d35d	482	*/
<>	135:176b8275d35d	483
<>	135:176b8275d35d	484	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	485	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	135:176b8275d35d	486	* @{
<>	135:176b8275d35d	487	*/
<>	135:176b8275d35d	488
<>	135:176b8275d35d	489	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	135:176b8275d35d	490	* @{
<>	135:176b8275d35d	491	*/
<>	135:176b8275d35d	492	/**
<>	135:176b8275d35d	493	* @brief Enable DMA channel.
<>	135:176b8275d35d	494	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	135:176b8275d35d	495	* @param DMAx DMAx Instance
<>	135:176b8275d35d	496	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	497	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	498	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	499	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	500	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	501	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	502	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	503	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	504	* @retval None
<>	135:176b8275d35d	505	*/
<>	135:176b8275d35d	506	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	507	{
<>	135:176b8275d35d	508	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	135:176b8275d35d	509	}
<>	135:176b8275d35d	510
<>	135:176b8275d35d	511	/**
<>	135:176b8275d35d	512	* @brief Disable DMA channel.
<>	135:176b8275d35d	513	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	135:176b8275d35d	514	* @param DMAx DMAx Instance
<>	135:176b8275d35d	515	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	516	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	517	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	518	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	519	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	520	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	521	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	522	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	523	* @retval None
<>	135:176b8275d35d	524	*/
<>	135:176b8275d35d	525	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	526	{
<>	135:176b8275d35d	527	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	135:176b8275d35d	528	}
<>	135:176b8275d35d	529
<>	135:176b8275d35d	530	/**
<>	135:176b8275d35d	531	* @brief Check if DMA channel is enabled or disabled.
<>	135:176b8275d35d	532	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	135:176b8275d35d	533	* @param DMAx DMAx Instance
<>	135:176b8275d35d	534	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	535	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	536	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	537	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	538	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	539	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	540	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	541	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	542	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	543	*/
<>	135:176b8275d35d	544	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	545	{
<>	135:176b8275d35d	546	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	547	DMA_CCR_EN) == (DMA_CCR_EN));
<>	135:176b8275d35d	548	}
<>	135:176b8275d35d	549
<>	135:176b8275d35d	550	/**
<>	135:176b8275d35d	551	* @brief Configure all parameters link to DMA transfer.
<>	135:176b8275d35d	552	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	553	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	554	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	555	* CCR PINC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	556	* CCR MINC LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	557	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	558	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	135:176b8275d35d	559	* CCR PL LL_DMA_ConfigTransfer
<>	135:176b8275d35d	560	* @param DMAx DMAx Instance
<>	135:176b8275d35d	561	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	562	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	563	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	564	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	565	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	566	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	567	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	568	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	569	* @param Configuration This parameter must be a combination of all the following values:
<>	135:176b8275d35d	570	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	571	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	572	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	573	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	574	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	575	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	576	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	577	* @retval None
<>	135:176b8275d35d	578	*/
<>	135:176b8275d35d	579	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	135:176b8275d35d	580	{
<>	135:176b8275d35d	581	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	582	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	135:176b8275d35d	583	Configuration);
<>	135:176b8275d35d	584	}
<>	135:176b8275d35d	585
<>	135:176b8275d35d	586	/**
<>	135:176b8275d35d	587	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	135:176b8275d35d	588	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	135:176b8275d35d	589	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	135:176b8275d35d	590	* @param DMAx DMAx Instance
<>	135:176b8275d35d	591	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	592	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	593	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	594	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	595	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	596	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	597	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	598	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	599	* @param Direction This parameter can be one of the following values:
<>	135:176b8275d35d	600	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	601	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	602	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	603	* @retval None
<>	135:176b8275d35d	604	*/
<>	135:176b8275d35d	605	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	135:176b8275d35d	606	{
<>	135:176b8275d35d	607	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	608	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	135:176b8275d35d	609	}
<>	135:176b8275d35d	610
<>	135:176b8275d35d	611	/**
<>	135:176b8275d35d	612	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	135:176b8275d35d	613	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	135:176b8275d35d	614	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	135:176b8275d35d	615	* @param DMAx DMAx Instance
<>	135:176b8275d35d	616	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	617	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	618	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	619	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	620	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	621	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	622	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	623	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	624	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	625	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	626	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	627	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	628	*/
<>	135:176b8275d35d	629	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	630	{
<>	135:176b8275d35d	631	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	632	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	135:176b8275d35d	633	}
<>	135:176b8275d35d	634
<>	135:176b8275d35d	635	/**
<>	135:176b8275d35d	636	* @brief Set DMA mode circular or normal.
<>	135:176b8275d35d	637	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	135:176b8275d35d	638	* data transfer is configured on the selected Channel.
<>	135:176b8275d35d	639	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	135:176b8275d35d	640	* @param DMAx DMAx Instance
<>	135:176b8275d35d	641	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	642	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	643	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	644	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	645	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	646	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	647	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	648	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	649	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	650	* @arg @ref LL_DMA_MODE_NORMAL
<>	135:176b8275d35d	651	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	652	* @retval None
<>	135:176b8275d35d	653	*/
<>	135:176b8275d35d	654	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	135:176b8275d35d	655	{
<>	135:176b8275d35d	656	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	135:176b8275d35d	657	Mode);
<>	135:176b8275d35d	658	}
<>	135:176b8275d35d	659
<>	135:176b8275d35d	660	/**
<>	135:176b8275d35d	661	* @brief Get DMA mode circular or normal.
<>	135:176b8275d35d	662	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	135:176b8275d35d	663	* @param DMAx DMAx Instance
<>	135:176b8275d35d	664	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	665	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	666	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	667	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	668	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	669	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	670	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	671	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	672	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	673	* @arg @ref LL_DMA_MODE_NORMAL
<>	135:176b8275d35d	674	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	135:176b8275d35d	675	*/
<>	135:176b8275d35d	676	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	677	{
<>	135:176b8275d35d	678	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	679	DMA_CCR_CIRC));
<>	135:176b8275d35d	680	}
<>	135:176b8275d35d	681
<>	135:176b8275d35d	682	/**
<>	135:176b8275d35d	683	* @brief Set Peripheral increment mode.
<>	135:176b8275d35d	684	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	135:176b8275d35d	685	* @param DMAx DMAx Instance
<>	135:176b8275d35d	686	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	687	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	688	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	689	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	690	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	691	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	692	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	693	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	694	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	135:176b8275d35d	695	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	135:176b8275d35d	696	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	697	* @retval None
<>	135:176b8275d35d	698	*/
<>	135:176b8275d35d	699	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	135:176b8275d35d	700	{
<>	135:176b8275d35d	701	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	135:176b8275d35d	702	PeriphOrM2MSrcIncMode);
<>	135:176b8275d35d	703	}
<>	135:176b8275d35d	704
<>	135:176b8275d35d	705	/**
<>	135:176b8275d35d	706	* @brief Get Peripheral increment mode.
<>	135:176b8275d35d	707	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	135:176b8275d35d	708	* @param DMAx DMAx Instance
<>	135:176b8275d35d	709	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	710	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	711	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	712	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	713	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	714	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	715	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	716	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	717	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	718	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	135:176b8275d35d	719	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	135:176b8275d35d	720	*/
<>	135:176b8275d35d	721	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	722	{
<>	135:176b8275d35d	723	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	724	DMA_CCR_PINC));
<>	135:176b8275d35d	725	}
<>	135:176b8275d35d	726
<>	135:176b8275d35d	727	/**
<>	135:176b8275d35d	728	* @brief Set Memory increment mode.
<>	135:176b8275d35d	729	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	135:176b8275d35d	730	* @param DMAx DMAx Instance
<>	135:176b8275d35d	731	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	732	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	733	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	734	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	735	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	736	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	737	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	738	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	739	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	135:176b8275d35d	740	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	135:176b8275d35d	741	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	742	* @retval None
<>	135:176b8275d35d	743	*/
<>	135:176b8275d35d	744	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	135:176b8275d35d	745	{
<>	135:176b8275d35d	746	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	135:176b8275d35d	747	MemoryOrM2MDstIncMode);
<>	135:176b8275d35d	748	}
<>	135:176b8275d35d	749
<>	135:176b8275d35d	750	/**
<>	135:176b8275d35d	751	* @brief Get Memory increment mode.
<>	135:176b8275d35d	752	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	135:176b8275d35d	753	* @param DMAx DMAx Instance
<>	135:176b8275d35d	754	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	755	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	756	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	757	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	758	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	759	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	760	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	761	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	762	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	763	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	135:176b8275d35d	764	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	135:176b8275d35d	765	*/
<>	135:176b8275d35d	766	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	767	{
<>	135:176b8275d35d	768	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	769	DMA_CCR_MINC));
<>	135:176b8275d35d	770	}
<>	135:176b8275d35d	771
<>	135:176b8275d35d	772	/**
<>	135:176b8275d35d	773	* @brief Set Peripheral size.
<>	135:176b8275d35d	774	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	135:176b8275d35d	775	* @param DMAx DMAx Instance
<>	135:176b8275d35d	776	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	777	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	778	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	779	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	780	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	781	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	782	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	783	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	784	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	135:176b8275d35d	785	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	135:176b8275d35d	786	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	135:176b8275d35d	787	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	788	* @retval None
<>	135:176b8275d35d	789	*/
<>	135:176b8275d35d	790	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	135:176b8275d35d	791	{
<>	135:176b8275d35d	792	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	135:176b8275d35d	793	PeriphOrM2MSrcDataSize);
<>	135:176b8275d35d	794	}
<>	135:176b8275d35d	795
<>	135:176b8275d35d	796	/**
<>	135:176b8275d35d	797	* @brief Get Peripheral size.
<>	135:176b8275d35d	798	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	135:176b8275d35d	799	* @param DMAx DMAx Instance
<>	135:176b8275d35d	800	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	801	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	802	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	803	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	804	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	805	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	806	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	807	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	808	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	809	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	135:176b8275d35d	810	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	135:176b8275d35d	811	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	135:176b8275d35d	812	*/
<>	135:176b8275d35d	813	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	814	{
<>	135:176b8275d35d	815	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	816	DMA_CCR_PSIZE));
<>	135:176b8275d35d	817	}
<>	135:176b8275d35d	818
<>	135:176b8275d35d	819	/**
<>	135:176b8275d35d	820	* @brief Set Memory size.
<>	135:176b8275d35d	821	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	135:176b8275d35d	822	* @param DMAx DMAx Instance
<>	135:176b8275d35d	823	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	824	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	825	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	826	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	827	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	828	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	829	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	830	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	831	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	135:176b8275d35d	832	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	135:176b8275d35d	833	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	135:176b8275d35d	834	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	835	* @retval None
<>	135:176b8275d35d	836	*/
<>	135:176b8275d35d	837	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	135:176b8275d35d	838	{
<>	135:176b8275d35d	839	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	135:176b8275d35d	840	MemoryOrM2MDstDataSize);
<>	135:176b8275d35d	841	}
<>	135:176b8275d35d	842
<>	135:176b8275d35d	843	/**
<>	135:176b8275d35d	844	* @brief Get Memory size.
<>	135:176b8275d35d	845	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	135:176b8275d35d	846	* @param DMAx DMAx Instance
<>	135:176b8275d35d	847	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	848	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	849	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	850	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	851	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	852	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	853	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	854	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	855	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	856	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	135:176b8275d35d	857	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	135:176b8275d35d	858	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	135:176b8275d35d	859	*/
<>	135:176b8275d35d	860	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	861	{
<>	135:176b8275d35d	862	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	863	DMA_CCR_MSIZE));
<>	135:176b8275d35d	864	}
<>	135:176b8275d35d	865
<>	135:176b8275d35d	866	/**
<>	135:176b8275d35d	867	* @brief Set Channel priority level.
<>	135:176b8275d35d	868	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	135:176b8275d35d	869	* @param DMAx DMAx Instance
<>	135:176b8275d35d	870	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	871	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	872	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	873	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	874	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	875	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	876	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	877	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	878	* @param Priority This parameter can be one of the following values:
<>	135:176b8275d35d	879	* @arg @ref LL_DMA_PRIORITY_LOW
<>	135:176b8275d35d	880	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	135:176b8275d35d	881	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	135:176b8275d35d	882	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	883	* @retval None
<>	135:176b8275d35d	884	*/
<>	135:176b8275d35d	885	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	135:176b8275d35d	886	{
<>	135:176b8275d35d	887	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	135:176b8275d35d	888	Priority);
<>	135:176b8275d35d	889	}
<>	135:176b8275d35d	890
<>	135:176b8275d35d	891	/**
<>	135:176b8275d35d	892	* @brief Get Channel priority level.
<>	135:176b8275d35d	893	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	135:176b8275d35d	894	* @param DMAx DMAx Instance
<>	135:176b8275d35d	895	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	896	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	897	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	898	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	899	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	900	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	901	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	902	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	903	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	904	* @arg @ref LL_DMA_PRIORITY_LOW
<>	135:176b8275d35d	905	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	135:176b8275d35d	906	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	135:176b8275d35d	907	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	135:176b8275d35d	908	*/
<>	135:176b8275d35d	909	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	910	{
<>	135:176b8275d35d	911	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	912	DMA_CCR_PL));
<>	135:176b8275d35d	913	}
<>	135:176b8275d35d	914
<>	135:176b8275d35d	915	/**
<>	135:176b8275d35d	916	* @brief Set Number of data to transfer.
<>	135:176b8275d35d	917	* @note This action has no effect if
<>	135:176b8275d35d	918	* channel is enabled.
<>	135:176b8275d35d	919	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	135:176b8275d35d	920	* @param DMAx DMAx Instance
<>	135:176b8275d35d	921	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	922	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	923	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	924	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	925	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	926	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	927	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	928	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	929	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	135:176b8275d35d	930	* @retval None
<>	135:176b8275d35d	931	*/
<>	135:176b8275d35d	932	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	135:176b8275d35d	933	{
<>	135:176b8275d35d	934	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	135:176b8275d35d	935	DMA_CNDTR_NDT, NbData);
<>	135:176b8275d35d	936	}
<>	135:176b8275d35d	937
<>	135:176b8275d35d	938	/**
<>	135:176b8275d35d	939	* @brief Get Number of data to transfer.
<>	135:176b8275d35d	940	* @note Once the channel is enabled, the return value indicate the
<>	135:176b8275d35d	941	* remaining bytes to be transmitted.
<>	135:176b8275d35d	942	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	135:176b8275d35d	943	* @param DMAx DMAx Instance
<>	135:176b8275d35d	944	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	945	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	946	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	947	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	948	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	949	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	950	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	951	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	952	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	953	*/
<>	135:176b8275d35d	954	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	955	{
<>	135:176b8275d35d	956	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	135:176b8275d35d	957	DMA_CNDTR_NDT));
<>	135:176b8275d35d	958	}
<>	135:176b8275d35d	959
<>	135:176b8275d35d	960	/**
<>	135:176b8275d35d	961	* @brief Configure the Source and Destination addresses.
AnnaBridge	168:b9e159c1930a	962	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	168:b9e159c1930a	963	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
<>	135:176b8275d35d	964	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	135:176b8275d35d	965	* CMAR MA LL_DMA_ConfigAddresses
<>	135:176b8275d35d	966	* @param DMAx DMAx Instance
<>	135:176b8275d35d	967	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	968	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	969	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	970	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	971	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	972	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	973	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	974	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	975	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	976	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	977	* @param Direction This parameter can be one of the following values:
<>	135:176b8275d35d	978	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	135:176b8275d35d	979	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	135:176b8275d35d	980	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	135:176b8275d35d	981	* @retval None
<>	135:176b8275d35d	982	*/
<>	135:176b8275d35d	983	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	135:176b8275d35d	984	uint32_t DstAddress, uint32_t Direction)
<>	135:176b8275d35d	985	{
<>	135:176b8275d35d	986	/* Direction Memory to Periph */
<>	135:176b8275d35d	987	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	135:176b8275d35d	988	{
AnnaBridge	168:b9e159c1930a	989	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	168:b9e159c1930a	990	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
<>	135:176b8275d35d	991	}
<>	135:176b8275d35d	992	/* Direction Periph to Memory and Memory to Memory */
<>	135:176b8275d35d	993	else
<>	135:176b8275d35d	994	{
AnnaBridge	168:b9e159c1930a	995	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	168:b9e159c1930a	996	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
<>	135:176b8275d35d	997	}
<>	135:176b8275d35d	998	}
<>	135:176b8275d35d	999
<>	135:176b8275d35d	1000	/**
<>	135:176b8275d35d	1001	* @brief Set the Memory address.
<>	135:176b8275d35d	1002	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	168:b9e159c1930a	1003	* @note This API must not be called when the DMA channel is enabled.
<>	135:176b8275d35d	1004	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	135:176b8275d35d	1005	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1006	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1007	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1008	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1009	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1010	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1011	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1012	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1013	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1014	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1015	* @retval None
<>	135:176b8275d35d	1016	*/
<>	135:176b8275d35d	1017	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1018	{
AnnaBridge	168:b9e159c1930a	1019	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<>	135:176b8275d35d	1020	}
<>	135:176b8275d35d	1021
<>	135:176b8275d35d	1022	/**
<>	135:176b8275d35d	1023	* @brief Set the Peripheral address.
<>	135:176b8275d35d	1024	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	168:b9e159c1930a	1025	* @note This API must not be called when the DMA channel is enabled.
<>	135:176b8275d35d	1026	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	135:176b8275d35d	1027	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1028	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1029	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1030	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1031	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1032	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1033	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1034	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1035	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1036	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1037	* @retval None
<>	135:176b8275d35d	1038	*/
<>	135:176b8275d35d	1039	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	135:176b8275d35d	1040	{
AnnaBridge	168:b9e159c1930a	1041	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
<>	135:176b8275d35d	1042	}
<>	135:176b8275d35d	1043
<>	135:176b8275d35d	1044	/**
<>	135:176b8275d35d	1045	* @brief Get Memory address.
<>	135:176b8275d35d	1046	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1047	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	135:176b8275d35d	1048	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1049	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1050	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1051	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1052	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1053	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1054	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1055	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1056	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1057	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1058	*/
<>	135:176b8275d35d	1059	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1060	{
AnnaBridge	168:b9e159c1930a	1061	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<>	135:176b8275d35d	1062	}
<>	135:176b8275d35d	1063
<>	135:176b8275d35d	1064	/**
<>	135:176b8275d35d	1065	* @brief Get Peripheral address.
<>	135:176b8275d35d	1066	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	135:176b8275d35d	1067	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	135:176b8275d35d	1068	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1069	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1070	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1071	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1072	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1073	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1074	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1075	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1076	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1077	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1078	*/
<>	135:176b8275d35d	1079	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1080	{
AnnaBridge	168:b9e159c1930a	1081	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<>	135:176b8275d35d	1082	}
<>	135:176b8275d35d	1083
<>	135:176b8275d35d	1084	/**
<>	135:176b8275d35d	1085	* @brief Set the Memory to Memory Source address.
<>	135:176b8275d35d	1086	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	168:b9e159c1930a	1087	* @note This API must not be called when the DMA channel is enabled.
<>	135:176b8275d35d	1088	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	135:176b8275d35d	1089	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1090	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1091	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1092	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1093	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1094	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1095	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1096	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1097	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1098	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1099	* @retval None
<>	135:176b8275d35d	1100	*/
<>	135:176b8275d35d	1101	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1102	{
AnnaBridge	168:b9e159c1930a	1103	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
<>	135:176b8275d35d	1104	}
<>	135:176b8275d35d	1105
<>	135:176b8275d35d	1106	/**
<>	135:176b8275d35d	1107	* @brief Set the Memory to Memory Destination address.
<>	135:176b8275d35d	1108	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	168:b9e159c1930a	1109	* @note This API must not be called when the DMA channel is enabled.
<>	135:176b8275d35d	1110	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	135:176b8275d35d	1111	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1112	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1113	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1114	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1115	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1116	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1117	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1118	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1119	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1120	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1121	* @retval None
<>	135:176b8275d35d	1122	*/
<>	135:176b8275d35d	1123	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	135:176b8275d35d	1124	{
AnnaBridge	168:b9e159c1930a	1125	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<>	135:176b8275d35d	1126	}
<>	135:176b8275d35d	1127
<>	135:176b8275d35d	1128	/**
<>	135:176b8275d35d	1129	* @brief Get the Memory to Memory Source address.
<>	135:176b8275d35d	1130	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1131	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	135:176b8275d35d	1132	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1133	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1134	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1135	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1136	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1137	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1138	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1139	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1140	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1141	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1142	*/
<>	135:176b8275d35d	1143	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1144	{
AnnaBridge	168:b9e159c1930a	1145	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<>	135:176b8275d35d	1146	}
<>	135:176b8275d35d	1147
<>	135:176b8275d35d	1148	/**
<>	135:176b8275d35d	1149	* @brief Get the Memory to Memory Destination address.
<>	135:176b8275d35d	1150	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	135:176b8275d35d	1151	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	135:176b8275d35d	1152	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1153	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1154	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1155	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1156	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1157	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1158	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1159	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1160	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1161	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	135:176b8275d35d	1162	*/
<>	135:176b8275d35d	1163	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1164	{
AnnaBridge	168:b9e159c1930a	1165	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<>	135:176b8275d35d	1166	}
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168
<>	135:176b8275d35d	1169	/**
<>	135:176b8275d35d	1170	* @}
<>	135:176b8275d35d	1171	*/
<>	135:176b8275d35d	1172
<>	135:176b8275d35d	1173	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	135:176b8275d35d	1174	* @{
<>	135:176b8275d35d	1175	*/
<>	135:176b8275d35d	1176
<>	135:176b8275d35d	1177	/**
<>	135:176b8275d35d	1178	* @brief Get Channel 1 global interrupt flag.
<>	135:176b8275d35d	1179	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	135:176b8275d35d	1180	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1181	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1182	*/
<>	135:176b8275d35d	1183	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1184	{
<>	135:176b8275d35d	1185	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	135:176b8275d35d	1186	}
<>	135:176b8275d35d	1187
<>	135:176b8275d35d	1188	/**
<>	135:176b8275d35d	1189	* @brief Get Channel 2 global interrupt flag.
<>	135:176b8275d35d	1190	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	135:176b8275d35d	1191	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1192	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1193	*/
<>	135:176b8275d35d	1194	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1195	{
<>	135:176b8275d35d	1196	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	135:176b8275d35d	1197	}
<>	135:176b8275d35d	1198
<>	135:176b8275d35d	1199	/**
<>	135:176b8275d35d	1200	* @brief Get Channel 3 global interrupt flag.
<>	135:176b8275d35d	1201	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	135:176b8275d35d	1202	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1203	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1204	*/
<>	135:176b8275d35d	1205	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1206	{
<>	135:176b8275d35d	1207	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	135:176b8275d35d	1208	}
<>	135:176b8275d35d	1209
<>	135:176b8275d35d	1210	/**
<>	135:176b8275d35d	1211	* @brief Get Channel 4 global interrupt flag.
<>	135:176b8275d35d	1212	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	135:176b8275d35d	1213	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1214	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1215	*/
<>	135:176b8275d35d	1216	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1217	{
<>	135:176b8275d35d	1218	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	135:176b8275d35d	1219	}
<>	135:176b8275d35d	1220
<>	135:176b8275d35d	1221	/**
<>	135:176b8275d35d	1222	* @brief Get Channel 5 global interrupt flag.
<>	135:176b8275d35d	1223	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	135:176b8275d35d	1224	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1225	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1226	*/
<>	135:176b8275d35d	1227	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1228	{
<>	135:176b8275d35d	1229	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	135:176b8275d35d	1230	}
<>	135:176b8275d35d	1231
<>	135:176b8275d35d	1232	/**
<>	135:176b8275d35d	1233	* @brief Get Channel 6 global interrupt flag.
<>	135:176b8275d35d	1234	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	135:176b8275d35d	1235	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1236	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1237	*/
<>	135:176b8275d35d	1238	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1239	{
<>	135:176b8275d35d	1240	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	135:176b8275d35d	1241	}
<>	135:176b8275d35d	1242
<>	135:176b8275d35d	1243	/**
<>	135:176b8275d35d	1244	* @brief Get Channel 7 global interrupt flag.
<>	135:176b8275d35d	1245	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	135:176b8275d35d	1246	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1247	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1248	*/
<>	135:176b8275d35d	1249	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1250	{
<>	135:176b8275d35d	1251	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	135:176b8275d35d	1252	}
<>	135:176b8275d35d	1253
<>	135:176b8275d35d	1254	/**
<>	135:176b8275d35d	1255	* @brief Get Channel 1 transfer complete flag.
<>	135:176b8275d35d	1256	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	135:176b8275d35d	1257	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1258	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1259	*/
<>	135:176b8275d35d	1260	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1261	{
<>	135:176b8275d35d	1262	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	135:176b8275d35d	1263	}
<>	135:176b8275d35d	1264
<>	135:176b8275d35d	1265	/**
<>	135:176b8275d35d	1266	* @brief Get Channel 2 transfer complete flag.
<>	135:176b8275d35d	1267	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	135:176b8275d35d	1268	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1269	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1270	*/
<>	135:176b8275d35d	1271	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1272	{
<>	135:176b8275d35d	1273	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	135:176b8275d35d	1274	}
<>	135:176b8275d35d	1275
<>	135:176b8275d35d	1276	/**
<>	135:176b8275d35d	1277	* @brief Get Channel 3 transfer complete flag.
<>	135:176b8275d35d	1278	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	135:176b8275d35d	1279	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1280	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1281	*/
<>	135:176b8275d35d	1282	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1283	{
<>	135:176b8275d35d	1284	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	135:176b8275d35d	1285	}
<>	135:176b8275d35d	1286
<>	135:176b8275d35d	1287	/**
<>	135:176b8275d35d	1288	* @brief Get Channel 4 transfer complete flag.
<>	135:176b8275d35d	1289	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	135:176b8275d35d	1290	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1291	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1292	*/
<>	135:176b8275d35d	1293	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1294	{
<>	135:176b8275d35d	1295	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	135:176b8275d35d	1296	}
<>	135:176b8275d35d	1297
<>	135:176b8275d35d	1298	/**
<>	135:176b8275d35d	1299	* @brief Get Channel 5 transfer complete flag.
<>	135:176b8275d35d	1300	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	135:176b8275d35d	1301	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1302	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1303	*/
<>	135:176b8275d35d	1304	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1305	{
<>	135:176b8275d35d	1306	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	135:176b8275d35d	1307	}
<>	135:176b8275d35d	1308
<>	135:176b8275d35d	1309	/**
<>	135:176b8275d35d	1310	* @brief Get Channel 6 transfer complete flag.
<>	135:176b8275d35d	1311	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	135:176b8275d35d	1312	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1313	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1314	*/
<>	135:176b8275d35d	1315	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1316	{
<>	135:176b8275d35d	1317	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	135:176b8275d35d	1318	}
<>	135:176b8275d35d	1319
<>	135:176b8275d35d	1320	/**
<>	135:176b8275d35d	1321	* @brief Get Channel 7 transfer complete flag.
<>	135:176b8275d35d	1322	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	135:176b8275d35d	1323	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1324	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1325	*/
<>	135:176b8275d35d	1326	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1327	{
<>	135:176b8275d35d	1328	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	135:176b8275d35d	1329	}
<>	135:176b8275d35d	1330
<>	135:176b8275d35d	1331	/**
<>	135:176b8275d35d	1332	* @brief Get Channel 1 half transfer flag.
<>	135:176b8275d35d	1333	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	135:176b8275d35d	1334	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1335	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1336	*/
<>	135:176b8275d35d	1337	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1338	{
<>	135:176b8275d35d	1339	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	135:176b8275d35d	1340	}
<>	135:176b8275d35d	1341
<>	135:176b8275d35d	1342	/**
<>	135:176b8275d35d	1343	* @brief Get Channel 2 half transfer flag.
<>	135:176b8275d35d	1344	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	135:176b8275d35d	1345	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1346	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1347	*/
<>	135:176b8275d35d	1348	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1349	{
<>	135:176b8275d35d	1350	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	135:176b8275d35d	1351	}
<>	135:176b8275d35d	1352
<>	135:176b8275d35d	1353	/**
<>	135:176b8275d35d	1354	* @brief Get Channel 3 half transfer flag.
<>	135:176b8275d35d	1355	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	135:176b8275d35d	1356	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1357	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1358	*/
<>	135:176b8275d35d	1359	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1360	{
<>	135:176b8275d35d	1361	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	135:176b8275d35d	1362	}
<>	135:176b8275d35d	1363
<>	135:176b8275d35d	1364	/**
<>	135:176b8275d35d	1365	* @brief Get Channel 4 half transfer flag.
<>	135:176b8275d35d	1366	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	135:176b8275d35d	1367	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1368	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1369	*/
<>	135:176b8275d35d	1370	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1371	{
<>	135:176b8275d35d	1372	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	135:176b8275d35d	1373	}
<>	135:176b8275d35d	1374
<>	135:176b8275d35d	1375	/**
<>	135:176b8275d35d	1376	* @brief Get Channel 5 half transfer flag.
<>	135:176b8275d35d	1377	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	135:176b8275d35d	1378	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1379	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1380	*/
<>	135:176b8275d35d	1381	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1382	{
<>	135:176b8275d35d	1383	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	135:176b8275d35d	1384	}
<>	135:176b8275d35d	1385
<>	135:176b8275d35d	1386	/**
<>	135:176b8275d35d	1387	* @brief Get Channel 6 half transfer flag.
<>	135:176b8275d35d	1388	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	135:176b8275d35d	1389	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1390	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1391	*/
<>	135:176b8275d35d	1392	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1393	{
<>	135:176b8275d35d	1394	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	135:176b8275d35d	1395	}
<>	135:176b8275d35d	1396
<>	135:176b8275d35d	1397	/**
<>	135:176b8275d35d	1398	* @brief Get Channel 7 half transfer flag.
<>	135:176b8275d35d	1399	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	135:176b8275d35d	1400	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1401	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1402	*/
<>	135:176b8275d35d	1403	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1404	{
<>	135:176b8275d35d	1405	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	135:176b8275d35d	1406	}
<>	135:176b8275d35d	1407
<>	135:176b8275d35d	1408	/**
<>	135:176b8275d35d	1409	* @brief Get Channel 1 transfer error flag.
<>	135:176b8275d35d	1410	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	135:176b8275d35d	1411	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1412	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1413	*/
<>	135:176b8275d35d	1414	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1415	{
<>	135:176b8275d35d	1416	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	135:176b8275d35d	1417	}
<>	135:176b8275d35d	1418
<>	135:176b8275d35d	1419	/**
<>	135:176b8275d35d	1420	* @brief Get Channel 2 transfer error flag.
<>	135:176b8275d35d	1421	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	135:176b8275d35d	1422	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1423	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1424	*/
<>	135:176b8275d35d	1425	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1426	{
<>	135:176b8275d35d	1427	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	135:176b8275d35d	1428	}
<>	135:176b8275d35d	1429
<>	135:176b8275d35d	1430	/**
<>	135:176b8275d35d	1431	* @brief Get Channel 3 transfer error flag.
<>	135:176b8275d35d	1432	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	135:176b8275d35d	1433	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1434	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1435	*/
<>	135:176b8275d35d	1436	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1437	{
<>	135:176b8275d35d	1438	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	135:176b8275d35d	1439	}
<>	135:176b8275d35d	1440
<>	135:176b8275d35d	1441	/**
<>	135:176b8275d35d	1442	* @brief Get Channel 4 transfer error flag.
<>	135:176b8275d35d	1443	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	135:176b8275d35d	1444	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1445	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1446	*/
<>	135:176b8275d35d	1447	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1448	{
<>	135:176b8275d35d	1449	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	135:176b8275d35d	1450	}
<>	135:176b8275d35d	1451
<>	135:176b8275d35d	1452	/**
<>	135:176b8275d35d	1453	* @brief Get Channel 5 transfer error flag.
<>	135:176b8275d35d	1454	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	135:176b8275d35d	1455	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1456	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1457	*/
<>	135:176b8275d35d	1458	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1459	{
<>	135:176b8275d35d	1460	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	135:176b8275d35d	1461	}
<>	135:176b8275d35d	1462
<>	135:176b8275d35d	1463	/**
<>	135:176b8275d35d	1464	* @brief Get Channel 6 transfer error flag.
<>	135:176b8275d35d	1465	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	135:176b8275d35d	1466	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1467	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1468	*/
<>	135:176b8275d35d	1469	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1470	{
<>	135:176b8275d35d	1471	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	135:176b8275d35d	1472	}
<>	135:176b8275d35d	1473
<>	135:176b8275d35d	1474	/**
<>	135:176b8275d35d	1475	* @brief Get Channel 7 transfer error flag.
<>	135:176b8275d35d	1476	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	135:176b8275d35d	1477	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1478	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1479	*/
<>	135:176b8275d35d	1480	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1481	{
<>	135:176b8275d35d	1482	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	135:176b8275d35d	1483	}
<>	135:176b8275d35d	1484
<>	135:176b8275d35d	1485	/**
<>	135:176b8275d35d	1486	* @brief Clear Channel 1 global interrupt flag.
<>	135:176b8275d35d	1487	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	135:176b8275d35d	1488	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1489	* @retval None
<>	135:176b8275d35d	1490	*/
<>	135:176b8275d35d	1491	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1492	{
AnnaBridge	168:b9e159c1930a	1493	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	135:176b8275d35d	1494	}
<>	135:176b8275d35d	1495
<>	135:176b8275d35d	1496	/**
<>	135:176b8275d35d	1497	* @brief Clear Channel 2 global interrupt flag.
<>	135:176b8275d35d	1498	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	135:176b8275d35d	1499	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1500	* @retval None
<>	135:176b8275d35d	1501	*/
<>	135:176b8275d35d	1502	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1503	{
AnnaBridge	168:b9e159c1930a	1504	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	135:176b8275d35d	1505	}
<>	135:176b8275d35d	1506
<>	135:176b8275d35d	1507	/**
<>	135:176b8275d35d	1508	* @brief Clear Channel 3 global interrupt flag.
<>	135:176b8275d35d	1509	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	135:176b8275d35d	1510	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1511	* @retval None
<>	135:176b8275d35d	1512	*/
<>	135:176b8275d35d	1513	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1514	{
AnnaBridge	168:b9e159c1930a	1515	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	135:176b8275d35d	1516	}
<>	135:176b8275d35d	1517
<>	135:176b8275d35d	1518	/**
<>	135:176b8275d35d	1519	* @brief Clear Channel 4 global interrupt flag.
<>	135:176b8275d35d	1520	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	135:176b8275d35d	1521	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1522	* @retval None
<>	135:176b8275d35d	1523	*/
<>	135:176b8275d35d	1524	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1525	{
AnnaBridge	168:b9e159c1930a	1526	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	135:176b8275d35d	1527	}
<>	135:176b8275d35d	1528
<>	135:176b8275d35d	1529	/**
<>	135:176b8275d35d	1530	* @brief Clear Channel 5 global interrupt flag.
<>	135:176b8275d35d	1531	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	135:176b8275d35d	1532	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1533	* @retval None
<>	135:176b8275d35d	1534	*/
<>	135:176b8275d35d	1535	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1536	{
AnnaBridge	168:b9e159c1930a	1537	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	135:176b8275d35d	1538	}
<>	135:176b8275d35d	1539
<>	135:176b8275d35d	1540	/**
<>	135:176b8275d35d	1541	* @brief Clear Channel 6 global interrupt flag.
<>	135:176b8275d35d	1542	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	135:176b8275d35d	1543	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1544	* @retval None
<>	135:176b8275d35d	1545	*/
<>	135:176b8275d35d	1546	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1547	{
AnnaBridge	168:b9e159c1930a	1548	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	135:176b8275d35d	1549	}
<>	135:176b8275d35d	1550
<>	135:176b8275d35d	1551	/**
<>	135:176b8275d35d	1552	* @brief Clear Channel 7 global interrupt flag.
<>	135:176b8275d35d	1553	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	135:176b8275d35d	1554	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1555	* @retval None
<>	135:176b8275d35d	1556	*/
<>	135:176b8275d35d	1557	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1558	{
AnnaBridge	168:b9e159c1930a	1559	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	135:176b8275d35d	1560	}
<>	135:176b8275d35d	1561
<>	135:176b8275d35d	1562	/**
<>	135:176b8275d35d	1563	* @brief Clear Channel 1 transfer complete flag.
<>	135:176b8275d35d	1564	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	135:176b8275d35d	1565	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1566	* @retval None
<>	135:176b8275d35d	1567	*/
<>	135:176b8275d35d	1568	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1569	{
AnnaBridge	168:b9e159c1930a	1570	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	135:176b8275d35d	1571	}
<>	135:176b8275d35d	1572
<>	135:176b8275d35d	1573	/**
<>	135:176b8275d35d	1574	* @brief Clear Channel 2 transfer complete flag.
<>	135:176b8275d35d	1575	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	135:176b8275d35d	1576	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1577	* @retval None
<>	135:176b8275d35d	1578	*/
<>	135:176b8275d35d	1579	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1580	{
AnnaBridge	168:b9e159c1930a	1581	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	135:176b8275d35d	1582	}
<>	135:176b8275d35d	1583
<>	135:176b8275d35d	1584	/**
<>	135:176b8275d35d	1585	* @brief Clear Channel 3 transfer complete flag.
<>	135:176b8275d35d	1586	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	135:176b8275d35d	1587	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1588	* @retval None
<>	135:176b8275d35d	1589	*/
<>	135:176b8275d35d	1590	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1591	{
AnnaBridge	168:b9e159c1930a	1592	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	135:176b8275d35d	1593	}
<>	135:176b8275d35d	1594
<>	135:176b8275d35d	1595	/**
<>	135:176b8275d35d	1596	* @brief Clear Channel 4 transfer complete flag.
<>	135:176b8275d35d	1597	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	135:176b8275d35d	1598	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1599	* @retval None
<>	135:176b8275d35d	1600	*/
<>	135:176b8275d35d	1601	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1602	{
AnnaBridge	168:b9e159c1930a	1603	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	135:176b8275d35d	1604	}
<>	135:176b8275d35d	1605
<>	135:176b8275d35d	1606	/**
<>	135:176b8275d35d	1607	* @brief Clear Channel 5 transfer complete flag.
<>	135:176b8275d35d	1608	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	135:176b8275d35d	1609	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1610	* @retval None
<>	135:176b8275d35d	1611	*/
<>	135:176b8275d35d	1612	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1613	{
AnnaBridge	168:b9e159c1930a	1614	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	135:176b8275d35d	1615	}
<>	135:176b8275d35d	1616
<>	135:176b8275d35d	1617	/**
<>	135:176b8275d35d	1618	* @brief Clear Channel 6 transfer complete flag.
<>	135:176b8275d35d	1619	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	135:176b8275d35d	1620	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1621	* @retval None
<>	135:176b8275d35d	1622	*/
<>	135:176b8275d35d	1623	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1624	{
AnnaBridge	168:b9e159c1930a	1625	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	135:176b8275d35d	1626	}
<>	135:176b8275d35d	1627
<>	135:176b8275d35d	1628	/**
<>	135:176b8275d35d	1629	* @brief Clear Channel 7 transfer complete flag.
<>	135:176b8275d35d	1630	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	135:176b8275d35d	1631	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1632	* @retval None
<>	135:176b8275d35d	1633	*/
<>	135:176b8275d35d	1634	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1635	{
AnnaBridge	168:b9e159c1930a	1636	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	135:176b8275d35d	1637	}
<>	135:176b8275d35d	1638
<>	135:176b8275d35d	1639	/**
<>	135:176b8275d35d	1640	* @brief Clear Channel 1 half transfer flag.
<>	135:176b8275d35d	1641	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	135:176b8275d35d	1642	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1643	* @retval None
<>	135:176b8275d35d	1644	*/
<>	135:176b8275d35d	1645	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1646	{
AnnaBridge	168:b9e159c1930a	1647	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	135:176b8275d35d	1648	}
<>	135:176b8275d35d	1649
<>	135:176b8275d35d	1650	/**
<>	135:176b8275d35d	1651	* @brief Clear Channel 2 half transfer flag.
<>	135:176b8275d35d	1652	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	135:176b8275d35d	1653	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1654	* @retval None
<>	135:176b8275d35d	1655	*/
<>	135:176b8275d35d	1656	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1657	{
AnnaBridge	168:b9e159c1930a	1658	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	135:176b8275d35d	1659	}
<>	135:176b8275d35d	1660
<>	135:176b8275d35d	1661	/**
<>	135:176b8275d35d	1662	* @brief Clear Channel 3 half transfer flag.
<>	135:176b8275d35d	1663	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	135:176b8275d35d	1664	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1665	* @retval None
<>	135:176b8275d35d	1666	*/
<>	135:176b8275d35d	1667	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1668	{
AnnaBridge	168:b9e159c1930a	1669	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	135:176b8275d35d	1670	}
<>	135:176b8275d35d	1671
<>	135:176b8275d35d	1672	/**
<>	135:176b8275d35d	1673	* @brief Clear Channel 4 half transfer flag.
<>	135:176b8275d35d	1674	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	135:176b8275d35d	1675	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1676	* @retval None
<>	135:176b8275d35d	1677	*/
<>	135:176b8275d35d	1678	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1679	{
AnnaBridge	168:b9e159c1930a	1680	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	135:176b8275d35d	1681	}
<>	135:176b8275d35d	1682
<>	135:176b8275d35d	1683	/**
<>	135:176b8275d35d	1684	* @brief Clear Channel 5 half transfer flag.
<>	135:176b8275d35d	1685	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	135:176b8275d35d	1686	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1687	* @retval None
<>	135:176b8275d35d	1688	*/
<>	135:176b8275d35d	1689	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1690	{
AnnaBridge	168:b9e159c1930a	1691	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	135:176b8275d35d	1692	}
<>	135:176b8275d35d	1693
<>	135:176b8275d35d	1694	/**
<>	135:176b8275d35d	1695	* @brief Clear Channel 6 half transfer flag.
<>	135:176b8275d35d	1696	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	135:176b8275d35d	1697	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1698	* @retval None
<>	135:176b8275d35d	1699	*/
<>	135:176b8275d35d	1700	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1701	{
AnnaBridge	168:b9e159c1930a	1702	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	135:176b8275d35d	1703	}
<>	135:176b8275d35d	1704
<>	135:176b8275d35d	1705	/**
<>	135:176b8275d35d	1706	* @brief Clear Channel 7 half transfer flag.
<>	135:176b8275d35d	1707	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	135:176b8275d35d	1708	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1709	* @retval None
<>	135:176b8275d35d	1710	*/
<>	135:176b8275d35d	1711	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1712	{
AnnaBridge	168:b9e159c1930a	1713	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	135:176b8275d35d	1714	}
<>	135:176b8275d35d	1715
<>	135:176b8275d35d	1716	/**
<>	135:176b8275d35d	1717	* @brief Clear Channel 1 transfer error flag.
<>	135:176b8275d35d	1718	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	135:176b8275d35d	1719	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1720	* @retval None
<>	135:176b8275d35d	1721	*/
<>	135:176b8275d35d	1722	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1723	{
AnnaBridge	168:b9e159c1930a	1724	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	135:176b8275d35d	1725	}
<>	135:176b8275d35d	1726
<>	135:176b8275d35d	1727	/**
<>	135:176b8275d35d	1728	* @brief Clear Channel 2 transfer error flag.
<>	135:176b8275d35d	1729	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	135:176b8275d35d	1730	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1731	* @retval None
<>	135:176b8275d35d	1732	*/
<>	135:176b8275d35d	1733	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1734	{
AnnaBridge	168:b9e159c1930a	1735	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	135:176b8275d35d	1736	}
<>	135:176b8275d35d	1737
<>	135:176b8275d35d	1738	/**
<>	135:176b8275d35d	1739	* @brief Clear Channel 3 transfer error flag.
<>	135:176b8275d35d	1740	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	135:176b8275d35d	1741	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1742	* @retval None
<>	135:176b8275d35d	1743	*/
<>	135:176b8275d35d	1744	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1745	{
AnnaBridge	168:b9e159c1930a	1746	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	135:176b8275d35d	1747	}
<>	135:176b8275d35d	1748
<>	135:176b8275d35d	1749	/**
<>	135:176b8275d35d	1750	* @brief Clear Channel 4 transfer error flag.
<>	135:176b8275d35d	1751	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	135:176b8275d35d	1752	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1753	* @retval None
<>	135:176b8275d35d	1754	*/
<>	135:176b8275d35d	1755	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1756	{
AnnaBridge	168:b9e159c1930a	1757	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	135:176b8275d35d	1758	}
<>	135:176b8275d35d	1759
<>	135:176b8275d35d	1760	/**
<>	135:176b8275d35d	1761	* @brief Clear Channel 5 transfer error flag.
<>	135:176b8275d35d	1762	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	135:176b8275d35d	1763	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1764	* @retval None
<>	135:176b8275d35d	1765	*/
<>	135:176b8275d35d	1766	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1767	{
AnnaBridge	168:b9e159c1930a	1768	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	135:176b8275d35d	1769	}
<>	135:176b8275d35d	1770
<>	135:176b8275d35d	1771	/**
<>	135:176b8275d35d	1772	* @brief Clear Channel 6 transfer error flag.
<>	135:176b8275d35d	1773	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	135:176b8275d35d	1774	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1775	* @retval None
<>	135:176b8275d35d	1776	*/
<>	135:176b8275d35d	1777	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1778	{
AnnaBridge	168:b9e159c1930a	1779	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	135:176b8275d35d	1780	}
<>	135:176b8275d35d	1781
<>	135:176b8275d35d	1782	/**
<>	135:176b8275d35d	1783	* @brief Clear Channel 7 transfer error flag.
<>	135:176b8275d35d	1784	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	135:176b8275d35d	1785	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1786	* @retval None
<>	135:176b8275d35d	1787	*/
<>	135:176b8275d35d	1788	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	135:176b8275d35d	1789	{
AnnaBridge	168:b9e159c1930a	1790	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	135:176b8275d35d	1791	}
<>	135:176b8275d35d	1792
<>	135:176b8275d35d	1793	/**
<>	135:176b8275d35d	1794	* @}
<>	135:176b8275d35d	1795	*/
<>	135:176b8275d35d	1796
<>	135:176b8275d35d	1797	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	135:176b8275d35d	1798	* @{
<>	135:176b8275d35d	1799	*/
<>	135:176b8275d35d	1800	/**
<>	135:176b8275d35d	1801	* @brief Enable Transfer complete interrupt.
<>	135:176b8275d35d	1802	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	135:176b8275d35d	1803	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1804	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1805	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1806	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1807	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1808	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1809	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1810	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1811	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1812	* @retval None
<>	135:176b8275d35d	1813	*/
<>	135:176b8275d35d	1814	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1815	{
<>	135:176b8275d35d	1816	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	135:176b8275d35d	1817	}
<>	135:176b8275d35d	1818
<>	135:176b8275d35d	1819	/**
<>	135:176b8275d35d	1820	* @brief Enable Half transfer interrupt.
<>	135:176b8275d35d	1821	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	135:176b8275d35d	1822	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1823	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1824	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1825	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1826	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1827	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1828	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1829	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1830	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1831	* @retval None
<>	135:176b8275d35d	1832	*/
<>	135:176b8275d35d	1833	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1834	{
<>	135:176b8275d35d	1835	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	135:176b8275d35d	1836	}
<>	135:176b8275d35d	1837
<>	135:176b8275d35d	1838	/**
<>	135:176b8275d35d	1839	* @brief Enable Transfer error interrupt.
<>	135:176b8275d35d	1840	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	135:176b8275d35d	1841	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1842	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1843	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1844	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1845	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1846	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1847	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1848	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1849	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1850	* @retval None
<>	135:176b8275d35d	1851	*/
<>	135:176b8275d35d	1852	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1853	{
<>	135:176b8275d35d	1854	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	135:176b8275d35d	1855	}
<>	135:176b8275d35d	1856
<>	135:176b8275d35d	1857	/**
<>	135:176b8275d35d	1858	* @brief Disable Transfer complete interrupt.
<>	135:176b8275d35d	1859	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	135:176b8275d35d	1860	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1861	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1862	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1863	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1864	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1865	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1866	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1867	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1868	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1869	* @retval None
<>	135:176b8275d35d	1870	*/
<>	135:176b8275d35d	1871	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1872	{
<>	135:176b8275d35d	1873	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	135:176b8275d35d	1874	}
<>	135:176b8275d35d	1875
<>	135:176b8275d35d	1876	/**
<>	135:176b8275d35d	1877	* @brief Disable Half transfer interrupt.
<>	135:176b8275d35d	1878	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	135:176b8275d35d	1879	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1880	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1881	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1882	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1883	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1884	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1885	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1886	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1887	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1888	* @retval None
<>	135:176b8275d35d	1889	*/
<>	135:176b8275d35d	1890	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1891	{
<>	135:176b8275d35d	1892	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	135:176b8275d35d	1893	}
<>	135:176b8275d35d	1894
<>	135:176b8275d35d	1895	/**
<>	135:176b8275d35d	1896	* @brief Disable Transfer error interrupt.
<>	135:176b8275d35d	1897	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	135:176b8275d35d	1898	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1899	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1900	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1901	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1902	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1903	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1904	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1905	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1906	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1907	* @retval None
<>	135:176b8275d35d	1908	*/
<>	135:176b8275d35d	1909	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1910	{
<>	135:176b8275d35d	1911	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	135:176b8275d35d	1912	}
<>	135:176b8275d35d	1913
<>	135:176b8275d35d	1914	/**
<>	135:176b8275d35d	1915	* @brief Check if Transfer complete Interrupt is enabled.
<>	135:176b8275d35d	1916	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	135:176b8275d35d	1917	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1918	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1919	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1920	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1921	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1922	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1923	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1924	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1925	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1926	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1927	*/
<>	135:176b8275d35d	1928	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1929	{
<>	135:176b8275d35d	1930	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1931	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	135:176b8275d35d	1932	}
<>	135:176b8275d35d	1933
<>	135:176b8275d35d	1934	/**
<>	135:176b8275d35d	1935	* @brief Check if Half transfer Interrupt is enabled.
<>	135:176b8275d35d	1936	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	135:176b8275d35d	1937	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1938	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1939	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1940	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1941	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1942	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1943	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1944	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1945	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1946	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1947	*/
<>	135:176b8275d35d	1948	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1949	{
<>	135:176b8275d35d	1950	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1951	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	135:176b8275d35d	1952	}
<>	135:176b8275d35d	1953
<>	135:176b8275d35d	1954	/**
<>	135:176b8275d35d	1955	* @brief Check if Transfer error Interrupt is enabled.
<>	135:176b8275d35d	1956	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	135:176b8275d35d	1957	* @param DMAx DMAx Instance
<>	135:176b8275d35d	1958	* @param Channel This parameter can be one of the following values:
<>	135:176b8275d35d	1959	* @arg @ref LL_DMA_CHANNEL_1
<>	135:176b8275d35d	1960	* @arg @ref LL_DMA_CHANNEL_2
<>	135:176b8275d35d	1961	* @arg @ref LL_DMA_CHANNEL_3
<>	135:176b8275d35d	1962	* @arg @ref LL_DMA_CHANNEL_4
<>	135:176b8275d35d	1963	* @arg @ref LL_DMA_CHANNEL_5
<>	135:176b8275d35d	1964	* @arg @ref LL_DMA_CHANNEL_6
<>	135:176b8275d35d	1965	* @arg @ref LL_DMA_CHANNEL_7
<>	135:176b8275d35d	1966	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1967	*/
<>	135:176b8275d35d	1968	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	135:176b8275d35d	1969	{
<>	135:176b8275d35d	1970	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	135:176b8275d35d	1971	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	135:176b8275d35d	1972	}
<>	135:176b8275d35d	1973
<>	135:176b8275d35d	1974	/**
<>	135:176b8275d35d	1975	* @}
<>	135:176b8275d35d	1976	*/
<>	135:176b8275d35d	1977
<>	135:176b8275d35d	1978	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	1979	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	135:176b8275d35d	1980	* @{
<>	135:176b8275d35d	1981	*/
<>	135:176b8275d35d	1982
<>	135:176b8275d35d	1983	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	135:176b8275d35d	1984	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	135:176b8275d35d	1985	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	135:176b8275d35d	1986
<>	135:176b8275d35d	1987	/**
<>	135:176b8275d35d	1988	* @}
<>	135:176b8275d35d	1989	*/
<>	135:176b8275d35d	1990	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	1991
<>	135:176b8275d35d	1992	/**
<>	135:176b8275d35d	1993	* @}
<>	135:176b8275d35d	1994	*/
<>	135:176b8275d35d	1995
<>	135:176b8275d35d	1996	/**
<>	135:176b8275d35d	1997	* @}
<>	135:176b8275d35d	1998	*/
<>	135:176b8275d35d	1999
<>	135:176b8275d35d	2000	#endif /* DMA1 \|\| DMA2 */
<>	135:176b8275d35d	2001
<>	135:176b8275d35d	2002	/**
<>	135:176b8275d35d	2003	* @}
<>	135:176b8275d35d	2004	*/
<>	135:176b8275d35d	2005
<>	135:176b8275d35d	2006	#ifdef __cplusplus
<>	135:176b8275d35d	2007	}
<>	135:176b8275d35d	2008	#endif
<>	135:176b8275d35d	2009
<>	135:176b8275d35d	2010	#endif /* __STM32F3xx_LL_DMA_H */
<>	135:176b8275d35d	2011
<>	135:176b8275d35d	2012	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/