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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_bus.h@136:ef9c61f8c49f, 2017-02-14 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 14 11:24:20 2017 +0000
- Revision:
- 136:ef9c61f8c49f
- Parent:
- 135:176b8275d35d
- Child:
- 168:b9e159c1930a
Release 136 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 135:176b8275d35d | 1 | /** |
<> | 135:176b8275d35d | 2 | ****************************************************************************** |
<> | 135:176b8275d35d | 3 | * @file stm32f3xx_ll_bus.h |
<> | 135:176b8275d35d | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
<> | 135:176b8275d35d | 7 | * @brief Header file of BUS LL module. |
<> | 135:176b8275d35d | 8 | |
<> | 135:176b8275d35d | 9 | @verbatim |
<> | 135:176b8275d35d | 10 | ##### RCC Limitations ##### |
<> | 135:176b8275d35d | 11 | ============================================================================== |
<> | 135:176b8275d35d | 12 | [..] |
<> | 135:176b8275d35d | 13 | A delay between an RCC peripheral clock enable and the effective peripheral |
<> | 135:176b8275d35d | 14 | enabling should be taken into account in order to manage the peripheral read/write |
<> | 135:176b8275d35d | 15 | from/to registers. |
<> | 135:176b8275d35d | 16 | (+) This delay depends on the peripheral mapping. |
<> | 135:176b8275d35d | 17 | (++) AHB & APB peripherals, 1 dummy read is necessary |
<> | 135:176b8275d35d | 18 | |
<> | 135:176b8275d35d | 19 | [..] |
<> | 135:176b8275d35d | 20 | Workarounds: |
<> | 135:176b8275d35d | 21 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
<> | 135:176b8275d35d | 22 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
<> | 135:176b8275d35d | 23 | |
<> | 135:176b8275d35d | 24 | @endverbatim |
<> | 135:176b8275d35d | 25 | ****************************************************************************** |
<> | 135:176b8275d35d | 26 | * @attention |
<> | 135:176b8275d35d | 27 | * |
<> | 135:176b8275d35d | 28 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 135:176b8275d35d | 29 | * |
<> | 135:176b8275d35d | 30 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 135:176b8275d35d | 31 | * are permitted provided that the following conditions are met: |
<> | 135:176b8275d35d | 32 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 135:176b8275d35d | 33 | * this list of conditions and the following disclaimer. |
<> | 135:176b8275d35d | 34 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 135:176b8275d35d | 35 | * this list of conditions and the following disclaimer in the documentation |
<> | 135:176b8275d35d | 36 | * and/or other materials provided with the distribution. |
<> | 135:176b8275d35d | 37 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 135:176b8275d35d | 38 | * may be used to endorse or promote products derived from this software |
<> | 135:176b8275d35d | 39 | * without specific prior written permission. |
<> | 135:176b8275d35d | 40 | * |
<> | 135:176b8275d35d | 41 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 135:176b8275d35d | 42 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 135:176b8275d35d | 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 135:176b8275d35d | 44 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 135:176b8275d35d | 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 135:176b8275d35d | 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 135:176b8275d35d | 47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 135:176b8275d35d | 48 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 135:176b8275d35d | 49 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 135:176b8275d35d | 50 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 135:176b8275d35d | 51 | * |
<> | 135:176b8275d35d | 52 | ****************************************************************************** |
<> | 135:176b8275d35d | 53 | */ |
<> | 135:176b8275d35d | 54 | |
<> | 135:176b8275d35d | 55 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 135:176b8275d35d | 56 | #ifndef __STM32F3xx_LL_BUS_H |
<> | 135:176b8275d35d | 57 | #define __STM32F3xx_LL_BUS_H |
<> | 135:176b8275d35d | 58 | |
<> | 135:176b8275d35d | 59 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 60 | extern "C" { |
<> | 135:176b8275d35d | 61 | #endif |
<> | 135:176b8275d35d | 62 | |
<> | 135:176b8275d35d | 63 | /* Includes ------------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 64 | #include "stm32f3xx.h" |
<> | 135:176b8275d35d | 65 | |
<> | 135:176b8275d35d | 66 | /** @addtogroup STM32F3xx_LL_Driver |
<> | 135:176b8275d35d | 67 | * @{ |
<> | 135:176b8275d35d | 68 | */ |
<> | 135:176b8275d35d | 69 | |
<> | 135:176b8275d35d | 70 | #if defined(RCC) |
<> | 135:176b8275d35d | 71 | |
<> | 135:176b8275d35d | 72 | /** @defgroup BUS_LL BUS |
<> | 135:176b8275d35d | 73 | * @{ |
<> | 135:176b8275d35d | 74 | */ |
<> | 135:176b8275d35d | 75 | |
<> | 135:176b8275d35d | 76 | /* Private types -------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 77 | /* Private variables ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 78 | |
<> | 135:176b8275d35d | 79 | /* Private constants ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 80 | |
<> | 135:176b8275d35d | 81 | /* Private macros ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 82 | |
<> | 135:176b8275d35d | 83 | /* Exported types ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 84 | /* Exported constants --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 85 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
<> | 135:176b8275d35d | 86 | * @{ |
<> | 135:176b8275d35d | 87 | */ |
<> | 135:176b8275d35d | 88 | |
<> | 135:176b8275d35d | 89 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
<> | 135:176b8275d35d | 90 | * @{ |
<> | 135:176b8275d35d | 91 | */ |
<> | 135:176b8275d35d | 92 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
<> | 135:176b8275d35d | 93 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN |
<> | 135:176b8275d35d | 94 | #if defined(DMA2) |
<> | 135:176b8275d35d | 95 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN |
<> | 135:176b8275d35d | 96 | #endif /*DMA2*/ |
<> | 135:176b8275d35d | 97 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN |
<> | 135:176b8275d35d | 98 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN |
<> | 135:176b8275d35d | 99 | #if defined(FMC_Bank1) |
<> | 135:176b8275d35d | 100 | #define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN |
<> | 135:176b8275d35d | 101 | #endif /*FMC_Bank1*/ |
<> | 135:176b8275d35d | 102 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN |
<> | 135:176b8275d35d | 103 | #if defined(GPIOH) |
<> | 135:176b8275d35d | 104 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN |
<> | 135:176b8275d35d | 105 | #endif /*GPIOH*/ |
<> | 135:176b8275d35d | 106 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN |
<> | 135:176b8275d35d | 107 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN |
<> | 135:176b8275d35d | 108 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN |
<> | 135:176b8275d35d | 109 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN |
<> | 135:176b8275d35d | 110 | #if defined(GPIOE) |
<> | 135:176b8275d35d | 111 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN |
<> | 135:176b8275d35d | 112 | #endif /*GPIOE*/ |
<> | 135:176b8275d35d | 113 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN |
<> | 135:176b8275d35d | 114 | #if defined(GPIOG) |
<> | 135:176b8275d35d | 115 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN |
<> | 135:176b8275d35d | 116 | #endif /*GPIOH*/ |
<> | 135:176b8275d35d | 117 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN |
<> | 135:176b8275d35d | 118 | #if defined(RCC_AHBENR_ADC1EN) |
<> | 135:176b8275d35d | 119 | #define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN |
<> | 135:176b8275d35d | 120 | #endif /*RCC_AHBENR_ADC1EN*/ |
<> | 135:176b8275d35d | 121 | #if defined(ADC1_2_COMMON) |
<> | 135:176b8275d35d | 122 | #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN |
<> | 135:176b8275d35d | 123 | #endif /*ADC1_2_COMMON*/ |
<> | 135:176b8275d35d | 124 | #if defined(ADC3_4_COMMON) |
<> | 135:176b8275d35d | 125 | #define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN |
<> | 135:176b8275d35d | 126 | #endif /*ADC3_4_COMMON*/ |
<> | 135:176b8275d35d | 127 | /** |
<> | 135:176b8275d35d | 128 | * @} |
<> | 135:176b8275d35d | 129 | */ |
<> | 135:176b8275d35d | 130 | |
<> | 135:176b8275d35d | 131 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
<> | 135:176b8275d35d | 132 | * @{ |
<> | 135:176b8275d35d | 133 | */ |
<> | 135:176b8275d35d | 134 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
<> | 135:176b8275d35d | 135 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
<> | 135:176b8275d35d | 136 | #if defined(TIM3) |
<> | 135:176b8275d35d | 137 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
<> | 135:176b8275d35d | 138 | #endif /*TIM3*/ |
<> | 135:176b8275d35d | 139 | #if defined(TIM4) |
<> | 135:176b8275d35d | 140 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
<> | 135:176b8275d35d | 141 | #endif /*TIM4*/ |
<> | 135:176b8275d35d | 142 | #if defined(TIM5) |
<> | 135:176b8275d35d | 143 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
<> | 135:176b8275d35d | 144 | #endif /*TIM5*/ |
<> | 135:176b8275d35d | 145 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
<> | 135:176b8275d35d | 146 | #if defined(TIM7) |
<> | 135:176b8275d35d | 147 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
<> | 135:176b8275d35d | 148 | #endif /*TIM7*/ |
<> | 135:176b8275d35d | 149 | #if defined(TIM12) |
<> | 135:176b8275d35d | 150 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
<> | 135:176b8275d35d | 151 | #endif /*TIM12*/ |
<> | 135:176b8275d35d | 152 | #if defined(TIM13) |
<> | 135:176b8275d35d | 153 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
<> | 135:176b8275d35d | 154 | #endif /*TIM13*/ |
<> | 135:176b8275d35d | 155 | #if defined(TIM14) |
<> | 135:176b8275d35d | 156 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
<> | 135:176b8275d35d | 157 | #endif /*TIM14*/ |
<> | 135:176b8275d35d | 158 | #if defined(TIM18) |
<> | 135:176b8275d35d | 159 | #define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN |
<> | 135:176b8275d35d | 160 | #endif /*TIM18*/ |
<> | 135:176b8275d35d | 161 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
<> | 135:176b8275d35d | 162 | #if defined(SPI2) |
<> | 135:176b8275d35d | 163 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
<> | 135:176b8275d35d | 164 | #endif /*SPI2*/ |
<> | 135:176b8275d35d | 165 | #if defined(SPI3) |
<> | 135:176b8275d35d | 166 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
<> | 135:176b8275d35d | 167 | #endif /*SPI3*/ |
<> | 135:176b8275d35d | 168 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
<> | 135:176b8275d35d | 169 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
<> | 135:176b8275d35d | 170 | #if defined(UART4) |
<> | 135:176b8275d35d | 171 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
<> | 135:176b8275d35d | 172 | #endif /*UART4*/ |
<> | 135:176b8275d35d | 173 | #if defined(UART5) |
<> | 135:176b8275d35d | 174 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
<> | 135:176b8275d35d | 175 | #endif /*UART5*/ |
<> | 135:176b8275d35d | 176 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
<> | 135:176b8275d35d | 177 | #if defined(I2C2) |
<> | 135:176b8275d35d | 178 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
<> | 135:176b8275d35d | 179 | #endif /*I2C2*/ |
<> | 135:176b8275d35d | 180 | #if defined(USB) |
<> | 135:176b8275d35d | 181 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN |
<> | 135:176b8275d35d | 182 | #endif /*USB*/ |
<> | 135:176b8275d35d | 183 | #if defined(CAN) |
<> | 135:176b8275d35d | 184 | #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN |
<> | 135:176b8275d35d | 185 | #endif /*CAN*/ |
<> | 135:176b8275d35d | 186 | #if defined(DAC2) |
<> | 135:176b8275d35d | 187 | #define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN |
<> | 135:176b8275d35d | 188 | #endif /*DAC2*/ |
<> | 135:176b8275d35d | 189 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
<> | 135:176b8275d35d | 190 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN |
<> | 135:176b8275d35d | 191 | #if defined(CEC) |
<> | 135:176b8275d35d | 192 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
<> | 135:176b8275d35d | 193 | #endif /*CEC*/ |
<> | 135:176b8275d35d | 194 | #if defined(I2C3) |
<> | 135:176b8275d35d | 195 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN |
<> | 135:176b8275d35d | 196 | #endif /*I2C3*/ |
<> | 135:176b8275d35d | 197 | /** |
<> | 135:176b8275d35d | 198 | * @} |
<> | 135:176b8275d35d | 199 | */ |
<> | 135:176b8275d35d | 200 | |
<> | 135:176b8275d35d | 201 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
<> | 135:176b8275d35d | 202 | * @{ |
<> | 135:176b8275d35d | 203 | */ |
<> | 135:176b8275d35d | 204 | #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
<> | 135:176b8275d35d | 205 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
<> | 135:176b8275d35d | 206 | #if defined(RCC_APB2ENR_ADC1EN) |
<> | 135:176b8275d35d | 207 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
<> | 135:176b8275d35d | 208 | #endif /*RCC_APB2ENR_ADC1EN*/ |
<> | 135:176b8275d35d | 209 | #if defined(TIM1) |
<> | 135:176b8275d35d | 210 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
<> | 135:176b8275d35d | 211 | #endif /*TIM1*/ |
<> | 135:176b8275d35d | 212 | #if defined(SPI1) |
<> | 135:176b8275d35d | 213 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
<> | 135:176b8275d35d | 214 | #endif /*SPI1*/ |
<> | 135:176b8275d35d | 215 | #if defined(TIM8) |
<> | 135:176b8275d35d | 216 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
<> | 135:176b8275d35d | 217 | #endif /*TIM8*/ |
<> | 135:176b8275d35d | 218 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
<> | 135:176b8275d35d | 219 | #if defined(SPI4) |
<> | 135:176b8275d35d | 220 | #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN |
<> | 135:176b8275d35d | 221 | #endif /*SPI4*/ |
<> | 135:176b8275d35d | 222 | #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN |
<> | 135:176b8275d35d | 223 | #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN |
<> | 135:176b8275d35d | 224 | #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN |
<> | 135:176b8275d35d | 225 | #if defined(TIM19) |
<> | 135:176b8275d35d | 226 | #define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN |
<> | 135:176b8275d35d | 227 | #endif /*TIM19*/ |
<> | 135:176b8275d35d | 228 | #if defined(TIM20) |
<> | 135:176b8275d35d | 229 | #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN |
<> | 135:176b8275d35d | 230 | #endif /*TIM20*/ |
<> | 135:176b8275d35d | 231 | #if defined(HRTIM1) |
<> | 135:176b8275d35d | 232 | #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN |
<> | 135:176b8275d35d | 233 | #endif /*HRTIM1*/ |
<> | 135:176b8275d35d | 234 | #if defined(SDADC1) |
<> | 135:176b8275d35d | 235 | #define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN |
<> | 135:176b8275d35d | 236 | #endif /*SDADC1*/ |
<> | 135:176b8275d35d | 237 | #if defined(SDADC2) |
<> | 135:176b8275d35d | 238 | #define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN |
<> | 135:176b8275d35d | 239 | #endif /*SDADC2*/ |
<> | 135:176b8275d35d | 240 | #if defined(SDADC3) |
<> | 135:176b8275d35d | 241 | #define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN |
<> | 135:176b8275d35d | 242 | #endif /*SDADC3*/ |
<> | 135:176b8275d35d | 243 | /** |
<> | 135:176b8275d35d | 244 | * @} |
<> | 135:176b8275d35d | 245 | */ |
<> | 135:176b8275d35d | 246 | |
<> | 135:176b8275d35d | 247 | /** |
<> | 135:176b8275d35d | 248 | * @} |
<> | 135:176b8275d35d | 249 | */ |
<> | 135:176b8275d35d | 250 | |
<> | 135:176b8275d35d | 251 | /* Exported macro ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 252 | |
<> | 135:176b8275d35d | 253 | /* Exported functions --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 254 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
<> | 135:176b8275d35d | 255 | * @{ |
<> | 135:176b8275d35d | 256 | */ |
<> | 135:176b8275d35d | 257 | |
<> | 135:176b8275d35d | 258 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
<> | 135:176b8275d35d | 259 | * @{ |
<> | 135:176b8275d35d | 260 | */ |
<> | 135:176b8275d35d | 261 | |
<> | 135:176b8275d35d | 262 | /** |
<> | 135:176b8275d35d | 263 | * @brief Enable AHB1 peripherals clock. |
<> | 135:176b8275d35d | 264 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 265 | * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 266 | * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 267 | * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 268 | * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 269 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 270 | * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 271 | * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 272 | * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 273 | * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 274 | * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 275 | * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 276 | * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 277 | * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 278 | * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 279 | * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 280 | * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 281 | * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock |
<> | 135:176b8275d35d | 282 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 283 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
<> | 135:176b8275d35d | 284 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
<> | 135:176b8275d35d | 285 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
<> | 135:176b8275d35d | 286 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
<> | 135:176b8275d35d | 287 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
<> | 135:176b8275d35d | 288 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
<> | 135:176b8275d35d | 289 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
<> | 135:176b8275d35d | 290 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
<> | 135:176b8275d35d | 291 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
<> | 135:176b8275d35d | 292 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
<> | 135:176b8275d35d | 293 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
<> | 135:176b8275d35d | 294 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
<> | 135:176b8275d35d | 295 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
<> | 135:176b8275d35d | 296 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
<> | 135:176b8275d35d | 297 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
<> | 135:176b8275d35d | 298 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 299 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
<> | 135:176b8275d35d | 300 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
<> | 135:176b8275d35d | 301 | * |
<> | 135:176b8275d35d | 302 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 303 | * @retval None |
<> | 135:176b8275d35d | 304 | */ |
<> | 135:176b8275d35d | 305 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 306 | { |
<> | 135:176b8275d35d | 307 | __IO uint32_t tmpreg; |
<> | 135:176b8275d35d | 308 | SET_BIT(RCC->AHBENR, Periphs); |
<> | 135:176b8275d35d | 309 | /* Delay after an RCC peripheral clock enabling */ |
<> | 135:176b8275d35d | 310 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
<> | 135:176b8275d35d | 311 | (void)tmpreg; |
<> | 135:176b8275d35d | 312 | } |
<> | 135:176b8275d35d | 313 | |
<> | 135:176b8275d35d | 314 | /** |
<> | 135:176b8275d35d | 315 | * @brief Check if AHB1 peripheral clock is enabled or not |
<> | 135:176b8275d35d | 316 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 317 | * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 318 | * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 319 | * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 320 | * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 321 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 322 | * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 323 | * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 324 | * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 325 | * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 326 | * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 327 | * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 328 | * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 329 | * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 330 | * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 331 | * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 332 | * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 333 | * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock |
<> | 135:176b8275d35d | 334 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
<> | 135:176b8275d35d | 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
<> | 135:176b8275d35d | 337 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
<> | 135:176b8275d35d | 338 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
<> | 135:176b8275d35d | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
<> | 135:176b8275d35d | 340 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
<> | 135:176b8275d35d | 341 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
<> | 135:176b8275d35d | 342 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
<> | 135:176b8275d35d | 343 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
<> | 135:176b8275d35d | 344 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
<> | 135:176b8275d35d | 345 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
<> | 135:176b8275d35d | 346 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
<> | 135:176b8275d35d | 347 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
<> | 135:176b8275d35d | 348 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
<> | 135:176b8275d35d | 349 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
<> | 135:176b8275d35d | 350 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 351 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
<> | 135:176b8275d35d | 352 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
<> | 135:176b8275d35d | 353 | * |
<> | 135:176b8275d35d | 354 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 355 | * @retval State of Periphs (1 or 0). |
<> | 135:176b8275d35d | 356 | */ |
<> | 135:176b8275d35d | 357 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 358 | { |
<> | 135:176b8275d35d | 359 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
<> | 135:176b8275d35d | 360 | } |
<> | 135:176b8275d35d | 361 | |
<> | 135:176b8275d35d | 362 | /** |
<> | 135:176b8275d35d | 363 | * @brief Disable AHB1 peripherals clock. |
<> | 135:176b8275d35d | 364 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 365 | * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 366 | * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 367 | * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 368 | * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 369 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 370 | * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 371 | * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 372 | * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 373 | * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 374 | * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 375 | * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 376 | * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 377 | * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 378 | * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 379 | * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 380 | * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 381 | * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock |
<> | 135:176b8275d35d | 382 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 383 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
<> | 135:176b8275d35d | 384 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
<> | 135:176b8275d35d | 385 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
<> | 135:176b8275d35d | 386 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
<> | 135:176b8275d35d | 387 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
<> | 135:176b8275d35d | 388 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
<> | 135:176b8275d35d | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
<> | 135:176b8275d35d | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
<> | 135:176b8275d35d | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
<> | 135:176b8275d35d | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
<> | 135:176b8275d35d | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
<> | 135:176b8275d35d | 394 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
<> | 135:176b8275d35d | 395 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
<> | 135:176b8275d35d | 396 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
<> | 135:176b8275d35d | 397 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
<> | 135:176b8275d35d | 398 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 399 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
<> | 135:176b8275d35d | 400 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
<> | 135:176b8275d35d | 401 | * |
<> | 135:176b8275d35d | 402 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 403 | * @retval None |
<> | 135:176b8275d35d | 404 | */ |
<> | 135:176b8275d35d | 405 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 406 | { |
<> | 135:176b8275d35d | 407 | CLEAR_BIT(RCC->AHBENR, Periphs); |
<> | 135:176b8275d35d | 408 | } |
<> | 135:176b8275d35d | 409 | |
<> | 135:176b8275d35d | 410 | /** |
<> | 135:176b8275d35d | 411 | * @brief Force AHB1 peripherals reset. |
<> | 135:176b8275d35d | 412 | * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 413 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 414 | * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 415 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 416 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 417 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 418 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 419 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 420 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 421 | * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 422 | * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 423 | * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 424 | * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset |
<> | 135:176b8275d35d | 425 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 426 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 427 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
<> | 135:176b8275d35d | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
<> | 135:176b8275d35d | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
<> | 135:176b8275d35d | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
<> | 135:176b8275d35d | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
<> | 135:176b8275d35d | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
<> | 135:176b8275d35d | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
<> | 135:176b8275d35d | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
<> | 135:176b8275d35d | 435 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
<> | 135:176b8275d35d | 436 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
<> | 135:176b8275d35d | 437 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 438 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
<> | 135:176b8275d35d | 439 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
<> | 135:176b8275d35d | 440 | * |
<> | 135:176b8275d35d | 441 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 442 | * @retval None |
<> | 135:176b8275d35d | 443 | */ |
<> | 135:176b8275d35d | 444 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 445 | { |
<> | 135:176b8275d35d | 446 | SET_BIT(RCC->AHBRSTR, Periphs); |
<> | 135:176b8275d35d | 447 | } |
<> | 135:176b8275d35d | 448 | |
<> | 135:176b8275d35d | 449 | /** |
<> | 135:176b8275d35d | 450 | * @brief Release AHB1 peripherals reset. |
<> | 135:176b8275d35d | 451 | * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 452 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 453 | * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 454 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 455 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 456 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 457 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 458 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 459 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 460 | * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 461 | * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 462 | * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 463 | * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset |
<> | 135:176b8275d35d | 464 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 465 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 466 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
<> | 135:176b8275d35d | 467 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
<> | 135:176b8275d35d | 468 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
<> | 135:176b8275d35d | 469 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
<> | 135:176b8275d35d | 470 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
<> | 135:176b8275d35d | 471 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
<> | 135:176b8275d35d | 472 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
<> | 135:176b8275d35d | 473 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
<> | 135:176b8275d35d | 474 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
<> | 135:176b8275d35d | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
<> | 135:176b8275d35d | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 477 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
<> | 135:176b8275d35d | 478 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
<> | 135:176b8275d35d | 479 | * |
<> | 135:176b8275d35d | 480 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 481 | * @retval None |
<> | 135:176b8275d35d | 482 | */ |
<> | 135:176b8275d35d | 483 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 484 | { |
<> | 135:176b8275d35d | 485 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
<> | 135:176b8275d35d | 486 | } |
<> | 135:176b8275d35d | 487 | |
<> | 135:176b8275d35d | 488 | /** |
<> | 135:176b8275d35d | 489 | * @} |
<> | 135:176b8275d35d | 490 | */ |
<> | 135:176b8275d35d | 491 | |
<> | 135:176b8275d35d | 492 | /** @defgroup BUS_LL_EF_APB1 APB1 |
<> | 135:176b8275d35d | 493 | * @{ |
<> | 135:176b8275d35d | 494 | */ |
<> | 135:176b8275d35d | 495 | |
<> | 135:176b8275d35d | 496 | /** |
<> | 135:176b8275d35d | 497 | * @brief Enable APB1 peripherals clock. |
<> | 135:176b8275d35d | 498 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 499 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 500 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 501 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 502 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 503 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 504 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 505 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 506 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 507 | * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 508 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 509 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 510 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 511 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 512 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 513 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 514 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 515 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 516 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 517 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 518 | * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 519 | * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 520 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 521 | * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 522 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 523 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock |
<> | 135:176b8275d35d | 524 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 525 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
<> | 135:176b8275d35d | 526 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
<> | 135:176b8275d35d | 527 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
<> | 135:176b8275d35d | 528 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
<> | 135:176b8275d35d | 529 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
<> | 135:176b8275d35d | 530 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
<> | 135:176b8275d35d | 531 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
<> | 135:176b8275d35d | 532 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
<> | 135:176b8275d35d | 533 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
<> | 135:176b8275d35d | 534 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
<> | 135:176b8275d35d | 535 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
<> | 135:176b8275d35d | 536 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
<> | 135:176b8275d35d | 537 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
<> | 135:176b8275d35d | 538 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
<> | 135:176b8275d35d | 539 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
<> | 135:176b8275d35d | 540 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
<> | 135:176b8275d35d | 541 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
<> | 135:176b8275d35d | 542 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
<> | 135:176b8275d35d | 543 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
<> | 135:176b8275d35d | 544 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
<> | 135:176b8275d35d | 545 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
<> | 135:176b8275d35d | 546 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
<> | 135:176b8275d35d | 547 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
<> | 135:176b8275d35d | 548 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
<> | 135:176b8275d35d | 549 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
<> | 135:176b8275d35d | 550 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
<> | 135:176b8275d35d | 551 | * |
<> | 135:176b8275d35d | 552 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 553 | * @retval None |
<> | 135:176b8275d35d | 554 | */ |
<> | 135:176b8275d35d | 555 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 556 | { |
<> | 135:176b8275d35d | 557 | __IO uint32_t tmpreg; |
<> | 135:176b8275d35d | 558 | SET_BIT(RCC->APB1ENR, Periphs); |
<> | 135:176b8275d35d | 559 | /* Delay after an RCC peripheral clock enabling */ |
<> | 135:176b8275d35d | 560 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
<> | 135:176b8275d35d | 561 | (void)tmpreg; |
<> | 135:176b8275d35d | 562 | } |
<> | 135:176b8275d35d | 563 | |
<> | 135:176b8275d35d | 564 | /** |
<> | 135:176b8275d35d | 565 | * @brief Check if APB1 peripheral clock is enabled or not |
<> | 135:176b8275d35d | 566 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 567 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 568 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 569 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 570 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 571 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 572 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 573 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 574 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 575 | * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 576 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 577 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 578 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 579 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 580 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 581 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 582 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 583 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 584 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 585 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 586 | * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 587 | * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 588 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 589 | * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 590 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 591 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock |
<> | 135:176b8275d35d | 592 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 593 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
<> | 135:176b8275d35d | 594 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
<> | 135:176b8275d35d | 595 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
<> | 135:176b8275d35d | 596 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
<> | 135:176b8275d35d | 597 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
<> | 135:176b8275d35d | 598 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
<> | 135:176b8275d35d | 599 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
<> | 135:176b8275d35d | 600 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
<> | 135:176b8275d35d | 601 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
<> | 135:176b8275d35d | 602 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
<> | 135:176b8275d35d | 603 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
<> | 135:176b8275d35d | 604 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
<> | 135:176b8275d35d | 605 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
<> | 135:176b8275d35d | 606 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
<> | 135:176b8275d35d | 607 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
<> | 135:176b8275d35d | 608 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
<> | 135:176b8275d35d | 609 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
<> | 135:176b8275d35d | 610 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
<> | 135:176b8275d35d | 611 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
<> | 135:176b8275d35d | 612 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
<> | 135:176b8275d35d | 613 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
<> | 135:176b8275d35d | 614 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
<> | 135:176b8275d35d | 615 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
<> | 135:176b8275d35d | 616 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
<> | 135:176b8275d35d | 617 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
<> | 135:176b8275d35d | 618 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
<> | 135:176b8275d35d | 619 | * |
<> | 135:176b8275d35d | 620 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 621 | * @retval State of Periphs (1 or 0). |
<> | 135:176b8275d35d | 622 | */ |
<> | 135:176b8275d35d | 623 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 624 | { |
<> | 135:176b8275d35d | 625 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
<> | 135:176b8275d35d | 626 | } |
<> | 135:176b8275d35d | 627 | |
<> | 135:176b8275d35d | 628 | /** |
<> | 135:176b8275d35d | 629 | * @brief Disable APB1 peripherals clock. |
<> | 135:176b8275d35d | 630 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 631 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 632 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 633 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 634 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 635 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 636 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 637 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 638 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 639 | * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 640 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 641 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 642 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 643 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 644 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 645 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 646 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 647 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 648 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 649 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 650 | * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 651 | * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 652 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 653 | * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 654 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 655 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock |
<> | 135:176b8275d35d | 656 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 657 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
<> | 135:176b8275d35d | 658 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
<> | 135:176b8275d35d | 659 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
<> | 135:176b8275d35d | 660 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
<> | 135:176b8275d35d | 661 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
<> | 135:176b8275d35d | 662 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
<> | 135:176b8275d35d | 663 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
<> | 135:176b8275d35d | 664 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
<> | 135:176b8275d35d | 665 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
<> | 135:176b8275d35d | 666 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
<> | 135:176b8275d35d | 667 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
<> | 135:176b8275d35d | 668 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
<> | 135:176b8275d35d | 669 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
<> | 135:176b8275d35d | 670 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
<> | 135:176b8275d35d | 671 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
<> | 135:176b8275d35d | 672 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
<> | 135:176b8275d35d | 673 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
<> | 135:176b8275d35d | 674 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
<> | 135:176b8275d35d | 675 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
<> | 135:176b8275d35d | 676 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
<> | 135:176b8275d35d | 677 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
<> | 135:176b8275d35d | 678 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
<> | 135:176b8275d35d | 679 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
<> | 135:176b8275d35d | 680 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
<> | 135:176b8275d35d | 681 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
<> | 135:176b8275d35d | 682 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
<> | 135:176b8275d35d | 683 | * |
<> | 135:176b8275d35d | 684 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 685 | * @retval None |
<> | 135:176b8275d35d | 686 | */ |
<> | 135:176b8275d35d | 687 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 688 | { |
<> | 135:176b8275d35d | 689 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
<> | 135:176b8275d35d | 690 | } |
<> | 135:176b8275d35d | 691 | |
<> | 135:176b8275d35d | 692 | /** |
<> | 135:176b8275d35d | 693 | * @brief Force APB1 peripherals reset. |
<> | 135:176b8275d35d | 694 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 695 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 696 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 697 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 698 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 699 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 700 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 701 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 702 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 703 | * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 704 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 705 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 706 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 707 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 708 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 709 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 710 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 711 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 712 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 713 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 714 | * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 715 | * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 716 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 717 | * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 718 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 719 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset |
<> | 135:176b8275d35d | 720 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 721 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 722 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
<> | 135:176b8275d35d | 723 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
<> | 135:176b8275d35d | 724 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
<> | 135:176b8275d35d | 725 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
<> | 135:176b8275d35d | 726 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
<> | 135:176b8275d35d | 727 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
<> | 135:176b8275d35d | 728 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
<> | 135:176b8275d35d | 729 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
<> | 135:176b8275d35d | 730 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
<> | 135:176b8275d35d | 731 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
<> | 135:176b8275d35d | 732 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
<> | 135:176b8275d35d | 733 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
<> | 135:176b8275d35d | 734 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
<> | 135:176b8275d35d | 735 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
<> | 135:176b8275d35d | 736 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
<> | 135:176b8275d35d | 737 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
<> | 135:176b8275d35d | 738 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
<> | 135:176b8275d35d | 739 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
<> | 135:176b8275d35d | 740 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
<> | 135:176b8275d35d | 741 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
<> | 135:176b8275d35d | 742 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
<> | 135:176b8275d35d | 743 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
<> | 135:176b8275d35d | 744 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
<> | 135:176b8275d35d | 745 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
<> | 135:176b8275d35d | 746 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
<> | 135:176b8275d35d | 747 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
<> | 135:176b8275d35d | 748 | * |
<> | 135:176b8275d35d | 749 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 750 | * @retval None |
<> | 135:176b8275d35d | 751 | */ |
<> | 135:176b8275d35d | 752 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 753 | { |
<> | 135:176b8275d35d | 754 | SET_BIT(RCC->APB1RSTR, Periphs); |
<> | 135:176b8275d35d | 755 | } |
<> | 135:176b8275d35d | 756 | |
<> | 135:176b8275d35d | 757 | /** |
<> | 135:176b8275d35d | 758 | * @brief Release APB1 peripherals reset. |
<> | 135:176b8275d35d | 759 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 760 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 761 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 762 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 763 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 764 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 765 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 766 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 767 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 768 | * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 769 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 770 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 771 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 772 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 773 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 774 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 775 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 776 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 777 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 778 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 779 | * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 780 | * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 781 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 782 | * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 783 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 784 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset |
<> | 135:176b8275d35d | 785 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 786 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 787 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
<> | 135:176b8275d35d | 788 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
<> | 135:176b8275d35d | 789 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
<> | 135:176b8275d35d | 790 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
<> | 135:176b8275d35d | 791 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
<> | 135:176b8275d35d | 792 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
<> | 135:176b8275d35d | 793 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
<> | 135:176b8275d35d | 794 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
<> | 135:176b8275d35d | 795 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
<> | 135:176b8275d35d | 796 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
<> | 135:176b8275d35d | 797 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
<> | 135:176b8275d35d | 798 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
<> | 135:176b8275d35d | 799 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
<> | 135:176b8275d35d | 800 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
<> | 135:176b8275d35d | 801 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
<> | 135:176b8275d35d | 802 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
<> | 135:176b8275d35d | 803 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
<> | 135:176b8275d35d | 804 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
<> | 135:176b8275d35d | 805 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
<> | 135:176b8275d35d | 806 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
<> | 135:176b8275d35d | 807 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
<> | 135:176b8275d35d | 808 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
<> | 135:176b8275d35d | 809 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
<> | 135:176b8275d35d | 810 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
<> | 135:176b8275d35d | 811 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
<> | 135:176b8275d35d | 812 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
<> | 135:176b8275d35d | 813 | * |
<> | 135:176b8275d35d | 814 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 815 | * @retval None |
<> | 135:176b8275d35d | 816 | */ |
<> | 135:176b8275d35d | 817 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 818 | { |
<> | 135:176b8275d35d | 819 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
<> | 135:176b8275d35d | 820 | } |
<> | 135:176b8275d35d | 821 | |
<> | 135:176b8275d35d | 822 | /** |
<> | 135:176b8275d35d | 823 | * @} |
<> | 135:176b8275d35d | 824 | */ |
<> | 135:176b8275d35d | 825 | |
<> | 135:176b8275d35d | 826 | /** @defgroup BUS_LL_EF_APB2 APB2 |
<> | 135:176b8275d35d | 827 | * @{ |
<> | 135:176b8275d35d | 828 | */ |
<> | 135:176b8275d35d | 829 | |
<> | 135:176b8275d35d | 830 | /** |
<> | 135:176b8275d35d | 831 | * @brief Enable APB2 peripherals clock. |
<> | 135:176b8275d35d | 832 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 833 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 834 | * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 835 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 836 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 837 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 838 | * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 839 | * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 840 | * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 841 | * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 842 | * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 843 | * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 844 | * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 845 | * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 846 | * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n |
<> | 135:176b8275d35d | 847 | * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock |
<> | 135:176b8275d35d | 848 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 849 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
<> | 135:176b8275d35d | 850 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 851 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
<> | 135:176b8275d35d | 852 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
<> | 135:176b8275d35d | 853 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
<> | 135:176b8275d35d | 854 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
<> | 135:176b8275d35d | 855 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
<> | 135:176b8275d35d | 856 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
<> | 135:176b8275d35d | 857 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
<> | 135:176b8275d35d | 858 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
<> | 135:176b8275d35d | 859 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
<> | 135:176b8275d35d | 860 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
<> | 135:176b8275d35d | 861 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
<> | 135:176b8275d35d | 862 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
<> | 135:176b8275d35d | 863 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
<> | 135:176b8275d35d | 864 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
<> | 135:176b8275d35d | 865 | * |
<> | 135:176b8275d35d | 866 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 867 | * @retval None |
<> | 135:176b8275d35d | 868 | */ |
<> | 135:176b8275d35d | 869 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 870 | { |
<> | 135:176b8275d35d | 871 | __IO uint32_t tmpreg; |
<> | 135:176b8275d35d | 872 | SET_BIT(RCC->APB2ENR, Periphs); |
<> | 135:176b8275d35d | 873 | /* Delay after an RCC peripheral clock enabling */ |
<> | 135:176b8275d35d | 874 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
<> | 135:176b8275d35d | 875 | (void)tmpreg; |
<> | 135:176b8275d35d | 876 | } |
<> | 135:176b8275d35d | 877 | |
<> | 135:176b8275d35d | 878 | /** |
<> | 135:176b8275d35d | 879 | * @brief Check if APB2 peripheral clock is enabled or not |
<> | 135:176b8275d35d | 880 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 881 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 882 | * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 883 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 884 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 885 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 886 | * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 887 | * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 888 | * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 889 | * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 890 | * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 891 | * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 892 | * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 893 | * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 894 | * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n |
<> | 135:176b8275d35d | 895 | * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock |
<> | 135:176b8275d35d | 896 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 897 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
<> | 135:176b8275d35d | 898 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 899 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
<> | 135:176b8275d35d | 900 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
<> | 135:176b8275d35d | 901 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
<> | 135:176b8275d35d | 902 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
<> | 135:176b8275d35d | 903 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
<> | 135:176b8275d35d | 904 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
<> | 135:176b8275d35d | 905 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
<> | 135:176b8275d35d | 906 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
<> | 135:176b8275d35d | 907 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
<> | 135:176b8275d35d | 908 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
<> | 135:176b8275d35d | 909 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
<> | 135:176b8275d35d | 910 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
<> | 135:176b8275d35d | 911 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
<> | 135:176b8275d35d | 912 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
<> | 135:176b8275d35d | 913 | * |
<> | 135:176b8275d35d | 914 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 915 | * @retval State of Periphs (1 or 0). |
<> | 135:176b8275d35d | 916 | */ |
<> | 135:176b8275d35d | 917 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 918 | { |
<> | 135:176b8275d35d | 919 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
<> | 135:176b8275d35d | 920 | } |
<> | 135:176b8275d35d | 921 | |
<> | 135:176b8275d35d | 922 | /** |
<> | 135:176b8275d35d | 923 | * @brief Disable APB2 peripherals clock. |
<> | 135:176b8275d35d | 924 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 925 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 926 | * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 927 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 928 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 929 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 930 | * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 931 | * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 932 | * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 933 | * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 934 | * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 935 | * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 936 | * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 937 | * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 938 | * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n |
<> | 135:176b8275d35d | 939 | * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock |
<> | 135:176b8275d35d | 940 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 941 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
<> | 135:176b8275d35d | 942 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 943 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
<> | 135:176b8275d35d | 944 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
<> | 135:176b8275d35d | 945 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
<> | 135:176b8275d35d | 946 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
<> | 135:176b8275d35d | 947 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
<> | 135:176b8275d35d | 948 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
<> | 135:176b8275d35d | 949 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
<> | 135:176b8275d35d | 950 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
<> | 135:176b8275d35d | 951 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
<> | 135:176b8275d35d | 952 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
<> | 135:176b8275d35d | 953 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
<> | 135:176b8275d35d | 954 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
<> | 135:176b8275d35d | 955 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
<> | 135:176b8275d35d | 956 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
<> | 135:176b8275d35d | 957 | * |
<> | 135:176b8275d35d | 958 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 959 | * @retval None |
<> | 135:176b8275d35d | 960 | */ |
<> | 135:176b8275d35d | 961 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
<> | 135:176b8275d35d | 962 | { |
<> | 135:176b8275d35d | 963 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
<> | 135:176b8275d35d | 964 | } |
<> | 135:176b8275d35d | 965 | |
<> | 135:176b8275d35d | 966 | /** |
<> | 135:176b8275d35d | 967 | * @brief Force APB2 peripherals reset. |
<> | 135:176b8275d35d | 968 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 969 | * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 970 | * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 971 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 972 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 973 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 974 | * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 975 | * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 976 | * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 977 | * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 978 | * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 979 | * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 980 | * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 981 | * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 982 | * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n |
<> | 135:176b8275d35d | 983 | * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset |
<> | 135:176b8275d35d | 984 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 985 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 986 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
<> | 135:176b8275d35d | 987 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 988 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
<> | 135:176b8275d35d | 989 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
<> | 135:176b8275d35d | 990 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
<> | 135:176b8275d35d | 991 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
<> | 135:176b8275d35d | 992 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
<> | 135:176b8275d35d | 993 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
<> | 135:176b8275d35d | 994 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
<> | 135:176b8275d35d | 995 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
<> | 135:176b8275d35d | 996 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
<> | 135:176b8275d35d | 997 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
<> | 135:176b8275d35d | 998 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
<> | 135:176b8275d35d | 999 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
<> | 135:176b8275d35d | 1000 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
<> | 135:176b8275d35d | 1001 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
<> | 135:176b8275d35d | 1002 | * |
<> | 135:176b8275d35d | 1003 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1004 | * @retval None |
<> | 135:176b8275d35d | 1005 | */ |
<> | 135:176b8275d35d | 1006 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 1007 | { |
<> | 135:176b8275d35d | 1008 | SET_BIT(RCC->APB2RSTR, Periphs); |
<> | 135:176b8275d35d | 1009 | } |
<> | 135:176b8275d35d | 1010 | |
<> | 135:176b8275d35d | 1011 | /** |
<> | 135:176b8275d35d | 1012 | * @brief Release APB2 peripherals reset. |
<> | 135:176b8275d35d | 1013 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1014 | * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1015 | * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1016 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1017 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1018 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1019 | * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1020 | * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1021 | * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1022 | * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1023 | * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1024 | * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1025 | * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1026 | * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1027 | * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n |
<> | 135:176b8275d35d | 1028 | * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset |
<> | 135:176b8275d35d | 1029 | * @param Periphs This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 1030 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
<> | 135:176b8275d35d | 1031 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
<> | 135:176b8275d35d | 1032 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
<> | 135:176b8275d35d | 1033 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
<> | 135:176b8275d35d | 1034 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
<> | 135:176b8275d35d | 1035 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
<> | 135:176b8275d35d | 1036 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
<> | 135:176b8275d35d | 1037 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
<> | 135:176b8275d35d | 1038 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
<> | 135:176b8275d35d | 1039 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
<> | 135:176b8275d35d | 1040 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
<> | 135:176b8275d35d | 1041 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
<> | 135:176b8275d35d | 1042 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
<> | 135:176b8275d35d | 1043 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
<> | 135:176b8275d35d | 1044 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
<> | 135:176b8275d35d | 1045 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
<> | 135:176b8275d35d | 1046 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
<> | 135:176b8275d35d | 1047 | * |
<> | 135:176b8275d35d | 1048 | * (*) value not defined in all devices. |
<> | 135:176b8275d35d | 1049 | * @retval None |
<> | 135:176b8275d35d | 1050 | */ |
<> | 135:176b8275d35d | 1051 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
<> | 135:176b8275d35d | 1052 | { |
<> | 135:176b8275d35d | 1053 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
<> | 135:176b8275d35d | 1054 | } |
<> | 135:176b8275d35d | 1055 | |
<> | 135:176b8275d35d | 1056 | /** |
<> | 135:176b8275d35d | 1057 | * @} |
<> | 135:176b8275d35d | 1058 | */ |
<> | 135:176b8275d35d | 1059 | |
<> | 135:176b8275d35d | 1060 | |
<> | 135:176b8275d35d | 1061 | /** |
<> | 135:176b8275d35d | 1062 | * @} |
<> | 135:176b8275d35d | 1063 | */ |
<> | 135:176b8275d35d | 1064 | |
<> | 135:176b8275d35d | 1065 | /** |
<> | 135:176b8275d35d | 1066 | * @} |
<> | 135:176b8275d35d | 1067 | */ |
<> | 135:176b8275d35d | 1068 | |
<> | 135:176b8275d35d | 1069 | #endif /* defined(RCC) */ |
<> | 135:176b8275d35d | 1070 | |
<> | 135:176b8275d35d | 1071 | /** |
<> | 135:176b8275d35d | 1072 | * @} |
<> | 135:176b8275d35d | 1073 | */ |
<> | 135:176b8275d35d | 1074 | |
<> | 135:176b8275d35d | 1075 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 1076 | } |
<> | 135:176b8275d35d | 1077 | #endif |
<> | 135:176b8275d35d | 1078 | |
<> | 135:176b8275d35d | 1079 | #endif /* __STM32F3xx_LL_BUS_H */ |
<> | 135:176b8275d35d | 1080 | |
<> | 135:176b8275d35d | 1081 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |