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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 14 11:24:20 2017 +0000
- Revision:
- 136:ef9c61f8c49f
- Parent:
- 135:176b8275d35d
Release 136 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 86:04dd9b1680ae | 1 | /** |
bogdanm | 86:04dd9b1680ae | 2 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 3 | * @file stm32f3xx_hal_tim_ex.h |
bogdanm | 86:04dd9b1680ae | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
bogdanm | 92:4fc01daae5a5 | 7 | * @brief Header file of TIM HAL Extended module. |
bogdanm | 86:04dd9b1680ae | 8 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 9 | * @attention |
bogdanm | 86:04dd9b1680ae | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
bogdanm | 86:04dd9b1680ae | 12 | * |
bogdanm | 86:04dd9b1680ae | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 86:04dd9b1680ae | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 86:04dd9b1680ae | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 86:04dd9b1680ae | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 86:04dd9b1680ae | 19 | * and/or other materials provided with the distribution. |
bogdanm | 86:04dd9b1680ae | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 86:04dd9b1680ae | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 86:04dd9b1680ae | 22 | * without specific prior written permission. |
bogdanm | 86:04dd9b1680ae | 23 | * |
bogdanm | 86:04dd9b1680ae | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 86:04dd9b1680ae | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 86:04dd9b1680ae | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 86:04dd9b1680ae | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 86:04dd9b1680ae | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 86:04dd9b1680ae | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 86:04dd9b1680ae | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 86:04dd9b1680ae | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 86:04dd9b1680ae | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 86:04dd9b1680ae | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 86:04dd9b1680ae | 34 | * |
bogdanm | 86:04dd9b1680ae | 35 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 36 | */ |
bogdanm | 86:04dd9b1680ae | 37 | |
bogdanm | 86:04dd9b1680ae | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 39 | #ifndef __STM32F3xx_HAL_TIM_EX_H |
bogdanm | 86:04dd9b1680ae | 40 | #define __STM32F3xx_HAL_TIM_EX_H |
bogdanm | 86:04dd9b1680ae | 41 | |
bogdanm | 86:04dd9b1680ae | 42 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 43 | extern "C" { |
bogdanm | 86:04dd9b1680ae | 44 | #endif |
bogdanm | 86:04dd9b1680ae | 45 | |
bogdanm | 86:04dd9b1680ae | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 47 | #include "stm32f3xx_hal_def.h" |
bogdanm | 86:04dd9b1680ae | 48 | |
bogdanm | 86:04dd9b1680ae | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
bogdanm | 86:04dd9b1680ae | 50 | * @{ |
bogdanm | 86:04dd9b1680ae | 51 | */ |
bogdanm | 86:04dd9b1680ae | 52 | |
bogdanm | 86:04dd9b1680ae | 53 | /** @addtogroup TIMEx |
bogdanm | 86:04dd9b1680ae | 54 | * @{ |
Kojto | 122:f9eeca106725 | 55 | */ |
bogdanm | 86:04dd9b1680ae | 56 | |
Kojto | 122:f9eeca106725 | 57 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 58 | /** @defgroup TIMEx_Exported_Types TIMEx Exported Types |
bogdanm | 92:4fc01daae5a5 | 59 | * @{ |
bogdanm | 92:4fc01daae5a5 | 60 | */ |
bogdanm | 86:04dd9b1680ae | 61 | |
Kojto | 122:f9eeca106725 | 62 | /** |
Kojto | 122:f9eeca106725 | 63 | * @brief TIM Hall sensor Configuration Structure definition |
bogdanm | 86:04dd9b1680ae | 64 | */ |
bogdanm | 86:04dd9b1680ae | 65 | |
bogdanm | 86:04dd9b1680ae | 66 | typedef struct |
bogdanm | 86:04dd9b1680ae | 67 | { |
Kojto | 122:f9eeca106725 | 68 | |
bogdanm | 86:04dd9b1680ae | 69 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
bogdanm | 86:04dd9b1680ae | 70 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
Kojto | 122:f9eeca106725 | 71 | |
bogdanm | 86:04dd9b1680ae | 72 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
bogdanm | 86:04dd9b1680ae | 73 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
Kojto | 122:f9eeca106725 | 74 | |
bogdanm | 86:04dd9b1680ae | 75 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
<> | 135:176b8275d35d | 76 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
Kojto | 122:f9eeca106725 | 77 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
<> | 135:176b8275d35d | 78 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ |
bogdanm | 86:04dd9b1680ae | 79 | } TIM_HallSensor_InitTypeDef; |
bogdanm | 86:04dd9b1680ae | 80 | |
bogdanm | 86:04dd9b1680ae | 81 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 122:f9eeca106725 | 82 | /** |
Kojto | 122:f9eeca106725 | 83 | * @brief TIM Master configuration Structure definition |
bogdanm | 86:04dd9b1680ae | 84 | * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO |
bogdanm | 86:04dd9b1680ae | 85 | * output |
Kojto | 122:f9eeca106725 | 86 | */ |
bogdanm | 86:04dd9b1680ae | 87 | typedef struct { |
Kojto | 122:f9eeca106725 | 88 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
Kojto | 122:f9eeca106725 | 89 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
Kojto | 122:f9eeca106725 | 90 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
bogdanm | 86:04dd9b1680ae | 91 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
bogdanm | 86:04dd9b1680ae | 92 | }TIM_MasterConfigTypeDef; |
bogdanm | 86:04dd9b1680ae | 93 | |
Kojto | 122:f9eeca106725 | 94 | /** |
Kojto | 122:f9eeca106725 | 95 | * @brief TIM Break and Dead time configuration Structure definition |
bogdanm | 86:04dd9b1680ae | 96 | * @note STM32F373xC and STM32F378xx: single break input with configurable polarity. |
Kojto | 122:f9eeca106725 | 97 | */ |
bogdanm | 86:04dd9b1680ae | 98 | typedef struct |
bogdanm | 86:04dd9b1680ae | 99 | { |
Kojto | 122:f9eeca106725 | 100 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
bogdanm | 86:04dd9b1680ae | 101 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
Kojto | 122:f9eeca106725 | 102 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
bogdanm | 86:04dd9b1680ae | 103 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
Kojto | 122:f9eeca106725 | 104 | uint32_t LockLevel; /*!< TIM Lock level |
Kojto | 122:f9eeca106725 | 105 | This parameter can be a value of @ref TIM_Lock_level */ |
Kojto | 122:f9eeca106725 | 106 | uint32_t DeadTime; /*!< TIM dead Time |
<> | 135:176b8275d35d | 107 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ |
Kojto | 122:f9eeca106725 | 108 | uint32_t BreakState; /*!< TIM Break State |
bogdanm | 86:04dd9b1680ae | 109 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
Kojto | 122:f9eeca106725 | 110 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
bogdanm | 86:04dd9b1680ae | 111 | This parameter can be a value of @ref TIM_Break_Polarity */ |
Kojto | 122:f9eeca106725 | 112 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
Kojto | 122:f9eeca106725 | 113 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
bogdanm | 86:04dd9b1680ae | 114 | } TIM_BreakDeadTimeConfigTypeDef; |
bogdanm | 86:04dd9b1680ae | 115 | |
bogdanm | 86:04dd9b1680ae | 116 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 86:04dd9b1680ae | 117 | |
bogdanm | 92:4fc01daae5a5 | 118 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 92:4fc01daae5a5 | 119 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 92:4fc01daae5a5 | 120 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 121 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 122:f9eeca106725 | 122 | /** |
Kojto | 122:f9eeca106725 | 123 | * @brief TIM Break input(s) and Dead time configuration Structure definition |
Kojto | 122:f9eeca106725 | 124 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
bogdanm | 86:04dd9b1680ae | 125 | * filter and polarity. |
Kojto | 122:f9eeca106725 | 126 | */ |
bogdanm | 86:04dd9b1680ae | 127 | typedef struct |
bogdanm | 86:04dd9b1680ae | 128 | { |
Kojto | 122:f9eeca106725 | 129 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
bogdanm | 86:04dd9b1680ae | 130 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
Kojto | 122:f9eeca106725 | 131 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
bogdanm | 86:04dd9b1680ae | 132 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
Kojto | 122:f9eeca106725 | 133 | uint32_t LockLevel; /*!< TIM Lock level |
Kojto | 122:f9eeca106725 | 134 | This parameter can be a value of @ref TIM_Lock_level */ |
Kojto | 122:f9eeca106725 | 135 | uint32_t DeadTime; /*!< TIM dead Time |
<> | 135:176b8275d35d | 136 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ |
Kojto | 122:f9eeca106725 | 137 | uint32_t BreakState; /*!< TIM Break State |
bogdanm | 86:04dd9b1680ae | 138 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
Kojto | 122:f9eeca106725 | 139 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
bogdanm | 86:04dd9b1680ae | 140 | This parameter can be a value of @ref TIM_Break_Polarity */ |
bogdanm | 86:04dd9b1680ae | 141 | uint32_t BreakFilter; /*!< Specifies the brek input filter. |
<> | 135:176b8275d35d | 142 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
Kojto | 122:f9eeca106725 | 143 | uint32_t Break2State; /*!< TIM Break2 State |
bogdanm | 86:04dd9b1680ae | 144 | This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */ |
Kojto | 122:f9eeca106725 | 145 | uint32_t Break2Polarity; /*!< TIM Break2 input polarity |
bogdanm | 86:04dd9b1680ae | 146 | This parameter can be a value of @ref TIMEx_Break2_Polarity */ |
bogdanm | 86:04dd9b1680ae | 147 | uint32_t Break2Filter; /*!< TIM break2 input filter. |
<> | 135:176b8275d35d | 148 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
Kojto | 122:f9eeca106725 | 149 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
Kojto | 122:f9eeca106725 | 150 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
bogdanm | 86:04dd9b1680ae | 151 | } TIM_BreakDeadTimeConfigTypeDef; |
bogdanm | 86:04dd9b1680ae | 152 | |
Kojto | 122:f9eeca106725 | 153 | /** |
Kojto | 122:f9eeca106725 | 154 | * @brief TIM Master configuration Structure definition |
bogdanm | 86:04dd9b1680ae | 155 | * @note Advanced timers provide TRGO2 internal line which is redirected |
Kojto | 122:f9eeca106725 | 156 | * to the ADC |
Kojto | 122:f9eeca106725 | 157 | */ |
bogdanm | 86:04dd9b1680ae | 158 | typedef struct { |
Kojto | 122:f9eeca106725 | 159 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
Kojto | 122:f9eeca106725 | 160 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
Kojto | 122:f9eeca106725 | 161 | uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection |
bogdanm | 86:04dd9b1680ae | 162 | This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */ |
Kojto | 122:f9eeca106725 | 163 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
bogdanm | 86:04dd9b1680ae | 164 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
bogdanm | 86:04dd9b1680ae | 165 | }TIM_MasterConfigTypeDef; |
bogdanm | 92:4fc01daae5a5 | 166 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 86:04dd9b1680ae | 167 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 92:4fc01daae5a5 | 168 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 169 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 92:4fc01daae5a5 | 170 | /** |
bogdanm | 92:4fc01daae5a5 | 171 | * @} |
bogdanm | 92:4fc01daae5a5 | 172 | */ |
bogdanm | 86:04dd9b1680ae | 173 | |
bogdanm | 86:04dd9b1680ae | 174 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 175 | /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants |
bogdanm | 86:04dd9b1680ae | 176 | * @{ |
bogdanm | 86:04dd9b1680ae | 177 | */ |
bogdanm | 86:04dd9b1680ae | 178 | |
bogdanm | 86:04dd9b1680ae | 179 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 122:f9eeca106725 | 180 | /** @defgroup TIMEx_Channel TIMEx Channel |
bogdanm | 86:04dd9b1680ae | 181 | * @{ |
bogdanm | 86:04dd9b1680ae | 182 | */ |
<> | 135:176b8275d35d | 183 | #define TIM_CHANNEL_1 (0x0000U) |
<> | 135:176b8275d35d | 184 | #define TIM_CHANNEL_2 (0x0004U) |
<> | 135:176b8275d35d | 185 | #define TIM_CHANNEL_3 (0x0008U) |
<> | 135:176b8275d35d | 186 | #define TIM_CHANNEL_4 (0x000CU) |
<> | 135:176b8275d35d | 187 | #define TIM_CHANNEL_ALL (0x0018U) |
bogdanm | 86:04dd9b1680ae | 188 | /** |
bogdanm | 86:04dd9b1680ae | 189 | * @} |
Kojto | 122:f9eeca106725 | 190 | */ |
bogdanm | 86:04dd9b1680ae | 191 | |
Kojto | 122:f9eeca106725 | 192 | /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes |
bogdanm | 86:04dd9b1680ae | 193 | * @{ |
bogdanm | 86:04dd9b1680ae | 194 | */ |
<> | 135:176b8275d35d | 195 | #define TIM_OCMODE_TIMING (0x0000U) |
bogdanm | 86:04dd9b1680ae | 196 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 197 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
bogdanm | 86:04dd9b1680ae | 198 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
bogdanm | 86:04dd9b1680ae | 199 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 200 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M) |
bogdanm | 86:04dd9b1680ae | 201 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 202 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 203 | /** |
bogdanm | 86:04dd9b1680ae | 204 | * @} |
bogdanm | 86:04dd9b1680ae | 205 | */ |
bogdanm | 86:04dd9b1680ae | 206 | |
Kojto | 122:f9eeca106725 | 207 | /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source |
bogdanm | 86:04dd9b1680ae | 208 | * @{ |
bogdanm | 86:04dd9b1680ae | 209 | */ |
<> | 135:176b8275d35d | 210 | #define TIM_CLEARINPUTSOURCE_ETR (0x0001U) |
<> | 135:176b8275d35d | 211 | #define TIM_CLEARINPUTSOURCE_NONE (0x0000U) |
Kojto | 122:f9eeca106725 | 212 | /** |
Kojto | 122:f9eeca106725 | 213 | * @} |
Kojto | 122:f9eeca106725 | 214 | */ |
bogdanm | 86:04dd9b1680ae | 215 | |
Kojto | 122:f9eeca106725 | 216 | /** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode |
Kojto | 122:f9eeca106725 | 217 | * @{ |
Kojto | 122:f9eeca106725 | 218 | */ |
<> | 135:176b8275d35d | 219 | #define TIM_SLAVEMODE_DISABLE (0x0000U) |
Kojto | 122:f9eeca106725 | 220 | #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) |
Kojto | 122:f9eeca106725 | 221 | #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) |
Kojto | 122:f9eeca106725 | 222 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) |
Kojto | 122:f9eeca106725 | 223 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) |
bogdanm | 86:04dd9b1680ae | 224 | /** |
bogdanm | 86:04dd9b1680ae | 225 | * @} |
bogdanm | 86:04dd9b1680ae | 226 | */ |
bogdanm | 86:04dd9b1680ae | 227 | |
Kojto | 122:f9eeca106725 | 228 | /** @defgroup TIMEx_Event_Source TIMEx Event Source |
bogdanm | 86:04dd9b1680ae | 229 | * @{ |
bogdanm | 86:04dd9b1680ae | 230 | */ |
Kojto | 122:f9eeca106725 | 231 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
<> | 135:176b8275d35d | 232 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */ |
<> | 135:176b8275d35d | 233 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */ |
<> | 135:176b8275d35d | 234 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */ |
<> | 135:176b8275d35d | 235 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */ |
Kojto | 122:f9eeca106725 | 236 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
Kojto | 122:f9eeca106725 | 237 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
Kojto | 122:f9eeca106725 | 238 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ |
bogdanm | 86:04dd9b1680ae | 239 | /** |
bogdanm | 86:04dd9b1680ae | 240 | * @} |
bogdanm | 86:04dd9b1680ae | 241 | */ |
bogdanm | 86:04dd9b1680ae | 242 | |
Kojto | 122:f9eeca106725 | 243 | /** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address |
Kojto | 122:f9eeca106725 | 244 | * @{ |
Kojto | 122:f9eeca106725 | 245 | */ |
<> | 135:176b8275d35d | 246 | #define TIM_DMABASE_CR1 (0x00000000U) |
<> | 135:176b8275d35d | 247 | #define TIM_DMABASE_CR2 (0x00000001U) |
<> | 135:176b8275d35d | 248 | #define TIM_DMABASE_SMCR (0x00000002U) |
<> | 135:176b8275d35d | 249 | #define TIM_DMABASE_DIER (0x00000003U) |
<> | 135:176b8275d35d | 250 | #define TIM_DMABASE_SR (0x00000004U) |
<> | 135:176b8275d35d | 251 | #define TIM_DMABASE_EGR (0x00000005U) |
<> | 135:176b8275d35d | 252 | #define TIM_DMABASE_CCMR1 (0x00000006U) |
<> | 135:176b8275d35d | 253 | #define TIM_DMABASE_CCMR2 (0x00000007U) |
<> | 135:176b8275d35d | 254 | #define TIM_DMABASE_CCER (0x00000008U) |
<> | 135:176b8275d35d | 255 | #define TIM_DMABASE_CNT (0x00000009U) |
<> | 135:176b8275d35d | 256 | #define TIM_DMABASE_PSC (0x0000000AU) |
<> | 135:176b8275d35d | 257 | #define TIM_DMABASE_ARR (0x0000000BU) |
<> | 135:176b8275d35d | 258 | #define TIM_DMABASE_RCR (0x0000000CU) |
<> | 135:176b8275d35d | 259 | #define TIM_DMABASE_CCR1 (0x0000000DU) |
<> | 135:176b8275d35d | 260 | #define TIM_DMABASE_CCR2 (0x0000000EU) |
<> | 135:176b8275d35d | 261 | #define TIM_DMABASE_CCR3 (0x0000000FU) |
<> | 135:176b8275d35d | 262 | #define TIM_DMABASE_CCR4 (0x00000010U) |
<> | 135:176b8275d35d | 263 | #define TIM_DMABASE_BDTR (0x00000011U) |
<> | 135:176b8275d35d | 264 | #define TIM_DMABASE_DCR (0x00000012U) |
<> | 135:176b8275d35d | 265 | #define TIM_DMABASE_OR (0x00000013U) |
bogdanm | 86:04dd9b1680ae | 266 | /** |
bogdanm | 86:04dd9b1680ae | 267 | * @} |
Kojto | 122:f9eeca106725 | 268 | */ |
bogdanm | 86:04dd9b1680ae | 269 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 86:04dd9b1680ae | 270 | |
bogdanm | 92:4fc01daae5a5 | 271 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 92:4fc01daae5a5 | 272 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 92:4fc01daae5a5 | 273 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 274 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 122:f9eeca106725 | 275 | /** @defgroup TIMEx_Channel TIMEx Channel |
bogdanm | 86:04dd9b1680ae | 276 | * @{ |
bogdanm | 86:04dd9b1680ae | 277 | */ |
<> | 135:176b8275d35d | 278 | #define TIM_CHANNEL_1 (0x0000U) |
<> | 135:176b8275d35d | 279 | #define TIM_CHANNEL_2 (0x0004U) |
<> | 135:176b8275d35d | 280 | #define TIM_CHANNEL_3 (0x0008U) |
<> | 135:176b8275d35d | 281 | #define TIM_CHANNEL_4 (0x000CU) |
<> | 135:176b8275d35d | 282 | #define TIM_CHANNEL_5 (0x0010U) |
<> | 135:176b8275d35d | 283 | #define TIM_CHANNEL_6 (0x0014U) |
<> | 135:176b8275d35d | 284 | #define TIM_CHANNEL_ALL (0x003CU) |
bogdanm | 86:04dd9b1680ae | 285 | /** |
bogdanm | 86:04dd9b1680ae | 286 | * @} |
Kojto | 122:f9eeca106725 | 287 | */ |
bogdanm | 86:04dd9b1680ae | 288 | |
Kojto | 122:f9eeca106725 | 289 | /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes |
bogdanm | 86:04dd9b1680ae | 290 | * @{ |
bogdanm | 86:04dd9b1680ae | 291 | */ |
<> | 135:176b8275d35d | 292 | #define TIM_OCMODE_TIMING (0x0000U) |
bogdanm | 86:04dd9b1680ae | 293 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 294 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
bogdanm | 86:04dd9b1680ae | 295 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 296 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
bogdanm | 86:04dd9b1680ae | 297 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 298 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 299 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 300 | |
bogdanm | 86:04dd9b1680ae | 301 | #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) |
bogdanm | 86:04dd9b1680ae | 302 | #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
bogdanm | 86:04dd9b1680ae | 303 | #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 304 | #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 305 | #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
bogdanm | 86:04dd9b1680ae | 306 | #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) |
bogdanm | 86:04dd9b1680ae | 307 | |
Kojto | 122:f9eeca106725 | 308 | /** |
Kojto | 122:f9eeca106725 | 309 | * @} |
Kojto | 122:f9eeca106725 | 310 | */ |
Kojto | 122:f9eeca106725 | 311 | |
Kojto | 122:f9eeca106725 | 312 | /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source |
Kojto | 122:f9eeca106725 | 313 | * @{ |
Kojto | 122:f9eeca106725 | 314 | */ |
<> | 135:176b8275d35d | 315 | #define TIM_CLEARINPUTSOURCE_ETR (0x0001U) |
<> | 135:176b8275d35d | 316 | #define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U) |
<> | 135:176b8275d35d | 317 | #define TIM_CLEARINPUTSOURCE_NONE (0x0000U) |
Kojto | 122:f9eeca106725 | 318 | /** |
Kojto | 122:f9eeca106725 | 319 | * @} |
Kojto | 122:f9eeca106725 | 320 | */ |
Kojto | 122:f9eeca106725 | 321 | |
Kojto | 122:f9eeca106725 | 322 | /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable |
Kojto | 122:f9eeca106725 | 323 | * @{ |
Kojto | 122:f9eeca106725 | 324 | */ |
<> | 135:176b8275d35d | 325 | #define TIM_BREAK2_DISABLE (0x00000000U) |
Kojto | 122:f9eeca106725 | 326 | #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) |
Kojto | 122:f9eeca106725 | 327 | /** |
Kojto | 122:f9eeca106725 | 328 | * @} |
Kojto | 122:f9eeca106725 | 329 | */ |
Kojto | 122:f9eeca106725 | 330 | |
Kojto | 122:f9eeca106725 | 331 | /** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity |
Kojto | 122:f9eeca106725 | 332 | * @{ |
Kojto | 122:f9eeca106725 | 333 | */ |
<> | 135:176b8275d35d | 334 | #define TIM_BREAK2POLARITY_LOW (0x00000000U) |
Kojto | 122:f9eeca106725 | 335 | #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) |
Kojto | 122:f9eeca106725 | 336 | /** |
Kojto | 122:f9eeca106725 | 337 | * @} |
Kojto | 122:f9eeca106725 | 338 | */ |
Kojto | 122:f9eeca106725 | 339 | |
Kojto | 122:f9eeca106725 | 340 | /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) |
Kojto | 122:f9eeca106725 | 341 | * @{ |
Kojto | 122:f9eeca106725 | 342 | */ |
<> | 135:176b8275d35d | 343 | #define TIM_TRGO2_RESET (0x00000000U) |
Kojto | 122:f9eeca106725 | 344 | #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 345 | #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) |
Kojto | 122:f9eeca106725 | 346 | #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 347 | #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) |
Kojto | 122:f9eeca106725 | 348 | #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 349 | #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) |
Kojto | 122:f9eeca106725 | 350 | #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 351 | #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) |
Kojto | 122:f9eeca106725 | 352 | #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 353 | #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) |
Kojto | 122:f9eeca106725 | 354 | #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 355 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) |
Kojto | 122:f9eeca106725 | 356 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 357 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) |
Kojto | 122:f9eeca106725 | 358 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
Kojto | 122:f9eeca106725 | 359 | /** |
Kojto | 122:f9eeca106725 | 360 | * @} |
Kojto | 122:f9eeca106725 | 361 | */ |
Kojto | 122:f9eeca106725 | 362 | |
Kojto | 122:f9eeca106725 | 363 | /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode |
Kojto | 122:f9eeca106725 | 364 | * @{ |
Kojto | 122:f9eeca106725 | 365 | */ |
<> | 135:176b8275d35d | 366 | #define TIM_SLAVEMODE_DISABLE (0x0000U) |
Kojto | 122:f9eeca106725 | 367 | #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) |
Kojto | 122:f9eeca106725 | 368 | #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) |
Kojto | 122:f9eeca106725 | 369 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) |
Kojto | 122:f9eeca106725 | 370 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) |
Kojto | 122:f9eeca106725 | 371 | #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) |
Kojto | 122:f9eeca106725 | 372 | /** |
Kojto | 122:f9eeca106725 | 373 | * @} |
Kojto | 122:f9eeca106725 | 374 | */ |
Kojto | 122:f9eeca106725 | 375 | |
Kojto | 122:f9eeca106725 | 376 | /** @defgroup TIM_Event_Source TIMEx Event Source |
Kojto | 122:f9eeca106725 | 377 | * @{ |
Kojto | 122:f9eeca106725 | 378 | */ |
Kojto | 122:f9eeca106725 | 379 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
<> | 135:176b8275d35d | 380 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */ |
<> | 135:176b8275d35d | 381 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */ |
<> | 135:176b8275d35d | 382 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */ |
<> | 135:176b8275d35d | 383 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */ |
Kojto | 122:f9eeca106725 | 384 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
Kojto | 122:f9eeca106725 | 385 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
Kojto | 122:f9eeca106725 | 386 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ |
Kojto | 122:f9eeca106725 | 387 | #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ |
Kojto | 122:f9eeca106725 | 388 | /** |
Kojto | 122:f9eeca106725 | 389 | * @} |
Kojto | 122:f9eeca106725 | 390 | */ |
Kojto | 122:f9eeca106725 | 391 | |
Kojto | 122:f9eeca106725 | 392 | /** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address |
Kojto | 122:f9eeca106725 | 393 | * @{ |
Kojto | 122:f9eeca106725 | 394 | */ |
<> | 135:176b8275d35d | 395 | #define TIM_DMABASE_CR1 (0x00000000U) |
<> | 135:176b8275d35d | 396 | #define TIM_DMABASE_CR2 (0x00000001U) |
<> | 135:176b8275d35d | 397 | #define TIM_DMABASE_SMCR (0x00000002U) |
<> | 135:176b8275d35d | 398 | #define TIM_DMABASE_DIER (0x00000003U) |
<> | 135:176b8275d35d | 399 | #define TIM_DMABASE_SR (0x00000004U) |
<> | 135:176b8275d35d | 400 | #define TIM_DMABASE_EGR (0x00000005U) |
<> | 135:176b8275d35d | 401 | #define TIM_DMABASE_CCMR1 (0x00000006U) |
<> | 135:176b8275d35d | 402 | #define TIM_DMABASE_CCMR2 (0x00000007U) |
<> | 135:176b8275d35d | 403 | #define TIM_DMABASE_CCER (0x00000008U) |
<> | 135:176b8275d35d | 404 | #define TIM_DMABASE_CNT (0x00000009U) |
<> | 135:176b8275d35d | 405 | #define TIM_DMABASE_PSC (0x0000000AU) |
<> | 135:176b8275d35d | 406 | #define TIM_DMABASE_ARR (0x0000000BU) |
<> | 135:176b8275d35d | 407 | #define TIM_DMABASE_RCR (0x0000000CU) |
<> | 135:176b8275d35d | 408 | #define TIM_DMABASE_CCR1 (0x0000000DU) |
<> | 135:176b8275d35d | 409 | #define TIM_DMABASE_CCR2 (0x0000000EU) |
<> | 135:176b8275d35d | 410 | #define TIM_DMABASE_CCR3 (0x0000000FU) |
<> | 135:176b8275d35d | 411 | #define TIM_DMABASE_CCR4 (0x00000010U) |
<> | 135:176b8275d35d | 412 | #define TIM_DMABASE_BDTR (0x00000011U) |
<> | 135:176b8275d35d | 413 | #define TIM_DMABASE_DCR (0x00000012U) |
<> | 135:176b8275d35d | 414 | #define TIM_DMABASE_CCMR3 (0x00000015U) |
<> | 135:176b8275d35d | 415 | #define TIM_DMABASE_CCR5 (0x00000016U) |
<> | 135:176b8275d35d | 416 | #define TIM_DMABASE_CCR6 (0x00000017U) |
<> | 135:176b8275d35d | 417 | #define TIM_DMABASE_OR (0x00000018U) |
Kojto | 122:f9eeca106725 | 418 | /** |
Kojto | 122:f9eeca106725 | 419 | * @} |
Kojto | 122:f9eeca106725 | 420 | */ |
Kojto | 122:f9eeca106725 | 421 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 122:f9eeca106725 | 422 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 122:f9eeca106725 | 423 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 122:f9eeca106725 | 424 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 122:f9eeca106725 | 425 | |
Kojto | 122:f9eeca106725 | 426 | #if defined(STM32F302xE) || \ |
Kojto | 122:f9eeca106725 | 427 | defined(STM32F302xC) || \ |
<> | 135:176b8275d35d | 428 | defined(STM32F303x8) || defined(STM32F328xx) || \ |
Kojto | 122:f9eeca106725 | 429 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 122:f9eeca106725 | 430 | /** @defgroup TIMEx_Remap TIMEx Remapping |
Kojto | 122:f9eeca106725 | 431 | * @{ |
Kojto | 122:f9eeca106725 | 432 | */ |
<> | 135:176b8275d35d | 433 | #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 434 | #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ |
<> | 135:176b8275d35d | 435 | #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ |
<> | 135:176b8275d35d | 436 | #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ |
<> | 135:176b8275d35d | 437 | #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 438 | #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ |
<> | 135:176b8275d35d | 439 | #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ |
<> | 135:176b8275d35d | 440 | #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ |
Kojto | 122:f9eeca106725 | 441 | /** |
Kojto | 122:f9eeca106725 | 442 | * @} |
Kojto | 122:f9eeca106725 | 443 | */ |
Kojto | 122:f9eeca106725 | 444 | #endif /* STM32F302xE || */ |
Kojto | 122:f9eeca106725 | 445 | /* STM32F302xC || */ |
<> | 135:176b8275d35d | 446 | /* STM32F303x8 || STM32F328xx || */ |
Kojto | 122:f9eeca106725 | 447 | /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
Kojto | 122:f9eeca106725 | 448 | |
<> | 135:176b8275d35d | 449 | |
<> | 135:176b8275d35d | 450 | #if defined(STM32F334x8) |
Kojto | 122:f9eeca106725 | 451 | /** @defgroup TIMEx_Remap TIMEx Remapping 1 |
Kojto | 122:f9eeca106725 | 452 | * @{ |
Kojto | 122:f9eeca106725 | 453 | */ |
<> | 135:176b8275d35d | 454 | #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 455 | #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ |
<> | 135:176b8275d35d | 456 | #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ |
<> | 135:176b8275d35d | 457 | #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ |
<> | 135:176b8275d35d | 458 | #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 459 | #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ |
<> | 135:176b8275d35d | 460 | #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ |
<> | 135:176b8275d35d | 461 | #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ |
Kojto | 122:f9eeca106725 | 462 | /** |
Kojto | 122:f9eeca106725 | 463 | * @} |
Kojto | 122:f9eeca106725 | 464 | */ |
Kojto | 122:f9eeca106725 | 465 | |
Kojto | 122:f9eeca106725 | 466 | /** @defgroup TIMEx_Remap2 TIMEx Remapping 2 |
Kojto | 122:f9eeca106725 | 467 | * @{ |
Kojto | 122:f9eeca106725 | 468 | */ |
<> | 135:176b8275d35d | 469 | #define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 470 | #define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */ |
<> | 135:176b8275d35d | 471 | #define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */ |
<> | 135:176b8275d35d | 472 | #define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */ |
<> | 135:176b8275d35d | 473 | #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ |
<> | 135:176b8275d35d | 474 | /** |
<> | 135:176b8275d35d | 475 | * @} |
<> | 135:176b8275d35d | 476 | */ |
<> | 135:176b8275d35d | 477 | #endif /* STM32F334x8 */ |
<> | 135:176b8275d35d | 478 | |
<> | 135:176b8275d35d | 479 | #if defined(STM32F303xC) || defined(STM32F358xx) |
<> | 135:176b8275d35d | 480 | /** @defgroup TIMEx_Remap TIMEx Remapping 1 |
<> | 135:176b8275d35d | 481 | * @{ |
<> | 135:176b8275d35d | 482 | */ |
<> | 135:176b8275d35d | 483 | #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 484 | #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ |
<> | 135:176b8275d35d | 485 | #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ |
<> | 135:176b8275d35d | 486 | #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ |
<> | 135:176b8275d35d | 487 | #define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 488 | #define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ |
<> | 135:176b8275d35d | 489 | #define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ |
<> | 135:176b8275d35d | 490 | #define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ |
<> | 135:176b8275d35d | 491 | #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 492 | #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ |
<> | 135:176b8275d35d | 493 | #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ |
<> | 135:176b8275d35d | 494 | #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ |
<> | 135:176b8275d35d | 495 | /** |
<> | 135:176b8275d35d | 496 | * @} |
<> | 135:176b8275d35d | 497 | */ |
<> | 135:176b8275d35d | 498 | |
<> | 135:176b8275d35d | 499 | /** @defgroup TIMEx_Remap2 TIMEx Remapping 2 |
<> | 135:176b8275d35d | 500 | * @{ |
<> | 135:176b8275d35d | 501 | */ |
<> | 135:176b8275d35d | 502 | #define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 503 | #define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ |
<> | 135:176b8275d35d | 504 | #define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ |
<> | 135:176b8275d35d | 505 | #define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ |
<> | 135:176b8275d35d | 506 | #define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 507 | #define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ |
<> | 135:176b8275d35d | 508 | #define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ |
<> | 135:176b8275d35d | 509 | #define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ |
<> | 135:176b8275d35d | 510 | #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ |
Kojto | 122:f9eeca106725 | 511 | /** |
Kojto | 122:f9eeca106725 | 512 | * @} |
Kojto | 122:f9eeca106725 | 513 | */ |
Kojto | 122:f9eeca106725 | 514 | #endif /* STM32F303xC || STM32F358xx */ |
Kojto | 122:f9eeca106725 | 515 | |
Kojto | 122:f9eeca106725 | 516 | #if defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 122:f9eeca106725 | 517 | /** @defgroup TIMEx_Remap TIMEx Remapping 1 |
Kojto | 122:f9eeca106725 | 518 | * @{ |
Kojto | 122:f9eeca106725 | 519 | */ |
<> | 135:176b8275d35d | 520 | #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 521 | #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ |
<> | 135:176b8275d35d | 522 | #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ |
<> | 135:176b8275d35d | 523 | #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ |
<> | 135:176b8275d35d | 524 | #define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 525 | #define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ |
<> | 135:176b8275d35d | 526 | #define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ |
<> | 135:176b8275d35d | 527 | #define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ |
<> | 135:176b8275d35d | 528 | #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 529 | #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ |
<> | 135:176b8275d35d | 530 | #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ |
<> | 135:176b8275d35d | 531 | #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ |
<> | 135:176b8275d35d | 532 | #define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 533 | #define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */ |
<> | 135:176b8275d35d | 534 | #define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */ |
<> | 135:176b8275d35d | 535 | #define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */ |
Kojto | 122:f9eeca106725 | 536 | /** |
Kojto | 122:f9eeca106725 | 537 | * @} |
Kojto | 122:f9eeca106725 | 538 | */ |
Kojto | 122:f9eeca106725 | 539 | |
Kojto | 122:f9eeca106725 | 540 | /** @defgroup TIMEx_Remap2 TIMEx Remapping 2 |
Kojto | 122:f9eeca106725 | 541 | * @{ |
Kojto | 122:f9eeca106725 | 542 | */ |
<> | 135:176b8275d35d | 543 | #define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
<> | 135:176b8275d35d | 544 | #define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ |
<> | 135:176b8275d35d | 545 | #define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ |
<> | 135:176b8275d35d | 546 | #define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ |
<> | 135:176b8275d35d | 547 | #define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 548 | #define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ |
<> | 135:176b8275d35d | 549 | #define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ |
<> | 135:176b8275d35d | 550 | #define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ |
<> | 135:176b8275d35d | 551 | #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ |
<> | 135:176b8275d35d | 552 | #define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ |
<> | 135:176b8275d35d | 553 | #define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */ |
<> | 135:176b8275d35d | 554 | #define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */ |
<> | 135:176b8275d35d | 555 | #define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */ |
Kojto | 122:f9eeca106725 | 556 | /** |
Kojto | 122:f9eeca106725 | 557 | * @} |
Kojto | 122:f9eeca106725 | 558 | */ |
Kojto | 122:f9eeca106725 | 559 | #endif /* STM32F303xE || STM32F398xx */ |
Kojto | 122:f9eeca106725 | 560 | |
Kojto | 122:f9eeca106725 | 561 | |
Kojto | 122:f9eeca106725 | 562 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 122:f9eeca106725 | 563 | /** @defgroup TIMEx_Remap TIMEx remapping |
Kojto | 122:f9eeca106725 | 564 | * @{ |
Kojto | 122:f9eeca106725 | 565 | */ |
<> | 135:176b8275d35d | 566 | #define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */ |
<> | 135:176b8275d35d | 567 | #define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */ |
<> | 135:176b8275d35d | 568 | #define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */ |
<> | 135:176b8275d35d | 569 | #define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */ |
<> | 135:176b8275d35d | 570 | #define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 571 | #define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ |
<> | 135:176b8275d35d | 572 | #define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ |
<> | 135:176b8275d35d | 573 | #define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ |
Kojto | 122:f9eeca106725 | 574 | /** |
Kojto | 122:f9eeca106725 | 575 | * @} |
Kojto | 122:f9eeca106725 | 576 | */ |
Kojto | 122:f9eeca106725 | 577 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 122:f9eeca106725 | 578 | |
Kojto | 122:f9eeca106725 | 579 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 122:f9eeca106725 | 580 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 122:f9eeca106725 | 581 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 122:f9eeca106725 | 582 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
<> | 135:176b8275d35d | 583 | /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3 |
Kojto | 122:f9eeca106725 | 584 | * @{ |
Kojto | 122:f9eeca106725 | 585 | */ |
<> | 135:176b8275d35d | 586 | #define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
Kojto | 122:f9eeca106725 | 587 | #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
Kojto | 122:f9eeca106725 | 588 | #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
Kojto | 122:f9eeca106725 | 589 | #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
Kojto | 122:f9eeca106725 | 590 | /** |
Kojto | 122:f9eeca106725 | 591 | * @} |
Kojto | 122:f9eeca106725 | 592 | */ |
Kojto | 122:f9eeca106725 | 593 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 122:f9eeca106725 | 594 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 122:f9eeca106725 | 595 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 122:f9eeca106725 | 596 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 122:f9eeca106725 | 597 | |
Kojto | 122:f9eeca106725 | 598 | /** |
Kojto | 122:f9eeca106725 | 599 | * @} |
Kojto | 122:f9eeca106725 | 600 | */ |
Kojto | 122:f9eeca106725 | 601 | |
Kojto | 122:f9eeca106725 | 602 | |
Kojto | 122:f9eeca106725 | 603 | /* Private Macros -----------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 604 | /** @defgroup TIM_Private_Macros TIM Private Macros |
Kojto | 122:f9eeca106725 | 605 | * @{ |
Kojto | 122:f9eeca106725 | 606 | */ |
Kojto | 122:f9eeca106725 | 607 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 122:f9eeca106725 | 608 | |
Kojto | 122:f9eeca106725 | 609 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 610 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
Kojto | 122:f9eeca106725 | 611 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
Kojto | 122:f9eeca106725 | 612 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
Kojto | 122:f9eeca106725 | 613 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
Kojto | 122:f9eeca106725 | 614 | |
Kojto | 122:f9eeca106725 | 615 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 616 | ((CHANNEL) == TIM_CHANNEL_2)) |
Kojto | 122:f9eeca106725 | 617 | |
Kojto | 122:f9eeca106725 | 618 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 619 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
Kojto | 122:f9eeca106725 | 620 | ((CHANNEL) == TIM_CHANNEL_3)) |
Kojto | 122:f9eeca106725 | 621 | |
Kojto | 122:f9eeca106725 | 622 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
Kojto | 122:f9eeca106725 | 623 | ((MODE) == TIM_OCMODE_PWM2)) |
Kojto | 122:f9eeca106725 | 624 | |
Kojto | 122:f9eeca106725 | 625 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
Kojto | 122:f9eeca106725 | 626 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
Kojto | 122:f9eeca106725 | 627 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
Kojto | 122:f9eeca106725 | 628 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
Kojto | 122:f9eeca106725 | 629 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
Kojto | 122:f9eeca106725 | 630 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
Kojto | 122:f9eeca106725 | 631 | |
Kojto | 122:f9eeca106725 | 632 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ |
Kojto | 122:f9eeca106725 | 633 | ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) |
Kojto | 122:f9eeca106725 | 634 | |
Kojto | 122:f9eeca106725 | 635 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
Kojto | 122:f9eeca106725 | 636 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
Kojto | 122:f9eeca106725 | 637 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
Kojto | 122:f9eeca106725 | 638 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
Kojto | 122:f9eeca106725 | 639 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
Kojto | 122:f9eeca106725 | 640 | |
<> | 135:176b8275d35d | 641 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
Kojto | 122:f9eeca106725 | 642 | |
Kojto | 122:f9eeca106725 | 643 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
Kojto | 122:f9eeca106725 | 644 | ((BASE) == TIM_DMABASE_CR2) || \ |
Kojto | 122:f9eeca106725 | 645 | ((BASE) == TIM_DMABASE_SMCR) || \ |
Kojto | 122:f9eeca106725 | 646 | ((BASE) == TIM_DMABASE_DIER) || \ |
Kojto | 122:f9eeca106725 | 647 | ((BASE) == TIM_DMABASE_SR) || \ |
Kojto | 122:f9eeca106725 | 648 | ((BASE) == TIM_DMABASE_EGR) || \ |
Kojto | 122:f9eeca106725 | 649 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
Kojto | 122:f9eeca106725 | 650 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
Kojto | 122:f9eeca106725 | 651 | ((BASE) == TIM_DMABASE_CCER) || \ |
Kojto | 122:f9eeca106725 | 652 | ((BASE) == TIM_DMABASE_CNT) || \ |
Kojto | 122:f9eeca106725 | 653 | ((BASE) == TIM_DMABASE_PSC) || \ |
Kojto | 122:f9eeca106725 | 654 | ((BASE) == TIM_DMABASE_ARR) || \ |
Kojto | 122:f9eeca106725 | 655 | ((BASE) == TIM_DMABASE_RCR) || \ |
Kojto | 122:f9eeca106725 | 656 | ((BASE) == TIM_DMABASE_CCR1) || \ |
Kojto | 122:f9eeca106725 | 657 | ((BASE) == TIM_DMABASE_CCR2) || \ |
Kojto | 122:f9eeca106725 | 658 | ((BASE) == TIM_DMABASE_CCR3) || \ |
Kojto | 122:f9eeca106725 | 659 | ((BASE) == TIM_DMABASE_CCR4) || \ |
Kojto | 122:f9eeca106725 | 660 | ((BASE) == TIM_DMABASE_BDTR) || \ |
Kojto | 122:f9eeca106725 | 661 | ((BASE) == TIM_DMABASE_DCR) || \ |
Kojto | 122:f9eeca106725 | 662 | ((BASE) == TIM_DMABASE_OR)) |
Kojto | 122:f9eeca106725 | 663 | |
Kojto | 122:f9eeca106725 | 664 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 122:f9eeca106725 | 665 | |
Kojto | 122:f9eeca106725 | 666 | |
Kojto | 122:f9eeca106725 | 667 | |
Kojto | 122:f9eeca106725 | 668 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 122:f9eeca106725 | 669 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 122:f9eeca106725 | 670 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 122:f9eeca106725 | 671 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 122:f9eeca106725 | 672 | |
Kojto | 122:f9eeca106725 | 673 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 674 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
Kojto | 122:f9eeca106725 | 675 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
Kojto | 122:f9eeca106725 | 676 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
Kojto | 122:f9eeca106725 | 677 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
Kojto | 122:f9eeca106725 | 678 | ((CHANNEL) == TIM_CHANNEL_6) || \ |
Kojto | 122:f9eeca106725 | 679 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
Kojto | 122:f9eeca106725 | 680 | |
Kojto | 122:f9eeca106725 | 681 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 682 | ((CHANNEL) == TIM_CHANNEL_2)) |
Kojto | 122:f9eeca106725 | 683 | |
Kojto | 122:f9eeca106725 | 684 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
Kojto | 122:f9eeca106725 | 685 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
Kojto | 122:f9eeca106725 | 686 | ((CHANNEL) == TIM_CHANNEL_3)) |
Kojto | 122:f9eeca106725 | 687 | |
bogdanm | 86:04dd9b1680ae | 688 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
bogdanm | 86:04dd9b1680ae | 689 | ((MODE) == TIM_OCMODE_PWM2) || \ |
bogdanm | 86:04dd9b1680ae | 690 | ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \ |
bogdanm | 86:04dd9b1680ae | 691 | ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \ |
bogdanm | 86:04dd9b1680ae | 692 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ |
bogdanm | 86:04dd9b1680ae | 693 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2)) |
bogdanm | 86:04dd9b1680ae | 694 | |
bogdanm | 86:04dd9b1680ae | 695 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
bogdanm | 86:04dd9b1680ae | 696 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
bogdanm | 86:04dd9b1680ae | 697 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
bogdanm | 86:04dd9b1680ae | 698 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
bogdanm | 86:04dd9b1680ae | 699 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
bogdanm | 86:04dd9b1680ae | 700 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \ |
bogdanm | 86:04dd9b1680ae | 701 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ |
bogdanm | 86:04dd9b1680ae | 702 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2)) |
bogdanm | 86:04dd9b1680ae | 703 | |
bogdanm | 86:04dd9b1680ae | 704 | #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
bogdanm | 86:04dd9b1680ae | 705 | ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ |
bogdanm | 86:04dd9b1680ae | 706 | ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) |
bogdanm | 86:04dd9b1680ae | 707 | |
<> | 135:176b8275d35d | 708 | #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU) |
bogdanm | 86:04dd9b1680ae | 709 | |
bogdanm | 86:04dd9b1680ae | 710 | #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \ |
bogdanm | 86:04dd9b1680ae | 711 | ((STATE) == TIM_BREAK2_DISABLE)) |
bogdanm | 86:04dd9b1680ae | 712 | |
bogdanm | 86:04dd9b1680ae | 713 | #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \ |
bogdanm | 86:04dd9b1680ae | 714 | ((POLARITY) == TIM_BREAK2POLARITY_HIGH)) |
bogdanm | 86:04dd9b1680ae | 715 | |
bogdanm | 86:04dd9b1680ae | 716 | #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \ |
bogdanm | 86:04dd9b1680ae | 717 | ((SOURCE) == TIM_TRGO2_ENABLE) || \ |
bogdanm | 86:04dd9b1680ae | 718 | ((SOURCE) == TIM_TRGO2_UPDATE) || \ |
bogdanm | 86:04dd9b1680ae | 719 | ((SOURCE) == TIM_TRGO2_OC1) || \ |
bogdanm | 86:04dd9b1680ae | 720 | ((SOURCE) == TIM_TRGO2_OC1REF) || \ |
bogdanm | 86:04dd9b1680ae | 721 | ((SOURCE) == TIM_TRGO2_OC2REF) || \ |
bogdanm | 86:04dd9b1680ae | 722 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
bogdanm | 86:04dd9b1680ae | 723 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
bogdanm | 86:04dd9b1680ae | 724 | ((SOURCE) == TIM_TRGO2_OC4REF) || \ |
bogdanm | 86:04dd9b1680ae | 725 | ((SOURCE) == TIM_TRGO2_OC5REF) || \ |
bogdanm | 86:04dd9b1680ae | 726 | ((SOURCE) == TIM_TRGO2_OC6REF) || \ |
bogdanm | 86:04dd9b1680ae | 727 | ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ |
bogdanm | 86:04dd9b1680ae | 728 | ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ |
bogdanm | 86:04dd9b1680ae | 729 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ |
bogdanm | 86:04dd9b1680ae | 730 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ |
bogdanm | 86:04dd9b1680ae | 731 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ |
bogdanm | 86:04dd9b1680ae | 732 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) |
bogdanm | 86:04dd9b1680ae | 733 | |
bogdanm | 86:04dd9b1680ae | 734 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
bogdanm | 86:04dd9b1680ae | 735 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
bogdanm | 86:04dd9b1680ae | 736 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
bogdanm | 86:04dd9b1680ae | 737 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
bogdanm | 86:04dd9b1680ae | 738 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ |
bogdanm | 86:04dd9b1680ae | 739 | ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) |
bogdanm | 86:04dd9b1680ae | 740 | |
<> | 135:176b8275d35d | 741 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
Kojto | 122:f9eeca106725 | 742 | |
Kojto | 122:f9eeca106725 | 743 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
Kojto | 122:f9eeca106725 | 744 | ((BASE) == TIM_DMABASE_CR2) || \ |
Kojto | 122:f9eeca106725 | 745 | ((BASE) == TIM_DMABASE_SMCR) || \ |
Kojto | 122:f9eeca106725 | 746 | ((BASE) == TIM_DMABASE_DIER) || \ |
Kojto | 122:f9eeca106725 | 747 | ((BASE) == TIM_DMABASE_SR) || \ |
Kojto | 122:f9eeca106725 | 748 | ((BASE) == TIM_DMABASE_EGR) || \ |
Kojto | 122:f9eeca106725 | 749 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
Kojto | 122:f9eeca106725 | 750 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
Kojto | 122:f9eeca106725 | 751 | ((BASE) == TIM_DMABASE_CCER) || \ |
Kojto | 122:f9eeca106725 | 752 | ((BASE) == TIM_DMABASE_CNT) || \ |
Kojto | 122:f9eeca106725 | 753 | ((BASE) == TIM_DMABASE_PSC) || \ |
Kojto | 122:f9eeca106725 | 754 | ((BASE) == TIM_DMABASE_ARR) || \ |
Kojto | 122:f9eeca106725 | 755 | ((BASE) == TIM_DMABASE_RCR) || \ |
Kojto | 122:f9eeca106725 | 756 | ((BASE) == TIM_DMABASE_CCR1) || \ |
Kojto | 122:f9eeca106725 | 757 | ((BASE) == TIM_DMABASE_CCR2) || \ |
Kojto | 122:f9eeca106725 | 758 | ((BASE) == TIM_DMABASE_CCR3) || \ |
Kojto | 122:f9eeca106725 | 759 | ((BASE) == TIM_DMABASE_CCR4) || \ |
Kojto | 122:f9eeca106725 | 760 | ((BASE) == TIM_DMABASE_BDTR) || \ |
Kojto | 122:f9eeca106725 | 761 | ((BASE) == TIM_DMABASE_CCMR3) || \ |
Kojto | 122:f9eeca106725 | 762 | ((BASE) == TIM_DMABASE_CCR5) || \ |
Kojto | 122:f9eeca106725 | 763 | ((BASE) == TIM_DMABASE_CCR6) || \ |
Kojto | 122:f9eeca106725 | 764 | ((BASE) == TIM_DMABASE_OR)) |
Kojto | 122:f9eeca106725 | 765 | |
bogdanm | 92:4fc01daae5a5 | 766 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 86:04dd9b1680ae | 767 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 92:4fc01daae5a5 | 768 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 769 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 86:04dd9b1680ae | 770 | |
bogdanm | 92:4fc01daae5a5 | 771 | #if defined(STM32F302xE) || \ |
bogdanm | 92:4fc01daae5a5 | 772 | defined(STM32F302xC) || \ |
<> | 135:176b8275d35d | 773 | defined(STM32F303x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 774 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 86:04dd9b1680ae | 775 | |
bogdanm | 86:04dd9b1680ae | 776 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\ |
bogdanm | 86:04dd9b1680ae | 777 | ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\ |
bogdanm | 86:04dd9b1680ae | 778 | ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\ |
bogdanm | 86:04dd9b1680ae | 779 | ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\ |
bogdanm | 86:04dd9b1680ae | 780 | ((REMAP) == TIM_TIM16_GPIO) ||\ |
bogdanm | 86:04dd9b1680ae | 781 | ((REMAP) == TIM_TIM16_RTC) ||\ |
bogdanm | 86:04dd9b1680ae | 782 | ((REMAP) == TIM_TIM16_HSE) ||\ |
bogdanm | 86:04dd9b1680ae | 783 | ((REMAP) == TIM_TIM16_MCO)) |
Kojto | 122:f9eeca106725 | 784 | |
bogdanm | 92:4fc01daae5a5 | 785 | #endif /* STM32F302xE || */ |
bogdanm | 92:4fc01daae5a5 | 786 | /* STM32F302xC || */ |
<> | 135:176b8275d35d | 787 | /* STM32F303x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 788 | /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
bogdanm | 86:04dd9b1680ae | 789 | |
<> | 135:176b8275d35d | 790 | #if defined(STM32F334x8) |
<> | 135:176b8275d35d | 791 | #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ |
<> | 135:176b8275d35d | 792 | ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\ |
<> | 135:176b8275d35d | 793 | ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\ |
<> | 135:176b8275d35d | 794 | ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\ |
<> | 135:176b8275d35d | 795 | ((REMAP1) == TIM_TIM16_GPIO) ||\ |
<> | 135:176b8275d35d | 796 | ((REMAP1) == TIM_TIM16_RTC) ||\ |
<> | 135:176b8275d35d | 797 | ((REMAP1) == TIM_TIM16_HSE) ||\ |
<> | 135:176b8275d35d | 798 | ((REMAP1) == TIM_TIM16_MCO)) |
<> | 135:176b8275d35d | 799 | |
<> | 135:176b8275d35d | 800 | #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\ |
<> | 135:176b8275d35d | 801 | ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\ |
<> | 135:176b8275d35d | 802 | ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\ |
<> | 135:176b8275d35d | 803 | ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\ |
<> | 135:176b8275d35d | 804 | ((REMAP2) == TIM_TIM16_NONE)) |
<> | 135:176b8275d35d | 805 | |
<> | 135:176b8275d35d | 806 | #endif /* STM32F334x8 */ |
<> | 135:176b8275d35d | 807 | |
bogdanm | 86:04dd9b1680ae | 808 | #if defined(STM32F303xC) || defined(STM32F358xx) |
bogdanm | 86:04dd9b1680ae | 809 | |
bogdanm | 86:04dd9b1680ae | 810 | #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ |
bogdanm | 86:04dd9b1680ae | 811 | ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\ |
bogdanm | 86:04dd9b1680ae | 812 | ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\ |
bogdanm | 86:04dd9b1680ae | 813 | ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\ |
bogdanm | 86:04dd9b1680ae | 814 | ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\ |
bogdanm | 86:04dd9b1680ae | 815 | ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\ |
bogdanm | 86:04dd9b1680ae | 816 | ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\ |
bogdanm | 86:04dd9b1680ae | 817 | ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\ |
bogdanm | 86:04dd9b1680ae | 818 | ((REMAP1) == TIM_TIM16_GPIO) ||\ |
bogdanm | 86:04dd9b1680ae | 819 | ((REMAP1) == TIM_TIM16_RTC) ||\ |
bogdanm | 86:04dd9b1680ae | 820 | ((REMAP1) == TIM_TIM16_HSE) ||\ |
bogdanm | 86:04dd9b1680ae | 821 | ((REMAP1) == TIM_TIM16_MCO)) |
bogdanm | 86:04dd9b1680ae | 822 | |
bogdanm | 86:04dd9b1680ae | 823 | #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\ |
bogdanm | 86:04dd9b1680ae | 824 | ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\ |
bogdanm | 86:04dd9b1680ae | 825 | ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\ |
bogdanm | 86:04dd9b1680ae | 826 | ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\ |
bogdanm | 86:04dd9b1680ae | 827 | ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\ |
bogdanm | 86:04dd9b1680ae | 828 | ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\ |
bogdanm | 86:04dd9b1680ae | 829 | ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\ |
bogdanm | 86:04dd9b1680ae | 830 | ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\ |
bogdanm | 86:04dd9b1680ae | 831 | ((REMAP2) == TIM_TIM16_NONE)) |
Kojto | 122:f9eeca106725 | 832 | |
bogdanm | 86:04dd9b1680ae | 833 | #endif /* STM32F303xC || STM32F358xx */ |
bogdanm | 86:04dd9b1680ae | 834 | |
bogdanm | 92:4fc01daae5a5 | 835 | #if defined(STM32F303xE) || defined(STM32F398xx) |
bogdanm | 92:4fc01daae5a5 | 836 | |
bogdanm | 92:4fc01daae5a5 | 837 | #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 838 | ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 839 | ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 840 | ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\ |
bogdanm | 92:4fc01daae5a5 | 841 | ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 842 | ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 843 | ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 844 | ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\ |
bogdanm | 92:4fc01daae5a5 | 845 | ((REMAP1) == TIM_TIM16_GPIO) ||\ |
bogdanm | 92:4fc01daae5a5 | 846 | ((REMAP1) == TIM_TIM16_RTC) ||\ |
bogdanm | 92:4fc01daae5a5 | 847 | ((REMAP1) == TIM_TIM16_HSE) ||\ |
bogdanm | 92:4fc01daae5a5 | 848 | ((REMAP1) == TIM_TIM16_MCO) ||\ |
bogdanm | 92:4fc01daae5a5 | 849 | ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 850 | ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 851 | ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 852 | ((REMAP1) == TIM_TIM20_ADC3_AWD3)) |
bogdanm | 92:4fc01daae5a5 | 853 | |
bogdanm | 92:4fc01daae5a5 | 854 | #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 855 | ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 856 | ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 857 | ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\ |
bogdanm | 92:4fc01daae5a5 | 858 | ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 859 | ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 860 | ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 861 | ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\ |
bogdanm | 92:4fc01daae5a5 | 862 | ((REMAP2) == TIM_TIM16_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 863 | ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\ |
bogdanm | 92:4fc01daae5a5 | 864 | ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\ |
bogdanm | 92:4fc01daae5a5 | 865 | ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\ |
bogdanm | 92:4fc01daae5a5 | 866 | ((REMAP2) == TIM_TIM20_ADC4_AWD3)) |
Kojto | 122:f9eeca106725 | 867 | |
bogdanm | 92:4fc01daae5a5 | 868 | #endif /* STM32F303xE || STM32F398xx */ |
bogdanm | 92:4fc01daae5a5 | 869 | |
bogdanm | 86:04dd9b1680ae | 870 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 86:04dd9b1680ae | 871 | |
bogdanm | 86:04dd9b1680ae | 872 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\ |
bogdanm | 86:04dd9b1680ae | 873 | ((REMAP) == TIM_TIM2_ETH_PTP) ||\ |
bogdanm | 86:04dd9b1680ae | 874 | ((REMAP) == TIM_TIM2_USBFS_SOF) ||\ |
bogdanm | 86:04dd9b1680ae | 875 | ((REMAP) == TIM_TIM2_USBHS_SOF) ||\ |
bogdanm | 86:04dd9b1680ae | 876 | ((REMAP) == TIM_TIM14_GPIO) ||\ |
bogdanm | 86:04dd9b1680ae | 877 | ((REMAP) == TIM_TIM14_RTC) ||\ |
bogdanm | 86:04dd9b1680ae | 878 | ((REMAP) == TIM_TIM14_HSE) ||\ |
bogdanm | 86:04dd9b1680ae | 879 | ((REMAP) == TIM_TIM14_MCO)) |
bogdanm | 86:04dd9b1680ae | 880 | |
bogdanm | 86:04dd9b1680ae | 881 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 86:04dd9b1680ae | 882 | |
Kojto | 122:f9eeca106725 | 883 | |
bogdanm | 92:4fc01daae5a5 | 884 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 92:4fc01daae5a5 | 885 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 92:4fc01daae5a5 | 886 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 887 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 86:04dd9b1680ae | 888 | |
<> | 135:176b8275d35d | 889 | #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U)) |
Kojto | 122:f9eeca106725 | 890 | |
bogdanm | 92:4fc01daae5a5 | 891 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 86:04dd9b1680ae | 892 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 92:4fc01daae5a5 | 893 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 894 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 122:f9eeca106725 | 895 | |
<> | 135:176b8275d35d | 896 | #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) |
bogdanm | 92:4fc01daae5a5 | 897 | |
bogdanm | 86:04dd9b1680ae | 898 | /** |
bogdanm | 86:04dd9b1680ae | 899 | * @} |
Kojto | 122:f9eeca106725 | 900 | */ |
Kojto | 122:f9eeca106725 | 901 | /* End of private macros -----------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 902 | |
bogdanm | 86:04dd9b1680ae | 903 | |
bogdanm | 86:04dd9b1680ae | 904 | /* Exported macro ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 905 | /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros |
bogdanm | 92:4fc01daae5a5 | 906 | * @{ |
Kojto | 122:f9eeca106725 | 907 | */ |
bogdanm | 92:4fc01daae5a5 | 908 | |
bogdanm | 86:04dd9b1680ae | 909 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 86:04dd9b1680ae | 910 | /** |
bogdanm | 86:04dd9b1680ae | 911 | * @brief Sets the TIM Capture Compare Register value on runtime without |
bogdanm | 86:04dd9b1680ae | 912 | * calling another time ConfigChannel function. |
bogdanm | 86:04dd9b1680ae | 913 | * @param __HANDLE__: TIM handle. |
Kojto | 122:f9eeca106725 | 914 | * @param __CHANNEL__: TIM Channels to be configured. |
bogdanm | 86:04dd9b1680ae | 915 | * This parameter can be one of the following values: |
bogdanm | 86:04dd9b1680ae | 916 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
bogdanm | 86:04dd9b1680ae | 917 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
bogdanm | 86:04dd9b1680ae | 918 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
bogdanm | 86:04dd9b1680ae | 919 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
bogdanm | 86:04dd9b1680ae | 920 | * @param __COMPARE__: specifies the Capture Compare register new value. |
bogdanm | 86:04dd9b1680ae | 921 | * @retval None |
bogdanm | 86:04dd9b1680ae | 922 | */ |
Kojto | 122:f9eeca106725 | 923 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
<> | 135:176b8275d35d | 924 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) |
bogdanm | 86:04dd9b1680ae | 925 | |
bogdanm | 86:04dd9b1680ae | 926 | /** |
bogdanm | 86:04dd9b1680ae | 927 | * @brief Gets the TIM Capture Compare Register value on runtime |
bogdanm | 86:04dd9b1680ae | 928 | * @param __HANDLE__: TIM handle. |
Kojto | 122:f9eeca106725 | 929 | * @param __CHANNEL__: TIM Channel associated with the capture compare register |
bogdanm | 86:04dd9b1680ae | 930 | * This parameter can be one of the following values: |
bogdanm | 86:04dd9b1680ae | 931 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
bogdanm | 86:04dd9b1680ae | 932 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
bogdanm | 86:04dd9b1680ae | 933 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
bogdanm | 86:04dd9b1680ae | 934 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
bogdanm | 86:04dd9b1680ae | 935 | * @retval None |
bogdanm | 86:04dd9b1680ae | 936 | */ |
Kojto | 122:f9eeca106725 | 937 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
<> | 135:176b8275d35d | 938 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) |
<> | 135:176b8275d35d | 939 | |
<> | 135:176b8275d35d | 940 | /** |
<> | 135:176b8275d35d | 941 | * @brief Sets the TIM Output compare preload. |
<> | 135:176b8275d35d | 942 | * @param __HANDLE__: TIM handle. |
<> | 135:176b8275d35d | 943 | * @param __CHANNEL__: TIM Channels to be configured. |
<> | 135:176b8275d35d | 944 | * This parameter can be one of the following values: |
<> | 135:176b8275d35d | 945 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 135:176b8275d35d | 946 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 135:176b8275d35d | 947 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 135:176b8275d35d | 948 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 135:176b8275d35d | 949 | * @retval None |
<> | 135:176b8275d35d | 950 | */ |
<> | 135:176b8275d35d | 951 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
<> | 135:176b8275d35d | 952 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
<> | 135:176b8275d35d | 953 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
<> | 135:176b8275d35d | 954 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
<> | 135:176b8275d35d | 955 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) |
<> | 135:176b8275d35d | 956 | |
<> | 135:176b8275d35d | 957 | /** |
<> | 135:176b8275d35d | 958 | * @brief Resets the TIM Output compare preload. |
<> | 135:176b8275d35d | 959 | * @param __HANDLE__: TIM handle. |
<> | 135:176b8275d35d | 960 | * @param __CHANNEL__: TIM Channels to be configured. |
<> | 135:176b8275d35d | 961 | * This parameter can be one of the following values: |
<> | 135:176b8275d35d | 962 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 135:176b8275d35d | 963 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 135:176b8275d35d | 964 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 135:176b8275d35d | 965 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 135:176b8275d35d | 966 | * @retval None |
<> | 135:176b8275d35d | 967 | */ |
<> | 135:176b8275d35d | 968 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
<> | 135:176b8275d35d | 969 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ |
<> | 135:176b8275d35d | 970 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ |
<> | 135:176b8275d35d | 971 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ |
<> | 135:176b8275d35d | 972 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) |
<> | 135:176b8275d35d | 973 | |
bogdanm | 86:04dd9b1680ae | 974 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 122:f9eeca106725 | 975 | |
bogdanm | 92:4fc01daae5a5 | 976 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 92:4fc01daae5a5 | 977 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 92:4fc01daae5a5 | 978 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 979 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 86:04dd9b1680ae | 980 | /** |
bogdanm | 86:04dd9b1680ae | 981 | * @brief Sets the TIM Capture Compare Register value on runtime without |
bogdanm | 86:04dd9b1680ae | 982 | * calling another time ConfigChannel function. |
bogdanm | 86:04dd9b1680ae | 983 | * @param __HANDLE__: TIM handle. |
Kojto | 122:f9eeca106725 | 984 | * @param __CHANNEL__: TIM Channels to be configured. |
bogdanm | 86:04dd9b1680ae | 985 | * This parameter can be one of the following values: |
bogdanm | 86:04dd9b1680ae | 986 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
bogdanm | 86:04dd9b1680ae | 987 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
bogdanm | 86:04dd9b1680ae | 988 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
bogdanm | 86:04dd9b1680ae | 989 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
bogdanm | 86:04dd9b1680ae | 990 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
bogdanm | 86:04dd9b1680ae | 991 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
bogdanm | 86:04dd9b1680ae | 992 | * @param __COMPARE__: specifies the Capture Compare register new value. |
bogdanm | 86:04dd9b1680ae | 993 | * @retval None |
bogdanm | 86:04dd9b1680ae | 994 | */ |
Kojto | 122:f9eeca106725 | 995 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
bogdanm | 86:04dd9b1680ae | 996 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
bogdanm | 86:04dd9b1680ae | 997 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
bogdanm | 86:04dd9b1680ae | 998 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
bogdanm | 86:04dd9b1680ae | 999 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ |
bogdanm | 86:04dd9b1680ae | 1000 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ |
Kojto | 122:f9eeca106725 | 1001 | ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) |
bogdanm | 86:04dd9b1680ae | 1002 | |
bogdanm | 86:04dd9b1680ae | 1003 | /** |
bogdanm | 86:04dd9b1680ae | 1004 | * @brief Gets the TIM Capture Compare Register value on runtime |
bogdanm | 86:04dd9b1680ae | 1005 | * @param __HANDLE__: TIM handle. |
Kojto | 122:f9eeca106725 | 1006 | * @param __CHANNEL__: TIM Channel associated with the capture compare register |
bogdanm | 86:04dd9b1680ae | 1007 | * This parameter can be one of the following values: |
bogdanm | 86:04dd9b1680ae | 1008 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
bogdanm | 86:04dd9b1680ae | 1009 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
bogdanm | 86:04dd9b1680ae | 1010 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
bogdanm | 86:04dd9b1680ae | 1011 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
bogdanm | 86:04dd9b1680ae | 1012 | * @arg TIM_CHANNEL_5: get capture/compare 5 register value |
bogdanm | 86:04dd9b1680ae | 1013 | * @arg TIM_CHANNEL_6: get capture/compare 6 register value |
bogdanm | 86:04dd9b1680ae | 1014 | * @retval None |
bogdanm | 86:04dd9b1680ae | 1015 | */ |
Kojto | 122:f9eeca106725 | 1016 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
bogdanm | 86:04dd9b1680ae | 1017 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
bogdanm | 86:04dd9b1680ae | 1018 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
bogdanm | 86:04dd9b1680ae | 1019 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
bogdanm | 86:04dd9b1680ae | 1020 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ |
bogdanm | 86:04dd9b1680ae | 1021 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ |
bogdanm | 86:04dd9b1680ae | 1022 | ((__HANDLE__)->Instance->CCR6)) |
<> | 135:176b8275d35d | 1023 | |
<> | 135:176b8275d35d | 1024 | /** |
<> | 135:176b8275d35d | 1025 | * @brief Sets the TIM Output compare preload. |
<> | 135:176b8275d35d | 1026 | * @param __HANDLE__: TIM handle. |
<> | 135:176b8275d35d | 1027 | * @param __CHANNEL__: TIM Channels to be configured. |
<> | 135:176b8275d35d | 1028 | * This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1029 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 135:176b8275d35d | 1030 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 135:176b8275d35d | 1031 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 135:176b8275d35d | 1032 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 135:176b8275d35d | 1033 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
<> | 135:176b8275d35d | 1034 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
<> | 135:176b8275d35d | 1035 | * @retval None |
<> | 135:176b8275d35d | 1036 | */ |
<> | 135:176b8275d35d | 1037 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
<> | 135:176b8275d35d | 1038 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
<> | 135:176b8275d35d | 1039 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
<> | 135:176b8275d35d | 1040 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
<> | 135:176b8275d35d | 1041 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ |
<> | 135:176b8275d35d | 1042 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ |
<> | 135:176b8275d35d | 1043 | ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) |
<> | 135:176b8275d35d | 1044 | |
<> | 135:176b8275d35d | 1045 | /** |
<> | 135:176b8275d35d | 1046 | * @brief Resets the TIM Output compare preload. |
<> | 135:176b8275d35d | 1047 | * @param __HANDLE__: TIM handle. |
<> | 135:176b8275d35d | 1048 | * @param __CHANNEL__: TIM Channels to be configured. |
<> | 135:176b8275d35d | 1049 | * This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1050 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 135:176b8275d35d | 1051 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 135:176b8275d35d | 1052 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 135:176b8275d35d | 1053 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 135:176b8275d35d | 1054 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
<> | 135:176b8275d35d | 1055 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
<> | 135:176b8275d35d | 1056 | * @retval None |
<> | 135:176b8275d35d | 1057 | */ |
<> | 135:176b8275d35d | 1058 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
<> | 135:176b8275d35d | 1059 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ |
<> | 135:176b8275d35d | 1060 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ |
<> | 135:176b8275d35d | 1061 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ |
<> | 135:176b8275d35d | 1062 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ |
<> | 135:176b8275d35d | 1063 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ |
<> | 135:176b8275d35d | 1064 | ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) |
<> | 135:176b8275d35d | 1065 | |
bogdanm | 92:4fc01daae5a5 | 1066 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 86:04dd9b1680ae | 1067 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 92:4fc01daae5a5 | 1068 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 1069 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 92:4fc01daae5a5 | 1070 | /** |
bogdanm | 92:4fc01daae5a5 | 1071 | * @} |
Kojto | 122:f9eeca106725 | 1072 | */ |
bogdanm | 86:04dd9b1680ae | 1073 | |
bogdanm | 86:04dd9b1680ae | 1074 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1075 | /** @addtogroup TIMEx_Exported_Functions |
bogdanm | 92:4fc01daae5a5 | 1076 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1077 | */ |
bogdanm | 86:04dd9b1680ae | 1078 | |
Kojto | 122:f9eeca106725 | 1079 | /** @addtogroup TIMEx_Exported_Functions_Group1 |
bogdanm | 92:4fc01daae5a5 | 1080 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1081 | */ |
bogdanm | 86:04dd9b1680ae | 1082 | /* Timer Hall Sensor functions **********************************************/ |
bogdanm | 86:04dd9b1680ae | 1083 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); |
bogdanm | 86:04dd9b1680ae | 1084 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1085 | |
bogdanm | 86:04dd9b1680ae | 1086 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1087 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1088 | |
bogdanm | 86:04dd9b1680ae | 1089 | /* Blocking mode: Polling */ |
bogdanm | 86:04dd9b1680ae | 1090 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1091 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1092 | /* Non-Blocking mode: Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1093 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1094 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1095 | /* Non-Blocking mode: DMA */ |
bogdanm | 86:04dd9b1680ae | 1096 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
bogdanm | 86:04dd9b1680ae | 1097 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
bogdanm | 92:4fc01daae5a5 | 1098 | /** |
bogdanm | 92:4fc01daae5a5 | 1099 | * @} |
bogdanm | 92:4fc01daae5a5 | 1100 | */ |
bogdanm | 86:04dd9b1680ae | 1101 | |
Kojto | 122:f9eeca106725 | 1102 | /** @addtogroup TIMEx_Exported_Functions_Group2 |
bogdanm | 92:4fc01daae5a5 | 1103 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1104 | */ |
bogdanm | 86:04dd9b1680ae | 1105 | /* Timer Complementary Output Compare functions *****************************/ |
bogdanm | 86:04dd9b1680ae | 1106 | /* Blocking mode: Polling */ |
bogdanm | 86:04dd9b1680ae | 1107 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1108 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1109 | |
bogdanm | 86:04dd9b1680ae | 1110 | /* Non-Blocking mode: Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1111 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1112 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1113 | |
bogdanm | 86:04dd9b1680ae | 1114 | /* Non-Blocking mode: DMA */ |
bogdanm | 86:04dd9b1680ae | 1115 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
bogdanm | 86:04dd9b1680ae | 1116 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 92:4fc01daae5a5 | 1117 | /** |
bogdanm | 92:4fc01daae5a5 | 1118 | * @} |
bogdanm | 92:4fc01daae5a5 | 1119 | */ |
bogdanm | 86:04dd9b1680ae | 1120 | |
Kojto | 122:f9eeca106725 | 1121 | /** @addtogroup TIMEx_Exported_Functions_Group3 |
bogdanm | 92:4fc01daae5a5 | 1122 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1123 | */ |
bogdanm | 86:04dd9b1680ae | 1124 | /* Timer Complementary PWM functions ****************************************/ |
bogdanm | 86:04dd9b1680ae | 1125 | /* Blocking mode: Polling */ |
bogdanm | 86:04dd9b1680ae | 1126 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1127 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1128 | |
bogdanm | 86:04dd9b1680ae | 1129 | /* Non-Blocking mode: Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1130 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1131 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 86:04dd9b1680ae | 1132 | /* Non-Blocking mode: DMA */ |
bogdanm | 86:04dd9b1680ae | 1133 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
bogdanm | 86:04dd9b1680ae | 1134 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
bogdanm | 92:4fc01daae5a5 | 1135 | /** |
bogdanm | 92:4fc01daae5a5 | 1136 | * @} |
bogdanm | 92:4fc01daae5a5 | 1137 | */ |
bogdanm | 86:04dd9b1680ae | 1138 | |
Kojto | 122:f9eeca106725 | 1139 | /** @addtogroup TIMEx_Exported_Functions_Group4 |
bogdanm | 92:4fc01daae5a5 | 1140 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1141 | */ |
bogdanm | 86:04dd9b1680ae | 1142 | /* Timer Complementary One Pulse functions **********************************/ |
bogdanm | 86:04dd9b1680ae | 1143 | /* Blocking mode: Polling */ |
bogdanm | 86:04dd9b1680ae | 1144 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
bogdanm | 86:04dd9b1680ae | 1145 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
bogdanm | 86:04dd9b1680ae | 1146 | |
bogdanm | 86:04dd9b1680ae | 1147 | /* Non-Blocking mode: Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1148 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
bogdanm | 86:04dd9b1680ae | 1149 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
bogdanm | 92:4fc01daae5a5 | 1150 | /** |
bogdanm | 92:4fc01daae5a5 | 1151 | * @} |
bogdanm | 92:4fc01daae5a5 | 1152 | */ |
bogdanm | 86:04dd9b1680ae | 1153 | |
Kojto | 122:f9eeca106725 | 1154 | /** @addtogroup TIMEx_Exported_Functions_Group5 |
bogdanm | 92:4fc01daae5a5 | 1155 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1156 | */ |
bogdanm | 92:4fc01daae5a5 | 1157 | /* Extended Control functions ************************************************/ |
bogdanm | 86:04dd9b1680ae | 1158 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
bogdanm | 86:04dd9b1680ae | 1159 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
bogdanm | 86:04dd9b1680ae | 1160 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
bogdanm | 86:04dd9b1680ae | 1161 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); |
bogdanm | 86:04dd9b1680ae | 1162 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
bogdanm | 86:04dd9b1680ae | 1163 | |
bogdanm | 92:4fc01daae5a5 | 1164 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
<> | 135:176b8275d35d | 1165 | defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8) |
bogdanm | 86:04dd9b1680ae | 1166 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2); |
bogdanm | 92:4fc01daae5a5 | 1167 | #endif /* STM32F303xE || STM32F398xx || */ |
bogdanm | 92:4fc01daae5a5 | 1168 | /* STM32F303xC || STM32F358xx */ |
bogdanm | 86:04dd9b1680ae | 1169 | |
bogdanm | 92:4fc01daae5a5 | 1170 | #if defined(STM32F302xE) || \ |
bogdanm | 92:4fc01daae5a5 | 1171 | defined(STM32F302xC) || \ |
<> | 135:176b8275d35d | 1172 | defined(STM32F303x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 1173 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
bogdanm | 86:04dd9b1680ae | 1174 | defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 86:04dd9b1680ae | 1175 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
bogdanm | 92:4fc01daae5a5 | 1176 | #endif /* STM32F302xE || */ |
bogdanm | 92:4fc01daae5a5 | 1177 | /* STM32F302xC || */ |
bogdanm | 86:04dd9b1680ae | 1178 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 1179 | /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
bogdanm | 92:4fc01daae5a5 | 1180 | /* STM32F373xC || STM32F378xx */ |
bogdanm | 86:04dd9b1680ae | 1181 | |
bogdanm | 92:4fc01daae5a5 | 1182 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 92:4fc01daae5a5 | 1183 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 92:4fc01daae5a5 | 1184 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 92:4fc01daae5a5 | 1185 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 86:04dd9b1680ae | 1186 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); |
bogdanm | 92:4fc01daae5a5 | 1187 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 86:04dd9b1680ae | 1188 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 92:4fc01daae5a5 | 1189 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 92:4fc01daae5a5 | 1190 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 92:4fc01daae5a5 | 1191 | /** |
bogdanm | 92:4fc01daae5a5 | 1192 | * @} |
bogdanm | 92:4fc01daae5a5 | 1193 | */ |
bogdanm | 86:04dd9b1680ae | 1194 | |
Kojto | 122:f9eeca106725 | 1195 | /** @addtogroup TIMEx_Exported_Functions_Group6 |
bogdanm | 92:4fc01daae5a5 | 1196 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1197 | */ |
bogdanm | 92:4fc01daae5a5 | 1198 | /* Extended Callback *********************************************************/ |
bogdanm | 86:04dd9b1680ae | 1199 | void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); |
bogdanm | 86:04dd9b1680ae | 1200 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
bogdanm | 92:4fc01daae5a5 | 1201 | /** |
bogdanm | 92:4fc01daae5a5 | 1202 | * @} |
bogdanm | 92:4fc01daae5a5 | 1203 | */ |
bogdanm | 86:04dd9b1680ae | 1204 | |
Kojto | 122:f9eeca106725 | 1205 | /** @addtogroup TIMEx_Exported_Functions_Group7 |
bogdanm | 92:4fc01daae5a5 | 1206 | * @{ |
bogdanm | 92:4fc01daae5a5 | 1207 | */ |
bogdanm | 92:4fc01daae5a5 | 1208 | /* Extended Peripheral State functions **************************************/ |
bogdanm | 86:04dd9b1680ae | 1209 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
bogdanm | 92:4fc01daae5a5 | 1210 | /** |
bogdanm | 92:4fc01daae5a5 | 1211 | * @} |
bogdanm | 92:4fc01daae5a5 | 1212 | */ |
bogdanm | 92:4fc01daae5a5 | 1213 | |
bogdanm | 92:4fc01daae5a5 | 1214 | /** |
bogdanm | 92:4fc01daae5a5 | 1215 | * @} |
Kojto | 122:f9eeca106725 | 1216 | */ |
Kojto | 122:f9eeca106725 | 1217 | /* End of exported functions -------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 1218 | |
Kojto | 122:f9eeca106725 | 1219 | /* Private functions----------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1220 | /** @defgroup TIMEx_Private_Functions TIMEx Private Functions |
Kojto | 122:f9eeca106725 | 1221 | * @{ |
Kojto | 122:f9eeca106725 | 1222 | */ |
Kojto | 122:f9eeca106725 | 1223 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
bogdanm | 86:04dd9b1680ae | 1224 | /** |
bogdanm | 86:04dd9b1680ae | 1225 | * @} |
Kojto | 122:f9eeca106725 | 1226 | */ |
Kojto | 122:f9eeca106725 | 1227 | /* End of private functions --------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 1228 | |
bogdanm | 86:04dd9b1680ae | 1229 | /** |
bogdanm | 86:04dd9b1680ae | 1230 | * @} |
bogdanm | 86:04dd9b1680ae | 1231 | */ |
Kojto | 122:f9eeca106725 | 1232 | |
Kojto | 122:f9eeca106725 | 1233 | /** |
Kojto | 122:f9eeca106725 | 1234 | * @} |
Kojto | 122:f9eeca106725 | 1235 | */ |
Kojto | 122:f9eeca106725 | 1236 | |
bogdanm | 86:04dd9b1680ae | 1237 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 1238 | } |
bogdanm | 86:04dd9b1680ae | 1239 | #endif |
bogdanm | 86:04dd9b1680ae | 1240 | |
bogdanm | 86:04dd9b1680ae | 1241 | |
bogdanm | 86:04dd9b1680ae | 1242 | #endif /* __STM32F3xx_HAL_TIM_EX_H */ |
bogdanm | 86:04dd9b1680ae | 1243 | |
bogdanm | 86:04dd9b1680ae | 1244 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |