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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 135:176b8275d35d

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f3xx_hal_rcc.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
bogdanm	86:04dd9b1680ae	7	* @brief Header file of RCC HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F3xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F3xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f3xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	86:04dd9b1680ae	53	/** @addtogroup RCC
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
Kojto	122:f9eeca106725	57	/** @addtogroup RCC_Private_Constants
Kojto	122:f9eeca106725	58	* @{
Kojto	122:f9eeca106725	59	*/
Kojto	122:f9eeca106725	60
Kojto	122:f9eeca106725	61	/** @defgroup RCC_Timeout RCC Timeout
Kojto	122:f9eeca106725	62	* @{
Kojto	122:f9eeca106725	63	*/
Kojto	122:f9eeca106725	64
Kojto	122:f9eeca106725	65	/* Disable Backup domain write protection state change timeout */
Kojto	123:b0220dba8be7	66	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
Kojto	122:f9eeca106725	67	/* LSE state change timeout */
Kojto	122:f9eeca106725	68	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	123:b0220dba8be7	69	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
Kojto	122:f9eeca106725	70	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<>	135:176b8275d35d	71	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
<>	135:176b8275d35d	72	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
<>	135:176b8275d35d	73	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
Kojto	122:f9eeca106725	74	/**
Kojto	122:f9eeca106725	75	* @}
Kojto	122:f9eeca106725	76	*/
Kojto	122:f9eeca106725	77
Kojto	122:f9eeca106725	78	/** @defgroup RCC_Register_Offset Register offsets
Kojto	122:f9eeca106725	79	* @{
Kojto	122:f9eeca106725	80	*/
Kojto	122:f9eeca106725	81	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	122:f9eeca106725	82	#define RCC_CR_OFFSET 0x00
Kojto	122:f9eeca106725	83	#define RCC_CFGR_OFFSET 0x04
Kojto	122:f9eeca106725	84	#define RCC_CIR_OFFSET 0x08
Kojto	122:f9eeca106725	85	#define RCC_BDCR_OFFSET 0x20
Kojto	122:f9eeca106725	86	#define RCC_CSR_OFFSET 0x24
Kojto	122:f9eeca106725	87
Kojto	122:f9eeca106725	88	/**
Kojto	122:f9eeca106725	89	* @}
Kojto	122:f9eeca106725	90	*/
Kojto	122:f9eeca106725	91
Kojto	122:f9eeca106725	92	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
Kojto	122:f9eeca106725	93	* @brief RCC registers bit address in the alias region
Kojto	122:f9eeca106725	94	* @{
Kojto	122:f9eeca106725	95	*/
Kojto	122:f9eeca106725	96	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
Kojto	122:f9eeca106725	97	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
Kojto	122:f9eeca106725	98	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
Kojto	122:f9eeca106725	99	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
Kojto	122:f9eeca106725	100	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
Kojto	122:f9eeca106725	101
Kojto	122:f9eeca106725	102	/* --- CR Register ---*/
Kojto	122:f9eeca106725	103	/* Alias word address of HSION bit */
Kojto	122:f9eeca106725	104	#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
<>	135:176b8275d35d	105	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	106	/* Alias word address of HSEON bit */
Kojto	122:f9eeca106725	107	#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
<>	135:176b8275d35d	108	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	109	/* Alias word address of CSSON bit */
Kojto	122:f9eeca106725	110	#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
<>	135:176b8275d35d	111	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	112	/* Alias word address of PLLON bit */
Kojto	122:f9eeca106725	113	#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
<>	135:176b8275d35d	114	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	115
Kojto	122:f9eeca106725	116	/* --- CSR Register ---*/
Kojto	122:f9eeca106725	117	/* Alias word address of LSION bit */
Kojto	122:f9eeca106725	118	#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
<>	135:176b8275d35d	119	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	120
Kojto	122:f9eeca106725	121	/* Alias word address of RMVF bit */
Kojto	122:f9eeca106725	122	#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
<>	135:176b8275d35d	123	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	124
Kojto	122:f9eeca106725	125	/* --- BDCR Registers ---*/
Kojto	122:f9eeca106725	126	/* Alias word address of LSEON bit */
Kojto	122:f9eeca106725	127	#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
<>	135:176b8275d35d	128	#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	129
Kojto	122:f9eeca106725	130	/* Alias word address of LSEON bit */
Kojto	122:f9eeca106725	131	#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
<>	135:176b8275d35d	132	#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	133
Kojto	122:f9eeca106725	134	/* Alias word address of RTCEN bit */
Kojto	122:f9eeca106725	135	#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
<>	135:176b8275d35d	136	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	137
Kojto	122:f9eeca106725	138	/* Alias word address of BDRST bit */
Kojto	122:f9eeca106725	139	#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
<>	135:176b8275d35d	140	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	/**
Kojto	122:f9eeca106725	143	* @}
Kojto	122:f9eeca106725	144	*/
Kojto	122:f9eeca106725	145
Kojto	122:f9eeca106725	146	/* CR register byte 2 (Bits[23:16]) base address */
<>	135:176b8275d35d	147	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
Kojto	122:f9eeca106725	148
Kojto	122:f9eeca106725	149	/* CIR register byte 1 (Bits[15:8]) base address */
<>	135:176b8275d35d	150	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
Kojto	122:f9eeca106725	151
Kojto	122:f9eeca106725	152	/* CIR register byte 2 (Bits[23:16]) base address */
<>	135:176b8275d35d	153	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
Kojto	122:f9eeca106725	154
Kojto	122:f9eeca106725	155	/* Defines used for Flags */
<>	135:176b8275d35d	156	#define CR_REG_INDEX ((uint8_t)1U)
<>	135:176b8275d35d	157	#define BDCR_REG_INDEX ((uint8_t)2U)
<>	135:176b8275d35d	158	#define CSR_REG_INDEX ((uint8_t)3U)
<>	135:176b8275d35d	159	#define CFGR_REG_INDEX ((uint8_t)4U)
Kojto	122:f9eeca106725	160
<>	135:176b8275d35d	161	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
Kojto	122:f9eeca106725	162
Kojto	122:f9eeca106725	163	/**
Kojto	122:f9eeca106725	164	* @}
Kojto	122:f9eeca106725	165	*/
Kojto	122:f9eeca106725	166
Kojto	122:f9eeca106725	167	/** @addtogroup RCC_Private_Macros
Kojto	122:f9eeca106725	168	* @{
Kojto	122:f9eeca106725	169	*/
Kojto	122:f9eeca106725	170	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	171	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	122:f9eeca106725	172	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	122:f9eeca106725	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	122:f9eeca106725	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	122:f9eeca106725	175	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	122:f9eeca106725	176	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto	122:f9eeca106725	177	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	122:f9eeca106725	178	((__HSE__) == RCC_HSE_BYPASS))
Kojto	122:f9eeca106725	179	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	122:f9eeca106725	180	((__LSE__) == RCC_LSE_BYPASS))
Kojto	122:f9eeca106725	181	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
<>	135:176b8275d35d	182	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
Kojto	122:f9eeca106725	183	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	122:f9eeca106725	184	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	122:f9eeca106725	185	((__PLL__) == RCC_PLL_ON))
Kojto	122:f9eeca106725	186	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
Kojto	122:f9eeca106725	187	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
Kojto	122:f9eeca106725	188	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
Kojto	122:f9eeca106725	189	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
Kojto	122:f9eeca106725	190	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
Kojto	122:f9eeca106725	191	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
Kojto	122:f9eeca106725	192	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
Kojto	122:f9eeca106725	193	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
Kojto	122:f9eeca106725	194	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
Kojto	122:f9eeca106725	195	#else
Kojto	122:f9eeca106725	196	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
Kojto	122:f9eeca106725	197	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
Kojto	122:f9eeca106725	198	#endif
Kojto	122:f9eeca106725	199	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
Kojto	122:f9eeca106725	200	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
Kojto	122:f9eeca106725	201	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
Kojto	122:f9eeca106725	202	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
Kojto	122:f9eeca106725	203	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
Kojto	122:f9eeca106725	204	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
Kojto	122:f9eeca106725	205	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
Kojto	122:f9eeca106725	206	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
Kojto	122:f9eeca106725	207	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
Kojto	122:f9eeca106725	208	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
Kojto	122:f9eeca106725	209
Kojto	122:f9eeca106725	210	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
Kojto	122:f9eeca106725	211	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
Kojto	122:f9eeca106725	212	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
Kojto	122:f9eeca106725	213	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
Kojto	122:f9eeca106725	214	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
Kojto	122:f9eeca106725	215	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
Kojto	122:f9eeca106725	216	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
Kojto	122:f9eeca106725	217	((__MUL__) == RCC_PLL_MUL16))
Kojto	122:f9eeca106725	218	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	219	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
Kojto	122:f9eeca106725	220	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
Kojto	122:f9eeca106725	221	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
Kojto	122:f9eeca106725	222	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	223	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	122:f9eeca106725	224	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	122:f9eeca106725	225	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	122:f9eeca106725	226	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	122:f9eeca106725	227	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto	122:f9eeca106725	228	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	122:f9eeca106725	229	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	122:f9eeca106725	230	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	122:f9eeca106725	231	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	122:f9eeca106725	232	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	122:f9eeca106725	233	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	122:f9eeca106725	234	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	122:f9eeca106725	235	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	122:f9eeca106725	236	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
Kojto	122:f9eeca106725	237	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
Kojto	122:f9eeca106725	238	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	239	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	122:f9eeca106725	240	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto	122:f9eeca106725	241	#if defined(RCC_CFGR3_USART2SW)
Kojto	122:f9eeca106725	242	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	122:f9eeca106725	243	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	244	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	245	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Kojto	122:f9eeca106725	246	#endif /* RCC_CFGR3_USART2SW */
Kojto	122:f9eeca106725	247	#if defined(RCC_CFGR3_USART3SW)
Kojto	122:f9eeca106725	248	#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	122:f9eeca106725	249	((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	250	((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	251	((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
Kojto	122:f9eeca106725	252	#endif /* RCC_CFGR3_USART3SW */
Kojto	122:f9eeca106725	253	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	254	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto	122:f9eeca106725	255
Kojto	122:f9eeca106725	256	/**
Kojto	122:f9eeca106725	257	* @}
Kojto	122:f9eeca106725	258	*/
Kojto	122:f9eeca106725	259
bogdanm	86:04dd9b1680ae	260	/* Exported types ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	261
bogdanm	92:4fc01daae5a5	262	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	92:4fc01daae5a5	263	* @{
bogdanm	86:04dd9b1680ae	264	*/
bogdanm	86:04dd9b1680ae	265
Kojto	122:f9eeca106725	266	/**
Kojto	122:f9eeca106725	267	* @brief RCC PLL configuration structure definition
Kojto	122:f9eeca106725	268	*/
Kojto	122:f9eeca106725	269	typedef struct
Kojto	122:f9eeca106725	270	{
Kojto	122:f9eeca106725	271	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	122:f9eeca106725	272	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	122:f9eeca106725	273
Kojto	122:f9eeca106725	274	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	122:f9eeca106725	275	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	122:f9eeca106725	276
Kojto	122:f9eeca106725	277	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	122:f9eeca106725	278	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	122:f9eeca106725	279
Kojto	122:f9eeca106725	280	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
Kojto	122:f9eeca106725	281	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto	122:f9eeca106725	282	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
Kojto	122:f9eeca106725	283
Kojto	122:f9eeca106725	284	#endif
Kojto	122:f9eeca106725	285	} RCC_PLLInitTypeDef;
Kojto	122:f9eeca106725	286
bogdanm	86:04dd9b1680ae	287	/**
Kojto	122:f9eeca106725	288	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	86:04dd9b1680ae	289	*/
bogdanm	86:04dd9b1680ae	290	typedef struct
bogdanm	86:04dd9b1680ae	291	{
Kojto	122:f9eeca106725	292	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	122:f9eeca106725	293	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	122:f9eeca106725	294
Kojto	122:f9eeca106725	295	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	122:f9eeca106725	296	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	122:f9eeca106725	297
Kojto	122:f9eeca106725	298	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
Kojto	122:f9eeca106725	299	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
Kojto	122:f9eeca106725	300	This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
bogdanm	86:04dd9b1680ae	301
Kojto	122:f9eeca106725	302	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
Kojto	122:f9eeca106725	303	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	122:f9eeca106725	304	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	122:f9eeca106725	305
Kojto	122:f9eeca106725	306	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	122:f9eeca106725	307	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	122:f9eeca106725	308
Kojto	122:f9eeca106725	309	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<>	135:176b8275d35d	310	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
Kojto	122:f9eeca106725	311
Kojto	122:f9eeca106725	312	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	122:f9eeca106725	313	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	86:04dd9b1680ae	314
Kojto	122:f9eeca106725	315	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	122:f9eeca106725	316
Kojto	122:f9eeca106725	317	} RCC_OscInitTypeDef;
Kojto	122:f9eeca106725	318
Kojto	122:f9eeca106725	319	/**
Kojto	122:f9eeca106725	320	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	122:f9eeca106725	321	*/
Kojto	122:f9eeca106725	322	typedef struct
Kojto	122:f9eeca106725	323	{
Kojto	122:f9eeca106725	324	uint32_t ClockType; /*!< The clock to be configured.
Kojto	122:f9eeca106725	325	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	86:04dd9b1680ae	326
Kojto	122:f9eeca106725	327	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	122:f9eeca106725	328	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	122:f9eeca106725	329
Kojto	122:f9eeca106725	330	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	122:f9eeca106725	331	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	86:04dd9b1680ae	332
Kojto	122:f9eeca106725	333	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	122:f9eeca106725	334	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	86:04dd9b1680ae	335
Kojto	122:f9eeca106725	336	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	122:f9eeca106725	337	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	122:f9eeca106725	338	} RCC_ClkInitTypeDef;
bogdanm	86:04dd9b1680ae	339
bogdanm	92:4fc01daae5a5	340	/**
bogdanm	92:4fc01daae5a5	341	* @}
bogdanm	92:4fc01daae5a5	342	*/
Kojto	122:f9eeca106725	343
bogdanm	86:04dd9b1680ae	344	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	345	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	86:04dd9b1680ae	346	* @{
bogdanm	86:04dd9b1680ae	347	*/
bogdanm	86:04dd9b1680ae	348
Kojto	122:f9eeca106725	349	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	86:04dd9b1680ae	350	* @{
bogdanm	86:04dd9b1680ae	351	*/
bogdanm	86:04dd9b1680ae	352
Kojto	122:f9eeca106725	353	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
Kojto	122:f9eeca106725	354	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /!< HSI clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	355	#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
Kojto	122:f9eeca106725	356	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
Kojto	122:f9eeca106725	357	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /!< HSI clock divided by 2 selected as PLL entry clock source /
Kojto	122:f9eeca106725	358	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
Kojto	122:f9eeca106725	359	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
bogdanm	86:04dd9b1680ae	360
bogdanm	92:4fc01daae5a5	361	/**
bogdanm	92:4fc01daae5a5	362	* @}
bogdanm	92:4fc01daae5a5	363	*/
bogdanm	92:4fc01daae5a5	364
Kojto	122:f9eeca106725	365	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	86:04dd9b1680ae	366	* @{
bogdanm	86:04dd9b1680ae	367	*/
<>	135:176b8275d35d	368	#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
<>	135:176b8275d35d	369	#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
<>	135:176b8275d35d	370	#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
<>	135:176b8275d35d	371	#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
<>	135:176b8275d35d	372	#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
Kojto	122:f9eeca106725	373	/**
Kojto	122:f9eeca106725	374	* @}
Kojto	122:f9eeca106725	375	*/
bogdanm	86:04dd9b1680ae	376
Kojto	122:f9eeca106725	377	/** @defgroup RCC_HSE_Config HSE Config
Kojto	122:f9eeca106725	378	* @{
Kojto	122:f9eeca106725	379	*/
<>	135:176b8275d35d	380	#define RCC_HSE_OFF (0x00000000U) /!< HSE clock deactivation /
Kojto	122:f9eeca106725	381	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
Kojto	122:f9eeca106725	382	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
Kojto	122:f9eeca106725	383	/**
Kojto	122:f9eeca106725	384	* @}
Kojto	122:f9eeca106725	385	*/
Kojto	122:f9eeca106725	386
Kojto	122:f9eeca106725	387	/** @defgroup RCC_LSE_Config LSE Config
Kojto	122:f9eeca106725	388	* @{
Kojto	122:f9eeca106725	389	*/
<>	135:176b8275d35d	390	#define RCC_LSE_OFF (0x00000000U) /!< LSE clock deactivation /
Kojto	122:f9eeca106725	391	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
Kojto	122:f9eeca106725	392	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
Kojto	122:f9eeca106725	393
bogdanm	86:04dd9b1680ae	394	/**
bogdanm	86:04dd9b1680ae	395	* @}
bogdanm	86:04dd9b1680ae	396	*/
bogdanm	86:04dd9b1680ae	397
Kojto	122:f9eeca106725	398	/** @defgroup RCC_HSI_Config HSI Config
Kojto	122:f9eeca106725	399	* @{
Kojto	122:f9eeca106725	400	*/
<>	135:176b8275d35d	401	#define RCC_HSI_OFF (0x00000000U) /!< HSI clock deactivation /
Kojto	122:f9eeca106725	402	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
Kojto	122:f9eeca106725	403
<>	135:176b8275d35d	404	#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
Kojto	122:f9eeca106725	405
Kojto	122:f9eeca106725	406	/**
Kojto	122:f9eeca106725	407	* @}
Kojto	122:f9eeca106725	408	*/
Kojto	122:f9eeca106725	409
Kojto	122:f9eeca106725	410	/** @defgroup RCC_LSI_Config LSI Config
bogdanm	86:04dd9b1680ae	411	* @{
bogdanm	86:04dd9b1680ae	412	*/
<>	135:176b8275d35d	413	#define RCC_LSI_OFF (0x00000000U) /!< LSI clock deactivation /
Kojto	122:f9eeca106725	414	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
Kojto	122:f9eeca106725	415
Kojto	122:f9eeca106725	416	/**
Kojto	122:f9eeca106725	417	* @}
Kojto	122:f9eeca106725	418	*/
bogdanm	86:04dd9b1680ae	419
Kojto	122:f9eeca106725	420	/** @defgroup RCC_PLL_Config PLL Config
Kojto	122:f9eeca106725	421	* @{
Kojto	122:f9eeca106725	422	*/
<>	135:176b8275d35d	423	#define RCC_PLL_NONE (0x00000000U) /!< PLL is not configured /
<>	135:176b8275d35d	424	#define RCC_PLL_OFF (0x00000001U) /!< PLL deactivation /
<>	135:176b8275d35d	425	#define RCC_PLL_ON (0x00000002U) /!< PLL activation /
Kojto	122:f9eeca106725	426
bogdanm	86:04dd9b1680ae	427	/**
bogdanm	86:04dd9b1680ae	428	* @}
bogdanm	86:04dd9b1680ae	429	*/
bogdanm	86:04dd9b1680ae	430
Kojto	122:f9eeca106725	431	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	122:f9eeca106725	432	* @{
Kojto	122:f9eeca106725	433	*/
<>	135:176b8275d35d	434	#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /!< SYSCLK to configure /
<>	135:176b8275d35d	435	#define RCC_CLOCKTYPE_HCLK (0x00000002U) /!< HCLK to configure /
<>	135:176b8275d35d	436	#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /!< PCLK1 to configure /
<>	135:176b8275d35d	437	#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /!< PCLK2 to configure /
Kojto	122:f9eeca106725	438
Kojto	122:f9eeca106725	439	/**
Kojto	122:f9eeca106725	440	* @}
Kojto	122:f9eeca106725	441	*/
Kojto	122:f9eeca106725	442
Kojto	122:f9eeca106725	443	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	86:04dd9b1680ae	444	* @{
bogdanm	86:04dd9b1680ae	445	*/
Kojto	122:f9eeca106725	446	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
Kojto	122:f9eeca106725	447	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
Kojto	122:f9eeca106725	448	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
Kojto	122:f9eeca106725	449
Kojto	122:f9eeca106725	450	/**
Kojto	122:f9eeca106725	451	* @}
Kojto	122:f9eeca106725	452	*/
bogdanm	86:04dd9b1680ae	453
Kojto	122:f9eeca106725	454	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	122:f9eeca106725	455	* @{
Kojto	122:f9eeca106725	456	*/
Kojto	122:f9eeca106725	457	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	122:f9eeca106725	458	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	122:f9eeca106725	459	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	122:f9eeca106725	460
bogdanm	86:04dd9b1680ae	461	/**
bogdanm	86:04dd9b1680ae	462	* @}
bogdanm	86:04dd9b1680ae	463	*/
bogdanm	86:04dd9b1680ae	464
Kojto	122:f9eeca106725	465	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm	86:04dd9b1680ae	466	* @{
bogdanm	86:04dd9b1680ae	467	*/
Kojto	122:f9eeca106725	468	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
Kojto	122:f9eeca106725	469	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
Kojto	122:f9eeca106725	470	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
Kojto	122:f9eeca106725	471	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
Kojto	122:f9eeca106725	472	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
Kojto	122:f9eeca106725	473	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
Kojto	122:f9eeca106725	474	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
Kojto	122:f9eeca106725	475	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
Kojto	122:f9eeca106725	476	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
bogdanm	86:04dd9b1680ae	477
Kojto	122:f9eeca106725	478	/**
Kojto	122:f9eeca106725	479	* @}
Kojto	122:f9eeca106725	480	*/
Kojto	122:f9eeca106725	481
Kojto	122:f9eeca106725	482	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
Kojto	122:f9eeca106725	483	* @{
Kojto	122:f9eeca106725	484	*/
Kojto	122:f9eeca106725	485	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
Kojto	122:f9eeca106725	486	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	487	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	488	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	489	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
bogdanm	92:4fc01daae5a5	490
bogdanm	86:04dd9b1680ae	491	/**
bogdanm	86:04dd9b1680ae	492	* @}
bogdanm	86:04dd9b1680ae	493	*/
bogdanm	86:04dd9b1680ae	494
Kojto	122:f9eeca106725	495	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm	86:04dd9b1680ae	496	* @{
bogdanm	86:04dd9b1680ae	497	*/
Kojto	122:f9eeca106725	498	#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /!< No clock /
Kojto	122:f9eeca106725	499	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	500	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	501	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /!< HSE oscillator clock divided by 32 used as RTC clock /
bogdanm	86:04dd9b1680ae	502	/**
bogdanm	86:04dd9b1680ae	503	* @}
bogdanm	86:04dd9b1680ae	504	*/
bogdanm	86:04dd9b1680ae	505
bogdanm	92:4fc01daae5a5	506	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm	86:04dd9b1680ae	507	* @{
bogdanm	86:04dd9b1680ae	508	*/
bogdanm	86:04dd9b1680ae	509	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm	86:04dd9b1680ae	510	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm	86:04dd9b1680ae	511	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm	86:04dd9b1680ae	512	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm	86:04dd9b1680ae	513	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm	86:04dd9b1680ae	514	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm	86:04dd9b1680ae	515	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm	86:04dd9b1680ae	516	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm	86:04dd9b1680ae	517	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm	86:04dd9b1680ae	518	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm	86:04dd9b1680ae	519	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm	86:04dd9b1680ae	520	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm	86:04dd9b1680ae	521	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm	86:04dd9b1680ae	522	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm	86:04dd9b1680ae	523	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm	86:04dd9b1680ae	524
bogdanm	86:04dd9b1680ae	525	/**
bogdanm	86:04dd9b1680ae	526	* @}
bogdanm	86:04dd9b1680ae	527	*/
bogdanm	86:04dd9b1680ae	528
Kojto	122:f9eeca106725	529	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
Kojto	122:f9eeca106725	530	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
bogdanm	86:04dd9b1680ae	531	* @{
bogdanm	86:04dd9b1680ae	532	*/
bogdanm	86:04dd9b1680ae	533
Kojto	122:f9eeca106725	534	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	122:f9eeca106725	535	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	122:f9eeca106725	536	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	122:f9eeca106725	537	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	122:f9eeca106725	538	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	122:f9eeca106725	539	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	122:f9eeca106725	540	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	122:f9eeca106725	541	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	122:f9eeca106725	542	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	122:f9eeca106725	543	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	122:f9eeca106725	544	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	122:f9eeca106725	545	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	122:f9eeca106725	546	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	122:f9eeca106725	547	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	122:f9eeca106725	548	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	122:f9eeca106725	549	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	122:f9eeca106725	550
bogdanm	86:04dd9b1680ae	551	/**
bogdanm	86:04dd9b1680ae	552	* @}
bogdanm	86:04dd9b1680ae	553	*/
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	#endif
Kojto	122:f9eeca106725	556	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
Kojto	122:f9eeca106725	557	/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
bogdanm	86:04dd9b1680ae	558	* @{
bogdanm	86:04dd9b1680ae	559	*/
bogdanm	86:04dd9b1680ae	560
Kojto	122:f9eeca106725	561	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	122:f9eeca106725	562	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	122:f9eeca106725	563	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	122:f9eeca106725	564	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	122:f9eeca106725	565	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	122:f9eeca106725	566	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	122:f9eeca106725	567	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	122:f9eeca106725	568	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	122:f9eeca106725	569	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	122:f9eeca106725	570	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	122:f9eeca106725	571	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	122:f9eeca106725	572	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	122:f9eeca106725	573	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	122:f9eeca106725	574	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	122:f9eeca106725	575	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	122:f9eeca106725	576	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	122:f9eeca106725	577
bogdanm	86:04dd9b1680ae	578	/**
bogdanm	86:04dd9b1680ae	579	* @}
bogdanm	86:04dd9b1680ae	580	*/
Kojto	122:f9eeca106725	581	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
bogdanm	86:04dd9b1680ae	582
Kojto	122:f9eeca106725	583	#if defined(RCC_CFGR3_USART2SW)
bogdanm	92:4fc01daae5a5	584	/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
bogdanm	86:04dd9b1680ae	585	* @{
bogdanm	86:04dd9b1680ae	586	*/
bogdanm	86:04dd9b1680ae	587	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	86:04dd9b1680ae	588	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	86:04dd9b1680ae	589	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	86:04dd9b1680ae	590	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	86:04dd9b1680ae	591
bogdanm	86:04dd9b1680ae	592	/**
bogdanm	86:04dd9b1680ae	593	* @}
bogdanm	86:04dd9b1680ae	594	*/
Kojto	122:f9eeca106725	595	#endif /* RCC_CFGR3_USART2SW */
bogdanm	86:04dd9b1680ae	596
Kojto	122:f9eeca106725	597	#if defined(RCC_CFGR3_USART3SW)
bogdanm	92:4fc01daae5a5	598	/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
bogdanm	86:04dd9b1680ae	599	* @{
bogdanm	86:04dd9b1680ae	600	*/
bogdanm	86:04dd9b1680ae	601	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	86:04dd9b1680ae	602	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	86:04dd9b1680ae	603	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	86:04dd9b1680ae	604	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	86:04dd9b1680ae	605
bogdanm	86:04dd9b1680ae	606	/**
bogdanm	86:04dd9b1680ae	607	* @}
bogdanm	86:04dd9b1680ae	608	*/
Kojto	122:f9eeca106725	609	#endif /* RCC_CFGR3_USART3SW */
bogdanm	86:04dd9b1680ae	610
bogdanm	92:4fc01daae5a5	611	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm	86:04dd9b1680ae	612	* @{
bogdanm	86:04dd9b1680ae	613	*/
bogdanm	86:04dd9b1680ae	614	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm	86:04dd9b1680ae	615	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm	86:04dd9b1680ae	616
bogdanm	86:04dd9b1680ae	617	/**
bogdanm	86:04dd9b1680ae	618	* @}
bogdanm	86:04dd9b1680ae	619	*/
Kojto	122:f9eeca106725	620	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	86:04dd9b1680ae	621	* @{
bogdanm	86:04dd9b1680ae	622	*/
<>	135:176b8275d35d	623	#define RCC_MCO1 (0x00000000U)
Kojto	122:f9eeca106725	624	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	86:04dd9b1680ae	625
bogdanm	86:04dd9b1680ae	626	/**
bogdanm	86:04dd9b1680ae	627	* @}
bogdanm	86:04dd9b1680ae	628	*/
bogdanm	86:04dd9b1680ae	629
Kojto	122:f9eeca106725	630	/** @defgroup RCC_Interrupt Interrupts
bogdanm	86:04dd9b1680ae	631	* @{
bogdanm	86:04dd9b1680ae	632	*/
Kojto	122:f9eeca106725	633	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
Kojto	122:f9eeca106725	634	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
Kojto	122:f9eeca106725	635	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
Kojto	122:f9eeca106725	636	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
Kojto	122:f9eeca106725	637	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
Kojto	122:f9eeca106725	638	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
bogdanm	86:04dd9b1680ae	639	/**
bogdanm	86:04dd9b1680ae	640	* @}
Kojto	122:f9eeca106725	641	*/
bogdanm	86:04dd9b1680ae	642
Kojto	122:f9eeca106725	643	/** @defgroup RCC_Flag Flags
Kojto	122:f9eeca106725	644	* Elements values convention: XXXYYYYYb
bogdanm	86:04dd9b1680ae	645	* - YYYYY : Flag position in the register
Kojto	122:f9eeca106725	646	* - XXX : Register index
Kojto	122:f9eeca106725	647	* - 001: CR register
Kojto	122:f9eeca106725	648	* - 010: BDCR register
Kojto	122:f9eeca106725	649	* - 011: CSR register
Kojto	122:f9eeca106725	650	* - 100: CFGR register
bogdanm	86:04dd9b1680ae	651	* @{
bogdanm	86:04dd9b1680ae	652	*/
Kojto	122:f9eeca106725	653	/* Flags in the CR register */
<>	135:176b8275d35d	654	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
<>	135:176b8275d35d	655	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
<>	135:176b8275d35d	656	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
bogdanm	86:04dd9b1680ae	657
Kojto	122:f9eeca106725	658	/* Flags in the CSR register */
<>	135:176b8275d35d	659	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
Kojto	122:f9eeca106725	660	#if defined(RCC_CSR_V18PWRRSTF)
<>	135:176b8275d35d	661	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_V18PWRRSTF)))
Kojto	122:f9eeca106725	662	#endif
<>	135:176b8275d35d	663	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Options bytes loading reset flag /
<>	135:176b8275d35d	664	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
<>	135:176b8275d35d	665	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
<>	135:176b8275d35d	666	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
<>	135:176b8275d35d	667	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
<>	135:176b8275d35d	668	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
<>	135:176b8275d35d	669	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
bogdanm	86:04dd9b1680ae	670
bogdanm	86:04dd9b1680ae	671	/* Flags in the BDCR register */
<>	135:176b8275d35d	672	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
bogdanm	86:04dd9b1680ae	673
Kojto	122:f9eeca106725	674	/* Flags in the CFGR register */
Kojto	122:f9eeca106725	675	#if defined(RCC_CFGR_MCOF)
<>	135:176b8275d35d	676	#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CFGR_MCOF))) /!< Microcontroller Clock Output Flag /
Kojto	122:f9eeca106725	677	#endif /* RCC_CFGR_MCOF */
Kojto	122:f9eeca106725	678
bogdanm	86:04dd9b1680ae	679	/**
bogdanm	86:04dd9b1680ae	680	* @}
bogdanm	86:04dd9b1680ae	681	*/
bogdanm	86:04dd9b1680ae	682
bogdanm	86:04dd9b1680ae	683	/**
bogdanm	86:04dd9b1680ae	684	* @}
bogdanm	86:04dd9b1680ae	685	*/
Kojto	122:f9eeca106725	686
bogdanm	86:04dd9b1680ae	687	/* Exported macro ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	688
bogdanm	92:4fc01daae5a5	689	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	122:f9eeca106725	690	* @{
Kojto	122:f9eeca106725	691	*/
bogdanm	92:4fc01daae5a5	692
bogdanm	92:4fc01daae5a5	693	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm	92:4fc01daae5a5	694	* @brief Enable or disable the AHB peripheral clock.
bogdanm	86:04dd9b1680ae	695	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	696	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	697	* using it.
bogdanm	92:4fc01daae5a5	698	* @{
bogdanm	86:04dd9b1680ae	699	*/
Kojto	122:f9eeca106725	700	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	701	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	702	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto	122:f9eeca106725	703	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	704	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto	122:f9eeca106725	705	UNUSED(tmpreg); \
<>	135:176b8275d35d	706	} while(0U)
Kojto	122:f9eeca106725	707	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	708	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	709	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto	122:f9eeca106725	710	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	711	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto	122:f9eeca106725	712	UNUSED(tmpreg); \
<>	135:176b8275d35d	713	} while(0U)
Kojto	122:f9eeca106725	714	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	715	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	716	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto	122:f9eeca106725	717	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	718	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto	122:f9eeca106725	719	UNUSED(tmpreg); \
<>	135:176b8275d35d	720	} while(0U)
Kojto	122:f9eeca106725	721	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	722	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	723	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	122:f9eeca106725	724	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	725	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	122:f9eeca106725	726	UNUSED(tmpreg); \
<>	135:176b8275d35d	727	} while(0U)
Kojto	122:f9eeca106725	728	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	729	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	730	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto	122:f9eeca106725	731	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	732	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto	122:f9eeca106725	733	UNUSED(tmpreg); \
<>	135:176b8275d35d	734	} while(0U)
Kojto	122:f9eeca106725	735	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	736	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	737	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	122:f9eeca106725	738	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	739	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	122:f9eeca106725	740	UNUSED(tmpreg); \
<>	135:176b8275d35d	741	} while(0U)
Kojto	122:f9eeca106725	742	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	743	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	744	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	122:f9eeca106725	745	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	746	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	122:f9eeca106725	747	UNUSED(tmpreg); \
<>	135:176b8275d35d	748	} while(0U)
Kojto	122:f9eeca106725	749	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	750	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	751	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	122:f9eeca106725	752	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	753	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	122:f9eeca106725	754	UNUSED(tmpreg); \
<>	135:176b8275d35d	755	} while(0U)
Kojto	122:f9eeca106725	756	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	757	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	758	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	122:f9eeca106725	759	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	760	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	122:f9eeca106725	761	UNUSED(tmpreg); \
<>	135:176b8275d35d	762	} while(0U)
Kojto	122:f9eeca106725	763	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	764	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	765	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	122:f9eeca106725	766	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	767	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	122:f9eeca106725	768	UNUSED(tmpreg); \
<>	135:176b8275d35d	769	} while(0U)
bogdanm	86:04dd9b1680ae	770
Kojto	122:f9eeca106725	771	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	122:f9eeca106725	772	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	122:f9eeca106725	773	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	122:f9eeca106725	774	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	122:f9eeca106725	775	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto	122:f9eeca106725	776	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	122:f9eeca106725	777	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	122:f9eeca106725	778	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto	122:f9eeca106725	779	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	122:f9eeca106725	780	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	92:4fc01daae5a5	781	/**
bogdanm	92:4fc01daae5a5	782	* @}
bogdanm	92:4fc01daae5a5	783	*/
bogdanm	86:04dd9b1680ae	784
bogdanm	92:4fc01daae5a5	785	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm	92:4fc01daae5a5	786	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	86:04dd9b1680ae	787	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	788	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	789	* using it.
bogdanm	92:4fc01daae5a5	790	* @{
bogdanm	86:04dd9b1680ae	791	*/
Kojto	122:f9eeca106725	792	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	793	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	794	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	795	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	796	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	797	UNUSED(tmpreg); \
<>	135:176b8275d35d	798	} while(0U)
Kojto	122:f9eeca106725	799	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	800	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	801	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	802	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	803	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	804	UNUSED(tmpreg); \
<>	135:176b8275d35d	805	} while(0U)
Kojto	122:f9eeca106725	806	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	807	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	122:f9eeca106725	809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	122:f9eeca106725	811	UNUSED(tmpreg); \
<>	135:176b8275d35d	812	} while(0U)
Kojto	122:f9eeca106725	813	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	814	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	815	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	122:f9eeca106725	816	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	817	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	122:f9eeca106725	818	UNUSED(tmpreg); \
<>	135:176b8275d35d	819	} while(0U)
Kojto	122:f9eeca106725	820	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	821	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	822	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	823	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	824	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	825	UNUSED(tmpreg); \
<>	135:176b8275d35d	826	} while(0U)
Kojto	122:f9eeca106725	827	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	828	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	829	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	122:f9eeca106725	830	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	831	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	122:f9eeca106725	832	UNUSED(tmpreg); \
<>	135:176b8275d35d	833	} while(0U)
Kojto	122:f9eeca106725	834	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	835	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	836	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	122:f9eeca106725	837	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	838	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	122:f9eeca106725	839	UNUSED(tmpreg); \
<>	135:176b8275d35d	840	} while(0U)
Kojto	122:f9eeca106725	841	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	842	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	843	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
Kojto	122:f9eeca106725	844	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	845	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
Kojto	122:f9eeca106725	846	UNUSED(tmpreg); \
<>	135:176b8275d35d	847	} while(0U)
bogdanm	86:04dd9b1680ae	848
Kojto	122:f9eeca106725	849	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	122:f9eeca106725	850	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	122:f9eeca106725	851	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	122:f9eeca106725	852	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	122:f9eeca106725	853	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	122:f9eeca106725	854	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	122:f9eeca106725	855	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	122:f9eeca106725	856	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
bogdanm	92:4fc01daae5a5	857	/**
bogdanm	92:4fc01daae5a5	858	* @}
bogdanm	92:4fc01daae5a5	859	*/
bogdanm	92:4fc01daae5a5	860
bogdanm	92:4fc01daae5a5	861	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm	92:4fc01daae5a5	862	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	86:04dd9b1680ae	863	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	864	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	865	* using it.
bogdanm	92:4fc01daae5a5	866	* @{
bogdanm	86:04dd9b1680ae	867	*/
Kojto	122:f9eeca106725	868	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	869	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	870	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	122:f9eeca106725	871	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	872	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	122:f9eeca106725	873	UNUSED(tmpreg); \
<>	135:176b8275d35d	874	} while(0U)
Kojto	122:f9eeca106725	875	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	876	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	877	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	122:f9eeca106725	878	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	879	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	122:f9eeca106725	880	UNUSED(tmpreg); \
<>	135:176b8275d35d	881	} while(0U)
Kojto	122:f9eeca106725	882	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	883	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	884	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto	122:f9eeca106725	885	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	886	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto	122:f9eeca106725	887	UNUSED(tmpreg); \
<>	135:176b8275d35d	888	} while(0U)
Kojto	122:f9eeca106725	889	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	890	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	891	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto	122:f9eeca106725	892	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	893	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto	122:f9eeca106725	894	UNUSED(tmpreg); \
<>	135:176b8275d35d	895	} while(0U)
Kojto	122:f9eeca106725	896	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	897	__IO uint32_t tmpreg; \
Kojto	122:f9eeca106725	898	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	122:f9eeca106725	899	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	900	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	122:f9eeca106725	901	UNUSED(tmpreg); \
<>	135:176b8275d35d	902	} while(0U)
Kojto	122:f9eeca106725	903
Kojto	122:f9eeca106725	904	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	122:f9eeca106725	905	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto	122:f9eeca106725	906	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto	122:f9eeca106725	907	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto	122:f9eeca106725	908	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	122:f9eeca106725	909	/**
Kojto	122:f9eeca106725	910	* @}
Kojto	122:f9eeca106725	911	*/
bogdanm	86:04dd9b1680ae	912
Kojto	122:f9eeca106725	913	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	914	* @brief Get the enable or disable status of the AHB peripheral clock.
Kojto	122:f9eeca106725	915	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	916	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	917	* using it.
Kojto	122:f9eeca106725	918	* @{
Kojto	122:f9eeca106725	919	*/
Kojto	122:f9eeca106725	920	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
Kojto	122:f9eeca106725	921	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
Kojto	122:f9eeca106725	922	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
Kojto	122:f9eeca106725	923	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	924	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	925	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	926	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
Kojto	122:f9eeca106725	927	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
Kojto	122:f9eeca106725	928	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
Kojto	122:f9eeca106725	929	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
Kojto	122:f9eeca106725	930
Kojto	122:f9eeca106725	931	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
Kojto	122:f9eeca106725	932	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
Kojto	122:f9eeca106725	933	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
Kojto	122:f9eeca106725	934	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	935	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	936	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	937	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Kojto	122:f9eeca106725	938	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
Kojto	122:f9eeca106725	939	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
Kojto	122:f9eeca106725	940	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Kojto	122:f9eeca106725	941	/**
Kojto	122:f9eeca106725	942	* @}
Kojto	122:f9eeca106725	943	*/
Kojto	122:f9eeca106725	944
Kojto	122:f9eeca106725	945	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	946	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	947	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	948	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	949	* using it.
Kojto	122:f9eeca106725	950	* @{
Kojto	122:f9eeca106725	951	*/
Kojto	122:f9eeca106725	952	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	953	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	954	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto	122:f9eeca106725	955	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	122:f9eeca106725	956	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	957	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto	122:f9eeca106725	958	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto	122:f9eeca106725	959	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
Kojto	122:f9eeca106725	960
Kojto	122:f9eeca106725	961	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	962	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	963	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto	122:f9eeca106725	964	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	122:f9eeca106725	965	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	966	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto	122:f9eeca106725	967	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto	122:f9eeca106725	968	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
Kojto	122:f9eeca106725	969	/**
Kojto	122:f9eeca106725	970	* @}
Kojto	122:f9eeca106725	971	*/
Kojto	122:f9eeca106725	972
Kojto	122:f9eeca106725	973	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	974	* @brief EGet the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	975	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	976	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	977	* using it.
Kojto	122:f9eeca106725	978	* @{
Kojto	122:f9eeca106725	979	*/
Kojto	122:f9eeca106725	980	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto	122:f9eeca106725	981	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
Kojto	122:f9eeca106725	982	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
Kojto	122:f9eeca106725	983	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
Kojto	122:f9eeca106725	984	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto	122:f9eeca106725	985
Kojto	122:f9eeca106725	986	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto	122:f9eeca106725	987	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
Kojto	122:f9eeca106725	988	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
Kojto	122:f9eeca106725	989	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
Kojto	122:f9eeca106725	990	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
bogdanm	92:4fc01daae5a5	991	/**
bogdanm	92:4fc01daae5a5	992	* @}
bogdanm	92:4fc01daae5a5	993	*/
bogdanm	86:04dd9b1680ae	994
bogdanm	92:4fc01daae5a5	995	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm	92:4fc01daae5a5	996	* @brief Force or release AHB peripheral reset.
bogdanm	92:4fc01daae5a5	997	* @{
bogdanm	86:04dd9b1680ae	998	*/
Kojto	122:f9eeca106725	999	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	1000	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	122:f9eeca106725	1001	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	122:f9eeca106725	1002	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	122:f9eeca106725	1003	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	122:f9eeca106725	1004	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
Kojto	122:f9eeca106725	1005	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	86:04dd9b1680ae	1006
Kojto	123:b0220dba8be7	1007	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
Kojto	122:f9eeca106725	1008	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	122:f9eeca106725	1009	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	122:f9eeca106725	1010	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	122:f9eeca106725	1011	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	122:f9eeca106725	1012	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto	122:f9eeca106725	1013	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	92:4fc01daae5a5	1014	/**
bogdanm	92:4fc01daae5a5	1015	* @}
bogdanm	92:4fc01daae5a5	1016	*/
bogdanm	86:04dd9b1680ae	1017
bogdanm	92:4fc01daae5a5	1018	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm	92:4fc01daae5a5	1019	* @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	1020	* @{
bogdanm	86:04dd9b1680ae	1021	*/
Kojto	122:f9eeca106725	1022	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	1023	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	122:f9eeca106725	1024	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	122:f9eeca106725	1025	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	122:f9eeca106725	1026	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	122:f9eeca106725	1027	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	122:f9eeca106725	1028	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	122:f9eeca106725	1029	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	122:f9eeca106725	1030	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC1RST))
bogdanm	86:04dd9b1680ae	1031
Kojto	123:b0220dba8be7	1032	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
Kojto	122:f9eeca106725	1033	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	122:f9eeca106725	1034	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	122:f9eeca106725	1035	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	122:f9eeca106725	1036	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	122:f9eeca106725	1037	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	122:f9eeca106725	1038	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	122:f9eeca106725	1039	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	122:f9eeca106725	1040	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
bogdanm	92:4fc01daae5a5	1041	/**
bogdanm	92:4fc01daae5a5	1042	* @}
bogdanm	92:4fc01daae5a5	1043	*/
bogdanm	86:04dd9b1680ae	1044
bogdanm	92:4fc01daae5a5	1045	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm	92:4fc01daae5a5	1046	* @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	1047	* @{
bogdanm	86:04dd9b1680ae	1048	*/
Kojto	122:f9eeca106725	1049	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	1050	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	122:f9eeca106725	1051	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
Kojto	122:f9eeca106725	1052	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
Kojto	122:f9eeca106725	1053	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
Kojto	122:f9eeca106725	1054	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	86:04dd9b1680ae	1055
Kojto	123:b0220dba8be7	1056	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
Kojto	122:f9eeca106725	1057	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	122:f9eeca106725	1058	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto	122:f9eeca106725	1059	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto	122:f9eeca106725	1060	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto	122:f9eeca106725	1061	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	92:4fc01daae5a5	1062	/**
bogdanm	92:4fc01daae5a5	1063	* @}
bogdanm	92:4fc01daae5a5	1064	*/
bogdanm	92:4fc01daae5a5	1065
Kojto	122:f9eeca106725	1066	/** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm	92:4fc01daae5a5	1067	* @{
Kojto	122:f9eeca106725	1068	*/
bogdanm	86:04dd9b1680ae	1069
bogdanm	86:04dd9b1680ae	1070	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	86:04dd9b1680ae	1071	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	1072	* It is used (enabled by hardware) as system clock source after startup
bogdanm	86:04dd9b1680ae	1073	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	86:04dd9b1680ae	1074	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	86:04dd9b1680ae	1075	* Security System CSS is enabled).
bogdanm	86:04dd9b1680ae	1076	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	122:f9eeca106725	1077	* you have to select another source of the system clock then stop the HSI.
bogdanm	86:04dd9b1680ae	1078	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	86:04dd9b1680ae	1079	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	122:f9eeca106725	1080	* system clock source.
bogdanm	86:04dd9b1680ae	1081	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	122:f9eeca106725	1082	* clock cycles.
bogdanm	86:04dd9b1680ae	1083	*/
Kojto	122:f9eeca106725	1084	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
Kojto	122:f9eeca106725	1085	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
bogdanm	86:04dd9b1680ae	1086
bogdanm	86:04dd9b1680ae	1087	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	86:04dd9b1680ae	1088	* @note The calibration is used to compensate for the variations in voltage
bogdanm	86:04dd9b1680ae	1089	* and temperature that influence the frequency of the internal HSI RC.
Kojto	122:f9eeca106725	1090	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
Kojto	122:f9eeca106725	1091	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	86:04dd9b1680ae	1092	* This parameter must be a number between 0 and 0x1F.
Kojto	122:f9eeca106725	1093	*/
Kojto	122:f9eeca106725	1094	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto	122:f9eeca106725	1095	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto	122:f9eeca106725	1096
bogdanm	92:4fc01daae5a5	1097	/**
bogdanm	92:4fc01daae5a5	1098	* @}
bogdanm	92:4fc01daae5a5	1099	*/
bogdanm	86:04dd9b1680ae	1100
Kojto	122:f9eeca106725	1101	/** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm	92:4fc01daae5a5	1102	* @{
Kojto	122:f9eeca106725	1103	*/
bogdanm	86:04dd9b1680ae	1104
Kojto	122:f9eeca106725	1105	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
Kojto	122:f9eeca106725	1106	* @note After enabling the LSI, the application software should wait on
bogdanm	86:04dd9b1680ae	1107	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	86:04dd9b1680ae	1108	* be used to clock the IWDG and/or the RTC.
Kojto	122:f9eeca106725	1109	*/
Kojto	122:f9eeca106725	1110	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
Kojto	122:f9eeca106725	1111
Kojto	122:f9eeca106725	1112	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
Kojto	122:f9eeca106725	1113	* @note LSI can not be disabled if the IWDG is running.
bogdanm	86:04dd9b1680ae	1114	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	122:f9eeca106725	1115	* clock cycles.
bogdanm	86:04dd9b1680ae	1116	*/
Kojto	122:f9eeca106725	1117	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
Kojto	122:f9eeca106725	1118
bogdanm	92:4fc01daae5a5	1119	/**
bogdanm	92:4fc01daae5a5	1120	* @}
bogdanm	92:4fc01daae5a5	1121	*/
bogdanm	92:4fc01daae5a5	1122
Kojto	122:f9eeca106725	1123	/** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm	92:4fc01daae5a5	1124	* @{
Kojto	122:f9eeca106725	1125	*/
bogdanm	86:04dd9b1680ae	1126
bogdanm	86:04dd9b1680ae	1127	/**
bogdanm	86:04dd9b1680ae	1128	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	122:f9eeca106725	1129	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto	122:f9eeca106725	1130	* supported by this macro. User should request a transition to HSE Off
Kojto	122:f9eeca106725	1131	* first and then HSE On or HSE Bypass.
bogdanm	86:04dd9b1680ae	1132	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	86:04dd9b1680ae	1133	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	86:04dd9b1680ae	1134	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	86:04dd9b1680ae	1135	* @note HSE state can not be changed if it is used directly or through the
bogdanm	86:04dd9b1680ae	1136	* PLL as system clock. In this case, you have to select another source
bogdanm	86:04dd9b1680ae	1137	* of the system clock then change the HSE state (ex. disable it).
bogdanm	86:04dd9b1680ae	1138	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	122:f9eeca106725	1139	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	86:04dd9b1680ae	1140	* was previously enabled you have to enable it again after calling this
bogdanm	86:04dd9b1680ae	1141	* function.
Kojto	122:f9eeca106725	1142	* @param __STATE__ specifies the new state of the HSE.
bogdanm	86:04dd9b1680ae	1143	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1144	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	86:04dd9b1680ae	1145	* 6 HSE oscillator clock cycles.
Kojto	122:f9eeca106725	1146	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
Kojto	122:f9eeca106725	1147	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
bogdanm	86:04dd9b1680ae	1148	*/
Kojto	122:f9eeca106725	1149	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	122:f9eeca106725	1150	do{ \
Kojto	122:f9eeca106725	1151	if ((__STATE__) == RCC_HSE_ON) \
Kojto	122:f9eeca106725	1152	{ \
Kojto	122:f9eeca106725	1153	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	122:f9eeca106725	1154	} \
Kojto	122:f9eeca106725	1155	else if ((__STATE__) == RCC_HSE_OFF) \
Kojto	122:f9eeca106725	1156	{ \
Kojto	122:f9eeca106725	1157	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	122:f9eeca106725	1158	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	122:f9eeca106725	1159	} \
Kojto	122:f9eeca106725	1160	else if ((__STATE__) == RCC_HSE_BYPASS) \
Kojto	122:f9eeca106725	1161	{ \
Kojto	122:f9eeca106725	1162	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	122:f9eeca106725	1163	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	122:f9eeca106725	1164	} \
Kojto	122:f9eeca106725	1165	else \
Kojto	122:f9eeca106725	1166	{ \
Kojto	122:f9eeca106725	1167	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	122:f9eeca106725	1168	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	122:f9eeca106725	1169	} \
<>	135:176b8275d35d	1170	}while(0U)
bogdanm	86:04dd9b1680ae	1171
bogdanm	92:4fc01daae5a5	1172	/**
bogdanm	92:4fc01daae5a5	1173	* @}
bogdanm	92:4fc01daae5a5	1174	*/
bogdanm	86:04dd9b1680ae	1175
Kojto	122:f9eeca106725	1176	/** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm	92:4fc01daae5a5	1177	* @{
Kojto	122:f9eeca106725	1178	*/
Kojto	122:f9eeca106725	1179
Kojto	122:f9eeca106725	1180	/**
Kojto	122:f9eeca106725	1181	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	122:f9eeca106725	1182	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto	122:f9eeca106725	1183	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	122:f9eeca106725	1184	* this domain after reset, you have to enable write access using
Kojto	122:f9eeca106725	1185	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	122:f9eeca106725	1186	* (to be done once after reset).
Kojto	122:f9eeca106725	1187	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	122:f9eeca106725	1188	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	122:f9eeca106725	1189	* is stable and can be used to clock the RTC.
Kojto	122:f9eeca106725	1190	* @param __STATE__ specifies the new state of the LSE.
bogdanm	86:04dd9b1680ae	1191	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1192	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	122:f9eeca106725	1193	* 6 LSE oscillator clock cycles.
Kojto	122:f9eeca106725	1194	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
Kojto	122:f9eeca106725	1195	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
bogdanm	86:04dd9b1680ae	1196	*/
Kojto	122:f9eeca106725	1197	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	122:f9eeca106725	1198	do{ \
Kojto	122:f9eeca106725	1199	if ((__STATE__) == RCC_LSE_ON) \
Kojto	122:f9eeca106725	1200	{ \
Kojto	122:f9eeca106725	1201	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	122:f9eeca106725	1202	} \
Kojto	122:f9eeca106725	1203	else if ((__STATE__) == RCC_LSE_OFF) \
Kojto	122:f9eeca106725	1204	{ \
Kojto	122:f9eeca106725	1205	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	122:f9eeca106725	1206	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	122:f9eeca106725	1207	} \
Kojto	122:f9eeca106725	1208	else if ((__STATE__) == RCC_LSE_BYPASS) \
Kojto	122:f9eeca106725	1209	{ \
Kojto	122:f9eeca106725	1210	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	122:f9eeca106725	1211	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	122:f9eeca106725	1212	} \
Kojto	122:f9eeca106725	1213	else \
Kojto	122:f9eeca106725	1214	{ \
Kojto	122:f9eeca106725	1215	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	122:f9eeca106725	1216	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	122:f9eeca106725	1217	} \
<>	135:176b8275d35d	1218	}while(0U)
bogdanm	86:04dd9b1680ae	1219
bogdanm	92:4fc01daae5a5	1220	/**
bogdanm	92:4fc01daae5a5	1221	* @}
bogdanm	92:4fc01daae5a5	1222	*/
bogdanm	86:04dd9b1680ae	1223
bogdanm	92:4fc01daae5a5	1224	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm	92:4fc01daae5a5	1225	* @{
Kojto	122:f9eeca106725	1226	*/
bogdanm	92:4fc01daae5a5	1227
Kojto	122:f9eeca106725	1228	/** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto	122:f9eeca106725	1229	* @param __USART1CLKSOURCE__ specifies the USART1 clock source.
bogdanm	86:04dd9b1680ae	1230	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1231	@if STM32F302xC
Kojto	122:f9eeca106725	1232	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1233	@endif
Kojto	122:f9eeca106725	1234	@if STM32F303xC
Kojto	122:f9eeca106725	1235	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1236	@endif
Kojto	122:f9eeca106725	1237	@if STM32F358xx
Kojto	122:f9eeca106725	1238	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1239	@endif
Kojto	122:f9eeca106725	1240	@if STM32F302xE
Kojto	122:f9eeca106725	1241	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1242	@endif
Kojto	122:f9eeca106725	1243	@if STM32F303xE
Kojto	122:f9eeca106725	1244	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1245	@endif
Kojto	122:f9eeca106725	1246	@if STM32F398xx
Kojto	122:f9eeca106725	1247	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1248	@endif
Kojto	122:f9eeca106725	1249	@if STM32F373xC
Kojto	122:f9eeca106725	1250	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1251	@endif
Kojto	122:f9eeca106725	1252	@if STM32F378xx
Kojto	122:f9eeca106725	1253	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1254	@endif
Kojto	122:f9eeca106725	1255	@if STM32F301x8
Kojto	122:f9eeca106725	1256	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1257	@endif
Kojto	122:f9eeca106725	1258	@if STM32F302x8
Kojto	122:f9eeca106725	1259	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1260	@endif
Kojto	122:f9eeca106725	1261	@if STM32F318xx
Kojto	122:f9eeca106725	1262	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1263	@endif
Kojto	122:f9eeca106725	1264	@if STM32F303x8
Kojto	122:f9eeca106725	1265	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1266	@endif
Kojto	122:f9eeca106725	1267	@if STM32F334x8
Kojto	122:f9eeca106725	1268	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1269	@endif
Kojto	122:f9eeca106725	1270	@if STM32F328xx
Kojto	122:f9eeca106725	1271	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1272	@endif
Kojto	122:f9eeca106725	1273	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto	122:f9eeca106725	1274	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto	122:f9eeca106725	1275	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
bogdanm	86:04dd9b1680ae	1276	*/
Kojto	122:f9eeca106725	1277	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
Kojto	122:f9eeca106725	1278	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
bogdanm	86:04dd9b1680ae	1279
bogdanm	86:04dd9b1680ae	1280	/** @brief Macro to get the USART1 clock source.
bogdanm	86:04dd9b1680ae	1281	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1282	@if STM32F302xC
Kojto	122:f9eeca106725	1283	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1284	@endif
Kojto	122:f9eeca106725	1285	@if STM32F303xC
Kojto	122:f9eeca106725	1286	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1287	@endif
Kojto	122:f9eeca106725	1288	@if STM32F358xx
Kojto	122:f9eeca106725	1289	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1290	@endif
Kojto	122:f9eeca106725	1291	@if STM32F302xE
Kojto	122:f9eeca106725	1292	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1293	@endif
Kojto	122:f9eeca106725	1294	@if STM32F303xE
Kojto	122:f9eeca106725	1295	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1296	@endif
Kojto	122:f9eeca106725	1297	@if STM32F398xx
Kojto	122:f9eeca106725	1298	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1299	@endif
Kojto	122:f9eeca106725	1300	@if STM32F373xC
Kojto	122:f9eeca106725	1301	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1302	@endif
Kojto	122:f9eeca106725	1303	@if STM32F378xx
Kojto	122:f9eeca106725	1304	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto	122:f9eeca106725	1305	@endif
Kojto	122:f9eeca106725	1306	@if STM32F301x8
Kojto	122:f9eeca106725	1307	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1308	@endif
Kojto	122:f9eeca106725	1309	@if STM32F302x8
Kojto	122:f9eeca106725	1310	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1311	@endif
Kojto	122:f9eeca106725	1312	@if STM32F318xx
Kojto	122:f9eeca106725	1313	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1314	@endif
Kojto	122:f9eeca106725	1315	@if STM32F303x8
Kojto	122:f9eeca106725	1316	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1317	@endif
Kojto	122:f9eeca106725	1318	@if STM32F334x8
Kojto	122:f9eeca106725	1319	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1320	@endif
Kojto	122:f9eeca106725	1321	@if STM32F328xx
Kojto	122:f9eeca106725	1322	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto	122:f9eeca106725	1323	@endif
Kojto	122:f9eeca106725	1324	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto	122:f9eeca106725	1325	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto	122:f9eeca106725	1326	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
bogdanm	86:04dd9b1680ae	1327	*/
bogdanm	86:04dd9b1680ae	1328	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm	86:04dd9b1680ae	1329
Kojto	122:f9eeca106725	1330	#if defined(RCC_CFGR3_USART2SW)
bogdanm	86:04dd9b1680ae	1331	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	122:f9eeca106725	1332	* @param __USART2CLKSOURCE__ specifies the USART2 clock source.
bogdanm	86:04dd9b1680ae	1333	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1334	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto	122:f9eeca106725	1335	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto	122:f9eeca106725	1336	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto	122:f9eeca106725	1337	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
bogdanm	86:04dd9b1680ae	1338	*/
Kojto	122:f9eeca106725	1339	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
Kojto	122:f9eeca106725	1340	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
bogdanm	86:04dd9b1680ae	1341
bogdanm	86:04dd9b1680ae	1342	/** @brief Macro to get the USART2 clock source.
bogdanm	86:04dd9b1680ae	1343	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1344	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto	122:f9eeca106725	1345	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto	122:f9eeca106725	1346	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto	122:f9eeca106725	1347	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
bogdanm	86:04dd9b1680ae	1348	*/
bogdanm	86:04dd9b1680ae	1349	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	122:f9eeca106725	1350	#endif /* RCC_CFGR3_USART2SW */
bogdanm	86:04dd9b1680ae	1351
Kojto	122:f9eeca106725	1352	#if defined(RCC_CFGR3_USART3SW)
bogdanm	86:04dd9b1680ae	1353	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	122:f9eeca106725	1354	* @param __USART3CLKSOURCE__ specifies the USART3 clock source.
bogdanm	86:04dd9b1680ae	1355	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1356	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto	122:f9eeca106725	1357	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto	122:f9eeca106725	1358	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto	122:f9eeca106725	1359	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
bogdanm	86:04dd9b1680ae	1360	*/
Kojto	122:f9eeca106725	1361	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
Kojto	122:f9eeca106725	1362	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
bogdanm	86:04dd9b1680ae	1363
bogdanm	86:04dd9b1680ae	1364	/** @brief Macro to get the USART3 clock source.
bogdanm	86:04dd9b1680ae	1365	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1366	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto	122:f9eeca106725	1367	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto	122:f9eeca106725	1368	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto	122:f9eeca106725	1369	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
bogdanm	86:04dd9b1680ae	1370	*/
bogdanm	86:04dd9b1680ae	1371	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto	122:f9eeca106725	1372	#endif /* RCC_CFGR3_USART2SW */
bogdanm	92:4fc01daae5a5	1373	/**
bogdanm	92:4fc01daae5a5	1374	* @}
bogdanm	92:4fc01daae5a5	1375	*/
bogdanm	86:04dd9b1680ae	1376
Kojto	122:f9eeca106725	1377	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto	122:f9eeca106725	1378	* @{
Kojto	122:f9eeca106725	1379	*/
Kojto	122:f9eeca106725	1380
Kojto	122:f9eeca106725	1381	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto	122:f9eeca106725	1382	* @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
Kojto	122:f9eeca106725	1383	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1384	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto	122:f9eeca106725	1385	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto	122:f9eeca106725	1386	*/
Kojto	122:f9eeca106725	1387	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
Kojto	122:f9eeca106725	1388	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
Kojto	122:f9eeca106725	1389
Kojto	122:f9eeca106725	1390	/** @brief Macro to get the I2C1 clock source.
Kojto	122:f9eeca106725	1391	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1392	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto	122:f9eeca106725	1393	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto	122:f9eeca106725	1394	*/
Kojto	122:f9eeca106725	1395	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto	122:f9eeca106725	1396	/**
Kojto	122:f9eeca106725	1397	* @}
Kojto	122:f9eeca106725	1398	*/
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	122:f9eeca106725	1401	* @{
Kojto	122:f9eeca106725	1402	*/
Kojto	122:f9eeca106725	1403
Kojto	122:f9eeca106725	1404	/** @brief Macro to enable the main PLL.
Kojto	122:f9eeca106725	1405	* @note After enabling the main PLL, the application software should wait on
Kojto	122:f9eeca106725	1406	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	122:f9eeca106725	1407	* be used as system clock source.
Kojto	122:f9eeca106725	1408	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	122:f9eeca106725	1409	*/
Kojto	122:f9eeca106725	1410	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
Kojto	122:f9eeca106725	1411
Kojto	122:f9eeca106725	1412	/** @brief Macro to disable the main PLL.
Kojto	122:f9eeca106725	1413	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	122:f9eeca106725	1414	*/
Kojto	122:f9eeca106725	1415	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
Kojto	122:f9eeca106725	1416
Kojto	122:f9eeca106725	1417
Kojto	122:f9eeca106725	1418	/** @brief Get oscillator clock selected as PLL input clock
Kojto	122:f9eeca106725	1419	* @retval The clock source used for PLL entry. The returned value can be one
Kojto	122:f9eeca106725	1420	* of the following:
Kojto	122:f9eeca106725	1421	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
Kojto	122:f9eeca106725	1422	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
Kojto	122:f9eeca106725	1423	*/
Kojto	122:f9eeca106725	1424	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto	122:f9eeca106725	1425
Kojto	122:f9eeca106725	1426	/**
Kojto	122:f9eeca106725	1427	* @}
Kojto	122:f9eeca106725	1428	*/
Kojto	122:f9eeca106725	1429
Kojto	122:f9eeca106725	1430	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	122:f9eeca106725	1431	* @{
Kojto	122:f9eeca106725	1432	*/
Kojto	122:f9eeca106725	1433
Kojto	122:f9eeca106725	1434	/**
Kojto	122:f9eeca106725	1435	* @brief Macro to configure the system clock source.
Kojto	122:f9eeca106725	1436	* @param __SYSCLKSOURCE__ specifies the system clock source.
Kojto	122:f9eeca106725	1437	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1438	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
Kojto	122:f9eeca106725	1439	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
Kojto	122:f9eeca106725	1440	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
Kojto	122:f9eeca106725	1441	*/
Kojto	122:f9eeca106725	1442	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto	122:f9eeca106725	1443	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto	122:f9eeca106725	1444
Kojto	122:f9eeca106725	1445	/** @brief Macro to get the clock source used as system clock.
Kojto	122:f9eeca106725	1446	* @retval The clock source used as system clock. The returned value can be one
Kojto	122:f9eeca106725	1447	* of the following:
Kojto	122:f9eeca106725	1448	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
Kojto	122:f9eeca106725	1449	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
Kojto	122:f9eeca106725	1450	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
Kojto	122:f9eeca106725	1451	*/
Kojto	122:f9eeca106725	1452	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto	122:f9eeca106725	1453
Kojto	122:f9eeca106725	1454	/**
Kojto	122:f9eeca106725	1455	* @}
Kojto	122:f9eeca106725	1456	*/
Kojto	122:f9eeca106725	1457
Kojto	122:f9eeca106725	1458	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
bogdanm	92:4fc01daae5a5	1459	* @{
bogdanm	92:4fc01daae5a5	1460	*/
Kojto	122:f9eeca106725	1461
Kojto	122:f9eeca106725	1462	#if defined(RCC_CFGR_MCOPRE)
Kojto	122:f9eeca106725	1463	/** @brief Macro to configure the MCO clock.
Kojto	122:f9eeca106725	1464	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	122:f9eeca106725	1465	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1466	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Kojto	122:f9eeca106725	1467	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
Kojto	122:f9eeca106725	1468	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
Kojto	122:f9eeca106725	1469	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
Kojto	122:f9eeca106725	1470	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
Kojto	122:f9eeca106725	1471	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
Kojto	122:f9eeca106725	1472	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
Kojto	122:f9eeca106725	1473	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	122:f9eeca106725	1474	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1475	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
Kojto	122:f9eeca106725	1476	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
Kojto	122:f9eeca106725	1477	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
Kojto	122:f9eeca106725	1478	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
Kojto	122:f9eeca106725	1479	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
Kojto	122:f9eeca106725	1480	* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
Kojto	122:f9eeca106725	1481	* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
Kojto	122:f9eeca106725	1482	* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
bogdanm	86:04dd9b1680ae	1483	*/
Kojto	122:f9eeca106725	1484	#else
Kojto	122:f9eeca106725	1485	/** @brief Macro to configure the MCO clock.
Kojto	122:f9eeca106725	1486	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	122:f9eeca106725	1487	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1488	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Kojto	122:f9eeca106725	1489	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
Kojto	122:f9eeca106725	1490	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
Kojto	122:f9eeca106725	1491	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
Kojto	122:f9eeca106725	1492	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
Kojto	122:f9eeca106725	1493	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
Kojto	122:f9eeca106725	1494	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
Kojto	122:f9eeca106725	1495	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	122:f9eeca106725	1496	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1497	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
Kojto	122:f9eeca106725	1498	*/
Kojto	122:f9eeca106725	1499	#endif
Kojto	122:f9eeca106725	1500	#if defined(RCC_CFGR_MCOPRE)
Kojto	122:f9eeca106725	1501	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	122:f9eeca106725	1502	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
Kojto	122:f9eeca106725	1503	#else
bogdanm	86:04dd9b1680ae	1504
Kojto	122:f9eeca106725	1505	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	122:f9eeca106725	1506	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Kojto	122:f9eeca106725	1507
Kojto	122:f9eeca106725	1508	#endif
Kojto	122:f9eeca106725	1509
Kojto	122:f9eeca106725	1510	/**
Kojto	122:f9eeca106725	1511	* @}
Kojto	122:f9eeca106725	1512	*/
Kojto	122:f9eeca106725	1513
Kojto	122:f9eeca106725	1514	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto	122:f9eeca106725	1515	* @{
Kojto	122:f9eeca106725	1516	*/
Kojto	122:f9eeca106725	1517
Kojto	122:f9eeca106725	1518	/** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm	86:04dd9b1680ae	1519	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	86:04dd9b1680ae	1520	* access is denied to this domain after reset, you have to enable write
bogdanm	86:04dd9b1680ae	1521	* access using the Power Backup Access macro before to configure
Kojto	122:f9eeca106725	1522	* the RTC clock source (to be done once after reset).
Kojto	123:b0220dba8be7	1523	* @note Once the RTC clock is configured it cannot be changed unless the
Kojto	122:f9eeca106725	1524	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	86:04dd9b1680ae	1525	* a Power On Reset (POR).
bogdanm	86:04dd9b1680ae	1526	*
Kojto	122:f9eeca106725	1527	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
Kojto	122:f9eeca106725	1528	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1529	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Kojto	122:f9eeca106725	1530	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto	122:f9eeca106725	1531	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto	122:f9eeca106725	1532	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
Kojto	122:f9eeca106725	1533	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	86:04dd9b1680ae	1534	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	86:04dd9b1680ae	1535	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm	86:04dd9b1680ae	1536	* the RTC cannot be used in STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	1537	* @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm	86:04dd9b1680ae	1538	* equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm	86:04dd9b1680ae	1539	*/
Kojto	122:f9eeca106725	1540	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto	122:f9eeca106725	1541
Kojto	122:f9eeca106725	1542	/** @brief Macro to get the RTC clock source.
bogdanm	86:04dd9b1680ae	1543	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1544	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Kojto	122:f9eeca106725	1545	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto	122:f9eeca106725	1546	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto	122:f9eeca106725	1547	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
Kojto	122:f9eeca106725	1548	*/
Kojto	122:f9eeca106725	1549	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Kojto	122:f9eeca106725	1550
Kojto	122:f9eeca106725	1551	/** @brief Macro to enable the the RTC clock.
Kojto	122:f9eeca106725	1552	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	86:04dd9b1680ae	1553	*/
Kojto	122:f9eeca106725	1554	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto	122:f9eeca106725	1555
Kojto	122:f9eeca106725	1556	/** @brief Macro to disable the the RTC clock.
Kojto	122:f9eeca106725	1557	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	92:4fc01daae5a5	1558	*/
Kojto	122:f9eeca106725	1559	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm	92:4fc01daae5a5	1560
Kojto	122:f9eeca106725	1561	/** @brief Macro to force the Backup domain reset.
Kojto	122:f9eeca106725	1562	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	122:f9eeca106725	1563	* and the RTC clock source selection in RCC_BDCR register.
Kojto	122:f9eeca106725	1564	*/
Kojto	122:f9eeca106725	1565	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
bogdanm	86:04dd9b1680ae	1566
Kojto	122:f9eeca106725	1567	/** @brief Macros to release the Backup domain reset.
bogdanm	86:04dd9b1680ae	1568	*/
Kojto	122:f9eeca106725	1569	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
Kojto	122:f9eeca106725	1570
bogdanm	92:4fc01daae5a5	1571	/**
bogdanm	92:4fc01daae5a5	1572	* @}
bogdanm	92:4fc01daae5a5	1573	*/
bogdanm	92:4fc01daae5a5	1574
Kojto	122:f9eeca106725	1575	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	86:04dd9b1680ae	1576	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	86:04dd9b1680ae	1577	* @{
bogdanm	86:04dd9b1680ae	1578	*/
bogdanm	86:04dd9b1680ae	1579
Kojto	122:f9eeca106725	1580	/** @brief Enable RCC interrupt.
Kojto	122:f9eeca106725	1581	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
Kojto	122:f9eeca106725	1582	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1583	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto	122:f9eeca106725	1584	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto	122:f9eeca106725	1585	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto	122:f9eeca106725	1586	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto	122:f9eeca106725	1587	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
bogdanm	86:04dd9b1680ae	1588	*/
Kojto	122:f9eeca106725	1589	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1590
Kojto	122:f9eeca106725	1591	/** @brief Disable RCC interrupt.
Kojto	122:f9eeca106725	1592	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
Kojto	122:f9eeca106725	1593	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1594	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto	122:f9eeca106725	1595	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto	122:f9eeca106725	1596	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto	122:f9eeca106725	1597	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto	122:f9eeca106725	1598	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
bogdanm	86:04dd9b1680ae	1599	*/
Kojto	122:f9eeca106725	1600	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	1601
Kojto	122:f9eeca106725	1602	/** @brief Clear the RCC's interrupt pending bits.
Kojto	122:f9eeca106725	1603	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Kojto	122:f9eeca106725	1604	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1605	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
Kojto	122:f9eeca106725	1606	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
Kojto	122:f9eeca106725	1607	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
Kojto	122:f9eeca106725	1608	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
Kojto	122:f9eeca106725	1609	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
Kojto	122:f9eeca106725	1610	* @arg @ref RCC_IT_CSS Clock Security System interrupt
bogdanm	86:04dd9b1680ae	1611	*/
Kojto	122:f9eeca106725	1612	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1613
Kojto	122:f9eeca106725	1614	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	122:f9eeca106725	1615	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
Kojto	122:f9eeca106725	1616	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1617	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
Kojto	122:f9eeca106725	1618	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
Kojto	122:f9eeca106725	1619	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
Kojto	122:f9eeca106725	1620	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
Kojto	122:f9eeca106725	1621	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
Kojto	122:f9eeca106725	1622	* @arg @ref RCC_IT_CSS Clock Security System interrupt
Kojto	122:f9eeca106725	1623	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	1624	*/
Kojto	122:f9eeca106725	1625	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	1626
Kojto	122:f9eeca106725	1627	/** @brief Set RMVF bit to clear the reset flags.
Kojto	122:f9eeca106725	1628	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	122:f9eeca106725	1629	* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	86:04dd9b1680ae	1630	*/
Kojto	122:f9eeca106725	1631	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )RCC_CSR_RMVF_BB = ENABLE)
bogdanm	86:04dd9b1680ae	1632
bogdanm	86:04dd9b1680ae	1633	/** @brief Check RCC flag is set or not.
Kojto	122:f9eeca106725	1634	* @param __FLAG__ specifies the flag to check.
Kojto	122:f9eeca106725	1635	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1636	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
Kojto	122:f9eeca106725	1637	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
Kojto	122:f9eeca106725	1638	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
Kojto	122:f9eeca106725	1639	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
Kojto	122:f9eeca106725	1640	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
Kojto	122:f9eeca106725	1641	* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
Kojto	122:f9eeca106725	1642	* @arg @ref RCC_FLAG_PINRST Pin reset.
Kojto	122:f9eeca106725	1643	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
Kojto	122:f9eeca106725	1644	* @arg @ref RCC_FLAG_SFTRST Software reset.
Kojto	122:f9eeca106725	1645	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
Kojto	122:f9eeca106725	1646	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
Kojto	122:f9eeca106725	1647	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
Kojto	122:f9eeca106725	1648	@if defined(STM32F301x8)
Kojto	122:f9eeca106725	1649	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1650	@endif
Kojto	122:f9eeca106725	1651	@if defined(STM32F302x8)
Kojto	122:f9eeca106725	1652	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1653	@endif
Kojto	122:f9eeca106725	1654	@if defined(STM32F302xC)
Kojto	122:f9eeca106725	1655	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1656	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
Kojto	122:f9eeca106725	1657	@endif
Kojto	122:f9eeca106725	1658	@if defined(STM32F302xE)
Kojto	122:f9eeca106725	1659	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1660	@endif
Kojto	122:f9eeca106725	1661	@if defined(STM32F303x8)
Kojto	122:f9eeca106725	1662	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1663	@endif
Kojto	122:f9eeca106725	1664	@if defined(STM32F303xC)
Kojto	122:f9eeca106725	1665	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1666	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
Kojto	122:f9eeca106725	1667	@endif
Kojto	122:f9eeca106725	1668	@if defined(STM32F303xE)
Kojto	122:f9eeca106725	1669	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1670	@endif
Kojto	122:f9eeca106725	1671	@if defined(STM32F334x8)
Kojto	122:f9eeca106725	1672	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1673	@endif
Kojto	122:f9eeca106725	1674	@if defined(STM32F358xx)
Kojto	122:f9eeca106725	1675	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
Kojto	122:f9eeca106725	1676	@endif
Kojto	122:f9eeca106725	1677	@if defined(STM32F373xC)
Kojto	122:f9eeca106725	1678	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto	122:f9eeca106725	1679	@endif
bogdanm	86:04dd9b1680ae	1680	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	1681	*/
<>	135:176b8275d35d	1682	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
<>	135:176b8275d35d	1683	(((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
<>	135:176b8275d35d	1684	(((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
<>	135:176b8275d35d	1685	RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	86:04dd9b1680ae	1686
bogdanm	86:04dd9b1680ae	1687	/**
bogdanm	86:04dd9b1680ae	1688	* @}
bogdanm	86:04dd9b1680ae	1689	*/
bogdanm	86:04dd9b1680ae	1690
bogdanm	92:4fc01daae5a5	1691	/**
bogdanm	92:4fc01daae5a5	1692	* @}
bogdanm	92:4fc01daae5a5	1693	*/
bogdanm	92:4fc01daae5a5	1694
Kojto	122:f9eeca106725	1695	/* Include RCC HAL Extension module */
bogdanm	86:04dd9b1680ae	1696	#include "stm32f3xx_hal_rcc_ex.h"
bogdanm	86:04dd9b1680ae	1697
bogdanm	86:04dd9b1680ae	1698	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1699	/** @addtogroup RCC_Exported_Functions
bogdanm	92:4fc01daae5a5	1700	* @{
bogdanm	92:4fc01daae5a5	1701	*/
bogdanm	92:4fc01daae5a5	1702
Kojto	122:f9eeca106725	1703	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	1704	* @{
bogdanm	92:4fc01daae5a5	1705	*/
bogdanm	92:4fc01daae5a5	1706
Kojto	122:f9eeca106725	1707	/* Initialization and de-initialization functions ******************************/
Kojto	122:f9eeca106725	1708	void HAL_RCC_DeInit(void);
Kojto	122:f9eeca106725	1709	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	122:f9eeca106725	1710	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	86:04dd9b1680ae	1711
bogdanm	92:4fc01daae5a5	1712	/**
bogdanm	92:4fc01daae5a5	1713	* @}
bogdanm	92:4fc01daae5a5	1714	*/
bogdanm	92:4fc01daae5a5	1715
Kojto	122:f9eeca106725	1716	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	1717	* @{
bogdanm	92:4fc01daae5a5	1718	*/
Kojto	122:f9eeca106725	1719
Kojto	122:f9eeca106725	1720	/* Peripheral Control functions ************************************************/
Kojto	122:f9eeca106725	1721	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	122:f9eeca106725	1722	void HAL_RCC_EnableCSS(void);
<>	135:176b8275d35d	1723	/* CSS NMI IRQ handler */
<>	135:176b8275d35d	1724	void HAL_RCC_NMI_IRQHandler(void);
<>	135:176b8275d35d	1725	/* User Callbacks in non blocking mode (IT mode) */
<>	135:176b8275d35d	1726	void HAL_RCC_CSSCallback(void);
Kojto	122:f9eeca106725	1727	void HAL_RCC_DisableCSS(void);
Kojto	122:f9eeca106725	1728	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	122:f9eeca106725	1729	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	122:f9eeca106725	1730	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	122:f9eeca106725	1731	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	122:f9eeca106725	1732	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	122:f9eeca106725	1733	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	86:04dd9b1680ae	1734
bogdanm	86:04dd9b1680ae	1735	/**
bogdanm	86:04dd9b1680ae	1736	* @}
bogdanm	86:04dd9b1680ae	1737	*/
bogdanm	86:04dd9b1680ae	1738
bogdanm	86:04dd9b1680ae	1739	/**
bogdanm	86:04dd9b1680ae	1740	* @}
bogdanm	86:04dd9b1680ae	1741	*/
bogdanm	86:04dd9b1680ae	1742
bogdanm	92:4fc01daae5a5	1743	/**
bogdanm	92:4fc01daae5a5	1744	* @}
bogdanm	92:4fc01daae5a5	1745	*/
bogdanm	92:4fc01daae5a5	1746
bogdanm	92:4fc01daae5a5	1747	/**
bogdanm	92:4fc01daae5a5	1748	* @}
bogdanm	92:4fc01daae5a5	1749	*/
Kojto	122:f9eeca106725	1750
bogdanm	86:04dd9b1680ae	1751	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	1752	}
bogdanm	86:04dd9b1680ae	1753	#endif
bogdanm	86:04dd9b1680ae	1754
bogdanm	86:04dd9b1680ae	1755	#endif /* __STM32F3xx_HAL_RCC_H */
bogdanm	86:04dd9b1680ae	1756
bogdanm	86:04dd9b1680ae	1757	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	122:f9eeca106725	1758