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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h@136:ef9c61f8c49f, 2017-02-14 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 14 11:24:20 2017 +0000
- Revision:
- 136:ef9c61f8c49f
- Parent:
- 135:176b8275d35d
Release 136 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 86:04dd9b1680ae | 1 | /** |
bogdanm | 86:04dd9b1680ae | 2 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 3 | * @file stm32f3xx_hal_dma.h |
bogdanm | 86:04dd9b1680ae | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
bogdanm | 86:04dd9b1680ae | 7 | * @brief Header file of DMA HAL module. |
bogdanm | 86:04dd9b1680ae | 8 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 9 | * @attention |
bogdanm | 86:04dd9b1680ae | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
bogdanm | 86:04dd9b1680ae | 12 | * |
bogdanm | 86:04dd9b1680ae | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 86:04dd9b1680ae | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 86:04dd9b1680ae | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 86:04dd9b1680ae | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 86:04dd9b1680ae | 19 | * and/or other materials provided with the distribution. |
bogdanm | 86:04dd9b1680ae | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 86:04dd9b1680ae | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 86:04dd9b1680ae | 22 | * without specific prior written permission. |
bogdanm | 86:04dd9b1680ae | 23 | * |
bogdanm | 86:04dd9b1680ae | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 86:04dd9b1680ae | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 86:04dd9b1680ae | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 86:04dd9b1680ae | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 86:04dd9b1680ae | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 86:04dd9b1680ae | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 86:04dd9b1680ae | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 86:04dd9b1680ae | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 86:04dd9b1680ae | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 86:04dd9b1680ae | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 86:04dd9b1680ae | 34 | * |
bogdanm | 86:04dd9b1680ae | 35 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 36 | */ |
bogdanm | 86:04dd9b1680ae | 37 | |
bogdanm | 86:04dd9b1680ae | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 39 | #ifndef __STM32F3xx_HAL_DMA_H |
bogdanm | 86:04dd9b1680ae | 40 | #define __STM32F3xx_HAL_DMA_H |
bogdanm | 86:04dd9b1680ae | 41 | |
bogdanm | 86:04dd9b1680ae | 42 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 43 | extern "C" { |
bogdanm | 86:04dd9b1680ae | 44 | #endif |
bogdanm | 86:04dd9b1680ae | 45 | |
bogdanm | 86:04dd9b1680ae | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 47 | #include "stm32f3xx_hal_def.h" |
bogdanm | 86:04dd9b1680ae | 48 | |
bogdanm | 86:04dd9b1680ae | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
bogdanm | 86:04dd9b1680ae | 50 | * @{ |
bogdanm | 86:04dd9b1680ae | 51 | */ |
bogdanm | 86:04dd9b1680ae | 52 | |
Kojto | 122:f9eeca106725 | 53 | /** @addtogroup DMA |
bogdanm | 86:04dd9b1680ae | 54 | * @{ |
bogdanm | 86:04dd9b1680ae | 55 | */ |
bogdanm | 86:04dd9b1680ae | 56 | |
bogdanm | 86:04dd9b1680ae | 57 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 58 | |
bogdanm | 92:4fc01daae5a5 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
bogdanm | 92:4fc01daae5a5 | 60 | * @{ |
bogdanm | 92:4fc01daae5a5 | 61 | */ |
bogdanm | 86:04dd9b1680ae | 62 | |
bogdanm | 86:04dd9b1680ae | 63 | /** |
bogdanm | 86:04dd9b1680ae | 64 | * @brief DMA Configuration Structure definition |
bogdanm | 86:04dd9b1680ae | 65 | */ |
bogdanm | 86:04dd9b1680ae | 66 | typedef struct |
bogdanm | 86:04dd9b1680ae | 67 | { |
bogdanm | 86:04dd9b1680ae | 68 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
bogdanm | 86:04dd9b1680ae | 69 | from memory to memory or from peripheral to memory. |
bogdanm | 86:04dd9b1680ae | 70 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
bogdanm | 86:04dd9b1680ae | 71 | |
bogdanm | 86:04dd9b1680ae | 72 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
bogdanm | 86:04dd9b1680ae | 73 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
bogdanm | 86:04dd9b1680ae | 74 | |
bogdanm | 86:04dd9b1680ae | 75 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
bogdanm | 86:04dd9b1680ae | 76 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
bogdanm | 86:04dd9b1680ae | 77 | |
bogdanm | 86:04dd9b1680ae | 78 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
bogdanm | 86:04dd9b1680ae | 79 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
bogdanm | 86:04dd9b1680ae | 80 | |
bogdanm | 86:04dd9b1680ae | 81 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
bogdanm | 86:04dd9b1680ae | 82 | This parameter can be a value of @ref DMA_Memory_data_size */ |
bogdanm | 86:04dd9b1680ae | 83 | |
bogdanm | 86:04dd9b1680ae | 84 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
bogdanm | 86:04dd9b1680ae | 85 | This parameter can be a value of @ref DMA_mode |
bogdanm | 86:04dd9b1680ae | 86 | @note The circular buffer mode cannot be used if the memory-to-memory |
<> | 135:176b8275d35d | 87 | data transfer is configured on the selected Channel */ |
bogdanm | 86:04dd9b1680ae | 88 | |
bogdanm | 86:04dd9b1680ae | 89 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
bogdanm | 86:04dd9b1680ae | 90 | This parameter can be a value of @ref DMA_Priority_level */ |
bogdanm | 86:04dd9b1680ae | 91 | } DMA_InitTypeDef; |
bogdanm | 86:04dd9b1680ae | 92 | |
bogdanm | 86:04dd9b1680ae | 93 | /** |
bogdanm | 86:04dd9b1680ae | 94 | * @brief HAL DMA State structures definition |
bogdanm | 86:04dd9b1680ae | 95 | */ |
bogdanm | 86:04dd9b1680ae | 96 | typedef enum |
bogdanm | 86:04dd9b1680ae | 97 | { |
<> | 135:176b8275d35d | 98 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
<> | 135:176b8275d35d | 99 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
<> | 135:176b8275d35d | 100 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
<> | 135:176b8275d35d | 101 | HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */ |
bogdanm | 86:04dd9b1680ae | 102 | }HAL_DMA_StateTypeDef; |
bogdanm | 86:04dd9b1680ae | 103 | |
bogdanm | 86:04dd9b1680ae | 104 | /** |
bogdanm | 86:04dd9b1680ae | 105 | * @brief HAL DMA Error Code structure definition |
bogdanm | 86:04dd9b1680ae | 106 | */ |
bogdanm | 86:04dd9b1680ae | 107 | typedef enum |
bogdanm | 86:04dd9b1680ae | 108 | { |
<> | 135:176b8275d35d | 109 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
<> | 135:176b8275d35d | 110 | HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ |
<> | 135:176b8275d35d | 111 | }HAL_DMA_LevelCompleteTypeDef; |
<> | 135:176b8275d35d | 112 | |
<> | 135:176b8275d35d | 113 | /** |
<> | 135:176b8275d35d | 114 | * @brief HAL DMA Callback ID structure definition |
<> | 135:176b8275d35d | 115 | */ |
<> | 135:176b8275d35d | 116 | typedef enum |
<> | 135:176b8275d35d | 117 | { |
<> | 135:176b8275d35d | 118 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
<> | 135:176b8275d35d | 119 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ |
<> | 135:176b8275d35d | 120 | HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ |
<> | 135:176b8275d35d | 121 | HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ |
<> | 135:176b8275d35d | 122 | HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ |
<> | 135:176b8275d35d | 123 | }HAL_DMA_CallbackIDTypeDef; |
<> | 135:176b8275d35d | 124 | |
bogdanm | 86:04dd9b1680ae | 125 | /** |
bogdanm | 86:04dd9b1680ae | 126 | * @brief DMA handle Structure definition |
bogdanm | 86:04dd9b1680ae | 127 | */ |
bogdanm | 86:04dd9b1680ae | 128 | typedef struct __DMA_HandleTypeDef |
bogdanm | 86:04dd9b1680ae | 129 | { |
Kojto | 122:f9eeca106725 | 130 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
bogdanm | 86:04dd9b1680ae | 131 | |
bogdanm | 86:04dd9b1680ae | 132 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
bogdanm | 86:04dd9b1680ae | 133 | |
bogdanm | 86:04dd9b1680ae | 134 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
bogdanm | 86:04dd9b1680ae | 135 | |
bogdanm | 86:04dd9b1680ae | 136 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
bogdanm | 86:04dd9b1680ae | 137 | |
bogdanm | 86:04dd9b1680ae | 138 | void *Parent; /*!< Parent object state */ |
bogdanm | 86:04dd9b1680ae | 139 | |
bogdanm | 86:04dd9b1680ae | 140 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
bogdanm | 86:04dd9b1680ae | 141 | |
bogdanm | 86:04dd9b1680ae | 142 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
Kojto | 122:f9eeca106725 | 143 | |
bogdanm | 86:04dd9b1680ae | 144 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
bogdanm | 86:04dd9b1680ae | 145 | |
<> | 135:176b8275d35d | 146 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
bogdanm | 86:04dd9b1680ae | 147 | |
Kojto | 122:f9eeca106725 | 148 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
<> | 135:176b8275d35d | 149 | |
<> | 135:176b8275d35d | 150 | DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
<> | 135:176b8275d35d | 151 | |
<> | 135:176b8275d35d | 152 | uint32_t ChannelIndex; /*!< DMA Channel Index */ |
bogdanm | 86:04dd9b1680ae | 153 | } DMA_HandleTypeDef; |
bogdanm | 92:4fc01daae5a5 | 154 | /** |
bogdanm | 92:4fc01daae5a5 | 155 | * @} |
bogdanm | 92:4fc01daae5a5 | 156 | */ |
bogdanm | 86:04dd9b1680ae | 157 | |
bogdanm | 86:04dd9b1680ae | 158 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 159 | |
bogdanm | 92:4fc01daae5a5 | 160 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
bogdanm | 86:04dd9b1680ae | 161 | * @{ |
bogdanm | 86:04dd9b1680ae | 162 | */ |
bogdanm | 86:04dd9b1680ae | 163 | |
Kojto | 122:f9eeca106725 | 164 | /** @defgroup DMA_Error_Code DMA Error Code |
bogdanm | 86:04dd9b1680ae | 165 | * @{ |
bogdanm | 86:04dd9b1680ae | 166 | */ |
<> | 135:176b8275d35d | 167 | #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ |
<> | 135:176b8275d35d | 168 | #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ |
<> | 135:176b8275d35d | 169 | #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ |
<> | 135:176b8275d35d | 170 | #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ |
<> | 135:176b8275d35d | 171 | #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ |
bogdanm | 86:04dd9b1680ae | 172 | /** |
bogdanm | 86:04dd9b1680ae | 173 | * @} |
bogdanm | 86:04dd9b1680ae | 174 | */ |
bogdanm | 86:04dd9b1680ae | 175 | |
Kojto | 122:f9eeca106725 | 176 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
bogdanm | 86:04dd9b1680ae | 177 | * @{ |
bogdanm | 86:04dd9b1680ae | 178 | */ |
<> | 135:176b8275d35d | 179 | #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ |
bogdanm | 86:04dd9b1680ae | 180 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
Kojto | 122:f9eeca106725 | 181 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
bogdanm | 86:04dd9b1680ae | 182 | |
bogdanm | 86:04dd9b1680ae | 183 | /** |
bogdanm | 86:04dd9b1680ae | 184 | * @} |
bogdanm | 86:04dd9b1680ae | 185 | */ |
<> | 135:176b8275d35d | 186 | |
bogdanm | 92:4fc01daae5a5 | 187 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
bogdanm | 86:04dd9b1680ae | 188 | * @{ |
bogdanm | 86:04dd9b1680ae | 189 | */ |
bogdanm | 86:04dd9b1680ae | 190 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
<> | 135:176b8275d35d | 191 | #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ |
bogdanm | 86:04dd9b1680ae | 192 | /** |
bogdanm | 86:04dd9b1680ae | 193 | * @} |
bogdanm | 86:04dd9b1680ae | 194 | */ |
bogdanm | 86:04dd9b1680ae | 195 | |
bogdanm | 92:4fc01daae5a5 | 196 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
bogdanm | 86:04dd9b1680ae | 197 | * @{ |
bogdanm | 86:04dd9b1680ae | 198 | */ |
bogdanm | 86:04dd9b1680ae | 199 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
<> | 135:176b8275d35d | 200 | #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ |
bogdanm | 86:04dd9b1680ae | 201 | /** |
bogdanm | 86:04dd9b1680ae | 202 | * @} |
bogdanm | 86:04dd9b1680ae | 203 | */ |
bogdanm | 86:04dd9b1680ae | 204 | |
bogdanm | 92:4fc01daae5a5 | 205 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
bogdanm | 86:04dd9b1680ae | 206 | * @{ |
bogdanm | 86:04dd9b1680ae | 207 | */ |
<> | 135:176b8275d35d | 208 | #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ |
bogdanm | 86:04dd9b1680ae | 209 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
bogdanm | 86:04dd9b1680ae | 210 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
bogdanm | 86:04dd9b1680ae | 211 | /** |
bogdanm | 86:04dd9b1680ae | 212 | * @} |
bogdanm | 86:04dd9b1680ae | 213 | */ |
bogdanm | 86:04dd9b1680ae | 214 | |
bogdanm | 92:4fc01daae5a5 | 215 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
bogdanm | 86:04dd9b1680ae | 216 | * @{ |
bogdanm | 86:04dd9b1680ae | 217 | */ |
<> | 135:176b8275d35d | 218 | #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ |
bogdanm | 86:04dd9b1680ae | 219 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
bogdanm | 86:04dd9b1680ae | 220 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
bogdanm | 86:04dd9b1680ae | 221 | /** |
bogdanm | 86:04dd9b1680ae | 222 | * @} |
bogdanm | 86:04dd9b1680ae | 223 | */ |
bogdanm | 86:04dd9b1680ae | 224 | |
bogdanm | 92:4fc01daae5a5 | 225 | /** @defgroup DMA_mode DMA mode |
bogdanm | 86:04dd9b1680ae | 226 | * @{ |
bogdanm | 86:04dd9b1680ae | 227 | */ |
<> | 135:176b8275d35d | 228 | #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ |
<> | 135:176b8275d35d | 229 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
bogdanm | 86:04dd9b1680ae | 230 | /** |
bogdanm | 86:04dd9b1680ae | 231 | * @} |
bogdanm | 86:04dd9b1680ae | 232 | */ |
bogdanm | 86:04dd9b1680ae | 233 | |
bogdanm | 92:4fc01daae5a5 | 234 | /** @defgroup DMA_Priority_level DMA Priority level |
bogdanm | 86:04dd9b1680ae | 235 | * @{ |
bogdanm | 86:04dd9b1680ae | 236 | */ |
<> | 135:176b8275d35d | 237 | #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ |
bogdanm | 86:04dd9b1680ae | 238 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
bogdanm | 86:04dd9b1680ae | 239 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
bogdanm | 86:04dd9b1680ae | 240 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
bogdanm | 86:04dd9b1680ae | 241 | /** |
bogdanm | 86:04dd9b1680ae | 242 | * @} |
bogdanm | 86:04dd9b1680ae | 243 | */ |
bogdanm | 86:04dd9b1680ae | 244 | |
bogdanm | 86:04dd9b1680ae | 245 | |
bogdanm | 92:4fc01daae5a5 | 246 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
bogdanm | 86:04dd9b1680ae | 247 | * @{ |
bogdanm | 86:04dd9b1680ae | 248 | */ |
bogdanm | 86:04dd9b1680ae | 249 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
bogdanm | 86:04dd9b1680ae | 250 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
bogdanm | 86:04dd9b1680ae | 251 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
bogdanm | 86:04dd9b1680ae | 252 | /** |
bogdanm | 86:04dd9b1680ae | 253 | * @} |
bogdanm | 86:04dd9b1680ae | 254 | */ |
bogdanm | 86:04dd9b1680ae | 255 | |
bogdanm | 92:4fc01daae5a5 | 256 | /** @defgroup DMA_flag_definitions DMA flag definitions |
bogdanm | 86:04dd9b1680ae | 257 | * @{ |
bogdanm | 86:04dd9b1680ae | 258 | */ |
<> | 135:176b8275d35d | 259 | #define DMA_FLAG_GL1 (0x00000001U) |
<> | 135:176b8275d35d | 260 | #define DMA_FLAG_TC1 (0x00000002U) |
<> | 135:176b8275d35d | 261 | #define DMA_FLAG_HT1 (0x00000004U) |
<> | 135:176b8275d35d | 262 | #define DMA_FLAG_TE1 (0x00000008U) |
<> | 135:176b8275d35d | 263 | #define DMA_FLAG_GL2 (0x00000010U) |
<> | 135:176b8275d35d | 264 | #define DMA_FLAG_TC2 (0x00000020U) |
<> | 135:176b8275d35d | 265 | #define DMA_FLAG_HT2 (0x00000040U) |
<> | 135:176b8275d35d | 266 | #define DMA_FLAG_TE2 (0x00000080U) |
<> | 135:176b8275d35d | 267 | #define DMA_FLAG_GL3 (0x00000100U) |
<> | 135:176b8275d35d | 268 | #define DMA_FLAG_TC3 (0x00000200U) |
<> | 135:176b8275d35d | 269 | #define DMA_FLAG_HT3 (0x00000400U) |
<> | 135:176b8275d35d | 270 | #define DMA_FLAG_TE3 (0x00000800U) |
<> | 135:176b8275d35d | 271 | #define DMA_FLAG_GL4 (0x00001000U) |
<> | 135:176b8275d35d | 272 | #define DMA_FLAG_TC4 (0x00002000U) |
<> | 135:176b8275d35d | 273 | #define DMA_FLAG_HT4 (0x00004000U) |
<> | 135:176b8275d35d | 274 | #define DMA_FLAG_TE4 (0x00008000U) |
<> | 135:176b8275d35d | 275 | #define DMA_FLAG_GL5 (0x00010000U) |
<> | 135:176b8275d35d | 276 | #define DMA_FLAG_TC5 (0x00020000U) |
<> | 135:176b8275d35d | 277 | #define DMA_FLAG_HT5 (0x00040000U) |
<> | 135:176b8275d35d | 278 | #define DMA_FLAG_TE5 (0x00080000U) |
<> | 135:176b8275d35d | 279 | #define DMA_FLAG_GL6 (0x00100000U) |
<> | 135:176b8275d35d | 280 | #define DMA_FLAG_TC6 (0x00200000U) |
<> | 135:176b8275d35d | 281 | #define DMA_FLAG_HT6 (0x00400000U) |
<> | 135:176b8275d35d | 282 | #define DMA_FLAG_TE6 (0x00800000U) |
<> | 135:176b8275d35d | 283 | #define DMA_FLAG_GL7 (0x01000000U) |
<> | 135:176b8275d35d | 284 | #define DMA_FLAG_TC7 (0x02000000U) |
<> | 135:176b8275d35d | 285 | #define DMA_FLAG_HT7 (0x04000000U) |
<> | 135:176b8275d35d | 286 | #define DMA_FLAG_TE7 (0x08000000U) |
bogdanm | 86:04dd9b1680ae | 287 | /** |
bogdanm | 86:04dd9b1680ae | 288 | * @} |
bogdanm | 86:04dd9b1680ae | 289 | */ |
bogdanm | 86:04dd9b1680ae | 290 | |
bogdanm | 86:04dd9b1680ae | 291 | /** |
bogdanm | 86:04dd9b1680ae | 292 | * @} |
bogdanm | 86:04dd9b1680ae | 293 | */ |
bogdanm | 86:04dd9b1680ae | 294 | |
Kojto | 122:f9eeca106725 | 295 | |
Kojto | 122:f9eeca106725 | 296 | /* Exported macro ------------------------------------------------------------*/ |
bogdanm | 92:4fc01daae5a5 | 297 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
bogdanm | 92:4fc01daae5a5 | 298 | * @{ |
bogdanm | 92:4fc01daae5a5 | 299 | */ |
bogdanm | 86:04dd9b1680ae | 300 | |
bogdanm | 86:04dd9b1680ae | 301 | /** @brief Reset DMA handle state |
bogdanm | 86:04dd9b1680ae | 302 | * @param __HANDLE__: DMA handle. |
bogdanm | 86:04dd9b1680ae | 303 | * @retval None |
bogdanm | 86:04dd9b1680ae | 304 | */ |
bogdanm | 86:04dd9b1680ae | 305 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
bogdanm | 86:04dd9b1680ae | 306 | |
bogdanm | 86:04dd9b1680ae | 307 | /** |
bogdanm | 86:04dd9b1680ae | 308 | * @brief Enable the specified DMA Channel. |
bogdanm | 86:04dd9b1680ae | 309 | * @param __HANDLE__: DMA handle |
<> | 135:176b8275d35d | 310 | * @retval None |
bogdanm | 86:04dd9b1680ae | 311 | */ |
<> | 135:176b8275d35d | 312 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
bogdanm | 86:04dd9b1680ae | 313 | |
bogdanm | 86:04dd9b1680ae | 314 | /** |
bogdanm | 86:04dd9b1680ae | 315 | * @brief Disable the specified DMA Channel. |
bogdanm | 86:04dd9b1680ae | 316 | * @param __HANDLE__: DMA handle |
<> | 135:176b8275d35d | 317 | * @retval None |
bogdanm | 86:04dd9b1680ae | 318 | */ |
<> | 135:176b8275d35d | 319 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
bogdanm | 86:04dd9b1680ae | 320 | |
bogdanm | 86:04dd9b1680ae | 321 | |
bogdanm | 86:04dd9b1680ae | 322 | /* Interrupt & Flag management */ |
bogdanm | 86:04dd9b1680ae | 323 | |
bogdanm | 86:04dd9b1680ae | 324 | /** |
bogdanm | 86:04dd9b1680ae | 325 | * @brief Enables the specified DMA Channel interrupts. |
bogdanm | 86:04dd9b1680ae | 326 | * @param __HANDLE__: DMA handle |
bogdanm | 86:04dd9b1680ae | 327 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
bogdanm | 86:04dd9b1680ae | 328 | * This parameter can be any combination of the following values: |
bogdanm | 86:04dd9b1680ae | 329 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 330 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 331 | * @arg DMA_IT_TE: Transfer error interrupt mask |
bogdanm | 86:04dd9b1680ae | 332 | * @retval None |
bogdanm | 86:04dd9b1680ae | 333 | */ |
<> | 135:176b8275d35d | 334 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
bogdanm | 86:04dd9b1680ae | 335 | |
bogdanm | 86:04dd9b1680ae | 336 | /** |
bogdanm | 86:04dd9b1680ae | 337 | * @brief Disables the specified DMA Channel interrupts. |
bogdanm | 86:04dd9b1680ae | 338 | * @param __HANDLE__: DMA handle |
bogdanm | 86:04dd9b1680ae | 339 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
bogdanm | 86:04dd9b1680ae | 340 | * This parameter can be any combination of the following values: |
bogdanm | 86:04dd9b1680ae | 341 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 342 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 343 | * @arg DMA_IT_TE: Transfer error interrupt mask |
bogdanm | 86:04dd9b1680ae | 344 | * @retval None |
bogdanm | 86:04dd9b1680ae | 345 | */ |
<> | 135:176b8275d35d | 346 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
bogdanm | 86:04dd9b1680ae | 347 | |
bogdanm | 86:04dd9b1680ae | 348 | /** |
Kojto | 122:f9eeca106725 | 349 | * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. |
bogdanm | 86:04dd9b1680ae | 350 | * @param __HANDLE__: DMA handle |
bogdanm | 86:04dd9b1680ae | 351 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
bogdanm | 86:04dd9b1680ae | 352 | * This parameter can be one of the following values: |
bogdanm | 86:04dd9b1680ae | 353 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 354 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
bogdanm | 86:04dd9b1680ae | 355 | * @arg DMA_IT_TE: Transfer error interrupt mask |
bogdanm | 86:04dd9b1680ae | 356 | * @retval The state of DMA_IT (SET or RESET). |
bogdanm | 86:04dd9b1680ae | 357 | */ |
<> | 135:176b8275d35d | 358 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
bogdanm | 86:04dd9b1680ae | 359 | |
bogdanm | 92:4fc01daae5a5 | 360 | /** |
Kojto | 122:f9eeca106725 | 361 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
Kojto | 122:f9eeca106725 | 362 | * @param __HANDLE__: DMA handle |
Kojto | 122:f9eeca106725 | 363 | * |
Kojto | 122:f9eeca106725 | 364 | * @retval The number of remaining data units in the current DMA Channel transfer. |
Kojto | 122:f9eeca106725 | 365 | */ |
Kojto | 122:f9eeca106725 | 366 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
Kojto | 122:f9eeca106725 | 367 | |
Kojto | 122:f9eeca106725 | 368 | /** |
bogdanm | 92:4fc01daae5a5 | 369 | * @} |
bogdanm | 92:4fc01daae5a5 | 370 | */ |
bogdanm | 92:4fc01daae5a5 | 371 | |
bogdanm | 92:4fc01daae5a5 | 372 | /* Include DMA HAL Extended module */ |
bogdanm | 86:04dd9b1680ae | 373 | #include "stm32f3xx_hal_dma_ex.h" |
bogdanm | 86:04dd9b1680ae | 374 | |
bogdanm | 86:04dd9b1680ae | 375 | /* Exported functions --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 376 | /** @addtogroup DMA_Exported_Functions |
bogdanm | 92:4fc01daae5a5 | 377 | * @{ |
bogdanm | 92:4fc01daae5a5 | 378 | */ |
bogdanm | 92:4fc01daae5a5 | 379 | |
bogdanm | 92:4fc01daae5a5 | 380 | /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
bogdanm | 92:4fc01daae5a5 | 381 | * @{ |
bogdanm | 92:4fc01daae5a5 | 382 | */ |
bogdanm | 86:04dd9b1680ae | 383 | /* Initialization and de-initialization functions *****************************/ |
Kojto | 122:f9eeca106725 | 384 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
bogdanm | 86:04dd9b1680ae | 385 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
bogdanm | 92:4fc01daae5a5 | 386 | /** |
bogdanm | 92:4fc01daae5a5 | 387 | * @} |
bogdanm | 92:4fc01daae5a5 | 388 | */ |
bogdanm | 92:4fc01daae5a5 | 389 | |
bogdanm | 92:4fc01daae5a5 | 390 | /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions |
bogdanm | 92:4fc01daae5a5 | 391 | * @{ |
bogdanm | 92:4fc01daae5a5 | 392 | */ |
<> | 135:176b8275d35d | 393 | /* Input and Output operation functions *****************************************************/ |
bogdanm | 86:04dd9b1680ae | 394 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
bogdanm | 86:04dd9b1680ae | 395 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
bogdanm | 86:04dd9b1680ae | 396 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
Kojto | 122:f9eeca106725 | 397 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
bogdanm | 86:04dd9b1680ae | 398 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
bogdanm | 86:04dd9b1680ae | 399 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
<> | 135:176b8275d35d | 400 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
<> | 135:176b8275d35d | 401 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
bogdanm | 92:4fc01daae5a5 | 402 | /** |
bogdanm | 92:4fc01daae5a5 | 403 | * @} |
bogdanm | 92:4fc01daae5a5 | 404 | */ |
bogdanm | 92:4fc01daae5a5 | 405 | |
bogdanm | 92:4fc01daae5a5 | 406 | /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions |
bogdanm | 92:4fc01daae5a5 | 407 | * @{ |
bogdanm | 92:4fc01daae5a5 | 408 | */ |
bogdanm | 86:04dd9b1680ae | 409 | /* Peripheral State and Error functions ***************************************/ |
bogdanm | 86:04dd9b1680ae | 410 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
bogdanm | 86:04dd9b1680ae | 411 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
bogdanm | 86:04dd9b1680ae | 412 | /** |
bogdanm | 86:04dd9b1680ae | 413 | * @} |
bogdanm | 92:4fc01daae5a5 | 414 | */ |
bogdanm | 92:4fc01daae5a5 | 415 | |
bogdanm | 92:4fc01daae5a5 | 416 | /** |
bogdanm | 92:4fc01daae5a5 | 417 | * @} |
bogdanm | 92:4fc01daae5a5 | 418 | */ |
Kojto | 122:f9eeca106725 | 419 | /* Private macros ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 420 | /** @defgroup DMA_Private_Macros DMA Private Macros |
Kojto | 122:f9eeca106725 | 421 | * @brief DMA private macros |
Kojto | 122:f9eeca106725 | 422 | * @{ |
Kojto | 122:f9eeca106725 | 423 | */ |
Kojto | 122:f9eeca106725 | 424 | |
<> | 135:176b8275d35d | 425 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
Kojto | 122:f9eeca106725 | 426 | |
Kojto | 122:f9eeca106725 | 427 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
Kojto | 122:f9eeca106725 | 428 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
Kojto | 122:f9eeca106725 | 429 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
Kojto | 122:f9eeca106725 | 430 | |
Kojto | 122:f9eeca106725 | 431 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 432 | ((STATE) == DMA_PINC_DISABLE)) |
Kojto | 122:f9eeca106725 | 433 | |
Kojto | 122:f9eeca106725 | 434 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 435 | ((STATE) == DMA_MINC_DISABLE)) |
Kojto | 122:f9eeca106725 | 436 | |
Kojto | 122:f9eeca106725 | 437 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
Kojto | 122:f9eeca106725 | 438 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
Kojto | 122:f9eeca106725 | 439 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
Kojto | 122:f9eeca106725 | 440 | |
Kojto | 122:f9eeca106725 | 441 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
Kojto | 122:f9eeca106725 | 442 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
Kojto | 122:f9eeca106725 | 443 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
Kojto | 122:f9eeca106725 | 444 | |
Kojto | 122:f9eeca106725 | 445 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
Kojto | 122:f9eeca106725 | 446 | ((MODE) == DMA_CIRCULAR)) |
Kojto | 122:f9eeca106725 | 447 | |
Kojto | 122:f9eeca106725 | 448 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
Kojto | 122:f9eeca106725 | 449 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
Kojto | 122:f9eeca106725 | 450 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
Kojto | 122:f9eeca106725 | 451 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
Kojto | 122:f9eeca106725 | 452 | |
Kojto | 122:f9eeca106725 | 453 | /** |
Kojto | 122:f9eeca106725 | 454 | * @} |
Kojto | 122:f9eeca106725 | 455 | */ |
Kojto | 122:f9eeca106725 | 456 | |
bogdanm | 92:4fc01daae5a5 | 457 | |
bogdanm | 92:4fc01daae5a5 | 458 | /** |
bogdanm | 92:4fc01daae5a5 | 459 | * @} |
bogdanm | 86:04dd9b1680ae | 460 | */ |
bogdanm | 86:04dd9b1680ae | 461 | |
bogdanm | 86:04dd9b1680ae | 462 | /** |
bogdanm | 86:04dd9b1680ae | 463 | * @} |
bogdanm | 86:04dd9b1680ae | 464 | */ |
bogdanm | 86:04dd9b1680ae | 465 | |
bogdanm | 86:04dd9b1680ae | 466 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 467 | } |
bogdanm | 86:04dd9b1680ae | 468 | #endif |
bogdanm | 86:04dd9b1680ae | 469 | |
bogdanm | 86:04dd9b1680ae | 470 | #endif /* __STM32F3xx_HAL_DMA_H */ |
bogdanm | 86:04dd9b1680ae | 471 | |
bogdanm | 86:04dd9b1680ae | 472 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |