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TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 14 11:24:20 2017 +0000
- Revision:
- 136:ef9c61f8c49f
- Parent:
- 135:176b8275d35d
Release 136 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 86:04dd9b1680ae | 1 | /** |
bogdanm | 86:04dd9b1680ae | 2 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 3 | * @file stm32f3xx_hal_cortex.h |
bogdanm | 86:04dd9b1680ae | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
bogdanm | 86:04dd9b1680ae | 7 | * @brief Header file of CORTEX HAL module. |
bogdanm | 86:04dd9b1680ae | 8 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 9 | * @attention |
bogdanm | 86:04dd9b1680ae | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
bogdanm | 86:04dd9b1680ae | 12 | * |
bogdanm | 86:04dd9b1680ae | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 86:04dd9b1680ae | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 86:04dd9b1680ae | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 86:04dd9b1680ae | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 86:04dd9b1680ae | 19 | * and/or other materials provided with the distribution. |
bogdanm | 86:04dd9b1680ae | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 86:04dd9b1680ae | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 86:04dd9b1680ae | 22 | * without specific prior written permission. |
bogdanm | 86:04dd9b1680ae | 23 | * |
bogdanm | 86:04dd9b1680ae | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 86:04dd9b1680ae | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 86:04dd9b1680ae | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 86:04dd9b1680ae | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 86:04dd9b1680ae | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 86:04dd9b1680ae | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 86:04dd9b1680ae | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 86:04dd9b1680ae | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 86:04dd9b1680ae | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 86:04dd9b1680ae | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 86:04dd9b1680ae | 34 | * |
bogdanm | 86:04dd9b1680ae | 35 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 36 | */ |
bogdanm | 86:04dd9b1680ae | 37 | |
bogdanm | 86:04dd9b1680ae | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 39 | #ifndef __STM32F3xx_HAL_CORTEX_H |
bogdanm | 86:04dd9b1680ae | 40 | #define __STM32F3xx_HAL_CORTEX_H |
bogdanm | 86:04dd9b1680ae | 41 | |
bogdanm | 86:04dd9b1680ae | 42 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 43 | extern "C" { |
bogdanm | 86:04dd9b1680ae | 44 | #endif |
bogdanm | 86:04dd9b1680ae | 45 | |
bogdanm | 86:04dd9b1680ae | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 47 | #include "stm32f3xx_hal_def.h" |
bogdanm | 86:04dd9b1680ae | 48 | |
bogdanm | 86:04dd9b1680ae | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
bogdanm | 86:04dd9b1680ae | 50 | * @{ |
bogdanm | 86:04dd9b1680ae | 51 | */ |
bogdanm | 86:04dd9b1680ae | 52 | |
bogdanm | 86:04dd9b1680ae | 53 | /** @addtogroup CORTEX |
bogdanm | 86:04dd9b1680ae | 54 | * @{ |
bogdanm | 86:04dd9b1680ae | 55 | */ |
bogdanm | 86:04dd9b1680ae | 56 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 57 | /** @defgroup CORTEX_Exported_Types CORTEX Exported Types |
Kojto | 122:f9eeca106725 | 58 | * @{ |
Kojto | 122:f9eeca106725 | 59 | */ |
Kojto | 122:f9eeca106725 | 60 | |
<> | 135:176b8275d35d | 61 | #if (__MPU_PRESENT == 1U) |
Kojto | 122:f9eeca106725 | 62 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
Kojto | 122:f9eeca106725 | 63 | * @brief MPU Region initialization structure |
Kojto | 122:f9eeca106725 | 64 | * @{ |
Kojto | 122:f9eeca106725 | 65 | */ |
Kojto | 122:f9eeca106725 | 66 | typedef struct |
Kojto | 122:f9eeca106725 | 67 | { |
Kojto | 122:f9eeca106725 | 68 | uint8_t Enable; /*!< Specifies the status of the region. |
Kojto | 122:f9eeca106725 | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
Kojto | 122:f9eeca106725 | 70 | uint8_t Number; /*!< Specifies the number of the region to protect. |
Kojto | 122:f9eeca106725 | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
Kojto | 122:f9eeca106725 | 72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
Kojto | 122:f9eeca106725 | 73 | uint8_t Size; /*!< Specifies the size of the region to protect. |
Kojto | 122:f9eeca106725 | 74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
Kojto | 122:f9eeca106725 | 75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
Kojto | 122:f9eeca106725 | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
Kojto | 122:f9eeca106725 | 77 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
Kojto | 122:f9eeca106725 | 78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
Kojto | 122:f9eeca106725 | 79 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
Kojto | 122:f9eeca106725 | 80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
Kojto | 122:f9eeca106725 | 81 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
Kojto | 122:f9eeca106725 | 82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
Kojto | 122:f9eeca106725 | 83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
Kojto | 122:f9eeca106725 | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
Kojto | 122:f9eeca106725 | 85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
Kojto | 122:f9eeca106725 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
Kojto | 122:f9eeca106725 | 87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
Kojto | 122:f9eeca106725 | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
Kojto | 122:f9eeca106725 | 89 | }MPU_Region_InitTypeDef; |
Kojto | 122:f9eeca106725 | 90 | /** |
Kojto | 122:f9eeca106725 | 91 | * @} |
Kojto | 122:f9eeca106725 | 92 | */ |
Kojto | 122:f9eeca106725 | 93 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 94 | |
Kojto | 122:f9eeca106725 | 95 | /** |
Kojto | 122:f9eeca106725 | 96 | * @} |
Kojto | 122:f9eeca106725 | 97 | */ |
Kojto | 122:f9eeca106725 | 98 | |
bogdanm | 86:04dd9b1680ae | 99 | /* Exported constants --------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 100 | |
bogdanm | 92:4fc01daae5a5 | 101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
bogdanm | 86:04dd9b1680ae | 102 | * @{ |
bogdanm | 86:04dd9b1680ae | 103 | */ |
bogdanm | 86:04dd9b1680ae | 104 | |
bogdanm | 92:4fc01daae5a5 | 105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
bogdanm | 86:04dd9b1680ae | 106 | * @{ |
bogdanm | 86:04dd9b1680ae | 107 | */ |
<> | 135:176b8275d35d | 108 | #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority |
bogdanm | 86:04dd9b1680ae | 109 | 4 bits for subpriority */ |
<> | 135:176b8275d35d | 110 | #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority |
bogdanm | 86:04dd9b1680ae | 111 | 3 bits for subpriority */ |
<> | 135:176b8275d35d | 112 | #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority |
bogdanm | 86:04dd9b1680ae | 113 | 2 bits for subpriority */ |
<> | 135:176b8275d35d | 114 | #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority |
bogdanm | 86:04dd9b1680ae | 115 | 1 bits for subpriority */ |
<> | 135:176b8275d35d | 116 | #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority |
bogdanm | 86:04dd9b1680ae | 117 | 0 bits for subpriority */ |
Kojto | 122:f9eeca106725 | 118 | /** |
Kojto | 122:f9eeca106725 | 119 | * @} |
Kojto | 122:f9eeca106725 | 120 | */ |
bogdanm | 86:04dd9b1680ae | 121 | |
Kojto | 122:f9eeca106725 | 122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source |
Kojto | 122:f9eeca106725 | 123 | * @{ |
Kojto | 122:f9eeca106725 | 124 | */ |
<> | 135:176b8275d35d | 125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) |
<> | 135:176b8275d35d | 126 | #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) |
Kojto | 122:f9eeca106725 | 127 | /** |
Kojto | 122:f9eeca106725 | 128 | * @} |
Kojto | 122:f9eeca106725 | 129 | */ |
Kojto | 122:f9eeca106725 | 130 | |
<> | 135:176b8275d35d | 131 | #if (__MPU_PRESENT == 1U) |
Kojto | 122:f9eeca106725 | 132 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
Kojto | 122:f9eeca106725 | 133 | * @{ |
Kojto | 122:f9eeca106725 | 134 | */ |
<> | 135:176b8275d35d | 135 | #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) |
<> | 135:176b8275d35d | 136 | #define MPU_HARDFAULT_NMI (0x00000002U) |
<> | 135:176b8275d35d | 137 | #define MPU_PRIVILEGED_DEFAULT (0x00000004U) |
<> | 135:176b8275d35d | 138 | #define MPU_HFNMI_PRIVDEF (0x00000006U) |
Kojto | 122:f9eeca106725 | 139 | /** |
Kojto | 122:f9eeca106725 | 140 | * @} |
Kojto | 122:f9eeca106725 | 141 | */ |
Kojto | 122:f9eeca106725 | 142 | |
Kojto | 122:f9eeca106725 | 143 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
Kojto | 122:f9eeca106725 | 144 | * @{ |
Kojto | 122:f9eeca106725 | 145 | */ |
<> | 135:176b8275d35d | 146 | #define MPU_REGION_ENABLE ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 147 | #define MPU_REGION_DISABLE ((uint8_t)0x00U) |
Kojto | 122:f9eeca106725 | 148 | /** |
Kojto | 122:f9eeca106725 | 149 | * @} |
Kojto | 122:f9eeca106725 | 150 | */ |
bogdanm | 86:04dd9b1680ae | 151 | |
Kojto | 122:f9eeca106725 | 152 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
Kojto | 122:f9eeca106725 | 153 | * @{ |
Kojto | 122:f9eeca106725 | 154 | */ |
<> | 135:176b8275d35d | 155 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) |
<> | 135:176b8275d35d | 156 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) |
Kojto | 122:f9eeca106725 | 157 | /** |
Kojto | 122:f9eeca106725 | 158 | * @} |
Kojto | 122:f9eeca106725 | 159 | */ |
bogdanm | 86:04dd9b1680ae | 160 | |
Kojto | 122:f9eeca106725 | 161 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
Kojto | 122:f9eeca106725 | 162 | * @{ |
Kojto | 122:f9eeca106725 | 163 | */ |
<> | 135:176b8275d35d | 164 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 165 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) |
Kojto | 122:f9eeca106725 | 166 | /** |
Kojto | 122:f9eeca106725 | 167 | * @} |
Kojto | 122:f9eeca106725 | 168 | */ |
bogdanm | 86:04dd9b1680ae | 169 | |
Kojto | 122:f9eeca106725 | 170 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
Kojto | 122:f9eeca106725 | 171 | * @{ |
Kojto | 122:f9eeca106725 | 172 | */ |
<> | 135:176b8275d35d | 173 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 174 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) |
Kojto | 122:f9eeca106725 | 175 | /** |
Kojto | 122:f9eeca106725 | 176 | * @} |
Kojto | 122:f9eeca106725 | 177 | */ |
Kojto | 122:f9eeca106725 | 178 | |
Kojto | 122:f9eeca106725 | 179 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
Kojto | 122:f9eeca106725 | 180 | * @{ |
Kojto | 122:f9eeca106725 | 181 | */ |
<> | 135:176b8275d35d | 182 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 183 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) |
bogdanm | 86:04dd9b1680ae | 184 | /** |
bogdanm | 86:04dd9b1680ae | 185 | * @} |
bogdanm | 86:04dd9b1680ae | 186 | */ |
bogdanm | 86:04dd9b1680ae | 187 | |
Kojto | 122:f9eeca106725 | 188 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
bogdanm | 86:04dd9b1680ae | 189 | * @{ |
bogdanm | 86:04dd9b1680ae | 190 | */ |
<> | 135:176b8275d35d | 191 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00U) |
<> | 135:176b8275d35d | 192 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 193 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02U) |
bogdanm | 86:04dd9b1680ae | 194 | /** |
bogdanm | 86:04dd9b1680ae | 195 | * @} |
bogdanm | 86:04dd9b1680ae | 196 | */ |
bogdanm | 86:04dd9b1680ae | 197 | |
Kojto | 122:f9eeca106725 | 198 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
Kojto | 122:f9eeca106725 | 199 | * @{ |
Kojto | 122:f9eeca106725 | 200 | */ |
<> | 135:176b8275d35d | 201 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) |
<> | 135:176b8275d35d | 202 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) |
<> | 135:176b8275d35d | 203 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) |
<> | 135:176b8275d35d | 204 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) |
<> | 135:176b8275d35d | 205 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) |
<> | 135:176b8275d35d | 206 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) |
<> | 135:176b8275d35d | 207 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) |
<> | 135:176b8275d35d | 208 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) |
<> | 135:176b8275d35d | 209 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) |
<> | 135:176b8275d35d | 210 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) |
<> | 135:176b8275d35d | 211 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) |
<> | 135:176b8275d35d | 212 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) |
<> | 135:176b8275d35d | 213 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) |
<> | 135:176b8275d35d | 214 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) |
<> | 135:176b8275d35d | 215 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) |
<> | 135:176b8275d35d | 216 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) |
<> | 135:176b8275d35d | 217 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) |
<> | 135:176b8275d35d | 218 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) |
<> | 135:176b8275d35d | 219 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) |
<> | 135:176b8275d35d | 220 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) |
<> | 135:176b8275d35d | 221 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) |
<> | 135:176b8275d35d | 222 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) |
<> | 135:176b8275d35d | 223 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) |
<> | 135:176b8275d35d | 224 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) |
<> | 135:176b8275d35d | 225 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) |
<> | 135:176b8275d35d | 226 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) |
<> | 135:176b8275d35d | 227 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) |
<> | 135:176b8275d35d | 228 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) |
Kojto | 122:f9eeca106725 | 229 | /** |
Kojto | 122:f9eeca106725 | 230 | * @} |
Kojto | 122:f9eeca106725 | 231 | */ |
Kojto | 122:f9eeca106725 | 232 | |
Kojto | 122:f9eeca106725 | 233 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
Kojto | 122:f9eeca106725 | 234 | * @{ |
Kojto | 122:f9eeca106725 | 235 | */ |
<> | 135:176b8275d35d | 236 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) |
<> | 135:176b8275d35d | 237 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 238 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) |
<> | 135:176b8275d35d | 239 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) |
<> | 135:176b8275d35d | 240 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) |
<> | 135:176b8275d35d | 241 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) |
Kojto | 122:f9eeca106725 | 242 | /** |
Kojto | 122:f9eeca106725 | 243 | * @} |
Kojto | 122:f9eeca106725 | 244 | */ |
Kojto | 122:f9eeca106725 | 245 | |
Kojto | 122:f9eeca106725 | 246 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
Kojto | 122:f9eeca106725 | 247 | * @{ |
Kojto | 122:f9eeca106725 | 248 | */ |
<> | 135:176b8275d35d | 249 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) |
<> | 135:176b8275d35d | 250 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) |
<> | 135:176b8275d35d | 251 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) |
<> | 135:176b8275d35d | 252 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) |
<> | 135:176b8275d35d | 253 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) |
<> | 135:176b8275d35d | 254 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) |
<> | 135:176b8275d35d | 255 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) |
<> | 135:176b8275d35d | 256 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) |
Kojto | 122:f9eeca106725 | 257 | /** |
Kojto | 122:f9eeca106725 | 258 | * @} |
Kojto | 122:f9eeca106725 | 259 | */ |
Kojto | 122:f9eeca106725 | 260 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 261 | |
bogdanm | 86:04dd9b1680ae | 262 | /** |
bogdanm | 86:04dd9b1680ae | 263 | * @} |
bogdanm | 86:04dd9b1680ae | 264 | */ |
bogdanm | 86:04dd9b1680ae | 265 | |
Kojto | 122:f9eeca106725 | 266 | /* Exported Macros -----------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 267 | |
Kojto | 122:f9eeca106725 | 268 | |
Kojto | 122:f9eeca106725 | 269 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 270 | /** @addtogroup CORTEX_Exported_Functions |
bogdanm | 92:4fc01daae5a5 | 271 | * @{ |
bogdanm | 92:4fc01daae5a5 | 272 | */ |
Kojto | 122:f9eeca106725 | 273 | |
Kojto | 122:f9eeca106725 | 274 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
bogdanm | 92:4fc01daae5a5 | 275 | * @{ |
bogdanm | 92:4fc01daae5a5 | 276 | */ |
bogdanm | 86:04dd9b1680ae | 277 | /* Initialization and de-initialization functions *****************************/ |
bogdanm | 86:04dd9b1680ae | 278 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
bogdanm | 86:04dd9b1680ae | 279 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
bogdanm | 86:04dd9b1680ae | 280 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 281 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 282 | void HAL_NVIC_SystemReset(void); |
bogdanm | 86:04dd9b1680ae | 283 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
bogdanm | 92:4fc01daae5a5 | 284 | /** |
bogdanm | 92:4fc01daae5a5 | 285 | * @} |
bogdanm | 92:4fc01daae5a5 | 286 | */ |
bogdanm | 92:4fc01daae5a5 | 287 | |
Kojto | 122:f9eeca106725 | 288 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
bogdanm | 92:4fc01daae5a5 | 289 | * @{ |
bogdanm | 92:4fc01daae5a5 | 290 | */ |
bogdanm | 86:04dd9b1680ae | 291 | /* Peripheral Control functions ***********************************************/ |
<> | 135:176b8275d35d | 292 | #if (__MPU_PRESENT == 1U) |
Kojto | 122:f9eeca106725 | 293 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
Kojto | 122:f9eeca106725 | 294 | #endif /* __MPU_PRESENT */ |
bogdanm | 86:04dd9b1680ae | 295 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
bogdanm | 86:04dd9b1680ae | 296 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
bogdanm | 86:04dd9b1680ae | 297 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 298 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 299 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 300 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
bogdanm | 86:04dd9b1680ae | 301 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
bogdanm | 86:04dd9b1680ae | 302 | void HAL_SYSTICK_IRQHandler(void); |
bogdanm | 86:04dd9b1680ae | 303 | void HAL_SYSTICK_Callback(void); |
bogdanm | 92:4fc01daae5a5 | 304 | /** |
bogdanm | 92:4fc01daae5a5 | 305 | * @} |
Kojto | 122:f9eeca106725 | 306 | */ |
Kojto | 122:f9eeca106725 | 307 | |
Kojto | 122:f9eeca106725 | 308 | /** |
Kojto | 122:f9eeca106725 | 309 | * @} |
bogdanm | 92:4fc01daae5a5 | 310 | */ |
bogdanm | 92:4fc01daae5a5 | 311 | |
Kojto | 122:f9eeca106725 | 312 | /* Private types -------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 313 | /* Private variables ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 314 | /* Private constants ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 315 | /* Private macros ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 316 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
Kojto | 122:f9eeca106725 | 317 | * @{ |
Kojto | 122:f9eeca106725 | 318 | */ |
Kojto | 122:f9eeca106725 | 319 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
Kojto | 122:f9eeca106725 | 320 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
Kojto | 122:f9eeca106725 | 321 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
Kojto | 122:f9eeca106725 | 322 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
Kojto | 122:f9eeca106725 | 323 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
Kojto | 122:f9eeca106725 | 324 | |
<> | 135:176b8275d35d | 325 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
Kojto | 122:f9eeca106725 | 326 | |
<> | 135:176b8275d35d | 327 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
Kojto | 122:f9eeca106725 | 328 | |
Kojto | 122:f9eeca106725 | 329 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
Kojto | 122:f9eeca106725 | 330 | |
Kojto | 122:f9eeca106725 | 331 | /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source |
Kojto | 122:f9eeca106725 | 332 | * @{ |
Kojto | 122:f9eeca106725 | 333 | */ |
Kojto | 122:f9eeca106725 | 334 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
Kojto | 122:f9eeca106725 | 335 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
Kojto | 122:f9eeca106725 | 336 | /** |
Kojto | 122:f9eeca106725 | 337 | * @} |
Kojto | 122:f9eeca106725 | 338 | */ |
Kojto | 122:f9eeca106725 | 339 | |
<> | 135:176b8275d35d | 340 | #if (__MPU_PRESENT == 1U) |
Kojto | 122:f9eeca106725 | 341 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 342 | ((STATE) == MPU_REGION_DISABLE)) |
Kojto | 122:f9eeca106725 | 343 | |
Kojto | 122:f9eeca106725 | 344 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 345 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
Kojto | 122:f9eeca106725 | 346 | |
Kojto | 122:f9eeca106725 | 347 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
Kojto | 122:f9eeca106725 | 348 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
Kojto | 122:f9eeca106725 | 349 | |
Kojto | 122:f9eeca106725 | 350 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
Kojto | 122:f9eeca106725 | 351 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
Kojto | 122:f9eeca106725 | 352 | |
Kojto | 122:f9eeca106725 | 353 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
Kojto | 122:f9eeca106725 | 354 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
Kojto | 122:f9eeca106725 | 355 | |
Kojto | 122:f9eeca106725 | 356 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
Kojto | 122:f9eeca106725 | 357 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
Kojto | 122:f9eeca106725 | 358 | ((TYPE) == MPU_TEX_LEVEL2)) |
Kojto | 122:f9eeca106725 | 359 | |
Kojto | 122:f9eeca106725 | 360 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
Kojto | 122:f9eeca106725 | 361 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
Kojto | 122:f9eeca106725 | 362 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
Kojto | 122:f9eeca106725 | 363 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
Kojto | 122:f9eeca106725 | 364 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
Kojto | 122:f9eeca106725 | 365 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
Kojto | 122:f9eeca106725 | 366 | |
Kojto | 122:f9eeca106725 | 367 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
Kojto | 122:f9eeca106725 | 368 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
Kojto | 122:f9eeca106725 | 369 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
Kojto | 122:f9eeca106725 | 370 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
Kojto | 122:f9eeca106725 | 371 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
Kojto | 122:f9eeca106725 | 372 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
Kojto | 122:f9eeca106725 | 373 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
Kojto | 122:f9eeca106725 | 374 | ((NUMBER) == MPU_REGION_NUMBER7)) |
Kojto | 122:f9eeca106725 | 375 | |
Kojto | 122:f9eeca106725 | 376 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
Kojto | 122:f9eeca106725 | 377 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
Kojto | 122:f9eeca106725 | 378 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
Kojto | 122:f9eeca106725 | 379 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
Kojto | 122:f9eeca106725 | 380 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
Kojto | 122:f9eeca106725 | 381 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
Kojto | 122:f9eeca106725 | 382 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
Kojto | 122:f9eeca106725 | 383 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
Kojto | 122:f9eeca106725 | 384 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
Kojto | 122:f9eeca106725 | 385 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
Kojto | 122:f9eeca106725 | 386 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
Kojto | 122:f9eeca106725 | 387 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
Kojto | 122:f9eeca106725 | 388 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
Kojto | 122:f9eeca106725 | 389 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
Kojto | 122:f9eeca106725 | 390 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
Kojto | 122:f9eeca106725 | 391 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
Kojto | 122:f9eeca106725 | 392 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
Kojto | 122:f9eeca106725 | 393 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
Kojto | 122:f9eeca106725 | 394 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
Kojto | 122:f9eeca106725 | 395 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
Kojto | 122:f9eeca106725 | 396 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
Kojto | 122:f9eeca106725 | 397 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
Kojto | 122:f9eeca106725 | 398 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
Kojto | 122:f9eeca106725 | 399 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
Kojto | 122:f9eeca106725 | 400 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
Kojto | 122:f9eeca106725 | 401 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
Kojto | 122:f9eeca106725 | 402 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
Kojto | 122:f9eeca106725 | 403 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
Kojto | 122:f9eeca106725 | 404 | |
<> | 135:176b8275d35d | 405 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) |
Kojto | 122:f9eeca106725 | 406 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 407 | |
Kojto | 122:f9eeca106725 | 408 | /** |
Kojto | 122:f9eeca106725 | 409 | * @} |
Kojto | 122:f9eeca106725 | 410 | */ |
Kojto | 122:f9eeca106725 | 411 | |
Kojto | 122:f9eeca106725 | 412 | /* Private functions ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 413 | /** @defgroup CORTEX_Private_Functions CORTEX Private Functions |
Kojto | 122:f9eeca106725 | 414 | * @brief CORTEX private functions |
Kojto | 122:f9eeca106725 | 415 | * @{ |
Kojto | 122:f9eeca106725 | 416 | */ |
Kojto | 122:f9eeca106725 | 417 | |
<> | 135:176b8275d35d | 418 | #if (__MPU_PRESENT == 1U) |
Kojto | 122:f9eeca106725 | 419 | |
<> | 135:176b8275d35d | 420 | void HAL_MPU_Disable(void); |
<> | 135:176b8275d35d | 421 | void HAL_MPU_Enable(uint32_t MPU_Control); |
<> | 135:176b8275d35d | 422 | |
Kojto | 122:f9eeca106725 | 423 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 424 | |
bogdanm | 92:4fc01daae5a5 | 425 | /** |
bogdanm | 92:4fc01daae5a5 | 426 | * @} |
bogdanm | 92:4fc01daae5a5 | 427 | */ |
bogdanm | 86:04dd9b1680ae | 428 | |
bogdanm | 86:04dd9b1680ae | 429 | /** |
bogdanm | 86:04dd9b1680ae | 430 | * @} |
bogdanm | 86:04dd9b1680ae | 431 | */ |
bogdanm | 86:04dd9b1680ae | 432 | |
bogdanm | 86:04dd9b1680ae | 433 | /** |
bogdanm | 86:04dd9b1680ae | 434 | * @} |
bogdanm | 86:04dd9b1680ae | 435 | */ |
bogdanm | 86:04dd9b1680ae | 436 | |
bogdanm | 86:04dd9b1680ae | 437 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 438 | } |
bogdanm | 86:04dd9b1680ae | 439 | #endif |
bogdanm | 86:04dd9b1680ae | 440 | |
bogdanm | 86:04dd9b1680ae | 441 | #endif /* __STM32F3xx_HAL_CORTEX_H */ |
bogdanm | 86:04dd9b1680ae | 442 | |
bogdanm | 86:04dd9b1680ae | 443 | |
bogdanm | 86:04dd9b1680ae | 444 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |