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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_wwdg.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_ll_wwdg.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of WWDG LL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_LL_WWDG_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_LL_WWDG_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_LL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #if defined (WWDG)
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @defgroup WWDG_LL WWDG
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /* Private types -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 60 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 67 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 68 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
<> 128:9bcdf88f62b0 69 * @{
<> 128:9bcdf88f62b0 70 */
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72
<> 128:9bcdf88f62b0 73 /** @defgroup WWDG_LL_EC_IT IT Defines
<> 128:9bcdf88f62b0 74 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
<> 128:9bcdf88f62b0 75 * @{
<> 128:9bcdf88f62b0 76 */
<> 128:9bcdf88f62b0 77 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
<> 128:9bcdf88f62b0 78 /**
<> 128:9bcdf88f62b0 79 * @}
<> 128:9bcdf88f62b0 80 */
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
<> 128:9bcdf88f62b0 83 * @{
<> 128:9bcdf88f62b0 84 */
<> 128:9bcdf88f62b0 85 #define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
<> 128:9bcdf88f62b0 86 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
<> 128:9bcdf88f62b0 87 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
<> 128:9bcdf88f62b0 88 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
<> 128:9bcdf88f62b0 89 /**
<> 128:9bcdf88f62b0 90 * @}
<> 128:9bcdf88f62b0 91 */
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 /**
<> 128:9bcdf88f62b0 94 * @}
<> 128:9bcdf88f62b0 95 */
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 98 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
<> 128:9bcdf88f62b0 99 * @{
<> 128:9bcdf88f62b0 100 */
<> 128:9bcdf88f62b0 101 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
<> 128:9bcdf88f62b0 102 * @{
<> 128:9bcdf88f62b0 103 */
<> 128:9bcdf88f62b0 104 /**
<> 128:9bcdf88f62b0 105 * @brief Write a value in WWDG register
<> 128:9bcdf88f62b0 106 * @param __INSTANCE__ WWDG Instance
<> 128:9bcdf88f62b0 107 * @param __REG__ Register to be written
<> 128:9bcdf88f62b0 108 * @param __VALUE__ Value to be written in the register
<> 128:9bcdf88f62b0 109 * @retval None
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /**
<> 128:9bcdf88f62b0 114 * @brief Read a value in WWDG register
<> 128:9bcdf88f62b0 115 * @param __INSTANCE__ WWDG Instance
<> 128:9bcdf88f62b0 116 * @param __REG__ Register to be read
<> 128:9bcdf88f62b0 117 * @retval Register value
<> 128:9bcdf88f62b0 118 */
<> 128:9bcdf88f62b0 119 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 128:9bcdf88f62b0 120 /**
<> 128:9bcdf88f62b0 121 * @}
<> 128:9bcdf88f62b0 122 */
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /**
<> 128:9bcdf88f62b0 126 * @}
<> 128:9bcdf88f62b0 127 */
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 130 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
<> 128:9bcdf88f62b0 131 * @{
<> 128:9bcdf88f62b0 132 */
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 /** @defgroup WWDG_LL_EF_Configuration Configuration
<> 128:9bcdf88f62b0 135 * @{
<> 128:9bcdf88f62b0 136 */
<> 128:9bcdf88f62b0 137 /**
<> 128:9bcdf88f62b0 138 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
<> 128:9bcdf88f62b0 139 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
<> 128:9bcdf88f62b0 140 * then it cannot be disabled again except by a reset.
<> 128:9bcdf88f62b0 141 * This bit is set by software and only cleared by hardware after a reset.
<> 128:9bcdf88f62b0 142 * When WDGA = 1, the watchdog can generate a reset.
<> 128:9bcdf88f62b0 143 * @rmtoll CR WDGA LL_WWDG_Enable
<> 128:9bcdf88f62b0 144 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 145 * @retval None
<> 128:9bcdf88f62b0 146 */
<> 128:9bcdf88f62b0 147 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 148 {
<> 128:9bcdf88f62b0 149 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
<> 128:9bcdf88f62b0 150 }
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /**
<> 128:9bcdf88f62b0 153 * @brief Checks if Window Watchdog is enabled
<> 128:9bcdf88f62b0 154 * @rmtoll CR WDGA LL_WWDG_IsEnabled
<> 128:9bcdf88f62b0 155 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 156 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 157 */
<> 128:9bcdf88f62b0 158 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 159 {
<> 128:9bcdf88f62b0 160 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
<> 128:9bcdf88f62b0 161 }
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 /**
<> 128:9bcdf88f62b0 164 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
<> 128:9bcdf88f62b0 165 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
<> 128:9bcdf88f62b0 166 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 128:9bcdf88f62b0 167 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
<> 128:9bcdf88f62b0 168 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
<> 128:9bcdf88f62b0 169 * @rmtoll CR T LL_WWDG_SetCounter
<> 128:9bcdf88f62b0 170 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 171 * @param Counter 0..0x7F (7 bit counter value)
<> 128:9bcdf88f62b0 172 * @retval None
<> 128:9bcdf88f62b0 173 */
<> 128:9bcdf88f62b0 174 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
<> 128:9bcdf88f62b0 175 {
<> 128:9bcdf88f62b0 176 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
<> 128:9bcdf88f62b0 177 }
<> 128:9bcdf88f62b0 178
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @brief Return current Watchdog Counter Value (7 bits counter value)
<> 128:9bcdf88f62b0 181 * @rmtoll CR T LL_WWDG_GetCounter
<> 128:9bcdf88f62b0 182 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 183 * @retval 7 bit Watchdog Counter value
<> 128:9bcdf88f62b0 184 */
<> 128:9bcdf88f62b0 185 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 186 {
<> 128:9bcdf88f62b0 187 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
<> 128:9bcdf88f62b0 188 }
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 /**
<> 128:9bcdf88f62b0 191 * @brief Set the time base of the prescaler (WDGTB).
<> 128:9bcdf88f62b0 192 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
<> 128:9bcdf88f62b0 193 * is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 128:9bcdf88f62b0 194 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
<> 128:9bcdf88f62b0 195 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 196 * @param Prescaler This parameter can be one of the following values:
<> 128:9bcdf88f62b0 197 * @arg @ref LL_WWDG_PRESCALER_1
<> 128:9bcdf88f62b0 198 * @arg @ref LL_WWDG_PRESCALER_2
<> 128:9bcdf88f62b0 199 * @arg @ref LL_WWDG_PRESCALER_4
<> 128:9bcdf88f62b0 200 * @arg @ref LL_WWDG_PRESCALER_8
<> 128:9bcdf88f62b0 201 * @retval None
<> 128:9bcdf88f62b0 202 */
<> 128:9bcdf88f62b0 203 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
<> 128:9bcdf88f62b0 204 {
<> 128:9bcdf88f62b0 205 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
<> 128:9bcdf88f62b0 206 }
<> 128:9bcdf88f62b0 207
<> 128:9bcdf88f62b0 208 /**
<> 128:9bcdf88f62b0 209 * @brief Return current Watchdog Prescaler Value
<> 128:9bcdf88f62b0 210 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
<> 128:9bcdf88f62b0 211 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 212 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 213 * @arg @ref LL_WWDG_PRESCALER_1
<> 128:9bcdf88f62b0 214 * @arg @ref LL_WWDG_PRESCALER_2
<> 128:9bcdf88f62b0 215 * @arg @ref LL_WWDG_PRESCALER_4
<> 128:9bcdf88f62b0 216 * @arg @ref LL_WWDG_PRESCALER_8
<> 128:9bcdf88f62b0 217 */
<> 128:9bcdf88f62b0 218 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 219 {
<> 128:9bcdf88f62b0 220 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
<> 128:9bcdf88f62b0 221 }
<> 128:9bcdf88f62b0 222
<> 128:9bcdf88f62b0 223 /**
<> 128:9bcdf88f62b0 224 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
<> 128:9bcdf88f62b0 225 * @note This window value defines when write in the WWDG_CR register
<> 128:9bcdf88f62b0 226 * to program Watchdog counter is allowed.
<> 128:9bcdf88f62b0 227 * Watchdog counter value update must occur only when the counter value
<> 128:9bcdf88f62b0 228 * is lower than the Watchdog window register value.
<> 128:9bcdf88f62b0 229 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
<> 128:9bcdf88f62b0 230 * (in the control register) is refreshed before the downcounter has reached
<> 128:9bcdf88f62b0 231 * the watchdog window register value.
<> 128:9bcdf88f62b0 232 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
<> 128:9bcdf88f62b0 233 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
<> 128:9bcdf88f62b0 234 * @rmtoll CFR W LL_WWDG_SetWindow
<> 128:9bcdf88f62b0 235 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 236 * @param Window 0x00..0x7F (7 bit Window value)
<> 128:9bcdf88f62b0 237 * @retval None
<> 128:9bcdf88f62b0 238 */
<> 128:9bcdf88f62b0 239 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
<> 128:9bcdf88f62b0 240 {
<> 128:9bcdf88f62b0 241 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
<> 128:9bcdf88f62b0 242 }
<> 128:9bcdf88f62b0 243
<> 128:9bcdf88f62b0 244 /**
<> 128:9bcdf88f62b0 245 * @brief Return current Watchdog Window Value (7 bits value)
<> 128:9bcdf88f62b0 246 * @rmtoll CFR W LL_WWDG_GetWindow
<> 128:9bcdf88f62b0 247 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 248 * @retval 7 bit Watchdog Window value
<> 128:9bcdf88f62b0 249 */
<> 128:9bcdf88f62b0 250 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 251 {
<> 128:9bcdf88f62b0 252 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
<> 128:9bcdf88f62b0 253 }
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 /**
<> 128:9bcdf88f62b0 256 * @}
<> 128:9bcdf88f62b0 257 */
<> 128:9bcdf88f62b0 258
<> 128:9bcdf88f62b0 259 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
<> 128:9bcdf88f62b0 260 * @{
<> 128:9bcdf88f62b0 261 */
<> 128:9bcdf88f62b0 262 /**
<> 128:9bcdf88f62b0 263 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
<> 128:9bcdf88f62b0 264 * @note This bit is set by hardware when the counter has reached the value 0x40.
<> 128:9bcdf88f62b0 265 * It must be cleared by software by writing 0.
<> 128:9bcdf88f62b0 266 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
<> 128:9bcdf88f62b0 267 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
<> 128:9bcdf88f62b0 268 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 269 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 270 */
<> 128:9bcdf88f62b0 271 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 272 {
<> 128:9bcdf88f62b0 273 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
<> 128:9bcdf88f62b0 274 }
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 /**
<> 128:9bcdf88f62b0 277 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
<> 128:9bcdf88f62b0 278 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
<> 128:9bcdf88f62b0 279 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 280 * @retval None
<> 128:9bcdf88f62b0 281 */
<> 128:9bcdf88f62b0 282 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 283 {
<> 128:9bcdf88f62b0 284 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
<> 128:9bcdf88f62b0 285 }
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 /**
<> 128:9bcdf88f62b0 288 * @}
<> 128:9bcdf88f62b0 289 */
<> 128:9bcdf88f62b0 290
<> 128:9bcdf88f62b0 291 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
<> 128:9bcdf88f62b0 292 * @{
<> 128:9bcdf88f62b0 293 */
<> 128:9bcdf88f62b0 294 /**
<> 128:9bcdf88f62b0 295 * @brief Enable the Early Wakeup Interrupt.
<> 128:9bcdf88f62b0 296 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
<> 128:9bcdf88f62b0 297 * This interrupt is only cleared by hardware after a reset
<> 128:9bcdf88f62b0 298 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
<> 128:9bcdf88f62b0 299 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 300 * @retval None
<> 128:9bcdf88f62b0 301 */
<> 128:9bcdf88f62b0 302 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 303 {
<> 128:9bcdf88f62b0 304 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
<> 128:9bcdf88f62b0 305 }
<> 128:9bcdf88f62b0 306
<> 128:9bcdf88f62b0 307 /**
<> 128:9bcdf88f62b0 308 * @brief Check if Early Wakeup Interrupt is enabled
<> 128:9bcdf88f62b0 309 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
<> 128:9bcdf88f62b0 310 * @param WWDGx WWDG Instance
<> 128:9bcdf88f62b0 311 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 312 */
<> 128:9bcdf88f62b0 313 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 128:9bcdf88f62b0 314 {
<> 128:9bcdf88f62b0 315 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
<> 128:9bcdf88f62b0 316 }
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 /**
<> 128:9bcdf88f62b0 319 * @}
<> 128:9bcdf88f62b0 320 */
<> 128:9bcdf88f62b0 321
<> 128:9bcdf88f62b0 322 /**
<> 128:9bcdf88f62b0 323 * @}
<> 128:9bcdf88f62b0 324 */
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /**
<> 128:9bcdf88f62b0 327 * @}
<> 128:9bcdf88f62b0 328 */
<> 128:9bcdf88f62b0 329
<> 128:9bcdf88f62b0 330 #endif /* WWDG */
<> 128:9bcdf88f62b0 331
<> 128:9bcdf88f62b0 332 /**
<> 128:9bcdf88f62b0 333 * @}
<> 128:9bcdf88f62b0 334 */
<> 128:9bcdf88f62b0 335
<> 128:9bcdf88f62b0 336 #ifdef __cplusplus
<> 128:9bcdf88f62b0 337 }
<> 128:9bcdf88f62b0 338 #endif
<> 128:9bcdf88f62b0 339
<> 128:9bcdf88f62b0 340 #endif /* __STM32L1xx_LL_WWDG_H */
<> 128:9bcdf88f62b0 341
<> 128:9bcdf88f62b0 342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/