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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_usart.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of USART LL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_USART_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_USART_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_LL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	#if defined (USART1) \|\| defined (USART2) \|\| defined (USART3) \|\| defined (UART4) \|\| defined (UART5)
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @defgroup USART_LL USART
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Private types -------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/* Private variables ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	61
<>	128:9bcdf88f62b0	62	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	63	/** @defgroup USART_LL_Private_Constants USART Private Constants
<>	128:9bcdf88f62b0	64	* @{
<>	128:9bcdf88f62b0	65	*/
<>	128:9bcdf88f62b0	66
<>	128:9bcdf88f62b0	67	/* Defines used for the bit position in the register and perform offsets*/
<>	128:9bcdf88f62b0	68	#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
<>	128:9bcdf88f62b0	69	/**
<>	128:9bcdf88f62b0	70	* @}
<>	128:9bcdf88f62b0	71	*/
<>	128:9bcdf88f62b0	72
<>	128:9bcdf88f62b0	73	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	74	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	75	/** @defgroup USART_LL_Private_Macros USART Private Macros
<>	128:9bcdf88f62b0	76	* @{
<>	128:9bcdf88f62b0	77	*/
<>	128:9bcdf88f62b0	78	/**
<>	128:9bcdf88f62b0	79	* @}
<>	128:9bcdf88f62b0	80	*/
<>	128:9bcdf88f62b0	81	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	82
<>	128:9bcdf88f62b0	83	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	84	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	85	/** @defgroup USART_LL_ES_INIT USART Exported Init structures
<>	128:9bcdf88f62b0	86	* @{
<>	128:9bcdf88f62b0	87	*/
<>	128:9bcdf88f62b0	88
<>	128:9bcdf88f62b0	89	/**
<>	128:9bcdf88f62b0	90	* @brief LL USART Init Structure definition
<>	128:9bcdf88f62b0	91	*/
<>	128:9bcdf88f62b0	92	typedef struct
<>	128:9bcdf88f62b0	93	{
<>	128:9bcdf88f62b0	94	uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
<>	128:9bcdf88f62b0	95
<>	128:9bcdf88f62b0	96	This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
<>	128:9bcdf88f62b0	97
<>	128:9bcdf88f62b0	98	uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
<>	128:9bcdf88f62b0	99	This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
<>	128:9bcdf88f62b0	100
<>	128:9bcdf88f62b0	101	This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
<>	128:9bcdf88f62b0	102
<>	128:9bcdf88f62b0	103	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<>	128:9bcdf88f62b0	104	This parameter can be a value of @ref USART_LL_EC_STOPBITS.
<>	128:9bcdf88f62b0	105
<>	128:9bcdf88f62b0	106	This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
<>	128:9bcdf88f62b0	107
<>	128:9bcdf88f62b0	108	uint32_t Parity; /*!< Specifies the parity mode.
<>	128:9bcdf88f62b0	109	This parameter can be a value of @ref USART_LL_EC_PARITY.
<>	128:9bcdf88f62b0	110
<>	128:9bcdf88f62b0	111	This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
<>	128:9bcdf88f62b0	112
<>	128:9bcdf88f62b0	113	uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
<>	128:9bcdf88f62b0	114	This parameter can be a value of @ref USART_LL_EC_DIRECTION.
<>	128:9bcdf88f62b0	115
<>	128:9bcdf88f62b0	116	This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
<>	128:9bcdf88f62b0	117
<>	128:9bcdf88f62b0	118	uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
<>	128:9bcdf88f62b0	119	This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
<>	128:9bcdf88f62b0	120
<>	128:9bcdf88f62b0	121	This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
<>	128:9bcdf88f62b0	122
<>	128:9bcdf88f62b0	123	uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
<>	128:9bcdf88f62b0	124	This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
<>	128:9bcdf88f62b0	125
<>	128:9bcdf88f62b0	126	This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
<>	128:9bcdf88f62b0	127
<>	128:9bcdf88f62b0	128	} LL_USART_InitTypeDef;
<>	128:9bcdf88f62b0	129
<>	128:9bcdf88f62b0	130	/**
<>	128:9bcdf88f62b0	131	* @brief LL USART Clock Init Structure definition
<>	128:9bcdf88f62b0	132	*/
<>	128:9bcdf88f62b0	133	typedef struct
<>	128:9bcdf88f62b0	134	{
<>	128:9bcdf88f62b0	135	uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
<>	128:9bcdf88f62b0	136	This parameter can be a value of @ref USART_LL_EC_CLOCK.
<>	128:9bcdf88f62b0	137
<>	128:9bcdf88f62b0	138	USART HW configuration can be modified afterwards using unitary functions
<>	128:9bcdf88f62b0	139	@ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
<>	128:9bcdf88f62b0	140	For more details, refer to description of this function. */
<>	128:9bcdf88f62b0	141
<>	128:9bcdf88f62b0	142	uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
<>	128:9bcdf88f62b0	143	This parameter can be a value of @ref USART_LL_EC_POLARITY.
<>	128:9bcdf88f62b0	144
<>	128:9bcdf88f62b0	145	USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
<>	128:9bcdf88f62b0	146	For more details, refer to description of this function. */
<>	128:9bcdf88f62b0	147
<>	128:9bcdf88f62b0	148	uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
<>	128:9bcdf88f62b0	149	This parameter can be a value of @ref USART_LL_EC_PHASE.
<>	128:9bcdf88f62b0	150
<>	128:9bcdf88f62b0	151	USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
<>	128:9bcdf88f62b0	152	For more details, refer to description of this function. */
<>	128:9bcdf88f62b0	153
<>	128:9bcdf88f62b0	154	uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
<>	128:9bcdf88f62b0	155	data bit (MSB) has to be output on the SCLK pin in synchronous mode.
<>	128:9bcdf88f62b0	156	This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
<>	128:9bcdf88f62b0	157
<>	128:9bcdf88f62b0	158	USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
<>	128:9bcdf88f62b0	159	For more details, refer to description of this function. */
<>	128:9bcdf88f62b0	160
<>	128:9bcdf88f62b0	161	} LL_USART_ClockInitTypeDef;
<>	128:9bcdf88f62b0	162
<>	128:9bcdf88f62b0	163	/**
<>	128:9bcdf88f62b0	164	* @}
<>	128:9bcdf88f62b0	165	*/
<>	128:9bcdf88f62b0	166	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	167
<>	128:9bcdf88f62b0	168	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	169	/** @defgroup USART_LL_Exported_Constants USART Exported Constants
<>	128:9bcdf88f62b0	170	* @{
<>	128:9bcdf88f62b0	171	*/
<>	128:9bcdf88f62b0	172
<>	128:9bcdf88f62b0	173	/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
<>	128:9bcdf88f62b0	174	* @brief Flags defines which can be used with LL_USART_ReadReg function
<>	128:9bcdf88f62b0	175	* @{
<>	128:9bcdf88f62b0	176	*/
<>	128:9bcdf88f62b0	177	#define LL_USART_SR_PE USART_SR_PE /!< Parity error flag /
<>	128:9bcdf88f62b0	178	#define LL_USART_SR_FE USART_SR_FE /!< Framing error flag /
<>	128:9bcdf88f62b0	179	#define LL_USART_SR_NE USART_SR_NE /!< Noise detected flag /
<>	128:9bcdf88f62b0	180	#define LL_USART_SR_ORE USART_SR_ORE /!< Overrun error flag /
<>	128:9bcdf88f62b0	181	#define LL_USART_SR_IDLE USART_SR_IDLE /!< Idle line detected flag /
<>	128:9bcdf88f62b0	182	#define LL_USART_SR_RXNE USART_SR_RXNE /!< Read data register not empty flag /
<>	128:9bcdf88f62b0	183	#define LL_USART_SR_TC USART_SR_TC /!< Transmission complete flag /
<>	128:9bcdf88f62b0	184	#define LL_USART_SR_TXE USART_SR_TXE /!< Transmit data register empty flag /
<>	128:9bcdf88f62b0	185	#define LL_USART_SR_LBD USART_SR_LBD /!< LIN break detection flag /
<>	128:9bcdf88f62b0	186	#define LL_USART_SR_CTS USART_SR_CTS /!< CTS flag /
<>	128:9bcdf88f62b0	187	/**
<>	128:9bcdf88f62b0	188	* @}
<>	128:9bcdf88f62b0	189	*/
<>	128:9bcdf88f62b0	190
<>	128:9bcdf88f62b0	191	/** @defgroup USART_LL_EC_IT IT Defines
<>	128:9bcdf88f62b0	192	* @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
<>	128:9bcdf88f62b0	193	* @{
<>	128:9bcdf88f62b0	194	*/
<>	128:9bcdf88f62b0	195	#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /!< IDLE interrupt enable /
<>	128:9bcdf88f62b0	196	#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /!< Read data register not empty interrupt enable /
<>	128:9bcdf88f62b0	197	#define LL_USART_CR1_TCIE USART_CR1_TCIE /!< Transmission complete interrupt enable /
<>	128:9bcdf88f62b0	198	#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /!< Transmit data register empty interrupt enable /
<>	128:9bcdf88f62b0	199	#define LL_USART_CR1_PEIE USART_CR1_PEIE /!< Parity error /
<>	128:9bcdf88f62b0	200	#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /!< LIN break detection interrupt enable /
<>	128:9bcdf88f62b0	201	#define LL_USART_CR3_EIE USART_CR3_EIE /!< Error interrupt enable /
<>	128:9bcdf88f62b0	202	#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /!< CTS interrupt enable /
<>	128:9bcdf88f62b0	203	/**
<>	128:9bcdf88f62b0	204	* @}
<>	128:9bcdf88f62b0	205	*/
<>	128:9bcdf88f62b0	206
<>	128:9bcdf88f62b0	207	/** @defgroup USART_LL_EC_DIRECTION Communication Direction
<>	128:9bcdf88f62b0	208	* @{
<>	128:9bcdf88f62b0	209	*/
<>	128:9bcdf88f62b0	210	#define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U /!< Transmitter and Receiver are disabled /
<>	128:9bcdf88f62b0	211	#define LL_USART_DIRECTION_RX USART_CR1_RE /!< Transmitter is disabled and Receiver is enabled /
<>	128:9bcdf88f62b0	212	#define LL_USART_DIRECTION_TX USART_CR1_TE /!< Transmitter is enabled and Receiver is disabled /
<>	128:9bcdf88f62b0	213	#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE \|USART_CR1_RE) /!< Transmitter and Receiver are enabled /
<>	128:9bcdf88f62b0	214	/**
<>	128:9bcdf88f62b0	215	* @}
<>	128:9bcdf88f62b0	216	*/
<>	128:9bcdf88f62b0	217
<>	128:9bcdf88f62b0	218	/** @defgroup USART_LL_EC_PARITY Parity Control
<>	128:9bcdf88f62b0	219	* @{
<>	128:9bcdf88f62b0	220	*/
<>	128:9bcdf88f62b0	221	#define LL_USART_PARITY_NONE (uint32_t)0x00000000U /!< Parity control disabled /
<>	128:9bcdf88f62b0	222	#define LL_USART_PARITY_EVEN USART_CR1_PCE /!< Parity control enabled and Even Parity is selected /
<>	128:9bcdf88f62b0	223	#define LL_USART_PARITY_ODD (USART_CR1_PCE \| USART_CR1_PS) /!< Parity control enabled and Odd Parity is selected /
<>	128:9bcdf88f62b0	224	/**
<>	128:9bcdf88f62b0	225	* @}
<>	128:9bcdf88f62b0	226	*/
<>	128:9bcdf88f62b0	227
<>	128:9bcdf88f62b0	228	/** @defgroup USART_LL_EC_WAKEUP Wakeup
<>	128:9bcdf88f62b0	229	* @{
<>	128:9bcdf88f62b0	230	*/
<>	128:9bcdf88f62b0	231	#define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U /!< USART wake up from Mute mode on Idle Line /
<>	128:9bcdf88f62b0	232	#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /!< USART wake up from Mute mode on Address Mark /
<>	128:9bcdf88f62b0	233	/**
<>	128:9bcdf88f62b0	234	* @}
<>	128:9bcdf88f62b0	235	*/
<>	128:9bcdf88f62b0	236
<>	128:9bcdf88f62b0	237	/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
<>	128:9bcdf88f62b0	238	* @{
<>	128:9bcdf88f62b0	239	*/
<>	128:9bcdf88f62b0	240	#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /!< 8 bits word length : Start bit, 8 data bits, n stop bits /
<>	128:9bcdf88f62b0	241	#define LL_USART_DATAWIDTH_9B USART_CR1_M /!< 9 bits word length : Start bit, 9 data bits, n stop bits /
<>	128:9bcdf88f62b0	242	/**
<>	128:9bcdf88f62b0	243	* @}
<>	128:9bcdf88f62b0	244	*/
<>	128:9bcdf88f62b0	245
<>	128:9bcdf88f62b0	246	/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
<>	128:9bcdf88f62b0	247	* @{
<>	128:9bcdf88f62b0	248	*/
<>	128:9bcdf88f62b0	249	#define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U /!< Oversampling by 16 /
<>	128:9bcdf88f62b0	250	#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /!< Oversampling by 8 /
<>	128:9bcdf88f62b0	251	/**
<>	128:9bcdf88f62b0	252	* @}
<>	128:9bcdf88f62b0	253	*/
<>	128:9bcdf88f62b0	254
<>	128:9bcdf88f62b0	255	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	256	/** @defgroup USART_LL_EC_CLOCK Clock Signal
<>	128:9bcdf88f62b0	257	* @{
<>	128:9bcdf88f62b0	258	*/
<>	128:9bcdf88f62b0	259
<>	128:9bcdf88f62b0	260	#define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U /!< Clock signal not provided /
<>	128:9bcdf88f62b0	261	#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /!< Clock signal provided /
<>	128:9bcdf88f62b0	262	/**
<>	128:9bcdf88f62b0	263	* @}
<>	128:9bcdf88f62b0	264	*/
<>	128:9bcdf88f62b0	265	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	266
<>	128:9bcdf88f62b0	267	/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
<>	128:9bcdf88f62b0	268	* @{
<>	128:9bcdf88f62b0	269	*/
<>	128:9bcdf88f62b0	270	#define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U /!< The clock pulse of the last data bit is not output to the SCLK pin /
<>	128:9bcdf88f62b0	271	#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /!< The clock pulse of the last data bit is output to the SCLK pin /
<>	128:9bcdf88f62b0	272	/**
<>	128:9bcdf88f62b0	273	* @}
<>	128:9bcdf88f62b0	274	*/
<>	128:9bcdf88f62b0	275
<>	128:9bcdf88f62b0	276	/** @defgroup USART_LL_EC_PHASE Clock Phase
<>	128:9bcdf88f62b0	277	* @{
<>	128:9bcdf88f62b0	278	*/
<>	128:9bcdf88f62b0	279	#define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U /!< The first clock transition is the first data capture edge /
<>	128:9bcdf88f62b0	280	#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /!< The second clock transition is the first data capture edge /
<>	128:9bcdf88f62b0	281	/**
<>	128:9bcdf88f62b0	282	* @}
<>	128:9bcdf88f62b0	283	*/
<>	128:9bcdf88f62b0	284
<>	128:9bcdf88f62b0	285	/** @defgroup USART_LL_EC_POLARITY Clock Polarity
<>	128:9bcdf88f62b0	286	* @{
<>	128:9bcdf88f62b0	287	*/
<>	128:9bcdf88f62b0	288	#define LL_USART_POLARITY_LOW (uint32_t)0x00000000U /!< Steady low value on SCLK pin outside transmission window/
<>	128:9bcdf88f62b0	289	#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /!< Steady high value on SCLK pin outside transmission window /
<>	128:9bcdf88f62b0	290	/**
<>	128:9bcdf88f62b0	291	* @}
<>	128:9bcdf88f62b0	292	*/
<>	128:9bcdf88f62b0	293
<>	128:9bcdf88f62b0	294	/** @defgroup USART_LL_EC_STOPBITS Stop Bits
<>	128:9bcdf88f62b0	295	* @{
<>	128:9bcdf88f62b0	296	*/
<>	128:9bcdf88f62b0	297	#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /!< 0.5 stop bit /
<>	128:9bcdf88f62b0	298	#define LL_USART_STOPBITS_1 (uint32_t)0x00000000U /!< 1 stop bit /
<>	128:9bcdf88f62b0	299	#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 \| USART_CR2_STOP_1) /!< 1.5 stop bits /
<>	128:9bcdf88f62b0	300	#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /!< 2 stop bits /
<>	128:9bcdf88f62b0	301	/**
<>	128:9bcdf88f62b0	302	* @}
<>	128:9bcdf88f62b0	303	*/
<>	128:9bcdf88f62b0	304
<>	128:9bcdf88f62b0	305	/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
<>	128:9bcdf88f62b0	306	* @{
<>	128:9bcdf88f62b0	307	*/
<>	128:9bcdf88f62b0	308	#define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U /!< CTS and RTS hardware flow control disabled /
<>	128:9bcdf88f62b0	309	#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /!< RTS output enabled, data is only requested when there is space in the receive buffer /
<>	128:9bcdf88f62b0	310	#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) /
<>	128:9bcdf88f62b0	311	#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE \| USART_CR3_CTSE) /!< CTS and RTS hardware flow control enabled /
<>	128:9bcdf88f62b0	312	/**
<>	128:9bcdf88f62b0	313	* @}
<>	128:9bcdf88f62b0	314	*/
<>	128:9bcdf88f62b0	315
<>	128:9bcdf88f62b0	316	/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
<>	128:9bcdf88f62b0	317	* @{
<>	128:9bcdf88f62b0	318	*/
<>	128:9bcdf88f62b0	319	#define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U /!< IrDA normal power mode /
<>	128:9bcdf88f62b0	320	#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /!< IrDA low power mode /
<>	128:9bcdf88f62b0	321	/**
<>	128:9bcdf88f62b0	322	* @}
<>	128:9bcdf88f62b0	323	*/
<>	128:9bcdf88f62b0	324
<>	128:9bcdf88f62b0	325	/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
<>	128:9bcdf88f62b0	326	* @{
<>	128:9bcdf88f62b0	327	*/
<>	128:9bcdf88f62b0	328	#define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U /!< 10-bit break detection method selected /
<>	128:9bcdf88f62b0	329	#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /!< 11-bit break detection method selected /
<>	128:9bcdf88f62b0	330	/**
<>	128:9bcdf88f62b0	331	* @}
<>	128:9bcdf88f62b0	332	*/
<>	128:9bcdf88f62b0	333
<>	128:9bcdf88f62b0	334	/**
<>	128:9bcdf88f62b0	335	* @}
<>	128:9bcdf88f62b0	336	*/
<>	128:9bcdf88f62b0	337
<>	128:9bcdf88f62b0	338	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	339	/** @defgroup USART_LL_Exported_Macros USART Exported Macros
<>	128:9bcdf88f62b0	340	* @{
<>	128:9bcdf88f62b0	341	*/
<>	128:9bcdf88f62b0	342
<>	128:9bcdf88f62b0	343	/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
<>	128:9bcdf88f62b0	344	* @{
<>	128:9bcdf88f62b0	345	*/
<>	128:9bcdf88f62b0	346
<>	128:9bcdf88f62b0	347	/**
<>	128:9bcdf88f62b0	348	* @brief Write a value in USART register
<>	128:9bcdf88f62b0	349	* @param __INSTANCE__ USART Instance
<>	128:9bcdf88f62b0	350	* @param __REG__ Register to be written
<>	128:9bcdf88f62b0	351	* @param __VALUE__ Value to be written in the register
<>	128:9bcdf88f62b0	352	* @retval None
<>	128:9bcdf88f62b0	353	*/
<>	128:9bcdf88f62b0	354	#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	128:9bcdf88f62b0	355
<>	128:9bcdf88f62b0	356	/**
<>	128:9bcdf88f62b0	357	* @brief Read a value in USART register
<>	128:9bcdf88f62b0	358	* @param __INSTANCE__ USART Instance
<>	128:9bcdf88f62b0	359	* @param __REG__ Register to be read
<>	128:9bcdf88f62b0	360	* @retval Register value
<>	128:9bcdf88f62b0	361	*/
<>	128:9bcdf88f62b0	362	#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	128:9bcdf88f62b0	363	/**
<>	128:9bcdf88f62b0	364	* @}
<>	128:9bcdf88f62b0	365	*/
<>	128:9bcdf88f62b0	366
<>	128:9bcdf88f62b0	367	/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
<>	128:9bcdf88f62b0	368	* @{
<>	128:9bcdf88f62b0	369	*/
<>	128:9bcdf88f62b0	370
<>	128:9bcdf88f62b0	371	/**
<>	128:9bcdf88f62b0	372	* @brief Compute USARTDIV value according to Peripheral Clock and
<>	128:9bcdf88f62b0	373	* expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
<>	128:9bcdf88f62b0	374	* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
<>	128:9bcdf88f62b0	375	* @param __BAUDRATE__ Baud rate value to achieve
<>	128:9bcdf88f62b0	376	* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
<>	128:9bcdf88f62b0	377	*/
<>	128:9bcdf88f62b0	378	#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)25)/(2(__BAUDRATE__)))
<>	128:9bcdf88f62b0	379	#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
<>	128:9bcdf88f62b0	380	#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
<>	128:9bcdf88f62b0	381	/* UART BRR = mantissa + overflow + fraction
<>	128:9bcdf88f62b0	382	= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
<>	128:9bcdf88f62b0	383	#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
<>	128:9bcdf88f62b0	384	((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
<>	128:9bcdf88f62b0	385	(__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
<>	128:9bcdf88f62b0	386
<>	128:9bcdf88f62b0	387	/**
<>	128:9bcdf88f62b0	388	* @brief Compute USARTDIV value according to Peripheral Clock and
<>	128:9bcdf88f62b0	389	* expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
<>	128:9bcdf88f62b0	390	* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
<>	128:9bcdf88f62b0	391	* @param __BAUDRATE__ Baud rate value to achieve
<>	128:9bcdf88f62b0	392	* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
<>	128:9bcdf88f62b0	393	*/
<>	128:9bcdf88f62b0	394	#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)25)/(4(__BAUDRATE__)))
<>	128:9bcdf88f62b0	395	#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
<>	128:9bcdf88f62b0	396	#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
<>	128:9bcdf88f62b0	397	/* USART BRR = mantissa + overflow + fraction
<>	128:9bcdf88f62b0	398	= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
<>	128:9bcdf88f62b0	399	#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
<>	128:9bcdf88f62b0	400	(__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
<>	128:9bcdf88f62b0	401	(__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
<>	128:9bcdf88f62b0	402
<>	128:9bcdf88f62b0	403	/**
<>	128:9bcdf88f62b0	404	* @}
<>	128:9bcdf88f62b0	405	*/
<>	128:9bcdf88f62b0	406
<>	128:9bcdf88f62b0	407	/**
<>	128:9bcdf88f62b0	408	* @}
<>	128:9bcdf88f62b0	409	*/
<>	128:9bcdf88f62b0	410
<>	128:9bcdf88f62b0	411	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	412
<>	128:9bcdf88f62b0	413	/** @defgroup USART_LL_Exported_Functions USART Exported Functions
<>	128:9bcdf88f62b0	414	* @{
<>	128:9bcdf88f62b0	415	*/
<>	128:9bcdf88f62b0	416
<>	128:9bcdf88f62b0	417	/** @defgroup USART_LL_EF_Configuration Configuration functions
<>	128:9bcdf88f62b0	418	* @{
<>	128:9bcdf88f62b0	419	*/
<>	128:9bcdf88f62b0	420
<>	128:9bcdf88f62b0	421	/**
<>	128:9bcdf88f62b0	422	* @brief USART Enable
<>	128:9bcdf88f62b0	423	* @rmtoll CR1 UE LL_USART_Enable
<>	128:9bcdf88f62b0	424	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	425	* @retval None
<>	128:9bcdf88f62b0	426	*/
<>	128:9bcdf88f62b0	427	__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	428	{
<>	128:9bcdf88f62b0	429	SET_BIT(USARTx->CR1, USART_CR1_UE);
<>	128:9bcdf88f62b0	430	}
<>	128:9bcdf88f62b0	431
<>	128:9bcdf88f62b0	432	/**
<>	128:9bcdf88f62b0	433	* @brief USART Disable (all USART prescalers and outputs are disabled)
<>	128:9bcdf88f62b0	434	* @note When USART is disabled, USART prescalers and outputs are stopped immediately,
<>	128:9bcdf88f62b0	435	* and current operations are discarded. The configuration of the USART is kept, but all the status
<>	128:9bcdf88f62b0	436	* flags, in the USARTx_SR are set to their default values.
<>	128:9bcdf88f62b0	437	* @rmtoll CR1 UE LL_USART_Disable
<>	128:9bcdf88f62b0	438	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	439	* @retval None
<>	128:9bcdf88f62b0	440	*/
<>	128:9bcdf88f62b0	441	__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	442	{
<>	128:9bcdf88f62b0	443	CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
<>	128:9bcdf88f62b0	444	}
<>	128:9bcdf88f62b0	445
<>	128:9bcdf88f62b0	446	/**
<>	128:9bcdf88f62b0	447	* @brief Indicate if USART is enabled
<>	128:9bcdf88f62b0	448	* @rmtoll CR1 UE LL_USART_IsEnabled
<>	128:9bcdf88f62b0	449	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	450	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	451	*/
<>	128:9bcdf88f62b0	452	__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	453	{
<>	128:9bcdf88f62b0	454	return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
<>	128:9bcdf88f62b0	455	}
<>	128:9bcdf88f62b0	456
<>	128:9bcdf88f62b0	457	/**
<>	128:9bcdf88f62b0	458	* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
<>	128:9bcdf88f62b0	459	* @rmtoll CR1 RE LL_USART_EnableDirectionRx
<>	128:9bcdf88f62b0	460	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	461	* @retval None
<>	128:9bcdf88f62b0	462	*/
<>	128:9bcdf88f62b0	463	__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	464	{
<>	128:9bcdf88f62b0	465	SET_BIT(USARTx->CR1, USART_CR1_RE);
<>	128:9bcdf88f62b0	466	}
<>	128:9bcdf88f62b0	467
<>	128:9bcdf88f62b0	468	/**
<>	128:9bcdf88f62b0	469	* @brief Receiver Disable
<>	128:9bcdf88f62b0	470	* @rmtoll CR1 RE LL_USART_DisableDirectionRx
<>	128:9bcdf88f62b0	471	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	472	* @retval None
<>	128:9bcdf88f62b0	473	*/
<>	128:9bcdf88f62b0	474	__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	475	{
<>	128:9bcdf88f62b0	476	CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
<>	128:9bcdf88f62b0	477	}
<>	128:9bcdf88f62b0	478
<>	128:9bcdf88f62b0	479	/**
<>	128:9bcdf88f62b0	480	* @brief Transmitter Enable
<>	128:9bcdf88f62b0	481	* @rmtoll CR1 TE LL_USART_EnableDirectionTx
<>	128:9bcdf88f62b0	482	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	483	* @retval None
<>	128:9bcdf88f62b0	484	*/
<>	128:9bcdf88f62b0	485	__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	486	{
<>	128:9bcdf88f62b0	487	SET_BIT(USARTx->CR1, USART_CR1_TE);
<>	128:9bcdf88f62b0	488	}
<>	128:9bcdf88f62b0	489
<>	128:9bcdf88f62b0	490	/**
<>	128:9bcdf88f62b0	491	* @brief Transmitter Disable
<>	128:9bcdf88f62b0	492	* @rmtoll CR1 TE LL_USART_DisableDirectionTx
<>	128:9bcdf88f62b0	493	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	494	* @retval None
<>	128:9bcdf88f62b0	495	*/
<>	128:9bcdf88f62b0	496	__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	497	{
<>	128:9bcdf88f62b0	498	CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
<>	128:9bcdf88f62b0	499	}
<>	128:9bcdf88f62b0	500
<>	128:9bcdf88f62b0	501	/**
<>	128:9bcdf88f62b0	502	* @brief Configure simultaneously enabled/disabled states
<>	128:9bcdf88f62b0	503	* of Transmitter and Receiver
<>	128:9bcdf88f62b0	504	* @rmtoll CR1 RE LL_USART_SetTransferDirection\n
<>	128:9bcdf88f62b0	505	* CR1 TE LL_USART_SetTransferDirection
<>	128:9bcdf88f62b0	506	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	507	* @param TransferDirection This parameter can be one of the following values:
<>	128:9bcdf88f62b0	508	* @arg @ref LL_USART_DIRECTION_NONE
<>	128:9bcdf88f62b0	509	* @arg @ref LL_USART_DIRECTION_RX
<>	128:9bcdf88f62b0	510	* @arg @ref LL_USART_DIRECTION_TX
<>	128:9bcdf88f62b0	511	* @arg @ref LL_USART_DIRECTION_TX_RX
<>	128:9bcdf88f62b0	512	* @retval None
<>	128:9bcdf88f62b0	513	*/
<>	128:9bcdf88f62b0	514	__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
<>	128:9bcdf88f62b0	515	{
<>	128:9bcdf88f62b0	516	MODIFY_REG(USARTx->CR1, USART_CR1_RE \| USART_CR1_TE, TransferDirection);
<>	128:9bcdf88f62b0	517	}
<>	128:9bcdf88f62b0	518
<>	128:9bcdf88f62b0	519	/**
<>	128:9bcdf88f62b0	520	* @brief Return enabled/disabled states of Transmitter and Receiver
<>	128:9bcdf88f62b0	521	* @rmtoll CR1 RE LL_USART_GetTransferDirection\n
<>	128:9bcdf88f62b0	522	* CR1 TE LL_USART_GetTransferDirection
<>	128:9bcdf88f62b0	523	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	524	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	525	* @arg @ref LL_USART_DIRECTION_NONE
<>	128:9bcdf88f62b0	526	* @arg @ref LL_USART_DIRECTION_RX
<>	128:9bcdf88f62b0	527	* @arg @ref LL_USART_DIRECTION_TX
<>	128:9bcdf88f62b0	528	* @arg @ref LL_USART_DIRECTION_TX_RX
<>	128:9bcdf88f62b0	529	*/
<>	128:9bcdf88f62b0	530	__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	531	{
<>	128:9bcdf88f62b0	532	return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE \| USART_CR1_TE));
<>	128:9bcdf88f62b0	533	}
<>	128:9bcdf88f62b0	534
<>	128:9bcdf88f62b0	535	/**
<>	128:9bcdf88f62b0	536	* @brief Configure Parity (enabled/disabled and parity mode if enabled).
<>	128:9bcdf88f62b0	537	* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
<>	128:9bcdf88f62b0	538	* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
<>	128:9bcdf88f62b0	539	* (9th or 8th bit depending on data width) and parity is checked on the received data.
<>	128:9bcdf88f62b0	540	* @rmtoll CR1 PS LL_USART_SetParity\n
<>	128:9bcdf88f62b0	541	* CR1 PCE LL_USART_SetParity
<>	128:9bcdf88f62b0	542	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	543	* @param Parity This parameter can be one of the following values:
<>	128:9bcdf88f62b0	544	* @arg @ref LL_USART_PARITY_NONE
<>	128:9bcdf88f62b0	545	* @arg @ref LL_USART_PARITY_EVEN
<>	128:9bcdf88f62b0	546	* @arg @ref LL_USART_PARITY_ODD
<>	128:9bcdf88f62b0	547	* @retval None
<>	128:9bcdf88f62b0	548	*/
<>	128:9bcdf88f62b0	549	__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
<>	128:9bcdf88f62b0	550	{
<>	128:9bcdf88f62b0	551	MODIFY_REG(USARTx->CR1, USART_CR1_PS \| USART_CR1_PCE, Parity);
<>	128:9bcdf88f62b0	552	}
<>	128:9bcdf88f62b0	553
<>	128:9bcdf88f62b0	554	/**
<>	128:9bcdf88f62b0	555	* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
<>	128:9bcdf88f62b0	556	* @rmtoll CR1 PS LL_USART_GetParity\n
<>	128:9bcdf88f62b0	557	* CR1 PCE LL_USART_GetParity
<>	128:9bcdf88f62b0	558	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	559	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	560	* @arg @ref LL_USART_PARITY_NONE
<>	128:9bcdf88f62b0	561	* @arg @ref LL_USART_PARITY_EVEN
<>	128:9bcdf88f62b0	562	* @arg @ref LL_USART_PARITY_ODD
<>	128:9bcdf88f62b0	563	*/
<>	128:9bcdf88f62b0	564	__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	565	{
<>	128:9bcdf88f62b0	566	return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS \| USART_CR1_PCE));
<>	128:9bcdf88f62b0	567	}
<>	128:9bcdf88f62b0	568
<>	128:9bcdf88f62b0	569	/**
<>	128:9bcdf88f62b0	570	* @brief Set Receiver Wake Up method from Mute mode.
<>	128:9bcdf88f62b0	571	* @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
<>	128:9bcdf88f62b0	572	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	573	* @param Method This parameter can be one of the following values:
<>	128:9bcdf88f62b0	574	* @arg @ref LL_USART_WAKEUP_IDLELINE
<>	128:9bcdf88f62b0	575	* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
<>	128:9bcdf88f62b0	576	* @retval None
<>	128:9bcdf88f62b0	577	*/
<>	128:9bcdf88f62b0	578	__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
<>	128:9bcdf88f62b0	579	{
<>	128:9bcdf88f62b0	580	MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
<>	128:9bcdf88f62b0	581	}
<>	128:9bcdf88f62b0	582
<>	128:9bcdf88f62b0	583	/**
<>	128:9bcdf88f62b0	584	* @brief Return Receiver Wake Up method from Mute mode
<>	128:9bcdf88f62b0	585	* @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
<>	128:9bcdf88f62b0	586	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	587	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	588	* @arg @ref LL_USART_WAKEUP_IDLELINE
<>	128:9bcdf88f62b0	589	* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
<>	128:9bcdf88f62b0	590	*/
<>	128:9bcdf88f62b0	591	__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	592	{
<>	128:9bcdf88f62b0	593	return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
<>	128:9bcdf88f62b0	594	}
<>	128:9bcdf88f62b0	595
<>	128:9bcdf88f62b0	596	/**
<>	128:9bcdf88f62b0	597	* @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
<>	128:9bcdf88f62b0	598	* @rmtoll CR1 M LL_USART_SetDataWidth
<>	128:9bcdf88f62b0	599	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	600	* @param DataWidth This parameter can be one of the following values:
<>	128:9bcdf88f62b0	601	* @arg @ref LL_USART_DATAWIDTH_8B
<>	128:9bcdf88f62b0	602	* @arg @ref LL_USART_DATAWIDTH_9B
<>	128:9bcdf88f62b0	603	* @retval None
<>	128:9bcdf88f62b0	604	*/
<>	128:9bcdf88f62b0	605	__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
<>	128:9bcdf88f62b0	606	{
<>	128:9bcdf88f62b0	607	MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
<>	128:9bcdf88f62b0	608	}
<>	128:9bcdf88f62b0	609
<>	128:9bcdf88f62b0	610	/**
<>	128:9bcdf88f62b0	611	* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
<>	128:9bcdf88f62b0	612	* @rmtoll CR1 M LL_USART_GetDataWidth
<>	128:9bcdf88f62b0	613	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	614	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	615	* @arg @ref LL_USART_DATAWIDTH_8B
<>	128:9bcdf88f62b0	616	* @arg @ref LL_USART_DATAWIDTH_9B
<>	128:9bcdf88f62b0	617	*/
<>	128:9bcdf88f62b0	618	__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	619	{
<>	128:9bcdf88f62b0	620	return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
<>	128:9bcdf88f62b0	621	}
<>	128:9bcdf88f62b0	622
<>	128:9bcdf88f62b0	623	/**
<>	128:9bcdf88f62b0	624	* @brief Set Oversampling to 8-bit or 16-bit mode
<>	128:9bcdf88f62b0	625	* @rmtoll CR1 OVER8 LL_USART_SetOverSampling
<>	128:9bcdf88f62b0	626	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	627	* @param OverSampling This parameter can be one of the following values:
<>	128:9bcdf88f62b0	628	* @arg @ref LL_USART_OVERSAMPLING_16
<>	128:9bcdf88f62b0	629	* @arg @ref LL_USART_OVERSAMPLING_8
<>	128:9bcdf88f62b0	630	* @retval None
<>	128:9bcdf88f62b0	631	*/
<>	128:9bcdf88f62b0	632	__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
<>	128:9bcdf88f62b0	633	{
<>	128:9bcdf88f62b0	634	MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
<>	128:9bcdf88f62b0	635	}
<>	128:9bcdf88f62b0	636
<>	128:9bcdf88f62b0	637	/**
<>	128:9bcdf88f62b0	638	* @brief Return Oversampling mode
<>	128:9bcdf88f62b0	639	* @rmtoll CR1 OVER8 LL_USART_GetOverSampling
<>	128:9bcdf88f62b0	640	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	641	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	642	* @arg @ref LL_USART_OVERSAMPLING_16
<>	128:9bcdf88f62b0	643	* @arg @ref LL_USART_OVERSAMPLING_8
<>	128:9bcdf88f62b0	644	*/
<>	128:9bcdf88f62b0	645	__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	646	{
<>	128:9bcdf88f62b0	647	return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
<>	128:9bcdf88f62b0	648	}
<>	128:9bcdf88f62b0	649
<>	128:9bcdf88f62b0	650	/**
<>	128:9bcdf88f62b0	651	* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
<>	128:9bcdf88f62b0	652	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	653	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	654	* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
<>	128:9bcdf88f62b0	655	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	656	* @param LastBitClockPulse This parameter can be one of the following values:
<>	128:9bcdf88f62b0	657	* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
<>	128:9bcdf88f62b0	658	* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
<>	128:9bcdf88f62b0	659	* @retval None
<>	128:9bcdf88f62b0	660	*/
<>	128:9bcdf88f62b0	661	__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
<>	128:9bcdf88f62b0	662	{
<>	128:9bcdf88f62b0	663	MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
<>	128:9bcdf88f62b0	664	}
<>	128:9bcdf88f62b0	665
<>	128:9bcdf88f62b0	666	/**
<>	128:9bcdf88f62b0	667	* @brief Retrieve Clock pulse of the last data bit output configuration
<>	128:9bcdf88f62b0	668	* (Last bit Clock pulse output to the SCLK pin or not)
<>	128:9bcdf88f62b0	669	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	670	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	671	* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
<>	128:9bcdf88f62b0	672	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	673	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	674	* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
<>	128:9bcdf88f62b0	675	* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
<>	128:9bcdf88f62b0	676	*/
<>	128:9bcdf88f62b0	677	__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	678	{
<>	128:9bcdf88f62b0	679	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
<>	128:9bcdf88f62b0	680	}
<>	128:9bcdf88f62b0	681
<>	128:9bcdf88f62b0	682	/**
<>	128:9bcdf88f62b0	683	* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
<>	128:9bcdf88f62b0	684	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	685	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	686	* @rmtoll CR2 CPHA LL_USART_SetClockPhase
<>	128:9bcdf88f62b0	687	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	688	* @param ClockPhase This parameter can be one of the following values:
<>	128:9bcdf88f62b0	689	* @arg @ref LL_USART_PHASE_1EDGE
<>	128:9bcdf88f62b0	690	* @arg @ref LL_USART_PHASE_2EDGE
<>	128:9bcdf88f62b0	691	* @retval None
<>	128:9bcdf88f62b0	692	*/
<>	128:9bcdf88f62b0	693	__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
<>	128:9bcdf88f62b0	694	{
<>	128:9bcdf88f62b0	695	MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
<>	128:9bcdf88f62b0	696	}
<>	128:9bcdf88f62b0	697
<>	128:9bcdf88f62b0	698	/**
<>	128:9bcdf88f62b0	699	* @brief Return phase of the clock output on the SCLK pin in synchronous mode
<>	128:9bcdf88f62b0	700	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	701	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	702	* @rmtoll CR2 CPHA LL_USART_GetClockPhase
<>	128:9bcdf88f62b0	703	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	704	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	705	* @arg @ref LL_USART_PHASE_1EDGE
<>	128:9bcdf88f62b0	706	* @arg @ref LL_USART_PHASE_2EDGE
<>	128:9bcdf88f62b0	707	*/
<>	128:9bcdf88f62b0	708	__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	709	{
<>	128:9bcdf88f62b0	710	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
<>	128:9bcdf88f62b0	711	}
<>	128:9bcdf88f62b0	712
<>	128:9bcdf88f62b0	713	/**
<>	128:9bcdf88f62b0	714	* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
<>	128:9bcdf88f62b0	715	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	716	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	717	* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
<>	128:9bcdf88f62b0	718	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	719	* @param ClockPolarity This parameter can be one of the following values:
<>	128:9bcdf88f62b0	720	* @arg @ref LL_USART_POLARITY_LOW
<>	128:9bcdf88f62b0	721	* @arg @ref LL_USART_POLARITY_HIGH
<>	128:9bcdf88f62b0	722	* @retval None
<>	128:9bcdf88f62b0	723	*/
<>	128:9bcdf88f62b0	724	__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
<>	128:9bcdf88f62b0	725	{
<>	128:9bcdf88f62b0	726	MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
<>	128:9bcdf88f62b0	727	}
<>	128:9bcdf88f62b0	728
<>	128:9bcdf88f62b0	729	/**
<>	128:9bcdf88f62b0	730	* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
<>	128:9bcdf88f62b0	731	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	732	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	733	* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
<>	128:9bcdf88f62b0	734	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	735	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	736	* @arg @ref LL_USART_POLARITY_LOW
<>	128:9bcdf88f62b0	737	* @arg @ref LL_USART_POLARITY_HIGH
<>	128:9bcdf88f62b0	738	*/
<>	128:9bcdf88f62b0	739	__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	740	{
<>	128:9bcdf88f62b0	741	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
<>	128:9bcdf88f62b0	742	}
<>	128:9bcdf88f62b0	743
<>	128:9bcdf88f62b0	744	/**
<>	128:9bcdf88f62b0	745	* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
<>	128:9bcdf88f62b0	746	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	747	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	748	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	749	* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
<>	128:9bcdf88f62b0	750	* - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
<>	128:9bcdf88f62b0	751	* - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
<>	128:9bcdf88f62b0	752	* @rmtoll CR2 CPHA LL_USART_ConfigClock\n
<>	128:9bcdf88f62b0	753	* CR2 CPOL LL_USART_ConfigClock\n
<>	128:9bcdf88f62b0	754	* CR2 LBCL LL_USART_ConfigClock
<>	128:9bcdf88f62b0	755	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	756	* @param Phase This parameter can be one of the following values:
<>	128:9bcdf88f62b0	757	* @arg @ref LL_USART_PHASE_1EDGE
<>	128:9bcdf88f62b0	758	* @arg @ref LL_USART_PHASE_2EDGE
<>	128:9bcdf88f62b0	759	* @param Polarity This parameter can be one of the following values:
<>	128:9bcdf88f62b0	760	* @arg @ref LL_USART_POLARITY_LOW
<>	128:9bcdf88f62b0	761	* @arg @ref LL_USART_POLARITY_HIGH
<>	128:9bcdf88f62b0	762	* @param LBCPOutput This parameter can be one of the following values:
<>	128:9bcdf88f62b0	763	* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
<>	128:9bcdf88f62b0	764	* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
<>	128:9bcdf88f62b0	765	* @retval None
<>	128:9bcdf88f62b0	766	*/
<>	128:9bcdf88f62b0	767	__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
<>	128:9bcdf88f62b0	768	{
<>	128:9bcdf88f62b0	769	MODIFY_REG(USARTx->CR2, USART_CR2_CPHA \| USART_CR2_CPOL \| USART_CR2_LBCL, Phase \| Polarity \| LBCPOutput);
<>	128:9bcdf88f62b0	770	}
<>	128:9bcdf88f62b0	771
<>	128:9bcdf88f62b0	772	/**
<>	128:9bcdf88f62b0	773	* @brief Enable Clock output on SCLK pin
<>	128:9bcdf88f62b0	774	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	775	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	776	* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
<>	128:9bcdf88f62b0	777	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	778	* @retval None
<>	128:9bcdf88f62b0	779	*/
<>	128:9bcdf88f62b0	780	__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	781	{
<>	128:9bcdf88f62b0	782	SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
<>	128:9bcdf88f62b0	783	}
<>	128:9bcdf88f62b0	784
<>	128:9bcdf88f62b0	785	/**
<>	128:9bcdf88f62b0	786	* @brief Disable Clock output on SCLK pin
<>	128:9bcdf88f62b0	787	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	788	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	789	* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
<>	128:9bcdf88f62b0	790	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	791	* @retval None
<>	128:9bcdf88f62b0	792	*/
<>	128:9bcdf88f62b0	793	__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	794	{
<>	128:9bcdf88f62b0	795	CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
<>	128:9bcdf88f62b0	796	}
<>	128:9bcdf88f62b0	797
<>	128:9bcdf88f62b0	798	/**
<>	128:9bcdf88f62b0	799	* @brief Indicate if Clock output on SCLK pin is enabled
<>	128:9bcdf88f62b0	800	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	801	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	802	* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
<>	128:9bcdf88f62b0	803	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	804	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	805	*/
<>	128:9bcdf88f62b0	806	__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	807	{
<>	128:9bcdf88f62b0	808	return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
<>	128:9bcdf88f62b0	809	}
<>	128:9bcdf88f62b0	810
<>	128:9bcdf88f62b0	811	/**
<>	128:9bcdf88f62b0	812	* @brief Set the length of the stop bits
<>	128:9bcdf88f62b0	813	* @rmtoll CR2 STOP LL_USART_SetStopBitsLength
<>	128:9bcdf88f62b0	814	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	815	* @param StopBits This parameter can be one of the following values:
<>	128:9bcdf88f62b0	816	* @arg @ref LL_USART_STOPBITS_0_5
<>	128:9bcdf88f62b0	817	* @arg @ref LL_USART_STOPBITS_1
<>	128:9bcdf88f62b0	818	* @arg @ref LL_USART_STOPBITS_1_5
<>	128:9bcdf88f62b0	819	* @arg @ref LL_USART_STOPBITS_2
<>	128:9bcdf88f62b0	820	* @retval None
<>	128:9bcdf88f62b0	821	*/
<>	128:9bcdf88f62b0	822	__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
<>	128:9bcdf88f62b0	823	{
<>	128:9bcdf88f62b0	824	MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
<>	128:9bcdf88f62b0	825	}
<>	128:9bcdf88f62b0	826
<>	128:9bcdf88f62b0	827	/**
<>	128:9bcdf88f62b0	828	* @brief Retrieve the length of the stop bits
<>	128:9bcdf88f62b0	829	* @rmtoll CR2 STOP LL_USART_GetStopBitsLength
<>	128:9bcdf88f62b0	830	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	831	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	832	* @arg @ref LL_USART_STOPBITS_0_5
<>	128:9bcdf88f62b0	833	* @arg @ref LL_USART_STOPBITS_1
<>	128:9bcdf88f62b0	834	* @arg @ref LL_USART_STOPBITS_1_5
<>	128:9bcdf88f62b0	835	* @arg @ref LL_USART_STOPBITS_2
<>	128:9bcdf88f62b0	836	*/
<>	128:9bcdf88f62b0	837	__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	838	{
<>	128:9bcdf88f62b0	839	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
<>	128:9bcdf88f62b0	840	}
<>	128:9bcdf88f62b0	841
<>	128:9bcdf88f62b0	842	/**
<>	128:9bcdf88f62b0	843	* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
<>	128:9bcdf88f62b0	844	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	845	* - Data Width configuration using @ref LL_USART_SetDataWidth() function
<>	128:9bcdf88f62b0	846	* - Parity Control and mode configuration using @ref LL_USART_SetParity() function
<>	128:9bcdf88f62b0	847	* - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
<>	128:9bcdf88f62b0	848	* @rmtoll CR1 PS LL_USART_ConfigCharacter\n
<>	128:9bcdf88f62b0	849	* CR1 PCE LL_USART_ConfigCharacter\n
<>	128:9bcdf88f62b0	850	* CR1 M LL_USART_ConfigCharacter\n
<>	128:9bcdf88f62b0	851	* CR2 STOP LL_USART_ConfigCharacter
<>	128:9bcdf88f62b0	852	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	853	* @param DataWidth This parameter can be one of the following values:
<>	128:9bcdf88f62b0	854	* @arg @ref LL_USART_DATAWIDTH_8B
<>	128:9bcdf88f62b0	855	* @arg @ref LL_USART_DATAWIDTH_9B
<>	128:9bcdf88f62b0	856	* @param Parity This parameter can be one of the following values:
<>	128:9bcdf88f62b0	857	* @arg @ref LL_USART_PARITY_NONE
<>	128:9bcdf88f62b0	858	* @arg @ref LL_USART_PARITY_EVEN
<>	128:9bcdf88f62b0	859	* @arg @ref LL_USART_PARITY_ODD
<>	128:9bcdf88f62b0	860	* @param StopBits This parameter can be one of the following values:
<>	128:9bcdf88f62b0	861	* @arg @ref LL_USART_STOPBITS_0_5
<>	128:9bcdf88f62b0	862	* @arg @ref LL_USART_STOPBITS_1
<>	128:9bcdf88f62b0	863	* @arg @ref LL_USART_STOPBITS_1_5
<>	128:9bcdf88f62b0	864	* @arg @ref LL_USART_STOPBITS_2
<>	128:9bcdf88f62b0	865	* @retval None
<>	128:9bcdf88f62b0	866	*/
<>	128:9bcdf88f62b0	867	__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
<>	128:9bcdf88f62b0	868	uint32_t StopBits)
<>	128:9bcdf88f62b0	869	{
<>	128:9bcdf88f62b0	870	MODIFY_REG(USARTx->CR1, USART_CR1_PS \| USART_CR1_PCE \| USART_CR1_M, Parity \| DataWidth);
<>	128:9bcdf88f62b0	871	MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
<>	128:9bcdf88f62b0	872	}
<>	128:9bcdf88f62b0	873
<>	128:9bcdf88f62b0	874	/**
<>	128:9bcdf88f62b0	875	* @brief Set Address of the USART node.
<>	128:9bcdf88f62b0	876	* @note This is used in multiprocessor communication during Mute mode or Stop mode,
<>	128:9bcdf88f62b0	877	* for wake up with address mark detection.
<>	128:9bcdf88f62b0	878	* @rmtoll CR2 ADD LL_USART_SetNodeAddress
<>	128:9bcdf88f62b0	879	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	880	* @param NodeAddress 4 bit Address of the USART node.
<>	128:9bcdf88f62b0	881	* @retval None
<>	128:9bcdf88f62b0	882	*/
<>	128:9bcdf88f62b0	883	__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
<>	128:9bcdf88f62b0	884	{
<>	128:9bcdf88f62b0	885	MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
<>	128:9bcdf88f62b0	886	}
<>	128:9bcdf88f62b0	887
<>	128:9bcdf88f62b0	888	/**
<>	128:9bcdf88f62b0	889	* @brief Return 4 bit Address of the USART node as set in ADD field of CR2.
<>	128:9bcdf88f62b0	890	* @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
<>	128:9bcdf88f62b0	891	* @rmtoll CR2 ADD LL_USART_GetNodeAddress
<>	128:9bcdf88f62b0	892	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	893	* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
<>	128:9bcdf88f62b0	894	*/
<>	128:9bcdf88f62b0	895	__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	896	{
<>	128:9bcdf88f62b0	897	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
<>	128:9bcdf88f62b0	898	}
<>	128:9bcdf88f62b0	899
<>	128:9bcdf88f62b0	900	/**
<>	128:9bcdf88f62b0	901	* @brief Enable RTS HW Flow Control
<>	128:9bcdf88f62b0	902	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	903	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	904	* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
<>	128:9bcdf88f62b0	905	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	906	* @retval None
<>	128:9bcdf88f62b0	907	*/
<>	128:9bcdf88f62b0	908	__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	909	{
<>	128:9bcdf88f62b0	910	SET_BIT(USARTx->CR3, USART_CR3_RTSE);
<>	128:9bcdf88f62b0	911	}
<>	128:9bcdf88f62b0	912
<>	128:9bcdf88f62b0	913	/**
<>	128:9bcdf88f62b0	914	* @brief Disable RTS HW Flow Control
<>	128:9bcdf88f62b0	915	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	916	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	917	* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
<>	128:9bcdf88f62b0	918	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	919	* @retval None
<>	128:9bcdf88f62b0	920	*/
<>	128:9bcdf88f62b0	921	__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	922	{
<>	128:9bcdf88f62b0	923	CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
<>	128:9bcdf88f62b0	924	}
<>	128:9bcdf88f62b0	925
<>	128:9bcdf88f62b0	926	/**
<>	128:9bcdf88f62b0	927	* @brief Enable CTS HW Flow Control
<>	128:9bcdf88f62b0	928	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	929	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	930	* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
<>	128:9bcdf88f62b0	931	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	932	* @retval None
<>	128:9bcdf88f62b0	933	*/
<>	128:9bcdf88f62b0	934	__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	935	{
<>	128:9bcdf88f62b0	936	SET_BIT(USARTx->CR3, USART_CR3_CTSE);
<>	128:9bcdf88f62b0	937	}
<>	128:9bcdf88f62b0	938
<>	128:9bcdf88f62b0	939	/**
<>	128:9bcdf88f62b0	940	* @brief Disable CTS HW Flow Control
<>	128:9bcdf88f62b0	941	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	942	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	943	* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
<>	128:9bcdf88f62b0	944	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	945	* @retval None
<>	128:9bcdf88f62b0	946	*/
<>	128:9bcdf88f62b0	947	__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	948	{
<>	128:9bcdf88f62b0	949	CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
<>	128:9bcdf88f62b0	950	}
<>	128:9bcdf88f62b0	951
<>	128:9bcdf88f62b0	952	/**
<>	128:9bcdf88f62b0	953	* @brief Configure HW Flow Control mode (both CTS and RTS)
<>	128:9bcdf88f62b0	954	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	955	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	956	* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
<>	128:9bcdf88f62b0	957	* CR3 CTSE LL_USART_SetHWFlowCtrl
<>	128:9bcdf88f62b0	958	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	959	* @param HardwareFlowControl This parameter can be one of the following values:
<>	128:9bcdf88f62b0	960	* @arg @ref LL_USART_HWCONTROL_NONE
<>	128:9bcdf88f62b0	961	* @arg @ref LL_USART_HWCONTROL_RTS
<>	128:9bcdf88f62b0	962	* @arg @ref LL_USART_HWCONTROL_CTS
<>	128:9bcdf88f62b0	963	* @arg @ref LL_USART_HWCONTROL_RTS_CTS
<>	128:9bcdf88f62b0	964	* @retval None
<>	128:9bcdf88f62b0	965	*/
<>	128:9bcdf88f62b0	966	__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
<>	128:9bcdf88f62b0	967	{
<>	128:9bcdf88f62b0	968	MODIFY_REG(USARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE, HardwareFlowControl);
<>	128:9bcdf88f62b0	969	}
<>	128:9bcdf88f62b0	970
<>	128:9bcdf88f62b0	971	/**
<>	128:9bcdf88f62b0	972	* @brief Return HW Flow Control configuration (both CTS and RTS)
<>	128:9bcdf88f62b0	973	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	974	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	975	* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
<>	128:9bcdf88f62b0	976	* CR3 CTSE LL_USART_GetHWFlowCtrl
<>	128:9bcdf88f62b0	977	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	978	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	979	* @arg @ref LL_USART_HWCONTROL_NONE
<>	128:9bcdf88f62b0	980	* @arg @ref LL_USART_HWCONTROL_RTS
<>	128:9bcdf88f62b0	981	* @arg @ref LL_USART_HWCONTROL_CTS
<>	128:9bcdf88f62b0	982	* @arg @ref LL_USART_HWCONTROL_RTS_CTS
<>	128:9bcdf88f62b0	983	*/
<>	128:9bcdf88f62b0	984	__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	985	{
<>	128:9bcdf88f62b0	986	return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE));
<>	128:9bcdf88f62b0	987	}
<>	128:9bcdf88f62b0	988
<>	128:9bcdf88f62b0	989	/**
<>	128:9bcdf88f62b0	990	* @brief Enable One bit sampling method
<>	128:9bcdf88f62b0	991	* @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
<>	128:9bcdf88f62b0	992	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	993	* @retval None
<>	128:9bcdf88f62b0	994	*/
<>	128:9bcdf88f62b0	995	__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	996	{
<>	128:9bcdf88f62b0	997	SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
<>	128:9bcdf88f62b0	998	}
<>	128:9bcdf88f62b0	999
<>	128:9bcdf88f62b0	1000	/**
<>	128:9bcdf88f62b0	1001	* @brief Disable One bit sampling method
<>	128:9bcdf88f62b0	1002	* @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
<>	128:9bcdf88f62b0	1003	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1004	* @retval None
<>	128:9bcdf88f62b0	1005	*/
<>	128:9bcdf88f62b0	1006	__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1007	{
<>	128:9bcdf88f62b0	1008	CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
<>	128:9bcdf88f62b0	1009	}
<>	128:9bcdf88f62b0	1010
<>	128:9bcdf88f62b0	1011	/**
<>	128:9bcdf88f62b0	1012	* @brief Indicate if One bit sampling method is enabled
<>	128:9bcdf88f62b0	1013	* @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
<>	128:9bcdf88f62b0	1014	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1015	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1016	*/
<>	128:9bcdf88f62b0	1017	__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1018	{
<>	128:9bcdf88f62b0	1019	return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
<>	128:9bcdf88f62b0	1020	}
<>	128:9bcdf88f62b0	1021
<>	128:9bcdf88f62b0	1022	/**
<>	128:9bcdf88f62b0	1023	* @brief Configure USART BRR register for achieving expected Baud Rate value.
<>	128:9bcdf88f62b0	1024	* @note Compute and set USARTDIV value in BRR Register (full BRR content)
<>	128:9bcdf88f62b0	1025	* according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
<>	128:9bcdf88f62b0	1026	* @note Peripheral clock and Baud rate values provided as function parameters should be valid
<>	128:9bcdf88f62b0	1027	* (Baud rate value != 0)
<>	128:9bcdf88f62b0	1028	* @rmtoll BRR BRR LL_USART_SetBaudRate
<>	128:9bcdf88f62b0	1029	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1030	* @param PeriphClk Peripheral Clock
<>	128:9bcdf88f62b0	1031	* @param OverSampling This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1032	* @arg @ref LL_USART_OVERSAMPLING_16
<>	128:9bcdf88f62b0	1033	* @arg @ref LL_USART_OVERSAMPLING_8
<>	128:9bcdf88f62b0	1034	* @param BaudRate Baud Rate
<>	128:9bcdf88f62b0	1035	* @retval None
<>	128:9bcdf88f62b0	1036	*/
<>	128:9bcdf88f62b0	1037	__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
<>	128:9bcdf88f62b0	1038	uint32_t BaudRate)
<>	128:9bcdf88f62b0	1039	{
<>	128:9bcdf88f62b0	1040	if (OverSampling == LL_USART_OVERSAMPLING_8)
<>	128:9bcdf88f62b0	1041	{
<>	128:9bcdf88f62b0	1042	USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
<>	128:9bcdf88f62b0	1043	}
<>	128:9bcdf88f62b0	1044	else
<>	128:9bcdf88f62b0	1045	{
<>	128:9bcdf88f62b0	1046	USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
<>	128:9bcdf88f62b0	1047	}
<>	128:9bcdf88f62b0	1048	}
<>	128:9bcdf88f62b0	1049
<>	128:9bcdf88f62b0	1050	/**
<>	128:9bcdf88f62b0	1051	* @brief Return current Baud Rate value, according to USARTDIV present in BRR register
<>	128:9bcdf88f62b0	1052	* (full BRR content), and to used Peripheral Clock and Oversampling mode values
<>	128:9bcdf88f62b0	1053	* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
<>	128:9bcdf88f62b0	1054	* @rmtoll BRR BRR LL_USART_GetBaudRate
<>	128:9bcdf88f62b0	1055	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1056	* @param PeriphClk Peripheral Clock
<>	128:9bcdf88f62b0	1057	* @param OverSampling This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1058	* @arg @ref LL_USART_OVERSAMPLING_16
<>	128:9bcdf88f62b0	1059	* @arg @ref LL_USART_OVERSAMPLING_8
<>	128:9bcdf88f62b0	1060	* @retval Baud Rate
<>	128:9bcdf88f62b0	1061	*/
<>	128:9bcdf88f62b0	1062	__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
<>	128:9bcdf88f62b0	1063	{
<>	128:9bcdf88f62b0	1064	register uint32_t usartdiv = 0x0U;
<>	128:9bcdf88f62b0	1065	register uint32_t brrresult = 0x0U;
<>	128:9bcdf88f62b0	1066
<>	128:9bcdf88f62b0	1067	usartdiv = USARTx->BRR;
<>	128:9bcdf88f62b0	1068
<>	128:9bcdf88f62b0	1069	if (OverSampling == LL_USART_OVERSAMPLING_8)
<>	128:9bcdf88f62b0	1070	{
<>	128:9bcdf88f62b0	1071	if ((usartdiv & 0xFFF7U) != 0U)
<>	128:9bcdf88f62b0	1072	{
<>	128:9bcdf88f62b0	1073	usartdiv = (uint16_t)((usartdiv & 0xFFF0U) \| ((usartdiv & 0x0007U) << 1U)) ;
<>	128:9bcdf88f62b0	1074	brrresult = (PeriphClk * 2U) / usartdiv;
<>	128:9bcdf88f62b0	1075	}
<>	128:9bcdf88f62b0	1076	}
<>	128:9bcdf88f62b0	1077	else
<>	128:9bcdf88f62b0	1078	{
<>	128:9bcdf88f62b0	1079	if ((usartdiv & 0xFFFFU) != 0U)
<>	128:9bcdf88f62b0	1080	{
<>	128:9bcdf88f62b0	1081	brrresult = PeriphClk / usartdiv;
<>	128:9bcdf88f62b0	1082	}
<>	128:9bcdf88f62b0	1083	}
<>	128:9bcdf88f62b0	1084	return (brrresult);
<>	128:9bcdf88f62b0	1085	}
<>	128:9bcdf88f62b0	1086
<>	128:9bcdf88f62b0	1087	/**
<>	128:9bcdf88f62b0	1088	* @}
<>	128:9bcdf88f62b0	1089	*/
<>	128:9bcdf88f62b0	1090
<>	128:9bcdf88f62b0	1091	/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
<>	128:9bcdf88f62b0	1092	* @{
<>	128:9bcdf88f62b0	1093	*/
<>	128:9bcdf88f62b0	1094
<>	128:9bcdf88f62b0	1095	/**
<>	128:9bcdf88f62b0	1096	* @brief Enable IrDA mode
<>	128:9bcdf88f62b0	1097	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1098	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1099	* @rmtoll CR3 IREN LL_USART_EnableIrda
<>	128:9bcdf88f62b0	1100	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1101	* @retval None
<>	128:9bcdf88f62b0	1102	*/
<>	128:9bcdf88f62b0	1103	__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1104	{
<>	128:9bcdf88f62b0	1105	SET_BIT(USARTx->CR3, USART_CR3_IREN);
<>	128:9bcdf88f62b0	1106	}
<>	128:9bcdf88f62b0	1107
<>	128:9bcdf88f62b0	1108	/**
<>	128:9bcdf88f62b0	1109	* @brief Disable IrDA mode
<>	128:9bcdf88f62b0	1110	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1111	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1112	* @rmtoll CR3 IREN LL_USART_DisableIrda
<>	128:9bcdf88f62b0	1113	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1114	* @retval None
<>	128:9bcdf88f62b0	1115	*/
<>	128:9bcdf88f62b0	1116	__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1117	{
<>	128:9bcdf88f62b0	1118	CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
<>	128:9bcdf88f62b0	1119	}
<>	128:9bcdf88f62b0	1120
<>	128:9bcdf88f62b0	1121	/**
<>	128:9bcdf88f62b0	1122	* @brief Indicate if IrDA mode is enabled
<>	128:9bcdf88f62b0	1123	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1124	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1125	* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
<>	128:9bcdf88f62b0	1126	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1127	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1128	*/
<>	128:9bcdf88f62b0	1129	__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1130	{
<>	128:9bcdf88f62b0	1131	return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
<>	128:9bcdf88f62b0	1132	}
<>	128:9bcdf88f62b0	1133
<>	128:9bcdf88f62b0	1134	/**
<>	128:9bcdf88f62b0	1135	* @brief Configure IrDA Power Mode (Normal or Low Power)
<>	128:9bcdf88f62b0	1136	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1137	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1138	* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
<>	128:9bcdf88f62b0	1139	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1140	* @param PowerMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1141	* @arg @ref LL_USART_IRDA_POWER_NORMAL
<>	128:9bcdf88f62b0	1142	* @arg @ref LL_USART_IRDA_POWER_LOW
<>	128:9bcdf88f62b0	1143	* @retval None
<>	128:9bcdf88f62b0	1144	*/
<>	128:9bcdf88f62b0	1145	__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
<>	128:9bcdf88f62b0	1146	{
<>	128:9bcdf88f62b0	1147	MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
<>	128:9bcdf88f62b0	1148	}
<>	128:9bcdf88f62b0	1149
<>	128:9bcdf88f62b0	1150	/**
<>	128:9bcdf88f62b0	1151	* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
<>	128:9bcdf88f62b0	1152	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1153	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1154	* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
<>	128:9bcdf88f62b0	1155	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1156	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1157	* @arg @ref LL_USART_IRDA_POWER_NORMAL
<>	128:9bcdf88f62b0	1158	* @arg @ref LL_USART_PHASE_2EDGE
<>	128:9bcdf88f62b0	1159	*/
<>	128:9bcdf88f62b0	1160	__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1161	{
<>	128:9bcdf88f62b0	1162	return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
<>	128:9bcdf88f62b0	1163	}
<>	128:9bcdf88f62b0	1164
<>	128:9bcdf88f62b0	1165	/**
<>	128:9bcdf88f62b0	1166	* @brief Set Irda prescaler value, used for dividing the USART clock source
<>	128:9bcdf88f62b0	1167	* to achieve the Irda Low Power frequency (8 bits value)
<>	128:9bcdf88f62b0	1168	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1169	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1170	* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
<>	128:9bcdf88f62b0	1171	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1172	* @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	1173	* @retval None
<>	128:9bcdf88f62b0	1174	*/
<>	128:9bcdf88f62b0	1175	__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
<>	128:9bcdf88f62b0	1176	{
<>	128:9bcdf88f62b0	1177	MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
<>	128:9bcdf88f62b0	1178	}
<>	128:9bcdf88f62b0	1179
<>	128:9bcdf88f62b0	1180	/**
<>	128:9bcdf88f62b0	1181	* @brief Return Irda prescaler value, used for dividing the USART clock source
<>	128:9bcdf88f62b0	1182	* to achieve the Irda Low Power frequency (8 bits value)
<>	128:9bcdf88f62b0	1183	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1184	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1185	* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
<>	128:9bcdf88f62b0	1186	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1187	* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
<>	128:9bcdf88f62b0	1188	*/
<>	128:9bcdf88f62b0	1189	__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1190	{
<>	128:9bcdf88f62b0	1191	return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
<>	128:9bcdf88f62b0	1192	}
<>	128:9bcdf88f62b0	1193
<>	128:9bcdf88f62b0	1194	/**
<>	128:9bcdf88f62b0	1195	* @}
<>	128:9bcdf88f62b0	1196	*/
<>	128:9bcdf88f62b0	1197
<>	128:9bcdf88f62b0	1198	/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
<>	128:9bcdf88f62b0	1199	* @{
<>	128:9bcdf88f62b0	1200	*/
<>	128:9bcdf88f62b0	1201
<>	128:9bcdf88f62b0	1202	/**
<>	128:9bcdf88f62b0	1203	* @brief Enable Smartcard NACK transmission
<>	128:9bcdf88f62b0	1204	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1205	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1206	* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
<>	128:9bcdf88f62b0	1207	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1208	* @retval None
<>	128:9bcdf88f62b0	1209	*/
<>	128:9bcdf88f62b0	1210	__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1211	{
<>	128:9bcdf88f62b0	1212	SET_BIT(USARTx->CR3, USART_CR3_NACK);
<>	128:9bcdf88f62b0	1213	}
<>	128:9bcdf88f62b0	1214
<>	128:9bcdf88f62b0	1215	/**
<>	128:9bcdf88f62b0	1216	* @brief Disable Smartcard NACK transmission
<>	128:9bcdf88f62b0	1217	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1218	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1219	* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
<>	128:9bcdf88f62b0	1220	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1221	* @retval None
<>	128:9bcdf88f62b0	1222	*/
<>	128:9bcdf88f62b0	1223	__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1224	{
<>	128:9bcdf88f62b0	1225	CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
<>	128:9bcdf88f62b0	1226	}
<>	128:9bcdf88f62b0	1227
<>	128:9bcdf88f62b0	1228	/**
<>	128:9bcdf88f62b0	1229	* @brief Indicate if Smartcard NACK transmission is enabled
<>	128:9bcdf88f62b0	1230	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1231	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1232	* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
<>	128:9bcdf88f62b0	1233	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1234	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1235	*/
<>	128:9bcdf88f62b0	1236	__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1237	{
<>	128:9bcdf88f62b0	1238	return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
<>	128:9bcdf88f62b0	1239	}
<>	128:9bcdf88f62b0	1240
<>	128:9bcdf88f62b0	1241	/**
<>	128:9bcdf88f62b0	1242	* @brief Enable Smartcard mode
<>	128:9bcdf88f62b0	1243	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1244	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1245	* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
<>	128:9bcdf88f62b0	1246	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1247	* @retval None
<>	128:9bcdf88f62b0	1248	*/
<>	128:9bcdf88f62b0	1249	__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1250	{
<>	128:9bcdf88f62b0	1251	SET_BIT(USARTx->CR3, USART_CR3_SCEN);
<>	128:9bcdf88f62b0	1252	}
<>	128:9bcdf88f62b0	1253
<>	128:9bcdf88f62b0	1254	/**
<>	128:9bcdf88f62b0	1255	* @brief Disable Smartcard mode
<>	128:9bcdf88f62b0	1256	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1257	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1258	* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
<>	128:9bcdf88f62b0	1259	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1260	* @retval None
<>	128:9bcdf88f62b0	1261	*/
<>	128:9bcdf88f62b0	1262	__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1263	{
<>	128:9bcdf88f62b0	1264	CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
<>	128:9bcdf88f62b0	1265	}
<>	128:9bcdf88f62b0	1266
<>	128:9bcdf88f62b0	1267	/**
<>	128:9bcdf88f62b0	1268	* @brief Indicate if Smartcard mode is enabled
<>	128:9bcdf88f62b0	1269	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1270	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1271	* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
<>	128:9bcdf88f62b0	1272	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1273	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1274	*/
<>	128:9bcdf88f62b0	1275	__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1276	{
<>	128:9bcdf88f62b0	1277	return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
<>	128:9bcdf88f62b0	1278	}
<>	128:9bcdf88f62b0	1279
<>	128:9bcdf88f62b0	1280	/**
<>	128:9bcdf88f62b0	1281	* @brief Set Smartcard prescaler value, used for dividing the USART clock
<>	128:9bcdf88f62b0	1282	* source to provide the SMARTCARD Clock (5 bits value)
<>	128:9bcdf88f62b0	1283	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1284	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1285	* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
<>	128:9bcdf88f62b0	1286	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1287	* @param PrescalerValue Value between Min_Data=0 and Max_Data=31
<>	128:9bcdf88f62b0	1288	* @retval None
<>	128:9bcdf88f62b0	1289	*/
<>	128:9bcdf88f62b0	1290	__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
<>	128:9bcdf88f62b0	1291	{
<>	128:9bcdf88f62b0	1292	MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
<>	128:9bcdf88f62b0	1293	}
<>	128:9bcdf88f62b0	1294
<>	128:9bcdf88f62b0	1295	/**
<>	128:9bcdf88f62b0	1296	* @brief Return Smartcard prescaler value, used for dividing the USART clock
<>	128:9bcdf88f62b0	1297	* source to provide the SMARTCARD Clock (5 bits value)
<>	128:9bcdf88f62b0	1298	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1299	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1300	* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
<>	128:9bcdf88f62b0	1301	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1302	* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
<>	128:9bcdf88f62b0	1303	*/
<>	128:9bcdf88f62b0	1304	__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1305	{
<>	128:9bcdf88f62b0	1306	return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
<>	128:9bcdf88f62b0	1307	}
<>	128:9bcdf88f62b0	1308
<>	128:9bcdf88f62b0	1309	/**
<>	128:9bcdf88f62b0	1310	* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
<>	128:9bcdf88f62b0	1311	* (GT[7:0] bits : Guard time value)
<>	128:9bcdf88f62b0	1312	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1313	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1314	* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
<>	128:9bcdf88f62b0	1315	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1316	* @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	1317	* @retval None
<>	128:9bcdf88f62b0	1318	*/
<>	128:9bcdf88f62b0	1319	__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
<>	128:9bcdf88f62b0	1320	{
<>	128:9bcdf88f62b0	1321	MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
<>	128:9bcdf88f62b0	1322	}
<>	128:9bcdf88f62b0	1323
<>	128:9bcdf88f62b0	1324	/**
<>	128:9bcdf88f62b0	1325	* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
<>	128:9bcdf88f62b0	1326	* (GT[7:0] bits : Guard time value)
<>	128:9bcdf88f62b0	1327	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1328	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1329	* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
<>	128:9bcdf88f62b0	1330	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1331	* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
<>	128:9bcdf88f62b0	1332	*/
<>	128:9bcdf88f62b0	1333	__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1334	{
<>	128:9bcdf88f62b0	1335	return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
<>	128:9bcdf88f62b0	1336	}
<>	128:9bcdf88f62b0	1337
<>	128:9bcdf88f62b0	1338	/**
<>	128:9bcdf88f62b0	1339	* @}
<>	128:9bcdf88f62b0	1340	*/
<>	128:9bcdf88f62b0	1341
<>	128:9bcdf88f62b0	1342	/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
<>	128:9bcdf88f62b0	1343	* @{
<>	128:9bcdf88f62b0	1344	*/
<>	128:9bcdf88f62b0	1345
<>	128:9bcdf88f62b0	1346	/**
<>	128:9bcdf88f62b0	1347	* @brief Enable Single Wire Half-Duplex mode
<>	128:9bcdf88f62b0	1348	* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1349	* Half-Duplex mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1350	* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
<>	128:9bcdf88f62b0	1351	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1352	* @retval None
<>	128:9bcdf88f62b0	1353	*/
<>	128:9bcdf88f62b0	1354	__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1355	{
<>	128:9bcdf88f62b0	1356	SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
<>	128:9bcdf88f62b0	1357	}
<>	128:9bcdf88f62b0	1358
<>	128:9bcdf88f62b0	1359	/**
<>	128:9bcdf88f62b0	1360	* @brief Disable Single Wire Half-Duplex mode
<>	128:9bcdf88f62b0	1361	* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1362	* Half-Duplex mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1363	* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
<>	128:9bcdf88f62b0	1364	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1365	* @retval None
<>	128:9bcdf88f62b0	1366	*/
<>	128:9bcdf88f62b0	1367	__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1368	{
<>	128:9bcdf88f62b0	1369	CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
<>	128:9bcdf88f62b0	1370	}
<>	128:9bcdf88f62b0	1371
<>	128:9bcdf88f62b0	1372	/**
<>	128:9bcdf88f62b0	1373	* @brief Indicate if Single Wire Half-Duplex mode is enabled
<>	128:9bcdf88f62b0	1374	* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1375	* Half-Duplex mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1376	* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
<>	128:9bcdf88f62b0	1377	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1378	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1379	*/
<>	128:9bcdf88f62b0	1380	__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1381	{
<>	128:9bcdf88f62b0	1382	return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1383	}
<>	128:9bcdf88f62b0	1384
<>	128:9bcdf88f62b0	1385	/**
<>	128:9bcdf88f62b0	1386	* @}
<>	128:9bcdf88f62b0	1387	*/
<>	128:9bcdf88f62b0	1388
<>	128:9bcdf88f62b0	1389	/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
<>	128:9bcdf88f62b0	1390	* @{
<>	128:9bcdf88f62b0	1391	*/
<>	128:9bcdf88f62b0	1392
<>	128:9bcdf88f62b0	1393	/**
<>	128:9bcdf88f62b0	1394	* @brief Set LIN Break Detection Length
<>	128:9bcdf88f62b0	1395	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1396	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1397	* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
<>	128:9bcdf88f62b0	1398	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1399	* @param LINBDLength This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1400	* @arg @ref LL_USART_LINBREAK_DETECT_10B
<>	128:9bcdf88f62b0	1401	* @arg @ref LL_USART_LINBREAK_DETECT_11B
<>	128:9bcdf88f62b0	1402	* @retval None
<>	128:9bcdf88f62b0	1403	*/
<>	128:9bcdf88f62b0	1404	__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
<>	128:9bcdf88f62b0	1405	{
<>	128:9bcdf88f62b0	1406	MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
<>	128:9bcdf88f62b0	1407	}
<>	128:9bcdf88f62b0	1408
<>	128:9bcdf88f62b0	1409	/**
<>	128:9bcdf88f62b0	1410	* @brief Return LIN Break Detection Length
<>	128:9bcdf88f62b0	1411	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1412	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1413	* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
<>	128:9bcdf88f62b0	1414	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1415	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1416	* @arg @ref LL_USART_LINBREAK_DETECT_10B
<>	128:9bcdf88f62b0	1417	* @arg @ref LL_USART_LINBREAK_DETECT_11B
<>	128:9bcdf88f62b0	1418	*/
<>	128:9bcdf88f62b0	1419	__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1420	{
<>	128:9bcdf88f62b0	1421	return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
<>	128:9bcdf88f62b0	1422	}
<>	128:9bcdf88f62b0	1423
<>	128:9bcdf88f62b0	1424	/**
<>	128:9bcdf88f62b0	1425	* @brief Enable LIN mode
<>	128:9bcdf88f62b0	1426	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1427	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1428	* @rmtoll CR2 LINEN LL_USART_EnableLIN
<>	128:9bcdf88f62b0	1429	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1430	* @retval None
<>	128:9bcdf88f62b0	1431	*/
<>	128:9bcdf88f62b0	1432	__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1433	{
<>	128:9bcdf88f62b0	1434	SET_BIT(USARTx->CR2, USART_CR2_LINEN);
<>	128:9bcdf88f62b0	1435	}
<>	128:9bcdf88f62b0	1436
<>	128:9bcdf88f62b0	1437	/**
<>	128:9bcdf88f62b0	1438	* @brief Disable LIN mode
<>	128:9bcdf88f62b0	1439	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1440	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1441	* @rmtoll CR2 LINEN LL_USART_DisableLIN
<>	128:9bcdf88f62b0	1442	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1443	* @retval None
<>	128:9bcdf88f62b0	1444	*/
<>	128:9bcdf88f62b0	1445	__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1446	{
<>	128:9bcdf88f62b0	1447	CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
<>	128:9bcdf88f62b0	1448	}
<>	128:9bcdf88f62b0	1449
<>	128:9bcdf88f62b0	1450	/**
<>	128:9bcdf88f62b0	1451	* @brief Indicate if LIN mode is enabled
<>	128:9bcdf88f62b0	1452	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1453	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1454	* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
<>	128:9bcdf88f62b0	1455	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1456	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1457	*/
<>	128:9bcdf88f62b0	1458	__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1459	{
<>	128:9bcdf88f62b0	1460	return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
<>	128:9bcdf88f62b0	1461	}
<>	128:9bcdf88f62b0	1462
<>	128:9bcdf88f62b0	1463	/**
<>	128:9bcdf88f62b0	1464	* @}
<>	128:9bcdf88f62b0	1465	*/
<>	128:9bcdf88f62b0	1466
<>	128:9bcdf88f62b0	1467	/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
<>	128:9bcdf88f62b0	1468	* @{
<>	128:9bcdf88f62b0	1469	*/
<>	128:9bcdf88f62b0	1470
<>	128:9bcdf88f62b0	1471	/**
<>	128:9bcdf88f62b0	1472	* @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
<>	128:9bcdf88f62b0	1473	* @note In UART mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1474	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1475	* - CLKEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1476	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1477	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1478	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1479	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1480	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1481	* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
<>	128:9bcdf88f62b0	1482	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1483	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1484	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1485	* @note Other remaining configurations items related to Asynchronous Mode
<>	128:9bcdf88f62b0	1486	* (as Baud Rate, Word length, Parity, ...) should be set using
<>	128:9bcdf88f62b0	1487	* dedicated functions
<>	128:9bcdf88f62b0	1488	* @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
<>	128:9bcdf88f62b0	1489	* CR2 CLKEN LL_USART_ConfigAsyncMode\n
<>	128:9bcdf88f62b0	1490	* CR3 SCEN LL_USART_ConfigAsyncMode\n
<>	128:9bcdf88f62b0	1491	* CR3 IREN LL_USART_ConfigAsyncMode\n
<>	128:9bcdf88f62b0	1492	* CR3 HDSEL LL_USART_ConfigAsyncMode
<>	128:9bcdf88f62b0	1493	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1494	* @retval None
<>	128:9bcdf88f62b0	1495	*/
<>	128:9bcdf88f62b0	1496	__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1497	{
<>	128:9bcdf88f62b0	1498	/* In Asynchronous mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1499	- LINEN, CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1500	- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1501	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	128:9bcdf88f62b0	1502	CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN \| USART_CR3_IREN \| USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1503	}
<>	128:9bcdf88f62b0	1504
<>	128:9bcdf88f62b0	1505	/**
<>	128:9bcdf88f62b0	1506	* @brief Perform basic configuration of USART for enabling use in Synchronous Mode
<>	128:9bcdf88f62b0	1507	* @note In Synchronous mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1508	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1509	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1510	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1511	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1512	* This function also sets the USART in Synchronous mode.
<>	128:9bcdf88f62b0	1513	* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1514	* Synchronous mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1515	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1516	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1517	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1518	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1519	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1520	* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
<>	128:9bcdf88f62b0	1521	* @note Other remaining configurations items related to Synchronous Mode
<>	128:9bcdf88f62b0	1522	* (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
<>	128:9bcdf88f62b0	1523	* dedicated functions
<>	128:9bcdf88f62b0	1524	* @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
<>	128:9bcdf88f62b0	1525	* CR2 CLKEN LL_USART_ConfigSyncMode\n
<>	128:9bcdf88f62b0	1526	* CR3 SCEN LL_USART_ConfigSyncMode\n
<>	128:9bcdf88f62b0	1527	* CR3 IREN LL_USART_ConfigSyncMode\n
<>	128:9bcdf88f62b0	1528	* CR3 HDSEL LL_USART_ConfigSyncMode
<>	128:9bcdf88f62b0	1529	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1530	* @retval None
<>	128:9bcdf88f62b0	1531	*/
<>	128:9bcdf88f62b0	1532	__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1533	{
<>	128:9bcdf88f62b0	1534	/* In Synchronous mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1535	- LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1536	- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1537	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
<>	128:9bcdf88f62b0	1538	CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN \| USART_CR3_IREN \| USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1539	/* set the UART/USART in Synchronous mode */
<>	128:9bcdf88f62b0	1540	SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
<>	128:9bcdf88f62b0	1541	}
<>	128:9bcdf88f62b0	1542
<>	128:9bcdf88f62b0	1543	/**
<>	128:9bcdf88f62b0	1544	* @brief Perform basic configuration of USART for enabling use in LIN Mode
<>	128:9bcdf88f62b0	1545	* @note In LIN mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1546	* - STOP and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1547	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1548	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1549	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1550	* This function also set the UART/USART in LIN mode.
<>	128:9bcdf88f62b0	1551	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1552	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1553	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1554	* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
<>	128:9bcdf88f62b0	1555	* - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
<>	128:9bcdf88f62b0	1556	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1557	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1558	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1559	* - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
<>	128:9bcdf88f62b0	1560	* @note Other remaining configurations items related to LIN Mode
<>	128:9bcdf88f62b0	1561	* (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
<>	128:9bcdf88f62b0	1562	* dedicated functions
<>	128:9bcdf88f62b0	1563	* @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
<>	128:9bcdf88f62b0	1564	* CR2 STOP LL_USART_ConfigLINMode\n
<>	128:9bcdf88f62b0	1565	* CR2 LINEN LL_USART_ConfigLINMode\n
<>	128:9bcdf88f62b0	1566	* CR3 IREN LL_USART_ConfigLINMode\n
<>	128:9bcdf88f62b0	1567	* CR3 SCEN LL_USART_ConfigLINMode\n
<>	128:9bcdf88f62b0	1568	* CR3 HDSEL LL_USART_ConfigLINMode
<>	128:9bcdf88f62b0	1569	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1570	* @retval None
<>	128:9bcdf88f62b0	1571	*/
<>	128:9bcdf88f62b0	1572	__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1573	{
<>	128:9bcdf88f62b0	1574	/* In LIN mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1575	- STOP and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1576	- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1577	CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN \| USART_CR2_STOP));
<>	128:9bcdf88f62b0	1578	CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN \| USART_CR3_SCEN \| USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1579	/* Set the UART/USART in LIN mode */
<>	128:9bcdf88f62b0	1580	SET_BIT(USARTx->CR2, USART_CR2_LINEN);
<>	128:9bcdf88f62b0	1581	}
<>	128:9bcdf88f62b0	1582
<>	128:9bcdf88f62b0	1583	/**
<>	128:9bcdf88f62b0	1584	* @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
<>	128:9bcdf88f62b0	1585	* @note In Half Duplex mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1586	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1587	* - CLKEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1588	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1589	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1590	* This function also sets the UART/USART in Half Duplex mode.
<>	128:9bcdf88f62b0	1591	* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1592	* Half-Duplex mode is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1593	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1594	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1595	* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
<>	128:9bcdf88f62b0	1596	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1597	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1598	* - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
<>	128:9bcdf88f62b0	1599	* @note Other remaining configurations items related to Half Duplex Mode
<>	128:9bcdf88f62b0	1600	* (as Baud Rate, Word length, Parity, ...) should be set using
<>	128:9bcdf88f62b0	1601	* dedicated functions
<>	128:9bcdf88f62b0	1602	* @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
<>	128:9bcdf88f62b0	1603	* CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
<>	128:9bcdf88f62b0	1604	* CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
<>	128:9bcdf88f62b0	1605	* CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
<>	128:9bcdf88f62b0	1606	* CR3 IREN LL_USART_ConfigHalfDuplexMode
<>	128:9bcdf88f62b0	1607	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1608	* @retval None
<>	128:9bcdf88f62b0	1609	*/
<>	128:9bcdf88f62b0	1610	__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1611	{
<>	128:9bcdf88f62b0	1612	/* In Half Duplex mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1613	- LINEN and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1614	- SCEN and IREN bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1615	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	128:9bcdf88f62b0	1616	CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN \| USART_CR3_IREN));
<>	128:9bcdf88f62b0	1617	/* set the UART/USART in Half Duplex mode */
<>	128:9bcdf88f62b0	1618	SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
<>	128:9bcdf88f62b0	1619	}
<>	128:9bcdf88f62b0	1620
<>	128:9bcdf88f62b0	1621	/**
<>	128:9bcdf88f62b0	1622	* @brief Perform basic configuration of USART for enabling use in Smartcard Mode
<>	128:9bcdf88f62b0	1623	* @note In Smartcard mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1624	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1625	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1626	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1627	* This function also configures Stop bits to 1.5 bits and
<>	128:9bcdf88f62b0	1628	* sets the USART in Smartcard mode (SCEN bit).
<>	128:9bcdf88f62b0	1629	* Clock Output is also enabled (CLKEN).
<>	128:9bcdf88f62b0	1630	* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1631	* Smartcard feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1632	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1633	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1634	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1635	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1636	* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
<>	128:9bcdf88f62b0	1637	* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
<>	128:9bcdf88f62b0	1638	* - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
<>	128:9bcdf88f62b0	1639	* @note Other remaining configurations items related to Smartcard Mode
<>	128:9bcdf88f62b0	1640	* (as Baud Rate, Word length, Parity, ...) should be set using
<>	128:9bcdf88f62b0	1641	* dedicated functions
<>	128:9bcdf88f62b0	1642	* @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
<>	128:9bcdf88f62b0	1643	* CR2 STOP LL_USART_ConfigSmartcardMode\n
<>	128:9bcdf88f62b0	1644	* CR2 CLKEN LL_USART_ConfigSmartcardMode\n
<>	128:9bcdf88f62b0	1645	* CR3 HDSEL LL_USART_ConfigSmartcardMode\n
<>	128:9bcdf88f62b0	1646	* CR3 SCEN LL_USART_ConfigSmartcardMode
<>	128:9bcdf88f62b0	1647	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1648	* @retval None
<>	128:9bcdf88f62b0	1649	*/
<>	128:9bcdf88f62b0	1650	__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1651	{
<>	128:9bcdf88f62b0	1652	/* In Smartcard mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1653	- LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1654	- IREN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1655	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
<>	128:9bcdf88f62b0	1656	CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN \| USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1657	/* Configure Stop bits to 1.5 bits */
<>	128:9bcdf88f62b0	1658	/* Synchronous mode is activated by default */
<>	128:9bcdf88f62b0	1659	SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 \| USART_CR2_STOP_1 \| USART_CR2_CLKEN));
<>	128:9bcdf88f62b0	1660	/* set the UART/USART in Smartcard mode */
<>	128:9bcdf88f62b0	1661	SET_BIT(USARTx->CR3, USART_CR3_SCEN);
<>	128:9bcdf88f62b0	1662	}
<>	128:9bcdf88f62b0	1663
<>	128:9bcdf88f62b0	1664	/**
<>	128:9bcdf88f62b0	1665	* @brief Perform basic configuration of USART for enabling use in Irda Mode
<>	128:9bcdf88f62b0	1666	* @note In IRDA mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1667	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1668	* - STOP and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1669	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1670	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1671	* This function also sets the UART/USART in IRDA mode (IREN bit).
<>	128:9bcdf88f62b0	1672	* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1673	* IrDA feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1674	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1675	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1676	* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
<>	128:9bcdf88f62b0	1677	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1678	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1679	* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
<>	128:9bcdf88f62b0	1680	* - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
<>	128:9bcdf88f62b0	1681	* @note Other remaining configurations items related to Irda Mode
<>	128:9bcdf88f62b0	1682	* (as Baud Rate, Word length, Power mode, ...) should be set using
<>	128:9bcdf88f62b0	1683	* dedicated functions
<>	128:9bcdf88f62b0	1684	* @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
<>	128:9bcdf88f62b0	1685	* CR2 CLKEN LL_USART_ConfigIrdaMode\n
<>	128:9bcdf88f62b0	1686	* CR2 STOP LL_USART_ConfigIrdaMode\n
<>	128:9bcdf88f62b0	1687	* CR3 SCEN LL_USART_ConfigIrdaMode\n
<>	128:9bcdf88f62b0	1688	* CR3 HDSEL LL_USART_ConfigIrdaMode\n
<>	128:9bcdf88f62b0	1689	* CR3 IREN LL_USART_ConfigIrdaMode
<>	128:9bcdf88f62b0	1690	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1691	* @retval None
<>	128:9bcdf88f62b0	1692	*/
<>	128:9bcdf88f62b0	1693	__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1694	{
<>	128:9bcdf88f62b0	1695	/* In IRDA mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1696	- LINEN, STOP and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1697	- SCEN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1698	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN \| USART_CR2_STOP));
<>	128:9bcdf88f62b0	1699	CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL));
<>	128:9bcdf88f62b0	1700	/* set the UART/USART in IRDA mode */
<>	128:9bcdf88f62b0	1701	SET_BIT(USARTx->CR3, USART_CR3_IREN);
<>	128:9bcdf88f62b0	1702	}
<>	128:9bcdf88f62b0	1703
<>	128:9bcdf88f62b0	1704	/**
<>	128:9bcdf88f62b0	1705	* @brief Perform basic configuration of USART for enabling use in Multi processor Mode
<>	128:9bcdf88f62b0	1706	* (several USARTs connected in a network, one of the USARTs can be the master,
<>	128:9bcdf88f62b0	1707	* its TX output connected to the RX inputs of the other slaves USARTs).
<>	128:9bcdf88f62b0	1708	* @note In MultiProcessor mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1709	* - LINEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1710	* - CLKEN bit in the USART_CR2 register,
<>	128:9bcdf88f62b0	1711	* - SCEN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1712	* - IREN bit in the USART_CR3 register,
<>	128:9bcdf88f62b0	1713	* - HDSEL bit in the USART_CR3 register.
<>	128:9bcdf88f62b0	1714	* @note Call of this function is equivalent to following function call sequence :
<>	128:9bcdf88f62b0	1715	* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
<>	128:9bcdf88f62b0	1716	* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
<>	128:9bcdf88f62b0	1717	* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
<>	128:9bcdf88f62b0	1718	* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
<>	128:9bcdf88f62b0	1719	* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
<>	128:9bcdf88f62b0	1720	* @note Other remaining configurations items related to Multi processor Mode
<>	128:9bcdf88f62b0	1721	* (as Baud Rate, Wake Up Method, Node address, ...) should be set using
<>	128:9bcdf88f62b0	1722	* dedicated functions
<>	128:9bcdf88f62b0	1723	* @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
<>	128:9bcdf88f62b0	1724	* CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
<>	128:9bcdf88f62b0	1725	* CR3 SCEN LL_USART_ConfigMultiProcessMode\n
<>	128:9bcdf88f62b0	1726	* CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
<>	128:9bcdf88f62b0	1727	* CR3 IREN LL_USART_ConfigMultiProcessMode
<>	128:9bcdf88f62b0	1728	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1729	* @retval None
<>	128:9bcdf88f62b0	1730	*/
<>	128:9bcdf88f62b0	1731	__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1732	{
<>	128:9bcdf88f62b0	1733	/* In Multi Processor mode, the following bits must be kept cleared:
<>	128:9bcdf88f62b0	1734	- LINEN and CLKEN bits in the USART_CR2 register,
<>	128:9bcdf88f62b0	1735	- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
<>	128:9bcdf88f62b0	1736	CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	128:9bcdf88f62b0	1737	CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	128:9bcdf88f62b0	1738	}
<>	128:9bcdf88f62b0	1739
<>	128:9bcdf88f62b0	1740	/**
<>	128:9bcdf88f62b0	1741	* @}
<>	128:9bcdf88f62b0	1742	*/
<>	128:9bcdf88f62b0	1743
<>	128:9bcdf88f62b0	1744	/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
<>	128:9bcdf88f62b0	1745	* @{
<>	128:9bcdf88f62b0	1746	*/
<>	128:9bcdf88f62b0	1747
<>	128:9bcdf88f62b0	1748	/**
<>	128:9bcdf88f62b0	1749	* @brief Check if the USART Parity Error Flag is set or not
<>	128:9bcdf88f62b0	1750	* @rmtoll SR PE LL_USART_IsActiveFlag_PE
<>	128:9bcdf88f62b0	1751	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1752	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1753	*/
<>	128:9bcdf88f62b0	1754	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1755	{
<>	128:9bcdf88f62b0	1756	return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
<>	128:9bcdf88f62b0	1757	}
<>	128:9bcdf88f62b0	1758
<>	128:9bcdf88f62b0	1759	/**
<>	128:9bcdf88f62b0	1760	* @brief Check if the USART Framing Error Flag is set or not
<>	128:9bcdf88f62b0	1761	* @rmtoll SR FE LL_USART_IsActiveFlag_FE
<>	128:9bcdf88f62b0	1762	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1763	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1764	*/
<>	128:9bcdf88f62b0	1765	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1766	{
<>	128:9bcdf88f62b0	1767	return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
<>	128:9bcdf88f62b0	1768	}
<>	128:9bcdf88f62b0	1769
<>	128:9bcdf88f62b0	1770	/**
<>	128:9bcdf88f62b0	1771	* @brief Check if the USART Noise error detected Flag is set or not
<>	128:9bcdf88f62b0	1772	* @rmtoll SR NF LL_USART_IsActiveFlag_NE
<>	128:9bcdf88f62b0	1773	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1774	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1775	*/
<>	128:9bcdf88f62b0	1776	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1777	{
<>	128:9bcdf88f62b0	1778	return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
<>	128:9bcdf88f62b0	1779	}
<>	128:9bcdf88f62b0	1780
<>	128:9bcdf88f62b0	1781	/**
<>	128:9bcdf88f62b0	1782	* @brief Check if the USART OverRun Error Flag is set or not
<>	128:9bcdf88f62b0	1783	* @rmtoll SR ORE LL_USART_IsActiveFlag_ORE
<>	128:9bcdf88f62b0	1784	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1785	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1786	*/
<>	128:9bcdf88f62b0	1787	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1788	{
<>	128:9bcdf88f62b0	1789	return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
<>	128:9bcdf88f62b0	1790	}
<>	128:9bcdf88f62b0	1791
<>	128:9bcdf88f62b0	1792	/**
<>	128:9bcdf88f62b0	1793	* @brief Check if the USART IDLE line detected Flag is set or not
<>	128:9bcdf88f62b0	1794	* @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE
<>	128:9bcdf88f62b0	1795	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1796	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1797	*/
<>	128:9bcdf88f62b0	1798	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1799	{
<>	128:9bcdf88f62b0	1800	return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
<>	128:9bcdf88f62b0	1801	}
<>	128:9bcdf88f62b0	1802
<>	128:9bcdf88f62b0	1803	/**
<>	128:9bcdf88f62b0	1804	* @brief Check if the USART Read Data Register Not Empty Flag is set or not
<>	128:9bcdf88f62b0	1805	* @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE
<>	128:9bcdf88f62b0	1806	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1807	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1808	*/
<>	128:9bcdf88f62b0	1809	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1810	{
<>	128:9bcdf88f62b0	1811	return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
<>	128:9bcdf88f62b0	1812	}
<>	128:9bcdf88f62b0	1813
<>	128:9bcdf88f62b0	1814	/**
<>	128:9bcdf88f62b0	1815	* @brief Check if the USART Transmission Complete Flag is set or not
<>	128:9bcdf88f62b0	1816	* @rmtoll SR TC LL_USART_IsActiveFlag_TC
<>	128:9bcdf88f62b0	1817	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1818	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1819	*/
<>	128:9bcdf88f62b0	1820	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1821	{
<>	128:9bcdf88f62b0	1822	return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
<>	128:9bcdf88f62b0	1823	}
<>	128:9bcdf88f62b0	1824
<>	128:9bcdf88f62b0	1825	/**
<>	128:9bcdf88f62b0	1826	* @brief Check if the USART Transmit Data Register Empty Flag is set or not
<>	128:9bcdf88f62b0	1827	* @rmtoll SR TXE LL_USART_IsActiveFlag_TXE
<>	128:9bcdf88f62b0	1828	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1829	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1830	*/
<>	128:9bcdf88f62b0	1831	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1832	{
<>	128:9bcdf88f62b0	1833	return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
<>	128:9bcdf88f62b0	1834	}
<>	128:9bcdf88f62b0	1835
<>	128:9bcdf88f62b0	1836	/**
<>	128:9bcdf88f62b0	1837	* @brief Check if the USART LIN Break Detection Flag is set or not
<>	128:9bcdf88f62b0	1838	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1839	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1840	* @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
<>	128:9bcdf88f62b0	1841	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1842	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1843	*/
<>	128:9bcdf88f62b0	1844	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1845	{
<>	128:9bcdf88f62b0	1846	return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
<>	128:9bcdf88f62b0	1847	}
<>	128:9bcdf88f62b0	1848
<>	128:9bcdf88f62b0	1849	/**
<>	128:9bcdf88f62b0	1850	* @brief Check if the USART CTS Flag is set or not
<>	128:9bcdf88f62b0	1851	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	1852	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	1853	* @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
<>	128:9bcdf88f62b0	1854	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1855	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1856	*/
<>	128:9bcdf88f62b0	1857	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1858	{
<>	128:9bcdf88f62b0	1859	return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
<>	128:9bcdf88f62b0	1860	}
<>	128:9bcdf88f62b0	1861
<>	128:9bcdf88f62b0	1862	/**
<>	128:9bcdf88f62b0	1863	* @brief Check if the USART Send Break Flag is set or not
<>	128:9bcdf88f62b0	1864	* @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK
<>	128:9bcdf88f62b0	1865	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1866	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1867	*/
<>	128:9bcdf88f62b0	1868	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1869	{
<>	128:9bcdf88f62b0	1870	return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
<>	128:9bcdf88f62b0	1871	}
<>	128:9bcdf88f62b0	1872
<>	128:9bcdf88f62b0	1873	/**
<>	128:9bcdf88f62b0	1874	* @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
<>	128:9bcdf88f62b0	1875	* @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU
<>	128:9bcdf88f62b0	1876	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1877	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1878	*/
<>	128:9bcdf88f62b0	1879	__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1880	{
<>	128:9bcdf88f62b0	1881	return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
<>	128:9bcdf88f62b0	1882	}
<>	128:9bcdf88f62b0	1883
<>	128:9bcdf88f62b0	1884	/**
<>	128:9bcdf88f62b0	1885	* @brief Clear Parity Error Flag
<>	128:9bcdf88f62b0	1886	* @note Clearing this flag is done by a read access to the USARTx_SR
<>	128:9bcdf88f62b0	1887	* register followed by a read access to the USARTx_DR register.
<>	128:9bcdf88f62b0	1888	* @note Please also consider that when clearing this flag, other flags as
<>	128:9bcdf88f62b0	1889	* NE, FE, ORE, IDLE would also be cleared.
<>	128:9bcdf88f62b0	1890	* @rmtoll SR PE LL_USART_ClearFlag_PE
<>	128:9bcdf88f62b0	1891	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1892	* @retval None
<>	128:9bcdf88f62b0	1893	*/
<>	128:9bcdf88f62b0	1894	__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1895	{
<>	128:9bcdf88f62b0	1896	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1897	tmpreg = USARTx->SR;
<>	128:9bcdf88f62b0	1898	(void) tmpreg;
<>	128:9bcdf88f62b0	1899	tmpreg = USARTx->DR;
<>	128:9bcdf88f62b0	1900	(void) tmpreg;
<>	128:9bcdf88f62b0	1901	}
<>	128:9bcdf88f62b0	1902
<>	128:9bcdf88f62b0	1903	/**
<>	128:9bcdf88f62b0	1904	* @brief Clear Framing Error Flag
<>	128:9bcdf88f62b0	1905	* @note Clearing this flag is done by a read access to the USARTx_SR
<>	128:9bcdf88f62b0	1906	* register followed by a read access to the USARTx_DR register.
<>	128:9bcdf88f62b0	1907	* @note Please also consider that when clearing this flag, other flags as
<>	128:9bcdf88f62b0	1908	* PE, NE, ORE, IDLE would also be cleared.
<>	128:9bcdf88f62b0	1909	* @rmtoll SR FE LL_USART_ClearFlag_FE
<>	128:9bcdf88f62b0	1910	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1911	* @retval None
<>	128:9bcdf88f62b0	1912	*/
<>	128:9bcdf88f62b0	1913	__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1914	{
<>	128:9bcdf88f62b0	1915	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1916	tmpreg = USARTx->SR;
<>	128:9bcdf88f62b0	1917	(void) tmpreg;
<>	128:9bcdf88f62b0	1918	tmpreg = USARTx->DR;
<>	128:9bcdf88f62b0	1919	(void) tmpreg;
<>	128:9bcdf88f62b0	1920	}
<>	128:9bcdf88f62b0	1921
<>	128:9bcdf88f62b0	1922	/**
<>	128:9bcdf88f62b0	1923	* @brief Clear Noise detected Flag
<>	128:9bcdf88f62b0	1924	* @note Clearing this flag is done by a read access to the USARTx_SR
<>	128:9bcdf88f62b0	1925	* register followed by a read access to the USARTx_DR register.
<>	128:9bcdf88f62b0	1926	* @note Please also consider that when clearing this flag, other flags as
<>	128:9bcdf88f62b0	1927	* PE, FE, ORE, IDLE would also be cleared.
<>	128:9bcdf88f62b0	1928	* @rmtoll SR NF LL_USART_ClearFlag_NE
<>	128:9bcdf88f62b0	1929	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1930	* @retval None
<>	128:9bcdf88f62b0	1931	*/
<>	128:9bcdf88f62b0	1932	__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1933	{
<>	128:9bcdf88f62b0	1934	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1935	tmpreg = USARTx->SR;
<>	128:9bcdf88f62b0	1936	(void) tmpreg;
<>	128:9bcdf88f62b0	1937	tmpreg = USARTx->DR;
<>	128:9bcdf88f62b0	1938	(void) tmpreg;
<>	128:9bcdf88f62b0	1939	}
<>	128:9bcdf88f62b0	1940
<>	128:9bcdf88f62b0	1941	/**
<>	128:9bcdf88f62b0	1942	* @brief Clear OverRun Error Flag
<>	128:9bcdf88f62b0	1943	* @note Clearing this flag is done by a read access to the USARTx_SR
<>	128:9bcdf88f62b0	1944	* register followed by a read access to the USARTx_DR register.
<>	128:9bcdf88f62b0	1945	* @note Please also consider that when clearing this flag, other flags as
<>	128:9bcdf88f62b0	1946	* PE, NE, FE, IDLE would also be cleared.
<>	128:9bcdf88f62b0	1947	* @rmtoll SR ORE LL_USART_ClearFlag_ORE
<>	128:9bcdf88f62b0	1948	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1949	* @retval None
<>	128:9bcdf88f62b0	1950	*/
<>	128:9bcdf88f62b0	1951	__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1952	{
<>	128:9bcdf88f62b0	1953	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1954	tmpreg = USARTx->SR;
<>	128:9bcdf88f62b0	1955	(void) tmpreg;
<>	128:9bcdf88f62b0	1956	tmpreg = USARTx->DR;
<>	128:9bcdf88f62b0	1957	(void) tmpreg;
<>	128:9bcdf88f62b0	1958	}
<>	128:9bcdf88f62b0	1959
<>	128:9bcdf88f62b0	1960	/**
<>	128:9bcdf88f62b0	1961	* @brief Clear IDLE line detected Flag
<>	128:9bcdf88f62b0	1962	* @note Clearing this flag is done by a read access to the USARTx_SR
<>	128:9bcdf88f62b0	1963	* register followed by a read access to the USARTx_DR register.
<>	128:9bcdf88f62b0	1964	* @note Please also consider that when clearing this flag, other flags as
<>	128:9bcdf88f62b0	1965	* PE, NE, FE, ORE would also be cleared.
<>	128:9bcdf88f62b0	1966	* @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
<>	128:9bcdf88f62b0	1967	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1968	* @retval None
<>	128:9bcdf88f62b0	1969	*/
<>	128:9bcdf88f62b0	1970	__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1971	{
<>	128:9bcdf88f62b0	1972	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1973	tmpreg = USARTx->SR;
<>	128:9bcdf88f62b0	1974	(void) tmpreg;
<>	128:9bcdf88f62b0	1975	tmpreg = USARTx->DR;
<>	128:9bcdf88f62b0	1976	(void) tmpreg;
<>	128:9bcdf88f62b0	1977	}
<>	128:9bcdf88f62b0	1978
<>	128:9bcdf88f62b0	1979	/**
<>	128:9bcdf88f62b0	1980	* @brief Clear Transmission Complete Flag
<>	128:9bcdf88f62b0	1981	* @rmtoll SR TC LL_USART_ClearFlag_TC
<>	128:9bcdf88f62b0	1982	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1983	* @retval None
<>	128:9bcdf88f62b0	1984	*/
<>	128:9bcdf88f62b0	1985	__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1986	{
<>	128:9bcdf88f62b0	1987	WRITE_REG(USARTx->SR , ~(USART_SR_TC));
<>	128:9bcdf88f62b0	1988	}
<>	128:9bcdf88f62b0	1989
<>	128:9bcdf88f62b0	1990	/**
<>	128:9bcdf88f62b0	1991	* @brief Clear RX Not Empty Flag
<>	128:9bcdf88f62b0	1992	* @rmtoll SR RXNE LL_USART_ClearFlag_RXNE
<>	128:9bcdf88f62b0	1993	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	1994	* @retval None
<>	128:9bcdf88f62b0	1995	*/
<>	128:9bcdf88f62b0	1996	__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	1997	{
<>	128:9bcdf88f62b0	1998	WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
<>	128:9bcdf88f62b0	1999	}
<>	128:9bcdf88f62b0	2000
<>	128:9bcdf88f62b0	2001	/**
<>	128:9bcdf88f62b0	2002	* @brief Clear LIN Break Detection Flag
<>	128:9bcdf88f62b0	2003	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2004	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2005	* @rmtoll SR LBD LL_USART_ClearFlag_LBD
<>	128:9bcdf88f62b0	2006	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2007	* @retval None
<>	128:9bcdf88f62b0	2008	*/
<>	128:9bcdf88f62b0	2009	__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2010	{
<>	128:9bcdf88f62b0	2011	WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
<>	128:9bcdf88f62b0	2012	}
<>	128:9bcdf88f62b0	2013
<>	128:9bcdf88f62b0	2014	/**
<>	128:9bcdf88f62b0	2015	* @brief Clear CTS Interrupt Flag
<>	128:9bcdf88f62b0	2016	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2017	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2018	* @rmtoll SR CTS LL_USART_ClearFlag_nCTS
<>	128:9bcdf88f62b0	2019	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2020	* @retval None
<>	128:9bcdf88f62b0	2021	*/
<>	128:9bcdf88f62b0	2022	__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2023	{
<>	128:9bcdf88f62b0	2024	WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
<>	128:9bcdf88f62b0	2025	}
<>	128:9bcdf88f62b0	2026
<>	128:9bcdf88f62b0	2027	/**
<>	128:9bcdf88f62b0	2028	* @}
<>	128:9bcdf88f62b0	2029	*/
<>	128:9bcdf88f62b0	2030
<>	128:9bcdf88f62b0	2031	/** @defgroup USART_LL_EF_IT_Management IT_Management
<>	128:9bcdf88f62b0	2032	* @{
<>	128:9bcdf88f62b0	2033	*/
<>	128:9bcdf88f62b0	2034
<>	128:9bcdf88f62b0	2035	/**
<>	128:9bcdf88f62b0	2036	* @brief Enable IDLE Interrupt
<>	128:9bcdf88f62b0	2037	* @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
<>	128:9bcdf88f62b0	2038	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2039	* @retval None
<>	128:9bcdf88f62b0	2040	*/
<>	128:9bcdf88f62b0	2041	__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2042	{
<>	128:9bcdf88f62b0	2043	SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
<>	128:9bcdf88f62b0	2044	}
<>	128:9bcdf88f62b0	2045
<>	128:9bcdf88f62b0	2046	/**
<>	128:9bcdf88f62b0	2047	* @brief Enable RX Not Empty Interrupt
<>	128:9bcdf88f62b0	2048	* @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
<>	128:9bcdf88f62b0	2049	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2050	* @retval None
<>	128:9bcdf88f62b0	2051	*/
<>	128:9bcdf88f62b0	2052	__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2053	{
<>	128:9bcdf88f62b0	2054	SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
<>	128:9bcdf88f62b0	2055	}
<>	128:9bcdf88f62b0	2056
<>	128:9bcdf88f62b0	2057	/**
<>	128:9bcdf88f62b0	2058	* @brief Enable Transmission Complete Interrupt
<>	128:9bcdf88f62b0	2059	* @rmtoll CR1 TCIE LL_USART_EnableIT_TC
<>	128:9bcdf88f62b0	2060	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2061	* @retval None
<>	128:9bcdf88f62b0	2062	*/
<>	128:9bcdf88f62b0	2063	__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2064	{
<>	128:9bcdf88f62b0	2065	SET_BIT(USARTx->CR1, USART_CR1_TCIE);
<>	128:9bcdf88f62b0	2066	}
<>	128:9bcdf88f62b0	2067
<>	128:9bcdf88f62b0	2068	/**
<>	128:9bcdf88f62b0	2069	* @brief Enable TX Empty Interrupt
<>	128:9bcdf88f62b0	2070	* @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
<>	128:9bcdf88f62b0	2071	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2072	* @retval None
<>	128:9bcdf88f62b0	2073	*/
<>	128:9bcdf88f62b0	2074	__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2075	{
<>	128:9bcdf88f62b0	2076	SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
<>	128:9bcdf88f62b0	2077	}
<>	128:9bcdf88f62b0	2078
<>	128:9bcdf88f62b0	2079	/**
<>	128:9bcdf88f62b0	2080	* @brief Enable Parity Error Interrupt
<>	128:9bcdf88f62b0	2081	* @rmtoll CR1 PEIE LL_USART_EnableIT_PE
<>	128:9bcdf88f62b0	2082	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2083	* @retval None
<>	128:9bcdf88f62b0	2084	*/
<>	128:9bcdf88f62b0	2085	__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2086	{
<>	128:9bcdf88f62b0	2087	SET_BIT(USARTx->CR1, USART_CR1_PEIE);
<>	128:9bcdf88f62b0	2088	}
<>	128:9bcdf88f62b0	2089
<>	128:9bcdf88f62b0	2090	/**
<>	128:9bcdf88f62b0	2091	* @brief Enable LIN Break Detection Interrupt
<>	128:9bcdf88f62b0	2092	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2093	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2094	* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
<>	128:9bcdf88f62b0	2095	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2096	* @retval None
<>	128:9bcdf88f62b0	2097	*/
<>	128:9bcdf88f62b0	2098	__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2099	{
<>	128:9bcdf88f62b0	2100	SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
<>	128:9bcdf88f62b0	2101	}
<>	128:9bcdf88f62b0	2102
<>	128:9bcdf88f62b0	2103	/**
<>	128:9bcdf88f62b0	2104	* @brief Enable Error Interrupt
<>	128:9bcdf88f62b0	2105	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
<>	128:9bcdf88f62b0	2106	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
<>	128:9bcdf88f62b0	2107	* 0: Interrupt is inhibited
<>	128:9bcdf88f62b0	2108	* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
<>	128:9bcdf88f62b0	2109	* @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
<>	128:9bcdf88f62b0	2110	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2111	* @retval None
<>	128:9bcdf88f62b0	2112	*/
<>	128:9bcdf88f62b0	2113	__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2114	{
<>	128:9bcdf88f62b0	2115	SET_BIT(USARTx->CR3, USART_CR3_EIE);
<>	128:9bcdf88f62b0	2116	}
<>	128:9bcdf88f62b0	2117
<>	128:9bcdf88f62b0	2118	/**
<>	128:9bcdf88f62b0	2119	* @brief Enable CTS Interrupt
<>	128:9bcdf88f62b0	2120	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2121	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2122	* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
<>	128:9bcdf88f62b0	2123	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2124	* @retval None
<>	128:9bcdf88f62b0	2125	*/
<>	128:9bcdf88f62b0	2126	__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2127	{
<>	128:9bcdf88f62b0	2128	SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
<>	128:9bcdf88f62b0	2129	}
<>	128:9bcdf88f62b0	2130
<>	128:9bcdf88f62b0	2131	/**
<>	128:9bcdf88f62b0	2132	* @brief Disable IDLE Interrupt
<>	128:9bcdf88f62b0	2133	* @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
<>	128:9bcdf88f62b0	2134	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2135	* @retval None
<>	128:9bcdf88f62b0	2136	*/
<>	128:9bcdf88f62b0	2137	__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2138	{
<>	128:9bcdf88f62b0	2139	CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
<>	128:9bcdf88f62b0	2140	}
<>	128:9bcdf88f62b0	2141
<>	128:9bcdf88f62b0	2142	/**
<>	128:9bcdf88f62b0	2143	* @brief Disable RX Not Empty Interrupt
<>	128:9bcdf88f62b0	2144	* @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
<>	128:9bcdf88f62b0	2145	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2146	* @retval None
<>	128:9bcdf88f62b0	2147	*/
<>	128:9bcdf88f62b0	2148	__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2149	{
<>	128:9bcdf88f62b0	2150	CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
<>	128:9bcdf88f62b0	2151	}
<>	128:9bcdf88f62b0	2152
<>	128:9bcdf88f62b0	2153	/**
<>	128:9bcdf88f62b0	2154	* @brief Disable Transmission Complete Interrupt
<>	128:9bcdf88f62b0	2155	* @rmtoll CR1 TCIE LL_USART_DisableIT_TC
<>	128:9bcdf88f62b0	2156	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2157	* @retval None
<>	128:9bcdf88f62b0	2158	*/
<>	128:9bcdf88f62b0	2159	__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2160	{
<>	128:9bcdf88f62b0	2161	CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
<>	128:9bcdf88f62b0	2162	}
<>	128:9bcdf88f62b0	2163
<>	128:9bcdf88f62b0	2164	/**
<>	128:9bcdf88f62b0	2165	* @brief Disable TX Empty Interrupt
<>	128:9bcdf88f62b0	2166	* @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
<>	128:9bcdf88f62b0	2167	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2168	* @retval None
<>	128:9bcdf88f62b0	2169	*/
<>	128:9bcdf88f62b0	2170	__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2171	{
<>	128:9bcdf88f62b0	2172	CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
<>	128:9bcdf88f62b0	2173	}
<>	128:9bcdf88f62b0	2174
<>	128:9bcdf88f62b0	2175	/**
<>	128:9bcdf88f62b0	2176	* @brief Disable Parity Error Interrupt
<>	128:9bcdf88f62b0	2177	* @rmtoll CR1 PEIE LL_USART_DisableIT_PE
<>	128:9bcdf88f62b0	2178	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2179	* @retval None
<>	128:9bcdf88f62b0	2180	*/
<>	128:9bcdf88f62b0	2181	__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2182	{
<>	128:9bcdf88f62b0	2183	CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
<>	128:9bcdf88f62b0	2184	}
<>	128:9bcdf88f62b0	2185
<>	128:9bcdf88f62b0	2186	/**
<>	128:9bcdf88f62b0	2187	* @brief Disable LIN Break Detection Interrupt
<>	128:9bcdf88f62b0	2188	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2189	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2190	* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
<>	128:9bcdf88f62b0	2191	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2192	* @retval None
<>	128:9bcdf88f62b0	2193	*/
<>	128:9bcdf88f62b0	2194	__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2195	{
<>	128:9bcdf88f62b0	2196	CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
<>	128:9bcdf88f62b0	2197	}
<>	128:9bcdf88f62b0	2198
<>	128:9bcdf88f62b0	2199	/**
<>	128:9bcdf88f62b0	2200	* @brief Disable Error Interrupt
<>	128:9bcdf88f62b0	2201	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
<>	128:9bcdf88f62b0	2202	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
<>	128:9bcdf88f62b0	2203	* 0: Interrupt is inhibited
<>	128:9bcdf88f62b0	2204	* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
<>	128:9bcdf88f62b0	2205	* @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
<>	128:9bcdf88f62b0	2206	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2207	* @retval None
<>	128:9bcdf88f62b0	2208	*/
<>	128:9bcdf88f62b0	2209	__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2210	{
<>	128:9bcdf88f62b0	2211	CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
<>	128:9bcdf88f62b0	2212	}
<>	128:9bcdf88f62b0	2213
<>	128:9bcdf88f62b0	2214	/**
<>	128:9bcdf88f62b0	2215	* @brief Disable CTS Interrupt
<>	128:9bcdf88f62b0	2216	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2217	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2218	* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
<>	128:9bcdf88f62b0	2219	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2220	* @retval None
<>	128:9bcdf88f62b0	2221	*/
<>	128:9bcdf88f62b0	2222	__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2223	{
<>	128:9bcdf88f62b0	2224	CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
<>	128:9bcdf88f62b0	2225	}
<>	128:9bcdf88f62b0	2226
<>	128:9bcdf88f62b0	2227	/**
<>	128:9bcdf88f62b0	2228	* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	2229	* @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
<>	128:9bcdf88f62b0	2230	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2231	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2232	*/
<>	128:9bcdf88f62b0	2233	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2234	{
<>	128:9bcdf88f62b0	2235	return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
<>	128:9bcdf88f62b0	2236	}
<>	128:9bcdf88f62b0	2237
<>	128:9bcdf88f62b0	2238	/**
<>	128:9bcdf88f62b0	2239	* @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2240	* @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
<>	128:9bcdf88f62b0	2241	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2242	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2243	*/
<>	128:9bcdf88f62b0	2244	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2245	{
<>	128:9bcdf88f62b0	2246	return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
<>	128:9bcdf88f62b0	2247	}
<>	128:9bcdf88f62b0	2248
<>	128:9bcdf88f62b0	2249	/**
<>	128:9bcdf88f62b0	2250	* @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2251	* @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
<>	128:9bcdf88f62b0	2252	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2253	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2254	*/
<>	128:9bcdf88f62b0	2255	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2256	{
<>	128:9bcdf88f62b0	2257	return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
<>	128:9bcdf88f62b0	2258	}
<>	128:9bcdf88f62b0	2259
<>	128:9bcdf88f62b0	2260	/**
<>	128:9bcdf88f62b0	2261	* @brief Check if the USART TX Empty Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2262	* @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
<>	128:9bcdf88f62b0	2263	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2264	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2265	*/
<>	128:9bcdf88f62b0	2266	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2267	{
<>	128:9bcdf88f62b0	2268	return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
<>	128:9bcdf88f62b0	2269	}
<>	128:9bcdf88f62b0	2270
<>	128:9bcdf88f62b0	2271	/**
<>	128:9bcdf88f62b0	2272	* @brief Check if the USART Parity Error Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2273	* @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
<>	128:9bcdf88f62b0	2274	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2275	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2276	*/
<>	128:9bcdf88f62b0	2277	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2278	{
<>	128:9bcdf88f62b0	2279	return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
<>	128:9bcdf88f62b0	2280	}
<>	128:9bcdf88f62b0	2281
<>	128:9bcdf88f62b0	2282	/**
<>	128:9bcdf88f62b0	2283	* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2284	* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2285	* LIN feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2286	* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
<>	128:9bcdf88f62b0	2287	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2288	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2289	*/
<>	128:9bcdf88f62b0	2290	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2291	{
<>	128:9bcdf88f62b0	2292	return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
<>	128:9bcdf88f62b0	2293	}
<>	128:9bcdf88f62b0	2294
<>	128:9bcdf88f62b0	2295	/**
<>	128:9bcdf88f62b0	2296	* @brief Check if the USART Error Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2297	* @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
<>	128:9bcdf88f62b0	2298	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2299	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2300	*/
<>	128:9bcdf88f62b0	2301	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2302	{
<>	128:9bcdf88f62b0	2303	return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
<>	128:9bcdf88f62b0	2304	}
<>	128:9bcdf88f62b0	2305
<>	128:9bcdf88f62b0	2306	/**
<>	128:9bcdf88f62b0	2307	* @brief Check if the USART CTS Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	2308	* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
<>	128:9bcdf88f62b0	2309	* Hardware Flow control feature is supported by the USARTx instance.
<>	128:9bcdf88f62b0	2310	* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
<>	128:9bcdf88f62b0	2311	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2312	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2313	*/
<>	128:9bcdf88f62b0	2314	__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2315	{
<>	128:9bcdf88f62b0	2316	return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
<>	128:9bcdf88f62b0	2317	}
<>	128:9bcdf88f62b0	2318
<>	128:9bcdf88f62b0	2319	/**
<>	128:9bcdf88f62b0	2320	* @}
<>	128:9bcdf88f62b0	2321	*/
<>	128:9bcdf88f62b0	2322
<>	128:9bcdf88f62b0	2323	/** @defgroup USART_LL_EF_DMA_Management DMA_Management
<>	128:9bcdf88f62b0	2324	* @{
<>	128:9bcdf88f62b0	2325	*/
<>	128:9bcdf88f62b0	2326
<>	128:9bcdf88f62b0	2327	/**
<>	128:9bcdf88f62b0	2328	* @brief Enable DMA Mode for reception
<>	128:9bcdf88f62b0	2329	* @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
<>	128:9bcdf88f62b0	2330	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2331	* @retval None
<>	128:9bcdf88f62b0	2332	*/
<>	128:9bcdf88f62b0	2333	__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2334	{
<>	128:9bcdf88f62b0	2335	SET_BIT(USARTx->CR3, USART_CR3_DMAR);
<>	128:9bcdf88f62b0	2336	}
<>	128:9bcdf88f62b0	2337
<>	128:9bcdf88f62b0	2338	/**
<>	128:9bcdf88f62b0	2339	* @brief Disable DMA Mode for reception
<>	128:9bcdf88f62b0	2340	* @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
<>	128:9bcdf88f62b0	2341	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2342	* @retval None
<>	128:9bcdf88f62b0	2343	*/
<>	128:9bcdf88f62b0	2344	__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2345	{
<>	128:9bcdf88f62b0	2346	CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
<>	128:9bcdf88f62b0	2347	}
<>	128:9bcdf88f62b0	2348
<>	128:9bcdf88f62b0	2349	/**
<>	128:9bcdf88f62b0	2350	* @brief Check if DMA Mode is enabled for reception
<>	128:9bcdf88f62b0	2351	* @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
<>	128:9bcdf88f62b0	2352	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2353	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2354	*/
<>	128:9bcdf88f62b0	2355	__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2356	{
<>	128:9bcdf88f62b0	2357	return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
<>	128:9bcdf88f62b0	2358	}
<>	128:9bcdf88f62b0	2359
<>	128:9bcdf88f62b0	2360	/**
<>	128:9bcdf88f62b0	2361	* @brief Enable DMA Mode for transmission
<>	128:9bcdf88f62b0	2362	* @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
<>	128:9bcdf88f62b0	2363	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2364	* @retval None
<>	128:9bcdf88f62b0	2365	*/
<>	128:9bcdf88f62b0	2366	__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2367	{
<>	128:9bcdf88f62b0	2368	SET_BIT(USARTx->CR3, USART_CR3_DMAT);
<>	128:9bcdf88f62b0	2369	}
<>	128:9bcdf88f62b0	2370
<>	128:9bcdf88f62b0	2371	/**
<>	128:9bcdf88f62b0	2372	* @brief Disable DMA Mode for transmission
<>	128:9bcdf88f62b0	2373	* @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
<>	128:9bcdf88f62b0	2374	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2375	* @retval None
<>	128:9bcdf88f62b0	2376	*/
<>	128:9bcdf88f62b0	2377	__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2378	{
<>	128:9bcdf88f62b0	2379	CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
<>	128:9bcdf88f62b0	2380	}
<>	128:9bcdf88f62b0	2381
<>	128:9bcdf88f62b0	2382	/**
<>	128:9bcdf88f62b0	2383	* @brief Check if DMA Mode is enabled for transmission
<>	128:9bcdf88f62b0	2384	* @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
<>	128:9bcdf88f62b0	2385	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2386	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	2387	*/
<>	128:9bcdf88f62b0	2388	__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2389	{
<>	128:9bcdf88f62b0	2390	return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
<>	128:9bcdf88f62b0	2391	}
<>	128:9bcdf88f62b0	2392
<>	128:9bcdf88f62b0	2393	/**
<>	128:9bcdf88f62b0	2394	* @brief Get the data register address used for DMA transfer
<>	128:9bcdf88f62b0	2395	* @rmtoll DR DR LL_USART_DMA_GetRegAddr
<>	128:9bcdf88f62b0	2396	* @note Address of Data Register is valid for both Transmit and Receive transfers.
<>	128:9bcdf88f62b0	2397	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2398	* @retval Address of data register
<>	128:9bcdf88f62b0	2399	*/
<>	128:9bcdf88f62b0	2400	__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2401	{
<>	128:9bcdf88f62b0	2402	/* return address of DR register */
<>	128:9bcdf88f62b0	2403	return ((uint32_t) &(USARTx->DR));
<>	128:9bcdf88f62b0	2404	}
<>	128:9bcdf88f62b0	2405
<>	128:9bcdf88f62b0	2406	/**
<>	128:9bcdf88f62b0	2407	* @}
<>	128:9bcdf88f62b0	2408	*/
<>	128:9bcdf88f62b0	2409
<>	128:9bcdf88f62b0	2410	/** @defgroup USART_LL_EF_Data_Management Data_Management
<>	128:9bcdf88f62b0	2411	* @{
<>	128:9bcdf88f62b0	2412	*/
<>	128:9bcdf88f62b0	2413
<>	128:9bcdf88f62b0	2414	/**
<>	128:9bcdf88f62b0	2415	* @brief Read Receiver Data register (Receive Data value, 8 bits)
<>	128:9bcdf88f62b0	2416	* @rmtoll DR DR LL_USART_ReceiveData8
<>	128:9bcdf88f62b0	2417	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2418	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	2419	*/
<>	128:9bcdf88f62b0	2420	__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2421	{
<>	128:9bcdf88f62b0	2422	return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
<>	128:9bcdf88f62b0	2423	}
<>	128:9bcdf88f62b0	2424
<>	128:9bcdf88f62b0	2425	/**
<>	128:9bcdf88f62b0	2426	* @brief Read Receiver Data register (Receive Data value, 9 bits)
<>	128:9bcdf88f62b0	2427	* @rmtoll DR DR LL_USART_ReceiveData9
<>	128:9bcdf88f62b0	2428	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2429	* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
<>	128:9bcdf88f62b0	2430	*/
<>	128:9bcdf88f62b0	2431	__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2432	{
<>	128:9bcdf88f62b0	2433	return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
<>	128:9bcdf88f62b0	2434	}
<>	128:9bcdf88f62b0	2435
<>	128:9bcdf88f62b0	2436	/**
<>	128:9bcdf88f62b0	2437	* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
<>	128:9bcdf88f62b0	2438	* @rmtoll DR DR LL_USART_TransmitData8
<>	128:9bcdf88f62b0	2439	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2440	* @param Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	2441	* @retval None
<>	128:9bcdf88f62b0	2442	*/
<>	128:9bcdf88f62b0	2443	__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
<>	128:9bcdf88f62b0	2444	{
<>	128:9bcdf88f62b0	2445	USARTx->DR = Value;
<>	128:9bcdf88f62b0	2446	}
<>	128:9bcdf88f62b0	2447
<>	128:9bcdf88f62b0	2448	/**
<>	128:9bcdf88f62b0	2449	* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
<>	128:9bcdf88f62b0	2450	* @rmtoll DR DR LL_USART_TransmitData9
<>	128:9bcdf88f62b0	2451	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2452	* @param Value between Min_Data=0x00 and Max_Data=0x1FF
<>	128:9bcdf88f62b0	2453	* @retval None
<>	128:9bcdf88f62b0	2454	*/
<>	128:9bcdf88f62b0	2455	__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
<>	128:9bcdf88f62b0	2456	{
<>	128:9bcdf88f62b0	2457	USARTx->DR = Value & 0x1FFU;
<>	128:9bcdf88f62b0	2458	}
<>	128:9bcdf88f62b0	2459
<>	128:9bcdf88f62b0	2460	/**
<>	128:9bcdf88f62b0	2461	* @}
<>	128:9bcdf88f62b0	2462	*/
<>	128:9bcdf88f62b0	2463
<>	128:9bcdf88f62b0	2464	/** @defgroup USART_LL_EF_Execution Execution
<>	128:9bcdf88f62b0	2465	* @{
<>	128:9bcdf88f62b0	2466	*/
<>	128:9bcdf88f62b0	2467
<>	128:9bcdf88f62b0	2468	/**
<>	128:9bcdf88f62b0	2469	* @brief Request Break sending
<>	128:9bcdf88f62b0	2470	* @rmtoll CR1 SBK LL_USART_RequestBreakSending
<>	128:9bcdf88f62b0	2471	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2472	* @retval None
<>	128:9bcdf88f62b0	2473	*/
<>	128:9bcdf88f62b0	2474	__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2475	{
<>	128:9bcdf88f62b0	2476	SET_BIT(USARTx->CR1, USART_CR1_SBK);
<>	128:9bcdf88f62b0	2477	}
<>	128:9bcdf88f62b0	2478
<>	128:9bcdf88f62b0	2479	/**
<>	128:9bcdf88f62b0	2480	* @brief Put USART in Mute mode
<>	128:9bcdf88f62b0	2481	* @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode
<>	128:9bcdf88f62b0	2482	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2483	* @retval None
<>	128:9bcdf88f62b0	2484	*/
<>	128:9bcdf88f62b0	2485	__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2486	{
<>	128:9bcdf88f62b0	2487	SET_BIT(USARTx->CR1, USART_CR1_RWU);
<>	128:9bcdf88f62b0	2488	}
<>	128:9bcdf88f62b0	2489
<>	128:9bcdf88f62b0	2490	/**
<>	128:9bcdf88f62b0	2491	* @brief Put USART in Active mode
<>	128:9bcdf88f62b0	2492	* @rmtoll CR1 RWU LL_USART_RequestExitMuteMode
<>	128:9bcdf88f62b0	2493	* @param USARTx USART Instance
<>	128:9bcdf88f62b0	2494	* @retval None
<>	128:9bcdf88f62b0	2495	*/
<>	128:9bcdf88f62b0	2496	__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
<>	128:9bcdf88f62b0	2497	{
<>	128:9bcdf88f62b0	2498	CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
<>	128:9bcdf88f62b0	2499	}
<>	128:9bcdf88f62b0	2500
<>	128:9bcdf88f62b0	2501	/**
<>	128:9bcdf88f62b0	2502	* @}
<>	128:9bcdf88f62b0	2503	*/
<>	128:9bcdf88f62b0	2504
<>	128:9bcdf88f62b0	2505	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	2506	/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
<>	128:9bcdf88f62b0	2507	* @{
<>	128:9bcdf88f62b0	2508	*/
<>	128:9bcdf88f62b0	2509	ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
<>	128:9bcdf88f62b0	2510	ErrorStatus LL_USART_Init(USART_TypeDef USARTx, LL_USART_InitTypeDef USART_InitStruct);
<>	128:9bcdf88f62b0	2511	void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
<>	128:9bcdf88f62b0	2512	ErrorStatus LL_USART_ClockInit(USART_TypeDef USARTx, LL_USART_ClockInitTypeDef USART_ClockInitStruct);
<>	128:9bcdf88f62b0	2513	void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
<>	128:9bcdf88f62b0	2514	/**
<>	128:9bcdf88f62b0	2515	* @}
<>	128:9bcdf88f62b0	2516	*/
<>	128:9bcdf88f62b0	2517	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	2518
<>	128:9bcdf88f62b0	2519	/**
<>	128:9bcdf88f62b0	2520	* @}
<>	128:9bcdf88f62b0	2521	*/
<>	128:9bcdf88f62b0	2522
<>	128:9bcdf88f62b0	2523	/**
<>	128:9bcdf88f62b0	2524	* @}
<>	128:9bcdf88f62b0	2525	*/
<>	128:9bcdf88f62b0	2526
<>	128:9bcdf88f62b0	2527	#endif /* USART1 \|\| USART2\|\| USART3 \|\| UART4 \|\| UART5 */
<>	128:9bcdf88f62b0	2528
<>	128:9bcdf88f62b0	2529	/**
<>	128:9bcdf88f62b0	2530	* @}
<>	128:9bcdf88f62b0	2531	*/
<>	128:9bcdf88f62b0	2532
<>	128:9bcdf88f62b0	2533	#ifdef __cplusplus
<>	128:9bcdf88f62b0	2534	}
<>	128:9bcdf88f62b0	2535	#endif
<>	128:9bcdf88f62b0	2536
<>	128:9bcdf88f62b0	2537	#endif /* __STM32L1xx_LL_USART_H */
<>	128:9bcdf88f62b0	2538
<>	128:9bcdf88f62b0	2539	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/