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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_ll_tim.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of TIM LL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_LL_TIM_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_LL_TIM_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_LL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @defgroup TIM_LL TIM
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /* Private types -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 60 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 61 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
<> 128:9bcdf88f62b0 62 * @{
<> 128:9bcdf88f62b0 63 */
<> 128:9bcdf88f62b0 64 static const uint8_t OFFSET_TAB_CCMRx[] =
<> 128:9bcdf88f62b0 65 {
<> 128:9bcdf88f62b0 66 0x00U, /* 0: TIMx_CH1 */
<> 128:9bcdf88f62b0 67 0x00U, /* 1: NA */
<> 128:9bcdf88f62b0 68 0x00U, /* 2: TIMx_CH2 */
<> 128:9bcdf88f62b0 69 0x00U, /* 3: NA */
<> 128:9bcdf88f62b0 70 0x04U, /* 4: TIMx_CH3 */
<> 128:9bcdf88f62b0 71 0x00U, /* 5: NA */
<> 128:9bcdf88f62b0 72 0x04U /* 6: TIMx_CH4 */
<> 128:9bcdf88f62b0 73 };
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 static const uint8_t SHIFT_TAB_OCxx[] =
<> 128:9bcdf88f62b0 76 {
<> 128:9bcdf88f62b0 77 0U, /* 0: OC1M, OC1FE, OC1PE */
<> 128:9bcdf88f62b0 78 0U, /* 1: - NA */
<> 128:9bcdf88f62b0 79 8U, /* 2: OC2M, OC2FE, OC2PE */
<> 128:9bcdf88f62b0 80 0U, /* 3: - NA */
<> 128:9bcdf88f62b0 81 0U, /* 4: OC3M, OC3FE, OC3PE */
<> 128:9bcdf88f62b0 82 0U, /* 5: - NA */
<> 128:9bcdf88f62b0 83 8U /* 6: OC4M, OC4FE, OC4PE */
<> 128:9bcdf88f62b0 84 };
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 static const uint8_t SHIFT_TAB_ICxx[] =
<> 128:9bcdf88f62b0 87 {
<> 128:9bcdf88f62b0 88 0U, /* 0: CC1S, IC1PSC, IC1F */
<> 128:9bcdf88f62b0 89 0U, /* 1: - NA */
<> 128:9bcdf88f62b0 90 8U, /* 2: CC2S, IC2PSC, IC2F */
<> 128:9bcdf88f62b0 91 0U, /* 3: - NA */
<> 128:9bcdf88f62b0 92 0U, /* 4: CC3S, IC3PSC, IC3F */
<> 128:9bcdf88f62b0 93 0U, /* 5: - NA */
<> 128:9bcdf88f62b0 94 8U /* 6: CC4S, IC4PSC, IC4F */
<> 128:9bcdf88f62b0 95 };
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 static const uint8_t SHIFT_TAB_CCxP[] =
<> 128:9bcdf88f62b0 98 {
<> 128:9bcdf88f62b0 99 0U, /* 0: CC1P */
<> 128:9bcdf88f62b0 100 0U, /* 1: NA */
<> 128:9bcdf88f62b0 101 4U, /* 2: CC2P */
<> 128:9bcdf88f62b0 102 0U, /* 3: NA */
<> 128:9bcdf88f62b0 103 8U, /* 4: CC3P */
<> 128:9bcdf88f62b0 104 0U, /* 5: NA */
<> 128:9bcdf88f62b0 105 12U /* 6: CC4P */
<> 128:9bcdf88f62b0 106 };
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 /**
<> 128:9bcdf88f62b0 109 * @}
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
<> 128:9bcdf88f62b0 115 * @{
<> 128:9bcdf88f62b0 116 */
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 #define TIMx_OR_RMP_SHIFT ((uint32_t)16U)
<> 128:9bcdf88f62b0 120 #define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU)
<> 128:9bcdf88f62b0 121 #define TIM_OR_RMP_MASK ((uint32_t)((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT))
<> 128:9bcdf88f62b0 122 #define TIM9_OR_RMP_MASK ((uint32_t)((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT))
<> 128:9bcdf88f62b0 123 #define TIM2_OR_RMP_MASK ((uint32_t)(TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT))
<> 128:9bcdf88f62b0 124 #define TIM3_OR_RMP_MASK ((uint32_t)(TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT))
<> 128:9bcdf88f62b0 125
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 /**
<> 128:9bcdf88f62b0 129 * @}
<> 128:9bcdf88f62b0 130 */
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 134 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
<> 128:9bcdf88f62b0 135 * @{
<> 128:9bcdf88f62b0 136 */
<> 128:9bcdf88f62b0 137 /** @brief Convert channel id into channel index.
<> 128:9bcdf88f62b0 138 * @param __CHANNEL__ This parameter can be one of the following values:
<> 128:9bcdf88f62b0 139 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 140 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 141 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 142 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 143 * @retval none
<> 128:9bcdf88f62b0 144 */
<> 128:9bcdf88f62b0 145 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<> 128:9bcdf88f62b0 146 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<> 128:9bcdf88f62b0 147 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<> 128:9bcdf88f62b0 148 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
<> 128:9bcdf88f62b0 149
<> 128:9bcdf88f62b0 150 /**
<> 128:9bcdf88f62b0 151 * @}
<> 128:9bcdf88f62b0 152 */
<> 128:9bcdf88f62b0 153
<> 128:9bcdf88f62b0 154
<> 128:9bcdf88f62b0 155 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 156 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 157 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<> 128:9bcdf88f62b0 158 * @{
<> 128:9bcdf88f62b0 159 */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 /**
<> 128:9bcdf88f62b0 162 * @brief TIM Time Base configuration structure definition.
<> 128:9bcdf88f62b0 163 */
<> 128:9bcdf88f62b0 164 typedef struct
<> 128:9bcdf88f62b0 165 {
<> 128:9bcdf88f62b0 166 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<> 128:9bcdf88f62b0 167 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<> 128:9bcdf88f62b0 170
<> 128:9bcdf88f62b0 171 uint32_t CounterMode; /*!< Specifies the counter mode.
<> 128:9bcdf88f62b0 172 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<> 128:9bcdf88f62b0 175
<> 128:9bcdf88f62b0 176 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<> 128:9bcdf88f62b0 177 Auto-Reload Register at the next update event.
<> 128:9bcdf88f62b0 178 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<> 128:9bcdf88f62b0 179 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 uint32_t ClockDivision; /*!< Specifies the clock division.
<> 128:9bcdf88f62b0 184 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<> 128:9bcdf88f62b0 185
<> 128:9bcdf88f62b0 186 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<> 128:9bcdf88f62b0 187 } LL_TIM_InitTypeDef;
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 /**
<> 128:9bcdf88f62b0 190 * @brief TIM Output Compare configuration structure definition.
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192 typedef struct
<> 128:9bcdf88f62b0 193 {
<> 128:9bcdf88f62b0 194 uint32_t OCMode; /*!< Specifies the output mode.
<> 128:9bcdf88f62b0 195 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<> 128:9bcdf88f62b0 200 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<> 128:9bcdf88f62b0 203
<> 128:9bcdf88f62b0 204 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<> 128:9bcdf88f62b0 205 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<> 128:9bcdf88f62b0 206
<> 128:9bcdf88f62b0 207 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 128:9bcdf88f62b0 210 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<> 128:9bcdf88f62b0 211
<> 128:9bcdf88f62b0 212 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<> 128:9bcdf88f62b0 213
<> 128:9bcdf88f62b0 214 } LL_TIM_OC_InitTypeDef;
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 /**
<> 128:9bcdf88f62b0 217 * @brief TIM Input Capture configuration structure definition.
<> 128:9bcdf88f62b0 218 */
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220 typedef struct
<> 128:9bcdf88f62b0 221 {
<> 128:9bcdf88f62b0 222
<> 128:9bcdf88f62b0 223 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 224 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 uint32_t ICActiveInput; /*!< Specifies the input.
<> 128:9bcdf88f62b0 229 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<> 128:9bcdf88f62b0 230
<> 128:9bcdf88f62b0 231 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<> 128:9bcdf88f62b0 234 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 128:9bcdf88f62b0 239 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<> 128:9bcdf88f62b0 242 } LL_TIM_IC_InitTypeDef;
<> 128:9bcdf88f62b0 243
<> 128:9bcdf88f62b0 244
<> 128:9bcdf88f62b0 245 /**
<> 128:9bcdf88f62b0 246 * @brief TIM Encoder interface configuration structure definition.
<> 128:9bcdf88f62b0 247 */
<> 128:9bcdf88f62b0 248 typedef struct
<> 128:9bcdf88f62b0 249 {
<> 128:9bcdf88f62b0 250 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<> 128:9bcdf88f62b0 251 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<> 128:9bcdf88f62b0 252
<> 128:9bcdf88f62b0 253 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<> 128:9bcdf88f62b0 256 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<> 128:9bcdf88f62b0 261 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<> 128:9bcdf88f62b0 266 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<> 128:9bcdf88f62b0 267
<> 128:9bcdf88f62b0 268 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<> 128:9bcdf88f62b0 271 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<> 128:9bcdf88f62b0 272
<> 128:9bcdf88f62b0 273 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<> 128:9bcdf88f62b0 274
<> 128:9bcdf88f62b0 275 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<> 128:9bcdf88f62b0 276 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<> 128:9bcdf88f62b0 277
<> 128:9bcdf88f62b0 278 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<> 128:9bcdf88f62b0 279
<> 128:9bcdf88f62b0 280 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<> 128:9bcdf88f62b0 281 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<> 128:9bcdf88f62b0 282
<> 128:9bcdf88f62b0 283 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<> 128:9bcdf88f62b0 286 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<> 128:9bcdf88f62b0 289
<> 128:9bcdf88f62b0 290 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<> 128:9bcdf88f62b0 291 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<> 128:9bcdf88f62b0 292
<> 128:9bcdf88f62b0 293 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<> 128:9bcdf88f62b0 294
<> 128:9bcdf88f62b0 295 } LL_TIM_ENCODER_InitTypeDef;
<> 128:9bcdf88f62b0 296
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 /**
<> 128:9bcdf88f62b0 299 * @}
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 302
<> 128:9bcdf88f62b0 303 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 304 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<> 128:9bcdf88f62b0 305 * @{
<> 128:9bcdf88f62b0 306 */
<> 128:9bcdf88f62b0 307
<> 128:9bcdf88f62b0 308 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<> 128:9bcdf88f62b0 309 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
<> 128:9bcdf88f62b0 310 * @{
<> 128:9bcdf88f62b0 311 */
<> 128:9bcdf88f62b0 312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
<> 128:9bcdf88f62b0 313 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
<> 128:9bcdf88f62b0 314 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
<> 128:9bcdf88f62b0 315 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
<> 128:9bcdf88f62b0 316 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
<> 128:9bcdf88f62b0 317 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
<> 128:9bcdf88f62b0 318 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
<> 128:9bcdf88f62b0 319 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
<> 128:9bcdf88f62b0 320 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
<> 128:9bcdf88f62b0 321 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
<> 128:9bcdf88f62b0 322 /**
<> 128:9bcdf88f62b0 323 * @}
<> 128:9bcdf88f62b0 324 */
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /** @defgroup TIM_LL_EC_IT IT Defines
<> 128:9bcdf88f62b0 327 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<> 128:9bcdf88f62b0 328 * @{
<> 128:9bcdf88f62b0 329 */
<> 128:9bcdf88f62b0 330 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
<> 128:9bcdf88f62b0 331 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
<> 128:9bcdf88f62b0 332 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
<> 128:9bcdf88f62b0 333 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
<> 128:9bcdf88f62b0 334 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
<> 128:9bcdf88f62b0 335 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
<> 128:9bcdf88f62b0 336 /**
<> 128:9bcdf88f62b0 337 * @}
<> 128:9bcdf88f62b0 338 */
<> 128:9bcdf88f62b0 339
<> 128:9bcdf88f62b0 340 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<> 128:9bcdf88f62b0 341 * @{
<> 128:9bcdf88f62b0 342 */
<> 128:9bcdf88f62b0 343 #define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
<> 128:9bcdf88f62b0 344 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
<> 128:9bcdf88f62b0 345 /**
<> 128:9bcdf88f62b0 346 * @}
<> 128:9bcdf88f62b0 347 */
<> 128:9bcdf88f62b0 348
<> 128:9bcdf88f62b0 349 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<> 128:9bcdf88f62b0 350 * @{
<> 128:9bcdf88f62b0 351 */
<> 128:9bcdf88f62b0 352 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
<> 128:9bcdf88f62b0 353 #define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
<> 128:9bcdf88f62b0 354 /**
<> 128:9bcdf88f62b0 355 * @}
<> 128:9bcdf88f62b0 356 */
<> 128:9bcdf88f62b0 357
<> 128:9bcdf88f62b0 358 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<> 128:9bcdf88f62b0 359 * @{
<> 128:9bcdf88f62b0 360 */
<> 128:9bcdf88f62b0 361 #define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
<> 128:9bcdf88f62b0 362 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
<> 128:9bcdf88f62b0 363 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
<> 128:9bcdf88f62b0 364 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
<> 128:9bcdf88f62b0 365 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
<> 128:9bcdf88f62b0 366 /**
<> 128:9bcdf88f62b0 367 * @}
<> 128:9bcdf88f62b0 368 */
<> 128:9bcdf88f62b0 369
<> 128:9bcdf88f62b0 370 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<> 128:9bcdf88f62b0 371 * @{
<> 128:9bcdf88f62b0 372 */
<> 128:9bcdf88f62b0 373 #define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
<> 128:9bcdf88f62b0 374 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
<> 128:9bcdf88f62b0 375 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
<> 128:9bcdf88f62b0 376 /**
<> 128:9bcdf88f62b0 377 * @}
<> 128:9bcdf88f62b0 378 */
<> 128:9bcdf88f62b0 379
<> 128:9bcdf88f62b0 380 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<> 128:9bcdf88f62b0 381 * @{
<> 128:9bcdf88f62b0 382 */
<> 128:9bcdf88f62b0 383 #define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /*!< Timer counter counts up */
<> 128:9bcdf88f62b0 384 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
<> 128:9bcdf88f62b0 385 /**
<> 128:9bcdf88f62b0 386 * @}
<> 128:9bcdf88f62b0 387 */
<> 128:9bcdf88f62b0 388
<> 128:9bcdf88f62b0 389
<> 128:9bcdf88f62b0 390 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<> 128:9bcdf88f62b0 391 * @{
<> 128:9bcdf88f62b0 392 */
<> 128:9bcdf88f62b0 393 #define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
<> 128:9bcdf88f62b0 394 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
<> 128:9bcdf88f62b0 395 /**
<> 128:9bcdf88f62b0 396 * @}
<> 128:9bcdf88f62b0 397 */
<> 128:9bcdf88f62b0 398
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 /** @defgroup TIM_LL_EC_CHANNEL Channel
<> 128:9bcdf88f62b0 401 * @{
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
<> 128:9bcdf88f62b0 404 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
<> 128:9bcdf88f62b0 405 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
<> 128:9bcdf88f62b0 406 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
<> 128:9bcdf88f62b0 407 /**
<> 128:9bcdf88f62b0 408 * @}
<> 128:9bcdf88f62b0 409 */
<> 128:9bcdf88f62b0 410
<> 128:9bcdf88f62b0 411 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 412 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<> 128:9bcdf88f62b0 413 * @{
<> 128:9bcdf88f62b0 414 */
<> 128:9bcdf88f62b0 415 #define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /*!< OCx is not active */
<> 128:9bcdf88f62b0 416 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
<> 128:9bcdf88f62b0 417 /**
<> 128:9bcdf88f62b0 418 * @}
<> 128:9bcdf88f62b0 419 */
<> 128:9bcdf88f62b0 420 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 421
<> 128:9bcdf88f62b0 422 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<> 128:9bcdf88f62b0 423 * @{
<> 128:9bcdf88f62b0 424 */
<> 128:9bcdf88f62b0 425 #define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
<> 128:9bcdf88f62b0 426 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
<> 128:9bcdf88f62b0 427 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
<> 128:9bcdf88f62b0 428 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
<> 128:9bcdf88f62b0 429 #define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/
<> 128:9bcdf88f62b0 430 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
<> 128:9bcdf88f62b0 431 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
<> 128:9bcdf88f62b0 432 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
<> 128:9bcdf88f62b0 433 /**
<> 128:9bcdf88f62b0 434 * @}
<> 128:9bcdf88f62b0 435 */
<> 128:9bcdf88f62b0 436
<> 128:9bcdf88f62b0 437 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<> 128:9bcdf88f62b0 438 * @{
<> 128:9bcdf88f62b0 439 */
<> 128:9bcdf88f62b0 440 #define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/
<> 128:9bcdf88f62b0 441 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
<> 128:9bcdf88f62b0 442 /**
<> 128:9bcdf88f62b0 443 * @}
<> 128:9bcdf88f62b0 444 */
<> 128:9bcdf88f62b0 445
<> 128:9bcdf88f62b0 446
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<> 128:9bcdf88f62b0 449 * @{
<> 128:9bcdf88f62b0 450 */
<> 128:9bcdf88f62b0 451 #define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
<> 128:9bcdf88f62b0 452 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
<> 128:9bcdf88f62b0 453 #define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
<> 128:9bcdf88f62b0 454 /**
<> 128:9bcdf88f62b0 455 * @}
<> 128:9bcdf88f62b0 456 */
<> 128:9bcdf88f62b0 457
<> 128:9bcdf88f62b0 458 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<> 128:9bcdf88f62b0 459 * @{
<> 128:9bcdf88f62b0 460 */
<> 128:9bcdf88f62b0 461 #define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
<> 128:9bcdf88f62b0 462 #define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
<> 128:9bcdf88f62b0 463 #define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
<> 128:9bcdf88f62b0 464 #define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
<> 128:9bcdf88f62b0 465 /**
<> 128:9bcdf88f62b0 466 * @}
<> 128:9bcdf88f62b0 467 */
<> 128:9bcdf88f62b0 468
<> 128:9bcdf88f62b0 469 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<> 128:9bcdf88f62b0 470 * @{
<> 128:9bcdf88f62b0 471 */
<> 128:9bcdf88f62b0 472 #define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */
<> 128:9bcdf88f62b0 473 #define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
<> 128:9bcdf88f62b0 474 #define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
<> 128:9bcdf88f62b0 475 #define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
<> 128:9bcdf88f62b0 476 #define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
<> 128:9bcdf88f62b0 477 #define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
<> 128:9bcdf88f62b0 478 #define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
<> 128:9bcdf88f62b0 479 #define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
<> 128:9bcdf88f62b0 480 #define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
<> 128:9bcdf88f62b0 481 #define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
<> 128:9bcdf88f62b0 482 #define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
<> 128:9bcdf88f62b0 483 #define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
<> 128:9bcdf88f62b0 484 #define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
<> 128:9bcdf88f62b0 485 #define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
<> 128:9bcdf88f62b0 486 #define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
<> 128:9bcdf88f62b0 487 #define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
<> 128:9bcdf88f62b0 488 /**
<> 128:9bcdf88f62b0 489 * @}
<> 128:9bcdf88f62b0 490 */
<> 128:9bcdf88f62b0 491
<> 128:9bcdf88f62b0 492 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<> 128:9bcdf88f62b0 493 * @{
<> 128:9bcdf88f62b0 494 */
<> 128:9bcdf88f62b0 495 #define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
<> 128:9bcdf88f62b0 496 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
<> 128:9bcdf88f62b0 497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
<> 128:9bcdf88f62b0 498 /**
<> 128:9bcdf88f62b0 499 * @}
<> 128:9bcdf88f62b0 500 */
<> 128:9bcdf88f62b0 501
<> 128:9bcdf88f62b0 502 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<> 128:9bcdf88f62b0 503 * @{
<> 128:9bcdf88f62b0 504 */
<> 128:9bcdf88f62b0 505 #define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< The timer is clocked by the internal clock provided from the RCC */
<> 128:9bcdf88f62b0 506 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
<> 128:9bcdf88f62b0 507 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
<> 128:9bcdf88f62b0 508 /**
<> 128:9bcdf88f62b0 509 * @}
<> 128:9bcdf88f62b0 510 */
<> 128:9bcdf88f62b0 511
<> 128:9bcdf88f62b0 512 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<> 128:9bcdf88f62b0 513 * @{
<> 128:9bcdf88f62b0 514 */
<> 128:9bcdf88f62b0 515 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
<> 128:9bcdf88f62b0 516 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
<> 128:9bcdf88f62b0 517 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
<> 128:9bcdf88f62b0 518 /**
<> 128:9bcdf88f62b0 519 * @}
<> 128:9bcdf88f62b0 520 */
<> 128:9bcdf88f62b0 521
<> 128:9bcdf88f62b0 522 /** @defgroup TIM_LL_EC_TRGO Trigger Output
<> 128:9bcdf88f62b0 523 * @{
<> 128:9bcdf88f62b0 524 */
<> 128:9bcdf88f62b0 525 #define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /*!< UG bit from the TIMx_EGR register is used as trigger output */
<> 128:9bcdf88f62b0 526 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
<> 128:9bcdf88f62b0 527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
<> 128:9bcdf88f62b0 528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
<> 128:9bcdf88f62b0 529 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
<> 128:9bcdf88f62b0 530 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
<> 128:9bcdf88f62b0 531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
<> 128:9bcdf88f62b0 532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
<> 128:9bcdf88f62b0 533 /**
<> 128:9bcdf88f62b0 534 * @}
<> 128:9bcdf88f62b0 535 */
<> 128:9bcdf88f62b0 536
<> 128:9bcdf88f62b0 537
<> 128:9bcdf88f62b0 538 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<> 128:9bcdf88f62b0 539 * @{
<> 128:9bcdf88f62b0 540 */
<> 128:9bcdf88f62b0 541 #define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /*!< Slave mode disabled */
<> 128:9bcdf88f62b0 542 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
<> 128:9bcdf88f62b0 543 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
<> 128:9bcdf88f62b0 544 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
<> 128:9bcdf88f62b0 545 /**
<> 128:9bcdf88f62b0 546 * @}
<> 128:9bcdf88f62b0 547 */
<> 128:9bcdf88f62b0 548
<> 128:9bcdf88f62b0 549 /** @defgroup TIM_LL_EC_TS Trigger Selection
<> 128:9bcdf88f62b0 550 * @{
<> 128:9bcdf88f62b0 551 */
<> 128:9bcdf88f62b0 552 #define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /*!< Internal Trigger 0 (ITR0) is used as trigger input */
<> 128:9bcdf88f62b0 553 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
<> 128:9bcdf88f62b0 554 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
<> 128:9bcdf88f62b0 555 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
<> 128:9bcdf88f62b0 556 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
<> 128:9bcdf88f62b0 557 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
<> 128:9bcdf88f62b0 558 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
<> 128:9bcdf88f62b0 559 #define LL_TIM_TS_ETRF TIM_SMCR_TS /*!< Filtered external Trigger (ETRF) is used as trigger input */
<> 128:9bcdf88f62b0 560 /**
<> 128:9bcdf88f62b0 561 * @}
<> 128:9bcdf88f62b0 562 */
<> 128:9bcdf88f62b0 563
<> 128:9bcdf88f62b0 564 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<> 128:9bcdf88f62b0 565 * @{
<> 128:9bcdf88f62b0 566 */
<> 128:9bcdf88f62b0 567 #define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
<> 128:9bcdf88f62b0 568 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
<> 128:9bcdf88f62b0 569 /**
<> 128:9bcdf88f62b0 570 * @}
<> 128:9bcdf88f62b0 571 */
<> 128:9bcdf88f62b0 572
<> 128:9bcdf88f62b0 573 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<> 128:9bcdf88f62b0 574 * @{
<> 128:9bcdf88f62b0 575 */
<> 128:9bcdf88f62b0 576 #define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
<> 128:9bcdf88f62b0 577 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
<> 128:9bcdf88f62b0 578 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
<> 128:9bcdf88f62b0 579 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
<> 128:9bcdf88f62b0 580 /**
<> 128:9bcdf88f62b0 581 * @}
<> 128:9bcdf88f62b0 582 */
<> 128:9bcdf88f62b0 583
<> 128:9bcdf88f62b0 584 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<> 128:9bcdf88f62b0 585 * @{
<> 128:9bcdf88f62b0 586 */
<> 128:9bcdf88f62b0 587 #define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */
<> 128:9bcdf88f62b0 588 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
<> 128:9bcdf88f62b0 589 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
<> 128:9bcdf88f62b0 590 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
<> 128:9bcdf88f62b0 591 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
<> 128:9bcdf88f62b0 592 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
<> 128:9bcdf88f62b0 593 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */
<> 128:9bcdf88f62b0 594 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
<> 128:9bcdf88f62b0 595 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
<> 128:9bcdf88f62b0 596 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
<> 128:9bcdf88f62b0 597 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */
<> 128:9bcdf88f62b0 598 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
<> 128:9bcdf88f62b0 599 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */
<> 128:9bcdf88f62b0 600 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
<> 128:9bcdf88f62b0 601 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
<> 128:9bcdf88f62b0 602 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
<> 128:9bcdf88f62b0 603 /**
<> 128:9bcdf88f62b0 604 * @}
<> 128:9bcdf88f62b0 605 */
<> 128:9bcdf88f62b0 606
<> 128:9bcdf88f62b0 607
<> 128:9bcdf88f62b0 608
<> 128:9bcdf88f62b0 609
<> 128:9bcdf88f62b0 610
<> 128:9bcdf88f62b0 611
<> 128:9bcdf88f62b0 612
<> 128:9bcdf88f62b0 613 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<> 128:9bcdf88f62b0 614 * @{
<> 128:9bcdf88f62b0 615 */
<> 128:9bcdf88f62b0 616 #define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 617 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 618 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 619 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 620 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 621 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 622 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 623 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 624 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 625 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 626 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 627 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 628 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 629 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 630 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 631 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 632 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
<> 128:9bcdf88f62b0 633 /**
<> 128:9bcdf88f62b0 634 * @}
<> 128:9bcdf88f62b0 635 */
<> 128:9bcdf88f62b0 636
<> 128:9bcdf88f62b0 637 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<> 128:9bcdf88f62b0 638 * @{
<> 128:9bcdf88f62b0 639 */
<> 128:9bcdf88f62b0 640 #define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /*!< Transfer is done to 1 register starting from the DMA burst base address */
<> 128:9bcdf88f62b0 641 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 642 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 643 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 644 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 645 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 646 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 647 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 648 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 649 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 650 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 651 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 652 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 653 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 654 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 655 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 656 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 657 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
<> 128:9bcdf88f62b0 658 /**
<> 128:9bcdf88f62b0 659 * @}
<> 128:9bcdf88f62b0 660 */
<> 128:9bcdf88f62b0 661
<> 128:9bcdf88f62b0 662 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
<> 128:9bcdf88f62b0 663 * @{
<> 128:9bcdf88f62b0 664 */
<> 128:9bcdf88f62b0 665 #define LL_TIM_TIM10_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 666 #define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSI internal clock */
<> 128:9bcdf88f62b0 667 #define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSE internal clock */
<> 128:9bcdf88f62b0 668 #define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */
<> 128:9bcdf88f62b0 669 /**
<> 128:9bcdf88f62b0 670 * @}
<> 128:9bcdf88f62b0 671 */
<> 128:9bcdf88f62b0 672
<> 128:9bcdf88f62b0 673 /** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
<> 128:9bcdf88f62b0 674 * @{
<> 128:9bcdf88f62b0 675 */
<> 128:9bcdf88f62b0 676 #define LL_TIM_TIM10_ETR_RMP_LSE ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to LSE */
<> 128:9bcdf88f62b0 677 #define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to TIM9 TGO */
<> 128:9bcdf88f62b0 678 /**
<> 128:9bcdf88f62b0 679 * @}
<> 128:9bcdf88f62b0 680 */
<> 128:9bcdf88f62b0 681
<> 128:9bcdf88f62b0 682 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
<> 128:9bcdf88f62b0 683 * @{
<> 128:9bcdf88f62b0 684 */
<> 128:9bcdf88f62b0 685 #define LL_TIM_TIM10_TI1_RMP ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
<> 128:9bcdf88f62b0 686 #define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RI */
<> 128:9bcdf88f62b0 687 /**
<> 128:9bcdf88f62b0 688 * @}
<> 128:9bcdf88f62b0 689 */
<> 128:9bcdf88f62b0 690
<> 128:9bcdf88f62b0 691 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
<> 128:9bcdf88f62b0 692 * @{
<> 128:9bcdf88f62b0 693 */
<> 128:9bcdf88f62b0 694 #define LL_TIM_TIM11_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 695 #define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to MSI internal clock */
<> 128:9bcdf88f62b0 696 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to HSE RTC clock */
<> 128:9bcdf88f62b0 697 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 698 /**
<> 128:9bcdf88f62b0 699 * @}
<> 128:9bcdf88f62b0 700 */
<> 128:9bcdf88f62b0 701
<> 128:9bcdf88f62b0 702 /** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
<> 128:9bcdf88f62b0 703 * @{
<> 128:9bcdf88f62b0 704 */
<> 128:9bcdf88f62b0 705 #define LL_TIM_TIM11_ETR_RMP_LSE ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to LSE */
<> 128:9bcdf88f62b0 706 #define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to TIM9 TGO clock */
<> 128:9bcdf88f62b0 707 /**
<> 128:9bcdf88f62b0 708 * @}
<> 128:9bcdf88f62b0 709 */
<> 128:9bcdf88f62b0 710
<> 128:9bcdf88f62b0 711 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
<> 128:9bcdf88f62b0 712 * @{
<> 128:9bcdf88f62b0 713 */
<> 128:9bcdf88f62b0 714 #define LL_TIM_TIM11_TI1_RMP ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
<> 128:9bcdf88f62b0 715 #define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to RI */
<> 128:9bcdf88f62b0 716 /**
<> 128:9bcdf88f62b0 717 * @}
<> 128:9bcdf88f62b0 718 */
<> 128:9bcdf88f62b0 719
<> 128:9bcdf88f62b0 720 /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
<> 128:9bcdf88f62b0 721 * @{
<> 128:9bcdf88f62b0 722 */
<> 128:9bcdf88f62b0 723 #define LL_TIM_TIM9_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 724 #define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to LSE internal clock */
<> 128:9bcdf88f62b0 725 #define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 726 #define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 727 /**
<> 128:9bcdf88f62b0 728 * @}
<> 128:9bcdf88f62b0 729 */
<> 128:9bcdf88f62b0 730
<> 128:9bcdf88f62b0 731 /** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
<> 128:9bcdf88f62b0 732 * @{
<> 128:9bcdf88f62b0 733 */
<> 128:9bcdf88f62b0 734 #define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to TIM3 TGO signal */
<> 128:9bcdf88f62b0 735 #define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to touch sensing I/O */
<> 128:9bcdf88f62b0 736 /**
<> 128:9bcdf88f62b0 737 * @}
<> 128:9bcdf88f62b0 738 */
<> 128:9bcdf88f62b0 739
<> 128:9bcdf88f62b0 740 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
<> 128:9bcdf88f62b0 741 * @{
<> 128:9bcdf88f62b0 742 */
<> 128:9bcdf88f62b0 743 #define LL_TIM_TIM2_TIR1_RMP_TIM10_OC ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM10 OC*/
<> 128:9bcdf88f62b0 744 #define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM5 TGO */
<> 128:9bcdf88f62b0 745 /**
<> 128:9bcdf88f62b0 746 * @}
<> 128:9bcdf88f62b0 747 */
<> 128:9bcdf88f62b0 748
<> 128:9bcdf88f62b0 749 /** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
<> 128:9bcdf88f62b0 750 * @{
<> 128:9bcdf88f62b0 751 */
<> 128:9bcdf88f62b0 752 #define LL_TIM_TIM3_TIR2_RMP_TIM11_OC ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM11 OC */
<> 128:9bcdf88f62b0 753 #define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM5 TGO */
<> 128:9bcdf88f62b0 754 /**
<> 128:9bcdf88f62b0 755 * @}
<> 128:9bcdf88f62b0 756 */
<> 128:9bcdf88f62b0 757
<> 128:9bcdf88f62b0 758
<> 128:9bcdf88f62b0 759 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<> 128:9bcdf88f62b0 760 * @{
<> 128:9bcdf88f62b0 761 */
<> 128:9bcdf88f62b0 762 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
<> 128:9bcdf88f62b0 763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
<> 128:9bcdf88f62b0 764 /**
<> 128:9bcdf88f62b0 765 * @}
<> 128:9bcdf88f62b0 766 */
<> 128:9bcdf88f62b0 767
<> 128:9bcdf88f62b0 768
<> 128:9bcdf88f62b0 769 /**
<> 128:9bcdf88f62b0 770 * @}
<> 128:9bcdf88f62b0 771 */
<> 128:9bcdf88f62b0 772
<> 128:9bcdf88f62b0 773 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 774 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<> 128:9bcdf88f62b0 775 * @{
<> 128:9bcdf88f62b0 776 */
<> 128:9bcdf88f62b0 777
<> 128:9bcdf88f62b0 778 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<> 128:9bcdf88f62b0 779 * @{
<> 128:9bcdf88f62b0 780 */
<> 128:9bcdf88f62b0 781 /**
<> 128:9bcdf88f62b0 782 * @brief Write a value in TIM register.
<> 128:9bcdf88f62b0 783 * @param __INSTANCE__ TIM Instance
<> 128:9bcdf88f62b0 784 * @param __REG__ Register to be written
<> 128:9bcdf88f62b0 785 * @param __VALUE__ Value to be written in the register
<> 128:9bcdf88f62b0 786 * @retval None
<> 128:9bcdf88f62b0 787 */
<> 128:9bcdf88f62b0 788 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 128:9bcdf88f62b0 789
<> 128:9bcdf88f62b0 790 /**
<> 128:9bcdf88f62b0 791 * @brief Read a value in TIM register.
<> 128:9bcdf88f62b0 792 * @param __INSTANCE__ TIM Instance
<> 128:9bcdf88f62b0 793 * @param __REG__ Register to be read
<> 128:9bcdf88f62b0 794 * @retval Register value
<> 128:9bcdf88f62b0 795 */
<> 128:9bcdf88f62b0 796 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 128:9bcdf88f62b0 797 /**
<> 128:9bcdf88f62b0 798 * @}
<> 128:9bcdf88f62b0 799 */
<> 128:9bcdf88f62b0 800
<> 128:9bcdf88f62b0 801 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<> 128:9bcdf88f62b0 802 * @{
<> 128:9bcdf88f62b0 803 */
<> 128:9bcdf88f62b0 804
<> 128:9bcdf88f62b0 805
<> 128:9bcdf88f62b0 806 /**
<> 128:9bcdf88f62b0 807 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<> 128:9bcdf88f62b0 808 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<> 128:9bcdf88f62b0 809 * @param __TIMCLK__ timer input clock frequency (in Hz)
<> 128:9bcdf88f62b0 810 * @param __CNTCLK__ counter clock frequency (in Hz)
<> 128:9bcdf88f62b0 811 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 812 */
<> 128:9bcdf88f62b0 813 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<> 128:9bcdf88f62b0 814 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<> 128:9bcdf88f62b0 815
<> 128:9bcdf88f62b0 816 /**
<> 128:9bcdf88f62b0 817 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<> 128:9bcdf88f62b0 818 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<> 128:9bcdf88f62b0 819 * @param __TIMCLK__ timer input clock frequency (in Hz)
<> 128:9bcdf88f62b0 820 * @param __PSC__ prescaler
<> 128:9bcdf88f62b0 821 * @param __FREQ__ output signal frequency (in Hz)
<> 128:9bcdf88f62b0 822 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 823 */
<> 128:9bcdf88f62b0 824 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<> 128:9bcdf88f62b0 825 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<> 128:9bcdf88f62b0 826
<> 128:9bcdf88f62b0 827 /**
<> 128:9bcdf88f62b0 828 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<> 128:9bcdf88f62b0 829 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<> 128:9bcdf88f62b0 830 * @param __TIMCLK__ timer input clock frequency (in Hz)
<> 128:9bcdf88f62b0 831 * @param __PSC__ prescaler
<> 128:9bcdf88f62b0 832 * @param __DELAY__ timer output compare active/inactive delay (in us)
<> 128:9bcdf88f62b0 833 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 834 */
<> 128:9bcdf88f62b0 835 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<> 128:9bcdf88f62b0 836 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<> 128:9bcdf88f62b0 837 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<> 128:9bcdf88f62b0 838
<> 128:9bcdf88f62b0 839 /**
<> 128:9bcdf88f62b0 840 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<> 128:9bcdf88f62b0 841 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<> 128:9bcdf88f62b0 842 * @param __TIMCLK__ timer input clock frequency (in Hz)
<> 128:9bcdf88f62b0 843 * @param __PSC__ prescaler
<> 128:9bcdf88f62b0 844 * @param __DELAY__ timer output compare active/inactive delay (in us)
<> 128:9bcdf88f62b0 845 * @param __PULSE__ pulse duration (in us)
<> 128:9bcdf88f62b0 846 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 847 */
<> 128:9bcdf88f62b0 848 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<> 128:9bcdf88f62b0 849 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<> 128:9bcdf88f62b0 850 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<> 128:9bcdf88f62b0 851
<> 128:9bcdf88f62b0 852 /**
<> 128:9bcdf88f62b0 853 * @brief HELPER macro retrieving the ratio of the input capture prescaler
<> 128:9bcdf88f62b0 854 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<> 128:9bcdf88f62b0 855 * @param __ICPSC__ This parameter can be one of the following values:
<> 128:9bcdf88f62b0 856 * @arg @ref LL_TIM_ICPSC_DIV1
<> 128:9bcdf88f62b0 857 * @arg @ref LL_TIM_ICPSC_DIV2
<> 128:9bcdf88f62b0 858 * @arg @ref LL_TIM_ICPSC_DIV4
<> 128:9bcdf88f62b0 859 * @arg @ref LL_TIM_ICPSC_DIV8
<> 128:9bcdf88f62b0 860 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
<> 128:9bcdf88f62b0 861 */
<> 128:9bcdf88f62b0 862 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
<> 128:9bcdf88f62b0 863 ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<> 128:9bcdf88f62b0 864
<> 128:9bcdf88f62b0 865
<> 128:9bcdf88f62b0 866 /**
<> 128:9bcdf88f62b0 867 * @}
<> 128:9bcdf88f62b0 868 */
<> 128:9bcdf88f62b0 869
<> 128:9bcdf88f62b0 870
<> 128:9bcdf88f62b0 871 /**
<> 128:9bcdf88f62b0 872 * @}
<> 128:9bcdf88f62b0 873 */
<> 128:9bcdf88f62b0 874
<> 128:9bcdf88f62b0 875 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 876 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<> 128:9bcdf88f62b0 877 * @{
<> 128:9bcdf88f62b0 878 */
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<> 128:9bcdf88f62b0 881 * @{
<> 128:9bcdf88f62b0 882 */
<> 128:9bcdf88f62b0 883 /**
<> 128:9bcdf88f62b0 884 * @brief Enable timer counter.
<> 128:9bcdf88f62b0 885 * @rmtoll CR1 CEN LL_TIM_EnableCounter
<> 128:9bcdf88f62b0 886 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 887 * @retval None
<> 128:9bcdf88f62b0 888 */
<> 128:9bcdf88f62b0 889 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 890 {
<> 128:9bcdf88f62b0 891 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<> 128:9bcdf88f62b0 892 }
<> 128:9bcdf88f62b0 893
<> 128:9bcdf88f62b0 894 /**
<> 128:9bcdf88f62b0 895 * @brief Disable timer counter.
<> 128:9bcdf88f62b0 896 * @rmtoll CR1 CEN LL_TIM_DisableCounter
<> 128:9bcdf88f62b0 897 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 898 * @retval None
<> 128:9bcdf88f62b0 899 */
<> 128:9bcdf88f62b0 900 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 901 {
<> 128:9bcdf88f62b0 902 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<> 128:9bcdf88f62b0 903 }
<> 128:9bcdf88f62b0 904
<> 128:9bcdf88f62b0 905 /**
<> 128:9bcdf88f62b0 906 * @brief Indicates whether the timer counter is enabled.
<> 128:9bcdf88f62b0 907 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<> 128:9bcdf88f62b0 908 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 909 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 910 */
<> 128:9bcdf88f62b0 911 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 912 {
<> 128:9bcdf88f62b0 913 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<> 128:9bcdf88f62b0 914 }
<> 128:9bcdf88f62b0 915
<> 128:9bcdf88f62b0 916 /**
<> 128:9bcdf88f62b0 917 * @brief Enable update event generation.
<> 128:9bcdf88f62b0 918 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<> 128:9bcdf88f62b0 919 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 920 * @retval None
<> 128:9bcdf88f62b0 921 */
<> 128:9bcdf88f62b0 922 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 923 {
<> 128:9bcdf88f62b0 924 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<> 128:9bcdf88f62b0 925 }
<> 128:9bcdf88f62b0 926
<> 128:9bcdf88f62b0 927 /**
<> 128:9bcdf88f62b0 928 * @brief Disable update event generation.
<> 128:9bcdf88f62b0 929 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<> 128:9bcdf88f62b0 930 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 931 * @retval None
<> 128:9bcdf88f62b0 932 */
<> 128:9bcdf88f62b0 933 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 934 {
<> 128:9bcdf88f62b0 935 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<> 128:9bcdf88f62b0 936 }
<> 128:9bcdf88f62b0 937
<> 128:9bcdf88f62b0 938 /**
<> 128:9bcdf88f62b0 939 * @brief Indicates whether update event generation is enabled.
<> 128:9bcdf88f62b0 940 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<> 128:9bcdf88f62b0 941 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 942 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 943 */
<> 128:9bcdf88f62b0 944 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 945 {
<> 128:9bcdf88f62b0 946 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<> 128:9bcdf88f62b0 947 }
<> 128:9bcdf88f62b0 948
<> 128:9bcdf88f62b0 949 /**
<> 128:9bcdf88f62b0 950 * @brief Set update event source
<> 128:9bcdf88f62b0 951 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<> 128:9bcdf88f62b0 952 * generate an update interrupt or DMA request if enabled:
<> 128:9bcdf88f62b0 953 * - Counter overflow/underflow
<> 128:9bcdf88f62b0 954 * - Setting the UG bit
<> 128:9bcdf88f62b0 955 * - Update generation through the slave mode controller
<> 128:9bcdf88f62b0 956 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<> 128:9bcdf88f62b0 957 * overflow/underflow generates an update interrupt or DMA request if enabled.
<> 128:9bcdf88f62b0 958 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
<> 128:9bcdf88f62b0 959 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 960 * @param UpdateSource This parameter can be one of the following values:
<> 128:9bcdf88f62b0 961 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<> 128:9bcdf88f62b0 962 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<> 128:9bcdf88f62b0 963 * @retval None
<> 128:9bcdf88f62b0 964 */
<> 128:9bcdf88f62b0 965 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<> 128:9bcdf88f62b0 966 {
<> 128:9bcdf88f62b0 967 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<> 128:9bcdf88f62b0 968 }
<> 128:9bcdf88f62b0 969
<> 128:9bcdf88f62b0 970 /**
<> 128:9bcdf88f62b0 971 * @brief Get actual event update source
<> 128:9bcdf88f62b0 972 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
<> 128:9bcdf88f62b0 973 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 974 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 975 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<> 128:9bcdf88f62b0 976 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<> 128:9bcdf88f62b0 977 */
<> 128:9bcdf88f62b0 978 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 979 {
<> 128:9bcdf88f62b0 980 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<> 128:9bcdf88f62b0 981 }
<> 128:9bcdf88f62b0 982
<> 128:9bcdf88f62b0 983 /**
<> 128:9bcdf88f62b0 984 * @brief Set one pulse mode (one shot v.s. repetitive).
<> 128:9bcdf88f62b0 985 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<> 128:9bcdf88f62b0 986 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 987 * @param OnePulseMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 988 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<> 128:9bcdf88f62b0 989 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<> 128:9bcdf88f62b0 990 * @retval None
<> 128:9bcdf88f62b0 991 */
<> 128:9bcdf88f62b0 992 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<> 128:9bcdf88f62b0 993 {
<> 128:9bcdf88f62b0 994 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<> 128:9bcdf88f62b0 995 }
<> 128:9bcdf88f62b0 996
<> 128:9bcdf88f62b0 997 /**
<> 128:9bcdf88f62b0 998 * @brief Get actual one pulse mode.
<> 128:9bcdf88f62b0 999 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<> 128:9bcdf88f62b0 1000 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1001 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1002 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<> 128:9bcdf88f62b0 1003 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<> 128:9bcdf88f62b0 1004 */
<> 128:9bcdf88f62b0 1005 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1006 {
<> 128:9bcdf88f62b0 1007 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<> 128:9bcdf88f62b0 1008 }
<> 128:9bcdf88f62b0 1009
<> 128:9bcdf88f62b0 1010 /**
<> 128:9bcdf88f62b0 1011 * @brief Set the timer counter counting mode.
<> 128:9bcdf88f62b0 1012 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<> 128:9bcdf88f62b0 1013 * check whether or not the counter mode selection feature is supported
<> 128:9bcdf88f62b0 1014 * by a timer instance.
<> 128:9bcdf88f62b0 1015 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<> 128:9bcdf88f62b0 1016 * CR1 CMS LL_TIM_SetCounterMode
<> 128:9bcdf88f62b0 1017 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1018 * @param CounterMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1019 * @arg @ref LL_TIM_COUNTERMODE_UP
<> 128:9bcdf88f62b0 1020 * @arg @ref LL_TIM_COUNTERMODE_DOWN
<> 128:9bcdf88f62b0 1021 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<> 128:9bcdf88f62b0 1022 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<> 128:9bcdf88f62b0 1023 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<> 128:9bcdf88f62b0 1024 * @retval None
<> 128:9bcdf88f62b0 1025 */
<> 128:9bcdf88f62b0 1026 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<> 128:9bcdf88f62b0 1027 {
<> 128:9bcdf88f62b0 1028 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
<> 128:9bcdf88f62b0 1029 }
<> 128:9bcdf88f62b0 1030
<> 128:9bcdf88f62b0 1031 /**
<> 128:9bcdf88f62b0 1032 * @brief Get actual counter mode.
<> 128:9bcdf88f62b0 1033 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<> 128:9bcdf88f62b0 1034 * check whether or not the counter mode selection feature is supported
<> 128:9bcdf88f62b0 1035 * by a timer instance.
<> 128:9bcdf88f62b0 1036 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<> 128:9bcdf88f62b0 1037 * CR1 CMS LL_TIM_GetCounterMode
<> 128:9bcdf88f62b0 1038 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1039 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1040 * @arg @ref LL_TIM_COUNTERMODE_UP
<> 128:9bcdf88f62b0 1041 * @arg @ref LL_TIM_COUNTERMODE_DOWN
<> 128:9bcdf88f62b0 1042 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<> 128:9bcdf88f62b0 1043 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<> 128:9bcdf88f62b0 1044 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<> 128:9bcdf88f62b0 1045 */
<> 128:9bcdf88f62b0 1046 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1047 {
<> 128:9bcdf88f62b0 1048 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
<> 128:9bcdf88f62b0 1049 }
<> 128:9bcdf88f62b0 1050
<> 128:9bcdf88f62b0 1051 /**
<> 128:9bcdf88f62b0 1052 * @brief Enable auto-reload (ARR) preload.
<> 128:9bcdf88f62b0 1053 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<> 128:9bcdf88f62b0 1054 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1055 * @retval None
<> 128:9bcdf88f62b0 1056 */
<> 128:9bcdf88f62b0 1057 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1058 {
<> 128:9bcdf88f62b0 1059 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<> 128:9bcdf88f62b0 1060 }
<> 128:9bcdf88f62b0 1061
<> 128:9bcdf88f62b0 1062 /**
<> 128:9bcdf88f62b0 1063 * @brief Disable auto-reload (ARR) preload.
<> 128:9bcdf88f62b0 1064 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<> 128:9bcdf88f62b0 1065 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1066 * @retval None
<> 128:9bcdf88f62b0 1067 */
<> 128:9bcdf88f62b0 1068 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1069 {
<> 128:9bcdf88f62b0 1070 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<> 128:9bcdf88f62b0 1071 }
<> 128:9bcdf88f62b0 1072
<> 128:9bcdf88f62b0 1073 /**
<> 128:9bcdf88f62b0 1074 * @brief Indicates whether auto-reload (ARR) preload is enabled.
<> 128:9bcdf88f62b0 1075 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<> 128:9bcdf88f62b0 1076 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1077 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1078 */
<> 128:9bcdf88f62b0 1079 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1080 {
<> 128:9bcdf88f62b0 1081 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<> 128:9bcdf88f62b0 1082 }
<> 128:9bcdf88f62b0 1083
<> 128:9bcdf88f62b0 1084 /**
<> 128:9bcdf88f62b0 1085 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<> 128:9bcdf88f62b0 1086 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1087 * whether or not the clock division feature is supported by the timer
<> 128:9bcdf88f62b0 1088 * instance.
<> 128:9bcdf88f62b0 1089 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
<> 128:9bcdf88f62b0 1090 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1091 * @param ClockDivision This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1092 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<> 128:9bcdf88f62b0 1093 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<> 128:9bcdf88f62b0 1094 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<> 128:9bcdf88f62b0 1095 * @retval None
<> 128:9bcdf88f62b0 1096 */
<> 128:9bcdf88f62b0 1097 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<> 128:9bcdf88f62b0 1098 {
<> 128:9bcdf88f62b0 1099 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<> 128:9bcdf88f62b0 1100 }
<> 128:9bcdf88f62b0 1101
<> 128:9bcdf88f62b0 1102 /**
<> 128:9bcdf88f62b0 1103 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<> 128:9bcdf88f62b0 1104 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1105 * whether or not the clock division feature is supported by the timer
<> 128:9bcdf88f62b0 1106 * instance.
<> 128:9bcdf88f62b0 1107 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
<> 128:9bcdf88f62b0 1108 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1109 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1110 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<> 128:9bcdf88f62b0 1111 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<> 128:9bcdf88f62b0 1112 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<> 128:9bcdf88f62b0 1113 */
<> 128:9bcdf88f62b0 1114 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1115 {
<> 128:9bcdf88f62b0 1116 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<> 128:9bcdf88f62b0 1117 }
<> 128:9bcdf88f62b0 1118
<> 128:9bcdf88f62b0 1119 /**
<> 128:9bcdf88f62b0 1120 * @brief Set the counter value.
<> 128:9bcdf88f62b0 1121 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1122 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1123 * @rmtoll CNT CNT LL_TIM_SetCounter
<> 128:9bcdf88f62b0 1124 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1125 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<> 128:9bcdf88f62b0 1126 * @retval None
<> 128:9bcdf88f62b0 1127 */
<> 128:9bcdf88f62b0 1128 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<> 128:9bcdf88f62b0 1129 {
<> 128:9bcdf88f62b0 1130 WRITE_REG(TIMx->CNT, Counter);
<> 128:9bcdf88f62b0 1131 }
<> 128:9bcdf88f62b0 1132
<> 128:9bcdf88f62b0 1133 /**
<> 128:9bcdf88f62b0 1134 * @brief Get the counter value.
<> 128:9bcdf88f62b0 1135 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1136 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1137 * @rmtoll CNT CNT LL_TIM_GetCounter
<> 128:9bcdf88f62b0 1138 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1139 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<> 128:9bcdf88f62b0 1140 */
<> 128:9bcdf88f62b0 1141 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1142 {
<> 128:9bcdf88f62b0 1143 return (uint32_t)(READ_REG(TIMx->CNT));
<> 128:9bcdf88f62b0 1144 }
<> 128:9bcdf88f62b0 1145
<> 128:9bcdf88f62b0 1146 /**
<> 128:9bcdf88f62b0 1147 * @brief Get the current direction of the counter
<> 128:9bcdf88f62b0 1148 * @rmtoll CR1 DIR LL_TIM_GetDirection
<> 128:9bcdf88f62b0 1149 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1150 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1151 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
<> 128:9bcdf88f62b0 1152 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<> 128:9bcdf88f62b0 1153 */
<> 128:9bcdf88f62b0 1154 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1155 {
<> 128:9bcdf88f62b0 1156 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<> 128:9bcdf88f62b0 1157 }
<> 128:9bcdf88f62b0 1158
<> 128:9bcdf88f62b0 1159 /**
<> 128:9bcdf88f62b0 1160 * @brief Set the prescaler value.
<> 128:9bcdf88f62b0 1161 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<> 128:9bcdf88f62b0 1162 * @note The prescaler can be changed on the fly as this control register is buffered. The new
<> 128:9bcdf88f62b0 1163 * prescaler ratio is taken into account at the next update event.
<> 128:9bcdf88f62b0 1164 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<> 128:9bcdf88f62b0 1165 * @rmtoll PSC PSC LL_TIM_SetPrescaler
<> 128:9bcdf88f62b0 1166 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1167 * @param Prescaler between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1168 * @retval None
<> 128:9bcdf88f62b0 1169 */
<> 128:9bcdf88f62b0 1170 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<> 128:9bcdf88f62b0 1171 {
<> 128:9bcdf88f62b0 1172 WRITE_REG(TIMx->PSC, Prescaler);
<> 128:9bcdf88f62b0 1173 }
<> 128:9bcdf88f62b0 1174
<> 128:9bcdf88f62b0 1175 /**
<> 128:9bcdf88f62b0 1176 * @brief Get the prescaler value.
<> 128:9bcdf88f62b0 1177 * @rmtoll PSC PSC LL_TIM_GetPrescaler
<> 128:9bcdf88f62b0 1178 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1179 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1180 */
<> 128:9bcdf88f62b0 1181 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1182 {
<> 128:9bcdf88f62b0 1183 return (uint32_t)(READ_REG(TIMx->PSC));
<> 128:9bcdf88f62b0 1184 }
<> 128:9bcdf88f62b0 1185
<> 128:9bcdf88f62b0 1186 /**
<> 128:9bcdf88f62b0 1187 * @brief Set the auto-reload value.
<> 128:9bcdf88f62b0 1188 * @note The counter is blocked while the auto-reload value is null.
<> 128:9bcdf88f62b0 1189 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1190 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1191 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<> 128:9bcdf88f62b0 1192 * @rmtoll ARR ARR LL_TIM_SetAutoReload
<> 128:9bcdf88f62b0 1193 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1194 * @param AutoReload between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1195 * @retval None
<> 128:9bcdf88f62b0 1196 */
<> 128:9bcdf88f62b0 1197 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<> 128:9bcdf88f62b0 1198 {
<> 128:9bcdf88f62b0 1199 WRITE_REG(TIMx->ARR, AutoReload);
<> 128:9bcdf88f62b0 1200 }
<> 128:9bcdf88f62b0 1201
<> 128:9bcdf88f62b0 1202 /**
<> 128:9bcdf88f62b0 1203 * @brief Get the auto-reload value.
<> 128:9bcdf88f62b0 1204 * @rmtoll ARR ARR LL_TIM_GetAutoReload
<> 128:9bcdf88f62b0 1205 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1206 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1207 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1208 * @retval Auto-reload value
<> 128:9bcdf88f62b0 1209 */
<> 128:9bcdf88f62b0 1210 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1211 {
<> 128:9bcdf88f62b0 1212 return (uint32_t)(READ_REG(TIMx->ARR));
<> 128:9bcdf88f62b0 1213 }
<> 128:9bcdf88f62b0 1214
<> 128:9bcdf88f62b0 1215 /**
<> 128:9bcdf88f62b0 1216 * @}
<> 128:9bcdf88f62b0 1217 */
<> 128:9bcdf88f62b0 1218
<> 128:9bcdf88f62b0 1219 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<> 128:9bcdf88f62b0 1220 * @{
<> 128:9bcdf88f62b0 1221 */
<> 128:9bcdf88f62b0 1222 /**
<> 128:9bcdf88f62b0 1223 * @brief Set the trigger of the capture/compare DMA request.
<> 128:9bcdf88f62b0 1224 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<> 128:9bcdf88f62b0 1225 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1226 * @param DMAReqTrigger This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1227 * @arg @ref LL_TIM_CCDMAREQUEST_CC
<> 128:9bcdf88f62b0 1228 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<> 128:9bcdf88f62b0 1229 * @retval None
<> 128:9bcdf88f62b0 1230 */
<> 128:9bcdf88f62b0 1231 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<> 128:9bcdf88f62b0 1232 {
<> 128:9bcdf88f62b0 1233 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<> 128:9bcdf88f62b0 1234 }
<> 128:9bcdf88f62b0 1235
<> 128:9bcdf88f62b0 1236 /**
<> 128:9bcdf88f62b0 1237 * @brief Get actual trigger of the capture/compare DMA request.
<> 128:9bcdf88f62b0 1238 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<> 128:9bcdf88f62b0 1239 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1240 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1241 * @arg @ref LL_TIM_CCDMAREQUEST_CC
<> 128:9bcdf88f62b0 1242 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<> 128:9bcdf88f62b0 1243 */
<> 128:9bcdf88f62b0 1244 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1245 {
<> 128:9bcdf88f62b0 1246 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<> 128:9bcdf88f62b0 1247 }
<> 128:9bcdf88f62b0 1248
<> 128:9bcdf88f62b0 1249 /**
<> 128:9bcdf88f62b0 1250 * @brief Enable capture/compare channels.
<> 128:9bcdf88f62b0 1251 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<> 128:9bcdf88f62b0 1252 * CCER CC2E LL_TIM_CC_EnableChannel\n
<> 128:9bcdf88f62b0 1253 * CCER CC3E LL_TIM_CC_EnableChannel\n
<> 128:9bcdf88f62b0 1254 * CCER CC4E LL_TIM_CC_EnableChannel
<> 128:9bcdf88f62b0 1255 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1256 * @param Channels This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1257 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1258 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1259 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1260 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1261 * @retval None
<> 128:9bcdf88f62b0 1262 */
<> 128:9bcdf88f62b0 1263 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<> 128:9bcdf88f62b0 1264 {
<> 128:9bcdf88f62b0 1265 SET_BIT(TIMx->CCER, Channels);
<> 128:9bcdf88f62b0 1266 }
<> 128:9bcdf88f62b0 1267
<> 128:9bcdf88f62b0 1268 /**
<> 128:9bcdf88f62b0 1269 * @brief Disable capture/compare channels.
<> 128:9bcdf88f62b0 1270 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<> 128:9bcdf88f62b0 1271 * CCER CC2E LL_TIM_CC_DisableChannel\n
<> 128:9bcdf88f62b0 1272 * CCER CC3E LL_TIM_CC_DisableChannel\n
<> 128:9bcdf88f62b0 1273 * CCER CC4E LL_TIM_CC_DisableChannel
<> 128:9bcdf88f62b0 1274 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1275 * @param Channels This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1276 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1277 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1278 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1279 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1280 * @retval None
<> 128:9bcdf88f62b0 1281 */
<> 128:9bcdf88f62b0 1282 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<> 128:9bcdf88f62b0 1283 {
<> 128:9bcdf88f62b0 1284 CLEAR_BIT(TIMx->CCER, Channels);
<> 128:9bcdf88f62b0 1285 }
<> 128:9bcdf88f62b0 1286
<> 128:9bcdf88f62b0 1287 /**
<> 128:9bcdf88f62b0 1288 * @brief Indicate whether channel(s) is(are) enabled.
<> 128:9bcdf88f62b0 1289 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<> 128:9bcdf88f62b0 1290 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<> 128:9bcdf88f62b0 1291 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<> 128:9bcdf88f62b0 1292 * CCER CC4E LL_TIM_CC_IsEnabledChannel
<> 128:9bcdf88f62b0 1293 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1294 * @param Channels This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1295 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1296 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1297 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1298 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1299 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1300 */
<> 128:9bcdf88f62b0 1301 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<> 128:9bcdf88f62b0 1302 {
<> 128:9bcdf88f62b0 1303 return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<> 128:9bcdf88f62b0 1304 }
<> 128:9bcdf88f62b0 1305
<> 128:9bcdf88f62b0 1306 /**
<> 128:9bcdf88f62b0 1307 * @}
<> 128:9bcdf88f62b0 1308 */
<> 128:9bcdf88f62b0 1309
<> 128:9bcdf88f62b0 1310 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<> 128:9bcdf88f62b0 1311 * @{
<> 128:9bcdf88f62b0 1312 */
<> 128:9bcdf88f62b0 1313 /**
<> 128:9bcdf88f62b0 1314 * @brief Configure an output channel.
<> 128:9bcdf88f62b0 1315 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1316 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1317 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1318 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1319 * CCER CC1P LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1320 * CCER CC2P LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1321 * CCER CC3P LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1322 * CCER CC4P LL_TIM_OC_ConfigOutput\n
<> 128:9bcdf88f62b0 1323 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1324 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1325 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1326 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1327 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1328 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1329 * @param Configuration This parameter must be a combination of all the following values:
<> 128:9bcdf88f62b0 1330 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<> 128:9bcdf88f62b0 1331 * @retval None
<> 128:9bcdf88f62b0 1332 */
<> 128:9bcdf88f62b0 1333 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<> 128:9bcdf88f62b0 1334 {
<> 128:9bcdf88f62b0 1335 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1336 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1337 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1338 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<> 128:9bcdf88f62b0 1339 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 1340 }
<> 128:9bcdf88f62b0 1341
<> 128:9bcdf88f62b0 1342 /**
<> 128:9bcdf88f62b0 1343 * @brief Define the behavior of the output reference signal OCxREF from which
<> 128:9bcdf88f62b0 1344 * OCx and OCxN (when relevant) are derived.
<> 128:9bcdf88f62b0 1345 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<> 128:9bcdf88f62b0 1346 * CCMR1 OC2M LL_TIM_OC_SetMode\n
<> 128:9bcdf88f62b0 1347 * CCMR2 OC3M LL_TIM_OC_SetMode\n
<> 128:9bcdf88f62b0 1348 * CCMR2 OC4M LL_TIM_OC_SetMode
<> 128:9bcdf88f62b0 1349 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1350 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1351 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1352 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1353 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1354 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1355 * @param Mode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1356 * @arg @ref LL_TIM_OCMODE_FROZEN
<> 128:9bcdf88f62b0 1357 * @arg @ref LL_TIM_OCMODE_ACTIVE
<> 128:9bcdf88f62b0 1358 * @arg @ref LL_TIM_OCMODE_INACTIVE
<> 128:9bcdf88f62b0 1359 * @arg @ref LL_TIM_OCMODE_TOGGLE
<> 128:9bcdf88f62b0 1360 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<> 128:9bcdf88f62b0 1361 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<> 128:9bcdf88f62b0 1362 * @arg @ref LL_TIM_OCMODE_PWM1
<> 128:9bcdf88f62b0 1363 * @arg @ref LL_TIM_OCMODE_PWM2
<> 128:9bcdf88f62b0 1364 * @retval None
<> 128:9bcdf88f62b0 1365 */
<> 128:9bcdf88f62b0 1366 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<> 128:9bcdf88f62b0 1367 {
<> 128:9bcdf88f62b0 1368 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1369 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1370 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<> 128:9bcdf88f62b0 1371 }
<> 128:9bcdf88f62b0 1372
<> 128:9bcdf88f62b0 1373 /**
<> 128:9bcdf88f62b0 1374 * @brief Get the output compare mode of an output channel.
<> 128:9bcdf88f62b0 1375 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<> 128:9bcdf88f62b0 1376 * CCMR1 OC2M LL_TIM_OC_GetMode\n
<> 128:9bcdf88f62b0 1377 * CCMR2 OC3M LL_TIM_OC_GetMode\n
<> 128:9bcdf88f62b0 1378 * CCMR2 OC4M LL_TIM_OC_GetMode
<> 128:9bcdf88f62b0 1379 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1380 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1381 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1382 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1383 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1384 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1385 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1386 * @arg @ref LL_TIM_OCMODE_FROZEN
<> 128:9bcdf88f62b0 1387 * @arg @ref LL_TIM_OCMODE_ACTIVE
<> 128:9bcdf88f62b0 1388 * @arg @ref LL_TIM_OCMODE_INACTIVE
<> 128:9bcdf88f62b0 1389 * @arg @ref LL_TIM_OCMODE_TOGGLE
<> 128:9bcdf88f62b0 1390 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<> 128:9bcdf88f62b0 1391 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<> 128:9bcdf88f62b0 1392 * @arg @ref LL_TIM_OCMODE_PWM1
<> 128:9bcdf88f62b0 1393 * @arg @ref LL_TIM_OCMODE_PWM2
<> 128:9bcdf88f62b0 1394 */
<> 128:9bcdf88f62b0 1395 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1396 {
<> 128:9bcdf88f62b0 1397 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1398 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1399 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<> 128:9bcdf88f62b0 1400 }
<> 128:9bcdf88f62b0 1401
<> 128:9bcdf88f62b0 1402 /**
<> 128:9bcdf88f62b0 1403 * @brief Set the polarity of an output channel.
<> 128:9bcdf88f62b0 1404 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<> 128:9bcdf88f62b0 1405 * CCER CC2P LL_TIM_OC_SetPolarity\n
<> 128:9bcdf88f62b0 1406 * CCER CC3P LL_TIM_OC_SetPolarity\n
<> 128:9bcdf88f62b0 1407 * CCER CC4P LL_TIM_OC_SetPolarity
<> 128:9bcdf88f62b0 1408 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1409 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1410 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1411 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1412 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1413 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1414 * @param Polarity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1415 * @arg @ref LL_TIM_OCPOLARITY_HIGH
<> 128:9bcdf88f62b0 1416 * @arg @ref LL_TIM_OCPOLARITY_LOW
<> 128:9bcdf88f62b0 1417 * @retval None
<> 128:9bcdf88f62b0 1418 */
<> 128:9bcdf88f62b0 1419 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<> 128:9bcdf88f62b0 1420 {
<> 128:9bcdf88f62b0 1421 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1422 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 1423 }
<> 128:9bcdf88f62b0 1424
<> 128:9bcdf88f62b0 1425 /**
<> 128:9bcdf88f62b0 1426 * @brief Get the polarity of an output channel.
<> 128:9bcdf88f62b0 1427 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<> 128:9bcdf88f62b0 1428 * CCER CC2P LL_TIM_OC_GetPolarity\n
<> 128:9bcdf88f62b0 1429 * CCER CC3P LL_TIM_OC_GetPolarity\n
<> 128:9bcdf88f62b0 1430 * CCER CC4P LL_TIM_OC_GetPolarity
<> 128:9bcdf88f62b0 1431 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1432 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1433 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1434 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1435 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1436 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1437 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1438 * @arg @ref LL_TIM_OCPOLARITY_HIGH
<> 128:9bcdf88f62b0 1439 * @arg @ref LL_TIM_OCPOLARITY_LOW
<> 128:9bcdf88f62b0 1440 */
<> 128:9bcdf88f62b0 1441 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1442 {
<> 128:9bcdf88f62b0 1443 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1444 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 1445 }
<> 128:9bcdf88f62b0 1446
<> 128:9bcdf88f62b0 1447 /**
<> 128:9bcdf88f62b0 1448 * @brief Enable fast mode for the output channel.
<> 128:9bcdf88f62b0 1449 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<> 128:9bcdf88f62b0 1450 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<> 128:9bcdf88f62b0 1451 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<> 128:9bcdf88f62b0 1452 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<> 128:9bcdf88f62b0 1453 * CCMR2 OC4FE LL_TIM_OC_EnableFast
<> 128:9bcdf88f62b0 1454 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1455 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1456 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1457 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1458 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1459 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1460 * @retval None
<> 128:9bcdf88f62b0 1461 */
<> 128:9bcdf88f62b0 1462 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1463 {
<> 128:9bcdf88f62b0 1464 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1465 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1466 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1467
<> 128:9bcdf88f62b0 1468 }
<> 128:9bcdf88f62b0 1469
<> 128:9bcdf88f62b0 1470 /**
<> 128:9bcdf88f62b0 1471 * @brief Disable fast mode for the output channel.
<> 128:9bcdf88f62b0 1472 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<> 128:9bcdf88f62b0 1473 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<> 128:9bcdf88f62b0 1474 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<> 128:9bcdf88f62b0 1475 * CCMR2 OC4FE LL_TIM_OC_DisableFast
<> 128:9bcdf88f62b0 1476 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1477 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1478 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1479 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1480 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1481 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1482 * @retval None
<> 128:9bcdf88f62b0 1483 */
<> 128:9bcdf88f62b0 1484 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1485 {
<> 128:9bcdf88f62b0 1486 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1487 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1488 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1489
<> 128:9bcdf88f62b0 1490 }
<> 128:9bcdf88f62b0 1491
<> 128:9bcdf88f62b0 1492 /**
<> 128:9bcdf88f62b0 1493 * @brief Indicates whether fast mode is enabled for the output channel.
<> 128:9bcdf88f62b0 1494 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<> 128:9bcdf88f62b0 1495 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<> 128:9bcdf88f62b0 1496 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<> 128:9bcdf88f62b0 1497 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<> 128:9bcdf88f62b0 1498 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1499 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1500 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1501 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1502 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1503 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1504 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1505 */
<> 128:9bcdf88f62b0 1506 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1507 {
<> 128:9bcdf88f62b0 1508 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1509 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1510 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<> 128:9bcdf88f62b0 1511 return (READ_BIT(*pReg, bitfield) == bitfield);
<> 128:9bcdf88f62b0 1512 }
<> 128:9bcdf88f62b0 1513
<> 128:9bcdf88f62b0 1514 /**
<> 128:9bcdf88f62b0 1515 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<> 128:9bcdf88f62b0 1516 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<> 128:9bcdf88f62b0 1517 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<> 128:9bcdf88f62b0 1518 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<> 128:9bcdf88f62b0 1519 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
<> 128:9bcdf88f62b0 1520 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1521 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1522 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1523 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1524 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1525 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1526 * @retval None
<> 128:9bcdf88f62b0 1527 */
<> 128:9bcdf88f62b0 1528 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1529 {
<> 128:9bcdf88f62b0 1530 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1531 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1532 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1533 }
<> 128:9bcdf88f62b0 1534
<> 128:9bcdf88f62b0 1535 /**
<> 128:9bcdf88f62b0 1536 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<> 128:9bcdf88f62b0 1537 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<> 128:9bcdf88f62b0 1538 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<> 128:9bcdf88f62b0 1539 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<> 128:9bcdf88f62b0 1540 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
<> 128:9bcdf88f62b0 1541 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1542 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1543 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1544 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1545 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1546 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1547 * @retval None
<> 128:9bcdf88f62b0 1548 */
<> 128:9bcdf88f62b0 1549 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1550 {
<> 128:9bcdf88f62b0 1551 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1552 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1553 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1554 }
<> 128:9bcdf88f62b0 1555
<> 128:9bcdf88f62b0 1556 /**
<> 128:9bcdf88f62b0 1557 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<> 128:9bcdf88f62b0 1558 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<> 128:9bcdf88f62b0 1559 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<> 128:9bcdf88f62b0 1560 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<> 128:9bcdf88f62b0 1561 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<> 128:9bcdf88f62b0 1562 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1563 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1564 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1565 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1566 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1567 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1568 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1569 */
<> 128:9bcdf88f62b0 1570 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1571 {
<> 128:9bcdf88f62b0 1572 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1573 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1574 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<> 128:9bcdf88f62b0 1575 return (READ_BIT(*pReg, bitfield) == bitfield);
<> 128:9bcdf88f62b0 1576 }
<> 128:9bcdf88f62b0 1577
<> 128:9bcdf88f62b0 1578 /**
<> 128:9bcdf88f62b0 1579 * @brief Enable clearing the output channel on an external event.
<> 128:9bcdf88f62b0 1580 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<> 128:9bcdf88f62b0 1581 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<> 128:9bcdf88f62b0 1582 * or not a timer instance can clear the OCxREF signal on an external event.
<> 128:9bcdf88f62b0 1583 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<> 128:9bcdf88f62b0 1584 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<> 128:9bcdf88f62b0 1585 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<> 128:9bcdf88f62b0 1586 * CCMR2 OC4CE LL_TIM_OC_EnableClear
<> 128:9bcdf88f62b0 1587 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1588 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1589 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1590 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1591 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1592 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1593 * @retval None
<> 128:9bcdf88f62b0 1594 */
<> 128:9bcdf88f62b0 1595 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1596 {
<> 128:9bcdf88f62b0 1597 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1598 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1599 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1600 }
<> 128:9bcdf88f62b0 1601
<> 128:9bcdf88f62b0 1602 /**
<> 128:9bcdf88f62b0 1603 * @brief Disable clearing the output channel on an external event.
<> 128:9bcdf88f62b0 1604 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<> 128:9bcdf88f62b0 1605 * or not a timer instance can clear the OCxREF signal on an external event.
<> 128:9bcdf88f62b0 1606 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<> 128:9bcdf88f62b0 1607 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<> 128:9bcdf88f62b0 1608 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<> 128:9bcdf88f62b0 1609 * CCMR2 OC4CE LL_TIM_OC_DisableClear
<> 128:9bcdf88f62b0 1610 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1611 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1612 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1613 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1614 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1615 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1616 * @retval None
<> 128:9bcdf88f62b0 1617 */
<> 128:9bcdf88f62b0 1618 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1619 {
<> 128:9bcdf88f62b0 1620 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1621 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1622 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<> 128:9bcdf88f62b0 1623 }
<> 128:9bcdf88f62b0 1624
<> 128:9bcdf88f62b0 1625 /**
<> 128:9bcdf88f62b0 1626 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<> 128:9bcdf88f62b0 1627 * @note This function enables clearing the output channel on an external event.
<> 128:9bcdf88f62b0 1628 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<> 128:9bcdf88f62b0 1629 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<> 128:9bcdf88f62b0 1630 * or not a timer instance can clear the OCxREF signal on an external event.
<> 128:9bcdf88f62b0 1631 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<> 128:9bcdf88f62b0 1632 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<> 128:9bcdf88f62b0 1633 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<> 128:9bcdf88f62b0 1634 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<> 128:9bcdf88f62b0 1635 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1636 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1637 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1638 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1639 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1640 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1641 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1642 */
<> 128:9bcdf88f62b0 1643 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1644 {
<> 128:9bcdf88f62b0 1645 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1646 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1647 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<> 128:9bcdf88f62b0 1648 return (READ_BIT(*pReg, bitfield) == bitfield);
<> 128:9bcdf88f62b0 1649 }
<> 128:9bcdf88f62b0 1650
<> 128:9bcdf88f62b0 1651 /**
<> 128:9bcdf88f62b0 1652 * @brief Set compare value for output channel 1 (TIMx_CCR1).
<> 128:9bcdf88f62b0 1653 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1654 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1655 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1656 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1657 * output channel 1 is supported by a timer instance.
<> 128:9bcdf88f62b0 1658 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<> 128:9bcdf88f62b0 1659 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1660 * @param CompareValue between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1661 * @retval None
<> 128:9bcdf88f62b0 1662 */
<> 128:9bcdf88f62b0 1663 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<> 128:9bcdf88f62b0 1664 {
<> 128:9bcdf88f62b0 1665 WRITE_REG(TIMx->CCR1, CompareValue);
<> 128:9bcdf88f62b0 1666 }
<> 128:9bcdf88f62b0 1667
<> 128:9bcdf88f62b0 1668 /**
<> 128:9bcdf88f62b0 1669 * @brief Set compare value for output channel 2 (TIMx_CCR2).
<> 128:9bcdf88f62b0 1670 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1671 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1672 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1673 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1674 * output channel 2 is supported by a timer instance.
<> 128:9bcdf88f62b0 1675 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<> 128:9bcdf88f62b0 1676 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1677 * @param CompareValue between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1678 * @retval None
<> 128:9bcdf88f62b0 1679 */
<> 128:9bcdf88f62b0 1680 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<> 128:9bcdf88f62b0 1681 {
<> 128:9bcdf88f62b0 1682 WRITE_REG(TIMx->CCR2, CompareValue);
<> 128:9bcdf88f62b0 1683 }
<> 128:9bcdf88f62b0 1684
<> 128:9bcdf88f62b0 1685 /**
<> 128:9bcdf88f62b0 1686 * @brief Set compare value for output channel 3 (TIMx_CCR3).
<> 128:9bcdf88f62b0 1687 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1688 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1689 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1690 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1691 * output channel is supported by a timer instance.
<> 128:9bcdf88f62b0 1692 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<> 128:9bcdf88f62b0 1693 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1694 * @param CompareValue between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1695 * @retval None
<> 128:9bcdf88f62b0 1696 */
<> 128:9bcdf88f62b0 1697 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<> 128:9bcdf88f62b0 1698 {
<> 128:9bcdf88f62b0 1699 WRITE_REG(TIMx->CCR3, CompareValue);
<> 128:9bcdf88f62b0 1700 }
<> 128:9bcdf88f62b0 1701
<> 128:9bcdf88f62b0 1702 /**
<> 128:9bcdf88f62b0 1703 * @brief Set compare value for output channel 4 (TIMx_CCR4).
<> 128:9bcdf88f62b0 1704 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1705 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1706 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1707 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1708 * output channel 4 is supported by a timer instance.
<> 128:9bcdf88f62b0 1709 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<> 128:9bcdf88f62b0 1710 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1711 * @param CompareValue between Min_Data=0 and Max_Data=65535
<> 128:9bcdf88f62b0 1712 * @retval None
<> 128:9bcdf88f62b0 1713 */
<> 128:9bcdf88f62b0 1714 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<> 128:9bcdf88f62b0 1715 {
<> 128:9bcdf88f62b0 1716 WRITE_REG(TIMx->CCR4, CompareValue);
<> 128:9bcdf88f62b0 1717 }
<> 128:9bcdf88f62b0 1718
<> 128:9bcdf88f62b0 1719 /**
<> 128:9bcdf88f62b0 1720 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
<> 128:9bcdf88f62b0 1721 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1722 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1723 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1724 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1725 * output channel 1 is supported by a timer instance.
<> 128:9bcdf88f62b0 1726 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<> 128:9bcdf88f62b0 1727 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1728 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 1729 */
<> 128:9bcdf88f62b0 1730 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1731 {
<> 128:9bcdf88f62b0 1732 return (uint32_t)(READ_REG(TIMx->CCR1));
<> 128:9bcdf88f62b0 1733 }
<> 128:9bcdf88f62b0 1734
<> 128:9bcdf88f62b0 1735 /**
<> 128:9bcdf88f62b0 1736 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
<> 128:9bcdf88f62b0 1737 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1738 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1739 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1740 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1741 * output channel 2 is supported by a timer instance.
<> 128:9bcdf88f62b0 1742 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<> 128:9bcdf88f62b0 1743 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1744 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 1745 */
<> 128:9bcdf88f62b0 1746 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1747 {
<> 128:9bcdf88f62b0 1748 return (uint32_t)(READ_REG(TIMx->CCR2));
<> 128:9bcdf88f62b0 1749 }
<> 128:9bcdf88f62b0 1750
<> 128:9bcdf88f62b0 1751 /**
<> 128:9bcdf88f62b0 1752 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
<> 128:9bcdf88f62b0 1753 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1754 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1755 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1756 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1757 * output channel 3 is supported by a timer instance.
<> 128:9bcdf88f62b0 1758 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<> 128:9bcdf88f62b0 1759 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1760 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 1761 */
<> 128:9bcdf88f62b0 1762 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1763 {
<> 128:9bcdf88f62b0 1764 return (uint32_t)(READ_REG(TIMx->CCR3));
<> 128:9bcdf88f62b0 1765 }
<> 128:9bcdf88f62b0 1766
<> 128:9bcdf88f62b0 1767 /**
<> 128:9bcdf88f62b0 1768 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
<> 128:9bcdf88f62b0 1769 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 1770 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 1771 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 1772 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 1773 * output channel 4 is supported by a timer instance.
<> 128:9bcdf88f62b0 1774 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<> 128:9bcdf88f62b0 1775 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1776 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 1777 */
<> 128:9bcdf88f62b0 1778 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 1779 {
<> 128:9bcdf88f62b0 1780 return (uint32_t)(READ_REG(TIMx->CCR4));
<> 128:9bcdf88f62b0 1781 }
<> 128:9bcdf88f62b0 1782
<> 128:9bcdf88f62b0 1783 /**
<> 128:9bcdf88f62b0 1784 * @}
<> 128:9bcdf88f62b0 1785 */
<> 128:9bcdf88f62b0 1786
<> 128:9bcdf88f62b0 1787 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<> 128:9bcdf88f62b0 1788 * @{
<> 128:9bcdf88f62b0 1789 */
<> 128:9bcdf88f62b0 1790 /**
<> 128:9bcdf88f62b0 1791 * @brief Configure input channel.
<> 128:9bcdf88f62b0 1792 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1793 * CCMR1 IC1PSC LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1794 * CCMR1 IC1F LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1795 * CCMR1 CC2S LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1796 * CCMR1 IC2PSC LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1797 * CCMR1 IC2F LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1798 * CCMR2 CC3S LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1799 * CCMR2 IC3PSC LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1800 * CCMR2 IC3F LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1801 * CCMR2 CC4S LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1802 * CCMR2 IC4PSC LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1803 * CCMR2 IC4F LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1804 * CCER CC1P LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1805 * CCER CC1NP LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1806 * CCER CC2P LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1807 * CCER CC2NP LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1808 * CCER CC3P LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1809 * CCER CC3NP LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1810 * CCER CC4P LL_TIM_IC_Config\n
<> 128:9bcdf88f62b0 1811 * CCER CC4NP LL_TIM_IC_Config
<> 128:9bcdf88f62b0 1812 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1813 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1814 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1815 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1816 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1817 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1818 * @param Configuration This parameter must be a combination of all the following values:
<> 128:9bcdf88f62b0 1819 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<> 128:9bcdf88f62b0 1820 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<> 128:9bcdf88f62b0 1821 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<> 128:9bcdf88f62b0 1822 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<> 128:9bcdf88f62b0 1823 * @retval None
<> 128:9bcdf88f62b0 1824 */
<> 128:9bcdf88f62b0 1825 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<> 128:9bcdf88f62b0 1826 {
<> 128:9bcdf88f62b0 1827 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1828 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1829 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<> 128:9bcdf88f62b0 1830 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<> 128:9bcdf88f62b0 1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<> 128:9bcdf88f62b0 1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 1833 }
<> 128:9bcdf88f62b0 1834
<> 128:9bcdf88f62b0 1835 /**
<> 128:9bcdf88f62b0 1836 * @brief Set the active input.
<> 128:9bcdf88f62b0 1837 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<> 128:9bcdf88f62b0 1838 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<> 128:9bcdf88f62b0 1839 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<> 128:9bcdf88f62b0 1840 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
<> 128:9bcdf88f62b0 1841 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1842 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1843 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1844 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1845 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1846 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1847 * @param ICActiveInput This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1848 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<> 128:9bcdf88f62b0 1849 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<> 128:9bcdf88f62b0 1850 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
<> 128:9bcdf88f62b0 1851 * @retval None
<> 128:9bcdf88f62b0 1852 */
<> 128:9bcdf88f62b0 1853 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<> 128:9bcdf88f62b0 1854 {
<> 128:9bcdf88f62b0 1855 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1856 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1857 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<> 128:9bcdf88f62b0 1858 }
<> 128:9bcdf88f62b0 1859
<> 128:9bcdf88f62b0 1860 /**
<> 128:9bcdf88f62b0 1861 * @brief Get the current active input.
<> 128:9bcdf88f62b0 1862 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<> 128:9bcdf88f62b0 1863 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<> 128:9bcdf88f62b0 1864 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<> 128:9bcdf88f62b0 1865 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
<> 128:9bcdf88f62b0 1866 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1867 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1868 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1869 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1870 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1871 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1872 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1873 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<> 128:9bcdf88f62b0 1874 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<> 128:9bcdf88f62b0 1875 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
<> 128:9bcdf88f62b0 1876 */
<> 128:9bcdf88f62b0 1877 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1878 {
<> 128:9bcdf88f62b0 1879 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1880 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1881 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<> 128:9bcdf88f62b0 1882 }
<> 128:9bcdf88f62b0 1883
<> 128:9bcdf88f62b0 1884 /**
<> 128:9bcdf88f62b0 1885 * @brief Set the prescaler of input channel.
<> 128:9bcdf88f62b0 1886 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<> 128:9bcdf88f62b0 1887 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<> 128:9bcdf88f62b0 1888 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<> 128:9bcdf88f62b0 1889 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<> 128:9bcdf88f62b0 1890 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1891 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1892 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1893 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1894 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1895 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1896 * @param ICPrescaler This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1897 * @arg @ref LL_TIM_ICPSC_DIV1
<> 128:9bcdf88f62b0 1898 * @arg @ref LL_TIM_ICPSC_DIV2
<> 128:9bcdf88f62b0 1899 * @arg @ref LL_TIM_ICPSC_DIV4
<> 128:9bcdf88f62b0 1900 * @arg @ref LL_TIM_ICPSC_DIV8
<> 128:9bcdf88f62b0 1901 * @retval None
<> 128:9bcdf88f62b0 1902 */
<> 128:9bcdf88f62b0 1903 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<> 128:9bcdf88f62b0 1904 {
<> 128:9bcdf88f62b0 1905 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1906 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1907 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<> 128:9bcdf88f62b0 1908 }
<> 128:9bcdf88f62b0 1909
<> 128:9bcdf88f62b0 1910 /**
<> 128:9bcdf88f62b0 1911 * @brief Get the current prescaler value acting on an input channel.
<> 128:9bcdf88f62b0 1912 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<> 128:9bcdf88f62b0 1913 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<> 128:9bcdf88f62b0 1914 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<> 128:9bcdf88f62b0 1915 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<> 128:9bcdf88f62b0 1916 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1917 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1918 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1919 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1920 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1921 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1922 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1923 * @arg @ref LL_TIM_ICPSC_DIV1
<> 128:9bcdf88f62b0 1924 * @arg @ref LL_TIM_ICPSC_DIV2
<> 128:9bcdf88f62b0 1925 * @arg @ref LL_TIM_ICPSC_DIV4
<> 128:9bcdf88f62b0 1926 * @arg @ref LL_TIM_ICPSC_DIV8
<> 128:9bcdf88f62b0 1927 */
<> 128:9bcdf88f62b0 1928 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 1929 {
<> 128:9bcdf88f62b0 1930 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1931 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1932 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<> 128:9bcdf88f62b0 1933 }
<> 128:9bcdf88f62b0 1934
<> 128:9bcdf88f62b0 1935 /**
<> 128:9bcdf88f62b0 1936 * @brief Set the input filter duration.
<> 128:9bcdf88f62b0 1937 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<> 128:9bcdf88f62b0 1938 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
<> 128:9bcdf88f62b0 1939 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
<> 128:9bcdf88f62b0 1940 * CCMR2 IC4F LL_TIM_IC_SetFilter
<> 128:9bcdf88f62b0 1941 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1942 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1943 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1944 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1945 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1946 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1947 * @param ICFilter This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1948 * @arg @ref LL_TIM_IC_FILTER_FDIV1
<> 128:9bcdf88f62b0 1949 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<> 128:9bcdf88f62b0 1950 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<> 128:9bcdf88f62b0 1951 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<> 128:9bcdf88f62b0 1952 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<> 128:9bcdf88f62b0 1953 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<> 128:9bcdf88f62b0 1954 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<> 128:9bcdf88f62b0 1955 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<> 128:9bcdf88f62b0 1956 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<> 128:9bcdf88f62b0 1957 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<> 128:9bcdf88f62b0 1958 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<> 128:9bcdf88f62b0 1959 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<> 128:9bcdf88f62b0 1960 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<> 128:9bcdf88f62b0 1961 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<> 128:9bcdf88f62b0 1962 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<> 128:9bcdf88f62b0 1963 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<> 128:9bcdf88f62b0 1964 * @retval None
<> 128:9bcdf88f62b0 1965 */
<> 128:9bcdf88f62b0 1966 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<> 128:9bcdf88f62b0 1967 {
<> 128:9bcdf88f62b0 1968 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 1969 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 1970 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<> 128:9bcdf88f62b0 1971 }
<> 128:9bcdf88f62b0 1972
<> 128:9bcdf88f62b0 1973 /**
<> 128:9bcdf88f62b0 1974 * @brief Get the input filter duration.
<> 128:9bcdf88f62b0 1975 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<> 128:9bcdf88f62b0 1976 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
<> 128:9bcdf88f62b0 1977 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
<> 128:9bcdf88f62b0 1978 * CCMR2 IC4F LL_TIM_IC_GetFilter
<> 128:9bcdf88f62b0 1979 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 1980 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1981 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 1982 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 1983 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 1984 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 1985 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1986 * @arg @ref LL_TIM_IC_FILTER_FDIV1
<> 128:9bcdf88f62b0 1987 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<> 128:9bcdf88f62b0 1988 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<> 128:9bcdf88f62b0 1989 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<> 128:9bcdf88f62b0 1990 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<> 128:9bcdf88f62b0 1991 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<> 128:9bcdf88f62b0 1992 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<> 128:9bcdf88f62b0 1993 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<> 128:9bcdf88f62b0 1994 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<> 128:9bcdf88f62b0 1995 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<> 128:9bcdf88f62b0 1996 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<> 128:9bcdf88f62b0 1997 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<> 128:9bcdf88f62b0 1998 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<> 128:9bcdf88f62b0 1999 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<> 128:9bcdf88f62b0 2000 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<> 128:9bcdf88f62b0 2001 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<> 128:9bcdf88f62b0 2002 */
<> 128:9bcdf88f62b0 2003 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 2004 {
<> 128:9bcdf88f62b0 2005 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 2006 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<> 128:9bcdf88f62b0 2007 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<> 128:9bcdf88f62b0 2008 }
<> 128:9bcdf88f62b0 2009
<> 128:9bcdf88f62b0 2010 /**
<> 128:9bcdf88f62b0 2011 * @brief Set the input channel polarity.
<> 128:9bcdf88f62b0 2012 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2013 * CCER CC1NP LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2014 * CCER CC2P LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2015 * CCER CC2NP LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2016 * CCER CC3P LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2017 * CCER CC3NP LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2018 * CCER CC4P LL_TIM_IC_SetPolarity\n
<> 128:9bcdf88f62b0 2019 * CCER CC4NP LL_TIM_IC_SetPolarity
<> 128:9bcdf88f62b0 2020 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2021 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2022 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 2023 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 2024 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 2025 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 2026 * @param ICPolarity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2027 * @arg @ref LL_TIM_IC_POLARITY_RISING
<> 128:9bcdf88f62b0 2028 * @arg @ref LL_TIM_IC_POLARITY_FALLING
<> 128:9bcdf88f62b0 2029 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<> 128:9bcdf88f62b0 2030 * @retval None
<> 128:9bcdf88f62b0 2031 */
<> 128:9bcdf88f62b0 2032 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<> 128:9bcdf88f62b0 2033 {
<> 128:9bcdf88f62b0 2034 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<> 128:9bcdf88f62b0 2036 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 2037 }
<> 128:9bcdf88f62b0 2038
<> 128:9bcdf88f62b0 2039 /**
<> 128:9bcdf88f62b0 2040 * @brief Get the current input channel polarity.
<> 128:9bcdf88f62b0 2041 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2042 * CCER CC1NP LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2043 * CCER CC2P LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2044 * CCER CC2NP LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2045 * CCER CC3P LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2046 * CCER CC3NP LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2047 * CCER CC4P LL_TIM_IC_GetPolarity\n
<> 128:9bcdf88f62b0 2048 * CCER CC4NP LL_TIM_IC_GetPolarity
<> 128:9bcdf88f62b0 2049 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2050 * @param Channel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2051 * @arg @ref LL_TIM_CHANNEL_CH1
<> 128:9bcdf88f62b0 2052 * @arg @ref LL_TIM_CHANNEL_CH2
<> 128:9bcdf88f62b0 2053 * @arg @ref LL_TIM_CHANNEL_CH3
<> 128:9bcdf88f62b0 2054 * @arg @ref LL_TIM_CHANNEL_CH4
<> 128:9bcdf88f62b0 2055 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 2056 * @arg @ref LL_TIM_IC_POLARITY_RISING
<> 128:9bcdf88f62b0 2057 * @arg @ref LL_TIM_IC_POLARITY_FALLING
<> 128:9bcdf88f62b0 2058 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<> 128:9bcdf88f62b0 2059 */
<> 128:9bcdf88f62b0 2060 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<> 128:9bcdf88f62b0 2061 {
<> 128:9bcdf88f62b0 2062 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<> 128:9bcdf88f62b0 2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<> 128:9bcdf88f62b0 2064 SHIFT_TAB_CCxP[iChannel]);
<> 128:9bcdf88f62b0 2065 }
<> 128:9bcdf88f62b0 2066
<> 128:9bcdf88f62b0 2067 /**
<> 128:9bcdf88f62b0 2068 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<> 128:9bcdf88f62b0 2069 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2070 * a timer instance provides an XOR input.
<> 128:9bcdf88f62b0 2071 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<> 128:9bcdf88f62b0 2072 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2073 * @retval None
<> 128:9bcdf88f62b0 2074 */
<> 128:9bcdf88f62b0 2075 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2076 {
<> 128:9bcdf88f62b0 2077 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<> 128:9bcdf88f62b0 2078 }
<> 128:9bcdf88f62b0 2079
<> 128:9bcdf88f62b0 2080 /**
<> 128:9bcdf88f62b0 2081 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<> 128:9bcdf88f62b0 2082 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2083 * a timer instance provides an XOR input.
<> 128:9bcdf88f62b0 2084 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<> 128:9bcdf88f62b0 2085 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2086 * @retval None
<> 128:9bcdf88f62b0 2087 */
<> 128:9bcdf88f62b0 2088 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2089 {
<> 128:9bcdf88f62b0 2090 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<> 128:9bcdf88f62b0 2091 }
<> 128:9bcdf88f62b0 2092
<> 128:9bcdf88f62b0 2093 /**
<> 128:9bcdf88f62b0 2094 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<> 128:9bcdf88f62b0 2095 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2096 * a timer instance provides an XOR input.
<> 128:9bcdf88f62b0 2097 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<> 128:9bcdf88f62b0 2098 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2099 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2100 */
<> 128:9bcdf88f62b0 2101 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2102 {
<> 128:9bcdf88f62b0 2103 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<> 128:9bcdf88f62b0 2104 }
<> 128:9bcdf88f62b0 2105
<> 128:9bcdf88f62b0 2106 /**
<> 128:9bcdf88f62b0 2107 * @brief Get captured value for input channel 1.
<> 128:9bcdf88f62b0 2108 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 2109 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2110 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 2111 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2112 * input channel 1 is supported by a timer instance.
<> 128:9bcdf88f62b0 2113 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<> 128:9bcdf88f62b0 2114 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2115 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 2116 */
<> 128:9bcdf88f62b0 2117 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2118 {
<> 128:9bcdf88f62b0 2119 return (uint32_t)(READ_REG(TIMx->CCR1));
<> 128:9bcdf88f62b0 2120 }
<> 128:9bcdf88f62b0 2121
<> 128:9bcdf88f62b0 2122 /**
<> 128:9bcdf88f62b0 2123 * @brief Get captured value for input channel 2.
<> 128:9bcdf88f62b0 2124 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 2125 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2126 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 2127 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2128 * input channel 2 is supported by a timer instance.
<> 128:9bcdf88f62b0 2129 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<> 128:9bcdf88f62b0 2130 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2131 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 2132 */
<> 128:9bcdf88f62b0 2133 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2134 {
<> 128:9bcdf88f62b0 2135 return (uint32_t)(READ_REG(TIMx->CCR2));
<> 128:9bcdf88f62b0 2136 }
<> 128:9bcdf88f62b0 2137
<> 128:9bcdf88f62b0 2138 /**
<> 128:9bcdf88f62b0 2139 * @brief Get captured value for input channel 3.
<> 128:9bcdf88f62b0 2140 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 2141 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2142 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 2143 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2144 * input channel 3 is supported by a timer instance.
<> 128:9bcdf88f62b0 2145 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<> 128:9bcdf88f62b0 2146 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2147 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 2148 */
<> 128:9bcdf88f62b0 2149 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2150 {
<> 128:9bcdf88f62b0 2151 return (uint32_t)(READ_REG(TIMx->CCR3));
<> 128:9bcdf88f62b0 2152 }
<> 128:9bcdf88f62b0 2153
<> 128:9bcdf88f62b0 2154 /**
<> 128:9bcdf88f62b0 2155 * @brief Get captured value for input channel 4.
<> 128:9bcdf88f62b0 2156 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<> 128:9bcdf88f62b0 2157 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2158 * whether or not a timer instance supports a 32 bits counter.
<> 128:9bcdf88f62b0 2159 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2160 * input channel 4 is supported by a timer instance.
<> 128:9bcdf88f62b0 2161 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<> 128:9bcdf88f62b0 2162 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2163 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<> 128:9bcdf88f62b0 2164 */
<> 128:9bcdf88f62b0 2165 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2166 {
<> 128:9bcdf88f62b0 2167 return (uint32_t)(READ_REG(TIMx->CCR4));
<> 128:9bcdf88f62b0 2168 }
<> 128:9bcdf88f62b0 2169
<> 128:9bcdf88f62b0 2170 /**
<> 128:9bcdf88f62b0 2171 * @}
<> 128:9bcdf88f62b0 2172 */
<> 128:9bcdf88f62b0 2173
<> 128:9bcdf88f62b0 2174 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<> 128:9bcdf88f62b0 2175 * @{
<> 128:9bcdf88f62b0 2176 */
<> 128:9bcdf88f62b0 2177 /**
<> 128:9bcdf88f62b0 2178 * @brief Enable external clock mode 2.
<> 128:9bcdf88f62b0 2179 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<> 128:9bcdf88f62b0 2180 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2181 * whether or not a timer instance supports external clock mode2.
<> 128:9bcdf88f62b0 2182 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<> 128:9bcdf88f62b0 2183 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2184 * @retval None
<> 128:9bcdf88f62b0 2185 */
<> 128:9bcdf88f62b0 2186 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2187 {
<> 128:9bcdf88f62b0 2188 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<> 128:9bcdf88f62b0 2189 }
<> 128:9bcdf88f62b0 2190
<> 128:9bcdf88f62b0 2191 /**
<> 128:9bcdf88f62b0 2192 * @brief Disable external clock mode 2.
<> 128:9bcdf88f62b0 2193 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2194 * whether or not a timer instance supports external clock mode2.
<> 128:9bcdf88f62b0 2195 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<> 128:9bcdf88f62b0 2196 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2197 * @retval None
<> 128:9bcdf88f62b0 2198 */
<> 128:9bcdf88f62b0 2199 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2200 {
<> 128:9bcdf88f62b0 2201 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<> 128:9bcdf88f62b0 2202 }
<> 128:9bcdf88f62b0 2203
<> 128:9bcdf88f62b0 2204 /**
<> 128:9bcdf88f62b0 2205 * @brief Indicate whether external clock mode 2 is enabled.
<> 128:9bcdf88f62b0 2206 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2207 * whether or not a timer instance supports external clock mode2.
<> 128:9bcdf88f62b0 2208 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<> 128:9bcdf88f62b0 2209 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2210 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2211 */
<> 128:9bcdf88f62b0 2212 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2213 {
<> 128:9bcdf88f62b0 2214 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<> 128:9bcdf88f62b0 2215 }
<> 128:9bcdf88f62b0 2216
<> 128:9bcdf88f62b0 2217 /**
<> 128:9bcdf88f62b0 2218 * @brief Set the clock source of the counter clock.
<> 128:9bcdf88f62b0 2219 * @note when selected clock source is external clock mode 1, the timer input
<> 128:9bcdf88f62b0 2220 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<> 128:9bcdf88f62b0 2221 * function. This timer input must be configured by calling
<> 128:9bcdf88f62b0 2222 * the @ref LL_TIM_IC_Config() function.
<> 128:9bcdf88f62b0 2223 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2224 * whether or not a timer instance supports external clock mode1.
<> 128:9bcdf88f62b0 2225 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2226 * whether or not a timer instance supports external clock mode2.
<> 128:9bcdf88f62b0 2227 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<> 128:9bcdf88f62b0 2228 * SMCR ECE LL_TIM_SetClockSource
<> 128:9bcdf88f62b0 2229 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2230 * @param ClockSource This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2231 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<> 128:9bcdf88f62b0 2232 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<> 128:9bcdf88f62b0 2233 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<> 128:9bcdf88f62b0 2234 * @retval None
<> 128:9bcdf88f62b0 2235 */
<> 128:9bcdf88f62b0 2236 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<> 128:9bcdf88f62b0 2237 {
<> 128:9bcdf88f62b0 2238 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
<> 128:9bcdf88f62b0 2239 }
<> 128:9bcdf88f62b0 2240
<> 128:9bcdf88f62b0 2241 /**
<> 128:9bcdf88f62b0 2242 * @brief Set the encoder interface mode.
<> 128:9bcdf88f62b0 2243 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2244 * whether or not a timer instance supports the encoder mode.
<> 128:9bcdf88f62b0 2245 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<> 128:9bcdf88f62b0 2246 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2247 * @param EncoderMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2248 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<> 128:9bcdf88f62b0 2249 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<> 128:9bcdf88f62b0 2250 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<> 128:9bcdf88f62b0 2251 * @retval None
<> 128:9bcdf88f62b0 2252 */
<> 128:9bcdf88f62b0 2253 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<> 128:9bcdf88f62b0 2254 {
<> 128:9bcdf88f62b0 2255 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<> 128:9bcdf88f62b0 2256 }
<> 128:9bcdf88f62b0 2257
<> 128:9bcdf88f62b0 2258 /**
<> 128:9bcdf88f62b0 2259 * @}
<> 128:9bcdf88f62b0 2260 */
<> 128:9bcdf88f62b0 2261
<> 128:9bcdf88f62b0 2262 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<> 128:9bcdf88f62b0 2263 * @{
<> 128:9bcdf88f62b0 2264 */
<> 128:9bcdf88f62b0 2265 /**
<> 128:9bcdf88f62b0 2266 * @brief Set the trigger output (TRGO) used for timer synchronization .
<> 128:9bcdf88f62b0 2267 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<> 128:9bcdf88f62b0 2268 * whether or not a timer instance can operate as a master timer.
<> 128:9bcdf88f62b0 2269 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<> 128:9bcdf88f62b0 2270 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2271 * @param TimerSynchronization This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2272 * @arg @ref LL_TIM_TRGO_RESET
<> 128:9bcdf88f62b0 2273 * @arg @ref LL_TIM_TRGO_ENABLE
<> 128:9bcdf88f62b0 2274 * @arg @ref LL_TIM_TRGO_UPDATE
<> 128:9bcdf88f62b0 2275 * @arg @ref LL_TIM_TRGO_CC1IF
<> 128:9bcdf88f62b0 2276 * @arg @ref LL_TIM_TRGO_OC1REF
<> 128:9bcdf88f62b0 2277 * @arg @ref LL_TIM_TRGO_OC2REF
<> 128:9bcdf88f62b0 2278 * @arg @ref LL_TIM_TRGO_OC3REF
<> 128:9bcdf88f62b0 2279 * @arg @ref LL_TIM_TRGO_OC4REF
<> 128:9bcdf88f62b0 2280 * @retval None
<> 128:9bcdf88f62b0 2281 */
<> 128:9bcdf88f62b0 2282 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<> 128:9bcdf88f62b0 2283 {
<> 128:9bcdf88f62b0 2284 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<> 128:9bcdf88f62b0 2285 }
<> 128:9bcdf88f62b0 2286
<> 128:9bcdf88f62b0 2287 /**
<> 128:9bcdf88f62b0 2288 * @brief Set the synchronization mode of a slave timer.
<> 128:9bcdf88f62b0 2289 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2290 * a timer instance can operate as a slave timer.
<> 128:9bcdf88f62b0 2291 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<> 128:9bcdf88f62b0 2292 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2293 * @param SlaveMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2294 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
<> 128:9bcdf88f62b0 2295 * @arg @ref LL_TIM_SLAVEMODE_RESET
<> 128:9bcdf88f62b0 2296 * @arg @ref LL_TIM_SLAVEMODE_GATED
<> 128:9bcdf88f62b0 2297 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<> 128:9bcdf88f62b0 2298 * @retval None
<> 128:9bcdf88f62b0 2299 */
<> 128:9bcdf88f62b0 2300 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<> 128:9bcdf88f62b0 2301 {
<> 128:9bcdf88f62b0 2302 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<> 128:9bcdf88f62b0 2303 }
<> 128:9bcdf88f62b0 2304
<> 128:9bcdf88f62b0 2305 /**
<> 128:9bcdf88f62b0 2306 * @brief Set the selects the trigger input to be used to synchronize the counter.
<> 128:9bcdf88f62b0 2307 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2308 * a timer instance can operate as a slave timer.
<> 128:9bcdf88f62b0 2309 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
<> 128:9bcdf88f62b0 2310 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2311 * @param TriggerInput This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2312 * @arg @ref LL_TIM_TS_ITR0
<> 128:9bcdf88f62b0 2313 * @arg @ref LL_TIM_TS_ITR1
<> 128:9bcdf88f62b0 2314 * @arg @ref LL_TIM_TS_ITR2
<> 128:9bcdf88f62b0 2315 * @arg @ref LL_TIM_TS_ITR3
<> 128:9bcdf88f62b0 2316 * @arg @ref LL_TIM_TS_TI1F_ED
<> 128:9bcdf88f62b0 2317 * @arg @ref LL_TIM_TS_TI1FP1
<> 128:9bcdf88f62b0 2318 * @arg @ref LL_TIM_TS_TI2FP2
<> 128:9bcdf88f62b0 2319 * @arg @ref LL_TIM_TS_ETRF
<> 128:9bcdf88f62b0 2320 * @retval None
<> 128:9bcdf88f62b0 2321 */
<> 128:9bcdf88f62b0 2322 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<> 128:9bcdf88f62b0 2323 {
<> 128:9bcdf88f62b0 2324 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<> 128:9bcdf88f62b0 2325 }
<> 128:9bcdf88f62b0 2326
<> 128:9bcdf88f62b0 2327 /**
<> 128:9bcdf88f62b0 2328 * @brief Enable the Master/Slave mode.
<> 128:9bcdf88f62b0 2329 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2330 * a timer instance can operate as a slave timer.
<> 128:9bcdf88f62b0 2331 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<> 128:9bcdf88f62b0 2332 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2333 * @retval None
<> 128:9bcdf88f62b0 2334 */
<> 128:9bcdf88f62b0 2335 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2336 {
<> 128:9bcdf88f62b0 2337 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<> 128:9bcdf88f62b0 2338 }
<> 128:9bcdf88f62b0 2339
<> 128:9bcdf88f62b0 2340 /**
<> 128:9bcdf88f62b0 2341 * @brief Disable the Master/Slave mode.
<> 128:9bcdf88f62b0 2342 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2343 * a timer instance can operate as a slave timer.
<> 128:9bcdf88f62b0 2344 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<> 128:9bcdf88f62b0 2345 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2346 * @retval None
<> 128:9bcdf88f62b0 2347 */
<> 128:9bcdf88f62b0 2348 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2349 {
<> 128:9bcdf88f62b0 2350 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<> 128:9bcdf88f62b0 2351 }
<> 128:9bcdf88f62b0 2352
<> 128:9bcdf88f62b0 2353 /**
<> 128:9bcdf88f62b0 2354 * @brief Indicates whether the Master/Slave mode is enabled.
<> 128:9bcdf88f62b0 2355 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2356 * a timer instance can operate as a slave timer.
<> 128:9bcdf88f62b0 2357 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<> 128:9bcdf88f62b0 2358 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2359 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2360 */
<> 128:9bcdf88f62b0 2361 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2362 {
<> 128:9bcdf88f62b0 2363 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<> 128:9bcdf88f62b0 2364 }
<> 128:9bcdf88f62b0 2365
<> 128:9bcdf88f62b0 2366 /**
<> 128:9bcdf88f62b0 2367 * @brief Configure the external trigger (ETR) input.
<> 128:9bcdf88f62b0 2368 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2369 * a timer instance provides an external trigger input.
<> 128:9bcdf88f62b0 2370 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<> 128:9bcdf88f62b0 2371 * SMCR ETPS LL_TIM_ConfigETR\n
<> 128:9bcdf88f62b0 2372 * SMCR ETF LL_TIM_ConfigETR
<> 128:9bcdf88f62b0 2373 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2374 * @param ETRPolarity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2375 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<> 128:9bcdf88f62b0 2376 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<> 128:9bcdf88f62b0 2377 * @param ETRPrescaler This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2378 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<> 128:9bcdf88f62b0 2379 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<> 128:9bcdf88f62b0 2380 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<> 128:9bcdf88f62b0 2381 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<> 128:9bcdf88f62b0 2382 * @param ETRFilter This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2383 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
<> 128:9bcdf88f62b0 2384 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<> 128:9bcdf88f62b0 2385 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<> 128:9bcdf88f62b0 2386 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<> 128:9bcdf88f62b0 2387 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<> 128:9bcdf88f62b0 2388 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<> 128:9bcdf88f62b0 2389 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<> 128:9bcdf88f62b0 2390 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<> 128:9bcdf88f62b0 2391 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<> 128:9bcdf88f62b0 2392 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<> 128:9bcdf88f62b0 2393 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<> 128:9bcdf88f62b0 2394 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<> 128:9bcdf88f62b0 2395 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<> 128:9bcdf88f62b0 2396 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<> 128:9bcdf88f62b0 2397 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<> 128:9bcdf88f62b0 2398 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<> 128:9bcdf88f62b0 2399 * @retval None
<> 128:9bcdf88f62b0 2400 */
<> 128:9bcdf88f62b0 2401 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<> 128:9bcdf88f62b0 2402 uint32_t ETRFilter)
<> 128:9bcdf88f62b0 2403 {
<> 128:9bcdf88f62b0 2404 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
<> 128:9bcdf88f62b0 2405 }
<> 128:9bcdf88f62b0 2406
<> 128:9bcdf88f62b0 2407 /**
<> 128:9bcdf88f62b0 2408 * @}
<> 128:9bcdf88f62b0 2409 */
<> 128:9bcdf88f62b0 2410
<> 128:9bcdf88f62b0 2411 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<> 128:9bcdf88f62b0 2412 * @{
<> 128:9bcdf88f62b0 2413 */
<> 128:9bcdf88f62b0 2414 /**
<> 128:9bcdf88f62b0 2415 * @brief Configures the timer DMA burst feature.
<> 128:9bcdf88f62b0 2416 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<> 128:9bcdf88f62b0 2417 * not a timer instance supports the DMA burst mode.
<> 128:9bcdf88f62b0 2418 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<> 128:9bcdf88f62b0 2419 * DCR DBA LL_TIM_ConfigDMABurst
<> 128:9bcdf88f62b0 2420 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2421 * @param DMABurstBaseAddress This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2422 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<> 128:9bcdf88f62b0 2423 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<> 128:9bcdf88f62b0 2424 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<> 128:9bcdf88f62b0 2425 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<> 128:9bcdf88f62b0 2426 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<> 128:9bcdf88f62b0 2427 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<> 128:9bcdf88f62b0 2428 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<> 128:9bcdf88f62b0 2429 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<> 128:9bcdf88f62b0 2430 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<> 128:9bcdf88f62b0 2431 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<> 128:9bcdf88f62b0 2432 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<> 128:9bcdf88f62b0 2433 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<> 128:9bcdf88f62b0 2434 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<> 128:9bcdf88f62b0 2435 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<> 128:9bcdf88f62b0 2436 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<> 128:9bcdf88f62b0 2437 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<> 128:9bcdf88f62b0 2438 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
<> 128:9bcdf88f62b0 2439 * @param DMABurstLength This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2440 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<> 128:9bcdf88f62b0 2441 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<> 128:9bcdf88f62b0 2442 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<> 128:9bcdf88f62b0 2443 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<> 128:9bcdf88f62b0 2444 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<> 128:9bcdf88f62b0 2445 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<> 128:9bcdf88f62b0 2446 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<> 128:9bcdf88f62b0 2447 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<> 128:9bcdf88f62b0 2448 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<> 128:9bcdf88f62b0 2449 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<> 128:9bcdf88f62b0 2450 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<> 128:9bcdf88f62b0 2451 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<> 128:9bcdf88f62b0 2452 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<> 128:9bcdf88f62b0 2453 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<> 128:9bcdf88f62b0 2454 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<> 128:9bcdf88f62b0 2455 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<> 128:9bcdf88f62b0 2456 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<> 128:9bcdf88f62b0 2457 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<> 128:9bcdf88f62b0 2458 * @retval None
<> 128:9bcdf88f62b0 2459 */
<> 128:9bcdf88f62b0 2460 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<> 128:9bcdf88f62b0 2461 {
<> 128:9bcdf88f62b0 2462 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
<> 128:9bcdf88f62b0 2463 }
<> 128:9bcdf88f62b0 2464
<> 128:9bcdf88f62b0 2465 /**
<> 128:9bcdf88f62b0 2466 * @}
<> 128:9bcdf88f62b0 2467 */
<> 128:9bcdf88f62b0 2468
<> 128:9bcdf88f62b0 2469 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<> 128:9bcdf88f62b0 2470 * @{
<> 128:9bcdf88f62b0 2471 */
<> 128:9bcdf88f62b0 2472 /**
<> 128:9bcdf88f62b0 2473 * @brief Remap TIM inputs (input channel, internal/external triggers).
<> 128:9bcdf88f62b0 2474 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<> 128:9bcdf88f62b0 2475 * a some timer inputs can be remapped.
<> 128:9bcdf88f62b0 2476 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2477 * TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2478 * TIM9_OR TI1_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2479 * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2480 * TIM10_OR TI1_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2481 * TIM10_OR ETR_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2482 * TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2483 * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2484 * TIM11_OR ETR_RMP LL_TIM_SetRemap\n
<> 128:9bcdf88f62b0 2485 * TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
<> 128:9bcdf88f62b0 2486 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2487 * @param Remap Remap params depends on the TIMx. Description available only
<> 128:9bcdf88f62b0 2488 * in CHM version of the User Manual (not in .pdf).
<> 128:9bcdf88f62b0 2489 * Otherwise see Reference Manual description of OR registers.
<> 128:9bcdf88f62b0 2490 *
<> 128:9bcdf88f62b0 2491 * Below description summarizes "Timer Instance" and "Remap" param combinations:
<> 128:9bcdf88f62b0 2492 *
<> 128:9bcdf88f62b0 2493 * TIM2: any combination of ITR1_RMP where
<> 128:9bcdf88f62b0 2494 *
<> 128:9bcdf88f62b0 2495 * . . ITR1_RMP can be one of the following values
<> 128:9bcdf88f62b0 2496 * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
<> 128:9bcdf88f62b0 2497 * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
<> 128:9bcdf88f62b0 2498 *
<> 128:9bcdf88f62b0 2499 * TIM3: any combination of ITR2_RMP where
<> 128:9bcdf88f62b0 2500 *
<> 128:9bcdf88f62b0 2501 * . . ITR2_RMP can be one of the following values
<> 128:9bcdf88f62b0 2502 * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
<> 128:9bcdf88f62b0 2503 * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
<> 128:9bcdf88f62b0 2504 *
<> 128:9bcdf88f62b0 2505 * TIM9: any combination of TI1_RMP, ITR1_RMP where
<> 128:9bcdf88f62b0 2506 *
<> 128:9bcdf88f62b0 2507 * . . TI1_RMP can be one of the following values
<> 128:9bcdf88f62b0 2508 * @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
<> 128:9bcdf88f62b0 2509 * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
<> 128:9bcdf88f62b0 2510 *
<> 128:9bcdf88f62b0 2511 * . . ITR1_RMP can be one of the following values
<> 128:9bcdf88f62b0 2512 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
<> 128:9bcdf88f62b0 2513 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
<> 128:9bcdf88f62b0 2514 *
<> 128:9bcdf88f62b0 2515 *
<> 128:9bcdf88f62b0 2516 * TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
<> 128:9bcdf88f62b0 2517 *
<> 128:9bcdf88f62b0 2518 * . . TI1_RMP can be one of the following values
<> 128:9bcdf88f62b0 2519 * @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
<> 128:9bcdf88f62b0 2520 * @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
<> 128:9bcdf88f62b0 2521 * @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
<> 128:9bcdf88f62b0 2522 * @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
<> 128:9bcdf88f62b0 2523 *
<> 128:9bcdf88f62b0 2524 * . . ETR_RMP can be one of the following values
<> 128:9bcdf88f62b0 2525 * @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
<> 128:9bcdf88f62b0 2526 *
<> 128:9bcdf88f62b0 2527 * . . TI1_RMP_RI can be one of the following values
<> 128:9bcdf88f62b0 2528 * @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
<> 128:9bcdf88f62b0 2529 *
<> 128:9bcdf88f62b0 2530 *
<> 128:9bcdf88f62b0 2531 * TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
<> 128:9bcdf88f62b0 2532 *
<> 128:9bcdf88f62b0 2533 * . . TI1_RMP can be one of the following values
<> 128:9bcdf88f62b0 2534 * @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
<> 128:9bcdf88f62b0 2535 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
<> 128:9bcdf88f62b0 2536 * @arg @ref LL_TIM_TIM11_TI1_RMP
<> 128:9bcdf88f62b0 2537 *
<> 128:9bcdf88f62b0 2538 * . . ETR_RMP can be one of the following values
<> 128:9bcdf88f62b0 2539 * @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
<> 128:9bcdf88f62b0 2540 *
<> 128:9bcdf88f62b0 2541 * . . TI1_RMP_RI can be one of the following values
<> 128:9bcdf88f62b0 2542 * @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
<> 128:9bcdf88f62b0 2543 *
<> 128:9bcdf88f62b0 2544 * (*) value not available in all devices categories
<> 128:9bcdf88f62b0 2545 * (**) register not available in all devices categories
<> 128:9bcdf88f62b0 2546 *
<> 128:9bcdf88f62b0 2547 * @note Option registers are available only for cat.3, cat.4 and cat.5 devices
<> 128:9bcdf88f62b0 2548 * @retval None
<> 128:9bcdf88f62b0 2549 */
<> 128:9bcdf88f62b0 2550 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<> 128:9bcdf88f62b0 2551 {
<> 128:9bcdf88f62b0 2552 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<> 128:9bcdf88f62b0 2553 }
<> 128:9bcdf88f62b0 2554
<> 128:9bcdf88f62b0 2555 /**
<> 128:9bcdf88f62b0 2556 * @}
<> 128:9bcdf88f62b0 2557 */
<> 128:9bcdf88f62b0 2558
<> 128:9bcdf88f62b0 2559 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<> 128:9bcdf88f62b0 2560 * @{
<> 128:9bcdf88f62b0 2561 */
<> 128:9bcdf88f62b0 2562 /**
<> 128:9bcdf88f62b0 2563 * @brief Set the OCREF clear source
<> 128:9bcdf88f62b0 2564 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<> 128:9bcdf88f62b0 2565 * @note This function can only be used in Output compare and PWM modes.
<> 128:9bcdf88f62b0 2566 * @note the ETR signal can be connected to the output of a comparator to be used for current handling
<> 128:9bcdf88f62b0 2567 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<> 128:9bcdf88f62b0 2568 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2569 * @param OCRefClearInputSource This parameter can be one of the following values:
<> 128:9bcdf88f62b0 2570 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
<> 128:9bcdf88f62b0 2571 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<> 128:9bcdf88f62b0 2572 * @retval None
<> 128:9bcdf88f62b0 2573 */
<> 128:9bcdf88f62b0 2574 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
<> 128:9bcdf88f62b0 2575 {
<> 128:9bcdf88f62b0 2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<> 128:9bcdf88f62b0 2577 }
<> 128:9bcdf88f62b0 2578 /**
<> 128:9bcdf88f62b0 2579 * @}
<> 128:9bcdf88f62b0 2580 */
<> 128:9bcdf88f62b0 2581
<> 128:9bcdf88f62b0 2582 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<> 128:9bcdf88f62b0 2583 * @{
<> 128:9bcdf88f62b0 2584 */
<> 128:9bcdf88f62b0 2585 /**
<> 128:9bcdf88f62b0 2586 * @brief Clear the update interrupt flag (UIF).
<> 128:9bcdf88f62b0 2587 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<> 128:9bcdf88f62b0 2588 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2589 * @retval None
<> 128:9bcdf88f62b0 2590 */
<> 128:9bcdf88f62b0 2591 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2592 {
<> 128:9bcdf88f62b0 2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<> 128:9bcdf88f62b0 2594 }
<> 128:9bcdf88f62b0 2595
<> 128:9bcdf88f62b0 2596 /**
<> 128:9bcdf88f62b0 2597 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<> 128:9bcdf88f62b0 2598 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<> 128:9bcdf88f62b0 2599 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2600 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2601 */
<> 128:9bcdf88f62b0 2602 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2603 {
<> 128:9bcdf88f62b0 2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<> 128:9bcdf88f62b0 2605 }
<> 128:9bcdf88f62b0 2606
<> 128:9bcdf88f62b0 2607 /**
<> 128:9bcdf88f62b0 2608 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<> 128:9bcdf88f62b0 2609 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<> 128:9bcdf88f62b0 2610 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2611 * @retval None
<> 128:9bcdf88f62b0 2612 */
<> 128:9bcdf88f62b0 2613 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2614 {
<> 128:9bcdf88f62b0 2615 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<> 128:9bcdf88f62b0 2616 }
<> 128:9bcdf88f62b0 2617
<> 128:9bcdf88f62b0 2618 /**
<> 128:9bcdf88f62b0 2619 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<> 128:9bcdf88f62b0 2620 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<> 128:9bcdf88f62b0 2621 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2622 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2623 */
<> 128:9bcdf88f62b0 2624 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2625 {
<> 128:9bcdf88f62b0 2626 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<> 128:9bcdf88f62b0 2627 }
<> 128:9bcdf88f62b0 2628
<> 128:9bcdf88f62b0 2629 /**
<> 128:9bcdf88f62b0 2630 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<> 128:9bcdf88f62b0 2631 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<> 128:9bcdf88f62b0 2632 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2633 * @retval None
<> 128:9bcdf88f62b0 2634 */
<> 128:9bcdf88f62b0 2635 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2636 {
<> 128:9bcdf88f62b0 2637 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<> 128:9bcdf88f62b0 2638 }
<> 128:9bcdf88f62b0 2639
<> 128:9bcdf88f62b0 2640 /**
<> 128:9bcdf88f62b0 2641 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<> 128:9bcdf88f62b0 2642 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<> 128:9bcdf88f62b0 2643 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2644 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2645 */
<> 128:9bcdf88f62b0 2646 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2647 {
<> 128:9bcdf88f62b0 2648 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<> 128:9bcdf88f62b0 2649 }
<> 128:9bcdf88f62b0 2650
<> 128:9bcdf88f62b0 2651 /**
<> 128:9bcdf88f62b0 2652 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<> 128:9bcdf88f62b0 2653 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<> 128:9bcdf88f62b0 2654 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2655 * @retval None
<> 128:9bcdf88f62b0 2656 */
<> 128:9bcdf88f62b0 2657 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2658 {
<> 128:9bcdf88f62b0 2659 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<> 128:9bcdf88f62b0 2660 }
<> 128:9bcdf88f62b0 2661
<> 128:9bcdf88f62b0 2662 /**
<> 128:9bcdf88f62b0 2663 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<> 128:9bcdf88f62b0 2664 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<> 128:9bcdf88f62b0 2665 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2666 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2667 */
<> 128:9bcdf88f62b0 2668 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2669 {
<> 128:9bcdf88f62b0 2670 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<> 128:9bcdf88f62b0 2671 }
<> 128:9bcdf88f62b0 2672
<> 128:9bcdf88f62b0 2673 /**
<> 128:9bcdf88f62b0 2674 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<> 128:9bcdf88f62b0 2675 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<> 128:9bcdf88f62b0 2676 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2677 * @retval None
<> 128:9bcdf88f62b0 2678 */
<> 128:9bcdf88f62b0 2679 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2680 {
<> 128:9bcdf88f62b0 2681 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<> 128:9bcdf88f62b0 2682 }
<> 128:9bcdf88f62b0 2683
<> 128:9bcdf88f62b0 2684 /**
<> 128:9bcdf88f62b0 2685 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<> 128:9bcdf88f62b0 2686 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<> 128:9bcdf88f62b0 2687 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2688 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2689 */
<> 128:9bcdf88f62b0 2690 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2691 {
<> 128:9bcdf88f62b0 2692 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<> 128:9bcdf88f62b0 2693 }
<> 128:9bcdf88f62b0 2694
<> 128:9bcdf88f62b0 2695 /**
<> 128:9bcdf88f62b0 2696 * @brief Clear the trigger interrupt flag (TIF).
<> 128:9bcdf88f62b0 2697 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<> 128:9bcdf88f62b0 2698 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2699 * @retval None
<> 128:9bcdf88f62b0 2700 */
<> 128:9bcdf88f62b0 2701 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2702 {
<> 128:9bcdf88f62b0 2703 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<> 128:9bcdf88f62b0 2704 }
<> 128:9bcdf88f62b0 2705
<> 128:9bcdf88f62b0 2706 /**
<> 128:9bcdf88f62b0 2707 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<> 128:9bcdf88f62b0 2708 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<> 128:9bcdf88f62b0 2709 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2710 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2711 */
<> 128:9bcdf88f62b0 2712 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2713 {
<> 128:9bcdf88f62b0 2714 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<> 128:9bcdf88f62b0 2715 }
<> 128:9bcdf88f62b0 2716
<> 128:9bcdf88f62b0 2717 /**
<> 128:9bcdf88f62b0 2718 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<> 128:9bcdf88f62b0 2719 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<> 128:9bcdf88f62b0 2720 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2721 * @retval None
<> 128:9bcdf88f62b0 2722 */
<> 128:9bcdf88f62b0 2723 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2724 {
<> 128:9bcdf88f62b0 2725 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<> 128:9bcdf88f62b0 2726 }
<> 128:9bcdf88f62b0 2727
<> 128:9bcdf88f62b0 2728 /**
<> 128:9bcdf88f62b0 2729 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<> 128:9bcdf88f62b0 2730 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<> 128:9bcdf88f62b0 2731 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2732 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2733 */
<> 128:9bcdf88f62b0 2734 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2735 {
<> 128:9bcdf88f62b0 2736 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<> 128:9bcdf88f62b0 2737 }
<> 128:9bcdf88f62b0 2738
<> 128:9bcdf88f62b0 2739 /**
<> 128:9bcdf88f62b0 2740 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<> 128:9bcdf88f62b0 2741 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<> 128:9bcdf88f62b0 2742 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2743 * @retval None
<> 128:9bcdf88f62b0 2744 */
<> 128:9bcdf88f62b0 2745 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2746 {
<> 128:9bcdf88f62b0 2747 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<> 128:9bcdf88f62b0 2748 }
<> 128:9bcdf88f62b0 2749
<> 128:9bcdf88f62b0 2750 /**
<> 128:9bcdf88f62b0 2751 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<> 128:9bcdf88f62b0 2752 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<> 128:9bcdf88f62b0 2753 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2754 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2755 */
<> 128:9bcdf88f62b0 2756 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2757 {
<> 128:9bcdf88f62b0 2758 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<> 128:9bcdf88f62b0 2759 }
<> 128:9bcdf88f62b0 2760
<> 128:9bcdf88f62b0 2761 /**
<> 128:9bcdf88f62b0 2762 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<> 128:9bcdf88f62b0 2763 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<> 128:9bcdf88f62b0 2764 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2765 * @retval None
<> 128:9bcdf88f62b0 2766 */
<> 128:9bcdf88f62b0 2767 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2768 {
<> 128:9bcdf88f62b0 2769 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<> 128:9bcdf88f62b0 2770 }
<> 128:9bcdf88f62b0 2771
<> 128:9bcdf88f62b0 2772 /**
<> 128:9bcdf88f62b0 2773 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<> 128:9bcdf88f62b0 2774 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<> 128:9bcdf88f62b0 2775 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2776 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2777 */
<> 128:9bcdf88f62b0 2778 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2779 {
<> 128:9bcdf88f62b0 2780 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<> 128:9bcdf88f62b0 2781 }
<> 128:9bcdf88f62b0 2782
<> 128:9bcdf88f62b0 2783 /**
<> 128:9bcdf88f62b0 2784 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<> 128:9bcdf88f62b0 2785 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<> 128:9bcdf88f62b0 2786 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2787 * @retval None
<> 128:9bcdf88f62b0 2788 */
<> 128:9bcdf88f62b0 2789 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2790 {
<> 128:9bcdf88f62b0 2791 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<> 128:9bcdf88f62b0 2792 }
<> 128:9bcdf88f62b0 2793
<> 128:9bcdf88f62b0 2794 /**
<> 128:9bcdf88f62b0 2795 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<> 128:9bcdf88f62b0 2796 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<> 128:9bcdf88f62b0 2797 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2798 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2799 */
<> 128:9bcdf88f62b0 2800 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2801 {
<> 128:9bcdf88f62b0 2802 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<> 128:9bcdf88f62b0 2803 }
<> 128:9bcdf88f62b0 2804
<> 128:9bcdf88f62b0 2805 /**
<> 128:9bcdf88f62b0 2806 * @}
<> 128:9bcdf88f62b0 2807 */
<> 128:9bcdf88f62b0 2808
<> 128:9bcdf88f62b0 2809 /** @defgroup TIM_LL_EF_IT_Management IT-Management
<> 128:9bcdf88f62b0 2810 * @{
<> 128:9bcdf88f62b0 2811 */
<> 128:9bcdf88f62b0 2812 /**
<> 128:9bcdf88f62b0 2813 * @brief Enable update interrupt (UIE).
<> 128:9bcdf88f62b0 2814 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<> 128:9bcdf88f62b0 2815 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2816 * @retval None
<> 128:9bcdf88f62b0 2817 */
<> 128:9bcdf88f62b0 2818 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2819 {
<> 128:9bcdf88f62b0 2820 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<> 128:9bcdf88f62b0 2821 }
<> 128:9bcdf88f62b0 2822
<> 128:9bcdf88f62b0 2823 /**
<> 128:9bcdf88f62b0 2824 * @brief Disable update interrupt (UIE).
<> 128:9bcdf88f62b0 2825 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<> 128:9bcdf88f62b0 2826 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2827 * @retval None
<> 128:9bcdf88f62b0 2828 */
<> 128:9bcdf88f62b0 2829 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2830 {
<> 128:9bcdf88f62b0 2831 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<> 128:9bcdf88f62b0 2832 }
<> 128:9bcdf88f62b0 2833
<> 128:9bcdf88f62b0 2834 /**
<> 128:9bcdf88f62b0 2835 * @brief Indicates whether the update interrupt (UIE) is enabled.
<> 128:9bcdf88f62b0 2836 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<> 128:9bcdf88f62b0 2837 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2838 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2839 */
<> 128:9bcdf88f62b0 2840 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2841 {
<> 128:9bcdf88f62b0 2842 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<> 128:9bcdf88f62b0 2843 }
<> 128:9bcdf88f62b0 2844
<> 128:9bcdf88f62b0 2845 /**
<> 128:9bcdf88f62b0 2846 * @brief Enable capture/compare 1 interrupt (CC1IE).
<> 128:9bcdf88f62b0 2847 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<> 128:9bcdf88f62b0 2848 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2849 * @retval None
<> 128:9bcdf88f62b0 2850 */
<> 128:9bcdf88f62b0 2851 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2852 {
<> 128:9bcdf88f62b0 2853 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<> 128:9bcdf88f62b0 2854 }
<> 128:9bcdf88f62b0 2855
<> 128:9bcdf88f62b0 2856 /**
<> 128:9bcdf88f62b0 2857 * @brief Disable capture/compare 1 interrupt (CC1IE).
<> 128:9bcdf88f62b0 2858 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<> 128:9bcdf88f62b0 2859 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2860 * @retval None
<> 128:9bcdf88f62b0 2861 */
<> 128:9bcdf88f62b0 2862 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2863 {
<> 128:9bcdf88f62b0 2864 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<> 128:9bcdf88f62b0 2865 }
<> 128:9bcdf88f62b0 2866
<> 128:9bcdf88f62b0 2867 /**
<> 128:9bcdf88f62b0 2868 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<> 128:9bcdf88f62b0 2869 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<> 128:9bcdf88f62b0 2870 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2871 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2872 */
<> 128:9bcdf88f62b0 2873 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2874 {
<> 128:9bcdf88f62b0 2875 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<> 128:9bcdf88f62b0 2876 }
<> 128:9bcdf88f62b0 2877
<> 128:9bcdf88f62b0 2878 /**
<> 128:9bcdf88f62b0 2879 * @brief Enable capture/compare 2 interrupt (CC2IE).
<> 128:9bcdf88f62b0 2880 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<> 128:9bcdf88f62b0 2881 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2882 * @retval None
<> 128:9bcdf88f62b0 2883 */
<> 128:9bcdf88f62b0 2884 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2885 {
<> 128:9bcdf88f62b0 2886 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<> 128:9bcdf88f62b0 2887 }
<> 128:9bcdf88f62b0 2888
<> 128:9bcdf88f62b0 2889 /**
<> 128:9bcdf88f62b0 2890 * @brief Disable capture/compare 2 interrupt (CC2IE).
<> 128:9bcdf88f62b0 2891 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<> 128:9bcdf88f62b0 2892 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2893 * @retval None
<> 128:9bcdf88f62b0 2894 */
<> 128:9bcdf88f62b0 2895 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2896 {
<> 128:9bcdf88f62b0 2897 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<> 128:9bcdf88f62b0 2898 }
<> 128:9bcdf88f62b0 2899
<> 128:9bcdf88f62b0 2900 /**
<> 128:9bcdf88f62b0 2901 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<> 128:9bcdf88f62b0 2902 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<> 128:9bcdf88f62b0 2903 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2904 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2905 */
<> 128:9bcdf88f62b0 2906 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2907 {
<> 128:9bcdf88f62b0 2908 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<> 128:9bcdf88f62b0 2909 }
<> 128:9bcdf88f62b0 2910
<> 128:9bcdf88f62b0 2911 /**
<> 128:9bcdf88f62b0 2912 * @brief Enable capture/compare 3 interrupt (CC3IE).
<> 128:9bcdf88f62b0 2913 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<> 128:9bcdf88f62b0 2914 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2915 * @retval None
<> 128:9bcdf88f62b0 2916 */
<> 128:9bcdf88f62b0 2917 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2918 {
<> 128:9bcdf88f62b0 2919 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<> 128:9bcdf88f62b0 2920 }
<> 128:9bcdf88f62b0 2921
<> 128:9bcdf88f62b0 2922 /**
<> 128:9bcdf88f62b0 2923 * @brief Disable capture/compare 3 interrupt (CC3IE).
<> 128:9bcdf88f62b0 2924 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<> 128:9bcdf88f62b0 2925 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2926 * @retval None
<> 128:9bcdf88f62b0 2927 */
<> 128:9bcdf88f62b0 2928 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2929 {
<> 128:9bcdf88f62b0 2930 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<> 128:9bcdf88f62b0 2931 }
<> 128:9bcdf88f62b0 2932
<> 128:9bcdf88f62b0 2933 /**
<> 128:9bcdf88f62b0 2934 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<> 128:9bcdf88f62b0 2935 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<> 128:9bcdf88f62b0 2936 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2937 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2938 */
<> 128:9bcdf88f62b0 2939 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2940 {
<> 128:9bcdf88f62b0 2941 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<> 128:9bcdf88f62b0 2942 }
<> 128:9bcdf88f62b0 2943
<> 128:9bcdf88f62b0 2944 /**
<> 128:9bcdf88f62b0 2945 * @brief Enable capture/compare 4 interrupt (CC4IE).
<> 128:9bcdf88f62b0 2946 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<> 128:9bcdf88f62b0 2947 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2948 * @retval None
<> 128:9bcdf88f62b0 2949 */
<> 128:9bcdf88f62b0 2950 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2951 {
<> 128:9bcdf88f62b0 2952 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<> 128:9bcdf88f62b0 2953 }
<> 128:9bcdf88f62b0 2954
<> 128:9bcdf88f62b0 2955 /**
<> 128:9bcdf88f62b0 2956 * @brief Disable capture/compare 4 interrupt (CC4IE).
<> 128:9bcdf88f62b0 2957 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<> 128:9bcdf88f62b0 2958 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2959 * @retval None
<> 128:9bcdf88f62b0 2960 */
<> 128:9bcdf88f62b0 2961 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2962 {
<> 128:9bcdf88f62b0 2963 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<> 128:9bcdf88f62b0 2964 }
<> 128:9bcdf88f62b0 2965
<> 128:9bcdf88f62b0 2966 /**
<> 128:9bcdf88f62b0 2967 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<> 128:9bcdf88f62b0 2968 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<> 128:9bcdf88f62b0 2969 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2970 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 2971 */
<> 128:9bcdf88f62b0 2972 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2973 {
<> 128:9bcdf88f62b0 2974 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<> 128:9bcdf88f62b0 2975 }
<> 128:9bcdf88f62b0 2976
<> 128:9bcdf88f62b0 2977 /**
<> 128:9bcdf88f62b0 2978 * @brief Enable trigger interrupt (TIE).
<> 128:9bcdf88f62b0 2979 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<> 128:9bcdf88f62b0 2980 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2981 * @retval None
<> 128:9bcdf88f62b0 2982 */
<> 128:9bcdf88f62b0 2983 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2984 {
<> 128:9bcdf88f62b0 2985 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<> 128:9bcdf88f62b0 2986 }
<> 128:9bcdf88f62b0 2987
<> 128:9bcdf88f62b0 2988 /**
<> 128:9bcdf88f62b0 2989 * @brief Disable trigger interrupt (TIE).
<> 128:9bcdf88f62b0 2990 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<> 128:9bcdf88f62b0 2991 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 2992 * @retval None
<> 128:9bcdf88f62b0 2993 */
<> 128:9bcdf88f62b0 2994 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 2995 {
<> 128:9bcdf88f62b0 2996 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<> 128:9bcdf88f62b0 2997 }
<> 128:9bcdf88f62b0 2998
<> 128:9bcdf88f62b0 2999 /**
<> 128:9bcdf88f62b0 3000 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
<> 128:9bcdf88f62b0 3001 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<> 128:9bcdf88f62b0 3002 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3003 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3004 */
<> 128:9bcdf88f62b0 3005 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3006 {
<> 128:9bcdf88f62b0 3007 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<> 128:9bcdf88f62b0 3008 }
<> 128:9bcdf88f62b0 3009
<> 128:9bcdf88f62b0 3010 /**
<> 128:9bcdf88f62b0 3011 * @}
<> 128:9bcdf88f62b0 3012 */
<> 128:9bcdf88f62b0 3013
<> 128:9bcdf88f62b0 3014 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<> 128:9bcdf88f62b0 3015 * @{
<> 128:9bcdf88f62b0 3016 */
<> 128:9bcdf88f62b0 3017 /**
<> 128:9bcdf88f62b0 3018 * @brief Enable update DMA request (UDE).
<> 128:9bcdf88f62b0 3019 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<> 128:9bcdf88f62b0 3020 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3021 * @retval None
<> 128:9bcdf88f62b0 3022 */
<> 128:9bcdf88f62b0 3023 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3024 {
<> 128:9bcdf88f62b0 3025 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<> 128:9bcdf88f62b0 3026 }
<> 128:9bcdf88f62b0 3027
<> 128:9bcdf88f62b0 3028 /**
<> 128:9bcdf88f62b0 3029 * @brief Disable update DMA request (UDE).
<> 128:9bcdf88f62b0 3030 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<> 128:9bcdf88f62b0 3031 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3032 * @retval None
<> 128:9bcdf88f62b0 3033 */
<> 128:9bcdf88f62b0 3034 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3035 {
<> 128:9bcdf88f62b0 3036 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<> 128:9bcdf88f62b0 3037 }
<> 128:9bcdf88f62b0 3038
<> 128:9bcdf88f62b0 3039 /**
<> 128:9bcdf88f62b0 3040 * @brief Indicates whether the update DMA request (UDE) is enabled.
<> 128:9bcdf88f62b0 3041 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<> 128:9bcdf88f62b0 3042 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3043 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3044 */
<> 128:9bcdf88f62b0 3045 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3046 {
<> 128:9bcdf88f62b0 3047 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<> 128:9bcdf88f62b0 3048 }
<> 128:9bcdf88f62b0 3049
<> 128:9bcdf88f62b0 3050 /**
<> 128:9bcdf88f62b0 3051 * @brief Enable capture/compare 1 DMA request (CC1DE).
<> 128:9bcdf88f62b0 3052 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<> 128:9bcdf88f62b0 3053 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3054 * @retval None
<> 128:9bcdf88f62b0 3055 */
<> 128:9bcdf88f62b0 3056 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3057 {
<> 128:9bcdf88f62b0 3058 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<> 128:9bcdf88f62b0 3059 }
<> 128:9bcdf88f62b0 3060
<> 128:9bcdf88f62b0 3061 /**
<> 128:9bcdf88f62b0 3062 * @brief Disable capture/compare 1 DMA request (CC1DE).
<> 128:9bcdf88f62b0 3063 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<> 128:9bcdf88f62b0 3064 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3065 * @retval None
<> 128:9bcdf88f62b0 3066 */
<> 128:9bcdf88f62b0 3067 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3068 {
<> 128:9bcdf88f62b0 3069 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<> 128:9bcdf88f62b0 3070 }
<> 128:9bcdf88f62b0 3071
<> 128:9bcdf88f62b0 3072 /**
<> 128:9bcdf88f62b0 3073 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<> 128:9bcdf88f62b0 3074 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<> 128:9bcdf88f62b0 3075 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3076 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3077 */
<> 128:9bcdf88f62b0 3078 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3079 {
<> 128:9bcdf88f62b0 3080 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<> 128:9bcdf88f62b0 3081 }
<> 128:9bcdf88f62b0 3082
<> 128:9bcdf88f62b0 3083 /**
<> 128:9bcdf88f62b0 3084 * @brief Enable capture/compare 2 DMA request (CC2DE).
<> 128:9bcdf88f62b0 3085 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<> 128:9bcdf88f62b0 3086 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3087 * @retval None
<> 128:9bcdf88f62b0 3088 */
<> 128:9bcdf88f62b0 3089 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3090 {
<> 128:9bcdf88f62b0 3091 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<> 128:9bcdf88f62b0 3092 }
<> 128:9bcdf88f62b0 3093
<> 128:9bcdf88f62b0 3094 /**
<> 128:9bcdf88f62b0 3095 * @brief Disable capture/compare 2 DMA request (CC2DE).
<> 128:9bcdf88f62b0 3096 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<> 128:9bcdf88f62b0 3097 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3098 * @retval None
<> 128:9bcdf88f62b0 3099 */
<> 128:9bcdf88f62b0 3100 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3101 {
<> 128:9bcdf88f62b0 3102 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<> 128:9bcdf88f62b0 3103 }
<> 128:9bcdf88f62b0 3104
<> 128:9bcdf88f62b0 3105 /**
<> 128:9bcdf88f62b0 3106 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<> 128:9bcdf88f62b0 3107 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<> 128:9bcdf88f62b0 3108 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3109 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3110 */
<> 128:9bcdf88f62b0 3111 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3112 {
<> 128:9bcdf88f62b0 3113 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<> 128:9bcdf88f62b0 3114 }
<> 128:9bcdf88f62b0 3115
<> 128:9bcdf88f62b0 3116 /**
<> 128:9bcdf88f62b0 3117 * @brief Enable capture/compare 3 DMA request (CC3DE).
<> 128:9bcdf88f62b0 3118 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<> 128:9bcdf88f62b0 3119 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3120 * @retval None
<> 128:9bcdf88f62b0 3121 */
<> 128:9bcdf88f62b0 3122 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3123 {
<> 128:9bcdf88f62b0 3124 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<> 128:9bcdf88f62b0 3125 }
<> 128:9bcdf88f62b0 3126
<> 128:9bcdf88f62b0 3127 /**
<> 128:9bcdf88f62b0 3128 * @brief Disable capture/compare 3 DMA request (CC3DE).
<> 128:9bcdf88f62b0 3129 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<> 128:9bcdf88f62b0 3130 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3131 * @retval None
<> 128:9bcdf88f62b0 3132 */
<> 128:9bcdf88f62b0 3133 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3134 {
<> 128:9bcdf88f62b0 3135 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<> 128:9bcdf88f62b0 3136 }
<> 128:9bcdf88f62b0 3137
<> 128:9bcdf88f62b0 3138 /**
<> 128:9bcdf88f62b0 3139 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<> 128:9bcdf88f62b0 3140 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<> 128:9bcdf88f62b0 3141 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3142 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3143 */
<> 128:9bcdf88f62b0 3144 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3145 {
<> 128:9bcdf88f62b0 3146 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<> 128:9bcdf88f62b0 3147 }
<> 128:9bcdf88f62b0 3148
<> 128:9bcdf88f62b0 3149 /**
<> 128:9bcdf88f62b0 3150 * @brief Enable capture/compare 4 DMA request (CC4DE).
<> 128:9bcdf88f62b0 3151 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<> 128:9bcdf88f62b0 3152 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3153 * @retval None
<> 128:9bcdf88f62b0 3154 */
<> 128:9bcdf88f62b0 3155 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3156 {
<> 128:9bcdf88f62b0 3157 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<> 128:9bcdf88f62b0 3158 }
<> 128:9bcdf88f62b0 3159
<> 128:9bcdf88f62b0 3160 /**
<> 128:9bcdf88f62b0 3161 * @brief Disable capture/compare 4 DMA request (CC4DE).
<> 128:9bcdf88f62b0 3162 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<> 128:9bcdf88f62b0 3163 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3164 * @retval None
<> 128:9bcdf88f62b0 3165 */
<> 128:9bcdf88f62b0 3166 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3167 {
<> 128:9bcdf88f62b0 3168 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<> 128:9bcdf88f62b0 3169 }
<> 128:9bcdf88f62b0 3170
<> 128:9bcdf88f62b0 3171 /**
<> 128:9bcdf88f62b0 3172 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<> 128:9bcdf88f62b0 3173 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<> 128:9bcdf88f62b0 3174 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3175 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3176 */
<> 128:9bcdf88f62b0 3177 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3178 {
<> 128:9bcdf88f62b0 3179 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<> 128:9bcdf88f62b0 3180 }
<> 128:9bcdf88f62b0 3181
<> 128:9bcdf88f62b0 3182 /**
<> 128:9bcdf88f62b0 3183 * @brief Enable trigger interrupt (TDE).
<> 128:9bcdf88f62b0 3184 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<> 128:9bcdf88f62b0 3185 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3186 * @retval None
<> 128:9bcdf88f62b0 3187 */
<> 128:9bcdf88f62b0 3188 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3189 {
<> 128:9bcdf88f62b0 3190 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<> 128:9bcdf88f62b0 3191 }
<> 128:9bcdf88f62b0 3192
<> 128:9bcdf88f62b0 3193 /**
<> 128:9bcdf88f62b0 3194 * @brief Disable trigger interrupt (TDE).
<> 128:9bcdf88f62b0 3195 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<> 128:9bcdf88f62b0 3196 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3197 * @retval None
<> 128:9bcdf88f62b0 3198 */
<> 128:9bcdf88f62b0 3199 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3200 {
<> 128:9bcdf88f62b0 3201 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<> 128:9bcdf88f62b0 3202 }
<> 128:9bcdf88f62b0 3203
<> 128:9bcdf88f62b0 3204 /**
<> 128:9bcdf88f62b0 3205 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
<> 128:9bcdf88f62b0 3206 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<> 128:9bcdf88f62b0 3207 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3208 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 3209 */
<> 128:9bcdf88f62b0 3210 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3211 {
<> 128:9bcdf88f62b0 3212 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<> 128:9bcdf88f62b0 3213 }
<> 128:9bcdf88f62b0 3214
<> 128:9bcdf88f62b0 3215 /**
<> 128:9bcdf88f62b0 3216 * @}
<> 128:9bcdf88f62b0 3217 */
<> 128:9bcdf88f62b0 3218
<> 128:9bcdf88f62b0 3219 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<> 128:9bcdf88f62b0 3220 * @{
<> 128:9bcdf88f62b0 3221 */
<> 128:9bcdf88f62b0 3222 /**
<> 128:9bcdf88f62b0 3223 * @brief Generate an update event.
<> 128:9bcdf88f62b0 3224 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<> 128:9bcdf88f62b0 3225 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3226 * @retval None
<> 128:9bcdf88f62b0 3227 */
<> 128:9bcdf88f62b0 3228 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3229 {
<> 128:9bcdf88f62b0 3230 SET_BIT(TIMx->EGR, TIM_EGR_UG);
<> 128:9bcdf88f62b0 3231 }
<> 128:9bcdf88f62b0 3232
<> 128:9bcdf88f62b0 3233 /**
<> 128:9bcdf88f62b0 3234 * @brief Generate Capture/Compare 1 event.
<> 128:9bcdf88f62b0 3235 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<> 128:9bcdf88f62b0 3236 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3237 * @retval None
<> 128:9bcdf88f62b0 3238 */
<> 128:9bcdf88f62b0 3239 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3240 {
<> 128:9bcdf88f62b0 3241 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<> 128:9bcdf88f62b0 3242 }
<> 128:9bcdf88f62b0 3243
<> 128:9bcdf88f62b0 3244 /**
<> 128:9bcdf88f62b0 3245 * @brief Generate Capture/Compare 2 event.
<> 128:9bcdf88f62b0 3246 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<> 128:9bcdf88f62b0 3247 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3248 * @retval None
<> 128:9bcdf88f62b0 3249 */
<> 128:9bcdf88f62b0 3250 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3251 {
<> 128:9bcdf88f62b0 3252 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<> 128:9bcdf88f62b0 3253 }
<> 128:9bcdf88f62b0 3254
<> 128:9bcdf88f62b0 3255 /**
<> 128:9bcdf88f62b0 3256 * @brief Generate Capture/Compare 3 event.
<> 128:9bcdf88f62b0 3257 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<> 128:9bcdf88f62b0 3258 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3259 * @retval None
<> 128:9bcdf88f62b0 3260 */
<> 128:9bcdf88f62b0 3261 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3262 {
<> 128:9bcdf88f62b0 3263 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<> 128:9bcdf88f62b0 3264 }
<> 128:9bcdf88f62b0 3265
<> 128:9bcdf88f62b0 3266 /**
<> 128:9bcdf88f62b0 3267 * @brief Generate Capture/Compare 4 event.
<> 128:9bcdf88f62b0 3268 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<> 128:9bcdf88f62b0 3269 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3270 * @retval None
<> 128:9bcdf88f62b0 3271 */
<> 128:9bcdf88f62b0 3272 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3273 {
<> 128:9bcdf88f62b0 3274 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<> 128:9bcdf88f62b0 3275 }
<> 128:9bcdf88f62b0 3276
<> 128:9bcdf88f62b0 3277 /**
<> 128:9bcdf88f62b0 3278 * @brief Generate trigger event.
<> 128:9bcdf88f62b0 3279 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<> 128:9bcdf88f62b0 3280 * @param TIMx Timer instance
<> 128:9bcdf88f62b0 3281 * @retval None
<> 128:9bcdf88f62b0 3282 */
<> 128:9bcdf88f62b0 3283 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<> 128:9bcdf88f62b0 3284 {
<> 128:9bcdf88f62b0 3285 SET_BIT(TIMx->EGR, TIM_EGR_TG);
<> 128:9bcdf88f62b0 3286 }
<> 128:9bcdf88f62b0 3287
<> 128:9bcdf88f62b0 3288 /**
<> 128:9bcdf88f62b0 3289 * @}
<> 128:9bcdf88f62b0 3290 */
<> 128:9bcdf88f62b0 3291
<> 128:9bcdf88f62b0 3292 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 3293 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<> 128:9bcdf88f62b0 3294 * @{
<> 128:9bcdf88f62b0 3295 */
<> 128:9bcdf88f62b0 3296
<> 128:9bcdf88f62b0 3297 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<> 128:9bcdf88f62b0 3298 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<> 128:9bcdf88f62b0 3299 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
<> 128:9bcdf88f62b0 3300 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<> 128:9bcdf88f62b0 3301 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<> 128:9bcdf88f62b0 3302 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<> 128:9bcdf88f62b0 3303 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
<> 128:9bcdf88f62b0 3304 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<> 128:9bcdf88f62b0 3305 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<> 128:9bcdf88f62b0 3306 /**
<> 128:9bcdf88f62b0 3307 * @}
<> 128:9bcdf88f62b0 3308 */
<> 128:9bcdf88f62b0 3309 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 3310
<> 128:9bcdf88f62b0 3311 /**
<> 128:9bcdf88f62b0 3312 * @}
<> 128:9bcdf88f62b0 3313 */
<> 128:9bcdf88f62b0 3314
<> 128:9bcdf88f62b0 3315 /**
<> 128:9bcdf88f62b0 3316 * @}
<> 128:9bcdf88f62b0 3317 */
<> 128:9bcdf88f62b0 3318
<> 128:9bcdf88f62b0 3319 #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
<> 128:9bcdf88f62b0 3320
<> 128:9bcdf88f62b0 3321 /**
<> 128:9bcdf88f62b0 3322 * @}
<> 128:9bcdf88f62b0 3323 */
<> 128:9bcdf88f62b0 3324
<> 128:9bcdf88f62b0 3325 #ifdef __cplusplus
<> 128:9bcdf88f62b0 3326 }
<> 128:9bcdf88f62b0 3327 #endif
<> 128:9bcdf88f62b0 3328
<> 128:9bcdf88f62b0 3329 #endif /* __STM32L1xx_LL_TIM_H */
<> 128:9bcdf88f62b0 3330
<> 128:9bcdf88f62b0 3331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/