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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_ll_spi.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of SPI LL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_LL_SPI_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_LL_SPI_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_LL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @defgroup SPI_LL SPI
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /* Private types -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 60 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 61 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 64 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<> 128:9bcdf88f62b0 66 * @{
<> 128:9bcdf88f62b0 67 */
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69 /**
<> 128:9bcdf88f62b0 70 * @brief SPI Init structures definition
<> 128:9bcdf88f62b0 71 */
<> 128:9bcdf88f62b0 72 typedef struct
<> 128:9bcdf88f62b0 73 {
<> 128:9bcdf88f62b0 74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<> 128:9bcdf88f62b0 75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<> 128:9bcdf88f62b0 80 This parameter can be a value of @ref SPI_LL_EC_MODE.
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 uint32_t DataWidth; /*!< Specifies the SPI data width.
<> 128:9bcdf88f62b0 85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<> 128:9bcdf88f62b0 90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<> 128:9bcdf88f62b0 95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<> 128:9bcdf88f62b0 98
<> 128:9bcdf88f62b0 99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<> 128:9bcdf88f62b0 100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<> 128:9bcdf88f62b0 105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<> 128:9bcdf88f62b0 106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<> 128:9bcdf88f62b0 109
<> 128:9bcdf88f62b0 110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 128:9bcdf88f62b0 111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 128:9bcdf88f62b0 116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<> 128:9bcdf88f62b0 121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 } LL_SPI_InitTypeDef;
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 /**
<> 128:9bcdf88f62b0 128 * @}
<> 128:9bcdf88f62b0 129 */
<> 128:9bcdf88f62b0 130 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<> 128:9bcdf88f62b0 134 * @{
<> 128:9bcdf88f62b0 135 */
<> 128:9bcdf88f62b0 136
<> 128:9bcdf88f62b0 137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<> 128:9bcdf88f62b0 138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
<> 128:9bcdf88f62b0 139 * @{
<> 128:9bcdf88f62b0 140 */
<> 128:9bcdf88f62b0 141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
<> 128:9bcdf88f62b0 142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
<> 128:9bcdf88f62b0 143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
<> 128:9bcdf88f62b0 144 #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */
<> 128:9bcdf88f62b0 145 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
<> 128:9bcdf88f62b0 146 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
<> 128:9bcdf88f62b0 147 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
<> 128:9bcdf88f62b0 148 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
<> 128:9bcdf88f62b0 149 /**
<> 128:9bcdf88f62b0 150 * @}
<> 128:9bcdf88f62b0 151 */
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /** @defgroup SPI_LL_EC_IT IT Defines
<> 128:9bcdf88f62b0 154 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<> 128:9bcdf88f62b0 155 * @{
<> 128:9bcdf88f62b0 156 */
<> 128:9bcdf88f62b0 157 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
<> 128:9bcdf88f62b0 158 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
<> 128:9bcdf88f62b0 159 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
<> 128:9bcdf88f62b0 160 /**
<> 128:9bcdf88f62b0 161 * @}
<> 128:9bcdf88f62b0 162 */
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** @defgroup SPI_LL_EC_MODE Operation Mode
<> 128:9bcdf88f62b0 165 * @{
<> 128:9bcdf88f62b0 166 */
<> 128:9bcdf88f62b0 167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
<> 128:9bcdf88f62b0 168 #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */
<> 128:9bcdf88f62b0 169 /**
<> 128:9bcdf88f62b0 170 * @}
<> 128:9bcdf88f62b0 171 */
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 #if defined (SPI_CR2_FRF)
<> 128:9bcdf88f62b0 174 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<> 128:9bcdf88f62b0 175 * @{
<> 128:9bcdf88f62b0 176 */
<> 128:9bcdf88f62b0 177 #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */
<> 128:9bcdf88f62b0 178 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @}
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182 #endif /* SPI_CR2_FRF */
<> 128:9bcdf88f62b0 183
<> 128:9bcdf88f62b0 184 /** @defgroup SPI_LL_EC_PHASE Clock Phase
<> 128:9bcdf88f62b0 185 * @{
<> 128:9bcdf88f62b0 186 */
<> 128:9bcdf88f62b0 187 #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */
<> 128:9bcdf88f62b0 188 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
<> 128:9bcdf88f62b0 189 /**
<> 128:9bcdf88f62b0 190 * @}
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<> 128:9bcdf88f62b0 194 * @{
<> 128:9bcdf88f62b0 195 */
<> 128:9bcdf88f62b0 196 #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */
<> 128:9bcdf88f62b0 197 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
<> 128:9bcdf88f62b0 198 /**
<> 128:9bcdf88f62b0 199 * @}
<> 128:9bcdf88f62b0 200 */
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<> 128:9bcdf88f62b0 203 * @{
<> 128:9bcdf88f62b0 204 */
<> 128:9bcdf88f62b0 205 #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */
<> 128:9bcdf88f62b0 206 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
<> 128:9bcdf88f62b0 207 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
<> 128:9bcdf88f62b0 208 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
<> 128:9bcdf88f62b0 209 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
<> 128:9bcdf88f62b0 210 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
<> 128:9bcdf88f62b0 211 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
<> 128:9bcdf88f62b0 212 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
<> 128:9bcdf88f62b0 213 /**
<> 128:9bcdf88f62b0 214 * @}
<> 128:9bcdf88f62b0 215 */
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<> 128:9bcdf88f62b0 218 * @{
<> 128:9bcdf88f62b0 219 */
<> 128:9bcdf88f62b0 220 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
<> 128:9bcdf88f62b0 221 #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */
<> 128:9bcdf88f62b0 222 /**
<> 128:9bcdf88f62b0 223 * @}
<> 128:9bcdf88f62b0 224 */
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<> 128:9bcdf88f62b0 227 * @{
<> 128:9bcdf88f62b0 228 */
<> 128:9bcdf88f62b0 229 #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
<> 128:9bcdf88f62b0 230 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
<> 128:9bcdf88f62b0 231 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
<> 128:9bcdf88f62b0 232 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
<> 128:9bcdf88f62b0 233 /**
<> 128:9bcdf88f62b0 234 * @}
<> 128:9bcdf88f62b0 235 */
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<> 128:9bcdf88f62b0 238 * @{
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
<> 128:9bcdf88f62b0 241 #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */
<> 128:9bcdf88f62b0 242 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
<> 128:9bcdf88f62b0 243 /**
<> 128:9bcdf88f62b0 244 * @}
<> 128:9bcdf88f62b0 245 */
<> 128:9bcdf88f62b0 246
<> 128:9bcdf88f62b0 247 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<> 128:9bcdf88f62b0 248 * @{
<> 128:9bcdf88f62b0 249 */
<> 128:9bcdf88f62b0 250 #define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /*!< Data length for SPI transfer: 8 bits */
<> 128:9bcdf88f62b0 251 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
<> 128:9bcdf88f62b0 252 /**
<> 128:9bcdf88f62b0 253 * @}
<> 128:9bcdf88f62b0 254 */
<> 128:9bcdf88f62b0 255 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 256
<> 128:9bcdf88f62b0 257 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<> 128:9bcdf88f62b0 258 * @{
<> 128:9bcdf88f62b0 259 */
<> 128:9bcdf88f62b0 260 #define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */
<> 128:9bcdf88f62b0 261 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
<> 128:9bcdf88f62b0 262 /**
<> 128:9bcdf88f62b0 263 * @}
<> 128:9bcdf88f62b0 264 */
<> 128:9bcdf88f62b0 265 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 266
<> 128:9bcdf88f62b0 267 /**
<> 128:9bcdf88f62b0 268 * @}
<> 128:9bcdf88f62b0 269 */
<> 128:9bcdf88f62b0 270
<> 128:9bcdf88f62b0 271 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 272 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<> 128:9bcdf88f62b0 273 * @{
<> 128:9bcdf88f62b0 274 */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<> 128:9bcdf88f62b0 277 * @{
<> 128:9bcdf88f62b0 278 */
<> 128:9bcdf88f62b0 279
<> 128:9bcdf88f62b0 280 /**
<> 128:9bcdf88f62b0 281 * @brief Write a value in SPI register
<> 128:9bcdf88f62b0 282 * @param __INSTANCE__ SPI Instance
<> 128:9bcdf88f62b0 283 * @param __REG__ Register to be written
<> 128:9bcdf88f62b0 284 * @param __VALUE__ Value to be written in the register
<> 128:9bcdf88f62b0 285 * @retval None
<> 128:9bcdf88f62b0 286 */
<> 128:9bcdf88f62b0 287 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 /**
<> 128:9bcdf88f62b0 290 * @brief Read a value in SPI register
<> 128:9bcdf88f62b0 291 * @param __INSTANCE__ SPI Instance
<> 128:9bcdf88f62b0 292 * @param __REG__ Register to be read
<> 128:9bcdf88f62b0 293 * @retval Register value
<> 128:9bcdf88f62b0 294 */
<> 128:9bcdf88f62b0 295 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 128:9bcdf88f62b0 296 /**
<> 128:9bcdf88f62b0 297 * @}
<> 128:9bcdf88f62b0 298 */
<> 128:9bcdf88f62b0 299
<> 128:9bcdf88f62b0 300 /**
<> 128:9bcdf88f62b0 301 * @}
<> 128:9bcdf88f62b0 302 */
<> 128:9bcdf88f62b0 303
<> 128:9bcdf88f62b0 304 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 305 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<> 128:9bcdf88f62b0 306 * @{
<> 128:9bcdf88f62b0 307 */
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 /** @defgroup SPI_LL_EF_Configuration Configuration
<> 128:9bcdf88f62b0 310 * @{
<> 128:9bcdf88f62b0 311 */
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /**
<> 128:9bcdf88f62b0 314 * @brief Enable SPI peripheral
<> 128:9bcdf88f62b0 315 * @rmtoll CR1 SPE LL_SPI_Enable
<> 128:9bcdf88f62b0 316 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 317 * @retval None
<> 128:9bcdf88f62b0 318 */
<> 128:9bcdf88f62b0 319 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 320 {
<> 128:9bcdf88f62b0 321 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 128:9bcdf88f62b0 322 }
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324 /**
<> 128:9bcdf88f62b0 325 * @brief Disable SPI peripheral
<> 128:9bcdf88f62b0 326 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
<> 128:9bcdf88f62b0 327 * @rmtoll CR1 SPE LL_SPI_Disable
<> 128:9bcdf88f62b0 328 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 329 * @retval None
<> 128:9bcdf88f62b0 330 */
<> 128:9bcdf88f62b0 331 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 332 {
<> 128:9bcdf88f62b0 333 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 128:9bcdf88f62b0 334 }
<> 128:9bcdf88f62b0 335
<> 128:9bcdf88f62b0 336 /**
<> 128:9bcdf88f62b0 337 * @brief Check if SPI peripheral is enabled
<> 128:9bcdf88f62b0 338 * @rmtoll CR1 SPE LL_SPI_IsEnabled
<> 128:9bcdf88f62b0 339 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 340 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 341 */
<> 128:9bcdf88f62b0 342 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 343 {
<> 128:9bcdf88f62b0 344 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<> 128:9bcdf88f62b0 345 }
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 /**
<> 128:9bcdf88f62b0 348 * @brief Set SPI operation mode to Master or Slave
<> 128:9bcdf88f62b0 349 * @note This bit should not be changed when communication is ongoing.
<> 128:9bcdf88f62b0 350 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
<> 128:9bcdf88f62b0 351 * CR1 SSI LL_SPI_SetMode
<> 128:9bcdf88f62b0 352 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 353 * @param Mode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 354 * @arg @ref LL_SPI_MODE_MASTER
<> 128:9bcdf88f62b0 355 * @arg @ref LL_SPI_MODE_SLAVE
<> 128:9bcdf88f62b0 356 * @retval None
<> 128:9bcdf88f62b0 357 */
<> 128:9bcdf88f62b0 358 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<> 128:9bcdf88f62b0 359 {
<> 128:9bcdf88f62b0 360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
<> 128:9bcdf88f62b0 361 }
<> 128:9bcdf88f62b0 362
<> 128:9bcdf88f62b0 363 /**
<> 128:9bcdf88f62b0 364 * @brief Get SPI operation mode (Master or Slave)
<> 128:9bcdf88f62b0 365 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
<> 128:9bcdf88f62b0 366 * CR1 SSI LL_SPI_GetMode
<> 128:9bcdf88f62b0 367 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 368 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 369 * @arg @ref LL_SPI_MODE_MASTER
<> 128:9bcdf88f62b0 370 * @arg @ref LL_SPI_MODE_SLAVE
<> 128:9bcdf88f62b0 371 */
<> 128:9bcdf88f62b0 372 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 373 {
<> 128:9bcdf88f62b0 374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
<> 128:9bcdf88f62b0 375 }
<> 128:9bcdf88f62b0 376
<> 128:9bcdf88f62b0 377 #if defined (SPI_CR2_FRF)
<> 128:9bcdf88f62b0 378 /**
<> 128:9bcdf88f62b0 379 * @brief Set serial protocol used
<> 128:9bcdf88f62b0 380 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 128:9bcdf88f62b0 381 * @rmtoll CR2 FRF LL_SPI_SetStandard
<> 128:9bcdf88f62b0 382 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 383 * @param Standard This parameter can be one of the following values:
<> 128:9bcdf88f62b0 384 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<> 128:9bcdf88f62b0 385 * @arg @ref LL_SPI_PROTOCOL_TI
<> 128:9bcdf88f62b0 386 * @retval None
<> 128:9bcdf88f62b0 387 */
<> 128:9bcdf88f62b0 388 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<> 128:9bcdf88f62b0 389 {
<> 128:9bcdf88f62b0 390 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<> 128:9bcdf88f62b0 391 }
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /**
<> 128:9bcdf88f62b0 394 * @brief Get serial protocol used
<> 128:9bcdf88f62b0 395 * @rmtoll CR2 FRF LL_SPI_GetStandard
<> 128:9bcdf88f62b0 396 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 397 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 398 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<> 128:9bcdf88f62b0 399 * @arg @ref LL_SPI_PROTOCOL_TI
<> 128:9bcdf88f62b0 400 */
<> 128:9bcdf88f62b0 401 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 402 {
<> 128:9bcdf88f62b0 403 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<> 128:9bcdf88f62b0 404 }
<> 128:9bcdf88f62b0 405 #endif /* SPI_CR2_FRF */
<> 128:9bcdf88f62b0 406
<> 128:9bcdf88f62b0 407 /**
<> 128:9bcdf88f62b0 408 * @brief Set clock phase
<> 128:9bcdf88f62b0 409 * @note This bit should not be changed when communication is ongoing.
<> 128:9bcdf88f62b0 410 * This bit is not used in SPI TI mode.
<> 128:9bcdf88f62b0 411 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<> 128:9bcdf88f62b0 412 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 413 * @param ClockPhase This parameter can be one of the following values:
<> 128:9bcdf88f62b0 414 * @arg @ref LL_SPI_PHASE_1EDGE
<> 128:9bcdf88f62b0 415 * @arg @ref LL_SPI_PHASE_2EDGE
<> 128:9bcdf88f62b0 416 * @retval None
<> 128:9bcdf88f62b0 417 */
<> 128:9bcdf88f62b0 418 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<> 128:9bcdf88f62b0 419 {
<> 128:9bcdf88f62b0 420 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<> 128:9bcdf88f62b0 421 }
<> 128:9bcdf88f62b0 422
<> 128:9bcdf88f62b0 423 /**
<> 128:9bcdf88f62b0 424 * @brief Get clock phase
<> 128:9bcdf88f62b0 425 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<> 128:9bcdf88f62b0 426 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 427 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 428 * @arg @ref LL_SPI_PHASE_1EDGE
<> 128:9bcdf88f62b0 429 * @arg @ref LL_SPI_PHASE_2EDGE
<> 128:9bcdf88f62b0 430 */
<> 128:9bcdf88f62b0 431 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 432 {
<> 128:9bcdf88f62b0 433 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<> 128:9bcdf88f62b0 434 }
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 /**
<> 128:9bcdf88f62b0 437 * @brief Set clock polarity
<> 128:9bcdf88f62b0 438 * @note This bit should not be changed when communication is ongoing.
<> 128:9bcdf88f62b0 439 * This bit is not used in SPI TI mode.
<> 128:9bcdf88f62b0 440 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<> 128:9bcdf88f62b0 441 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 442 * @param ClockPolarity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 443 * @arg @ref LL_SPI_POLARITY_LOW
<> 128:9bcdf88f62b0 444 * @arg @ref LL_SPI_POLARITY_HIGH
<> 128:9bcdf88f62b0 445 * @retval None
<> 128:9bcdf88f62b0 446 */
<> 128:9bcdf88f62b0 447 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<> 128:9bcdf88f62b0 448 {
<> 128:9bcdf88f62b0 449 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<> 128:9bcdf88f62b0 450 }
<> 128:9bcdf88f62b0 451
<> 128:9bcdf88f62b0 452 /**
<> 128:9bcdf88f62b0 453 * @brief Get clock polarity
<> 128:9bcdf88f62b0 454 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<> 128:9bcdf88f62b0 455 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 456 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 457 * @arg @ref LL_SPI_POLARITY_LOW
<> 128:9bcdf88f62b0 458 * @arg @ref LL_SPI_POLARITY_HIGH
<> 128:9bcdf88f62b0 459 */
<> 128:9bcdf88f62b0 460 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 461 {
<> 128:9bcdf88f62b0 462 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<> 128:9bcdf88f62b0 463 }
<> 128:9bcdf88f62b0 464
<> 128:9bcdf88f62b0 465 /**
<> 128:9bcdf88f62b0 466 * @brief Set baud rate prescaler
<> 128:9bcdf88f62b0 467 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<> 128:9bcdf88f62b0 468 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<> 128:9bcdf88f62b0 469 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 470 * @param BaudRate This parameter can be one of the following values:
<> 128:9bcdf88f62b0 471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<> 128:9bcdf88f62b0 472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<> 128:9bcdf88f62b0 473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<> 128:9bcdf88f62b0 474 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<> 128:9bcdf88f62b0 475 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<> 128:9bcdf88f62b0 476 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<> 128:9bcdf88f62b0 477 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<> 128:9bcdf88f62b0 478 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<> 128:9bcdf88f62b0 479 * @retval None
<> 128:9bcdf88f62b0 480 */
<> 128:9bcdf88f62b0 481 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<> 128:9bcdf88f62b0 482 {
<> 128:9bcdf88f62b0 483 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<> 128:9bcdf88f62b0 484 }
<> 128:9bcdf88f62b0 485
<> 128:9bcdf88f62b0 486 /**
<> 128:9bcdf88f62b0 487 * @brief Get baud rate prescaler
<> 128:9bcdf88f62b0 488 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<> 128:9bcdf88f62b0 489 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 490 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<> 128:9bcdf88f62b0 492 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<> 128:9bcdf88f62b0 493 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<> 128:9bcdf88f62b0 494 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<> 128:9bcdf88f62b0 495 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<> 128:9bcdf88f62b0 496 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<> 128:9bcdf88f62b0 497 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<> 128:9bcdf88f62b0 498 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<> 128:9bcdf88f62b0 499 */
<> 128:9bcdf88f62b0 500 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 501 {
<> 128:9bcdf88f62b0 502 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<> 128:9bcdf88f62b0 503 }
<> 128:9bcdf88f62b0 504
<> 128:9bcdf88f62b0 505 /**
<> 128:9bcdf88f62b0 506 * @brief Set transfer bit order
<> 128:9bcdf88f62b0 507 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<> 128:9bcdf88f62b0 508 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<> 128:9bcdf88f62b0 509 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 510 * @param BitOrder This parameter can be one of the following values:
<> 128:9bcdf88f62b0 511 * @arg @ref LL_SPI_LSB_FIRST
<> 128:9bcdf88f62b0 512 * @arg @ref LL_SPI_MSB_FIRST
<> 128:9bcdf88f62b0 513 * @retval None
<> 128:9bcdf88f62b0 514 */
<> 128:9bcdf88f62b0 515 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<> 128:9bcdf88f62b0 516 {
<> 128:9bcdf88f62b0 517 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<> 128:9bcdf88f62b0 518 }
<> 128:9bcdf88f62b0 519
<> 128:9bcdf88f62b0 520 /**
<> 128:9bcdf88f62b0 521 * @brief Get transfer bit order
<> 128:9bcdf88f62b0 522 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<> 128:9bcdf88f62b0 523 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 524 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 525 * @arg @ref LL_SPI_LSB_FIRST
<> 128:9bcdf88f62b0 526 * @arg @ref LL_SPI_MSB_FIRST
<> 128:9bcdf88f62b0 527 */
<> 128:9bcdf88f62b0 528 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 529 {
<> 128:9bcdf88f62b0 530 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<> 128:9bcdf88f62b0 531 }
<> 128:9bcdf88f62b0 532
<> 128:9bcdf88f62b0 533 /**
<> 128:9bcdf88f62b0 534 * @brief Set transfer direction mode
<> 128:9bcdf88f62b0 535 * @note For Half-Duplex mode, Rx Direction is set by default.
<> 128:9bcdf88f62b0 536 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<> 128:9bcdf88f62b0 537 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<> 128:9bcdf88f62b0 538 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<> 128:9bcdf88f62b0 539 * CR1 BIDIOE LL_SPI_SetTransferDirection
<> 128:9bcdf88f62b0 540 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 541 * @param TransferDirection This parameter can be one of the following values:
<> 128:9bcdf88f62b0 542 * @arg @ref LL_SPI_FULL_DUPLEX
<> 128:9bcdf88f62b0 543 * @arg @ref LL_SPI_SIMPLEX_RX
<> 128:9bcdf88f62b0 544 * @arg @ref LL_SPI_HALF_DUPLEX_RX
<> 128:9bcdf88f62b0 545 * @arg @ref LL_SPI_HALF_DUPLEX_TX
<> 128:9bcdf88f62b0 546 * @retval None
<> 128:9bcdf88f62b0 547 */
<> 128:9bcdf88f62b0 548 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<> 128:9bcdf88f62b0 549 {
<> 128:9bcdf88f62b0 550 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
<> 128:9bcdf88f62b0 551 }
<> 128:9bcdf88f62b0 552
<> 128:9bcdf88f62b0 553 /**
<> 128:9bcdf88f62b0 554 * @brief Get transfer direction mode
<> 128:9bcdf88f62b0 555 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<> 128:9bcdf88f62b0 556 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<> 128:9bcdf88f62b0 557 * CR1 BIDIOE LL_SPI_GetTransferDirection
<> 128:9bcdf88f62b0 558 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 559 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 560 * @arg @ref LL_SPI_FULL_DUPLEX
<> 128:9bcdf88f62b0 561 * @arg @ref LL_SPI_SIMPLEX_RX
<> 128:9bcdf88f62b0 562 * @arg @ref LL_SPI_HALF_DUPLEX_RX
<> 128:9bcdf88f62b0 563 * @arg @ref LL_SPI_HALF_DUPLEX_TX
<> 128:9bcdf88f62b0 564 */
<> 128:9bcdf88f62b0 565 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 566 {
<> 128:9bcdf88f62b0 567 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
<> 128:9bcdf88f62b0 568 }
<> 128:9bcdf88f62b0 569
<> 128:9bcdf88f62b0 570 /**
<> 128:9bcdf88f62b0 571 * @brief Set frame data width
<> 128:9bcdf88f62b0 572 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
<> 128:9bcdf88f62b0 573 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 574 * @param DataWidth This parameter can be one of the following values:
<> 128:9bcdf88f62b0 575 * @arg @ref LL_SPI_DATAWIDTH_8BIT
<> 128:9bcdf88f62b0 576 * @arg @ref LL_SPI_DATAWIDTH_16BIT
<> 128:9bcdf88f62b0 577 * @retval None
<> 128:9bcdf88f62b0 578 */
<> 128:9bcdf88f62b0 579 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<> 128:9bcdf88f62b0 580 {
<> 128:9bcdf88f62b0 581 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
<> 128:9bcdf88f62b0 582 }
<> 128:9bcdf88f62b0 583
<> 128:9bcdf88f62b0 584 /**
<> 128:9bcdf88f62b0 585 * @brief Get frame data width
<> 128:9bcdf88f62b0 586 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
<> 128:9bcdf88f62b0 587 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 588 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 589 * @arg @ref LL_SPI_DATAWIDTH_8BIT
<> 128:9bcdf88f62b0 590 * @arg @ref LL_SPI_DATAWIDTH_16BIT
<> 128:9bcdf88f62b0 591 */
<> 128:9bcdf88f62b0 592 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 593 {
<> 128:9bcdf88f62b0 594 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
<> 128:9bcdf88f62b0 595 }
<> 128:9bcdf88f62b0 596
<> 128:9bcdf88f62b0 597 /**
<> 128:9bcdf88f62b0 598 * @}
<> 128:9bcdf88f62b0 599 */
<> 128:9bcdf88f62b0 600
<> 128:9bcdf88f62b0 601 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
<> 128:9bcdf88f62b0 602 * @{
<> 128:9bcdf88f62b0 603 */
<> 128:9bcdf88f62b0 604
<> 128:9bcdf88f62b0 605 /**
<> 128:9bcdf88f62b0 606 * @brief Enable CRC
<> 128:9bcdf88f62b0 607 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 128:9bcdf88f62b0 608 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<> 128:9bcdf88f62b0 609 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 610 * @retval None
<> 128:9bcdf88f62b0 611 */
<> 128:9bcdf88f62b0 612 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 613 {
<> 128:9bcdf88f62b0 614 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<> 128:9bcdf88f62b0 615 }
<> 128:9bcdf88f62b0 616
<> 128:9bcdf88f62b0 617 /**
<> 128:9bcdf88f62b0 618 * @brief Disable CRC
<> 128:9bcdf88f62b0 619 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 128:9bcdf88f62b0 620 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<> 128:9bcdf88f62b0 621 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 622 * @retval None
<> 128:9bcdf88f62b0 623 */
<> 128:9bcdf88f62b0 624 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 625 {
<> 128:9bcdf88f62b0 626 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<> 128:9bcdf88f62b0 627 }
<> 128:9bcdf88f62b0 628
<> 128:9bcdf88f62b0 629 /**
<> 128:9bcdf88f62b0 630 * @brief Check if CRC is enabled
<> 128:9bcdf88f62b0 631 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 128:9bcdf88f62b0 632 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<> 128:9bcdf88f62b0 633 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 634 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 635 */
<> 128:9bcdf88f62b0 636 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 637 {
<> 128:9bcdf88f62b0 638 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<> 128:9bcdf88f62b0 639 }
<> 128:9bcdf88f62b0 640
<> 128:9bcdf88f62b0 641 /**
<> 128:9bcdf88f62b0 642 * @brief Set CRCNext to transfer CRC on the line
<> 128:9bcdf88f62b0 643 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<> 128:9bcdf88f62b0 644 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<> 128:9bcdf88f62b0 645 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 646 * @retval None
<> 128:9bcdf88f62b0 647 */
<> 128:9bcdf88f62b0 648 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 649 {
<> 128:9bcdf88f62b0 650 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<> 128:9bcdf88f62b0 651 }
<> 128:9bcdf88f62b0 652
<> 128:9bcdf88f62b0 653 /**
<> 128:9bcdf88f62b0 654 * @brief Set polynomial for CRC calculation
<> 128:9bcdf88f62b0 655 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<> 128:9bcdf88f62b0 656 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 657 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 128:9bcdf88f62b0 658 * @retval None
<> 128:9bcdf88f62b0 659 */
<> 128:9bcdf88f62b0 660 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<> 128:9bcdf88f62b0 661 {
<> 128:9bcdf88f62b0 662 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<> 128:9bcdf88f62b0 663 }
<> 128:9bcdf88f62b0 664
<> 128:9bcdf88f62b0 665 /**
<> 128:9bcdf88f62b0 666 * @brief Get polynomial for CRC calculation
<> 128:9bcdf88f62b0 667 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<> 128:9bcdf88f62b0 668 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 669 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 128:9bcdf88f62b0 670 */
<> 128:9bcdf88f62b0 671 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 672 {
<> 128:9bcdf88f62b0 673 return (uint32_t)(READ_REG(SPIx->CRCPR));
<> 128:9bcdf88f62b0 674 }
<> 128:9bcdf88f62b0 675
<> 128:9bcdf88f62b0 676 /**
<> 128:9bcdf88f62b0 677 * @brief Get Rx CRC
<> 128:9bcdf88f62b0 678 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<> 128:9bcdf88f62b0 679 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 680 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 128:9bcdf88f62b0 681 */
<> 128:9bcdf88f62b0 682 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 683 {
<> 128:9bcdf88f62b0 684 return (uint32_t)(READ_REG(SPIx->RXCRCR));
<> 128:9bcdf88f62b0 685 }
<> 128:9bcdf88f62b0 686
<> 128:9bcdf88f62b0 687 /**
<> 128:9bcdf88f62b0 688 * @brief Get Tx CRC
<> 128:9bcdf88f62b0 689 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<> 128:9bcdf88f62b0 690 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 691 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 128:9bcdf88f62b0 692 */
<> 128:9bcdf88f62b0 693 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 694 {
<> 128:9bcdf88f62b0 695 return (uint32_t)(READ_REG(SPIx->TXCRCR));
<> 128:9bcdf88f62b0 696 }
<> 128:9bcdf88f62b0 697
<> 128:9bcdf88f62b0 698 /**
<> 128:9bcdf88f62b0 699 * @}
<> 128:9bcdf88f62b0 700 */
<> 128:9bcdf88f62b0 701
<> 128:9bcdf88f62b0 702 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<> 128:9bcdf88f62b0 703 * @{
<> 128:9bcdf88f62b0 704 */
<> 128:9bcdf88f62b0 705
<> 128:9bcdf88f62b0 706 /**
<> 128:9bcdf88f62b0 707 * @brief Set NSS mode
<> 128:9bcdf88f62b0 708 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<> 128:9bcdf88f62b0 709 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<> 128:9bcdf88f62b0 710 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<> 128:9bcdf88f62b0 711 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 712 * @param NSS This parameter can be one of the following values:
<> 128:9bcdf88f62b0 713 * @arg @ref LL_SPI_NSS_SOFT
<> 128:9bcdf88f62b0 714 * @arg @ref LL_SPI_NSS_HARD_INPUT
<> 128:9bcdf88f62b0 715 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
<> 128:9bcdf88f62b0 716 * @retval None
<> 128:9bcdf88f62b0 717 */
<> 128:9bcdf88f62b0 718 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<> 128:9bcdf88f62b0 719 {
<> 128:9bcdf88f62b0 720 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<> 128:9bcdf88f62b0 721 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<> 128:9bcdf88f62b0 722 }
<> 128:9bcdf88f62b0 723
<> 128:9bcdf88f62b0 724 /**
<> 128:9bcdf88f62b0 725 * @brief Get NSS mode
<> 128:9bcdf88f62b0 726 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<> 128:9bcdf88f62b0 727 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<> 128:9bcdf88f62b0 728 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 729 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 730 * @arg @ref LL_SPI_NSS_SOFT
<> 128:9bcdf88f62b0 731 * @arg @ref LL_SPI_NSS_HARD_INPUT
<> 128:9bcdf88f62b0 732 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
<> 128:9bcdf88f62b0 733 */
<> 128:9bcdf88f62b0 734 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 735 {
<> 128:9bcdf88f62b0 736 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<> 128:9bcdf88f62b0 737 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<> 128:9bcdf88f62b0 738 return (Ssm | Ssoe);
<> 128:9bcdf88f62b0 739 }
<> 128:9bcdf88f62b0 740
<> 128:9bcdf88f62b0 741 /**
<> 128:9bcdf88f62b0 742 * @}
<> 128:9bcdf88f62b0 743 */
<> 128:9bcdf88f62b0 744
<> 128:9bcdf88f62b0 745 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<> 128:9bcdf88f62b0 746 * @{
<> 128:9bcdf88f62b0 747 */
<> 128:9bcdf88f62b0 748
<> 128:9bcdf88f62b0 749 /**
<> 128:9bcdf88f62b0 750 * @brief Check if Rx buffer is not empty
<> 128:9bcdf88f62b0 751 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<> 128:9bcdf88f62b0 752 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 753 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 754 */
<> 128:9bcdf88f62b0 755 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 756 {
<> 128:9bcdf88f62b0 757 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<> 128:9bcdf88f62b0 758 }
<> 128:9bcdf88f62b0 759
<> 128:9bcdf88f62b0 760 /**
<> 128:9bcdf88f62b0 761 * @brief Check if Tx buffer is empty
<> 128:9bcdf88f62b0 762 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<> 128:9bcdf88f62b0 763 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 764 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 765 */
<> 128:9bcdf88f62b0 766 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 767 {
<> 128:9bcdf88f62b0 768 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<> 128:9bcdf88f62b0 769 }
<> 128:9bcdf88f62b0 770
<> 128:9bcdf88f62b0 771 /**
<> 128:9bcdf88f62b0 772 * @brief Get CRC error flag
<> 128:9bcdf88f62b0 773 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<> 128:9bcdf88f62b0 774 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 775 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 776 */
<> 128:9bcdf88f62b0 777 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 778 {
<> 128:9bcdf88f62b0 779 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<> 128:9bcdf88f62b0 780 }
<> 128:9bcdf88f62b0 781
<> 128:9bcdf88f62b0 782 /**
<> 128:9bcdf88f62b0 783 * @brief Get mode fault error flag
<> 128:9bcdf88f62b0 784 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<> 128:9bcdf88f62b0 785 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 786 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 787 */
<> 128:9bcdf88f62b0 788 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 789 {
<> 128:9bcdf88f62b0 790 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<> 128:9bcdf88f62b0 791 }
<> 128:9bcdf88f62b0 792
<> 128:9bcdf88f62b0 793 /**
<> 128:9bcdf88f62b0 794 * @brief Get overrun error flag
<> 128:9bcdf88f62b0 795 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<> 128:9bcdf88f62b0 796 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 797 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 798 */
<> 128:9bcdf88f62b0 799 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 800 {
<> 128:9bcdf88f62b0 801 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<> 128:9bcdf88f62b0 802 }
<> 128:9bcdf88f62b0 803
<> 128:9bcdf88f62b0 804 /**
<> 128:9bcdf88f62b0 805 * @brief Get busy flag
<> 128:9bcdf88f62b0 806 * @note The BSY flag is cleared under any one of the following conditions:
<> 128:9bcdf88f62b0 807 * -When the SPI is correctly disabled
<> 128:9bcdf88f62b0 808 * -When a fault is detected in Master mode (MODF bit set to 1)
<> 128:9bcdf88f62b0 809 * -In Master mode, when it finishes a data transmission and no new data is ready to be
<> 128:9bcdf88f62b0 810 * sent
<> 128:9bcdf88f62b0 811 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<> 128:9bcdf88f62b0 812 * each data transfer.
<> 128:9bcdf88f62b0 813 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<> 128:9bcdf88f62b0 814 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 815 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 816 */
<> 128:9bcdf88f62b0 817 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 818 {
<> 128:9bcdf88f62b0 819 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<> 128:9bcdf88f62b0 820 }
<> 128:9bcdf88f62b0 821
<> 128:9bcdf88f62b0 822 /**
<> 128:9bcdf88f62b0 823 * @brief Get frame format error flag
<> 128:9bcdf88f62b0 824 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<> 128:9bcdf88f62b0 825 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 826 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 827 */
<> 128:9bcdf88f62b0 828 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 829 {
<> 128:9bcdf88f62b0 830 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<> 128:9bcdf88f62b0 831 }
<> 128:9bcdf88f62b0 832
<> 128:9bcdf88f62b0 833 /**
<> 128:9bcdf88f62b0 834 * @brief Clear CRC error flag
<> 128:9bcdf88f62b0 835 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<> 128:9bcdf88f62b0 836 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 837 * @retval None
<> 128:9bcdf88f62b0 838 */
<> 128:9bcdf88f62b0 839 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 840 {
<> 128:9bcdf88f62b0 841 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<> 128:9bcdf88f62b0 842 }
<> 128:9bcdf88f62b0 843
<> 128:9bcdf88f62b0 844 /**
<> 128:9bcdf88f62b0 845 * @brief Clear mode fault error flag
<> 128:9bcdf88f62b0 846 * @note Clearing this flag is done by a read access to the SPIx_SR
<> 128:9bcdf88f62b0 847 * register followed by a write access to the SPIx_CR1 register
<> 128:9bcdf88f62b0 848 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<> 128:9bcdf88f62b0 849 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 850 * @retval None
<> 128:9bcdf88f62b0 851 */
<> 128:9bcdf88f62b0 852 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 853 {
<> 128:9bcdf88f62b0 854 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 855 tmpreg = SPIx->SR;
<> 128:9bcdf88f62b0 856 (void) tmpreg;
<> 128:9bcdf88f62b0 857 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 128:9bcdf88f62b0 858 (void) tmpreg;
<> 128:9bcdf88f62b0 859 }
<> 128:9bcdf88f62b0 860
<> 128:9bcdf88f62b0 861 /**
<> 128:9bcdf88f62b0 862 * @brief Clear overrun error flag
<> 128:9bcdf88f62b0 863 * @note Clearing this flag is done by a read access to the SPIx_DR
<> 128:9bcdf88f62b0 864 * register followed by a read access to the SPIx_SR register
<> 128:9bcdf88f62b0 865 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<> 128:9bcdf88f62b0 866 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 867 * @retval None
<> 128:9bcdf88f62b0 868 */
<> 128:9bcdf88f62b0 869 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 870 {
<> 128:9bcdf88f62b0 871 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 872 tmpreg = SPIx->DR;
<> 128:9bcdf88f62b0 873 (void) tmpreg;
<> 128:9bcdf88f62b0 874 tmpreg = SPIx->SR;
<> 128:9bcdf88f62b0 875 (void) tmpreg;
<> 128:9bcdf88f62b0 876 }
<> 128:9bcdf88f62b0 877
<> 128:9bcdf88f62b0 878 /**
<> 128:9bcdf88f62b0 879 * @brief Clear frame format error flag
<> 128:9bcdf88f62b0 880 * @note Clearing this flag is done by reading SPIx_SR register
<> 128:9bcdf88f62b0 881 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<> 128:9bcdf88f62b0 882 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 883 * @retval None
<> 128:9bcdf88f62b0 884 */
<> 128:9bcdf88f62b0 885 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 886 {
<> 128:9bcdf88f62b0 887 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 888 tmpreg = SPIx->SR;
<> 128:9bcdf88f62b0 889 (void) tmpreg;
<> 128:9bcdf88f62b0 890 }
<> 128:9bcdf88f62b0 891
<> 128:9bcdf88f62b0 892 /**
<> 128:9bcdf88f62b0 893 * @}
<> 128:9bcdf88f62b0 894 */
<> 128:9bcdf88f62b0 895
<> 128:9bcdf88f62b0 896 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<> 128:9bcdf88f62b0 897 * @{
<> 128:9bcdf88f62b0 898 */
<> 128:9bcdf88f62b0 899
<> 128:9bcdf88f62b0 900 /**
<> 128:9bcdf88f62b0 901 * @brief Enable error interrupt
<> 128:9bcdf88f62b0 902 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<> 128:9bcdf88f62b0 903 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<> 128:9bcdf88f62b0 904 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 905 * @retval None
<> 128:9bcdf88f62b0 906 */
<> 128:9bcdf88f62b0 907 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 908 {
<> 128:9bcdf88f62b0 909 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<> 128:9bcdf88f62b0 910 }
<> 128:9bcdf88f62b0 911
<> 128:9bcdf88f62b0 912 /**
<> 128:9bcdf88f62b0 913 * @brief Enable Rx buffer not empty interrupt
<> 128:9bcdf88f62b0 914 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<> 128:9bcdf88f62b0 915 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 916 * @retval None
<> 128:9bcdf88f62b0 917 */
<> 128:9bcdf88f62b0 918 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 919 {
<> 128:9bcdf88f62b0 920 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<> 128:9bcdf88f62b0 921 }
<> 128:9bcdf88f62b0 922
<> 128:9bcdf88f62b0 923 /**
<> 128:9bcdf88f62b0 924 * @brief Enable Tx buffer empty interrupt
<> 128:9bcdf88f62b0 925 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<> 128:9bcdf88f62b0 926 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 927 * @retval None
<> 128:9bcdf88f62b0 928 */
<> 128:9bcdf88f62b0 929 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 930 {
<> 128:9bcdf88f62b0 931 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<> 128:9bcdf88f62b0 932 }
<> 128:9bcdf88f62b0 933
<> 128:9bcdf88f62b0 934 /**
<> 128:9bcdf88f62b0 935 * @brief Disable error interrupt
<> 128:9bcdf88f62b0 936 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<> 128:9bcdf88f62b0 937 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<> 128:9bcdf88f62b0 938 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 939 * @retval None
<> 128:9bcdf88f62b0 940 */
<> 128:9bcdf88f62b0 941 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 942 {
<> 128:9bcdf88f62b0 943 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<> 128:9bcdf88f62b0 944 }
<> 128:9bcdf88f62b0 945
<> 128:9bcdf88f62b0 946 /**
<> 128:9bcdf88f62b0 947 * @brief Disable Rx buffer not empty interrupt
<> 128:9bcdf88f62b0 948 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<> 128:9bcdf88f62b0 949 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 950 * @retval None
<> 128:9bcdf88f62b0 951 */
<> 128:9bcdf88f62b0 952 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 953 {
<> 128:9bcdf88f62b0 954 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<> 128:9bcdf88f62b0 955 }
<> 128:9bcdf88f62b0 956
<> 128:9bcdf88f62b0 957 /**
<> 128:9bcdf88f62b0 958 * @brief Disable Tx buffer empty interrupt
<> 128:9bcdf88f62b0 959 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<> 128:9bcdf88f62b0 960 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 961 * @retval None
<> 128:9bcdf88f62b0 962 */
<> 128:9bcdf88f62b0 963 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 964 {
<> 128:9bcdf88f62b0 965 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<> 128:9bcdf88f62b0 966 }
<> 128:9bcdf88f62b0 967
<> 128:9bcdf88f62b0 968 /**
<> 128:9bcdf88f62b0 969 * @brief Check if error interrupt is enabled
<> 128:9bcdf88f62b0 970 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<> 128:9bcdf88f62b0 971 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 972 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 973 */
<> 128:9bcdf88f62b0 974 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 975 {
<> 128:9bcdf88f62b0 976 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<> 128:9bcdf88f62b0 977 }
<> 128:9bcdf88f62b0 978
<> 128:9bcdf88f62b0 979 /**
<> 128:9bcdf88f62b0 980 * @brief Check if Rx buffer not empty interrupt is enabled
<> 128:9bcdf88f62b0 981 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<> 128:9bcdf88f62b0 982 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 983 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 984 */
<> 128:9bcdf88f62b0 985 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 986 {
<> 128:9bcdf88f62b0 987 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<> 128:9bcdf88f62b0 988 }
<> 128:9bcdf88f62b0 989
<> 128:9bcdf88f62b0 990 /**
<> 128:9bcdf88f62b0 991 * @brief Check if Tx buffer empty interrupt
<> 128:9bcdf88f62b0 992 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<> 128:9bcdf88f62b0 993 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 994 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 995 */
<> 128:9bcdf88f62b0 996 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 997 {
<> 128:9bcdf88f62b0 998 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<> 128:9bcdf88f62b0 999 }
<> 128:9bcdf88f62b0 1000
<> 128:9bcdf88f62b0 1001 /**
<> 128:9bcdf88f62b0 1002 * @}
<> 128:9bcdf88f62b0 1003 */
<> 128:9bcdf88f62b0 1004
<> 128:9bcdf88f62b0 1005 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
<> 128:9bcdf88f62b0 1006 * @{
<> 128:9bcdf88f62b0 1007 */
<> 128:9bcdf88f62b0 1008
<> 128:9bcdf88f62b0 1009 /**
<> 128:9bcdf88f62b0 1010 * @brief Enable DMA Rx
<> 128:9bcdf88f62b0 1011 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<> 128:9bcdf88f62b0 1012 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1013 * @retval None
<> 128:9bcdf88f62b0 1014 */
<> 128:9bcdf88f62b0 1015 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1016 {
<> 128:9bcdf88f62b0 1017 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<> 128:9bcdf88f62b0 1018 }
<> 128:9bcdf88f62b0 1019
<> 128:9bcdf88f62b0 1020 /**
<> 128:9bcdf88f62b0 1021 * @brief Disable DMA Rx
<> 128:9bcdf88f62b0 1022 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<> 128:9bcdf88f62b0 1023 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1024 * @retval None
<> 128:9bcdf88f62b0 1025 */
<> 128:9bcdf88f62b0 1026 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1027 {
<> 128:9bcdf88f62b0 1028 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<> 128:9bcdf88f62b0 1029 }
<> 128:9bcdf88f62b0 1030
<> 128:9bcdf88f62b0 1031 /**
<> 128:9bcdf88f62b0 1032 * @brief Check if DMA Rx is enabled
<> 128:9bcdf88f62b0 1033 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<> 128:9bcdf88f62b0 1034 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1035 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1036 */
<> 128:9bcdf88f62b0 1037 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1038 {
<> 128:9bcdf88f62b0 1039 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<> 128:9bcdf88f62b0 1040 }
<> 128:9bcdf88f62b0 1041
<> 128:9bcdf88f62b0 1042 /**
<> 128:9bcdf88f62b0 1043 * @brief Enable DMA Tx
<> 128:9bcdf88f62b0 1044 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<> 128:9bcdf88f62b0 1045 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1046 * @retval None
<> 128:9bcdf88f62b0 1047 */
<> 128:9bcdf88f62b0 1048 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1049 {
<> 128:9bcdf88f62b0 1050 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<> 128:9bcdf88f62b0 1051 }
<> 128:9bcdf88f62b0 1052
<> 128:9bcdf88f62b0 1053 /**
<> 128:9bcdf88f62b0 1054 * @brief Disable DMA Tx
<> 128:9bcdf88f62b0 1055 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<> 128:9bcdf88f62b0 1056 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1057 * @retval None
<> 128:9bcdf88f62b0 1058 */
<> 128:9bcdf88f62b0 1059 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1060 {
<> 128:9bcdf88f62b0 1061 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<> 128:9bcdf88f62b0 1062 }
<> 128:9bcdf88f62b0 1063
<> 128:9bcdf88f62b0 1064 /**
<> 128:9bcdf88f62b0 1065 * @brief Check if DMA Tx is enabled
<> 128:9bcdf88f62b0 1066 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<> 128:9bcdf88f62b0 1067 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1068 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1069 */
<> 128:9bcdf88f62b0 1070 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1071 {
<> 128:9bcdf88f62b0 1072 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<> 128:9bcdf88f62b0 1073 }
<> 128:9bcdf88f62b0 1074
<> 128:9bcdf88f62b0 1075 /**
<> 128:9bcdf88f62b0 1076 * @brief Get the data register address used for DMA transfer
<> 128:9bcdf88f62b0 1077 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<> 128:9bcdf88f62b0 1078 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1079 * @retval Address of data register
<> 128:9bcdf88f62b0 1080 */
<> 128:9bcdf88f62b0 1081 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1082 {
<> 128:9bcdf88f62b0 1083 return (uint32_t) & (SPIx->DR);
<> 128:9bcdf88f62b0 1084 }
<> 128:9bcdf88f62b0 1085
<> 128:9bcdf88f62b0 1086 /**
<> 128:9bcdf88f62b0 1087 * @}
<> 128:9bcdf88f62b0 1088 */
<> 128:9bcdf88f62b0 1089
<> 128:9bcdf88f62b0 1090 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
<> 128:9bcdf88f62b0 1091 * @{
<> 128:9bcdf88f62b0 1092 */
<> 128:9bcdf88f62b0 1093
<> 128:9bcdf88f62b0 1094 /**
<> 128:9bcdf88f62b0 1095 * @brief Read 8-Bits in the data register
<> 128:9bcdf88f62b0 1096 * @rmtoll DR DR LL_SPI_ReceiveData8
<> 128:9bcdf88f62b0 1097 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1098 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<> 128:9bcdf88f62b0 1099 */
<> 128:9bcdf88f62b0 1100 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1101 {
<> 128:9bcdf88f62b0 1102 return (uint8_t)(READ_REG(SPIx->DR));
<> 128:9bcdf88f62b0 1103 }
<> 128:9bcdf88f62b0 1104
<> 128:9bcdf88f62b0 1105 /**
<> 128:9bcdf88f62b0 1106 * @brief Read 16-Bits in the data register
<> 128:9bcdf88f62b0 1107 * @rmtoll DR DR LL_SPI_ReceiveData16
<> 128:9bcdf88f62b0 1108 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1109 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<> 128:9bcdf88f62b0 1110 */
<> 128:9bcdf88f62b0 1111 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1112 {
<> 128:9bcdf88f62b0 1113 return (uint16_t)(READ_REG(SPIx->DR));
<> 128:9bcdf88f62b0 1114 }
<> 128:9bcdf88f62b0 1115
<> 128:9bcdf88f62b0 1116 /**
<> 128:9bcdf88f62b0 1117 * @brief Write 8-Bits in the data register
<> 128:9bcdf88f62b0 1118 * @rmtoll DR DR LL_SPI_TransmitData8
<> 128:9bcdf88f62b0 1119 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1120 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<> 128:9bcdf88f62b0 1121 * @retval None
<> 128:9bcdf88f62b0 1122 */
<> 128:9bcdf88f62b0 1123 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<> 128:9bcdf88f62b0 1124 {
<> 128:9bcdf88f62b0 1125 *((__IO uint8_t *)&SPIx->DR) = TxData;
<> 128:9bcdf88f62b0 1126 }
<> 128:9bcdf88f62b0 1127
<> 128:9bcdf88f62b0 1128 /**
<> 128:9bcdf88f62b0 1129 * @brief Write 16-Bits in the data register
<> 128:9bcdf88f62b0 1130 * @rmtoll DR DR LL_SPI_TransmitData16
<> 128:9bcdf88f62b0 1131 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1132 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<> 128:9bcdf88f62b0 1133 * @retval None
<> 128:9bcdf88f62b0 1134 */
<> 128:9bcdf88f62b0 1135 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<> 128:9bcdf88f62b0 1136 {
<> 128:9bcdf88f62b0 1137 *((__IO uint16_t *)&SPIx->DR) = TxData;
<> 128:9bcdf88f62b0 1138 }
<> 128:9bcdf88f62b0 1139
<> 128:9bcdf88f62b0 1140 /**
<> 128:9bcdf88f62b0 1141 * @}
<> 128:9bcdf88f62b0 1142 */
<> 128:9bcdf88f62b0 1143 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 1144 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<> 128:9bcdf88f62b0 1145 * @{
<> 128:9bcdf88f62b0 1146 */
<> 128:9bcdf88f62b0 1147
<> 128:9bcdf88f62b0 1148 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<> 128:9bcdf88f62b0 1149 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
<> 128:9bcdf88f62b0 1150 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<> 128:9bcdf88f62b0 1151
<> 128:9bcdf88f62b0 1152 /**
<> 128:9bcdf88f62b0 1153 * @}
<> 128:9bcdf88f62b0 1154 */
<> 128:9bcdf88f62b0 1155 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 1156 /**
<> 128:9bcdf88f62b0 1157 * @}
<> 128:9bcdf88f62b0 1158 */
<> 128:9bcdf88f62b0 1159
<> 128:9bcdf88f62b0 1160 /**
<> 128:9bcdf88f62b0 1161 * @}
<> 128:9bcdf88f62b0 1162 */
<> 128:9bcdf88f62b0 1163
<> 128:9bcdf88f62b0 1164 #if defined(SPI_I2S_SUPPORT)
<> 128:9bcdf88f62b0 1165 /** @defgroup I2S_LL I2S
<> 128:9bcdf88f62b0 1166 * @{
<> 128:9bcdf88f62b0 1167 */
<> 128:9bcdf88f62b0 1168
<> 128:9bcdf88f62b0 1169 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 1170 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 1171 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 1172
<> 128:9bcdf88f62b0 1173 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 1174 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 1175 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<> 128:9bcdf88f62b0 1176 * @{
<> 128:9bcdf88f62b0 1177 */
<> 128:9bcdf88f62b0 1178
<> 128:9bcdf88f62b0 1179 /**
<> 128:9bcdf88f62b0 1180 * @brief I2S Init structure definition
<> 128:9bcdf88f62b0 1181 */
<> 128:9bcdf88f62b0 1182
<> 128:9bcdf88f62b0 1183 typedef struct
<> 128:9bcdf88f62b0 1184 {
<> 128:9bcdf88f62b0 1185 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 128:9bcdf88f62b0 1186 This parameter can be a value of @ref I2S_LL_EC_MODE
<> 128:9bcdf88f62b0 1187
<> 128:9bcdf88f62b0 1188 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<> 128:9bcdf88f62b0 1189
<> 128:9bcdf88f62b0 1190 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 128:9bcdf88f62b0 1191 This parameter can be a value of @ref I2S_LL_EC_STANDARD
<> 128:9bcdf88f62b0 1192
<> 128:9bcdf88f62b0 1193 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<> 128:9bcdf88f62b0 1194
<> 128:9bcdf88f62b0 1195
<> 128:9bcdf88f62b0 1196 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 128:9bcdf88f62b0 1197 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<> 128:9bcdf88f62b0 1198
<> 128:9bcdf88f62b0 1199 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<> 128:9bcdf88f62b0 1200
<> 128:9bcdf88f62b0 1201
<> 128:9bcdf88f62b0 1202 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 128:9bcdf88f62b0 1203 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<> 128:9bcdf88f62b0 1204
<> 128:9bcdf88f62b0 1205 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<> 128:9bcdf88f62b0 1206
<> 128:9bcdf88f62b0 1207
<> 128:9bcdf88f62b0 1208 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 128:9bcdf88f62b0 1209 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<> 128:9bcdf88f62b0 1210
<> 128:9bcdf88f62b0 1211 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<> 128:9bcdf88f62b0 1212 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<> 128:9bcdf88f62b0 1213
<> 128:9bcdf88f62b0 1214
<> 128:9bcdf88f62b0 1215 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<> 128:9bcdf88f62b0 1216 This parameter can be a value of @ref I2S_LL_EC_POLARITY
<> 128:9bcdf88f62b0 1217
<> 128:9bcdf88f62b0 1218 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<> 128:9bcdf88f62b0 1219
<> 128:9bcdf88f62b0 1220 } LL_I2S_InitTypeDef;
<> 128:9bcdf88f62b0 1221
<> 128:9bcdf88f62b0 1222 /**
<> 128:9bcdf88f62b0 1223 * @}
<> 128:9bcdf88f62b0 1224 */
<> 128:9bcdf88f62b0 1225 #endif /*USE_FULL_LL_DRIVER*/
<> 128:9bcdf88f62b0 1226
<> 128:9bcdf88f62b0 1227 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1228 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<> 128:9bcdf88f62b0 1229 * @{
<> 128:9bcdf88f62b0 1230 */
<> 128:9bcdf88f62b0 1231
<> 128:9bcdf88f62b0 1232 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<> 128:9bcdf88f62b0 1233 * @brief Flags defines which can be used with LL_I2S_ReadReg function
<> 128:9bcdf88f62b0 1234 * @{
<> 128:9bcdf88f62b0 1235 */
<> 128:9bcdf88f62b0 1236 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
<> 128:9bcdf88f62b0 1237 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
<> 128:9bcdf88f62b0 1238 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
<> 128:9bcdf88f62b0 1239 #define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */
<> 128:9bcdf88f62b0 1240 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
<> 128:9bcdf88f62b0 1241 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
<> 128:9bcdf88f62b0 1242 /**
<> 128:9bcdf88f62b0 1243 * @}
<> 128:9bcdf88f62b0 1244 */
<> 128:9bcdf88f62b0 1245
<> 128:9bcdf88f62b0 1246 /** @defgroup SPI_LL_EC_IT IT Defines
<> 128:9bcdf88f62b0 1247 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<> 128:9bcdf88f62b0 1248 * @{
<> 128:9bcdf88f62b0 1249 */
<> 128:9bcdf88f62b0 1250 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
<> 128:9bcdf88f62b0 1251 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
<> 128:9bcdf88f62b0 1252 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
<> 128:9bcdf88f62b0 1253 /**
<> 128:9bcdf88f62b0 1254 * @}
<> 128:9bcdf88f62b0 1255 */
<> 128:9bcdf88f62b0 1256
<> 128:9bcdf88f62b0 1257 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<> 128:9bcdf88f62b0 1258 * @{
<> 128:9bcdf88f62b0 1259 */
<> 128:9bcdf88f62b0 1260 #define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */
<> 128:9bcdf88f62b0 1261 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
<> 128:9bcdf88f62b0 1262 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
<> 128:9bcdf88f62b0 1263 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
<> 128:9bcdf88f62b0 1264 /**
<> 128:9bcdf88f62b0 1265 * @}
<> 128:9bcdf88f62b0 1266 */
<> 128:9bcdf88f62b0 1267
<> 128:9bcdf88f62b0 1268 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<> 128:9bcdf88f62b0 1269 * @{
<> 128:9bcdf88f62b0 1270 */
<> 128:9bcdf88f62b0 1271 #define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */
<> 128:9bcdf88f62b0 1272 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
<> 128:9bcdf88f62b0 1273 /**
<> 128:9bcdf88f62b0 1274 * @}
<> 128:9bcdf88f62b0 1275 */
<> 128:9bcdf88f62b0 1276
<> 128:9bcdf88f62b0 1277 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
<> 128:9bcdf88f62b0 1278 * @{
<> 128:9bcdf88f62b0 1279 */
<> 128:9bcdf88f62b0 1280 #define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */
<> 128:9bcdf88f62b0 1281 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
<> 128:9bcdf88f62b0 1282 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
<> 128:9bcdf88f62b0 1283 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
<> 128:9bcdf88f62b0 1284 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
<> 128:9bcdf88f62b0 1285 /**
<> 128:9bcdf88f62b0 1286 * @}
<> 128:9bcdf88f62b0 1287 */
<> 128:9bcdf88f62b0 1288
<> 128:9bcdf88f62b0 1289 /** @defgroup I2S_LL_EC_MODE Operation Mode
<> 128:9bcdf88f62b0 1290 * @{
<> 128:9bcdf88f62b0 1291 */
<> 128:9bcdf88f62b0 1292 #define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */
<> 128:9bcdf88f62b0 1293 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
<> 128:9bcdf88f62b0 1294 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
<> 128:9bcdf88f62b0 1295 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
<> 128:9bcdf88f62b0 1296 /**
<> 128:9bcdf88f62b0 1297 * @}
<> 128:9bcdf88f62b0 1298 */
<> 128:9bcdf88f62b0 1299
<> 128:9bcdf88f62b0 1300 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<> 128:9bcdf88f62b0 1301 * @{
<> 128:9bcdf88f62b0 1302 */
<> 128:9bcdf88f62b0 1303 #define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
<> 128:9bcdf88f62b0 1304 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
<> 128:9bcdf88f62b0 1305 /**
<> 128:9bcdf88f62b0 1306 * @}
<> 128:9bcdf88f62b0 1307 */
<> 128:9bcdf88f62b0 1308
<> 128:9bcdf88f62b0 1309 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 1310
<> 128:9bcdf88f62b0 1311 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<> 128:9bcdf88f62b0 1312 * @{
<> 128:9bcdf88f62b0 1313 */
<> 128:9bcdf88f62b0 1314 #define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */
<> 128:9bcdf88f62b0 1315 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
<> 128:9bcdf88f62b0 1316 /**
<> 128:9bcdf88f62b0 1317 * @}
<> 128:9bcdf88f62b0 1318 */
<> 128:9bcdf88f62b0 1319
<> 128:9bcdf88f62b0 1320 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<> 128:9bcdf88f62b0 1321 * @{
<> 128:9bcdf88f62b0 1322 */
<> 128:9bcdf88f62b0 1323
<> 128:9bcdf88f62b0 1324 #define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */
<> 128:9bcdf88f62b0 1325 #define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */
<> 128:9bcdf88f62b0 1326 #define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */
<> 128:9bcdf88f62b0 1327 #define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */
<> 128:9bcdf88f62b0 1328 #define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */
<> 128:9bcdf88f62b0 1329 #define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */
<> 128:9bcdf88f62b0 1330 #define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */
<> 128:9bcdf88f62b0 1331 #define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */
<> 128:9bcdf88f62b0 1332 #define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */
<> 128:9bcdf88f62b0 1333 #define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */
<> 128:9bcdf88f62b0 1334 /**
<> 128:9bcdf88f62b0 1335 * @}
<> 128:9bcdf88f62b0 1336 */
<> 128:9bcdf88f62b0 1337 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 1338
<> 128:9bcdf88f62b0 1339 /**
<> 128:9bcdf88f62b0 1340 * @}
<> 128:9bcdf88f62b0 1341 */
<> 128:9bcdf88f62b0 1342
<> 128:9bcdf88f62b0 1343 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 1344 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<> 128:9bcdf88f62b0 1345 * @{
<> 128:9bcdf88f62b0 1346 */
<> 128:9bcdf88f62b0 1347
<> 128:9bcdf88f62b0 1348 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<> 128:9bcdf88f62b0 1349 * @{
<> 128:9bcdf88f62b0 1350 */
<> 128:9bcdf88f62b0 1351
<> 128:9bcdf88f62b0 1352 /**
<> 128:9bcdf88f62b0 1353 * @brief Write a value in I2S register
<> 128:9bcdf88f62b0 1354 * @param __INSTANCE__ I2S Instance
<> 128:9bcdf88f62b0 1355 * @param __REG__ Register to be written
<> 128:9bcdf88f62b0 1356 * @param __VALUE__ Value to be written in the register
<> 128:9bcdf88f62b0 1357 * @retval None
<> 128:9bcdf88f62b0 1358 */
<> 128:9bcdf88f62b0 1359 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 128:9bcdf88f62b0 1360
<> 128:9bcdf88f62b0 1361 /**
<> 128:9bcdf88f62b0 1362 * @brief Read a value in I2S register
<> 128:9bcdf88f62b0 1363 * @param __INSTANCE__ I2S Instance
<> 128:9bcdf88f62b0 1364 * @param __REG__ Register to be read
<> 128:9bcdf88f62b0 1365 * @retval Register value
<> 128:9bcdf88f62b0 1366 */
<> 128:9bcdf88f62b0 1367 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 128:9bcdf88f62b0 1368 /**
<> 128:9bcdf88f62b0 1369 * @}
<> 128:9bcdf88f62b0 1370 */
<> 128:9bcdf88f62b0 1371
<> 128:9bcdf88f62b0 1372 /**
<> 128:9bcdf88f62b0 1373 * @}
<> 128:9bcdf88f62b0 1374 */
<> 128:9bcdf88f62b0 1375
<> 128:9bcdf88f62b0 1376
<> 128:9bcdf88f62b0 1377 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1378
<> 128:9bcdf88f62b0 1379 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<> 128:9bcdf88f62b0 1380 * @{
<> 128:9bcdf88f62b0 1381 */
<> 128:9bcdf88f62b0 1382
<> 128:9bcdf88f62b0 1383 /** @defgroup I2S_LL_EF_Configuration Configuration
<> 128:9bcdf88f62b0 1384 * @{
<> 128:9bcdf88f62b0 1385 */
<> 128:9bcdf88f62b0 1386
<> 128:9bcdf88f62b0 1387 /**
<> 128:9bcdf88f62b0 1388 * @brief Select I2S mode and Enable I2S peripheral
<> 128:9bcdf88f62b0 1389 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<> 128:9bcdf88f62b0 1390 * I2SCFGR I2SE LL_I2S_Enable
<> 128:9bcdf88f62b0 1391 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1392 * @retval None
<> 128:9bcdf88f62b0 1393 */
<> 128:9bcdf88f62b0 1394 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1395 {
<> 128:9bcdf88f62b0 1396 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
<> 128:9bcdf88f62b0 1397 }
<> 128:9bcdf88f62b0 1398
<> 128:9bcdf88f62b0 1399 /**
<> 128:9bcdf88f62b0 1400 * @brief Disable I2S peripheral
<> 128:9bcdf88f62b0 1401 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
<> 128:9bcdf88f62b0 1402 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1403 * @retval None
<> 128:9bcdf88f62b0 1404 */
<> 128:9bcdf88f62b0 1405 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1406 {
<> 128:9bcdf88f62b0 1407 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
<> 128:9bcdf88f62b0 1408 }
<> 128:9bcdf88f62b0 1409
<> 128:9bcdf88f62b0 1410 /**
<> 128:9bcdf88f62b0 1411 * @brief Check if I2S peripheral is enabled
<> 128:9bcdf88f62b0 1412 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<> 128:9bcdf88f62b0 1413 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1414 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1415 */
<> 128:9bcdf88f62b0 1416 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1417 {
<> 128:9bcdf88f62b0 1418 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<> 128:9bcdf88f62b0 1419 }
<> 128:9bcdf88f62b0 1420
<> 128:9bcdf88f62b0 1421 /**
<> 128:9bcdf88f62b0 1422 * @brief Set I2S Data frame length
<> 128:9bcdf88f62b0 1423 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<> 128:9bcdf88f62b0 1424 * I2SCFGR CHLEN LL_I2S_SetDataFormat
<> 128:9bcdf88f62b0 1425 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1426 * @param DataFormat This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1427 * @arg @ref LL_I2S_DATAFORMAT_16B
<> 128:9bcdf88f62b0 1428 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<> 128:9bcdf88f62b0 1429 * @arg @ref LL_I2S_DATAFORMAT_24B
<> 128:9bcdf88f62b0 1430 * @arg @ref LL_I2S_DATAFORMAT_32B
<> 128:9bcdf88f62b0 1431 * @retval None
<> 128:9bcdf88f62b0 1432 */
<> 128:9bcdf88f62b0 1433 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<> 128:9bcdf88f62b0 1434 {
<> 128:9bcdf88f62b0 1435 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
<> 128:9bcdf88f62b0 1436 }
<> 128:9bcdf88f62b0 1437
<> 128:9bcdf88f62b0 1438 /**
<> 128:9bcdf88f62b0 1439 * @brief Get I2S Data frame length
<> 128:9bcdf88f62b0 1440 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<> 128:9bcdf88f62b0 1441 * I2SCFGR CHLEN LL_I2S_GetDataFormat
<> 128:9bcdf88f62b0 1442 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1443 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1444 * @arg @ref LL_I2S_DATAFORMAT_16B
<> 128:9bcdf88f62b0 1445 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<> 128:9bcdf88f62b0 1446 * @arg @ref LL_I2S_DATAFORMAT_24B
<> 128:9bcdf88f62b0 1447 * @arg @ref LL_I2S_DATAFORMAT_32B
<> 128:9bcdf88f62b0 1448 */
<> 128:9bcdf88f62b0 1449 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1450 {
<> 128:9bcdf88f62b0 1451 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
<> 128:9bcdf88f62b0 1452 }
<> 128:9bcdf88f62b0 1453
<> 128:9bcdf88f62b0 1454 /**
<> 128:9bcdf88f62b0 1455 * @brief Set I2S clock polarity
<> 128:9bcdf88f62b0 1456 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<> 128:9bcdf88f62b0 1457 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1458 * @param ClockPolarity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1459 * @arg @ref LL_I2S_POLARITY_LOW
<> 128:9bcdf88f62b0 1460 * @arg @ref LL_I2S_POLARITY_HIGH
<> 128:9bcdf88f62b0 1461 * @retval None
<> 128:9bcdf88f62b0 1462 */
<> 128:9bcdf88f62b0 1463 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<> 128:9bcdf88f62b0 1464 {
<> 128:9bcdf88f62b0 1465 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<> 128:9bcdf88f62b0 1466 }
<> 128:9bcdf88f62b0 1467
<> 128:9bcdf88f62b0 1468 /**
<> 128:9bcdf88f62b0 1469 * @brief Get I2S clock polarity
<> 128:9bcdf88f62b0 1470 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<> 128:9bcdf88f62b0 1471 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1472 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1473 * @arg @ref LL_I2S_POLARITY_LOW
<> 128:9bcdf88f62b0 1474 * @arg @ref LL_I2S_POLARITY_HIGH
<> 128:9bcdf88f62b0 1475 */
<> 128:9bcdf88f62b0 1476 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1477 {
<> 128:9bcdf88f62b0 1478 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<> 128:9bcdf88f62b0 1479 }
<> 128:9bcdf88f62b0 1480
<> 128:9bcdf88f62b0 1481 /**
<> 128:9bcdf88f62b0 1482 * @brief Set I2S Standard Protocol
<> 128:9bcdf88f62b0 1483 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<> 128:9bcdf88f62b0 1484 * I2SCFGR PCMSYNC LL_I2S_SetStandard
<> 128:9bcdf88f62b0 1485 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1486 * @param Standard This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1487 * @arg @ref LL_I2S_STANDARD_PHILIPS
<> 128:9bcdf88f62b0 1488 * @arg @ref LL_I2S_STANDARD_MSB
<> 128:9bcdf88f62b0 1489 * @arg @ref LL_I2S_STANDARD_LSB
<> 128:9bcdf88f62b0 1490 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
<> 128:9bcdf88f62b0 1491 * @arg @ref LL_I2S_STANDARD_PCM_LONG
<> 128:9bcdf88f62b0 1492 * @retval None
<> 128:9bcdf88f62b0 1493 */
<> 128:9bcdf88f62b0 1494 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<> 128:9bcdf88f62b0 1495 {
<> 128:9bcdf88f62b0 1496 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
<> 128:9bcdf88f62b0 1497 }
<> 128:9bcdf88f62b0 1498
<> 128:9bcdf88f62b0 1499 /**
<> 128:9bcdf88f62b0 1500 * @brief Get I2S Standard Protocol
<> 128:9bcdf88f62b0 1501 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<> 128:9bcdf88f62b0 1502 * I2SCFGR PCMSYNC LL_I2S_GetStandard
<> 128:9bcdf88f62b0 1503 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1504 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1505 * @arg @ref LL_I2S_STANDARD_PHILIPS
<> 128:9bcdf88f62b0 1506 * @arg @ref LL_I2S_STANDARD_MSB
<> 128:9bcdf88f62b0 1507 * @arg @ref LL_I2S_STANDARD_LSB
<> 128:9bcdf88f62b0 1508 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
<> 128:9bcdf88f62b0 1509 * @arg @ref LL_I2S_STANDARD_PCM_LONG
<> 128:9bcdf88f62b0 1510 */
<> 128:9bcdf88f62b0 1511 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1512 {
<> 128:9bcdf88f62b0 1513 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
<> 128:9bcdf88f62b0 1514 }
<> 128:9bcdf88f62b0 1515
<> 128:9bcdf88f62b0 1516 /**
<> 128:9bcdf88f62b0 1517 * @brief Set I2S Transfer Mode
<> 128:9bcdf88f62b0 1518 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<> 128:9bcdf88f62b0 1519 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1520 * @param Mode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1521 * @arg @ref LL_I2S_MODE_SLAVE_TX
<> 128:9bcdf88f62b0 1522 * @arg @ref LL_I2S_MODE_SLAVE_RX
<> 128:9bcdf88f62b0 1523 * @arg @ref LL_I2S_MODE_MASTER_TX
<> 128:9bcdf88f62b0 1524 * @arg @ref LL_I2S_MODE_MASTER_RX
<> 128:9bcdf88f62b0 1525 * @retval None
<> 128:9bcdf88f62b0 1526 */
<> 128:9bcdf88f62b0 1527 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<> 128:9bcdf88f62b0 1528 {
<> 128:9bcdf88f62b0 1529 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<> 128:9bcdf88f62b0 1530 }
<> 128:9bcdf88f62b0 1531
<> 128:9bcdf88f62b0 1532 /**
<> 128:9bcdf88f62b0 1533 * @brief Get I2S Transfer Mode
<> 128:9bcdf88f62b0 1534 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<> 128:9bcdf88f62b0 1535 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1536 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1537 * @arg @ref LL_I2S_MODE_SLAVE_TX
<> 128:9bcdf88f62b0 1538 * @arg @ref LL_I2S_MODE_SLAVE_RX
<> 128:9bcdf88f62b0 1539 * @arg @ref LL_I2S_MODE_MASTER_TX
<> 128:9bcdf88f62b0 1540 * @arg @ref LL_I2S_MODE_MASTER_RX
<> 128:9bcdf88f62b0 1541 */
<> 128:9bcdf88f62b0 1542 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1543 {
<> 128:9bcdf88f62b0 1544 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<> 128:9bcdf88f62b0 1545 }
<> 128:9bcdf88f62b0 1546
<> 128:9bcdf88f62b0 1547 /**
<> 128:9bcdf88f62b0 1548 * @brief Set I2S linear prescaler
<> 128:9bcdf88f62b0 1549 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<> 128:9bcdf88f62b0 1550 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1551 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<> 128:9bcdf88f62b0 1552 * @retval None
<> 128:9bcdf88f62b0 1553 */
<> 128:9bcdf88f62b0 1554 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<> 128:9bcdf88f62b0 1555 {
<> 128:9bcdf88f62b0 1556 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<> 128:9bcdf88f62b0 1557 }
<> 128:9bcdf88f62b0 1558
<> 128:9bcdf88f62b0 1559 /**
<> 128:9bcdf88f62b0 1560 * @brief Get I2S linear prescaler
<> 128:9bcdf88f62b0 1561 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<> 128:9bcdf88f62b0 1562 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1563 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<> 128:9bcdf88f62b0 1564 */
<> 128:9bcdf88f62b0 1565 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1566 {
<> 128:9bcdf88f62b0 1567 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<> 128:9bcdf88f62b0 1568 }
<> 128:9bcdf88f62b0 1569
<> 128:9bcdf88f62b0 1570 /**
<> 128:9bcdf88f62b0 1571 * @brief Set I2S parity prescaler
<> 128:9bcdf88f62b0 1572 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<> 128:9bcdf88f62b0 1573 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1574 * @param PrescalerParity This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1575 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 128:9bcdf88f62b0 1576 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 128:9bcdf88f62b0 1577 * @retval None
<> 128:9bcdf88f62b0 1578 */
<> 128:9bcdf88f62b0 1579 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<> 128:9bcdf88f62b0 1580 {
<> 128:9bcdf88f62b0 1581 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<> 128:9bcdf88f62b0 1582 }
<> 128:9bcdf88f62b0 1583
<> 128:9bcdf88f62b0 1584 /**
<> 128:9bcdf88f62b0 1585 * @brief Get I2S parity prescaler
<> 128:9bcdf88f62b0 1586 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<> 128:9bcdf88f62b0 1587 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1588 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1589 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 128:9bcdf88f62b0 1590 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 128:9bcdf88f62b0 1591 */
<> 128:9bcdf88f62b0 1592 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1593 {
<> 128:9bcdf88f62b0 1594 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<> 128:9bcdf88f62b0 1595 }
<> 128:9bcdf88f62b0 1596
<> 128:9bcdf88f62b0 1597 /**
<> 128:9bcdf88f62b0 1598 * @brief Enable the Master Clock Ouput (Pin MCK)
<> 128:9bcdf88f62b0 1599 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<> 128:9bcdf88f62b0 1600 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1601 * @retval None
<> 128:9bcdf88f62b0 1602 */
<> 128:9bcdf88f62b0 1603 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1604 {
<> 128:9bcdf88f62b0 1605 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<> 128:9bcdf88f62b0 1606 }
<> 128:9bcdf88f62b0 1607
<> 128:9bcdf88f62b0 1608 /**
<> 128:9bcdf88f62b0 1609 * @brief Disable the Master Clock Ouput (Pin MCK)
<> 128:9bcdf88f62b0 1610 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<> 128:9bcdf88f62b0 1611 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1612 * @retval None
<> 128:9bcdf88f62b0 1613 */
<> 128:9bcdf88f62b0 1614 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1615 {
<> 128:9bcdf88f62b0 1616 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<> 128:9bcdf88f62b0 1617 }
<> 128:9bcdf88f62b0 1618
<> 128:9bcdf88f62b0 1619 /**
<> 128:9bcdf88f62b0 1620 * @brief Check if the Master Clock Ouput (Pin MCK) is enabled
<> 128:9bcdf88f62b0 1621 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<> 128:9bcdf88f62b0 1622 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1623 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1624 */
<> 128:9bcdf88f62b0 1625 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1626 {
<> 128:9bcdf88f62b0 1627 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<> 128:9bcdf88f62b0 1628 }
<> 128:9bcdf88f62b0 1629
<> 128:9bcdf88f62b0 1630 /**
<> 128:9bcdf88f62b0 1631 * @}
<> 128:9bcdf88f62b0 1632 */
<> 128:9bcdf88f62b0 1633
<> 128:9bcdf88f62b0 1634 /** @defgroup I2S_LL_EF_FLAG FLAG Management
<> 128:9bcdf88f62b0 1635 * @{
<> 128:9bcdf88f62b0 1636 */
<> 128:9bcdf88f62b0 1637
<> 128:9bcdf88f62b0 1638 /**
<> 128:9bcdf88f62b0 1639 * @brief Check if Rx buffer is not empty
<> 128:9bcdf88f62b0 1640 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<> 128:9bcdf88f62b0 1641 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1642 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1643 */
<> 128:9bcdf88f62b0 1644 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1645 {
<> 128:9bcdf88f62b0 1646 return LL_SPI_IsActiveFlag_RXNE(SPIx);
<> 128:9bcdf88f62b0 1647 }
<> 128:9bcdf88f62b0 1648
<> 128:9bcdf88f62b0 1649 /**
<> 128:9bcdf88f62b0 1650 * @brief Check if Tx buffer is empty
<> 128:9bcdf88f62b0 1651 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<> 128:9bcdf88f62b0 1652 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1653 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1654 */
<> 128:9bcdf88f62b0 1655 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1656 {
<> 128:9bcdf88f62b0 1657 return LL_SPI_IsActiveFlag_TXE(SPIx);
<> 128:9bcdf88f62b0 1658 }
<> 128:9bcdf88f62b0 1659
<> 128:9bcdf88f62b0 1660 /**
<> 128:9bcdf88f62b0 1661 * @brief Get Busy flag
<> 128:9bcdf88f62b0 1662 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<> 128:9bcdf88f62b0 1663 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1664 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1665 */
<> 128:9bcdf88f62b0 1666 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1667 {
<> 128:9bcdf88f62b0 1668 return LL_SPI_IsActiveFlag_BSY(SPIx);
<> 128:9bcdf88f62b0 1669 }
<> 128:9bcdf88f62b0 1670
<> 128:9bcdf88f62b0 1671 /**
<> 128:9bcdf88f62b0 1672 * @brief Get Overrun error flag
<> 128:9bcdf88f62b0 1673 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<> 128:9bcdf88f62b0 1674 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1675 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1676 */
<> 128:9bcdf88f62b0 1677 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1678 {
<> 128:9bcdf88f62b0 1679 return LL_SPI_IsActiveFlag_OVR(SPIx);
<> 128:9bcdf88f62b0 1680 }
<> 128:9bcdf88f62b0 1681
<> 128:9bcdf88f62b0 1682 /**
<> 128:9bcdf88f62b0 1683 * @brief Get Underrun error flag
<> 128:9bcdf88f62b0 1684 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<> 128:9bcdf88f62b0 1685 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1686 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1687 */
<> 128:9bcdf88f62b0 1688 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1689 {
<> 128:9bcdf88f62b0 1690 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<> 128:9bcdf88f62b0 1691 }
<> 128:9bcdf88f62b0 1692
<> 128:9bcdf88f62b0 1693 /**
<> 128:9bcdf88f62b0 1694 * @brief Get Frame format error flag
<> 128:9bcdf88f62b0 1695 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<> 128:9bcdf88f62b0 1696 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1697 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1698 */
<> 128:9bcdf88f62b0 1699 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1700 {
<> 128:9bcdf88f62b0 1701 return LL_SPI_IsActiveFlag_FRE(SPIx);
<> 128:9bcdf88f62b0 1702 }
<> 128:9bcdf88f62b0 1703
<> 128:9bcdf88f62b0 1704 /**
<> 128:9bcdf88f62b0 1705 * @brief Get Channel side flag.
<> 128:9bcdf88f62b0 1706 * @note 0: Channel Left has to be transmitted or has been received\n
<> 128:9bcdf88f62b0 1707 * 1: Channel Right has to be transmitted or has been received\n
<> 128:9bcdf88f62b0 1708 * It has no significance in PCM mode.
<> 128:9bcdf88f62b0 1709 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<> 128:9bcdf88f62b0 1710 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1711 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1712 */
<> 128:9bcdf88f62b0 1713 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1714 {
<> 128:9bcdf88f62b0 1715 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<> 128:9bcdf88f62b0 1716 }
<> 128:9bcdf88f62b0 1717
<> 128:9bcdf88f62b0 1718 /**
<> 128:9bcdf88f62b0 1719 * @brief Clear Overrun error flag
<> 128:9bcdf88f62b0 1720 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<> 128:9bcdf88f62b0 1721 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1722 * @retval None
<> 128:9bcdf88f62b0 1723 */
<> 128:9bcdf88f62b0 1724 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1725 {
<> 128:9bcdf88f62b0 1726 LL_SPI_ClearFlag_OVR(SPIx);
<> 128:9bcdf88f62b0 1727 }
<> 128:9bcdf88f62b0 1728
<> 128:9bcdf88f62b0 1729 /**
<> 128:9bcdf88f62b0 1730 * @brief Clear Underrun error flag
<> 128:9bcdf88f62b0 1731 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<> 128:9bcdf88f62b0 1732 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1733 * @retval None
<> 128:9bcdf88f62b0 1734 */
<> 128:9bcdf88f62b0 1735 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1736 {
<> 128:9bcdf88f62b0 1737 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 1738 tmpreg = SPIx->SR;
<> 128:9bcdf88f62b0 1739 (void)tmpreg;
<> 128:9bcdf88f62b0 1740 }
<> 128:9bcdf88f62b0 1741
<> 128:9bcdf88f62b0 1742 /**
<> 128:9bcdf88f62b0 1743 * @brief Clear Frame format error flag
<> 128:9bcdf88f62b0 1744 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<> 128:9bcdf88f62b0 1745 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1746 * @retval None
<> 128:9bcdf88f62b0 1747 */
<> 128:9bcdf88f62b0 1748 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1749 {
<> 128:9bcdf88f62b0 1750 LL_SPI_ClearFlag_FRE(SPIx);
<> 128:9bcdf88f62b0 1751 }
<> 128:9bcdf88f62b0 1752
<> 128:9bcdf88f62b0 1753 /**
<> 128:9bcdf88f62b0 1754 * @}
<> 128:9bcdf88f62b0 1755 */
<> 128:9bcdf88f62b0 1756
<> 128:9bcdf88f62b0 1757 /** @defgroup I2S_LL_EF_IT Interrupt Management
<> 128:9bcdf88f62b0 1758 * @{
<> 128:9bcdf88f62b0 1759 */
<> 128:9bcdf88f62b0 1760
<> 128:9bcdf88f62b0 1761 /**
<> 128:9bcdf88f62b0 1762 * @brief Enable error IT
<> 128:9bcdf88f62b0 1763 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<> 128:9bcdf88f62b0 1764 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<> 128:9bcdf88f62b0 1765 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1766 * @retval None
<> 128:9bcdf88f62b0 1767 */
<> 128:9bcdf88f62b0 1768 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1769 {
<> 128:9bcdf88f62b0 1770 LL_SPI_EnableIT_ERR(SPIx);
<> 128:9bcdf88f62b0 1771 }
<> 128:9bcdf88f62b0 1772
<> 128:9bcdf88f62b0 1773 /**
<> 128:9bcdf88f62b0 1774 * @brief Enable Rx buffer not empty IT
<> 128:9bcdf88f62b0 1775 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<> 128:9bcdf88f62b0 1776 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1777 * @retval None
<> 128:9bcdf88f62b0 1778 */
<> 128:9bcdf88f62b0 1779 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1780 {
<> 128:9bcdf88f62b0 1781 LL_SPI_EnableIT_RXNE(SPIx);
<> 128:9bcdf88f62b0 1782 }
<> 128:9bcdf88f62b0 1783
<> 128:9bcdf88f62b0 1784 /**
<> 128:9bcdf88f62b0 1785 * @brief Enable Tx buffer empty IT
<> 128:9bcdf88f62b0 1786 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<> 128:9bcdf88f62b0 1787 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1788 * @retval None
<> 128:9bcdf88f62b0 1789 */
<> 128:9bcdf88f62b0 1790 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1791 {
<> 128:9bcdf88f62b0 1792 LL_SPI_EnableIT_TXE(SPIx);
<> 128:9bcdf88f62b0 1793 }
<> 128:9bcdf88f62b0 1794
<> 128:9bcdf88f62b0 1795 /**
<> 128:9bcdf88f62b0 1796 * @brief Disable Error IT
<> 128:9bcdf88f62b0 1797 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<> 128:9bcdf88f62b0 1798 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<> 128:9bcdf88f62b0 1799 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1800 * @retval None
<> 128:9bcdf88f62b0 1801 */
<> 128:9bcdf88f62b0 1802 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1803 {
<> 128:9bcdf88f62b0 1804 LL_SPI_DisableIT_ERR(SPIx);
<> 128:9bcdf88f62b0 1805 }
<> 128:9bcdf88f62b0 1806
<> 128:9bcdf88f62b0 1807 /**
<> 128:9bcdf88f62b0 1808 * @brief Disable Rx buffer not empty IT
<> 128:9bcdf88f62b0 1809 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<> 128:9bcdf88f62b0 1810 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1811 * @retval None
<> 128:9bcdf88f62b0 1812 */
<> 128:9bcdf88f62b0 1813 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1814 {
<> 128:9bcdf88f62b0 1815 LL_SPI_DisableIT_RXNE(SPIx);
<> 128:9bcdf88f62b0 1816 }
<> 128:9bcdf88f62b0 1817
<> 128:9bcdf88f62b0 1818 /**
<> 128:9bcdf88f62b0 1819 * @brief Disable Tx buffer empty IT
<> 128:9bcdf88f62b0 1820 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<> 128:9bcdf88f62b0 1821 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1822 * @retval None
<> 128:9bcdf88f62b0 1823 */
<> 128:9bcdf88f62b0 1824 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1825 {
<> 128:9bcdf88f62b0 1826 LL_SPI_DisableIT_TXE(SPIx);
<> 128:9bcdf88f62b0 1827 }
<> 128:9bcdf88f62b0 1828
<> 128:9bcdf88f62b0 1829 /**
<> 128:9bcdf88f62b0 1830 * @brief Check if ERR IT is enabled
<> 128:9bcdf88f62b0 1831 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<> 128:9bcdf88f62b0 1832 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1833 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1834 */
<> 128:9bcdf88f62b0 1835 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1836 {
<> 128:9bcdf88f62b0 1837 return LL_SPI_IsEnabledIT_ERR(SPIx);
<> 128:9bcdf88f62b0 1838 }
<> 128:9bcdf88f62b0 1839
<> 128:9bcdf88f62b0 1840 /**
<> 128:9bcdf88f62b0 1841 * @brief Check if RXNE IT is enabled
<> 128:9bcdf88f62b0 1842 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<> 128:9bcdf88f62b0 1843 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1844 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1845 */
<> 128:9bcdf88f62b0 1846 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1847 {
<> 128:9bcdf88f62b0 1848 return LL_SPI_IsEnabledIT_RXNE(SPIx);
<> 128:9bcdf88f62b0 1849 }
<> 128:9bcdf88f62b0 1850
<> 128:9bcdf88f62b0 1851 /**
<> 128:9bcdf88f62b0 1852 * @brief Check if TXE IT is enabled
<> 128:9bcdf88f62b0 1853 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<> 128:9bcdf88f62b0 1854 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1855 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1856 */
<> 128:9bcdf88f62b0 1857 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1858 {
<> 128:9bcdf88f62b0 1859 return LL_SPI_IsEnabledIT_TXE(SPIx);
<> 128:9bcdf88f62b0 1860 }
<> 128:9bcdf88f62b0 1861
<> 128:9bcdf88f62b0 1862 /**
<> 128:9bcdf88f62b0 1863 * @}
<> 128:9bcdf88f62b0 1864 */
<> 128:9bcdf88f62b0 1865
<> 128:9bcdf88f62b0 1866 /** @defgroup I2S_LL_EF_DMA DMA Management
<> 128:9bcdf88f62b0 1867 * @{
<> 128:9bcdf88f62b0 1868 */
<> 128:9bcdf88f62b0 1869
<> 128:9bcdf88f62b0 1870 /**
<> 128:9bcdf88f62b0 1871 * @brief Enable DMA Rx
<> 128:9bcdf88f62b0 1872 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<> 128:9bcdf88f62b0 1873 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1874 * @retval None
<> 128:9bcdf88f62b0 1875 */
<> 128:9bcdf88f62b0 1876 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1877 {
<> 128:9bcdf88f62b0 1878 LL_SPI_EnableDMAReq_RX(SPIx);
<> 128:9bcdf88f62b0 1879 }
<> 128:9bcdf88f62b0 1880
<> 128:9bcdf88f62b0 1881 /**
<> 128:9bcdf88f62b0 1882 * @brief Disable DMA Rx
<> 128:9bcdf88f62b0 1883 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<> 128:9bcdf88f62b0 1884 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1885 * @retval None
<> 128:9bcdf88f62b0 1886 */
<> 128:9bcdf88f62b0 1887 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1888 {
<> 128:9bcdf88f62b0 1889 LL_SPI_DisableDMAReq_RX(SPIx);
<> 128:9bcdf88f62b0 1890 }
<> 128:9bcdf88f62b0 1891
<> 128:9bcdf88f62b0 1892 /**
<> 128:9bcdf88f62b0 1893 * @brief Check if DMA Rx is enabled
<> 128:9bcdf88f62b0 1894 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<> 128:9bcdf88f62b0 1895 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1896 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1897 */
<> 128:9bcdf88f62b0 1898 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1899 {
<> 128:9bcdf88f62b0 1900 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<> 128:9bcdf88f62b0 1901 }
<> 128:9bcdf88f62b0 1902
<> 128:9bcdf88f62b0 1903 /**
<> 128:9bcdf88f62b0 1904 * @brief Enable DMA Tx
<> 128:9bcdf88f62b0 1905 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<> 128:9bcdf88f62b0 1906 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1907 * @retval None
<> 128:9bcdf88f62b0 1908 */
<> 128:9bcdf88f62b0 1909 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1910 {
<> 128:9bcdf88f62b0 1911 LL_SPI_EnableDMAReq_TX(SPIx);
<> 128:9bcdf88f62b0 1912 }
<> 128:9bcdf88f62b0 1913
<> 128:9bcdf88f62b0 1914 /**
<> 128:9bcdf88f62b0 1915 * @brief Disable DMA Tx
<> 128:9bcdf88f62b0 1916 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<> 128:9bcdf88f62b0 1917 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1918 * @retval None
<> 128:9bcdf88f62b0 1919 */
<> 128:9bcdf88f62b0 1920 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1921 {
<> 128:9bcdf88f62b0 1922 LL_SPI_DisableDMAReq_TX(SPIx);
<> 128:9bcdf88f62b0 1923 }
<> 128:9bcdf88f62b0 1924
<> 128:9bcdf88f62b0 1925 /**
<> 128:9bcdf88f62b0 1926 * @brief Check if DMA Tx is enabled
<> 128:9bcdf88f62b0 1927 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<> 128:9bcdf88f62b0 1928 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1929 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 1930 */
<> 128:9bcdf88f62b0 1931 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1932 {
<> 128:9bcdf88f62b0 1933 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<> 128:9bcdf88f62b0 1934 }
<> 128:9bcdf88f62b0 1935
<> 128:9bcdf88f62b0 1936 /**
<> 128:9bcdf88f62b0 1937 * @}
<> 128:9bcdf88f62b0 1938 */
<> 128:9bcdf88f62b0 1939
<> 128:9bcdf88f62b0 1940 /** @defgroup I2S_LL_EF_DATA DATA Management
<> 128:9bcdf88f62b0 1941 * @{
<> 128:9bcdf88f62b0 1942 */
<> 128:9bcdf88f62b0 1943
<> 128:9bcdf88f62b0 1944 /**
<> 128:9bcdf88f62b0 1945 * @brief Read 16-Bits in data register
<> 128:9bcdf88f62b0 1946 * @rmtoll DR DR LL_I2S_ReceiveData16
<> 128:9bcdf88f62b0 1947 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1948 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<> 128:9bcdf88f62b0 1949 */
<> 128:9bcdf88f62b0 1950 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<> 128:9bcdf88f62b0 1951 {
<> 128:9bcdf88f62b0 1952 return LL_SPI_ReceiveData16(SPIx);
<> 128:9bcdf88f62b0 1953 }
<> 128:9bcdf88f62b0 1954
<> 128:9bcdf88f62b0 1955 /**
<> 128:9bcdf88f62b0 1956 * @brief Write 16-Bits in data register
<> 128:9bcdf88f62b0 1957 * @rmtoll DR DR LL_I2S_TransmitData16
<> 128:9bcdf88f62b0 1958 * @param SPIx SPI Instance
<> 128:9bcdf88f62b0 1959 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<> 128:9bcdf88f62b0 1960 * @retval None
<> 128:9bcdf88f62b0 1961 */
<> 128:9bcdf88f62b0 1962 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<> 128:9bcdf88f62b0 1963 {
<> 128:9bcdf88f62b0 1964 LL_SPI_TransmitData16(SPIx, TxData);
<> 128:9bcdf88f62b0 1965 }
<> 128:9bcdf88f62b0 1966
<> 128:9bcdf88f62b0 1967 /**
<> 128:9bcdf88f62b0 1968 * @}
<> 128:9bcdf88f62b0 1969 */
<> 128:9bcdf88f62b0 1970
<> 128:9bcdf88f62b0 1971 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 1972 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<> 128:9bcdf88f62b0 1973 * @{
<> 128:9bcdf88f62b0 1974 */
<> 128:9bcdf88f62b0 1975
<> 128:9bcdf88f62b0 1976 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<> 128:9bcdf88f62b0 1977 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
<> 128:9bcdf88f62b0 1978 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<> 128:9bcdf88f62b0 1979 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<> 128:9bcdf88f62b0 1980
<> 128:9bcdf88f62b0 1981 /**
<> 128:9bcdf88f62b0 1982 * @}
<> 128:9bcdf88f62b0 1983 */
<> 128:9bcdf88f62b0 1984 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 1985
<> 128:9bcdf88f62b0 1986 /**
<> 128:9bcdf88f62b0 1987 * @}
<> 128:9bcdf88f62b0 1988 */
<> 128:9bcdf88f62b0 1989
<> 128:9bcdf88f62b0 1990 /**
<> 128:9bcdf88f62b0 1991 * @}
<> 128:9bcdf88f62b0 1992 */
<> 128:9bcdf88f62b0 1993 #endif /* SPI_I2S_SUPPORT */
<> 128:9bcdf88f62b0 1994
<> 128:9bcdf88f62b0 1995 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
<> 128:9bcdf88f62b0 1996
<> 128:9bcdf88f62b0 1997 /**
<> 128:9bcdf88f62b0 1998 * @}
<> 128:9bcdf88f62b0 1999 */
<> 128:9bcdf88f62b0 2000
<> 128:9bcdf88f62b0 2001 #ifdef __cplusplus
<> 128:9bcdf88f62b0 2002 }
<> 128:9bcdf88f62b0 2003 #endif
<> 128:9bcdf88f62b0 2004
<> 128:9bcdf88f62b0 2005 #endif /* __STM32L1xx_LL_SPI_H */
<> 128:9bcdf88f62b0 2006
<> 128:9bcdf88f62b0 2007 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/