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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_sdmmc.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of SDMMC HAL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_SD_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_SD_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#if defined(STM32L151xD) \|\| defined(STM32L152xD) \|\| defined(STM32L162xD)
<>	128:9bcdf88f62b0	43
<>	128:9bcdf88f62b0	44	#ifdef __cplusplus
<>	128:9bcdf88f62b0	45	extern "C" {
<>	128:9bcdf88f62b0	46	#endif
<>	128:9bcdf88f62b0	47
<>	128:9bcdf88f62b0	48	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	49	#include "stm32l1xx_hal_def.h"
<>	128:9bcdf88f62b0	50
<>	128:9bcdf88f62b0	51	/** @addtogroup STM32L1xx_HAL_Driver
<>	128:9bcdf88f62b0	52	* @{
<>	128:9bcdf88f62b0	53	*/
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @addtogroup SDMMC_LL
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<>	128:9bcdf88f62b0	61	* @{
<>	128:9bcdf88f62b0	62	*/
<>	128:9bcdf88f62b0	63
<>	128:9bcdf88f62b0	64	/**
<>	128:9bcdf88f62b0	65	* @brief SDMMC Configuration Structure definition
<>	128:9bcdf88f62b0	66	*/
<>	128:9bcdf88f62b0	67	typedef struct
<>	128:9bcdf88f62b0	68	{
<>	128:9bcdf88f62b0	69	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<>	128:9bcdf88f62b0	70	This parameter can be a value of @ref SDIO_Clock_Edge */
<>	128:9bcdf88f62b0	71
<>	128:9bcdf88f62b0	72	uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
<>	128:9bcdf88f62b0	73	enabled or disabled.
<>	128:9bcdf88f62b0	74	This parameter can be a value of @ref SDIO_Clock_Bypass */
<>	128:9bcdf88f62b0	75
<>	128:9bcdf88f62b0	76	uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
<>	128:9bcdf88f62b0	77	disabled when the bus is idle.
<>	128:9bcdf88f62b0	78	This parameter can be a value of @ref SDIO_Clock_Power_Save */
<>	128:9bcdf88f62b0	79
<>	128:9bcdf88f62b0	80	uint32_t BusWide; /*!< Specifies the SDIO bus width.
<>	128:9bcdf88f62b0	81	This parameter can be a value of @ref SDIO_Bus_Wide */
<>	128:9bcdf88f62b0	82
<>	128:9bcdf88f62b0	83	uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
<>	128:9bcdf88f62b0	84	This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
<>	128:9bcdf88f62b0	85
<>	128:9bcdf88f62b0	86	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
<>	128:9bcdf88f62b0	87	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<>	128:9bcdf88f62b0	88
<>	128:9bcdf88f62b0	89	}SDIO_InitTypeDef;
<>	128:9bcdf88f62b0	90
<>	128:9bcdf88f62b0	91
<>	128:9bcdf88f62b0	92	/**
<>	128:9bcdf88f62b0	93	* @brief SDIO Command Control structure
<>	128:9bcdf88f62b0	94	*/
<>	128:9bcdf88f62b0	95	typedef struct
<>	128:9bcdf88f62b0	96	{
<>	128:9bcdf88f62b0	97	uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
<>	128:9bcdf88f62b0	98	to a card as part of a command message. If a command
<>	128:9bcdf88f62b0	99	contains an argument, it must be loaded into this register
<>	128:9bcdf88f62b0	100	before writing the command to the command register. */
<>	128:9bcdf88f62b0	101
<>	128:9bcdf88f62b0	102	uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
<>	128:9bcdf88f62b0	103	Max_Data = 64 */
<>	128:9bcdf88f62b0	104
<>	128:9bcdf88f62b0	105	uint32_t Response; /*!< Specifies the SDIO response type.
<>	128:9bcdf88f62b0	106	This parameter can be a value of @ref SDIO_Response_Type */
<>	128:9bcdf88f62b0	107
<>	128:9bcdf88f62b0	108	uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
<>	128:9bcdf88f62b0	109	enabled or disabled.
<>	128:9bcdf88f62b0	110	This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
<>	128:9bcdf88f62b0	111
<>	128:9bcdf88f62b0	112	uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
<>	128:9bcdf88f62b0	113	is enabled or disabled.
<>	128:9bcdf88f62b0	114	This parameter can be a value of @ref SDIO_CPSM_State */
<>	128:9bcdf88f62b0	115	}SDIO_CmdInitTypeDef;
<>	128:9bcdf88f62b0	116
<>	128:9bcdf88f62b0	117
<>	128:9bcdf88f62b0	118	/**
<>	128:9bcdf88f62b0	119	* @brief SDIO Data Control structure
<>	128:9bcdf88f62b0	120	*/
<>	128:9bcdf88f62b0	121	typedef struct
<>	128:9bcdf88f62b0	122	{
<>	128:9bcdf88f62b0	123	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
<>	128:9bcdf88f62b0	124
<>	128:9bcdf88f62b0	125	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
<>	128:9bcdf88f62b0	126
<>	128:9bcdf88f62b0	127	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<>	128:9bcdf88f62b0	128	This parameter can be a value of @ref SDIO_Data_Block_Size */
<>	128:9bcdf88f62b0	129
<>	128:9bcdf88f62b0	130	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<>	128:9bcdf88f62b0	131	is a read or write.
<>	128:9bcdf88f62b0	132	This parameter can be a value of @ref SDIO_Transfer_Direction */
<>	128:9bcdf88f62b0	133
<>	128:9bcdf88f62b0	134	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<>	128:9bcdf88f62b0	135	This parameter can be a value of @ref SDIO_Transfer_Type */
<>	128:9bcdf88f62b0	136
<>	128:9bcdf88f62b0	137	uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
<>	128:9bcdf88f62b0	138	is enabled or disabled.
<>	128:9bcdf88f62b0	139	This parameter can be a value of @ref SDIO_DPSM_State */
<>	128:9bcdf88f62b0	140	}SDIO_DataInitTypeDef;
<>	128:9bcdf88f62b0	141
<>	128:9bcdf88f62b0	142	/**
<>	128:9bcdf88f62b0	143	* @}
<>	128:9bcdf88f62b0	144	*/
<>	128:9bcdf88f62b0	145
<>	128:9bcdf88f62b0	146	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	147	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<>	128:9bcdf88f62b0	148	* @{
<>	128:9bcdf88f62b0	149	*/
<>	128:9bcdf88f62b0	150
<>	128:9bcdf88f62b0	151	/** @defgroup SDIO_Clock_Edge Clock Edge
<>	128:9bcdf88f62b0	152	* @{
<>	128:9bcdf88f62b0	153	*/
<>	128:9bcdf88f62b0	154	#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	155	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
<>	128:9bcdf88f62b0	156
<>	128:9bcdf88f62b0	157	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
<>	128:9bcdf88f62b0	158	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
<>	128:9bcdf88f62b0	159	/**
<>	128:9bcdf88f62b0	160	* @}
<>	128:9bcdf88f62b0	161	*/
<>	128:9bcdf88f62b0	162
<>	128:9bcdf88f62b0	163	/** @defgroup SDIO_Clock_Bypass Clock Bypass
<>	128:9bcdf88f62b0	164	* @{
<>	128:9bcdf88f62b0	165	*/
<>	128:9bcdf88f62b0	166	#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	167	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
<>	128:9bcdf88f62b0	168
<>	128:9bcdf88f62b0	169	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
<>	128:9bcdf88f62b0	170	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
<>	128:9bcdf88f62b0	171	/**
<>	128:9bcdf88f62b0	172	* @}
<>	128:9bcdf88f62b0	173	*/
<>	128:9bcdf88f62b0	174
<>	128:9bcdf88f62b0	175	/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
<>	128:9bcdf88f62b0	176	* @{
<>	128:9bcdf88f62b0	177	*/
<>	128:9bcdf88f62b0	178	#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	179	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
<>	128:9bcdf88f62b0	180
<>	128:9bcdf88f62b0	181	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
<>	128:9bcdf88f62b0	182	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
<>	128:9bcdf88f62b0	183	/**
<>	128:9bcdf88f62b0	184	* @}
<>	128:9bcdf88f62b0	185	*/
<>	128:9bcdf88f62b0	186
<>	128:9bcdf88f62b0	187	/** @defgroup SDIO_Bus_Wide Bus Width
<>	128:9bcdf88f62b0	188	* @{
<>	128:9bcdf88f62b0	189	*/
<>	128:9bcdf88f62b0	190	#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	191	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
<>	128:9bcdf88f62b0	192	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
<>	128:9bcdf88f62b0	193
<>	128:9bcdf88f62b0	194	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
<>	128:9bcdf88f62b0	195	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
<>	128:9bcdf88f62b0	196	((WIDE) == SDIO_BUS_WIDE_8B))
<>	128:9bcdf88f62b0	197	/**
<>	128:9bcdf88f62b0	198	* @}
<>	128:9bcdf88f62b0	199	*/
<>	128:9bcdf88f62b0	200
<>	128:9bcdf88f62b0	201	/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
<>	128:9bcdf88f62b0	202	* @{
<>	128:9bcdf88f62b0	203	*/
<>	128:9bcdf88f62b0	204	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	205	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
<>	128:9bcdf88f62b0	206
<>	128:9bcdf88f62b0	207	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
<>	128:9bcdf88f62b0	208	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
<>	128:9bcdf88f62b0	209	/**
<>	128:9bcdf88f62b0	210	* @}
<>	128:9bcdf88f62b0	211	*/
<>	128:9bcdf88f62b0	212
<>	128:9bcdf88f62b0	213	/** @defgroup SDIO_Clock_Division Clock Division
<>	128:9bcdf88f62b0	214	* @{
<>	128:9bcdf88f62b0	215	*/
<>	128:9bcdf88f62b0	216	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
<>	128:9bcdf88f62b0	217	/**
<>	128:9bcdf88f62b0	218	* @}
<>	128:9bcdf88f62b0	219	*/
<>	128:9bcdf88f62b0	220
<>	128:9bcdf88f62b0	221	/** @defgroup SDIO_Command_Index Command Index
<>	128:9bcdf88f62b0	222	* @{
<>	128:9bcdf88f62b0	223	*/
<>	128:9bcdf88f62b0	224	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<>	128:9bcdf88f62b0	225	/**
<>	128:9bcdf88f62b0	226	* @}
<>	128:9bcdf88f62b0	227	*/
<>	128:9bcdf88f62b0	228
<>	128:9bcdf88f62b0	229	/** @defgroup SDIO_Response_Type Response Type
<>	128:9bcdf88f62b0	230	* @{
<>	128:9bcdf88f62b0	231	*/
<>	128:9bcdf88f62b0	232	#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	233	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
<>	128:9bcdf88f62b0	234	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
<>	128:9bcdf88f62b0	235
<>	128:9bcdf88f62b0	236	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
<>	128:9bcdf88f62b0	237	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
<>	128:9bcdf88f62b0	238	((RESPONSE) == SDIO_RESPONSE_LONG))
<>	128:9bcdf88f62b0	239	/**
<>	128:9bcdf88f62b0	240	* @}
<>	128:9bcdf88f62b0	241	*/
<>	128:9bcdf88f62b0	242
<>	128:9bcdf88f62b0	243	/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
<>	128:9bcdf88f62b0	244	* @{
<>	128:9bcdf88f62b0	245	*/
<>	128:9bcdf88f62b0	246	#define SDIO_WAIT_NO ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	247	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
<>	128:9bcdf88f62b0	248	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
<>	128:9bcdf88f62b0	249
<>	128:9bcdf88f62b0	250	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
<>	128:9bcdf88f62b0	251	((WAIT) == SDIO_WAIT_IT) \|\| \
<>	128:9bcdf88f62b0	252	((WAIT) == SDIO_WAIT_PEND))
<>	128:9bcdf88f62b0	253	/**
<>	128:9bcdf88f62b0	254	* @}
<>	128:9bcdf88f62b0	255	*/
<>	128:9bcdf88f62b0	256
<>	128:9bcdf88f62b0	257	/** @defgroup SDIO_CPSM_State CPSM State
<>	128:9bcdf88f62b0	258	* @{
<>	128:9bcdf88f62b0	259	*/
<>	128:9bcdf88f62b0	260	#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	261	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
<>	128:9bcdf88f62b0	262
<>	128:9bcdf88f62b0	263	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
<>	128:9bcdf88f62b0	264	((CPSM) == SDIO_CPSM_ENABLE))
<>	128:9bcdf88f62b0	265	/**
<>	128:9bcdf88f62b0	266	* @}
<>	128:9bcdf88f62b0	267	*/
<>	128:9bcdf88f62b0	268
<>	128:9bcdf88f62b0	269	/** @defgroup SDIO_Response_Registers Response Register
<>	128:9bcdf88f62b0	270	* @{
<>	128:9bcdf88f62b0	271	*/
<>	128:9bcdf88f62b0	272	#define SDIO_RESP1 ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	273	#define SDIO_RESP2 ((uint32_t)0x00000004)
<>	128:9bcdf88f62b0	274	#define SDIO_RESP3 ((uint32_t)0x00000008)
<>	128:9bcdf88f62b0	275	#define SDIO_RESP4 ((uint32_t)0x0000000C)
<>	128:9bcdf88f62b0	276
<>	128:9bcdf88f62b0	277	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
<>	128:9bcdf88f62b0	278	((RESP) == SDIO_RESP2) \|\| \
<>	128:9bcdf88f62b0	279	((RESP) == SDIO_RESP3) \|\| \
<>	128:9bcdf88f62b0	280	((RESP) == SDIO_RESP4))
<>	128:9bcdf88f62b0	281	/**
<>	128:9bcdf88f62b0	282	* @}
<>	128:9bcdf88f62b0	283	*/
<>	128:9bcdf88f62b0	284
<>	128:9bcdf88f62b0	285	/** @defgroup SDIO_Data_Length Data Lenght
<>	128:9bcdf88f62b0	286	* @{
<>	128:9bcdf88f62b0	287	*/
<>	128:9bcdf88f62b0	288	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
<>	128:9bcdf88f62b0	289	/**
<>	128:9bcdf88f62b0	290	* @}
<>	128:9bcdf88f62b0	291	*/
<>	128:9bcdf88f62b0	292
<>	128:9bcdf88f62b0	293	/** @defgroup SDIO_Data_Block_Size Data Block Size
<>	128:9bcdf88f62b0	294	* @{
<>	128:9bcdf88f62b0	295	*/
<>	128:9bcdf88f62b0	296	#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	297	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
<>	128:9bcdf88f62b0	298	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
<>	128:9bcdf88f62b0	299	#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
<>	128:9bcdf88f62b0	300	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
<>	128:9bcdf88f62b0	301	#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
<>	128:9bcdf88f62b0	302	#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
<>	128:9bcdf88f62b0	303	#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
<>	128:9bcdf88f62b0	304	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
<>	128:9bcdf88f62b0	305	#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
<>	128:9bcdf88f62b0	306	#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
<>	128:9bcdf88f62b0	307	#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
<>	128:9bcdf88f62b0	308	#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
<>	128:9bcdf88f62b0	309	#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
<>	128:9bcdf88f62b0	310	#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
<>	128:9bcdf88f62b0	311
<>	128:9bcdf88f62b0	312	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
<>	128:9bcdf88f62b0	313	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
<>	128:9bcdf88f62b0	314	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
<>	128:9bcdf88f62b0	315	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
<>	128:9bcdf88f62b0	316	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
<>	128:9bcdf88f62b0	317	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
<>	128:9bcdf88f62b0	318	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
<>	128:9bcdf88f62b0	319	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
<>	128:9bcdf88f62b0	320	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
<>	128:9bcdf88f62b0	321	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
<>	128:9bcdf88f62b0	322	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
<>	128:9bcdf88f62b0	323	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
<>	128:9bcdf88f62b0	324	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
<>	128:9bcdf88f62b0	325	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
<>	128:9bcdf88f62b0	326	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
<>	128:9bcdf88f62b0	327	/**
<>	128:9bcdf88f62b0	328	* @}
<>	128:9bcdf88f62b0	329	*/
<>	128:9bcdf88f62b0	330
<>	128:9bcdf88f62b0	331	/** @defgroup SDIO_Transfer_Direction Transfer Direction
<>	128:9bcdf88f62b0	332	* @{
<>	128:9bcdf88f62b0	333	*/
<>	128:9bcdf88f62b0	334	#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	335	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
<>	128:9bcdf88f62b0	336
<>	128:9bcdf88f62b0	337	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
<>	128:9bcdf88f62b0	338	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
<>	128:9bcdf88f62b0	339	/**
<>	128:9bcdf88f62b0	340	* @}
<>	128:9bcdf88f62b0	341	*/
<>	128:9bcdf88f62b0	342
<>	128:9bcdf88f62b0	343	/** @defgroup SDIO_Transfer_Type Transfer Type
<>	128:9bcdf88f62b0	344	* @{
<>	128:9bcdf88f62b0	345	*/
<>	128:9bcdf88f62b0	346	#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	347	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
<>	128:9bcdf88f62b0	348
<>	128:9bcdf88f62b0	349	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
<>	128:9bcdf88f62b0	350	((MODE) == SDIO_TRANSFER_MODE_STREAM))
<>	128:9bcdf88f62b0	351	/**
<>	128:9bcdf88f62b0	352	* @}
<>	128:9bcdf88f62b0	353	*/
<>	128:9bcdf88f62b0	354
<>	128:9bcdf88f62b0	355	/** @defgroup SDIO_DPSM_State DPSM State
<>	128:9bcdf88f62b0	356	* @{
<>	128:9bcdf88f62b0	357	*/
<>	128:9bcdf88f62b0	358	#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	359	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
<>	128:9bcdf88f62b0	360
<>	128:9bcdf88f62b0	361	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
<>	128:9bcdf88f62b0	362	((DPSM) == SDIO_DPSM_ENABLE))
<>	128:9bcdf88f62b0	363	/**
<>	128:9bcdf88f62b0	364	* @}
<>	128:9bcdf88f62b0	365	*/
<>	128:9bcdf88f62b0	366
<>	128:9bcdf88f62b0	367	/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
<>	128:9bcdf88f62b0	368	* @{
<>	128:9bcdf88f62b0	369	*/
<>	128:9bcdf88f62b0	370	#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	371	#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
<>	128:9bcdf88f62b0	372
<>	128:9bcdf88f62b0	373	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
<>	128:9bcdf88f62b0	374	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
<>	128:9bcdf88f62b0	375	/**
<>	128:9bcdf88f62b0	376	* @}
<>	128:9bcdf88f62b0	377	*/
<>	128:9bcdf88f62b0	378
<>	128:9bcdf88f62b0	379	/** @defgroup SDIO_Interrupt_sources Interrupt Sources
<>	128:9bcdf88f62b0	380	* @{
<>	128:9bcdf88f62b0	381	*/
<>	128:9bcdf88f62b0	382	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
<>	128:9bcdf88f62b0	383	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
<>	128:9bcdf88f62b0	384	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
<>	128:9bcdf88f62b0	385	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
<>	128:9bcdf88f62b0	386	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
<>	128:9bcdf88f62b0	387	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
<>	128:9bcdf88f62b0	388	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
<>	128:9bcdf88f62b0	389	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
<>	128:9bcdf88f62b0	390	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
<>	128:9bcdf88f62b0	391	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
<>	128:9bcdf88f62b0	392	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
<>	128:9bcdf88f62b0	393	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
<>	128:9bcdf88f62b0	394	#define SDIO_IT_TXACT SDIO_STA_TXACT
<>	128:9bcdf88f62b0	395	#define SDIO_IT_RXACT SDIO_STA_RXACT
<>	128:9bcdf88f62b0	396	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
<>	128:9bcdf88f62b0	397	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
<>	128:9bcdf88f62b0	398	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
<>	128:9bcdf88f62b0	399	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
<>	128:9bcdf88f62b0	400	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
<>	128:9bcdf88f62b0	401	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
<>	128:9bcdf88f62b0	402	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
<>	128:9bcdf88f62b0	403	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
<>	128:9bcdf88f62b0	404	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
<>	128:9bcdf88f62b0	405	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
<>	128:9bcdf88f62b0	406	/**
<>	128:9bcdf88f62b0	407	* @}
<>	128:9bcdf88f62b0	408	*/
<>	128:9bcdf88f62b0	409
<>	128:9bcdf88f62b0	410	/** @defgroup SDIO_Flags Flags
<>	128:9bcdf88f62b0	411	* @{
<>	128:9bcdf88f62b0	412	*/
<>	128:9bcdf88f62b0	413	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
<>	128:9bcdf88f62b0	414	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
<>	128:9bcdf88f62b0	415	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
<>	128:9bcdf88f62b0	416	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
<>	128:9bcdf88f62b0	417	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
<>	128:9bcdf88f62b0	418	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
<>	128:9bcdf88f62b0	419	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
<>	128:9bcdf88f62b0	420	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
<>	128:9bcdf88f62b0	421	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
<>	128:9bcdf88f62b0	422	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
<>	128:9bcdf88f62b0	423	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
<>	128:9bcdf88f62b0	424	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
<>	128:9bcdf88f62b0	425	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
<>	128:9bcdf88f62b0	426	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
<>	128:9bcdf88f62b0	427	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
<>	128:9bcdf88f62b0	428	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
<>	128:9bcdf88f62b0	429	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
<>	128:9bcdf88f62b0	430	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
<>	128:9bcdf88f62b0	431	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
<>	128:9bcdf88f62b0	432	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
<>	128:9bcdf88f62b0	433	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
<>	128:9bcdf88f62b0	434	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
<>	128:9bcdf88f62b0	435	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
<>	128:9bcdf88f62b0	436	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
<>	128:9bcdf88f62b0	437	/**
<>	128:9bcdf88f62b0	438	* @}
<>	128:9bcdf88f62b0	439	*/
<>	128:9bcdf88f62b0	440
<>	128:9bcdf88f62b0	441	/**
<>	128:9bcdf88f62b0	442	* @}
<>	128:9bcdf88f62b0	443	*/
<>	128:9bcdf88f62b0	444	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	445	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
<>	128:9bcdf88f62b0	446	* @{
<>	128:9bcdf88f62b0	447	*/
<>	128:9bcdf88f62b0	448
<>	128:9bcdf88f62b0	449	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
<>	128:9bcdf88f62b0	450	* @{
<>	128:9bcdf88f62b0	451	*/
<>	128:9bcdf88f62b0	452	/* ------------ SDIO registers bit address in the alias region -------------- */
<>	128:9bcdf88f62b0	453	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
<>	128:9bcdf88f62b0	454
<>	128:9bcdf88f62b0	455	/* --- CLKCR Register ---*/
<>	128:9bcdf88f62b0	456	/* Alias word address of CLKEN bit */
<>	128:9bcdf88f62b0	457	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
<>	128:9bcdf88f62b0	458	#define CLKEN_BITNUMBER 0x08
<>	128:9bcdf88f62b0	459	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
<>	128:9bcdf88f62b0	460
<>	128:9bcdf88f62b0	461	/* --- CMD Register ---*/
<>	128:9bcdf88f62b0	462	/* Alias word address of SDIOSUSPEND bit */
<>	128:9bcdf88f62b0	463	#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
<>	128:9bcdf88f62b0	464	#define SDIOSUSPEND_BITNUMBER 0x0B
<>	128:9bcdf88f62b0	465	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
<>	128:9bcdf88f62b0	466
<>	128:9bcdf88f62b0	467	/* Alias word address of ENCMDCOMPL bit */
<>	128:9bcdf88f62b0	468	#define ENCMDCOMPL_BITNUMBER 0x0C
<>	128:9bcdf88f62b0	469	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
<>	128:9bcdf88f62b0	470
<>	128:9bcdf88f62b0	471	/* Alias word address of NIEN bit */
<>	128:9bcdf88f62b0	472	#define NIEN_BITNUMBER 0x0D
<>	128:9bcdf88f62b0	473	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
<>	128:9bcdf88f62b0	474
<>	128:9bcdf88f62b0	475	/* Alias word address of ATACMD bit */
<>	128:9bcdf88f62b0	476	#define ATACMD_BITNUMBER 0x0E
<>	128:9bcdf88f62b0	477	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
<>	128:9bcdf88f62b0	478
<>	128:9bcdf88f62b0	479	/* --- DCTRL Register ---*/
<>	128:9bcdf88f62b0	480	/* Alias word address of DMAEN bit */
<>	128:9bcdf88f62b0	481	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
<>	128:9bcdf88f62b0	482	#define DMAEN_BITNUMBER 0x03
<>	128:9bcdf88f62b0	483	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
<>	128:9bcdf88f62b0	484
<>	128:9bcdf88f62b0	485	/* Alias word address of RWSTART bit */
<>	128:9bcdf88f62b0	486	#define RWSTART_BITNUMBER 0x08
<>	128:9bcdf88f62b0	487	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
<>	128:9bcdf88f62b0	488
<>	128:9bcdf88f62b0	489	/* Alias word address of RWSTOP bit */
<>	128:9bcdf88f62b0	490	#define RWSTOP_BITNUMBER 0x09
<>	128:9bcdf88f62b0	491	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
<>	128:9bcdf88f62b0	492
<>	128:9bcdf88f62b0	493	/* Alias word address of RWMOD bit */
<>	128:9bcdf88f62b0	494	#define RWMOD_BITNUMBER 0x0A
<>	128:9bcdf88f62b0	495	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
<>	128:9bcdf88f62b0	496
<>	128:9bcdf88f62b0	497	/* Alias word address of SDIOEN bit */
<>	128:9bcdf88f62b0	498	#define SDIOEN_BITNUMBER 0x0B
<>	128:9bcdf88f62b0	499	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
<>	128:9bcdf88f62b0	500	/**
<>	128:9bcdf88f62b0	501	* @}
<>	128:9bcdf88f62b0	502	*/
<>	128:9bcdf88f62b0	503
<>	128:9bcdf88f62b0	504	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
<>	128:9bcdf88f62b0	505	* @brief SDMMC_LL registers bit address in the alias region
<>	128:9bcdf88f62b0	506	* @{
<>	128:9bcdf88f62b0	507	*/
<>	128:9bcdf88f62b0	508
<>	128:9bcdf88f62b0	509	/* ---------------------- SDIO registers bit mask --------------------------- */
<>	128:9bcdf88f62b0	510	/* --- CLKCR Register ---*/
<>	128:9bcdf88f62b0	511	/* CLKCR register clear mask */
<>	128:9bcdf88f62b0	512	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
<>	128:9bcdf88f62b0	513	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
<>	128:9bcdf88f62b0	514	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
<>	128:9bcdf88f62b0	515
<>	128:9bcdf88f62b0	516	/* --- PWRCTRL Register ---*/
<>	128:9bcdf88f62b0	517	/* --- DCTRL Register ---*/
<>	128:9bcdf88f62b0	518	/* SDIO DCTRL Clear Mask */
<>	128:9bcdf88f62b0	519	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
<>	128:9bcdf88f62b0	520	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
<>	128:9bcdf88f62b0	521
<>	128:9bcdf88f62b0	522	/* --- CMD Register ---*/
<>	128:9bcdf88f62b0	523	/* CMD Register clear mask */
<>	128:9bcdf88f62b0	524	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
<>	128:9bcdf88f62b0	525	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
<>	128:9bcdf88f62b0	526	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
<>	128:9bcdf88f62b0	527
<>	128:9bcdf88f62b0	528	/* SDIO RESP Registers Address */
<>	128:9bcdf88f62b0	529	#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
<>	128:9bcdf88f62b0	530
<>	128:9bcdf88f62b0	531	/* SDIO Initialization Frequency (400KHz max) */
<>	128:9bcdf88f62b0	532	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
<>	128:9bcdf88f62b0	533
<>	128:9bcdf88f62b0	534	/* SDIO Data Transfer Frequency */
<>	128:9bcdf88f62b0	535	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
<>	128:9bcdf88f62b0	536
<>	128:9bcdf88f62b0	537	/**
<>	128:9bcdf88f62b0	538	* @}
<>	128:9bcdf88f62b0	539	*/
<>	128:9bcdf88f62b0	540
<>	128:9bcdf88f62b0	541	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
<>	128:9bcdf88f62b0	542	* @brief macros to handle interrupts and specific clock configurations
<>	128:9bcdf88f62b0	543	* @{
<>	128:9bcdf88f62b0	544	*/
<>	128:9bcdf88f62b0	545
<>	128:9bcdf88f62b0	546	/**
<>	128:9bcdf88f62b0	547	* @brief Enable the SDIO device.
<>	128:9bcdf88f62b0	548	* @retval None
<>	128:9bcdf88f62b0	549	*/
<>	128:9bcdf88f62b0	550	#define __SDIO_ENABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
<>	128:9bcdf88f62b0	551
<>	128:9bcdf88f62b0	552	/**
<>	128:9bcdf88f62b0	553	* @brief Disable the SDIO device.
<>	128:9bcdf88f62b0	554	* @retval None
<>	128:9bcdf88f62b0	555	*/
<>	128:9bcdf88f62b0	556	#define __SDIO_DISABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
<>	128:9bcdf88f62b0	557
<>	128:9bcdf88f62b0	558	/**
<>	128:9bcdf88f62b0	559	* @brief Enable the SDIO DMA transfer.
<>	128:9bcdf88f62b0	560	* @retval None
<>	128:9bcdf88f62b0	561	*/
<>	128:9bcdf88f62b0	562	#define __SDIO_DMA_ENABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
<>	128:9bcdf88f62b0	563
<>	128:9bcdf88f62b0	564	/**
<>	128:9bcdf88f62b0	565	* @brief Disable the SDIO DMA transfer.
<>	128:9bcdf88f62b0	566	* @retval None
<>	128:9bcdf88f62b0	567	*/
<>	128:9bcdf88f62b0	568	#define __SDIO_DMA_DISABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
<>	128:9bcdf88f62b0	569
<>	128:9bcdf88f62b0	570	/**
<>	128:9bcdf88f62b0	571	* @brief Enable the SDIO device interrupt.
<>	128:9bcdf88f62b0	572	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	573	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
<>	128:9bcdf88f62b0	574	* This parameter can be one or a combination of the following values:
<>	128:9bcdf88f62b0	575	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	576	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	577	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<>	128:9bcdf88f62b0	578	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<>	128:9bcdf88f62b0	579	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	128:9bcdf88f62b0	580	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<>	128:9bcdf88f62b0	581	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	582	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<>	128:9bcdf88f62b0	583	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	128:9bcdf88f62b0	584	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<>	128:9bcdf88f62b0	585	* bus mode interrupt
<>	128:9bcdf88f62b0	586	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	587	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<>	128:9bcdf88f62b0	588	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<>	128:9bcdf88f62b0	589	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
<>	128:9bcdf88f62b0	590	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	128:9bcdf88f62b0	591	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	128:9bcdf88f62b0	592	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<>	128:9bcdf88f62b0	593	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<>	128:9bcdf88f62b0	594	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	128:9bcdf88f62b0	595	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<>	128:9bcdf88f62b0	596	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	128:9bcdf88f62b0	597	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<>	128:9bcdf88f62b0	598	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<>	128:9bcdf88f62b0	599	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<>	128:9bcdf88f62b0	600	* @retval None
<>	128:9bcdf88f62b0	601	*/
<>	128:9bcdf88f62b0	602	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
<>	128:9bcdf88f62b0	603
<>	128:9bcdf88f62b0	604	/**
<>	128:9bcdf88f62b0	605	* @brief Disable the SDIO device interrupt.
<>	128:9bcdf88f62b0	606	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	607	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
<>	128:9bcdf88f62b0	608	* This parameter can be one or a combination of the following values:
<>	128:9bcdf88f62b0	609	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	610	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	611	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<>	128:9bcdf88f62b0	612	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<>	128:9bcdf88f62b0	613	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	128:9bcdf88f62b0	614	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<>	128:9bcdf88f62b0	615	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	616	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<>	128:9bcdf88f62b0	617	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	128:9bcdf88f62b0	618	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<>	128:9bcdf88f62b0	619	* bus mode interrupt
<>	128:9bcdf88f62b0	620	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	621	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<>	128:9bcdf88f62b0	622	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<>	128:9bcdf88f62b0	623	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
<>	128:9bcdf88f62b0	624	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	128:9bcdf88f62b0	625	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	128:9bcdf88f62b0	626	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<>	128:9bcdf88f62b0	627	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<>	128:9bcdf88f62b0	628	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	128:9bcdf88f62b0	629	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<>	128:9bcdf88f62b0	630	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	128:9bcdf88f62b0	631	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<>	128:9bcdf88f62b0	632	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<>	128:9bcdf88f62b0	633	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<>	128:9bcdf88f62b0	634	* @retval None
<>	128:9bcdf88f62b0	635	*/
<>	128:9bcdf88f62b0	636	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<>	128:9bcdf88f62b0	637
<>	128:9bcdf88f62b0	638	/**
<>	128:9bcdf88f62b0	639	* @brief Checks whether the specified SDIO flag is set or not.
<>	128:9bcdf88f62b0	640	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	641	* @param __FLAG__: specifies the flag to check.
<>	128:9bcdf88f62b0	642	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	643	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<>	128:9bcdf88f62b0	644	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<>	128:9bcdf88f62b0	645	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<>	128:9bcdf88f62b0	646	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
<>	128:9bcdf88f62b0	647	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<>	128:9bcdf88f62b0	648	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<>	128:9bcdf88f62b0	649	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<>	128:9bcdf88f62b0	650	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<>	128:9bcdf88f62b0	651	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<>	128:9bcdf88f62b0	652	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
<>	128:9bcdf88f62b0	653	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<>	128:9bcdf88f62b0	654	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
<>	128:9bcdf88f62b0	655	* @arg SDIO_FLAG_TXACT: Data transmit in progress
<>	128:9bcdf88f62b0	656	* @arg SDIO_FLAG_RXACT: Data receive in progress
<>	128:9bcdf88f62b0	657	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<>	128:9bcdf88f62b0	658	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<>	128:9bcdf88f62b0	659	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<>	128:9bcdf88f62b0	660	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<>	128:9bcdf88f62b0	661	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<>	128:9bcdf88f62b0	662	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<>	128:9bcdf88f62b0	663	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<>	128:9bcdf88f62b0	664	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<>	128:9bcdf88f62b0	665	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<>	128:9bcdf88f62b0	666	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<>	128:9bcdf88f62b0	667	* @retval The new state of SDIO_FLAG (SET or RESET).
<>	128:9bcdf88f62b0	668	*/
<>	128:9bcdf88f62b0	669	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<>	128:9bcdf88f62b0	670
<>	128:9bcdf88f62b0	671
<>	128:9bcdf88f62b0	672	/**
<>	128:9bcdf88f62b0	673	* @brief Clears the SDIO pending flags.
<>	128:9bcdf88f62b0	674	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	675	* @param __FLAG__: specifies the flag to clear.
<>	128:9bcdf88f62b0	676	* This parameter can be one or a combination of the following values:
<>	128:9bcdf88f62b0	677	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<>	128:9bcdf88f62b0	678	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<>	128:9bcdf88f62b0	679	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<>	128:9bcdf88f62b0	680	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
<>	128:9bcdf88f62b0	681	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<>	128:9bcdf88f62b0	682	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<>	128:9bcdf88f62b0	683	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<>	128:9bcdf88f62b0	684	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<>	128:9bcdf88f62b0	685	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<>	128:9bcdf88f62b0	686	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
<>	128:9bcdf88f62b0	687	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<>	128:9bcdf88f62b0	688	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<>	128:9bcdf88f62b0	689	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<>	128:9bcdf88f62b0	690	* @retval None
<>	128:9bcdf88f62b0	691	*/
<>	128:9bcdf88f62b0	692	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<>	128:9bcdf88f62b0	693
<>	128:9bcdf88f62b0	694	/**
<>	128:9bcdf88f62b0	695	* @brief Checks whether the specified SDIO interrupt has occurred or not.
<>	128:9bcdf88f62b0	696	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	697	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
<>	128:9bcdf88f62b0	698	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	699	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	700	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	701	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<>	128:9bcdf88f62b0	702	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<>	128:9bcdf88f62b0	703	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	128:9bcdf88f62b0	704	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<>	128:9bcdf88f62b0	705	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	706	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<>	128:9bcdf88f62b0	707	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	128:9bcdf88f62b0	708	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<>	128:9bcdf88f62b0	709	* bus mode interrupt
<>	128:9bcdf88f62b0	710	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	711	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<>	128:9bcdf88f62b0	712	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<>	128:9bcdf88f62b0	713	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
<>	128:9bcdf88f62b0	714	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	128:9bcdf88f62b0	715	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	128:9bcdf88f62b0	716	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<>	128:9bcdf88f62b0	717	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<>	128:9bcdf88f62b0	718	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	128:9bcdf88f62b0	719	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<>	128:9bcdf88f62b0	720	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	128:9bcdf88f62b0	721	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<>	128:9bcdf88f62b0	722	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<>	128:9bcdf88f62b0	723	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<>	128:9bcdf88f62b0	724	* @retval The new state of SDIO_IT (SET or RESET).
<>	128:9bcdf88f62b0	725	*/
<>	128:9bcdf88f62b0	726	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<>	128:9bcdf88f62b0	727
<>	128:9bcdf88f62b0	728	/**
<>	128:9bcdf88f62b0	729	* @brief Clears the SDIO's interrupt pending bits.
<>	128:9bcdf88f62b0	730	* @param __INSTANCE__ : Pointer to SDIO register base
<>	128:9bcdf88f62b0	731	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	128:9bcdf88f62b0	732	* This parameter can be one or a combination of the following values:
<>	128:9bcdf88f62b0	733	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	734	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	128:9bcdf88f62b0	735	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<>	128:9bcdf88f62b0	736	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<>	128:9bcdf88f62b0	737	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	128:9bcdf88f62b0	738	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<>	128:9bcdf88f62b0	739	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	128:9bcdf88f62b0	740	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<>	128:9bcdf88f62b0	741	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
<>	128:9bcdf88f62b0	742	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<>	128:9bcdf88f62b0	743	* bus mode interrupt
<>	128:9bcdf88f62b0	744	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<>	128:9bcdf88f62b0	745	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
<>	128:9bcdf88f62b0	746	* @retval None
<>	128:9bcdf88f62b0	747	*/
<>	128:9bcdf88f62b0	748	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<>	128:9bcdf88f62b0	749
<>	128:9bcdf88f62b0	750	/**
<>	128:9bcdf88f62b0	751	* @brief Enable Start the SD I/O Read Wait operation.
<>	128:9bcdf88f62b0	752	* @retval None
<>	128:9bcdf88f62b0	753	*/
<>	128:9bcdf88f62b0	754	#define __SDIO_START_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
<>	128:9bcdf88f62b0	755
<>	128:9bcdf88f62b0	756	/**
<>	128:9bcdf88f62b0	757	* @brief Disable Start the SD I/O Read Wait operations.
<>	128:9bcdf88f62b0	758	* @retval None
<>	128:9bcdf88f62b0	759	*/
<>	128:9bcdf88f62b0	760	#define __SDIO_START_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
<>	128:9bcdf88f62b0	761
<>	128:9bcdf88f62b0	762	/**
<>	128:9bcdf88f62b0	763	* @brief Enable Start the SD I/O Read Wait operation.
<>	128:9bcdf88f62b0	764	* @retval None
<>	128:9bcdf88f62b0	765	*/
<>	128:9bcdf88f62b0	766	#define __SDIO_STOP_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
<>	128:9bcdf88f62b0	767
<>	128:9bcdf88f62b0	768	/**
<>	128:9bcdf88f62b0	769	* @brief Disable Stop the SD I/O Read Wait operations.
<>	128:9bcdf88f62b0	770	* @retval None
<>	128:9bcdf88f62b0	771	*/
<>	128:9bcdf88f62b0	772	#define __SDIO_STOP_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
<>	128:9bcdf88f62b0	773
<>	128:9bcdf88f62b0	774	/**
<>	128:9bcdf88f62b0	775	* @brief Enable the SD I/O Mode Operation.
<>	128:9bcdf88f62b0	776	* @retval None
<>	128:9bcdf88f62b0	777	*/
<>	128:9bcdf88f62b0	778	#define __SDIO_OPERATION_ENABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
<>	128:9bcdf88f62b0	779
<>	128:9bcdf88f62b0	780	/**
<>	128:9bcdf88f62b0	781	* @brief Disable the SD I/O Mode Operation.
<>	128:9bcdf88f62b0	782	* @retval None
<>	128:9bcdf88f62b0	783	*/
<>	128:9bcdf88f62b0	784	#define __SDIO_OPERATION_DISABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
<>	128:9bcdf88f62b0	785
<>	128:9bcdf88f62b0	786	/**
<>	128:9bcdf88f62b0	787	* @brief Enable the SD I/O Suspend command sending.
<>	128:9bcdf88f62b0	788	* @retval None
<>	128:9bcdf88f62b0	789	*/
<>	128:9bcdf88f62b0	790	#define __SDIO_SUSPEND_CMD_ENABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
<>	128:9bcdf88f62b0	791
<>	128:9bcdf88f62b0	792	/**
<>	128:9bcdf88f62b0	793	* @brief Disable the SD I/O Suspend command sending.
<>	128:9bcdf88f62b0	794	* @retval None
<>	128:9bcdf88f62b0	795	*/
<>	128:9bcdf88f62b0	796	#define __SDIO_SUSPEND_CMD_DISABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
<>	128:9bcdf88f62b0	797
<>	128:9bcdf88f62b0	798	/**
<>	128:9bcdf88f62b0	799	* @brief Enable the command completion signal.
<>	128:9bcdf88f62b0	800	* @retval None
<>	128:9bcdf88f62b0	801	*/
<>	128:9bcdf88f62b0	802	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
<>	128:9bcdf88f62b0	803
<>	128:9bcdf88f62b0	804	/**
<>	128:9bcdf88f62b0	805	* @brief Disable the command completion signal.
<>	128:9bcdf88f62b0	806	* @retval None
<>	128:9bcdf88f62b0	807	*/
<>	128:9bcdf88f62b0	808	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
<>	128:9bcdf88f62b0	809
<>	128:9bcdf88f62b0	810	/**
<>	128:9bcdf88f62b0	811	* @brief Enable the CE-ATA interrupt.
<>	128:9bcdf88f62b0	812	* @retval None
<>	128:9bcdf88f62b0	813	*/
<>	128:9bcdf88f62b0	814	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0)
<>	128:9bcdf88f62b0	815
<>	128:9bcdf88f62b0	816	/**
<>	128:9bcdf88f62b0	817	* @brief Disable the CE-ATA interrupt.
<>	128:9bcdf88f62b0	818	* @retval None
<>	128:9bcdf88f62b0	819	*/
<>	128:9bcdf88f62b0	820	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1)
<>	128:9bcdf88f62b0	821
<>	128:9bcdf88f62b0	822	/**
<>	128:9bcdf88f62b0	823	* @brief Enable send CE-ATA command (CMD61).
<>	128:9bcdf88f62b0	824	* @retval None
<>	128:9bcdf88f62b0	825	*/
<>	128:9bcdf88f62b0	826	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
<>	128:9bcdf88f62b0	827
<>	128:9bcdf88f62b0	828	/**
<>	128:9bcdf88f62b0	829	* @brief Disable send CE-ATA command (CMD61).
<>	128:9bcdf88f62b0	830	* @retval None
<>	128:9bcdf88f62b0	831	*/
<>	128:9bcdf88f62b0	832	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
<>	128:9bcdf88f62b0	833
<>	128:9bcdf88f62b0	834	/**
<>	128:9bcdf88f62b0	835	* @}
<>	128:9bcdf88f62b0	836	*/
<>	128:9bcdf88f62b0	837
<>	128:9bcdf88f62b0	838	/**
<>	128:9bcdf88f62b0	839	* @}
<>	128:9bcdf88f62b0	840	*/
<>	128:9bcdf88f62b0	841
<>	128:9bcdf88f62b0	842	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	843	/** @addtogroup SDMMC_LL_Exported_Functions
<>	128:9bcdf88f62b0	844	* @{
<>	128:9bcdf88f62b0	845	*/
<>	128:9bcdf88f62b0	846
<>	128:9bcdf88f62b0	847	/* Initialization/de-initialization functions **********************************/
<>	128:9bcdf88f62b0	848	/** @addtogroup HAL_SDMMC_LL_Group1
<>	128:9bcdf88f62b0	849	* @{
<>	128:9bcdf88f62b0	850	*/
<>	128:9bcdf88f62b0	851	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
<>	128:9bcdf88f62b0	852	/**
<>	128:9bcdf88f62b0	853	* @}
<>	128:9bcdf88f62b0	854	*/
<>	128:9bcdf88f62b0	855
<>	128:9bcdf88f62b0	856	/* I/O operation functions *****************************************************/
<>	128:9bcdf88f62b0	857	/** @addtogroup HAL_SDMMC_LL_Group2
<>	128:9bcdf88f62b0	858	* @{
<>	128:9bcdf88f62b0	859	*/
<>	128:9bcdf88f62b0	860	/* Blocking mode: Polling */
<>	128:9bcdf88f62b0	861	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	862	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
<>	128:9bcdf88f62b0	863	/**
<>	128:9bcdf88f62b0	864	* @}
<>	128:9bcdf88f62b0	865	*/
<>	128:9bcdf88f62b0	866
<>	128:9bcdf88f62b0	867	/* Peripheral Control functions ************************************************/
<>	128:9bcdf88f62b0	868	/** @addtogroup HAL_SDMMC_LL_Group3
<>	128:9bcdf88f62b0	869	* @{
<>	128:9bcdf88f62b0	870	*/
<>	128:9bcdf88f62b0	871	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	872	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	873	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	874
<>	128:9bcdf88f62b0	875	/* Command path state machine (CPSM) management functions */
<>	128:9bcdf88f62b0	876	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef SDIO_CmdInitStruct);
<>	128:9bcdf88f62b0	877	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	878	uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
<>	128:9bcdf88f62b0	879
<>	128:9bcdf88f62b0	880	/* Data path state machine (DPSM) management functions */
<>	128:9bcdf88f62b0	881	HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef SDIO_DataInitStruct);
<>	128:9bcdf88f62b0	882	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	883	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
<>	128:9bcdf88f62b0	884
<>	128:9bcdf88f62b0	885	/* SDIO IO Cards mode management functions */
<>	128:9bcdf88f62b0	886	HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
<>	128:9bcdf88f62b0	887
<>	128:9bcdf88f62b0	888	/**
<>	128:9bcdf88f62b0	889	* @}
<>	128:9bcdf88f62b0	890	*/
<>	128:9bcdf88f62b0	891
<>	128:9bcdf88f62b0	892	/**
<>	128:9bcdf88f62b0	893	* @}
<>	128:9bcdf88f62b0	894	*/
<>	128:9bcdf88f62b0	895
<>	128:9bcdf88f62b0	896	/**
<>	128:9bcdf88f62b0	897	* @}
<>	128:9bcdf88f62b0	898	*/
<>	128:9bcdf88f62b0	899
<>	128:9bcdf88f62b0	900	/**
<>	128:9bcdf88f62b0	901	* @}
<>	128:9bcdf88f62b0	902	*/
<>	128:9bcdf88f62b0	903
<>	128:9bcdf88f62b0	904	#ifdef __cplusplus
<>	128:9bcdf88f62b0	905	}
<>	128:9bcdf88f62b0	906	#endif
<>	128:9bcdf88f62b0	907
<>	128:9bcdf88f62b0	908	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
<>	128:9bcdf88f62b0	909
<>	128:9bcdf88f62b0	910	#endif /* __STM32L1xx_LL_SD_H */
<>	128:9bcdf88f62b0	911
<>	128:9bcdf88f62b0	912	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/