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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_rcc.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of RCC LL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_RCC_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_RCC_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_LL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	#if defined(RCC)
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @defgroup RCC_LL RCC
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Private types -------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/* Private variables ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
<>	128:9bcdf88f62b0	62	* @{
<>	128:9bcdf88f62b0	63	*/
<>	128:9bcdf88f62b0	64
<>	128:9bcdf88f62b0	65	/**
<>	128:9bcdf88f62b0	66	* @}
<>	128:9bcdf88f62b0	67	*/
<>	128:9bcdf88f62b0	68
<>	128:9bcdf88f62b0	69	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	70	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
<>	128:9bcdf88f62b0	71	* @{
<>	128:9bcdf88f62b0	72	*/
<>	128:9bcdf88f62b0	73	/* Defines used for the bit position in the register and perform offsets*/
<>	128:9bcdf88f62b0	74	#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /!< field position in register RCC_CFGR /
<>	128:9bcdf88f62b0	75	#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /!< field position in register RCC_CFGR /
<>	128:9bcdf88f62b0	76	#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /!< field position in register RCC_CFGR /
<>	128:9bcdf88f62b0	77	#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL) /!< field position in register RCC_ICSCR /
<>	128:9bcdf88f62b0	78	#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM) /!< field position in register RCC_ICSCR /
<>	128:9bcdf88f62b0	79	#define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL) /!< field position in register RCC_ICSCR /
<>	128:9bcdf88f62b0	80	#define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) /!< field position in register RCC_ICSCR /
<>	128:9bcdf88f62b0	81	#define RCC_POSITION_MSIRANGE (uint32_t)POSITION_VAL(RCC_ICSCR_MSIRANGE) /!< field position in register RCC_ICSCR /
<>	128:9bcdf88f62b0	82	#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /!< field position in register RCC_CFGR /
<>	128:9bcdf88f62b0	83	#define RCC_POSITION_PLLDIV (uint32_t)POSITION_VAL(RCC_CFGR_PLLDIV) /!< field position in register RCC_CFGR /
<>	128:9bcdf88f62b0	84
<>	128:9bcdf88f62b0	85	/**
<>	128:9bcdf88f62b0	86	* @}
<>	128:9bcdf88f62b0	87	*/
<>	128:9bcdf88f62b0	88
<>	128:9bcdf88f62b0	89	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	90	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	91	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	92	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
<>	128:9bcdf88f62b0	93	* @{
<>	128:9bcdf88f62b0	94	*/
<>	128:9bcdf88f62b0	95
<>	128:9bcdf88f62b0	96	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<>	128:9bcdf88f62b0	97	* @{
<>	128:9bcdf88f62b0	98	*/
<>	128:9bcdf88f62b0	99
<>	128:9bcdf88f62b0	100	/**
<>	128:9bcdf88f62b0	101	* @brief RCC Clocks Frequency Structure
<>	128:9bcdf88f62b0	102	*/
<>	128:9bcdf88f62b0	103	typedef struct
<>	128:9bcdf88f62b0	104	{
<>	128:9bcdf88f62b0	105	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
<>	128:9bcdf88f62b0	106	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
<>	128:9bcdf88f62b0	107	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
<>	128:9bcdf88f62b0	108	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
<>	128:9bcdf88f62b0	109	} LL_RCC_ClocksTypeDef;
<>	128:9bcdf88f62b0	110
<>	128:9bcdf88f62b0	111	/**
<>	128:9bcdf88f62b0	112	* @}
<>	128:9bcdf88f62b0	113	*/
<>	128:9bcdf88f62b0	114
<>	128:9bcdf88f62b0	115	/**
<>	128:9bcdf88f62b0	116	* @}
<>	128:9bcdf88f62b0	117	*/
<>	128:9bcdf88f62b0	118	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	119
<>	128:9bcdf88f62b0	120	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	121	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<>	128:9bcdf88f62b0	122	* @{
<>	128:9bcdf88f62b0	123	*/
<>	128:9bcdf88f62b0	124
<>	128:9bcdf88f62b0	125	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<>	128:9bcdf88f62b0	126	* @brief Defines used to adapt values of different oscillators
<>	128:9bcdf88f62b0	127	* @note These values could be modified in the user environment according to
<>	128:9bcdf88f62b0	128	* HW set-up.
<>	128:9bcdf88f62b0	129	* @{
<>	128:9bcdf88f62b0	130	*/
<>	128:9bcdf88f62b0	131	#if !defined (HSE_VALUE)
<>	128:9bcdf88f62b0	132	#define HSE_VALUE ((uint32_t)8000000U) /!< Value of the HSE oscillator in Hz /
<>	128:9bcdf88f62b0	133	#endif /* HSE_VALUE */
<>	128:9bcdf88f62b0	134
<>	128:9bcdf88f62b0	135	#if !defined (HSI_VALUE)
<>	128:9bcdf88f62b0	136	#define HSI_VALUE ((uint32_t)16000000U) /!< Value of the HSI oscillator in Hz /
<>	128:9bcdf88f62b0	137	#endif /* HSI_VALUE */
<>	128:9bcdf88f62b0	138
<>	128:9bcdf88f62b0	139	#if !defined (LSE_VALUE)
<>	128:9bcdf88f62b0	140	#define LSE_VALUE ((uint32_t)32768U) /!< Value of the LSE oscillator in Hz /
<>	128:9bcdf88f62b0	141	#endif /* LSE_VALUE */
<>	128:9bcdf88f62b0	142
<>	128:9bcdf88f62b0	143	#if !defined (LSI_VALUE)
<>	128:9bcdf88f62b0	144	#define LSI_VALUE ((uint32_t)32000U) /!< Value of the LSI oscillator in Hz /
<>	128:9bcdf88f62b0	145	#endif /* LSI_VALUE */
<>	128:9bcdf88f62b0	146	/**
<>	128:9bcdf88f62b0	147	* @}
<>	128:9bcdf88f62b0	148	*/
<>	128:9bcdf88f62b0	149
<>	128:9bcdf88f62b0	150	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	128:9bcdf88f62b0	151	* @brief Flags defines which can be used with LL_RCC_WriteReg function
<>	128:9bcdf88f62b0	152	* @{
<>	128:9bcdf88f62b0	153	*/
<>	128:9bcdf88f62b0	154	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
<>	128:9bcdf88f62b0	155	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
<>	128:9bcdf88f62b0	156	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
<>	128:9bcdf88f62b0	157	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
<>	128:9bcdf88f62b0	158	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
<>	128:9bcdf88f62b0	159	#define LL_RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC /!< MSI Ready Interrupt Clear /
<>	128:9bcdf88f62b0	160	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	161	#define LL_RCC_CIR_LSECSSC RCC_CIR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
<>	128:9bcdf88f62b0	162	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	163	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
<>	128:9bcdf88f62b0	164	/**
<>	128:9bcdf88f62b0	165	* @}
<>	128:9bcdf88f62b0	166	*/
<>	128:9bcdf88f62b0	167
<>	128:9bcdf88f62b0	168	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<>	128:9bcdf88f62b0	169	* @brief Flags defines which can be used with LL_RCC_ReadReg function
<>	128:9bcdf88f62b0	170	* @{
<>	128:9bcdf88f62b0	171	*/
<>	128:9bcdf88f62b0	172	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	128:9bcdf88f62b0	173	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
<>	128:9bcdf88f62b0	174	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
<>	128:9bcdf88f62b0	175	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
<>	128:9bcdf88f62b0	176	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	128:9bcdf88f62b0	177	#define LL_RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF /!< MSI Ready Interrupt flag /
<>	128:9bcdf88f62b0	178	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	179	#define LL_RCC_CIR_LSECSSF RCC_CIR_LSECSSF /!< LSE Clock Security System Interrupt flag /
<>	128:9bcdf88f62b0	180	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	181	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
<>	128:9bcdf88f62b0	182	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
<>	128:9bcdf88f62b0	183	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
<>	128:9bcdf88f62b0	184	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
<>	128:9bcdf88f62b0	185	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
<>	128:9bcdf88f62b0	186	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
<>	128:9bcdf88f62b0	187	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
<>	128:9bcdf88f62b0	188	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
<>	128:9bcdf88f62b0	189	/**
<>	128:9bcdf88f62b0	190	* @}
<>	128:9bcdf88f62b0	191	*/
<>	128:9bcdf88f62b0	192
<>	128:9bcdf88f62b0	193	/** @defgroup RCC_LL_EC_IT IT Defines
<>	128:9bcdf88f62b0	194	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<>	128:9bcdf88f62b0	195	* @{
<>	128:9bcdf88f62b0	196	*/
<>	128:9bcdf88f62b0	197	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
<>	128:9bcdf88f62b0	198	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
<>	128:9bcdf88f62b0	199	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
<>	128:9bcdf88f62b0	200	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
<>	128:9bcdf88f62b0	201	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
<>	128:9bcdf88f62b0	202	#define LL_RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE /!< MSI Ready Interrupt Enable /
<>	128:9bcdf88f62b0	203	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	204	#define LL_RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE /!< LSE CSS Interrupt Enable /
<>	128:9bcdf88f62b0	205	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	206	/**
<>	128:9bcdf88f62b0	207	* @}
<>	128:9bcdf88f62b0	208	*/
<>	128:9bcdf88f62b0	209
<>	128:9bcdf88f62b0	210	/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
<>	128:9bcdf88f62b0	211	* @{
<>	128:9bcdf88f62b0	212	*/
<>	128:9bcdf88f62b0	213	#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/!< HSE is divided by 2 for RTC clock /
<>	128:9bcdf88f62b0	214	#define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
<>	128:9bcdf88f62b0	215	#define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
<>	128:9bcdf88f62b0	216	#define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
<>	128:9bcdf88f62b0	217	/**
<>	128:9bcdf88f62b0	218	* @}
<>	128:9bcdf88f62b0	219	*/
<>	128:9bcdf88f62b0	220
<>	128:9bcdf88f62b0	221	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
<>	128:9bcdf88f62b0	222	* @{
<>	128:9bcdf88f62b0	223	*/
<>	128:9bcdf88f62b0	224	#define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
<>	128:9bcdf88f62b0	225	#define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz/
<>	128:9bcdf88f62b0	226	#define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
<>	128:9bcdf88f62b0	227	#define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
<>	128:9bcdf88f62b0	228	#define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
<>	128:9bcdf88f62b0	229	#define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
<>	128:9bcdf88f62b0	230	#define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
<>	128:9bcdf88f62b0	231	/**
<>	128:9bcdf88f62b0	232	* @}
<>	128:9bcdf88f62b0	233	*/
<>	128:9bcdf88f62b0	234
<>	128:9bcdf88f62b0	235	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<>	128:9bcdf88f62b0	236	* @{
<>	128:9bcdf88f62b0	237	*/
<>	128:9bcdf88f62b0	238	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
<>	128:9bcdf88f62b0	239	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	128:9bcdf88f62b0	240	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	128:9bcdf88f62b0	241	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	128:9bcdf88f62b0	242	/**
<>	128:9bcdf88f62b0	243	* @}
<>	128:9bcdf88f62b0	244	*/
<>	128:9bcdf88f62b0	245
<>	128:9bcdf88f62b0	246	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<>	128:9bcdf88f62b0	247	* @{
<>	128:9bcdf88f62b0	248	*/
<>	128:9bcdf88f62b0	249	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
<>	128:9bcdf88f62b0	250	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	128:9bcdf88f62b0	251	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	128:9bcdf88f62b0	252	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	128:9bcdf88f62b0	253	/**
<>	128:9bcdf88f62b0	254	* @}
<>	128:9bcdf88f62b0	255	*/
<>	128:9bcdf88f62b0	256
<>	128:9bcdf88f62b0	257	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<>	128:9bcdf88f62b0	258	* @{
<>	128:9bcdf88f62b0	259	*/
<>	128:9bcdf88f62b0	260	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	128:9bcdf88f62b0	261	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	128:9bcdf88f62b0	262	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	128:9bcdf88f62b0	263	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	128:9bcdf88f62b0	264	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	128:9bcdf88f62b0	265	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	128:9bcdf88f62b0	266	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	128:9bcdf88f62b0	267	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	128:9bcdf88f62b0	268	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	128:9bcdf88f62b0	269	/**
<>	128:9bcdf88f62b0	270	* @}
<>	128:9bcdf88f62b0	271	*/
<>	128:9bcdf88f62b0	272
<>	128:9bcdf88f62b0	273	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<>	128:9bcdf88f62b0	274	* @{
<>	128:9bcdf88f62b0	275	*/
<>	128:9bcdf88f62b0	276	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	128:9bcdf88f62b0	277	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	128:9bcdf88f62b0	278	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	128:9bcdf88f62b0	279	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	128:9bcdf88f62b0	280	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	128:9bcdf88f62b0	281	/**
<>	128:9bcdf88f62b0	282	* @}
<>	128:9bcdf88f62b0	283	*/
<>	128:9bcdf88f62b0	284
<>	128:9bcdf88f62b0	285	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
<>	128:9bcdf88f62b0	286	* @{
<>	128:9bcdf88f62b0	287	*/
<>	128:9bcdf88f62b0	288	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
<>	128:9bcdf88f62b0	289	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
<>	128:9bcdf88f62b0	290	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
<>	128:9bcdf88f62b0	291	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
<>	128:9bcdf88f62b0	292	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
<>	128:9bcdf88f62b0	293	/**
<>	128:9bcdf88f62b0	294	* @}
<>	128:9bcdf88f62b0	295	*/
<>	128:9bcdf88f62b0	296
<>	128:9bcdf88f62b0	297	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<>	128:9bcdf88f62b0	298	* @{
<>	128:9bcdf88f62b0	299	*/
<>	128:9bcdf88f62b0	300	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
<>	128:9bcdf88f62b0	301	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
<>	128:9bcdf88f62b0	302	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
<>	128:9bcdf88f62b0	303	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /!< MSI selection as MCO source /
<>	128:9bcdf88f62b0	304	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
<>	128:9bcdf88f62b0	305	#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /!< LSI selection as MCO source /
<>	128:9bcdf88f62b0	306	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /!< LSE selection as MCO source /
<>	128:9bcdf88f62b0	307	#define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /!< PLLCLK selection as MCO source /
<>	128:9bcdf88f62b0	308	/**
<>	128:9bcdf88f62b0	309	* @}
<>	128:9bcdf88f62b0	310	*/
<>	128:9bcdf88f62b0	311
<>	128:9bcdf88f62b0	312	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
<>	128:9bcdf88f62b0	313	* @{
<>	128:9bcdf88f62b0	314	*/
<>	128:9bcdf88f62b0	315	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO Clock divided by 1 /
<>	128:9bcdf88f62b0	316	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO Clock divided by 2 /
<>	128:9bcdf88f62b0	317	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO Clock divided by 4 /
<>	128:9bcdf88f62b0	318	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO Clock divided by 8 /
<>	128:9bcdf88f62b0	319	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO Clock divided by 16 /
<>	128:9bcdf88f62b0	320	/**
<>	128:9bcdf88f62b0	321	* @}
<>	128:9bcdf88f62b0	322	*/
<>	128:9bcdf88f62b0	323	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	324	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<>	128:9bcdf88f62b0	325	* @{
<>	128:9bcdf88f62b0	326	*/
<>	128:9bcdf88f62b0	327	#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /!< No clock enabled for the peripheral /
<>	128:9bcdf88f62b0	328	#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
<>	128:9bcdf88f62b0	329	/**
<>	128:9bcdf88f62b0	330	* @}
<>	128:9bcdf88f62b0	331	*/
<>	128:9bcdf88f62b0	332	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	333
<>	128:9bcdf88f62b0	334
<>	128:9bcdf88f62b0	335
<>	128:9bcdf88f62b0	336	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<>	128:9bcdf88f62b0	337	* @{
<>	128:9bcdf88f62b0	338	*/
<>	128:9bcdf88f62b0	339	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /!< No clock used as RTC clock /
<>	128:9bcdf88f62b0	340	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
<>	128:9bcdf88f62b0	341	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
<>	128:9bcdf88f62b0	342	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler
<>	128:9bcdf88f62b0	343	(selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
<>	128:9bcdf88f62b0	344	/**
<>	128:9bcdf88f62b0	345	* @}
<>	128:9bcdf88f62b0	346	*/
<>	128:9bcdf88f62b0	347
<>	128:9bcdf88f62b0	348	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
<>	128:9bcdf88f62b0	349	* @{
<>	128:9bcdf88f62b0	350	*/
<>	128:9bcdf88f62b0	351	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /!< PLL input clock 3 */
<>	128:9bcdf88f62b0	352	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /!< PLL input clock 4 */
<>	128:9bcdf88f62b0	353	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /!< PLL input clock 6 */
<>	128:9bcdf88f62b0	354	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /!< PLL input clock 8 */
<>	128:9bcdf88f62b0	355	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /!< PLL input clock 12 */
<>	128:9bcdf88f62b0	356	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /!< PLL input clock 16 */
<>	128:9bcdf88f62b0	357	#define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /!< PLL input clock 24 */
<>	128:9bcdf88f62b0	358	#define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /!< PLL input clock 32 */
<>	128:9bcdf88f62b0	359	#define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /!< PLL input clock 48 */
<>	128:9bcdf88f62b0	360	/**
<>	128:9bcdf88f62b0	361	* @}
<>	128:9bcdf88f62b0	362	*/
<>	128:9bcdf88f62b0	363
<>	128:9bcdf88f62b0	364	/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
<>	128:9bcdf88f62b0	365	* @{
<>	128:9bcdf88f62b0	366	*/
<>	128:9bcdf88f62b0	367	#define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /!< PLL clock output = PLLVCO / 2 /
<>	128:9bcdf88f62b0	368	#define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /!< PLL clock output = PLLVCO / 3 /
<>	128:9bcdf88f62b0	369	#define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /!< PLL clock output = PLLVCO / 4 /
<>	128:9bcdf88f62b0	370	/**
<>	128:9bcdf88f62b0	371	* @}
<>	128:9bcdf88f62b0	372	*/
<>	128:9bcdf88f62b0	373
<>	128:9bcdf88f62b0	374	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
<>	128:9bcdf88f62b0	375	* @{
<>	128:9bcdf88f62b0	376	*/
<>	128:9bcdf88f62b0	377	#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
<>	128:9bcdf88f62b0	378	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
<>	128:9bcdf88f62b0	379	/**
<>	128:9bcdf88f62b0	380	* @}
<>	128:9bcdf88f62b0	381	*/
<>	128:9bcdf88f62b0	382
<>	128:9bcdf88f62b0	383	/**
<>	128:9bcdf88f62b0	384	* @}
<>	128:9bcdf88f62b0	385	*/
<>	128:9bcdf88f62b0	386
<>	128:9bcdf88f62b0	387	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	388	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<>	128:9bcdf88f62b0	389	* @{
<>	128:9bcdf88f62b0	390	*/
<>	128:9bcdf88f62b0	391
<>	128:9bcdf88f62b0	392	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<>	128:9bcdf88f62b0	393	* @{
<>	128:9bcdf88f62b0	394	*/
<>	128:9bcdf88f62b0	395
<>	128:9bcdf88f62b0	396	/**
<>	128:9bcdf88f62b0	397	* @brief Write a value in RCC register
<>	128:9bcdf88f62b0	398	* @param __REG__ Register to be written
<>	128:9bcdf88f62b0	399	* @param __VALUE__ Value to be written in the register
<>	128:9bcdf88f62b0	400	* @retval None
<>	128:9bcdf88f62b0	401	*/
<>	128:9bcdf88f62b0	402	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<>	128:9bcdf88f62b0	403
<>	128:9bcdf88f62b0	404	/**
<>	128:9bcdf88f62b0	405	* @brief Read a value in RCC register
<>	128:9bcdf88f62b0	406	* @param __REG__ Register to be read
<>	128:9bcdf88f62b0	407	* @retval Register value
<>	128:9bcdf88f62b0	408	*/
<>	128:9bcdf88f62b0	409	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<>	128:9bcdf88f62b0	410	/**
<>	128:9bcdf88f62b0	411	* @}
<>	128:9bcdf88f62b0	412	*/
<>	128:9bcdf88f62b0	413
<>	128:9bcdf88f62b0	414	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<>	128:9bcdf88f62b0	415	* @{
<>	128:9bcdf88f62b0	416	*/
<>	128:9bcdf88f62b0	417
<>	128:9bcdf88f62b0	418	/**
<>	128:9bcdf88f62b0	419	* @brief Helper macro to calculate the PLLCLK frequency
<>	128:9bcdf88f62b0	420	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
<>	128:9bcdf88f62b0	421	* @ref LL_RCC_PLL_GetMultiplicator (),
<>	128:9bcdf88f62b0	422	* @ref LL_RCC_PLL_GetDivider ());
<>	128:9bcdf88f62b0	423	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	128:9bcdf88f62b0	424	* @param __PLLMUL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	425	* @arg @ref LL_RCC_PLL_MUL_3
<>	128:9bcdf88f62b0	426	* @arg @ref LL_RCC_PLL_MUL_4
<>	128:9bcdf88f62b0	427	* @arg @ref LL_RCC_PLL_MUL_6
<>	128:9bcdf88f62b0	428	* @arg @ref LL_RCC_PLL_MUL_8
<>	128:9bcdf88f62b0	429	* @arg @ref LL_RCC_PLL_MUL_12
<>	128:9bcdf88f62b0	430	* @arg @ref LL_RCC_PLL_MUL_16
<>	128:9bcdf88f62b0	431	* @arg @ref LL_RCC_PLL_MUL_24
<>	128:9bcdf88f62b0	432	* @arg @ref LL_RCC_PLL_MUL_32
<>	128:9bcdf88f62b0	433	* @arg @ref LL_RCC_PLL_MUL_48
<>	128:9bcdf88f62b0	434	* @param __PLLDIV__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	435	* @arg @ref LL_RCC_PLL_DIV_2
<>	128:9bcdf88f62b0	436	* @arg @ref LL_RCC_PLL_DIV_3
<>	128:9bcdf88f62b0	437	* @arg @ref LL_RCC_PLL_DIV_4
<>	128:9bcdf88f62b0	438	* @retval PLL clock frequency (in Hz)
<>	128:9bcdf88f62b0	439	*/
<>	128:9bcdf88f62b0	440	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U))
<>	128:9bcdf88f62b0	441
<>	128:9bcdf88f62b0	442	/**
<>	128:9bcdf88f62b0	443	* @brief Helper macro to calculate the HCLK frequency
<>	128:9bcdf88f62b0	444	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
<>	128:9bcdf88f62b0	445	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
<>	128:9bcdf88f62b0	446	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
<>	128:9bcdf88f62b0	447	* @param __AHBPRESCALER__: This parameter can be one of the following values:
<>	128:9bcdf88f62b0	448	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	128:9bcdf88f62b0	449	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	128:9bcdf88f62b0	450	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	128:9bcdf88f62b0	451	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	128:9bcdf88f62b0	452	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	128:9bcdf88f62b0	453	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	128:9bcdf88f62b0	454	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	128:9bcdf88f62b0	455	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	128:9bcdf88f62b0	456	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	128:9bcdf88f62b0	457	* @retval HCLK clock frequency (in Hz)
<>	128:9bcdf88f62b0	458	*/
<>	128:9bcdf88f62b0	459	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
<>	128:9bcdf88f62b0	460
<>	128:9bcdf88f62b0	461	/**
<>	128:9bcdf88f62b0	462	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<>	128:9bcdf88f62b0	463	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
<>	128:9bcdf88f62b0	464	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
<>	128:9bcdf88f62b0	465	* @param __HCLKFREQ__ HCLK frequency
<>	128:9bcdf88f62b0	466	* @param __APB1PRESCALER__: This parameter can be one of the following values:
<>	128:9bcdf88f62b0	467	* @arg @ref LL_RCC_APB1_DIV_1
<>	128:9bcdf88f62b0	468	* @arg @ref LL_RCC_APB1_DIV_2
<>	128:9bcdf88f62b0	469	* @arg @ref LL_RCC_APB1_DIV_4
<>	128:9bcdf88f62b0	470	* @arg @ref LL_RCC_APB1_DIV_8
<>	128:9bcdf88f62b0	471	* @arg @ref LL_RCC_APB1_DIV_16
<>	128:9bcdf88f62b0	472	* @retval PCLK1 clock frequency (in Hz)
<>	128:9bcdf88f62b0	473	*/
<>	128:9bcdf88f62b0	474	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
<>	128:9bcdf88f62b0	475
<>	128:9bcdf88f62b0	476	/**
<>	128:9bcdf88f62b0	477	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
<>	128:9bcdf88f62b0	478	* @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
<>	128:9bcdf88f62b0	479	* ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
<>	128:9bcdf88f62b0	480	* @param __HCLKFREQ__ HCLK frequency
<>	128:9bcdf88f62b0	481	* @param __APB2PRESCALER__: This parameter can be one of the following values:
<>	128:9bcdf88f62b0	482	* @arg @ref LL_RCC_APB2_DIV_1
<>	128:9bcdf88f62b0	483	* @arg @ref LL_RCC_APB2_DIV_2
<>	128:9bcdf88f62b0	484	* @arg @ref LL_RCC_APB2_DIV_4
<>	128:9bcdf88f62b0	485	* @arg @ref LL_RCC_APB2_DIV_8
<>	128:9bcdf88f62b0	486	* @arg @ref LL_RCC_APB2_DIV_16
<>	128:9bcdf88f62b0	487	* @retval PCLK2 clock frequency (in Hz)
<>	128:9bcdf88f62b0	488	*/
<>	128:9bcdf88f62b0	489	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
<>	128:9bcdf88f62b0	490
<>	128:9bcdf88f62b0	491	/**
<>	128:9bcdf88f62b0	492	* @brief Helper macro to calculate the MSI frequency (in Hz)
<>	128:9bcdf88f62b0	493	* @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
<>	128:9bcdf88f62b0	494	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
<>	128:9bcdf88f62b0	495	* @param __MSIRANGE__: This parameter can be one of the following values:
<>	128:9bcdf88f62b0	496	* @arg @ref LL_RCC_MSIRANGE_0
<>	128:9bcdf88f62b0	497	* @arg @ref LL_RCC_MSIRANGE_1
<>	128:9bcdf88f62b0	498	* @arg @ref LL_RCC_MSIRANGE_2
<>	128:9bcdf88f62b0	499	* @arg @ref LL_RCC_MSIRANGE_3
<>	128:9bcdf88f62b0	500	* @arg @ref LL_RCC_MSIRANGE_4
<>	128:9bcdf88f62b0	501	* @arg @ref LL_RCC_MSIRANGE_5
<>	128:9bcdf88f62b0	502	* @arg @ref LL_RCC_MSIRANGE_6
<>	128:9bcdf88f62b0	503	* @retval MSI clock frequency (in Hz)
<>	128:9bcdf88f62b0	504	*/
<>	128:9bcdf88f62b0	505	#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U))))
<>	128:9bcdf88f62b0	506
<>	128:9bcdf88f62b0	507	/**
<>	128:9bcdf88f62b0	508	* @}
<>	128:9bcdf88f62b0	509	*/
<>	128:9bcdf88f62b0	510
<>	128:9bcdf88f62b0	511	/**
<>	128:9bcdf88f62b0	512	* @}
<>	128:9bcdf88f62b0	513	*/
<>	128:9bcdf88f62b0	514
<>	128:9bcdf88f62b0	515	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	516	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<>	128:9bcdf88f62b0	517	* @{
<>	128:9bcdf88f62b0	518	*/
<>	128:9bcdf88f62b0	519
<>	128:9bcdf88f62b0	520	/** @defgroup RCC_LL_EF_HSE HSE
<>	128:9bcdf88f62b0	521	* @{
<>	128:9bcdf88f62b0	522	*/
<>	128:9bcdf88f62b0	523
<>	128:9bcdf88f62b0	524	/**
<>	128:9bcdf88f62b0	525	* @brief Enable the Clock Security System.
<>	128:9bcdf88f62b0	526	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<>	128:9bcdf88f62b0	527	* @retval None
<>	128:9bcdf88f62b0	528	*/
<>	128:9bcdf88f62b0	529	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<>	128:9bcdf88f62b0	530	{
<>	128:9bcdf88f62b0	531	SET_BIT(RCC->CR, RCC_CR_CSSON);
<>	128:9bcdf88f62b0	532	}
<>	128:9bcdf88f62b0	533
<>	128:9bcdf88f62b0	534	/**
<>	128:9bcdf88f62b0	535	* @brief Disable the Clock Security System.
<>	128:9bcdf88f62b0	536	* @note Cannot be disabled in HSE is ready (only by hardware)
<>	128:9bcdf88f62b0	537	* @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
<>	128:9bcdf88f62b0	538	* @retval None
<>	128:9bcdf88f62b0	539	*/
<>	128:9bcdf88f62b0	540	__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
<>	128:9bcdf88f62b0	541	{
<>	128:9bcdf88f62b0	542	CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
<>	128:9bcdf88f62b0	543	}
<>	128:9bcdf88f62b0	544
<>	128:9bcdf88f62b0	545	/**
<>	128:9bcdf88f62b0	546	* @brief Enable HSE external oscillator (HSE Bypass)
<>	128:9bcdf88f62b0	547	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<>	128:9bcdf88f62b0	548	* @retval None
<>	128:9bcdf88f62b0	549	*/
<>	128:9bcdf88f62b0	550	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<>	128:9bcdf88f62b0	551	{
<>	128:9bcdf88f62b0	552	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	128:9bcdf88f62b0	553	}
<>	128:9bcdf88f62b0	554
<>	128:9bcdf88f62b0	555	/**
<>	128:9bcdf88f62b0	556	* @brief Disable HSE external oscillator (HSE Bypass)
<>	128:9bcdf88f62b0	557	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<>	128:9bcdf88f62b0	558	* @retval None
<>	128:9bcdf88f62b0	559	*/
<>	128:9bcdf88f62b0	560	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<>	128:9bcdf88f62b0	561	{
<>	128:9bcdf88f62b0	562	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	128:9bcdf88f62b0	563	}
<>	128:9bcdf88f62b0	564
<>	128:9bcdf88f62b0	565	/**
<>	128:9bcdf88f62b0	566	* @brief Enable HSE crystal oscillator (HSE ON)
<>	128:9bcdf88f62b0	567	* @rmtoll CR HSEON LL_RCC_HSE_Enable
<>	128:9bcdf88f62b0	568	* @retval None
<>	128:9bcdf88f62b0	569	*/
<>	128:9bcdf88f62b0	570	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
<>	128:9bcdf88f62b0	571	{
<>	128:9bcdf88f62b0	572	SET_BIT(RCC->CR, RCC_CR_HSEON);
<>	128:9bcdf88f62b0	573	}
<>	128:9bcdf88f62b0	574
<>	128:9bcdf88f62b0	575	/**
<>	128:9bcdf88f62b0	576	* @brief Disable HSE crystal oscillator (HSE ON)
<>	128:9bcdf88f62b0	577	* @rmtoll CR HSEON LL_RCC_HSE_Disable
<>	128:9bcdf88f62b0	578	* @retval None
<>	128:9bcdf88f62b0	579	*/
<>	128:9bcdf88f62b0	580	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
<>	128:9bcdf88f62b0	581	{
<>	128:9bcdf88f62b0	582	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<>	128:9bcdf88f62b0	583	}
<>	128:9bcdf88f62b0	584
<>	128:9bcdf88f62b0	585	/**
<>	128:9bcdf88f62b0	586	* @brief Check if HSE oscillator Ready
<>	128:9bcdf88f62b0	587	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<>	128:9bcdf88f62b0	588	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	589	*/
<>	128:9bcdf88f62b0	590	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<>	128:9bcdf88f62b0	591	{
<>	128:9bcdf88f62b0	592	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<>	128:9bcdf88f62b0	593	}
<>	128:9bcdf88f62b0	594
<>	128:9bcdf88f62b0	595	/**
<>	128:9bcdf88f62b0	596	* @brief Configure the RTC prescaler (divider)
<>	128:9bcdf88f62b0	597	* @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler
<>	128:9bcdf88f62b0	598	* @param Div This parameter can be one of the following values:
<>	128:9bcdf88f62b0	599	* @arg @ref LL_RCC_RTC_HSE_DIV_2
<>	128:9bcdf88f62b0	600	* @arg @ref LL_RCC_RTC_HSE_DIV_4
<>	128:9bcdf88f62b0	601	* @arg @ref LL_RCC_RTC_HSE_DIV_8
<>	128:9bcdf88f62b0	602	* @arg @ref LL_RCC_RTC_HSE_DIV_16
<>	128:9bcdf88f62b0	603	* @retval None
<>	128:9bcdf88f62b0	604	*/
<>	128:9bcdf88f62b0	605	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
<>	128:9bcdf88f62b0	606	{
<>	128:9bcdf88f62b0	607	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
<>	128:9bcdf88f62b0	608	}
<>	128:9bcdf88f62b0	609
<>	128:9bcdf88f62b0	610	/**
<>	128:9bcdf88f62b0	611	* @brief Get the RTC divider (prescaler)
<>	128:9bcdf88f62b0	612	* @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler
<>	128:9bcdf88f62b0	613	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	614	* @arg @ref LL_RCC_RTC_HSE_DIV_2
<>	128:9bcdf88f62b0	615	* @arg @ref LL_RCC_RTC_HSE_DIV_4
<>	128:9bcdf88f62b0	616	* @arg @ref LL_RCC_RTC_HSE_DIV_8
<>	128:9bcdf88f62b0	617	* @arg @ref LL_RCC_RTC_HSE_DIV_16
<>	128:9bcdf88f62b0	618	*/
<>	128:9bcdf88f62b0	619	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
<>	128:9bcdf88f62b0	620	{
<>	128:9bcdf88f62b0	621	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
<>	128:9bcdf88f62b0	622	}
<>	128:9bcdf88f62b0	623
<>	128:9bcdf88f62b0	624	/**
<>	128:9bcdf88f62b0	625	* @}
<>	128:9bcdf88f62b0	626	*/
<>	128:9bcdf88f62b0	627
<>	128:9bcdf88f62b0	628	/** @defgroup RCC_LL_EF_HSI HSI
<>	128:9bcdf88f62b0	629	* @{
<>	128:9bcdf88f62b0	630	*/
<>	128:9bcdf88f62b0	631
<>	128:9bcdf88f62b0	632	/**
<>	128:9bcdf88f62b0	633	* @brief Enable HSI oscillator
<>	128:9bcdf88f62b0	634	* @rmtoll CR HSION LL_RCC_HSI_Enable
<>	128:9bcdf88f62b0	635	* @retval None
<>	128:9bcdf88f62b0	636	*/
<>	128:9bcdf88f62b0	637	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
<>	128:9bcdf88f62b0	638	{
<>	128:9bcdf88f62b0	639	SET_BIT(RCC->CR, RCC_CR_HSION);
<>	128:9bcdf88f62b0	640	}
<>	128:9bcdf88f62b0	641
<>	128:9bcdf88f62b0	642	/**
<>	128:9bcdf88f62b0	643	* @brief Disable HSI oscillator
<>	128:9bcdf88f62b0	644	* @rmtoll CR HSION LL_RCC_HSI_Disable
<>	128:9bcdf88f62b0	645	* @retval None
<>	128:9bcdf88f62b0	646	*/
<>	128:9bcdf88f62b0	647	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
<>	128:9bcdf88f62b0	648	{
<>	128:9bcdf88f62b0	649	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<>	128:9bcdf88f62b0	650	}
<>	128:9bcdf88f62b0	651
<>	128:9bcdf88f62b0	652	/**
<>	128:9bcdf88f62b0	653	* @brief Check if HSI clock is ready
<>	128:9bcdf88f62b0	654	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<>	128:9bcdf88f62b0	655	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	656	*/
<>	128:9bcdf88f62b0	657	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<>	128:9bcdf88f62b0	658	{
<>	128:9bcdf88f62b0	659	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<>	128:9bcdf88f62b0	660	}
<>	128:9bcdf88f62b0	661
<>	128:9bcdf88f62b0	662	/**
<>	128:9bcdf88f62b0	663	* @brief Get HSI Calibration value
<>	128:9bcdf88f62b0	664	* @note When HSITRIM is written, HSICAL is updated with the sum of
<>	128:9bcdf88f62b0	665	* HSITRIM and the factory trim value
<>	128:9bcdf88f62b0	666	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
<>	128:9bcdf88f62b0	667	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	128:9bcdf88f62b0	668	*/
<>	128:9bcdf88f62b0	669	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<>	128:9bcdf88f62b0	670	{
<>	128:9bcdf88f62b0	671	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
<>	128:9bcdf88f62b0	672	}
<>	128:9bcdf88f62b0	673
<>	128:9bcdf88f62b0	674	/**
<>	128:9bcdf88f62b0	675	* @brief Set HSI Calibration trimming
<>	128:9bcdf88f62b0	676	* @note user-programmable trimming value that is added to the HSICAL
<>	128:9bcdf88f62b0	677	* @note Default value is 16, which, when added to the HSICAL value,
<>	128:9bcdf88f62b0	678	* should trim the HSI to 16 MHz +/- 1 %
<>	128:9bcdf88f62b0	679	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
<>	128:9bcdf88f62b0	680	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
<>	128:9bcdf88f62b0	681	* @retval None
<>	128:9bcdf88f62b0	682	*/
<>	128:9bcdf88f62b0	683	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<>	128:9bcdf88f62b0	684	{
<>	128:9bcdf88f62b0	685	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
<>	128:9bcdf88f62b0	686	}
<>	128:9bcdf88f62b0	687
<>	128:9bcdf88f62b0	688	/**
<>	128:9bcdf88f62b0	689	* @brief Get HSI Calibration trimming
<>	128:9bcdf88f62b0	690	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
<>	128:9bcdf88f62b0	691	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<>	128:9bcdf88f62b0	692	*/
<>	128:9bcdf88f62b0	693	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<>	128:9bcdf88f62b0	694	{
<>	128:9bcdf88f62b0	695	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
<>	128:9bcdf88f62b0	696	}
<>	128:9bcdf88f62b0	697
<>	128:9bcdf88f62b0	698	/**
<>	128:9bcdf88f62b0	699	* @}
<>	128:9bcdf88f62b0	700	*/
<>	128:9bcdf88f62b0	701
<>	128:9bcdf88f62b0	702	/** @defgroup RCC_LL_EF_LSE LSE
<>	128:9bcdf88f62b0	703	* @{
<>	128:9bcdf88f62b0	704	*/
<>	128:9bcdf88f62b0	705
<>	128:9bcdf88f62b0	706	/**
<>	128:9bcdf88f62b0	707	* @brief Enable Low Speed External (LSE) crystal.
<>	128:9bcdf88f62b0	708	* @rmtoll CSR LSEON LL_RCC_LSE_Enable
<>	128:9bcdf88f62b0	709	* @retval None
<>	128:9bcdf88f62b0	710	*/
<>	128:9bcdf88f62b0	711	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
<>	128:9bcdf88f62b0	712	{
<>	128:9bcdf88f62b0	713	SET_BIT(RCC->CSR, RCC_CSR_LSEON);
<>	128:9bcdf88f62b0	714	}
<>	128:9bcdf88f62b0	715
<>	128:9bcdf88f62b0	716	/**
<>	128:9bcdf88f62b0	717	* @brief Disable Low Speed External (LSE) crystal.
<>	128:9bcdf88f62b0	718	* @rmtoll CSR LSEON LL_RCC_LSE_Disable
<>	128:9bcdf88f62b0	719	* @retval None
<>	128:9bcdf88f62b0	720	*/
<>	128:9bcdf88f62b0	721	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
<>	128:9bcdf88f62b0	722	{
<>	128:9bcdf88f62b0	723	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
<>	128:9bcdf88f62b0	724	}
<>	128:9bcdf88f62b0	725
<>	128:9bcdf88f62b0	726	/**
<>	128:9bcdf88f62b0	727	* @brief Enable external clock source (LSE bypass).
<>	128:9bcdf88f62b0	728	* @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass
<>	128:9bcdf88f62b0	729	* @retval None
<>	128:9bcdf88f62b0	730	*/
<>	128:9bcdf88f62b0	731	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<>	128:9bcdf88f62b0	732	{
<>	128:9bcdf88f62b0	733	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
<>	128:9bcdf88f62b0	734	}
<>	128:9bcdf88f62b0	735
<>	128:9bcdf88f62b0	736	/**
<>	128:9bcdf88f62b0	737	* @brief Disable external clock source (LSE bypass).
<>	128:9bcdf88f62b0	738	* @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass
<>	128:9bcdf88f62b0	739	* @retval None
<>	128:9bcdf88f62b0	740	*/
<>	128:9bcdf88f62b0	741	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<>	128:9bcdf88f62b0	742	{
<>	128:9bcdf88f62b0	743	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
<>	128:9bcdf88f62b0	744	}
<>	128:9bcdf88f62b0	745
<>	128:9bcdf88f62b0	746	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	747	/**
<>	128:9bcdf88f62b0	748	* @brief Enable Clock security system on LSE.
<>	128:9bcdf88f62b0	749	* @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS
<>	128:9bcdf88f62b0	750	* @retval None
<>	128:9bcdf88f62b0	751	*/
<>	128:9bcdf88f62b0	752	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
<>	128:9bcdf88f62b0	753	{
<>	128:9bcdf88f62b0	754	SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
<>	128:9bcdf88f62b0	755	}
<>	128:9bcdf88f62b0	756
<>	128:9bcdf88f62b0	757	/**
<>	128:9bcdf88f62b0	758	* @brief Disable Clock security system on LSE.
<>	128:9bcdf88f62b0	759	* @note Clock security system can be disabled only after a LSE
<>	128:9bcdf88f62b0	760	* failure detection. In that case it MUST be disabled by software.
<>	128:9bcdf88f62b0	761	* @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS
<>	128:9bcdf88f62b0	762	* @retval None
<>	128:9bcdf88f62b0	763	*/
<>	128:9bcdf88f62b0	764	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
<>	128:9bcdf88f62b0	765	{
<>	128:9bcdf88f62b0	766	CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
<>	128:9bcdf88f62b0	767	}
<>	128:9bcdf88f62b0	768
<>	128:9bcdf88f62b0	769	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	770	/**
<>	128:9bcdf88f62b0	771	* @brief Check if LSE oscillator Ready
<>	128:9bcdf88f62b0	772	* @rmtoll CSR LSERDY LL_RCC_LSE_IsReady
<>	128:9bcdf88f62b0	773	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	774	*/
<>	128:9bcdf88f62b0	775	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<>	128:9bcdf88f62b0	776	{
<>	128:9bcdf88f62b0	777	return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY));
<>	128:9bcdf88f62b0	778	}
<>	128:9bcdf88f62b0	779
<>	128:9bcdf88f62b0	780	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	781	/**
<>	128:9bcdf88f62b0	782	* @brief Check if CSS on LSE failure Detection
<>	128:9bcdf88f62b0	783	* @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected
<>	128:9bcdf88f62b0	784	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	785	*/
<>	128:9bcdf88f62b0	786	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
<>	128:9bcdf88f62b0	787	{
<>	128:9bcdf88f62b0	788	return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD));
<>	128:9bcdf88f62b0	789	}
<>	128:9bcdf88f62b0	790
<>	128:9bcdf88f62b0	791	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	792	/**
<>	128:9bcdf88f62b0	793	* @}
<>	128:9bcdf88f62b0	794	*/
<>	128:9bcdf88f62b0	795
<>	128:9bcdf88f62b0	796	/** @defgroup RCC_LL_EF_LSI LSI
<>	128:9bcdf88f62b0	797	* @{
<>	128:9bcdf88f62b0	798	*/
<>	128:9bcdf88f62b0	799
<>	128:9bcdf88f62b0	800	/**
<>	128:9bcdf88f62b0	801	* @brief Enable LSI Oscillator
<>	128:9bcdf88f62b0	802	* @rmtoll CSR LSION LL_RCC_LSI_Enable
<>	128:9bcdf88f62b0	803	* @retval None
<>	128:9bcdf88f62b0	804	*/
<>	128:9bcdf88f62b0	805	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
<>	128:9bcdf88f62b0	806	{
<>	128:9bcdf88f62b0	807	SET_BIT(RCC->CSR, RCC_CSR_LSION);
<>	128:9bcdf88f62b0	808	}
<>	128:9bcdf88f62b0	809
<>	128:9bcdf88f62b0	810	/**
<>	128:9bcdf88f62b0	811	* @brief Disable LSI Oscillator
<>	128:9bcdf88f62b0	812	* @rmtoll CSR LSION LL_RCC_LSI_Disable
<>	128:9bcdf88f62b0	813	* @retval None
<>	128:9bcdf88f62b0	814	*/
<>	128:9bcdf88f62b0	815	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
<>	128:9bcdf88f62b0	816	{
<>	128:9bcdf88f62b0	817	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<>	128:9bcdf88f62b0	818	}
<>	128:9bcdf88f62b0	819
<>	128:9bcdf88f62b0	820	/**
<>	128:9bcdf88f62b0	821	* @brief Check if LSI is Ready
<>	128:9bcdf88f62b0	822	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<>	128:9bcdf88f62b0	823	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	824	*/
<>	128:9bcdf88f62b0	825	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<>	128:9bcdf88f62b0	826	{
<>	128:9bcdf88f62b0	827	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<>	128:9bcdf88f62b0	828	}
<>	128:9bcdf88f62b0	829
<>	128:9bcdf88f62b0	830	/**
<>	128:9bcdf88f62b0	831	* @}
<>	128:9bcdf88f62b0	832	*/
<>	128:9bcdf88f62b0	833
<>	128:9bcdf88f62b0	834	/** @defgroup RCC_LL_EF_MSI MSI
<>	128:9bcdf88f62b0	835	* @{
<>	128:9bcdf88f62b0	836	*/
<>	128:9bcdf88f62b0	837
<>	128:9bcdf88f62b0	838	/**
<>	128:9bcdf88f62b0	839	* @brief Enable MSI oscillator
<>	128:9bcdf88f62b0	840	* @rmtoll CR MSION LL_RCC_MSI_Enable
<>	128:9bcdf88f62b0	841	* @retval None
<>	128:9bcdf88f62b0	842	*/
<>	128:9bcdf88f62b0	843	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
<>	128:9bcdf88f62b0	844	{
<>	128:9bcdf88f62b0	845	SET_BIT(RCC->CR, RCC_CR_MSION);
<>	128:9bcdf88f62b0	846	}
<>	128:9bcdf88f62b0	847
<>	128:9bcdf88f62b0	848	/**
<>	128:9bcdf88f62b0	849	* @brief Disable MSI oscillator
<>	128:9bcdf88f62b0	850	* @rmtoll CR MSION LL_RCC_MSI_Disable
<>	128:9bcdf88f62b0	851	* @retval None
<>	128:9bcdf88f62b0	852	*/
<>	128:9bcdf88f62b0	853	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
<>	128:9bcdf88f62b0	854	{
<>	128:9bcdf88f62b0	855	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
<>	128:9bcdf88f62b0	856	}
<>	128:9bcdf88f62b0	857
<>	128:9bcdf88f62b0	858	/**
<>	128:9bcdf88f62b0	859	* @brief Check if MSI oscillator Ready
<>	128:9bcdf88f62b0	860	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
<>	128:9bcdf88f62b0	861	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	862	*/
<>	128:9bcdf88f62b0	863	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
<>	128:9bcdf88f62b0	864	{
<>	128:9bcdf88f62b0	865	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
<>	128:9bcdf88f62b0	866	}
<>	128:9bcdf88f62b0	867
<>	128:9bcdf88f62b0	868	/**
<>	128:9bcdf88f62b0	869	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
<>	128:9bcdf88f62b0	870	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange
<>	128:9bcdf88f62b0	871	* @param Range This parameter can be one of the following values:
<>	128:9bcdf88f62b0	872	* @arg @ref LL_RCC_MSIRANGE_0
<>	128:9bcdf88f62b0	873	* @arg @ref LL_RCC_MSIRANGE_1
<>	128:9bcdf88f62b0	874	* @arg @ref LL_RCC_MSIRANGE_2
<>	128:9bcdf88f62b0	875	* @arg @ref LL_RCC_MSIRANGE_3
<>	128:9bcdf88f62b0	876	* @arg @ref LL_RCC_MSIRANGE_4
<>	128:9bcdf88f62b0	877	* @arg @ref LL_RCC_MSIRANGE_5
<>	128:9bcdf88f62b0	878	* @arg @ref LL_RCC_MSIRANGE_6
<>	128:9bcdf88f62b0	879	* @retval None
<>	128:9bcdf88f62b0	880	*/
<>	128:9bcdf88f62b0	881	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
<>	128:9bcdf88f62b0	882	{
<>	128:9bcdf88f62b0	883	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
<>	128:9bcdf88f62b0	884	}
<>	128:9bcdf88f62b0	885
<>	128:9bcdf88f62b0	886	/**
<>	128:9bcdf88f62b0	887	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
<>	128:9bcdf88f62b0	888	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange
<>	128:9bcdf88f62b0	889	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	890	* @arg @ref LL_RCC_MSIRANGE_0
<>	128:9bcdf88f62b0	891	* @arg @ref LL_RCC_MSIRANGE_1
<>	128:9bcdf88f62b0	892	* @arg @ref LL_RCC_MSIRANGE_2
<>	128:9bcdf88f62b0	893	* @arg @ref LL_RCC_MSIRANGE_3
<>	128:9bcdf88f62b0	894	* @arg @ref LL_RCC_MSIRANGE_4
<>	128:9bcdf88f62b0	895	* @arg @ref LL_RCC_MSIRANGE_5
<>	128:9bcdf88f62b0	896	* @arg @ref LL_RCC_MSIRANGE_6
<>	128:9bcdf88f62b0	897	*/
<>	128:9bcdf88f62b0	898	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
<>	128:9bcdf88f62b0	899	{
<>	128:9bcdf88f62b0	900	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
<>	128:9bcdf88f62b0	901	}
<>	128:9bcdf88f62b0	902
<>	128:9bcdf88f62b0	903	/**
<>	128:9bcdf88f62b0	904	* @brief Get MSI Calibration value
<>	128:9bcdf88f62b0	905	* @note When MSITRIM is written, MSICAL is updated with the sum of
<>	128:9bcdf88f62b0	906	* MSITRIM and the factory trim value
<>	128:9bcdf88f62b0	907	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
<>	128:9bcdf88f62b0	908	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	128:9bcdf88f62b0	909	*/
<>	128:9bcdf88f62b0	910	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
<>	128:9bcdf88f62b0	911	{
<>	128:9bcdf88f62b0	912	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
<>	128:9bcdf88f62b0	913	}
<>	128:9bcdf88f62b0	914
<>	128:9bcdf88f62b0	915	/**
<>	128:9bcdf88f62b0	916	* @brief Set MSI Calibration trimming
<>	128:9bcdf88f62b0	917	* @note user-programmable trimming value that is added to the MSICAL
<>	128:9bcdf88f62b0	918	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
<>	128:9bcdf88f62b0	919	* @param Value between Min_Data = 0x00 and Max_Data = 0xFF
<>	128:9bcdf88f62b0	920	* @retval None
<>	128:9bcdf88f62b0	921	*/
<>	128:9bcdf88f62b0	922	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
<>	128:9bcdf88f62b0	923	{
<>	128:9bcdf88f62b0	924	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
<>	128:9bcdf88f62b0	925	}
<>	128:9bcdf88f62b0	926
<>	128:9bcdf88f62b0	927	/**
<>	128:9bcdf88f62b0	928	* @brief Get MSI Calibration trimming
<>	128:9bcdf88f62b0	929	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
<>	128:9bcdf88f62b0	930	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	128:9bcdf88f62b0	931	*/
<>	128:9bcdf88f62b0	932	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
<>	128:9bcdf88f62b0	933	{
<>	128:9bcdf88f62b0	934	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
<>	128:9bcdf88f62b0	935	}
<>	128:9bcdf88f62b0	936
<>	128:9bcdf88f62b0	937	/**
<>	128:9bcdf88f62b0	938	* @}
<>	128:9bcdf88f62b0	939	*/
<>	128:9bcdf88f62b0	940
<>	128:9bcdf88f62b0	941	/** @defgroup RCC_LL_EF_System System
<>	128:9bcdf88f62b0	942	* @{
<>	128:9bcdf88f62b0	943	*/
<>	128:9bcdf88f62b0	944
<>	128:9bcdf88f62b0	945	/**
<>	128:9bcdf88f62b0	946	* @brief Configure the system clock source
<>	128:9bcdf88f62b0	947	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
<>	128:9bcdf88f62b0	948	* @param Source This parameter can be one of the following values:
<>	128:9bcdf88f62b0	949	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
<>	128:9bcdf88f62b0	950	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<>	128:9bcdf88f62b0	951	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<>	128:9bcdf88f62b0	952	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<>	128:9bcdf88f62b0	953	* @retval None
<>	128:9bcdf88f62b0	954	*/
<>	128:9bcdf88f62b0	955	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<>	128:9bcdf88f62b0	956	{
<>	128:9bcdf88f62b0	957	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<>	128:9bcdf88f62b0	958	}
<>	128:9bcdf88f62b0	959
<>	128:9bcdf88f62b0	960	/**
<>	128:9bcdf88f62b0	961	* @brief Get the system clock source
<>	128:9bcdf88f62b0	962	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<>	128:9bcdf88f62b0	963	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	964	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
<>	128:9bcdf88f62b0	965	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<>	128:9bcdf88f62b0	966	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<>	128:9bcdf88f62b0	967	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<>	128:9bcdf88f62b0	968	*/
<>	128:9bcdf88f62b0	969	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<>	128:9bcdf88f62b0	970	{
<>	128:9bcdf88f62b0	971	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<>	128:9bcdf88f62b0	972	}
<>	128:9bcdf88f62b0	973
<>	128:9bcdf88f62b0	974	/**
<>	128:9bcdf88f62b0	975	* @brief Set AHB prescaler
<>	128:9bcdf88f62b0	976	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<>	128:9bcdf88f62b0	977	* @param Prescaler This parameter can be one of the following values:
<>	128:9bcdf88f62b0	978	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	128:9bcdf88f62b0	979	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	128:9bcdf88f62b0	980	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	128:9bcdf88f62b0	981	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	128:9bcdf88f62b0	982	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	128:9bcdf88f62b0	983	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	128:9bcdf88f62b0	984	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	128:9bcdf88f62b0	985	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	128:9bcdf88f62b0	986	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	128:9bcdf88f62b0	987	* @retval None
<>	128:9bcdf88f62b0	988	*/
<>	128:9bcdf88f62b0	989	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<>	128:9bcdf88f62b0	990	{
<>	128:9bcdf88f62b0	991	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<>	128:9bcdf88f62b0	992	}
<>	128:9bcdf88f62b0	993
<>	128:9bcdf88f62b0	994	/**
<>	128:9bcdf88f62b0	995	* @brief Set APB1 prescaler
<>	128:9bcdf88f62b0	996	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
<>	128:9bcdf88f62b0	997	* @param Prescaler This parameter can be one of the following values:
<>	128:9bcdf88f62b0	998	* @arg @ref LL_RCC_APB1_DIV_1
<>	128:9bcdf88f62b0	999	* @arg @ref LL_RCC_APB1_DIV_2
<>	128:9bcdf88f62b0	1000	* @arg @ref LL_RCC_APB1_DIV_4
<>	128:9bcdf88f62b0	1001	* @arg @ref LL_RCC_APB1_DIV_8
<>	128:9bcdf88f62b0	1002	* @arg @ref LL_RCC_APB1_DIV_16
<>	128:9bcdf88f62b0	1003	* @retval None
<>	128:9bcdf88f62b0	1004	*/
<>	128:9bcdf88f62b0	1005	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<>	128:9bcdf88f62b0	1006	{
<>	128:9bcdf88f62b0	1007	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
<>	128:9bcdf88f62b0	1008	}
<>	128:9bcdf88f62b0	1009
<>	128:9bcdf88f62b0	1010	/**
<>	128:9bcdf88f62b0	1011	* @brief Set APB2 prescaler
<>	128:9bcdf88f62b0	1012	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
<>	128:9bcdf88f62b0	1013	* @param Prescaler This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1014	* @arg @ref LL_RCC_APB2_DIV_1
<>	128:9bcdf88f62b0	1015	* @arg @ref LL_RCC_APB2_DIV_2
<>	128:9bcdf88f62b0	1016	* @arg @ref LL_RCC_APB2_DIV_4
<>	128:9bcdf88f62b0	1017	* @arg @ref LL_RCC_APB2_DIV_8
<>	128:9bcdf88f62b0	1018	* @arg @ref LL_RCC_APB2_DIV_16
<>	128:9bcdf88f62b0	1019	* @retval None
<>	128:9bcdf88f62b0	1020	*/
<>	128:9bcdf88f62b0	1021	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
<>	128:9bcdf88f62b0	1022	{
<>	128:9bcdf88f62b0	1023	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
<>	128:9bcdf88f62b0	1024	}
<>	128:9bcdf88f62b0	1025
<>	128:9bcdf88f62b0	1026	/**
<>	128:9bcdf88f62b0	1027	* @brief Get AHB prescaler
<>	128:9bcdf88f62b0	1028	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<>	128:9bcdf88f62b0	1029	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1030	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	128:9bcdf88f62b0	1031	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	128:9bcdf88f62b0	1032	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	128:9bcdf88f62b0	1033	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	128:9bcdf88f62b0	1034	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	128:9bcdf88f62b0	1035	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	128:9bcdf88f62b0	1036	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	128:9bcdf88f62b0	1037	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	128:9bcdf88f62b0	1038	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	128:9bcdf88f62b0	1039	*/
<>	128:9bcdf88f62b0	1040	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<>	128:9bcdf88f62b0	1041	{
<>	128:9bcdf88f62b0	1042	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<>	128:9bcdf88f62b0	1043	}
<>	128:9bcdf88f62b0	1044
<>	128:9bcdf88f62b0	1045	/**
<>	128:9bcdf88f62b0	1046	* @brief Get APB1 prescaler
<>	128:9bcdf88f62b0	1047	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
<>	128:9bcdf88f62b0	1048	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1049	* @arg @ref LL_RCC_APB1_DIV_1
<>	128:9bcdf88f62b0	1050	* @arg @ref LL_RCC_APB1_DIV_2
<>	128:9bcdf88f62b0	1051	* @arg @ref LL_RCC_APB1_DIV_4
<>	128:9bcdf88f62b0	1052	* @arg @ref LL_RCC_APB1_DIV_8
<>	128:9bcdf88f62b0	1053	* @arg @ref LL_RCC_APB1_DIV_16
<>	128:9bcdf88f62b0	1054	*/
<>	128:9bcdf88f62b0	1055	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<>	128:9bcdf88f62b0	1056	{
<>	128:9bcdf88f62b0	1057	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
<>	128:9bcdf88f62b0	1058	}
<>	128:9bcdf88f62b0	1059
<>	128:9bcdf88f62b0	1060	/**
<>	128:9bcdf88f62b0	1061	* @brief Get APB2 prescaler
<>	128:9bcdf88f62b0	1062	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
<>	128:9bcdf88f62b0	1063	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1064	* @arg @ref LL_RCC_APB2_DIV_1
<>	128:9bcdf88f62b0	1065	* @arg @ref LL_RCC_APB2_DIV_2
<>	128:9bcdf88f62b0	1066	* @arg @ref LL_RCC_APB2_DIV_4
<>	128:9bcdf88f62b0	1067	* @arg @ref LL_RCC_APB2_DIV_8
<>	128:9bcdf88f62b0	1068	* @arg @ref LL_RCC_APB2_DIV_16
<>	128:9bcdf88f62b0	1069	*/
<>	128:9bcdf88f62b0	1070	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
<>	128:9bcdf88f62b0	1071	{
<>	128:9bcdf88f62b0	1072	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
<>	128:9bcdf88f62b0	1073	}
<>	128:9bcdf88f62b0	1074
<>	128:9bcdf88f62b0	1075	/**
<>	128:9bcdf88f62b0	1076	* @}
<>	128:9bcdf88f62b0	1077	*/
<>	128:9bcdf88f62b0	1078
<>	128:9bcdf88f62b0	1079	/** @defgroup RCC_LL_EF_MCO MCO
<>	128:9bcdf88f62b0	1080	* @{
<>	128:9bcdf88f62b0	1081	*/
<>	128:9bcdf88f62b0	1082
<>	128:9bcdf88f62b0	1083	/**
<>	128:9bcdf88f62b0	1084	* @brief Configure MCOx
<>	128:9bcdf88f62b0	1085	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
<>	128:9bcdf88f62b0	1086	* CFGR MCOPRE LL_RCC_ConfigMCO
<>	128:9bcdf88f62b0	1087	* @param MCOxSource This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1088	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<>	128:9bcdf88f62b0	1089	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<>	128:9bcdf88f62b0	1090	* @arg @ref LL_RCC_MCO1SOURCE_HSI
<>	128:9bcdf88f62b0	1091	* @arg @ref LL_RCC_MCO1SOURCE_MSI
<>	128:9bcdf88f62b0	1092	* @arg @ref LL_RCC_MCO1SOURCE_HSE
<>	128:9bcdf88f62b0	1093	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
<>	128:9bcdf88f62b0	1094	* @arg @ref LL_RCC_MCO1SOURCE_LSI
<>	128:9bcdf88f62b0	1095	* @arg @ref LL_RCC_MCO1SOURCE_LSE
<>	128:9bcdf88f62b0	1096	* @param MCOxPrescaler This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1097	* @arg @ref LL_RCC_MCO1_DIV_1
<>	128:9bcdf88f62b0	1098	* @arg @ref LL_RCC_MCO1_DIV_2
<>	128:9bcdf88f62b0	1099	* @arg @ref LL_RCC_MCO1_DIV_4
<>	128:9bcdf88f62b0	1100	* @arg @ref LL_RCC_MCO1_DIV_8
<>	128:9bcdf88f62b0	1101	* @arg @ref LL_RCC_MCO1_DIV_16
<>	128:9bcdf88f62b0	1102	* @retval None
<>	128:9bcdf88f62b0	1103	*/
<>	128:9bcdf88f62b0	1104	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
<>	128:9bcdf88f62b0	1105	{
<>	128:9bcdf88f62b0	1106	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
<>	128:9bcdf88f62b0	1107	}
<>	128:9bcdf88f62b0	1108
<>	128:9bcdf88f62b0	1109	/**
<>	128:9bcdf88f62b0	1110	* @}
<>	128:9bcdf88f62b0	1111	*/
<>	128:9bcdf88f62b0	1112
<>	128:9bcdf88f62b0	1113
<>	128:9bcdf88f62b0	1114
<>	128:9bcdf88f62b0	1115	/** @defgroup RCC_LL_EF_RTC RTC
<>	128:9bcdf88f62b0	1116	* @{
<>	128:9bcdf88f62b0	1117	*/
<>	128:9bcdf88f62b0	1118
<>	128:9bcdf88f62b0	1119	/**
<>	128:9bcdf88f62b0	1120	* @brief Set RTC Clock Source
<>	128:9bcdf88f62b0	1121	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
<>	128:9bcdf88f62b0	1122	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
<>	128:9bcdf88f62b0	1123	* set). The RTCRST bit can be used to reset them.
<>	128:9bcdf88f62b0	1124	* @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource
<>	128:9bcdf88f62b0	1125	* @param Source This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1126	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	128:9bcdf88f62b0	1127	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	128:9bcdf88f62b0	1128	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	128:9bcdf88f62b0	1129	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
<>	128:9bcdf88f62b0	1130	* @retval None
<>	128:9bcdf88f62b0	1131	*/
<>	128:9bcdf88f62b0	1132	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<>	128:9bcdf88f62b0	1133	{
<>	128:9bcdf88f62b0	1134	MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
<>	128:9bcdf88f62b0	1135	}
<>	128:9bcdf88f62b0	1136
<>	128:9bcdf88f62b0	1137	/**
<>	128:9bcdf88f62b0	1138	* @brief Get RTC Clock Source
<>	128:9bcdf88f62b0	1139	* @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource
<>	128:9bcdf88f62b0	1140	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1141	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	128:9bcdf88f62b0	1142	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	128:9bcdf88f62b0	1143	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	128:9bcdf88f62b0	1144	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
<>	128:9bcdf88f62b0	1145	*/
<>	128:9bcdf88f62b0	1146	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<>	128:9bcdf88f62b0	1147	{
<>	128:9bcdf88f62b0	1148	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
<>	128:9bcdf88f62b0	1149	}
<>	128:9bcdf88f62b0	1150
<>	128:9bcdf88f62b0	1151	/**
<>	128:9bcdf88f62b0	1152	* @brief Enable RTC
<>	128:9bcdf88f62b0	1153	* @rmtoll CSR RTCEN LL_RCC_EnableRTC
<>	128:9bcdf88f62b0	1154	* @retval None
<>	128:9bcdf88f62b0	1155	*/
<>	128:9bcdf88f62b0	1156	__STATIC_INLINE void LL_RCC_EnableRTC(void)
<>	128:9bcdf88f62b0	1157	{
<>	128:9bcdf88f62b0	1158	SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
<>	128:9bcdf88f62b0	1159	}
<>	128:9bcdf88f62b0	1160
<>	128:9bcdf88f62b0	1161	/**
<>	128:9bcdf88f62b0	1162	* @brief Disable RTC
<>	128:9bcdf88f62b0	1163	* @rmtoll CSR RTCEN LL_RCC_DisableRTC
<>	128:9bcdf88f62b0	1164	* @retval None
<>	128:9bcdf88f62b0	1165	*/
<>	128:9bcdf88f62b0	1166	__STATIC_INLINE void LL_RCC_DisableRTC(void)
<>	128:9bcdf88f62b0	1167	{
<>	128:9bcdf88f62b0	1168	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
<>	128:9bcdf88f62b0	1169	}
<>	128:9bcdf88f62b0	1170
<>	128:9bcdf88f62b0	1171	/**
<>	128:9bcdf88f62b0	1172	* @brief Check if RTC has been enabled or not
<>	128:9bcdf88f62b0	1173	* @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC
<>	128:9bcdf88f62b0	1174	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1175	*/
<>	128:9bcdf88f62b0	1176	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<>	128:9bcdf88f62b0	1177	{
<>	128:9bcdf88f62b0	1178	return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN));
<>	128:9bcdf88f62b0	1179	}
<>	128:9bcdf88f62b0	1180
<>	128:9bcdf88f62b0	1181	/**
<>	128:9bcdf88f62b0	1182	* @brief Force the Backup domain reset
<>	128:9bcdf88f62b0	1183	* @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset
<>	128:9bcdf88f62b0	1184	* @retval None
<>	128:9bcdf88f62b0	1185	*/
<>	128:9bcdf88f62b0	1186	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<>	128:9bcdf88f62b0	1187	{
<>	128:9bcdf88f62b0	1188	SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
<>	128:9bcdf88f62b0	1189	}
<>	128:9bcdf88f62b0	1190
<>	128:9bcdf88f62b0	1191	/**
<>	128:9bcdf88f62b0	1192	* @brief Release the Backup domain reset
<>	128:9bcdf88f62b0	1193	* @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset
<>	128:9bcdf88f62b0	1194	* @retval None
<>	128:9bcdf88f62b0	1195	*/
<>	128:9bcdf88f62b0	1196	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<>	128:9bcdf88f62b0	1197	{
<>	128:9bcdf88f62b0	1198	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
<>	128:9bcdf88f62b0	1199	}
<>	128:9bcdf88f62b0	1200
<>	128:9bcdf88f62b0	1201	/**
<>	128:9bcdf88f62b0	1202	* @}
<>	128:9bcdf88f62b0	1203	*/
<>	128:9bcdf88f62b0	1204
<>	128:9bcdf88f62b0	1205	/** @defgroup RCC_LL_EF_PLL PLL
<>	128:9bcdf88f62b0	1206	* @{
<>	128:9bcdf88f62b0	1207	*/
<>	128:9bcdf88f62b0	1208
<>	128:9bcdf88f62b0	1209	/**
<>	128:9bcdf88f62b0	1210	* @brief Enable PLL
<>	128:9bcdf88f62b0	1211	* @rmtoll CR PLLON LL_RCC_PLL_Enable
<>	128:9bcdf88f62b0	1212	* @retval None
<>	128:9bcdf88f62b0	1213	*/
<>	128:9bcdf88f62b0	1214	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
<>	128:9bcdf88f62b0	1215	{
<>	128:9bcdf88f62b0	1216	SET_BIT(RCC->CR, RCC_CR_PLLON);
<>	128:9bcdf88f62b0	1217	}
<>	128:9bcdf88f62b0	1218
<>	128:9bcdf88f62b0	1219	/**
<>	128:9bcdf88f62b0	1220	* @brief Disable PLL
<>	128:9bcdf88f62b0	1221	* @note Cannot be disabled if the PLL clock is used as the system clock
<>	128:9bcdf88f62b0	1222	* @rmtoll CR PLLON LL_RCC_PLL_Disable
<>	128:9bcdf88f62b0	1223	* @retval None
<>	128:9bcdf88f62b0	1224	*/
<>	128:9bcdf88f62b0	1225	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
<>	128:9bcdf88f62b0	1226	{
<>	128:9bcdf88f62b0	1227	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<>	128:9bcdf88f62b0	1228	}
<>	128:9bcdf88f62b0	1229
<>	128:9bcdf88f62b0	1230	/**
<>	128:9bcdf88f62b0	1231	* @brief Check if PLL Ready
<>	128:9bcdf88f62b0	1232	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<>	128:9bcdf88f62b0	1233	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1234	*/
<>	128:9bcdf88f62b0	1235	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<>	128:9bcdf88f62b0	1236	{
<>	128:9bcdf88f62b0	1237	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<>	128:9bcdf88f62b0	1238	}
<>	128:9bcdf88f62b0	1239
<>	128:9bcdf88f62b0	1240	/**
<>	128:9bcdf88f62b0	1241	* @brief Configure PLL used for SYSCLK Domain
<>	128:9bcdf88f62b0	1242	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	128:9bcdf88f62b0	1243	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
<>	128:9bcdf88f62b0	1244	* CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS
<>	128:9bcdf88f62b0	1245	* @param Source This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1246	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	128:9bcdf88f62b0	1247	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	128:9bcdf88f62b0	1248	* @param PLLMul This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1249	* @arg @ref LL_RCC_PLL_MUL_3
<>	128:9bcdf88f62b0	1250	* @arg @ref LL_RCC_PLL_MUL_4
<>	128:9bcdf88f62b0	1251	* @arg @ref LL_RCC_PLL_MUL_6
<>	128:9bcdf88f62b0	1252	* @arg @ref LL_RCC_PLL_MUL_8
<>	128:9bcdf88f62b0	1253	* @arg @ref LL_RCC_PLL_MUL_12
<>	128:9bcdf88f62b0	1254	* @arg @ref LL_RCC_PLL_MUL_16
<>	128:9bcdf88f62b0	1255	* @arg @ref LL_RCC_PLL_MUL_24
<>	128:9bcdf88f62b0	1256	* @arg @ref LL_RCC_PLL_MUL_32
<>	128:9bcdf88f62b0	1257	* @arg @ref LL_RCC_PLL_MUL_48
<>	128:9bcdf88f62b0	1258	* @param PLLDiv This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1259	* @arg @ref LL_RCC_PLL_DIV_2
<>	128:9bcdf88f62b0	1260	* @arg @ref LL_RCC_PLL_DIV_3
<>	128:9bcdf88f62b0	1261	* @arg @ref LL_RCC_PLL_DIV_4
<>	128:9bcdf88f62b0	1262	* @retval None
<>	128:9bcdf88f62b0	1263	*/
<>	128:9bcdf88f62b0	1264	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
<>	128:9bcdf88f62b0	1265	{
<>	128:9bcdf88f62b0	1266	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV, Source \| PLLMul \| PLLDiv);
<>	128:9bcdf88f62b0	1267	}
<>	128:9bcdf88f62b0	1268
<>	128:9bcdf88f62b0	1269	/**
<>	128:9bcdf88f62b0	1270	* @brief Get the oscillator used as PLL clock source.
<>	128:9bcdf88f62b0	1271	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
<>	128:9bcdf88f62b0	1272	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1273	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	128:9bcdf88f62b0	1274	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	128:9bcdf88f62b0	1275	*/
<>	128:9bcdf88f62b0	1276	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<>	128:9bcdf88f62b0	1277	{
<>	128:9bcdf88f62b0	1278	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
<>	128:9bcdf88f62b0	1279	}
<>	128:9bcdf88f62b0	1280
<>	128:9bcdf88f62b0	1281	/**
<>	128:9bcdf88f62b0	1282	* @brief Get PLL multiplication Factor
<>	128:9bcdf88f62b0	1283	* @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
<>	128:9bcdf88f62b0	1284	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1285	* @arg @ref LL_RCC_PLL_MUL_3
<>	128:9bcdf88f62b0	1286	* @arg @ref LL_RCC_PLL_MUL_4
<>	128:9bcdf88f62b0	1287	* @arg @ref LL_RCC_PLL_MUL_6
<>	128:9bcdf88f62b0	1288	* @arg @ref LL_RCC_PLL_MUL_8
<>	128:9bcdf88f62b0	1289	* @arg @ref LL_RCC_PLL_MUL_12
<>	128:9bcdf88f62b0	1290	* @arg @ref LL_RCC_PLL_MUL_16
<>	128:9bcdf88f62b0	1291	* @arg @ref LL_RCC_PLL_MUL_24
<>	128:9bcdf88f62b0	1292	* @arg @ref LL_RCC_PLL_MUL_32
<>	128:9bcdf88f62b0	1293	* @arg @ref LL_RCC_PLL_MUL_48
<>	128:9bcdf88f62b0	1294	*/
<>	128:9bcdf88f62b0	1295	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
<>	128:9bcdf88f62b0	1296	{
<>	128:9bcdf88f62b0	1297	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
<>	128:9bcdf88f62b0	1298	}
<>	128:9bcdf88f62b0	1299
<>	128:9bcdf88f62b0	1300	/**
<>	128:9bcdf88f62b0	1301	* @brief Get Division factor for the main PLL and other PLL
<>	128:9bcdf88f62b0	1302	* @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider
<>	128:9bcdf88f62b0	1303	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1304	* @arg @ref LL_RCC_PLL_DIV_2
<>	128:9bcdf88f62b0	1305	* @arg @ref LL_RCC_PLL_DIV_3
<>	128:9bcdf88f62b0	1306	* @arg @ref LL_RCC_PLL_DIV_4
<>	128:9bcdf88f62b0	1307	*/
<>	128:9bcdf88f62b0	1308	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
<>	128:9bcdf88f62b0	1309	{
<>	128:9bcdf88f62b0	1310	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
<>	128:9bcdf88f62b0	1311	}
<>	128:9bcdf88f62b0	1312
<>	128:9bcdf88f62b0	1313	/**
<>	128:9bcdf88f62b0	1314	* @}
<>	128:9bcdf88f62b0	1315	*/
<>	128:9bcdf88f62b0	1316
<>	128:9bcdf88f62b0	1317	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<>	128:9bcdf88f62b0	1318	* @{
<>	128:9bcdf88f62b0	1319	*/
<>	128:9bcdf88f62b0	1320
<>	128:9bcdf88f62b0	1321	/**
<>	128:9bcdf88f62b0	1322	* @brief Clear LSI ready interrupt flag
<>	128:9bcdf88f62b0	1323	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<>	128:9bcdf88f62b0	1324	* @retval None
<>	128:9bcdf88f62b0	1325	*/
<>	128:9bcdf88f62b0	1326	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<>	128:9bcdf88f62b0	1327	{
<>	128:9bcdf88f62b0	1328	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<>	128:9bcdf88f62b0	1329	}
<>	128:9bcdf88f62b0	1330
<>	128:9bcdf88f62b0	1331	/**
<>	128:9bcdf88f62b0	1332	* @brief Clear LSE ready interrupt flag
<>	128:9bcdf88f62b0	1333	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<>	128:9bcdf88f62b0	1334	* @retval None
<>	128:9bcdf88f62b0	1335	*/
<>	128:9bcdf88f62b0	1336	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<>	128:9bcdf88f62b0	1337	{
<>	128:9bcdf88f62b0	1338	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<>	128:9bcdf88f62b0	1339	}
<>	128:9bcdf88f62b0	1340
<>	128:9bcdf88f62b0	1341	/**
<>	128:9bcdf88f62b0	1342	* @brief Clear MSI ready interrupt flag
<>	128:9bcdf88f62b0	1343	* @rmtoll CIR MSIRDYC LL_RCC_ClearFlag_MSIRDY
<>	128:9bcdf88f62b0	1344	* @retval None
<>	128:9bcdf88f62b0	1345	*/
<>	128:9bcdf88f62b0	1346	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
<>	128:9bcdf88f62b0	1347	{
<>	128:9bcdf88f62b0	1348	SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
<>	128:9bcdf88f62b0	1349	}
<>	128:9bcdf88f62b0	1350
<>	128:9bcdf88f62b0	1351	/**
<>	128:9bcdf88f62b0	1352	* @brief Clear HSI ready interrupt flag
<>	128:9bcdf88f62b0	1353	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<>	128:9bcdf88f62b0	1354	* @retval None
<>	128:9bcdf88f62b0	1355	*/
<>	128:9bcdf88f62b0	1356	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<>	128:9bcdf88f62b0	1357	{
<>	128:9bcdf88f62b0	1358	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<>	128:9bcdf88f62b0	1359	}
<>	128:9bcdf88f62b0	1360
<>	128:9bcdf88f62b0	1361	/**
<>	128:9bcdf88f62b0	1362	* @brief Clear HSE ready interrupt flag
<>	128:9bcdf88f62b0	1363	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<>	128:9bcdf88f62b0	1364	* @retval None
<>	128:9bcdf88f62b0	1365	*/
<>	128:9bcdf88f62b0	1366	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<>	128:9bcdf88f62b0	1367	{
<>	128:9bcdf88f62b0	1368	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<>	128:9bcdf88f62b0	1369	}
<>	128:9bcdf88f62b0	1370
<>	128:9bcdf88f62b0	1371	/**
<>	128:9bcdf88f62b0	1372	* @brief Clear PLL ready interrupt flag
<>	128:9bcdf88f62b0	1373	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<>	128:9bcdf88f62b0	1374	* @retval None
<>	128:9bcdf88f62b0	1375	*/
<>	128:9bcdf88f62b0	1376	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<>	128:9bcdf88f62b0	1377	{
<>	128:9bcdf88f62b0	1378	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<>	128:9bcdf88f62b0	1379	}
<>	128:9bcdf88f62b0	1380
<>	128:9bcdf88f62b0	1381	/**
<>	128:9bcdf88f62b0	1382	* @brief Clear Clock security system interrupt flag
<>	128:9bcdf88f62b0	1383	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<>	128:9bcdf88f62b0	1384	* @retval None
<>	128:9bcdf88f62b0	1385	*/
<>	128:9bcdf88f62b0	1386	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<>	128:9bcdf88f62b0	1387	{
<>	128:9bcdf88f62b0	1388	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<>	128:9bcdf88f62b0	1389	}
<>	128:9bcdf88f62b0	1390
<>	128:9bcdf88f62b0	1391	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	1392	/**
<>	128:9bcdf88f62b0	1393	* @brief Clear LSE Clock security system interrupt flag
<>	128:9bcdf88f62b0	1394	* @rmtoll CIR LSECSSC LL_RCC_ClearFlag_LSECSS
<>	128:9bcdf88f62b0	1395	* @retval None
<>	128:9bcdf88f62b0	1396	*/
<>	128:9bcdf88f62b0	1397	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
<>	128:9bcdf88f62b0	1398	{
<>	128:9bcdf88f62b0	1399	SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
<>	128:9bcdf88f62b0	1400	}
<>	128:9bcdf88f62b0	1401
<>	128:9bcdf88f62b0	1402	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	1403	/**
<>	128:9bcdf88f62b0	1404	* @brief Check if LSI ready interrupt occurred or not
<>	128:9bcdf88f62b0	1405	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<>	128:9bcdf88f62b0	1406	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1407	*/
<>	128:9bcdf88f62b0	1408	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<>	128:9bcdf88f62b0	1409	{
<>	128:9bcdf88f62b0	1410	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<>	128:9bcdf88f62b0	1411	}
<>	128:9bcdf88f62b0	1412
<>	128:9bcdf88f62b0	1413	/**
<>	128:9bcdf88f62b0	1414	* @brief Check if LSE ready interrupt occurred or not
<>	128:9bcdf88f62b0	1415	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<>	128:9bcdf88f62b0	1416	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1417	*/
<>	128:9bcdf88f62b0	1418	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<>	128:9bcdf88f62b0	1419	{
<>	128:9bcdf88f62b0	1420	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<>	128:9bcdf88f62b0	1421	}
<>	128:9bcdf88f62b0	1422
<>	128:9bcdf88f62b0	1423	/**
<>	128:9bcdf88f62b0	1424	* @brief Check if MSI ready interrupt occurred or not
<>	128:9bcdf88f62b0	1425	* @rmtoll CIR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
<>	128:9bcdf88f62b0	1426	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1427	*/
<>	128:9bcdf88f62b0	1428	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
<>	128:9bcdf88f62b0	1429	{
<>	128:9bcdf88f62b0	1430	return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == (RCC_CIR_MSIRDYF));
<>	128:9bcdf88f62b0	1431	}
<>	128:9bcdf88f62b0	1432
<>	128:9bcdf88f62b0	1433	/**
<>	128:9bcdf88f62b0	1434	* @brief Check if HSI ready interrupt occurred or not
<>	128:9bcdf88f62b0	1435	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<>	128:9bcdf88f62b0	1436	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1437	*/
<>	128:9bcdf88f62b0	1438	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<>	128:9bcdf88f62b0	1439	{
<>	128:9bcdf88f62b0	1440	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<>	128:9bcdf88f62b0	1441	}
<>	128:9bcdf88f62b0	1442
<>	128:9bcdf88f62b0	1443	/**
<>	128:9bcdf88f62b0	1444	* @brief Check if HSE ready interrupt occurred or not
<>	128:9bcdf88f62b0	1445	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<>	128:9bcdf88f62b0	1446	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1447	*/
<>	128:9bcdf88f62b0	1448	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<>	128:9bcdf88f62b0	1449	{
<>	128:9bcdf88f62b0	1450	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<>	128:9bcdf88f62b0	1451	}
<>	128:9bcdf88f62b0	1452
<>	128:9bcdf88f62b0	1453	/**
<>	128:9bcdf88f62b0	1454	* @brief Check if PLL ready interrupt occurred or not
<>	128:9bcdf88f62b0	1455	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<>	128:9bcdf88f62b0	1456	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1457	*/
<>	128:9bcdf88f62b0	1458	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<>	128:9bcdf88f62b0	1459	{
<>	128:9bcdf88f62b0	1460	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<>	128:9bcdf88f62b0	1461	}
<>	128:9bcdf88f62b0	1462
<>	128:9bcdf88f62b0	1463	/**
<>	128:9bcdf88f62b0	1464	* @brief Check if Clock security system interrupt occurred or not
<>	128:9bcdf88f62b0	1465	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<>	128:9bcdf88f62b0	1466	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1467	*/
<>	128:9bcdf88f62b0	1468	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<>	128:9bcdf88f62b0	1469	{
<>	128:9bcdf88f62b0	1470	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<>	128:9bcdf88f62b0	1471	}
<>	128:9bcdf88f62b0	1472
<>	128:9bcdf88f62b0	1473	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	1474	/**
<>	128:9bcdf88f62b0	1475	* @brief Check if LSE Clock security system interrupt occurred or not
<>	128:9bcdf88f62b0	1476	* @rmtoll CIR LSECSSF LL_RCC_IsActiveFlag_LSECSS
<>	128:9bcdf88f62b0	1477	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1478	*/
<>	128:9bcdf88f62b0	1479	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
<>	128:9bcdf88f62b0	1480	{
<>	128:9bcdf88f62b0	1481	return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == (RCC_CIR_LSECSSF));
<>	128:9bcdf88f62b0	1482	}
<>	128:9bcdf88f62b0	1483
<>	128:9bcdf88f62b0	1484	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	1485	/**
<>	128:9bcdf88f62b0	1486	* @brief Check if RCC flag Independent Watchdog reset is set or not.
<>	128:9bcdf88f62b0	1487	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<>	128:9bcdf88f62b0	1488	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1489	*/
<>	128:9bcdf88f62b0	1490	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<>	128:9bcdf88f62b0	1491	{
<>	128:9bcdf88f62b0	1492	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<>	128:9bcdf88f62b0	1493	}
<>	128:9bcdf88f62b0	1494
<>	128:9bcdf88f62b0	1495	/**
<>	128:9bcdf88f62b0	1496	* @brief Check if RCC flag Low Power reset is set or not.
<>	128:9bcdf88f62b0	1497	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<>	128:9bcdf88f62b0	1498	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1499	*/
<>	128:9bcdf88f62b0	1500	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<>	128:9bcdf88f62b0	1501	{
<>	128:9bcdf88f62b0	1502	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<>	128:9bcdf88f62b0	1503	}
<>	128:9bcdf88f62b0	1504
<>	128:9bcdf88f62b0	1505	/**
<>	128:9bcdf88f62b0	1506	* @brief Check if RCC flag is set or not.
<>	128:9bcdf88f62b0	1507	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
<>	128:9bcdf88f62b0	1508	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1509	*/
<>	128:9bcdf88f62b0	1510	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
<>	128:9bcdf88f62b0	1511	{
<>	128:9bcdf88f62b0	1512	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
<>	128:9bcdf88f62b0	1513	}
<>	128:9bcdf88f62b0	1514
<>	128:9bcdf88f62b0	1515	/**
<>	128:9bcdf88f62b0	1516	* @brief Check if RCC flag Pin reset is set or not.
<>	128:9bcdf88f62b0	1517	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<>	128:9bcdf88f62b0	1518	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1519	*/
<>	128:9bcdf88f62b0	1520	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<>	128:9bcdf88f62b0	1521	{
<>	128:9bcdf88f62b0	1522	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<>	128:9bcdf88f62b0	1523	}
<>	128:9bcdf88f62b0	1524
<>	128:9bcdf88f62b0	1525	/**
<>	128:9bcdf88f62b0	1526	* @brief Check if RCC flag POR/PDR reset is set or not.
<>	128:9bcdf88f62b0	1527	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<>	128:9bcdf88f62b0	1528	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1529	*/
<>	128:9bcdf88f62b0	1530	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<>	128:9bcdf88f62b0	1531	{
<>	128:9bcdf88f62b0	1532	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<>	128:9bcdf88f62b0	1533	}
<>	128:9bcdf88f62b0	1534
<>	128:9bcdf88f62b0	1535	/**
<>	128:9bcdf88f62b0	1536	* @brief Check if RCC flag Software reset is set or not.
<>	128:9bcdf88f62b0	1537	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<>	128:9bcdf88f62b0	1538	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1539	*/
<>	128:9bcdf88f62b0	1540	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<>	128:9bcdf88f62b0	1541	{
<>	128:9bcdf88f62b0	1542	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<>	128:9bcdf88f62b0	1543	}
<>	128:9bcdf88f62b0	1544
<>	128:9bcdf88f62b0	1545	/**
<>	128:9bcdf88f62b0	1546	* @brief Check if RCC flag Window Watchdog reset is set or not.
<>	128:9bcdf88f62b0	1547	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<>	128:9bcdf88f62b0	1548	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1549	*/
<>	128:9bcdf88f62b0	1550	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<>	128:9bcdf88f62b0	1551	{
<>	128:9bcdf88f62b0	1552	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<>	128:9bcdf88f62b0	1553	}
<>	128:9bcdf88f62b0	1554
<>	128:9bcdf88f62b0	1555	/**
<>	128:9bcdf88f62b0	1556	* @brief Set RMVF bit to clear the reset flags.
<>	128:9bcdf88f62b0	1557	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<>	128:9bcdf88f62b0	1558	* @retval None
<>	128:9bcdf88f62b0	1559	*/
<>	128:9bcdf88f62b0	1560	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<>	128:9bcdf88f62b0	1561	{
<>	128:9bcdf88f62b0	1562	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	128:9bcdf88f62b0	1563	}
<>	128:9bcdf88f62b0	1564
<>	128:9bcdf88f62b0	1565	/**
<>	128:9bcdf88f62b0	1566	* @}
<>	128:9bcdf88f62b0	1567	*/
<>	128:9bcdf88f62b0	1568
<>	128:9bcdf88f62b0	1569	/** @defgroup RCC_LL_EF_IT_Management IT Management
<>	128:9bcdf88f62b0	1570	* @{
<>	128:9bcdf88f62b0	1571	*/
<>	128:9bcdf88f62b0	1572
<>	128:9bcdf88f62b0	1573	/**
<>	128:9bcdf88f62b0	1574	* @brief Enable LSI ready interrupt
<>	128:9bcdf88f62b0	1575	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<>	128:9bcdf88f62b0	1576	* @retval None
<>	128:9bcdf88f62b0	1577	*/
<>	128:9bcdf88f62b0	1578	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<>	128:9bcdf88f62b0	1579	{
<>	128:9bcdf88f62b0	1580	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	128:9bcdf88f62b0	1581	}
<>	128:9bcdf88f62b0	1582
<>	128:9bcdf88f62b0	1583	/**
<>	128:9bcdf88f62b0	1584	* @brief Enable LSE ready interrupt
<>	128:9bcdf88f62b0	1585	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<>	128:9bcdf88f62b0	1586	* @retval None
<>	128:9bcdf88f62b0	1587	*/
<>	128:9bcdf88f62b0	1588	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<>	128:9bcdf88f62b0	1589	{
<>	128:9bcdf88f62b0	1590	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	128:9bcdf88f62b0	1591	}
<>	128:9bcdf88f62b0	1592
<>	128:9bcdf88f62b0	1593	/**
<>	128:9bcdf88f62b0	1594	* @brief Enable MSI ready interrupt
<>	128:9bcdf88f62b0	1595	* @rmtoll CIR MSIRDYIE LL_RCC_EnableIT_MSIRDY
<>	128:9bcdf88f62b0	1596	* @retval None
<>	128:9bcdf88f62b0	1597	*/
<>	128:9bcdf88f62b0	1598	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
<>	128:9bcdf88f62b0	1599	{
<>	128:9bcdf88f62b0	1600	SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
<>	128:9bcdf88f62b0	1601	}
<>	128:9bcdf88f62b0	1602
<>	128:9bcdf88f62b0	1603	/**
<>	128:9bcdf88f62b0	1604	* @brief Enable HSI ready interrupt
<>	128:9bcdf88f62b0	1605	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<>	128:9bcdf88f62b0	1606	* @retval None
<>	128:9bcdf88f62b0	1607	*/
<>	128:9bcdf88f62b0	1608	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<>	128:9bcdf88f62b0	1609	{
<>	128:9bcdf88f62b0	1610	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	128:9bcdf88f62b0	1611	}
<>	128:9bcdf88f62b0	1612
<>	128:9bcdf88f62b0	1613	/**
<>	128:9bcdf88f62b0	1614	* @brief Enable HSE ready interrupt
<>	128:9bcdf88f62b0	1615	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<>	128:9bcdf88f62b0	1616	* @retval None
<>	128:9bcdf88f62b0	1617	*/
<>	128:9bcdf88f62b0	1618	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<>	128:9bcdf88f62b0	1619	{
<>	128:9bcdf88f62b0	1620	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	128:9bcdf88f62b0	1621	}
<>	128:9bcdf88f62b0	1622
<>	128:9bcdf88f62b0	1623	/**
<>	128:9bcdf88f62b0	1624	* @brief Enable PLL ready interrupt
<>	128:9bcdf88f62b0	1625	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<>	128:9bcdf88f62b0	1626	* @retval None
<>	128:9bcdf88f62b0	1627	*/
<>	128:9bcdf88f62b0	1628	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<>	128:9bcdf88f62b0	1629	{
<>	128:9bcdf88f62b0	1630	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	128:9bcdf88f62b0	1631	}
<>	128:9bcdf88f62b0	1632
<>	128:9bcdf88f62b0	1633	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	1634	/**
<>	128:9bcdf88f62b0	1635	* @brief Enable LSE clock security system interrupt
<>	128:9bcdf88f62b0	1636	* @rmtoll CIR LSECSSIE LL_RCC_EnableIT_LSECSS
<>	128:9bcdf88f62b0	1637	* @retval None
<>	128:9bcdf88f62b0	1638	*/
<>	128:9bcdf88f62b0	1639	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
<>	128:9bcdf88f62b0	1640	{
<>	128:9bcdf88f62b0	1641	SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
<>	128:9bcdf88f62b0	1642	}
<>	128:9bcdf88f62b0	1643
<>	128:9bcdf88f62b0	1644	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	1645	/**
<>	128:9bcdf88f62b0	1646	* @brief Disable LSI ready interrupt
<>	128:9bcdf88f62b0	1647	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<>	128:9bcdf88f62b0	1648	* @retval None
<>	128:9bcdf88f62b0	1649	*/
<>	128:9bcdf88f62b0	1650	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<>	128:9bcdf88f62b0	1651	{
<>	128:9bcdf88f62b0	1652	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	128:9bcdf88f62b0	1653	}
<>	128:9bcdf88f62b0	1654
<>	128:9bcdf88f62b0	1655	/**
<>	128:9bcdf88f62b0	1656	* @brief Disable LSE ready interrupt
<>	128:9bcdf88f62b0	1657	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<>	128:9bcdf88f62b0	1658	* @retval None
<>	128:9bcdf88f62b0	1659	*/
<>	128:9bcdf88f62b0	1660	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<>	128:9bcdf88f62b0	1661	{
<>	128:9bcdf88f62b0	1662	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	128:9bcdf88f62b0	1663	}
<>	128:9bcdf88f62b0	1664
<>	128:9bcdf88f62b0	1665	/**
<>	128:9bcdf88f62b0	1666	* @brief Disable MSI ready interrupt
<>	128:9bcdf88f62b0	1667	* @rmtoll CIR MSIRDYIE LL_RCC_DisableIT_MSIRDY
<>	128:9bcdf88f62b0	1668	* @retval None
<>	128:9bcdf88f62b0	1669	*/
<>	128:9bcdf88f62b0	1670	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
<>	128:9bcdf88f62b0	1671	{
<>	128:9bcdf88f62b0	1672	CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
<>	128:9bcdf88f62b0	1673	}
<>	128:9bcdf88f62b0	1674
<>	128:9bcdf88f62b0	1675	/**
<>	128:9bcdf88f62b0	1676	* @brief Disable HSI ready interrupt
<>	128:9bcdf88f62b0	1677	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<>	128:9bcdf88f62b0	1678	* @retval None
<>	128:9bcdf88f62b0	1679	*/
<>	128:9bcdf88f62b0	1680	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<>	128:9bcdf88f62b0	1681	{
<>	128:9bcdf88f62b0	1682	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	128:9bcdf88f62b0	1683	}
<>	128:9bcdf88f62b0	1684
<>	128:9bcdf88f62b0	1685	/**
<>	128:9bcdf88f62b0	1686	* @brief Disable HSE ready interrupt
<>	128:9bcdf88f62b0	1687	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<>	128:9bcdf88f62b0	1688	* @retval None
<>	128:9bcdf88f62b0	1689	*/
<>	128:9bcdf88f62b0	1690	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<>	128:9bcdf88f62b0	1691	{
<>	128:9bcdf88f62b0	1692	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	128:9bcdf88f62b0	1693	}
<>	128:9bcdf88f62b0	1694
<>	128:9bcdf88f62b0	1695	/**
<>	128:9bcdf88f62b0	1696	* @brief Disable PLL ready interrupt
<>	128:9bcdf88f62b0	1697	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<>	128:9bcdf88f62b0	1698	* @retval None
<>	128:9bcdf88f62b0	1699	*/
<>	128:9bcdf88f62b0	1700	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<>	128:9bcdf88f62b0	1701	{
<>	128:9bcdf88f62b0	1702	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	128:9bcdf88f62b0	1703	}
<>	128:9bcdf88f62b0	1704
<>	128:9bcdf88f62b0	1705	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	1706	/**
<>	128:9bcdf88f62b0	1707	* @brief Disable LSE clock security system interrupt
<>	128:9bcdf88f62b0	1708	* @rmtoll CIR LSECSSIE LL_RCC_DisableIT_LSECSS
<>	128:9bcdf88f62b0	1709	* @retval None
<>	128:9bcdf88f62b0	1710	*/
<>	128:9bcdf88f62b0	1711	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
<>	128:9bcdf88f62b0	1712	{
<>	128:9bcdf88f62b0	1713	CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
<>	128:9bcdf88f62b0	1714	}
<>	128:9bcdf88f62b0	1715
<>	128:9bcdf88f62b0	1716	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	1717	/**
<>	128:9bcdf88f62b0	1718	* @brief Checks if LSI ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1719	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<>	128:9bcdf88f62b0	1720	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1721	*/
<>	128:9bcdf88f62b0	1722	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<>	128:9bcdf88f62b0	1723	{
<>	128:9bcdf88f62b0	1724	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<>	128:9bcdf88f62b0	1725	}
<>	128:9bcdf88f62b0	1726
<>	128:9bcdf88f62b0	1727	/**
<>	128:9bcdf88f62b0	1728	* @brief Checks if LSE ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1729	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<>	128:9bcdf88f62b0	1730	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1731	*/
<>	128:9bcdf88f62b0	1732	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<>	128:9bcdf88f62b0	1733	{
<>	128:9bcdf88f62b0	1734	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<>	128:9bcdf88f62b0	1735	}
<>	128:9bcdf88f62b0	1736
<>	128:9bcdf88f62b0	1737	/**
<>	128:9bcdf88f62b0	1738	* @brief Checks if MSI ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1739	* @rmtoll CIR MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
<>	128:9bcdf88f62b0	1740	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1741	*/
<>	128:9bcdf88f62b0	1742	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
<>	128:9bcdf88f62b0	1743	{
<>	128:9bcdf88f62b0	1744	return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == (RCC_CIR_MSIRDYIE));
<>	128:9bcdf88f62b0	1745	}
<>	128:9bcdf88f62b0	1746
<>	128:9bcdf88f62b0	1747	/**
<>	128:9bcdf88f62b0	1748	* @brief Checks if HSI ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1749	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<>	128:9bcdf88f62b0	1750	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1751	*/
<>	128:9bcdf88f62b0	1752	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<>	128:9bcdf88f62b0	1753	{
<>	128:9bcdf88f62b0	1754	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<>	128:9bcdf88f62b0	1755	}
<>	128:9bcdf88f62b0	1756
<>	128:9bcdf88f62b0	1757	/**
<>	128:9bcdf88f62b0	1758	* @brief Checks if HSE ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1759	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<>	128:9bcdf88f62b0	1760	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1761	*/
<>	128:9bcdf88f62b0	1762	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<>	128:9bcdf88f62b0	1763	{
<>	128:9bcdf88f62b0	1764	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<>	128:9bcdf88f62b0	1765	}
<>	128:9bcdf88f62b0	1766
<>	128:9bcdf88f62b0	1767	/**
<>	128:9bcdf88f62b0	1768	* @brief Checks if PLL ready interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1769	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<>	128:9bcdf88f62b0	1770	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1771	*/
<>	128:9bcdf88f62b0	1772	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<>	128:9bcdf88f62b0	1773	{
<>	128:9bcdf88f62b0	1774	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<>	128:9bcdf88f62b0	1775	}
<>	128:9bcdf88f62b0	1776
<>	128:9bcdf88f62b0	1777	#if defined(RCC_LSECSS_SUPPORT)
<>	128:9bcdf88f62b0	1778	/**
<>	128:9bcdf88f62b0	1779	* @brief Checks if LSECSS interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	1780	* @rmtoll CIR LSECSSIE LL_RCC_IsEnabledIT_LSECSS
<>	128:9bcdf88f62b0	1781	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1782	*/
<>	128:9bcdf88f62b0	1783	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
<>	128:9bcdf88f62b0	1784	{
<>	128:9bcdf88f62b0	1785	return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == (RCC_CIR_LSECSSIE));
<>	128:9bcdf88f62b0	1786	}
<>	128:9bcdf88f62b0	1787
<>	128:9bcdf88f62b0	1788	#endif /* RCC_LSECSS_SUPPORT */
<>	128:9bcdf88f62b0	1789	/**
<>	128:9bcdf88f62b0	1790	* @}
<>	128:9bcdf88f62b0	1791	*/
<>	128:9bcdf88f62b0	1792
<>	128:9bcdf88f62b0	1793	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	1794	/** @defgroup RCC_LL_EF_Init De-initialization function
<>	128:9bcdf88f62b0	1795	* @{
<>	128:9bcdf88f62b0	1796	*/
<>	128:9bcdf88f62b0	1797	ErrorStatus LL_RCC_DeInit(void);
<>	128:9bcdf88f62b0	1798	/**
<>	128:9bcdf88f62b0	1799	* @}
<>	128:9bcdf88f62b0	1800	*/
<>	128:9bcdf88f62b0	1801
<>	128:9bcdf88f62b0	1802	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<>	128:9bcdf88f62b0	1803	* @{
<>	128:9bcdf88f62b0	1804	*/
<>	128:9bcdf88f62b0	1805	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<>	128:9bcdf88f62b0	1806	/**
<>	128:9bcdf88f62b0	1807	* @}
<>	128:9bcdf88f62b0	1808	*/
<>	128:9bcdf88f62b0	1809	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	1810
<>	128:9bcdf88f62b0	1811	/**
<>	128:9bcdf88f62b0	1812	* @}
<>	128:9bcdf88f62b0	1813	*/
<>	128:9bcdf88f62b0	1814
<>	128:9bcdf88f62b0	1815	/**
<>	128:9bcdf88f62b0	1816	* @}
<>	128:9bcdf88f62b0	1817	*/
<>	128:9bcdf88f62b0	1818
<>	128:9bcdf88f62b0	1819	#endif /* RCC */
<>	128:9bcdf88f62b0	1820
<>	128:9bcdf88f62b0	1821	/**
<>	128:9bcdf88f62b0	1822	* @}
<>	128:9bcdf88f62b0	1823	*/
<>	128:9bcdf88f62b0	1824
<>	128:9bcdf88f62b0	1825	#ifdef __cplusplus
<>	128:9bcdf88f62b0	1826	}
<>	128:9bcdf88f62b0	1827	#endif
<>	128:9bcdf88f62b0	1828
<>	128:9bcdf88f62b0	1829	#endif /* __STM32L1xx_LL_RCC_H */
<>	128:9bcdf88f62b0	1830
<>	128:9bcdf88f62b0	1831	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/