mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_i2c.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of I2C LL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_I2C_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_I2C_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_LL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	#if defined (I2C1) \|\| defined (I2C2)
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @defgroup I2C_LL I2C
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Private types -------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/* Private variables ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	61
<>	128:9bcdf88f62b0	62	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	128:9bcdf88f62b0	64	* @{
<>	128:9bcdf88f62b0	65	*/
<>	128:9bcdf88f62b0	66	/* Defines used for the bit position in the register and perform offsets */
<>	128:9bcdf88f62b0	67	#define LL_I2C_POSITION_SR2_PEC (uint32_t)POSITION_VAL(I2C_SR2_PEC)
<>	128:9bcdf88f62b0	68
<>	128:9bcdf88f62b0	69	/* Defines used to perform compute and check in the macros */
<>	128:9bcdf88f62b0	70	#define LL_I2C_MAX_SPEED_STANDARD 100000U
<>	128:9bcdf88f62b0	71	#define LL_I2C_MAX_SPEED_FAST 400000U
<>	128:9bcdf88f62b0	72	/**
<>	128:9bcdf88f62b0	73	* @}
<>	128:9bcdf88f62b0	74	*/
<>	128:9bcdf88f62b0	75
<>	128:9bcdf88f62b0	76	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	77	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	78	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	128:9bcdf88f62b0	79	* @{
<>	128:9bcdf88f62b0	80	*/
<>	128:9bcdf88f62b0	81	/**
<>	128:9bcdf88f62b0	82	* @}
<>	128:9bcdf88f62b0	83	*/
<>	128:9bcdf88f62b0	84	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	85
<>	128:9bcdf88f62b0	86	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	87	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	88	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	128:9bcdf88f62b0	89	* @{
<>	128:9bcdf88f62b0	90	*/
<>	128:9bcdf88f62b0	91	typedef struct
<>	128:9bcdf88f62b0	92	{
<>	128:9bcdf88f62b0	93	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	128:9bcdf88f62b0	94	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	128:9bcdf88f62b0	95
<>	128:9bcdf88f62b0	96	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	128:9bcdf88f62b0	97
<>	128:9bcdf88f62b0	98	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
<>	128:9bcdf88f62b0	99	This parameter must be set to a value lower than 400kHz (in Hz)
<>	128:9bcdf88f62b0	100
<>	128:9bcdf88f62b0	101	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
<>	128:9bcdf88f62b0	102	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
<>	128:9bcdf88f62b0	103
<>	128:9bcdf88f62b0	104	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
<>	128:9bcdf88f62b0	105	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
<>	128:9bcdf88f62b0	106
<>	128:9bcdf88f62b0	107	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
<>	128:9bcdf88f62b0	108
<>	128:9bcdf88f62b0	109	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	128:9bcdf88f62b0	110	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	128:9bcdf88f62b0	111
<>	128:9bcdf88f62b0	112	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	128:9bcdf88f62b0	113
<>	128:9bcdf88f62b0	114	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	128:9bcdf88f62b0	115	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	128:9bcdf88f62b0	116
<>	128:9bcdf88f62b0	117	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	128:9bcdf88f62b0	118
<>	128:9bcdf88f62b0	119	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	128:9bcdf88f62b0	120	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	128:9bcdf88f62b0	121
<>	128:9bcdf88f62b0	122	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	128:9bcdf88f62b0	123	} LL_I2C_InitTypeDef;
<>	128:9bcdf88f62b0	124	/**
<>	128:9bcdf88f62b0	125	* @}
<>	128:9bcdf88f62b0	126	*/
<>	128:9bcdf88f62b0	127	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	128
<>	128:9bcdf88f62b0	129	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	130	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	128:9bcdf88f62b0	131	* @{
<>	128:9bcdf88f62b0	132	*/
<>	128:9bcdf88f62b0	133
<>	128:9bcdf88f62b0	134	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	128:9bcdf88f62b0	135	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	128:9bcdf88f62b0	136	* @{
<>	128:9bcdf88f62b0	137	*/
<>	128:9bcdf88f62b0	138	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
<>	128:9bcdf88f62b0	139	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
<>	128:9bcdf88f62b0	140	Address matched flag (slave mode) */
<>	128:9bcdf88f62b0	141	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
<>	128:9bcdf88f62b0	142	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
<>	128:9bcdf88f62b0	143	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
<>	128:9bcdf88f62b0	144	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
<>	128:9bcdf88f62b0	145	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
<>	128:9bcdf88f62b0	146	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
<>	128:9bcdf88f62b0	147	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
<>	128:9bcdf88f62b0	148	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
<>	128:9bcdf88f62b0	149	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
<>	128:9bcdf88f62b0	150	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	128:9bcdf88f62b0	151	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	128:9bcdf88f62b0	152	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
<>	128:9bcdf88f62b0	153	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
<>	128:9bcdf88f62b0	154	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
<>	128:9bcdf88f62b0	155	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
<>	128:9bcdf88f62b0	156	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
<>	128:9bcdf88f62b0	157	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
<>	128:9bcdf88f62b0	158	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
<>	128:9bcdf88f62b0	159	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
<>	128:9bcdf88f62b0	160	/**
<>	128:9bcdf88f62b0	161	* @}
<>	128:9bcdf88f62b0	162	*/
<>	128:9bcdf88f62b0	163
<>	128:9bcdf88f62b0	164	/** @defgroup I2C_LL_EC_IT IT Defines
<>	128:9bcdf88f62b0	165	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	128:9bcdf88f62b0	166	* @{
<>	128:9bcdf88f62b0	167	*/
<>	128:9bcdf88f62b0	168	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
<>	128:9bcdf88f62b0	169	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
<>	128:9bcdf88f62b0	170	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
<>	128:9bcdf88f62b0	171	/**
<>	128:9bcdf88f62b0	172	* @}
<>	128:9bcdf88f62b0	173	*/
<>	128:9bcdf88f62b0	174
<>	128:9bcdf88f62b0	175	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	128:9bcdf88f62b0	176	* @{
<>	128:9bcdf88f62b0	177	*/
<>	128:9bcdf88f62b0	178	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
<>	128:9bcdf88f62b0	179	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
<>	128:9bcdf88f62b0	180	/**
<>	128:9bcdf88f62b0	181	* @}
<>	128:9bcdf88f62b0	182	*/
<>	128:9bcdf88f62b0	183
<>	128:9bcdf88f62b0	184	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
<>	128:9bcdf88f62b0	185	* @{
<>	128:9bcdf88f62b0	186	*/
<>	128:9bcdf88f62b0	187	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
<>	128:9bcdf88f62b0	188	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
<>	128:9bcdf88f62b0	189	/**
<>	128:9bcdf88f62b0	190	* @}
<>	128:9bcdf88f62b0	191	*/
<>	128:9bcdf88f62b0	192
<>	128:9bcdf88f62b0	193	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
<>	128:9bcdf88f62b0	194	* @{
<>	128:9bcdf88f62b0	195	*/
<>	128:9bcdf88f62b0	196	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
<>	128:9bcdf88f62b0	197	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
<>	128:9bcdf88f62b0	198	/**
<>	128:9bcdf88f62b0	199	* @}
<>	128:9bcdf88f62b0	200	*/
<>	128:9bcdf88f62b0	201
<>	128:9bcdf88f62b0	202	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	128:9bcdf88f62b0	203	* @{
<>	128:9bcdf88f62b0	204	*/
<>	128:9bcdf88f62b0	205	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
<>	128:9bcdf88f62b0	206	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
<>	128:9bcdf88f62b0	207	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
<>	128:9bcdf88f62b0	208	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
<>	128:9bcdf88f62b0	209	/**
<>	128:9bcdf88f62b0	210	* @}
<>	128:9bcdf88f62b0	211	*/
<>	128:9bcdf88f62b0	212
<>	128:9bcdf88f62b0	213	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	128:9bcdf88f62b0	214	* @{
<>	128:9bcdf88f62b0	215	*/
<>	128:9bcdf88f62b0	216	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
<>	128:9bcdf88f62b0	217	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
<>	128:9bcdf88f62b0	218	/**
<>	128:9bcdf88f62b0	219	* @}
<>	128:9bcdf88f62b0	220	*/
<>	128:9bcdf88f62b0	221
<>	128:9bcdf88f62b0	222	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	128:9bcdf88f62b0	223	* @{
<>	128:9bcdf88f62b0	224	*/
<>	128:9bcdf88f62b0	225	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
<>	128:9bcdf88f62b0	226	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
<>	128:9bcdf88f62b0	227	/**
<>	128:9bcdf88f62b0	228	* @}
<>	128:9bcdf88f62b0	229	*/
<>	128:9bcdf88f62b0	230
<>	128:9bcdf88f62b0	231	/**
<>	128:9bcdf88f62b0	232	* @}
<>	128:9bcdf88f62b0	233	*/
<>	128:9bcdf88f62b0	234
<>	128:9bcdf88f62b0	235	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	236	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	128:9bcdf88f62b0	237	* @{
<>	128:9bcdf88f62b0	238	*/
<>	128:9bcdf88f62b0	239
<>	128:9bcdf88f62b0	240	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	128:9bcdf88f62b0	241	* @{
<>	128:9bcdf88f62b0	242	*/
<>	128:9bcdf88f62b0	243
<>	128:9bcdf88f62b0	244	/**
<>	128:9bcdf88f62b0	245	* @brief Write a value in I2C register
<>	128:9bcdf88f62b0	246	* @param __INSTANCE__ I2C Instance
<>	128:9bcdf88f62b0	247	* @param __REG__ Register to be written
<>	128:9bcdf88f62b0	248	* @param __VALUE__ Value to be written in the register
<>	128:9bcdf88f62b0	249	* @retval None
<>	128:9bcdf88f62b0	250	*/
<>	128:9bcdf88f62b0	251	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	128:9bcdf88f62b0	252
<>	128:9bcdf88f62b0	253	/**
<>	128:9bcdf88f62b0	254	* @brief Read a value in I2C register
<>	128:9bcdf88f62b0	255	* @param __INSTANCE__ I2C Instance
<>	128:9bcdf88f62b0	256	* @param __REG__ Register to be read
<>	128:9bcdf88f62b0	257	* @retval Register value
<>	128:9bcdf88f62b0	258	*/
<>	128:9bcdf88f62b0	259	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	128:9bcdf88f62b0	260	/**
<>	128:9bcdf88f62b0	261	* @}
<>	128:9bcdf88f62b0	262	*/
<>	128:9bcdf88f62b0	263
<>	128:9bcdf88f62b0	264	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
<>	128:9bcdf88f62b0	265	* @{
<>	128:9bcdf88f62b0	266	*/
<>	128:9bcdf88f62b0	267
<>	128:9bcdf88f62b0	268	/**
<>	128:9bcdf88f62b0	269	* @brief Convert Peripheral Clock Frequency in Mhz.
<>	128:9bcdf88f62b0	270	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	128:9bcdf88f62b0	271	* @retval Value of peripheral clock (in Mhz)
<>	128:9bcdf88f62b0	272	*/
<>	128:9bcdf88f62b0	273	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
<>	128:9bcdf88f62b0	274
<>	128:9bcdf88f62b0	275	/**
<>	128:9bcdf88f62b0	276	* @brief Convert Peripheral Clock Frequency in Hz.
<>	128:9bcdf88f62b0	277	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
<>	128:9bcdf88f62b0	278	* @retval Value of peripheral clock (in Hz)
<>	128:9bcdf88f62b0	279	*/
<>	128:9bcdf88f62b0	280	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
<>	128:9bcdf88f62b0	281
<>	128:9bcdf88f62b0	282	/**
<>	128:9bcdf88f62b0	283	* @brief Compute I2C Clock rising time.
<>	128:9bcdf88f62b0	284	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
<>	128:9bcdf88f62b0	285	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
<>	128:9bcdf88f62b0	286	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
<>	128:9bcdf88f62b0	287	*/
<>	128:9bcdf88f62b0	288	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
<>	128:9bcdf88f62b0	289
<>	128:9bcdf88f62b0	290	/**
<>	128:9bcdf88f62b0	291	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	128:9bcdf88f62b0	292	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	128:9bcdf88f62b0	293	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
<>	128:9bcdf88f62b0	294	* @param __DUTYCYCLE__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	295	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	128:9bcdf88f62b0	296	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	128:9bcdf88f62b0	297	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	128:9bcdf88f62b0	298	*/
<>	128:9bcdf88f62b0	299	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
<>	128:9bcdf88f62b0	300	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
<>	128:9bcdf88f62b0	301	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
<>	128:9bcdf88f62b0	302
<>	128:9bcdf88f62b0	303	/**
<>	128:9bcdf88f62b0	304	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	128:9bcdf88f62b0	305	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	128:9bcdf88f62b0	306	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
<>	128:9bcdf88f62b0	307	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
<>	128:9bcdf88f62b0	308	*/
<>	128:9bcdf88f62b0	309	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
<>	128:9bcdf88f62b0	310
<>	128:9bcdf88f62b0	311	/**
<>	128:9bcdf88f62b0	312	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	128:9bcdf88f62b0	313	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	128:9bcdf88f62b0	314	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
<>	128:9bcdf88f62b0	315	* @param __DUTYCYCLE__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	316	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	128:9bcdf88f62b0	317	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	128:9bcdf88f62b0	318	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	319	*/
<>	128:9bcdf88f62b0	320	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
<>	128:9bcdf88f62b0	321	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
<>	128:9bcdf88f62b0	322	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
<>	128:9bcdf88f62b0	323
<>	128:9bcdf88f62b0	324	/**
<>	128:9bcdf88f62b0	325	* @brief Get the Least significant bits of a 10-Bits address.
<>	128:9bcdf88f62b0	326	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	128:9bcdf88f62b0	327	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	328	*/
<>	128:9bcdf88f62b0	329	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
<>	128:9bcdf88f62b0	330
<>	128:9bcdf88f62b0	331	/**
<>	128:9bcdf88f62b0	332	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
<>	128:9bcdf88f62b0	333	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	128:9bcdf88f62b0	334	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
<>	128:9bcdf88f62b0	335	*/
<>	128:9bcdf88f62b0	336	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
<>	128:9bcdf88f62b0	337
<>	128:9bcdf88f62b0	338	/**
<>	128:9bcdf88f62b0	339	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
<>	128:9bcdf88f62b0	340	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	128:9bcdf88f62b0	341	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
<>	128:9bcdf88f62b0	342	*/
<>	128:9bcdf88f62b0	343	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
<>	128:9bcdf88f62b0	344
<>	128:9bcdf88f62b0	345	/**
<>	128:9bcdf88f62b0	346	* @}
<>	128:9bcdf88f62b0	347	*/
<>	128:9bcdf88f62b0	348
<>	128:9bcdf88f62b0	349	/**
<>	128:9bcdf88f62b0	350	* @}
<>	128:9bcdf88f62b0	351	*/
<>	128:9bcdf88f62b0	352
<>	128:9bcdf88f62b0	353	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	354
<>	128:9bcdf88f62b0	355	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	128:9bcdf88f62b0	356	* @{
<>	128:9bcdf88f62b0	357	*/
<>	128:9bcdf88f62b0	358
<>	128:9bcdf88f62b0	359	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	128:9bcdf88f62b0	360	* @{
<>	128:9bcdf88f62b0	361	*/
<>	128:9bcdf88f62b0	362
<>	128:9bcdf88f62b0	363	/**
<>	128:9bcdf88f62b0	364	* @brief Enable I2C peripheral (PE = 1).
<>	128:9bcdf88f62b0	365	* @rmtoll CR1 PE LL_I2C_Enable
<>	128:9bcdf88f62b0	366	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	367	* @retval None
<>	128:9bcdf88f62b0	368	*/
<>	128:9bcdf88f62b0	369	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	370	{
<>	128:9bcdf88f62b0	371	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	128:9bcdf88f62b0	372	}
<>	128:9bcdf88f62b0	373
<>	128:9bcdf88f62b0	374	/**
<>	128:9bcdf88f62b0	375	* @brief Disable I2C peripheral (PE = 0).
<>	128:9bcdf88f62b0	376	* @rmtoll CR1 PE LL_I2C_Disable
<>	128:9bcdf88f62b0	377	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	378	* @retval None
<>	128:9bcdf88f62b0	379	*/
<>	128:9bcdf88f62b0	380	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	381	{
<>	128:9bcdf88f62b0	382	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	128:9bcdf88f62b0	383	}
<>	128:9bcdf88f62b0	384
<>	128:9bcdf88f62b0	385	/**
<>	128:9bcdf88f62b0	386	* @brief Check if the I2C peripheral is enabled or disabled.
<>	128:9bcdf88f62b0	387	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	128:9bcdf88f62b0	388	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	389	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	390	*/
<>	128:9bcdf88f62b0	391	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	392	{
<>	128:9bcdf88f62b0	393	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	128:9bcdf88f62b0	394	}
<>	128:9bcdf88f62b0	395
<>	128:9bcdf88f62b0	396
<>	128:9bcdf88f62b0	397	/**
<>	128:9bcdf88f62b0	398	* @brief Enable DMA transmission requests.
<>	128:9bcdf88f62b0	399	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
<>	128:9bcdf88f62b0	400	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	401	* @retval None
<>	128:9bcdf88f62b0	402	*/
<>	128:9bcdf88f62b0	403	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	404	{
<>	128:9bcdf88f62b0	405	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	128:9bcdf88f62b0	406	}
<>	128:9bcdf88f62b0	407
<>	128:9bcdf88f62b0	408	/**
<>	128:9bcdf88f62b0	409	* @brief Disable DMA transmission requests.
<>	128:9bcdf88f62b0	410	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
<>	128:9bcdf88f62b0	411	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	412	* @retval None
<>	128:9bcdf88f62b0	413	*/
<>	128:9bcdf88f62b0	414	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	415	{
<>	128:9bcdf88f62b0	416	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	128:9bcdf88f62b0	417	}
<>	128:9bcdf88f62b0	418
<>	128:9bcdf88f62b0	419	/**
<>	128:9bcdf88f62b0	420	* @brief Check if DMA transmission requests are enabled or disabled.
<>	128:9bcdf88f62b0	421	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
<>	128:9bcdf88f62b0	422	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	423	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	424	*/
<>	128:9bcdf88f62b0	425	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	426	{
<>	128:9bcdf88f62b0	427	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
<>	128:9bcdf88f62b0	428	}
<>	128:9bcdf88f62b0	429
<>	128:9bcdf88f62b0	430	/**
<>	128:9bcdf88f62b0	431	* @brief Enable DMA reception requests.
<>	128:9bcdf88f62b0	432	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
<>	128:9bcdf88f62b0	433	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	434	* @retval None
<>	128:9bcdf88f62b0	435	*/
<>	128:9bcdf88f62b0	436	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	437	{
<>	128:9bcdf88f62b0	438	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	128:9bcdf88f62b0	439	}
<>	128:9bcdf88f62b0	440
<>	128:9bcdf88f62b0	441	/**
<>	128:9bcdf88f62b0	442	* @brief Disable DMA reception requests.
<>	128:9bcdf88f62b0	443	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
<>	128:9bcdf88f62b0	444	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	445	* @retval None
<>	128:9bcdf88f62b0	446	*/
<>	128:9bcdf88f62b0	447	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	448	{
<>	128:9bcdf88f62b0	449	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	128:9bcdf88f62b0	450	}
<>	128:9bcdf88f62b0	451
<>	128:9bcdf88f62b0	452	/**
<>	128:9bcdf88f62b0	453	* @brief Check if DMA reception requests are enabled or disabled.
<>	128:9bcdf88f62b0	454	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
<>	128:9bcdf88f62b0	455	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	456	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	457	*/
<>	128:9bcdf88f62b0	458	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	459	{
<>	128:9bcdf88f62b0	460	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
<>	128:9bcdf88f62b0	461	}
<>	128:9bcdf88f62b0	462
<>	128:9bcdf88f62b0	463	/**
<>	128:9bcdf88f62b0	464	* @brief Get the data register address used for DMA transfer.
<>	128:9bcdf88f62b0	465	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
<>	128:9bcdf88f62b0	466	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	467	* @retval Address of data register
<>	128:9bcdf88f62b0	468	*/
<>	128:9bcdf88f62b0	469	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	470	{
<>	128:9bcdf88f62b0	471	return (uint32_t) & (I2Cx->DR);
<>	128:9bcdf88f62b0	472	}
<>	128:9bcdf88f62b0	473
<>	128:9bcdf88f62b0	474	/**
<>	128:9bcdf88f62b0	475	* @brief Enable Clock stretching.
<>	128:9bcdf88f62b0	476	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	128:9bcdf88f62b0	477	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	128:9bcdf88f62b0	478	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	479	* @retval None
<>	128:9bcdf88f62b0	480	*/
<>	128:9bcdf88f62b0	481	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	482	{
<>	128:9bcdf88f62b0	483	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	128:9bcdf88f62b0	484	}
<>	128:9bcdf88f62b0	485
<>	128:9bcdf88f62b0	486	/**
<>	128:9bcdf88f62b0	487	* @brief Disable Clock stretching.
<>	128:9bcdf88f62b0	488	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	128:9bcdf88f62b0	489	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	128:9bcdf88f62b0	490	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	491	* @retval None
<>	128:9bcdf88f62b0	492	*/
<>	128:9bcdf88f62b0	493	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	494	{
<>	128:9bcdf88f62b0	495	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	128:9bcdf88f62b0	496	}
<>	128:9bcdf88f62b0	497
<>	128:9bcdf88f62b0	498	/**
<>	128:9bcdf88f62b0	499	* @brief Check if Clock stretching is enabled or disabled.
<>	128:9bcdf88f62b0	500	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	128:9bcdf88f62b0	501	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	502	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	503	*/
<>	128:9bcdf88f62b0	504	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	505	{
<>	128:9bcdf88f62b0	506	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	128:9bcdf88f62b0	507	}
<>	128:9bcdf88f62b0	508
<>	128:9bcdf88f62b0	509	/**
<>	128:9bcdf88f62b0	510	* @brief Enable General Call.
<>	128:9bcdf88f62b0	511	* @note When enabled the Address 0x00 is ACKed.
<>	128:9bcdf88f62b0	512	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
<>	128:9bcdf88f62b0	513	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	514	* @retval None
<>	128:9bcdf88f62b0	515	*/
<>	128:9bcdf88f62b0	516	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	517	{
<>	128:9bcdf88f62b0	518	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
<>	128:9bcdf88f62b0	519	}
<>	128:9bcdf88f62b0	520
<>	128:9bcdf88f62b0	521	/**
<>	128:9bcdf88f62b0	522	* @brief Disable General Call.
<>	128:9bcdf88f62b0	523	* @note When disabled the Address 0x00 is NACKed.
<>	128:9bcdf88f62b0	524	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
<>	128:9bcdf88f62b0	525	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	526	* @retval None
<>	128:9bcdf88f62b0	527	*/
<>	128:9bcdf88f62b0	528	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	529	{
<>	128:9bcdf88f62b0	530	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
<>	128:9bcdf88f62b0	531	}
<>	128:9bcdf88f62b0	532
<>	128:9bcdf88f62b0	533	/**
<>	128:9bcdf88f62b0	534	* @brief Check if General Call is enabled or disabled.
<>	128:9bcdf88f62b0	535	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
<>	128:9bcdf88f62b0	536	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	537	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	538	*/
<>	128:9bcdf88f62b0	539	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	540	{
<>	128:9bcdf88f62b0	541	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
<>	128:9bcdf88f62b0	542	}
<>	128:9bcdf88f62b0	543
<>	128:9bcdf88f62b0	544	/**
<>	128:9bcdf88f62b0	545	* @brief Set the Own Address1.
<>	128:9bcdf88f62b0	546	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
<>	128:9bcdf88f62b0	547	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
<>	128:9bcdf88f62b0	548	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
<>	128:9bcdf88f62b0	549	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
<>	128:9bcdf88f62b0	550	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	551	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	128:9bcdf88f62b0	552	* @param OwnAddrSize This parameter can be one of the following values:
<>	128:9bcdf88f62b0	553	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	128:9bcdf88f62b0	554	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	128:9bcdf88f62b0	555	* @retval None
<>	128:9bcdf88f62b0	556	*/
<>	128:9bcdf88f62b0	557	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	128:9bcdf88f62b0	558	{
<>	128:9bcdf88f62b0	559	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
<>	128:9bcdf88f62b0	560	}
<>	128:9bcdf88f62b0	561
<>	128:9bcdf88f62b0	562	/**
<>	128:9bcdf88f62b0	563	* @brief Set the 7bits Own Address2.
<>	128:9bcdf88f62b0	564	* @note This action has no effect if own address2 is enabled.
<>	128:9bcdf88f62b0	565	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
<>	128:9bcdf88f62b0	566	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	567	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
<>	128:9bcdf88f62b0	568	* @retval None
<>	128:9bcdf88f62b0	569	*/
<>	128:9bcdf88f62b0	570	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
<>	128:9bcdf88f62b0	571	{
<>	128:9bcdf88f62b0	572	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
<>	128:9bcdf88f62b0	573	}
<>	128:9bcdf88f62b0	574
<>	128:9bcdf88f62b0	575	/**
<>	128:9bcdf88f62b0	576	* @brief Enable acknowledge on Own Address2 match address.
<>	128:9bcdf88f62b0	577	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
<>	128:9bcdf88f62b0	578	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	579	* @retval None
<>	128:9bcdf88f62b0	580	*/
<>	128:9bcdf88f62b0	581	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	582	{
<>	128:9bcdf88f62b0	583	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
<>	128:9bcdf88f62b0	584	}
<>	128:9bcdf88f62b0	585
<>	128:9bcdf88f62b0	586	/**
<>	128:9bcdf88f62b0	587	* @brief Disable acknowledge on Own Address2 match address.
<>	128:9bcdf88f62b0	588	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
<>	128:9bcdf88f62b0	589	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	590	* @retval None
<>	128:9bcdf88f62b0	591	*/
<>	128:9bcdf88f62b0	592	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	593	{
<>	128:9bcdf88f62b0	594	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
<>	128:9bcdf88f62b0	595	}
<>	128:9bcdf88f62b0	596
<>	128:9bcdf88f62b0	597	/**
<>	128:9bcdf88f62b0	598	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	128:9bcdf88f62b0	599	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
<>	128:9bcdf88f62b0	600	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	601	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	602	*/
<>	128:9bcdf88f62b0	603	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	604	{
<>	128:9bcdf88f62b0	605	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
<>	128:9bcdf88f62b0	606	}
<>	128:9bcdf88f62b0	607
<>	128:9bcdf88f62b0	608	/**
<>	128:9bcdf88f62b0	609	* @brief Configure the Peripheral clock frequency.
<>	128:9bcdf88f62b0	610	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
<>	128:9bcdf88f62b0	611	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	612	* @param PeriphClock Peripheral Clock (in Hz)
<>	128:9bcdf88f62b0	613	* @retval None
<>	128:9bcdf88f62b0	614	*/
<>	128:9bcdf88f62b0	615	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
<>	128:9bcdf88f62b0	616	{
<>	128:9bcdf88f62b0	617	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
<>	128:9bcdf88f62b0	618	}
<>	128:9bcdf88f62b0	619
<>	128:9bcdf88f62b0	620	/**
<>	128:9bcdf88f62b0	621	* @brief Get the Peripheral clock frequency.
<>	128:9bcdf88f62b0	622	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
<>	128:9bcdf88f62b0	623	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	624	* @retval Value of Peripheral Clock (in Hz)
<>	128:9bcdf88f62b0	625	*/
<>	128:9bcdf88f62b0	626	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	627	{
<>	128:9bcdf88f62b0	628	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
<>	128:9bcdf88f62b0	629	}
<>	128:9bcdf88f62b0	630
<>	128:9bcdf88f62b0	631	/**
<>	128:9bcdf88f62b0	632	* @brief Configure the Duty cycle (Fast mode only).
<>	128:9bcdf88f62b0	633	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
<>	128:9bcdf88f62b0	634	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	635	* @param DutyCycle This parameter can be one of the following values:
<>	128:9bcdf88f62b0	636	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	128:9bcdf88f62b0	637	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	128:9bcdf88f62b0	638	* @retval None
<>	128:9bcdf88f62b0	639	*/
<>	128:9bcdf88f62b0	640	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
<>	128:9bcdf88f62b0	641	{
<>	128:9bcdf88f62b0	642	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
<>	128:9bcdf88f62b0	643	}
<>	128:9bcdf88f62b0	644
<>	128:9bcdf88f62b0	645	/**
<>	128:9bcdf88f62b0	646	* @brief Get the Duty cycle (Fast mode only).
<>	128:9bcdf88f62b0	647	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
<>	128:9bcdf88f62b0	648	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	649	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	650	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	128:9bcdf88f62b0	651	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	128:9bcdf88f62b0	652	*/
<>	128:9bcdf88f62b0	653	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	654	{
<>	128:9bcdf88f62b0	655	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
<>	128:9bcdf88f62b0	656	}
<>	128:9bcdf88f62b0	657
<>	128:9bcdf88f62b0	658	/**
<>	128:9bcdf88f62b0	659	* @brief Configure the I2C master clock speed mode.
<>	128:9bcdf88f62b0	660	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
<>	128:9bcdf88f62b0	661	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	662	* @param ClockSpeedMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	663	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
<>	128:9bcdf88f62b0	664	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
<>	128:9bcdf88f62b0	665	* @retval None
<>	128:9bcdf88f62b0	666	*/
<>	128:9bcdf88f62b0	667	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
<>	128:9bcdf88f62b0	668	{
<>	128:9bcdf88f62b0	669	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
<>	128:9bcdf88f62b0	670	}
<>	128:9bcdf88f62b0	671
<>	128:9bcdf88f62b0	672	/**
<>	128:9bcdf88f62b0	673	* @brief Get the the I2C master speed mode.
<>	128:9bcdf88f62b0	674	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
<>	128:9bcdf88f62b0	675	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	676	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	677	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
<>	128:9bcdf88f62b0	678	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
<>	128:9bcdf88f62b0	679	*/
<>	128:9bcdf88f62b0	680	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	681	{
<>	128:9bcdf88f62b0	682	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
<>	128:9bcdf88f62b0	683	}
<>	128:9bcdf88f62b0	684
<>	128:9bcdf88f62b0	685	/**
<>	128:9bcdf88f62b0	686	* @brief Configure the SCL, SDA rising time.
<>	128:9bcdf88f62b0	687	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	128:9bcdf88f62b0	688	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
<>	128:9bcdf88f62b0	689	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	690	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
<>	128:9bcdf88f62b0	691	* @retval None
<>	128:9bcdf88f62b0	692	*/
<>	128:9bcdf88f62b0	693	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
<>	128:9bcdf88f62b0	694	{
<>	128:9bcdf88f62b0	695	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
<>	128:9bcdf88f62b0	696	}
<>	128:9bcdf88f62b0	697
<>	128:9bcdf88f62b0	698	/**
<>	128:9bcdf88f62b0	699	* @brief Get the SCL, SDA rising time.
<>	128:9bcdf88f62b0	700	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
<>	128:9bcdf88f62b0	701	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	702	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
<>	128:9bcdf88f62b0	703	*/
<>	128:9bcdf88f62b0	704	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	705	{
<>	128:9bcdf88f62b0	706	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
<>	128:9bcdf88f62b0	707	}
<>	128:9bcdf88f62b0	708
<>	128:9bcdf88f62b0	709	/**
<>	128:9bcdf88f62b0	710	* @brief Configure the SCL high and low period.
<>	128:9bcdf88f62b0	711	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	128:9bcdf88f62b0	712	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
<>	128:9bcdf88f62b0	713	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	714	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	128:9bcdf88f62b0	715	* @retval None
<>	128:9bcdf88f62b0	716	*/
<>	128:9bcdf88f62b0	717	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
<>	128:9bcdf88f62b0	718	{
<>	128:9bcdf88f62b0	719	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
<>	128:9bcdf88f62b0	720	}
<>	128:9bcdf88f62b0	721
<>	128:9bcdf88f62b0	722	/**
<>	128:9bcdf88f62b0	723	* @brief Get the SCL high and low period.
<>	128:9bcdf88f62b0	724	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
<>	128:9bcdf88f62b0	725	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	726	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	128:9bcdf88f62b0	727	*/
<>	128:9bcdf88f62b0	728	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	729	{
<>	128:9bcdf88f62b0	730	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
<>	128:9bcdf88f62b0	731	}
<>	128:9bcdf88f62b0	732
<>	128:9bcdf88f62b0	733	/**
<>	128:9bcdf88f62b0	734	* @brief Configure the SCL speed.
<>	128:9bcdf88f62b0	735	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	128:9bcdf88f62b0	736	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
<>	128:9bcdf88f62b0	737	* TRISE TRISE LL_I2C_ConfigSpeed\n
<>	128:9bcdf88f62b0	738	* CCR FS LL_I2C_ConfigSpeed\n
<>	128:9bcdf88f62b0	739	* CCR DUTY LL_I2C_ConfigSpeed\n
<>	128:9bcdf88f62b0	740	* CCR CCR LL_I2C_ConfigSpeed
<>	128:9bcdf88f62b0	741	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	742	* @param PeriphClock Peripheral Clock (in Hz)
<>	128:9bcdf88f62b0	743	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
<>	128:9bcdf88f62b0	744	* @param DutyCycle This parameter can be one of the following values:
<>	128:9bcdf88f62b0	745	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	128:9bcdf88f62b0	746	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	128:9bcdf88f62b0	747	* @retval None
<>	128:9bcdf88f62b0	748	*/
<>	128:9bcdf88f62b0	749	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
<>	128:9bcdf88f62b0	750	uint32_t DutyCycle)
<>	128:9bcdf88f62b0	751	{
<>	128:9bcdf88f62b0	752	register uint32_t freqrange = 0x0U;
<>	128:9bcdf88f62b0	753	register uint32_t clockconfig = 0x0U;
<>	128:9bcdf88f62b0	754
<>	128:9bcdf88f62b0	755	/* Compute frequency range */
<>	128:9bcdf88f62b0	756	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
<>	128:9bcdf88f62b0	757
<>	128:9bcdf88f62b0	758	/* Configure I2Cx: Frequency range register */
<>	128:9bcdf88f62b0	759	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
<>	128:9bcdf88f62b0	760
<>	128:9bcdf88f62b0	761	/* Configure I2Cx: Rise Time register */
<>	128:9bcdf88f62b0	762	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
<>	128:9bcdf88f62b0	763
<>	128:9bcdf88f62b0	764	/* Configure Speed mode, Duty Cycle and Clock control register value */
<>	128:9bcdf88f62b0	765	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
<>	128:9bcdf88f62b0	766	{
<>	128:9bcdf88f62b0	767	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
<>	128:9bcdf88f62b0	768	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
<>	128:9bcdf88f62b0	769	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
<>	128:9bcdf88f62b0	770	DutyCycle;
<>	128:9bcdf88f62b0	771	}
<>	128:9bcdf88f62b0	772	else
<>	128:9bcdf88f62b0	773	{
<>	128:9bcdf88f62b0	774	/* Set Speed mode at standard for Clock Speed request in standard clock range */
<>	128:9bcdf88f62b0	775	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
<>	128:9bcdf88f62b0	776	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
<>	128:9bcdf88f62b0	777	}
<>	128:9bcdf88f62b0	778
<>	128:9bcdf88f62b0	779	/* Configure I2Cx: Clock control register */
<>	128:9bcdf88f62b0	780	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
<>	128:9bcdf88f62b0	781	}
<>	128:9bcdf88f62b0	782
<>	128:9bcdf88f62b0	783	/**
<>	128:9bcdf88f62b0	784	* @brief Configure peripheral mode.
<>	128:9bcdf88f62b0	785	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	786	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	787	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
<>	128:9bcdf88f62b0	788	* CR1 SMBTYPE LL_I2C_SetMode\n
<>	128:9bcdf88f62b0	789	* CR1 ENARP LL_I2C_SetMode
<>	128:9bcdf88f62b0	790	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	791	* @param PeripheralMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	792	* @arg @ref LL_I2C_MODE_I2C
<>	128:9bcdf88f62b0	793	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	128:9bcdf88f62b0	794	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	128:9bcdf88f62b0	795	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	128:9bcdf88f62b0	796	* @retval None
<>	128:9bcdf88f62b0	797	*/
<>	128:9bcdf88f62b0	798	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	128:9bcdf88f62b0	799	{
<>	128:9bcdf88f62b0	800	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
<>	128:9bcdf88f62b0	801	}
<>	128:9bcdf88f62b0	802
<>	128:9bcdf88f62b0	803	/**
<>	128:9bcdf88f62b0	804	* @brief Get peripheral mode.
<>	128:9bcdf88f62b0	805	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	806	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	807	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
<>	128:9bcdf88f62b0	808	* CR1 SMBTYPE LL_I2C_GetMode\n
<>	128:9bcdf88f62b0	809	* CR1 ENARP LL_I2C_GetMode
<>	128:9bcdf88f62b0	810	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	811	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	812	* @arg @ref LL_I2C_MODE_I2C
<>	128:9bcdf88f62b0	813	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	128:9bcdf88f62b0	814	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	128:9bcdf88f62b0	815	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	128:9bcdf88f62b0	816	*/
<>	128:9bcdf88f62b0	817	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	818	{
<>	128:9bcdf88f62b0	819	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
<>	128:9bcdf88f62b0	820	}
<>	128:9bcdf88f62b0	821
<>	128:9bcdf88f62b0	822	/**
<>	128:9bcdf88f62b0	823	* @brief Enable SMBus alert (Host or Device mode)
<>	128:9bcdf88f62b0	824	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	825	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	826	* @note SMBus Device mode:
<>	128:9bcdf88f62b0	827	* - SMBus Alert pin is drived low and
<>	128:9bcdf88f62b0	828	* Alert Response Address Header acknowledge is enabled.
<>	128:9bcdf88f62b0	829	* SMBus Host mode:
<>	128:9bcdf88f62b0	830	* - SMBus Alert pin management is supported.
<>	128:9bcdf88f62b0	831	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
<>	128:9bcdf88f62b0	832	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	833	* @retval None
<>	128:9bcdf88f62b0	834	*/
<>	128:9bcdf88f62b0	835	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	836	{
<>	128:9bcdf88f62b0	837	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
<>	128:9bcdf88f62b0	838	}
<>	128:9bcdf88f62b0	839
<>	128:9bcdf88f62b0	840	/**
<>	128:9bcdf88f62b0	841	* @brief Disable SMBus alert (Host or Device mode)
<>	128:9bcdf88f62b0	842	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	843	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	844	* @note SMBus Device mode:
<>	128:9bcdf88f62b0	845	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	128:9bcdf88f62b0	846	* Alert Response Address Header acknowledge is disabled.
<>	128:9bcdf88f62b0	847	* SMBus Host mode:
<>	128:9bcdf88f62b0	848	* - SMBus Alert pin management is not supported.
<>	128:9bcdf88f62b0	849	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
<>	128:9bcdf88f62b0	850	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	851	* @retval None
<>	128:9bcdf88f62b0	852	*/
<>	128:9bcdf88f62b0	853	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	854	{
<>	128:9bcdf88f62b0	855	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
<>	128:9bcdf88f62b0	856	}
<>	128:9bcdf88f62b0	857
<>	128:9bcdf88f62b0	858	/**
<>	128:9bcdf88f62b0	859	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	128:9bcdf88f62b0	860	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	861	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	862	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
<>	128:9bcdf88f62b0	863	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	864	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	865	*/
<>	128:9bcdf88f62b0	866	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	867	{
<>	128:9bcdf88f62b0	868	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
<>	128:9bcdf88f62b0	869	}
<>	128:9bcdf88f62b0	870
<>	128:9bcdf88f62b0	871	/**
<>	128:9bcdf88f62b0	872	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	128:9bcdf88f62b0	873	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	874	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	875	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
<>	128:9bcdf88f62b0	876	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	877	* @retval None
<>	128:9bcdf88f62b0	878	*/
<>	128:9bcdf88f62b0	879	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	880	{
<>	128:9bcdf88f62b0	881	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
<>	128:9bcdf88f62b0	882	}
<>	128:9bcdf88f62b0	883
<>	128:9bcdf88f62b0	884	/**
<>	128:9bcdf88f62b0	885	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	128:9bcdf88f62b0	886	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	887	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	888	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
<>	128:9bcdf88f62b0	889	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	890	* @retval None
<>	128:9bcdf88f62b0	891	*/
<>	128:9bcdf88f62b0	892	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	893	{
<>	128:9bcdf88f62b0	894	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
<>	128:9bcdf88f62b0	895	}
<>	128:9bcdf88f62b0	896
<>	128:9bcdf88f62b0	897	/**
<>	128:9bcdf88f62b0	898	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	128:9bcdf88f62b0	899	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	900	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	901	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
<>	128:9bcdf88f62b0	902	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	903	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	904	*/
<>	128:9bcdf88f62b0	905	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	906	{
<>	128:9bcdf88f62b0	907	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
<>	128:9bcdf88f62b0	908	}
<>	128:9bcdf88f62b0	909
<>	128:9bcdf88f62b0	910	/**
<>	128:9bcdf88f62b0	911	* @}
<>	128:9bcdf88f62b0	912	*/
<>	128:9bcdf88f62b0	913
<>	128:9bcdf88f62b0	914	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	128:9bcdf88f62b0	915	* @{
<>	128:9bcdf88f62b0	916	*/
<>	128:9bcdf88f62b0	917
<>	128:9bcdf88f62b0	918	/**
<>	128:9bcdf88f62b0	919	* @brief Enable TXE interrupt.
<>	128:9bcdf88f62b0	920	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
<>	128:9bcdf88f62b0	921	* CR2 ITBUFEN LL_I2C_EnableIT_TX
<>	128:9bcdf88f62b0	922	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	923	* @retval None
<>	128:9bcdf88f62b0	924	*/
<>	128:9bcdf88f62b0	925	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	926	{
<>	128:9bcdf88f62b0	927	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	928	}
<>	128:9bcdf88f62b0	929
<>	128:9bcdf88f62b0	930	/**
<>	128:9bcdf88f62b0	931	* @brief Disable TXE interrupt.
<>	128:9bcdf88f62b0	932	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
<>	128:9bcdf88f62b0	933	* CR2 ITBUFEN LL_I2C_DisableIT_TX
<>	128:9bcdf88f62b0	934	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	935	* @retval None
<>	128:9bcdf88f62b0	936	*/
<>	128:9bcdf88f62b0	937	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	938	{
<>	128:9bcdf88f62b0	939	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	940	}
<>	128:9bcdf88f62b0	941
<>	128:9bcdf88f62b0	942	/**
<>	128:9bcdf88f62b0	943	* @brief Check if the TXE Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	944	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
<>	128:9bcdf88f62b0	945	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
<>	128:9bcdf88f62b0	946	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	947	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	948	*/
<>	128:9bcdf88f62b0	949	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	950	{
<>	128:9bcdf88f62b0	951	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
<>	128:9bcdf88f62b0	952	}
<>	128:9bcdf88f62b0	953
<>	128:9bcdf88f62b0	954	/**
<>	128:9bcdf88f62b0	955	* @brief Enable RXNE interrupt.
<>	128:9bcdf88f62b0	956	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
<>	128:9bcdf88f62b0	957	* CR2 ITBUFEN LL_I2C_EnableIT_RX
<>	128:9bcdf88f62b0	958	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	959	* @retval None
<>	128:9bcdf88f62b0	960	*/
<>	128:9bcdf88f62b0	961	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	962	{
<>	128:9bcdf88f62b0	963	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	964	}
<>	128:9bcdf88f62b0	965
<>	128:9bcdf88f62b0	966	/**
<>	128:9bcdf88f62b0	967	* @brief Disable RXNE interrupt.
<>	128:9bcdf88f62b0	968	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
<>	128:9bcdf88f62b0	969	* CR2 ITBUFEN LL_I2C_DisableIT_RX
<>	128:9bcdf88f62b0	970	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	971	* @retval None
<>	128:9bcdf88f62b0	972	*/
<>	128:9bcdf88f62b0	973	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	974	{
<>	128:9bcdf88f62b0	975	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	976	}
<>	128:9bcdf88f62b0	977
<>	128:9bcdf88f62b0	978	/**
<>	128:9bcdf88f62b0	979	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	128:9bcdf88f62b0	980	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
<>	128:9bcdf88f62b0	981	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
<>	128:9bcdf88f62b0	982	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	983	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	984	*/
<>	128:9bcdf88f62b0	985	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	986	{
<>	128:9bcdf88f62b0	987	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
<>	128:9bcdf88f62b0	988	}
<>	128:9bcdf88f62b0	989
<>	128:9bcdf88f62b0	990	/**
<>	128:9bcdf88f62b0	991	* @brief Enable Events interrupts.
<>	128:9bcdf88f62b0	992	* @note Any of these events will generate interrupt :
<>	128:9bcdf88f62b0	993	* Start Bit (SB)
<>	128:9bcdf88f62b0	994	* Address sent, Address matched (ADDR)
<>	128:9bcdf88f62b0	995	* 10-bit header sent (ADD10)
<>	128:9bcdf88f62b0	996	* Stop detection (STOPF)
<>	128:9bcdf88f62b0	997	* Byte transfer finished (BTF)
<>	128:9bcdf88f62b0	998	*
<>	128:9bcdf88f62b0	999	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
<>	128:9bcdf88f62b0	1000	* Receive buffer not empty (RXNE)
<>	128:9bcdf88f62b0	1001	* Transmit buffer empty (TXE)
<>	128:9bcdf88f62b0	1002	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
<>	128:9bcdf88f62b0	1003	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1004	* @retval None
<>	128:9bcdf88f62b0	1005	*/
<>	128:9bcdf88f62b0	1006	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1007	{
<>	128:9bcdf88f62b0	1008	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
<>	128:9bcdf88f62b0	1009	}
<>	128:9bcdf88f62b0	1010
<>	128:9bcdf88f62b0	1011	/**
<>	128:9bcdf88f62b0	1012	* @brief Disable Events interrupts.
<>	128:9bcdf88f62b0	1013	* @note Any of these events will generate interrupt :
<>	128:9bcdf88f62b0	1014	* Start Bit (SB)
<>	128:9bcdf88f62b0	1015	* Address sent, Address matched (ADDR)
<>	128:9bcdf88f62b0	1016	* 10-bit header sent (ADD10)
<>	128:9bcdf88f62b0	1017	* Stop detection (STOPF)
<>	128:9bcdf88f62b0	1018	* Byte transfer finished (BTF)
<>	128:9bcdf88f62b0	1019	* Receive buffer not empty (RXNE)
<>	128:9bcdf88f62b0	1020	* Transmit buffer empty (TXE)
<>	128:9bcdf88f62b0	1021	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
<>	128:9bcdf88f62b0	1022	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1023	* @retval None
<>	128:9bcdf88f62b0	1024	*/
<>	128:9bcdf88f62b0	1025	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1026	{
<>	128:9bcdf88f62b0	1027	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
<>	128:9bcdf88f62b0	1028	}
<>	128:9bcdf88f62b0	1029
<>	128:9bcdf88f62b0	1030	/**
<>	128:9bcdf88f62b0	1031	* @brief Check if Events interrupts are enabled or disabled.
<>	128:9bcdf88f62b0	1032	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
<>	128:9bcdf88f62b0	1033	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1034	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1035	*/
<>	128:9bcdf88f62b0	1036	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1037	{
<>	128:9bcdf88f62b0	1038	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
<>	128:9bcdf88f62b0	1039	}
<>	128:9bcdf88f62b0	1040
<>	128:9bcdf88f62b0	1041	/**
<>	128:9bcdf88f62b0	1042	* @brief Enable Buffer interrupts.
<>	128:9bcdf88f62b0	1043	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
<>	128:9bcdf88f62b0	1044	* Receive buffer not empty (RXNE)
<>	128:9bcdf88f62b0	1045	* Transmit buffer empty (TXE)
<>	128:9bcdf88f62b0	1046	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
<>	128:9bcdf88f62b0	1047	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1048	* @retval None
<>	128:9bcdf88f62b0	1049	*/
<>	128:9bcdf88f62b0	1050	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1051	{
<>	128:9bcdf88f62b0	1052	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	1053	}
<>	128:9bcdf88f62b0	1054
<>	128:9bcdf88f62b0	1055	/**
<>	128:9bcdf88f62b0	1056	* @brief Disable Buffer interrupts.
<>	128:9bcdf88f62b0	1057	* @note Any of these Buffer events will generate interrupt :
<>	128:9bcdf88f62b0	1058	* Receive buffer not empty (RXNE)
<>	128:9bcdf88f62b0	1059	* Transmit buffer empty (TXE)
<>	128:9bcdf88f62b0	1060	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
<>	128:9bcdf88f62b0	1061	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1062	* @retval None
<>	128:9bcdf88f62b0	1063	*/
<>	128:9bcdf88f62b0	1064	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1065	{
<>	128:9bcdf88f62b0	1066	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
<>	128:9bcdf88f62b0	1067	}
<>	128:9bcdf88f62b0	1068
<>	128:9bcdf88f62b0	1069	/**
<>	128:9bcdf88f62b0	1070	* @brief Check if Buffer interrupts are enabled or disabled.
<>	128:9bcdf88f62b0	1071	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
<>	128:9bcdf88f62b0	1072	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1073	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1074	*/
<>	128:9bcdf88f62b0	1075	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1076	{
<>	128:9bcdf88f62b0	1077	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
<>	128:9bcdf88f62b0	1078	}
<>	128:9bcdf88f62b0	1079
<>	128:9bcdf88f62b0	1080	/**
<>	128:9bcdf88f62b0	1081	* @brief Enable Error interrupts.
<>	128:9bcdf88f62b0	1082	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1083	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1084	* @note Any of these errors will generate interrupt :
<>	128:9bcdf88f62b0	1085	* Bus Error detection (BERR)
<>	128:9bcdf88f62b0	1086	* Arbitration Loss (ARLO)
<>	128:9bcdf88f62b0	1087	* Acknowledge Failure(AF)
<>	128:9bcdf88f62b0	1088	* Overrun/Underrun (OVR)
<>	128:9bcdf88f62b0	1089	* SMBus Timeout detection (TIMEOUT)
<>	128:9bcdf88f62b0	1090	* SMBus PEC error detection (PECERR)
<>	128:9bcdf88f62b0	1091	* SMBus Alert pin event detection (SMBALERT)
<>	128:9bcdf88f62b0	1092	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
<>	128:9bcdf88f62b0	1093	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1094	* @retval None
<>	128:9bcdf88f62b0	1095	*/
<>	128:9bcdf88f62b0	1096	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1097	{
<>	128:9bcdf88f62b0	1098	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
<>	128:9bcdf88f62b0	1099	}
<>	128:9bcdf88f62b0	1100
<>	128:9bcdf88f62b0	1101	/**
<>	128:9bcdf88f62b0	1102	* @brief Disable Error interrupts.
<>	128:9bcdf88f62b0	1103	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1104	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1105	* @note Any of these errors will generate interrupt :
<>	128:9bcdf88f62b0	1106	* Bus Error detection (BERR)
<>	128:9bcdf88f62b0	1107	* Arbitration Loss (ARLO)
<>	128:9bcdf88f62b0	1108	* Acknowledge Failure(AF)
<>	128:9bcdf88f62b0	1109	* Overrun/Underrun (OVR)
<>	128:9bcdf88f62b0	1110	* SMBus Timeout detection (TIMEOUT)
<>	128:9bcdf88f62b0	1111	* SMBus PEC error detection (PECERR)
<>	128:9bcdf88f62b0	1112	* SMBus Alert pin event detection (SMBALERT)
<>	128:9bcdf88f62b0	1113	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
<>	128:9bcdf88f62b0	1114	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1115	* @retval None
<>	128:9bcdf88f62b0	1116	*/
<>	128:9bcdf88f62b0	1117	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1118	{
<>	128:9bcdf88f62b0	1119	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
<>	128:9bcdf88f62b0	1120	}
<>	128:9bcdf88f62b0	1121
<>	128:9bcdf88f62b0	1122	/**
<>	128:9bcdf88f62b0	1123	* @brief Check if Error interrupts are enabled or disabled.
<>	128:9bcdf88f62b0	1124	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
<>	128:9bcdf88f62b0	1125	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1126	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1127	*/
<>	128:9bcdf88f62b0	1128	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1129	{
<>	128:9bcdf88f62b0	1130	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
<>	128:9bcdf88f62b0	1131	}
<>	128:9bcdf88f62b0	1132
<>	128:9bcdf88f62b0	1133	/**
<>	128:9bcdf88f62b0	1134	* @}
<>	128:9bcdf88f62b0	1135	*/
<>	128:9bcdf88f62b0	1136
<>	128:9bcdf88f62b0	1137	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	128:9bcdf88f62b0	1138	* @{
<>	128:9bcdf88f62b0	1139	*/
<>	128:9bcdf88f62b0	1140
<>	128:9bcdf88f62b0	1141	/**
<>	128:9bcdf88f62b0	1142	* @brief Indicate the status of Transmit data register empty flag.
<>	128:9bcdf88f62b0	1143	* @note RESET: When next data is written in Transmit data register.
<>	128:9bcdf88f62b0	1144	* SET: When Transmit data register is empty.
<>	128:9bcdf88f62b0	1145	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
<>	128:9bcdf88f62b0	1146	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1147	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1148	*/
<>	128:9bcdf88f62b0	1149	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1150	{
<>	128:9bcdf88f62b0	1151	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
<>	128:9bcdf88f62b0	1152	}
<>	128:9bcdf88f62b0	1153
<>	128:9bcdf88f62b0	1154	/**
<>	128:9bcdf88f62b0	1155	* @brief Indicate the status of Byte Transfer Finished flag.
<>	128:9bcdf88f62b0	1156	* RESET: When Data byte transfer not done.
<>	128:9bcdf88f62b0	1157	* SET: When Data byte transfer succeeded.
<>	128:9bcdf88f62b0	1158	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
<>	128:9bcdf88f62b0	1159	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1160	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1161	*/
<>	128:9bcdf88f62b0	1162	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1163	{
<>	128:9bcdf88f62b0	1164	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
<>	128:9bcdf88f62b0	1165	}
<>	128:9bcdf88f62b0	1166
<>	128:9bcdf88f62b0	1167	/**
<>	128:9bcdf88f62b0	1168	* @brief Indicate the status of Receive data register not empty flag.
<>	128:9bcdf88f62b0	1169	* @note RESET: When Receive data register is read.
<>	128:9bcdf88f62b0	1170	* SET: When the received data is copied in Receive data register.
<>	128:9bcdf88f62b0	1171	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
<>	128:9bcdf88f62b0	1172	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1173	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1174	*/
<>	128:9bcdf88f62b0	1175	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1176	{
<>	128:9bcdf88f62b0	1177	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
<>	128:9bcdf88f62b0	1178	}
<>	128:9bcdf88f62b0	1179
<>	128:9bcdf88f62b0	1180	/**
<>	128:9bcdf88f62b0	1181	* @brief Indicate the status of Start Bit (master mode).
<>	128:9bcdf88f62b0	1182	* @note RESET: When No Start condition.
<>	128:9bcdf88f62b0	1183	* SET: When Start condition is generated.
<>	128:9bcdf88f62b0	1184	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
<>	128:9bcdf88f62b0	1185	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1186	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1187	*/
<>	128:9bcdf88f62b0	1188	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1189	{
<>	128:9bcdf88f62b0	1190	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
<>	128:9bcdf88f62b0	1191	}
<>	128:9bcdf88f62b0	1192
<>	128:9bcdf88f62b0	1193	/**
<>	128:9bcdf88f62b0	1194	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
<>	128:9bcdf88f62b0	1195	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1196	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
<>	128:9bcdf88f62b0	1197	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
<>	128:9bcdf88f62b0	1198	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1199	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1200	*/
<>	128:9bcdf88f62b0	1201	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1202	{
<>	128:9bcdf88f62b0	1203	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
<>	128:9bcdf88f62b0	1204	}
<>	128:9bcdf88f62b0	1205
<>	128:9bcdf88f62b0	1206	/**
<>	128:9bcdf88f62b0	1207	* @brief Indicate the status of 10-bit header sent (master mode).
<>	128:9bcdf88f62b0	1208	* @note RESET: When no ADD10 event occured.
<>	128:9bcdf88f62b0	1209	* SET: When the master has sent the first address byte (header).
<>	128:9bcdf88f62b0	1210	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
<>	128:9bcdf88f62b0	1211	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1212	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1213	*/
<>	128:9bcdf88f62b0	1214	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1215	{
<>	128:9bcdf88f62b0	1216	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
<>	128:9bcdf88f62b0	1217	}
<>	128:9bcdf88f62b0	1218
<>	128:9bcdf88f62b0	1219	/**
<>	128:9bcdf88f62b0	1220	* @brief Indicate the status of Acknowledge failure flag.
<>	128:9bcdf88f62b0	1221	* @note RESET: No acknowledge failure.
<>	128:9bcdf88f62b0	1222	* SET: When an acknowledge failure is received after a byte transmission.
<>	128:9bcdf88f62b0	1223	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
<>	128:9bcdf88f62b0	1224	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1225	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1226	*/
<>	128:9bcdf88f62b0	1227	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1228	{
<>	128:9bcdf88f62b0	1229	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
<>	128:9bcdf88f62b0	1230	}
<>	128:9bcdf88f62b0	1231
<>	128:9bcdf88f62b0	1232	/**
<>	128:9bcdf88f62b0	1233	* @brief Indicate the status of Stop detection flag (slave mode).
<>	128:9bcdf88f62b0	1234	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1235	* SET: When a Stop condition is detected.
<>	128:9bcdf88f62b0	1236	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
<>	128:9bcdf88f62b0	1237	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1238	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1239	*/
<>	128:9bcdf88f62b0	1240	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1241	{
<>	128:9bcdf88f62b0	1242	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
<>	128:9bcdf88f62b0	1243	}
<>	128:9bcdf88f62b0	1244
<>	128:9bcdf88f62b0	1245	/**
<>	128:9bcdf88f62b0	1246	* @brief Indicate the status of Bus error flag.
<>	128:9bcdf88f62b0	1247	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1248	* SET: When a misplaced Start or Stop condition is detected.
<>	128:9bcdf88f62b0	1249	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
<>	128:9bcdf88f62b0	1250	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1251	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1252	*/
<>	128:9bcdf88f62b0	1253	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1254	{
<>	128:9bcdf88f62b0	1255	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
<>	128:9bcdf88f62b0	1256	}
<>	128:9bcdf88f62b0	1257
<>	128:9bcdf88f62b0	1258	/**
<>	128:9bcdf88f62b0	1259	* @brief Indicate the status of Arbitration lost flag.
<>	128:9bcdf88f62b0	1260	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1261	* SET: When arbitration lost.
<>	128:9bcdf88f62b0	1262	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
<>	128:9bcdf88f62b0	1263	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1264	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1265	*/
<>	128:9bcdf88f62b0	1266	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1267	{
<>	128:9bcdf88f62b0	1268	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
<>	128:9bcdf88f62b0	1269	}
<>	128:9bcdf88f62b0	1270
<>	128:9bcdf88f62b0	1271	/**
<>	128:9bcdf88f62b0	1272	* @brief Indicate the status of Overrun/Underrun flag.
<>	128:9bcdf88f62b0	1273	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1274	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	128:9bcdf88f62b0	1275	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
<>	128:9bcdf88f62b0	1276	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1277	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1278	*/
<>	128:9bcdf88f62b0	1279	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1280	{
<>	128:9bcdf88f62b0	1281	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
<>	128:9bcdf88f62b0	1282	}
<>	128:9bcdf88f62b0	1283
<>	128:9bcdf88f62b0	1284	/**
<>	128:9bcdf88f62b0	1285	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	128:9bcdf88f62b0	1286	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1287	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1288	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	128:9bcdf88f62b0	1289	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1290	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1291	*/
<>	128:9bcdf88f62b0	1292	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1293	{
<>	128:9bcdf88f62b0	1294	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
<>	128:9bcdf88f62b0	1295	}
<>	128:9bcdf88f62b0	1296
<>	128:9bcdf88f62b0	1297	/**
<>	128:9bcdf88f62b0	1298	* @brief Indicate the status of SMBus Timeout detection flag.
<>	128:9bcdf88f62b0	1299	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1300	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1301	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	128:9bcdf88f62b0	1302	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1303	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1304	*/
<>	128:9bcdf88f62b0	1305	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1306	{
<>	128:9bcdf88f62b0	1307	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
<>	128:9bcdf88f62b0	1308	}
<>	128:9bcdf88f62b0	1309
<>	128:9bcdf88f62b0	1310	/**
<>	128:9bcdf88f62b0	1311	* @brief Indicate the status of SMBus alert flag.
<>	128:9bcdf88f62b0	1312	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1313	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1314	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	128:9bcdf88f62b0	1315	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1316	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1317	*/
<>	128:9bcdf88f62b0	1318	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1319	{
<>	128:9bcdf88f62b0	1320	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
<>	128:9bcdf88f62b0	1321	}
<>	128:9bcdf88f62b0	1322
<>	128:9bcdf88f62b0	1323	/**
<>	128:9bcdf88f62b0	1324	* @brief Indicate the status of Bus Busy flag.
<>	128:9bcdf88f62b0	1325	* @note RESET: Clear default value.
<>	128:9bcdf88f62b0	1326	* SET: When a Start condition is detected.
<>	128:9bcdf88f62b0	1327	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
<>	128:9bcdf88f62b0	1328	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1329	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1330	*/
<>	128:9bcdf88f62b0	1331	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1332	{
<>	128:9bcdf88f62b0	1333	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
<>	128:9bcdf88f62b0	1334	}
<>	128:9bcdf88f62b0	1335
<>	128:9bcdf88f62b0	1336	/**
<>	128:9bcdf88f62b0	1337	* @brief Indicate the status of Dual flag.
<>	128:9bcdf88f62b0	1338	* @note RESET: Received address matched with OAR1.
<>	128:9bcdf88f62b0	1339	* SET: Received address matched with OAR2.
<>	128:9bcdf88f62b0	1340	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
<>	128:9bcdf88f62b0	1341	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1342	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1343	*/
<>	128:9bcdf88f62b0	1344	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1345	{
<>	128:9bcdf88f62b0	1346	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
<>	128:9bcdf88f62b0	1347	}
<>	128:9bcdf88f62b0	1348
<>	128:9bcdf88f62b0	1349	/**
<>	128:9bcdf88f62b0	1350	* @brief Indicate the status of SMBus Host address reception (Slave mode).
<>	128:9bcdf88f62b0	1351	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1352	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1353	* @note RESET: No SMBus Host address
<>	128:9bcdf88f62b0	1354	* SET: SMBus Host address received.
<>	128:9bcdf88f62b0	1355	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	128:9bcdf88f62b0	1356	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
<>	128:9bcdf88f62b0	1357	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1358	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1359	*/
<>	128:9bcdf88f62b0	1360	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1361	{
<>	128:9bcdf88f62b0	1362	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
<>	128:9bcdf88f62b0	1363	}
<>	128:9bcdf88f62b0	1364
<>	128:9bcdf88f62b0	1365	/**
<>	128:9bcdf88f62b0	1366	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
<>	128:9bcdf88f62b0	1367	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1368	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1369	* @note RESET: No SMBus Device default address
<>	128:9bcdf88f62b0	1370	* SET: SMBus Device default address received.
<>	128:9bcdf88f62b0	1371	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	128:9bcdf88f62b0	1372	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
<>	128:9bcdf88f62b0	1373	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1374	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1375	*/
<>	128:9bcdf88f62b0	1376	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1377	{
<>	128:9bcdf88f62b0	1378	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
<>	128:9bcdf88f62b0	1379	}
<>	128:9bcdf88f62b0	1380
<>	128:9bcdf88f62b0	1381	/**
<>	128:9bcdf88f62b0	1382	* @brief Indicate the status of General call address reception (Slave mode).
<>	128:9bcdf88f62b0	1383	* @note RESET: No Generall call address
<>	128:9bcdf88f62b0	1384	* SET: General call address received.
<>	128:9bcdf88f62b0	1385	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	128:9bcdf88f62b0	1386	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
<>	128:9bcdf88f62b0	1387	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1388	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1389	*/
<>	128:9bcdf88f62b0	1390	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1391	{
<>	128:9bcdf88f62b0	1392	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
<>	128:9bcdf88f62b0	1393	}
<>	128:9bcdf88f62b0	1394
<>	128:9bcdf88f62b0	1395	/**
<>	128:9bcdf88f62b0	1396	* @brief Indicate the status of Master/Slave flag.
<>	128:9bcdf88f62b0	1397	* @note RESET: Slave Mode.
<>	128:9bcdf88f62b0	1398	* SET: Master Mode.
<>	128:9bcdf88f62b0	1399	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
<>	128:9bcdf88f62b0	1400	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1401	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1402	*/
<>	128:9bcdf88f62b0	1403	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1404	{
<>	128:9bcdf88f62b0	1405	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
<>	128:9bcdf88f62b0	1406	}
<>	128:9bcdf88f62b0	1407
<>	128:9bcdf88f62b0	1408	/**
<>	128:9bcdf88f62b0	1409	* @brief Clear Address Matched flag.
<>	128:9bcdf88f62b0	1410	* @note Clearing this flag is done by a read access to the I2Cx_SR1
<>	128:9bcdf88f62b0	1411	* register followed by a read access to the I2Cx_SR2 register.
<>	128:9bcdf88f62b0	1412	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
<>	128:9bcdf88f62b0	1413	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1414	* @retval None
<>	128:9bcdf88f62b0	1415	*/
<>	128:9bcdf88f62b0	1416	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1417	{
<>	128:9bcdf88f62b0	1418	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1419	tmpreg = I2Cx->SR1;
<>	128:9bcdf88f62b0	1420	(void) tmpreg;
<>	128:9bcdf88f62b0	1421	tmpreg = I2Cx->SR2;
<>	128:9bcdf88f62b0	1422	(void) tmpreg;
<>	128:9bcdf88f62b0	1423	}
<>	128:9bcdf88f62b0	1424
<>	128:9bcdf88f62b0	1425	/**
<>	128:9bcdf88f62b0	1426	* @brief Clear Acknowledge failure flag.
<>	128:9bcdf88f62b0	1427	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
<>	128:9bcdf88f62b0	1428	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1429	* @retval None
<>	128:9bcdf88f62b0	1430	*/
<>	128:9bcdf88f62b0	1431	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1432	{
<>	128:9bcdf88f62b0	1433	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
<>	128:9bcdf88f62b0	1434	}
<>	128:9bcdf88f62b0	1435
<>	128:9bcdf88f62b0	1436	/**
<>	128:9bcdf88f62b0	1437	* @brief Clear Stop detection flag.
<>	128:9bcdf88f62b0	1438	* @note Clearing this flag is done by a read access to the I2Cx_SR1
<>	128:9bcdf88f62b0	1439	* register followed by a write access to I2Cx_CR1 register.
<>	128:9bcdf88f62b0	1440	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
<>	128:9bcdf88f62b0	1441	* CR1 PE LL_I2C_ClearFlag_STOP
<>	128:9bcdf88f62b0	1442	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1443	* @retval None
<>	128:9bcdf88f62b0	1444	*/
<>	128:9bcdf88f62b0	1445	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1446	{
<>	128:9bcdf88f62b0	1447	__IO uint32_t tmpreg;
<>	128:9bcdf88f62b0	1448	tmpreg = I2Cx->SR1;
<>	128:9bcdf88f62b0	1449	(void) tmpreg;
<>	128:9bcdf88f62b0	1450	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	128:9bcdf88f62b0	1451	}
<>	128:9bcdf88f62b0	1452
<>	128:9bcdf88f62b0	1453	/**
<>	128:9bcdf88f62b0	1454	* @brief Clear Bus error flag.
<>	128:9bcdf88f62b0	1455	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
<>	128:9bcdf88f62b0	1456	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1457	* @retval None
<>	128:9bcdf88f62b0	1458	*/
<>	128:9bcdf88f62b0	1459	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1460	{
<>	128:9bcdf88f62b0	1461	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
<>	128:9bcdf88f62b0	1462	}
<>	128:9bcdf88f62b0	1463
<>	128:9bcdf88f62b0	1464	/**
<>	128:9bcdf88f62b0	1465	* @brief Clear Arbitration lost flag.
<>	128:9bcdf88f62b0	1466	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
<>	128:9bcdf88f62b0	1467	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1468	* @retval None
<>	128:9bcdf88f62b0	1469	*/
<>	128:9bcdf88f62b0	1470	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1471	{
<>	128:9bcdf88f62b0	1472	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
<>	128:9bcdf88f62b0	1473	}
<>	128:9bcdf88f62b0	1474
<>	128:9bcdf88f62b0	1475	/**
<>	128:9bcdf88f62b0	1476	* @brief Clear Overrun/Underrun flag.
<>	128:9bcdf88f62b0	1477	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
<>	128:9bcdf88f62b0	1478	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1479	* @retval None
<>	128:9bcdf88f62b0	1480	*/
<>	128:9bcdf88f62b0	1481	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1482	{
<>	128:9bcdf88f62b0	1483	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
<>	128:9bcdf88f62b0	1484	}
<>	128:9bcdf88f62b0	1485
<>	128:9bcdf88f62b0	1486	/**
<>	128:9bcdf88f62b0	1487	* @brief Clear SMBus PEC error flag.
<>	128:9bcdf88f62b0	1488	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
<>	128:9bcdf88f62b0	1489	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1490	* @retval None
<>	128:9bcdf88f62b0	1491	*/
<>	128:9bcdf88f62b0	1492	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1493	{
<>	128:9bcdf88f62b0	1494	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
<>	128:9bcdf88f62b0	1495	}
<>	128:9bcdf88f62b0	1496
<>	128:9bcdf88f62b0	1497	/**
<>	128:9bcdf88f62b0	1498	* @brief Clear SMBus Timeout detection flag.
<>	128:9bcdf88f62b0	1499	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1500	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1501	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
<>	128:9bcdf88f62b0	1502	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1503	* @retval None
<>	128:9bcdf88f62b0	1504	*/
<>	128:9bcdf88f62b0	1505	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1506	{
<>	128:9bcdf88f62b0	1507	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
<>	128:9bcdf88f62b0	1508	}
<>	128:9bcdf88f62b0	1509
<>	128:9bcdf88f62b0	1510	/**
<>	128:9bcdf88f62b0	1511	* @brief Clear SMBus Alert flag.
<>	128:9bcdf88f62b0	1512	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1513	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1514	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
<>	128:9bcdf88f62b0	1515	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1516	* @retval None
<>	128:9bcdf88f62b0	1517	*/
<>	128:9bcdf88f62b0	1518	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1519	{
<>	128:9bcdf88f62b0	1520	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
<>	128:9bcdf88f62b0	1521	}
<>	128:9bcdf88f62b0	1522
<>	128:9bcdf88f62b0	1523	/**
<>	128:9bcdf88f62b0	1524	* @}
<>	128:9bcdf88f62b0	1525	*/
<>	128:9bcdf88f62b0	1526
<>	128:9bcdf88f62b0	1527	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	128:9bcdf88f62b0	1528	* @{
<>	128:9bcdf88f62b0	1529	*/
<>	128:9bcdf88f62b0	1530
<>	128:9bcdf88f62b0	1531	/**
<>	128:9bcdf88f62b0	1532	* @brief Enable Reset of I2C peripheral.
<>	128:9bcdf88f62b0	1533	* @rmtoll CR1 SWRST LL_I2C_EnableReset
<>	128:9bcdf88f62b0	1534	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1535	* @retval None
<>	128:9bcdf88f62b0	1536	*/
<>	128:9bcdf88f62b0	1537	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1538	{
<>	128:9bcdf88f62b0	1539	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
<>	128:9bcdf88f62b0	1540	}
<>	128:9bcdf88f62b0	1541
<>	128:9bcdf88f62b0	1542	/**
<>	128:9bcdf88f62b0	1543	* @brief Check if the I2C peripheral is under reset state or not.
<>	128:9bcdf88f62b0	1544	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
<>	128:9bcdf88f62b0	1545	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1546	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1547	*/
<>	128:9bcdf88f62b0	1548	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1549	{
<>	128:9bcdf88f62b0	1550	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
<>	128:9bcdf88f62b0	1551	}
<>	128:9bcdf88f62b0	1552
<>	128:9bcdf88f62b0	1553	/**
<>	128:9bcdf88f62b0	1554	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	128:9bcdf88f62b0	1555	* @note Usage in Slave or Master mode.
<>	128:9bcdf88f62b0	1556	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
<>	128:9bcdf88f62b0	1557	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1558	* @param TypeAcknowledge This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1559	* @arg @ref LL_I2C_ACK
<>	128:9bcdf88f62b0	1560	* @arg @ref LL_I2C_NACK
<>	128:9bcdf88f62b0	1561	* @retval None
<>	128:9bcdf88f62b0	1562	*/
<>	128:9bcdf88f62b0	1563	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	128:9bcdf88f62b0	1564	{
<>	128:9bcdf88f62b0	1565	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
<>	128:9bcdf88f62b0	1566	}
<>	128:9bcdf88f62b0	1567
<>	128:9bcdf88f62b0	1568	/**
<>	128:9bcdf88f62b0	1569	* @brief Generate a START or RESTART condition
<>	128:9bcdf88f62b0	1570	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	128:9bcdf88f62b0	1571	* This action has no effect when RELOAD is set.
<>	128:9bcdf88f62b0	1572	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
<>	128:9bcdf88f62b0	1573	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1574	* @retval None
<>	128:9bcdf88f62b0	1575	*/
<>	128:9bcdf88f62b0	1576	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1577	{
<>	128:9bcdf88f62b0	1578	SET_BIT(I2Cx->CR1, I2C_CR1_START);
<>	128:9bcdf88f62b0	1579	}
<>	128:9bcdf88f62b0	1580
<>	128:9bcdf88f62b0	1581	/**
<>	128:9bcdf88f62b0	1582	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	128:9bcdf88f62b0	1583	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
<>	128:9bcdf88f62b0	1584	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1585	* @retval None
<>	128:9bcdf88f62b0	1586	*/
<>	128:9bcdf88f62b0	1587	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1588	{
<>	128:9bcdf88f62b0	1589	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
<>	128:9bcdf88f62b0	1590	}
<>	128:9bcdf88f62b0	1591
<>	128:9bcdf88f62b0	1592	/**
<>	128:9bcdf88f62b0	1593	* @brief Enable bit POS (master/host mode).
<>	128:9bcdf88f62b0	1594	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
<>	128:9bcdf88f62b0	1595	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
<>	128:9bcdf88f62b0	1596	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1597	* @retval None
<>	128:9bcdf88f62b0	1598	*/
<>	128:9bcdf88f62b0	1599	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1600	{
<>	128:9bcdf88f62b0	1601	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
<>	128:9bcdf88f62b0	1602	}
<>	128:9bcdf88f62b0	1603
<>	128:9bcdf88f62b0	1604	/**
<>	128:9bcdf88f62b0	1605	* @brief Disable bit POS (master/host mode).
<>	128:9bcdf88f62b0	1606	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
<>	128:9bcdf88f62b0	1607	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
<>	128:9bcdf88f62b0	1608	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1609	* @retval None
<>	128:9bcdf88f62b0	1610	*/
<>	128:9bcdf88f62b0	1611	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1612	{
<>	128:9bcdf88f62b0	1613	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
<>	128:9bcdf88f62b0	1614	}
<>	128:9bcdf88f62b0	1615
<>	128:9bcdf88f62b0	1616	/**
<>	128:9bcdf88f62b0	1617	* @brief Check if bit POS is enabled or disabled.
<>	128:9bcdf88f62b0	1618	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
<>	128:9bcdf88f62b0	1619	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1620	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1621	*/
<>	128:9bcdf88f62b0	1622	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1623	{
<>	128:9bcdf88f62b0	1624	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
<>	128:9bcdf88f62b0	1625	}
<>	128:9bcdf88f62b0	1626
<>	128:9bcdf88f62b0	1627	/**
<>	128:9bcdf88f62b0	1628	* @brief Indicate the value of transfer direction.
<>	128:9bcdf88f62b0	1629	* @note RESET: Bus is in read transfer (peripheral point of view).
<>	128:9bcdf88f62b0	1630	* SET: Bus is in write transfer (peripheral point of view).
<>	128:9bcdf88f62b0	1631	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
<>	128:9bcdf88f62b0	1632	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1633	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1634	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	128:9bcdf88f62b0	1635	* @arg @ref LL_I2C_DIRECTION_READ
<>	128:9bcdf88f62b0	1636	*/
<>	128:9bcdf88f62b0	1637	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1638	{
<>	128:9bcdf88f62b0	1639	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
<>	128:9bcdf88f62b0	1640	}
<>	128:9bcdf88f62b0	1641
<>	128:9bcdf88f62b0	1642	/**
<>	128:9bcdf88f62b0	1643	* @brief Enable DMA last transfer.
<>	128:9bcdf88f62b0	1644	* @note This action mean that next DMA EOT is the last transfer.
<>	128:9bcdf88f62b0	1645	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
<>	128:9bcdf88f62b0	1646	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1647	* @retval None
<>	128:9bcdf88f62b0	1648	*/
<>	128:9bcdf88f62b0	1649	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1650	{
<>	128:9bcdf88f62b0	1651	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
<>	128:9bcdf88f62b0	1652	}
<>	128:9bcdf88f62b0	1653
<>	128:9bcdf88f62b0	1654	/**
<>	128:9bcdf88f62b0	1655	* @brief Disable DMA last transfer.
<>	128:9bcdf88f62b0	1656	* @note This action mean that next DMA EOT is not the last transfer.
<>	128:9bcdf88f62b0	1657	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
<>	128:9bcdf88f62b0	1658	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1659	* @retval None
<>	128:9bcdf88f62b0	1660	*/
<>	128:9bcdf88f62b0	1661	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1662	{
<>	128:9bcdf88f62b0	1663	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
<>	128:9bcdf88f62b0	1664	}
<>	128:9bcdf88f62b0	1665
<>	128:9bcdf88f62b0	1666	/**
<>	128:9bcdf88f62b0	1667	* @brief Check if DMA last transfer is enabled or disabled.
<>	128:9bcdf88f62b0	1668	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
<>	128:9bcdf88f62b0	1669	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1670	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1671	*/
<>	128:9bcdf88f62b0	1672	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1673	{
<>	128:9bcdf88f62b0	1674	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
<>	128:9bcdf88f62b0	1675	}
<>	128:9bcdf88f62b0	1676
<>	128:9bcdf88f62b0	1677	/**
<>	128:9bcdf88f62b0	1678	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	128:9bcdf88f62b0	1679	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1680	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1681	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
<>	128:9bcdf88f62b0	1682	* or by a START or STOP condition, it is also cleared by software.
<>	128:9bcdf88f62b0	1683	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
<>	128:9bcdf88f62b0	1684	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1685	* @retval None
<>	128:9bcdf88f62b0	1686	*/
<>	128:9bcdf88f62b0	1687	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1688	{
<>	128:9bcdf88f62b0	1689	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
<>	128:9bcdf88f62b0	1690	}
<>	128:9bcdf88f62b0	1691
<>	128:9bcdf88f62b0	1692	/**
<>	128:9bcdf88f62b0	1693	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	128:9bcdf88f62b0	1694	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1695	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1696	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
<>	128:9bcdf88f62b0	1697	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1698	* @retval None
<>	128:9bcdf88f62b0	1699	*/
<>	128:9bcdf88f62b0	1700	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1701	{
<>	128:9bcdf88f62b0	1702	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
<>	128:9bcdf88f62b0	1703	}
<>	128:9bcdf88f62b0	1704
<>	128:9bcdf88f62b0	1705	/**
<>	128:9bcdf88f62b0	1706	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
<>	128:9bcdf88f62b0	1707	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1708	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1709	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
<>	128:9bcdf88f62b0	1710	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1711	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1712	*/
<>	128:9bcdf88f62b0	1713	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1714	{
<>	128:9bcdf88f62b0	1715	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
<>	128:9bcdf88f62b0	1716	}
<>	128:9bcdf88f62b0	1717
<>	128:9bcdf88f62b0	1718	/**
<>	128:9bcdf88f62b0	1719	* @brief Get the SMBus Packet Error byte calculated.
<>	128:9bcdf88f62b0	1720	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	128:9bcdf88f62b0	1721	* SMBus feature is supported by the I2Cx Instance.
<>	128:9bcdf88f62b0	1722	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
<>	128:9bcdf88f62b0	1723	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1724	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	1725	*/
<>	128:9bcdf88f62b0	1726	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1727	{
<>	128:9bcdf88f62b0	1728	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> LL_I2C_POSITION_SR2_PEC);
<>	128:9bcdf88f62b0	1729	}
<>	128:9bcdf88f62b0	1730
<>	128:9bcdf88f62b0	1731	/**
<>	128:9bcdf88f62b0	1732	* @brief Read Receive Data register.
<>	128:9bcdf88f62b0	1733	* @rmtoll DR DR LL_I2C_ReceiveData8
<>	128:9bcdf88f62b0	1734	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1735	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	128:9bcdf88f62b0	1736	*/
<>	128:9bcdf88f62b0	1737	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	128:9bcdf88f62b0	1738	{
<>	128:9bcdf88f62b0	1739	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
<>	128:9bcdf88f62b0	1740	}
<>	128:9bcdf88f62b0	1741
<>	128:9bcdf88f62b0	1742	/**
<>	128:9bcdf88f62b0	1743	* @brief Write in Transmit Data Register .
<>	128:9bcdf88f62b0	1744	* @rmtoll DR DR LL_I2C_TransmitData8
<>	128:9bcdf88f62b0	1745	* @param I2Cx I2C Instance.
<>	128:9bcdf88f62b0	1746	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
<>	128:9bcdf88f62b0	1747	* @retval None
<>	128:9bcdf88f62b0	1748	*/
<>	128:9bcdf88f62b0	1749	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	128:9bcdf88f62b0	1750	{
<>	128:9bcdf88f62b0	1751	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
<>	128:9bcdf88f62b0	1752	}
<>	128:9bcdf88f62b0	1753
<>	128:9bcdf88f62b0	1754	/**
<>	128:9bcdf88f62b0	1755	* @}
<>	128:9bcdf88f62b0	1756	*/
<>	128:9bcdf88f62b0	1757
<>	128:9bcdf88f62b0	1758	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	1759	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	128:9bcdf88f62b0	1760	* @{
<>	128:9bcdf88f62b0	1761	*/
<>	128:9bcdf88f62b0	1762
<>	128:9bcdf88f62b0	1763	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	128:9bcdf88f62b0	1764	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	128:9bcdf88f62b0	1765	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	128:9bcdf88f62b0	1766
<>	128:9bcdf88f62b0	1767
<>	128:9bcdf88f62b0	1768	/**
<>	128:9bcdf88f62b0	1769	* @}
<>	128:9bcdf88f62b0	1770	*/
<>	128:9bcdf88f62b0	1771	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	1772
<>	128:9bcdf88f62b0	1773	/**
<>	128:9bcdf88f62b0	1774	* @}
<>	128:9bcdf88f62b0	1775	*/
<>	128:9bcdf88f62b0	1776
<>	128:9bcdf88f62b0	1777	/**
<>	128:9bcdf88f62b0	1778	* @}
<>	128:9bcdf88f62b0	1779	*/
<>	128:9bcdf88f62b0	1780
<>	128:9bcdf88f62b0	1781	#endif /* I2C1 \|\| I2C2 */
<>	128:9bcdf88f62b0	1782
<>	128:9bcdf88f62b0	1783	/**
<>	128:9bcdf88f62b0	1784	* @}
<>	128:9bcdf88f62b0	1785	*/
<>	128:9bcdf88f62b0	1786
<>	128:9bcdf88f62b0	1787	#ifdef __cplusplus
<>	128:9bcdf88f62b0	1788	}
<>	128:9bcdf88f62b0	1789	#endif
<>	128:9bcdf88f62b0	1790
<>	128:9bcdf88f62b0	1791	#endif /* __STM32L1xx_LL_I2C_H */
<>	128:9bcdf88f62b0	1792
<>	128:9bcdf88f62b0	1793	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/