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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_adc.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of ADC LL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_ADC_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_ADC_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_LL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	#if defined (ADC1)
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @defgroup ADC_LL ADC
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Private types -------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/* Private variables ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	61
<>	128:9bcdf88f62b0	62	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	63	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
<>	128:9bcdf88f62b0	64	* @{
<>	128:9bcdf88f62b0	65	*/
<>	128:9bcdf88f62b0	66
<>	128:9bcdf88f62b0	67	/* Internal mask for ADC group regular sequencer: */
<>	128:9bcdf88f62b0	68	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
<>	128:9bcdf88f62b0	69	/* - sequencer register offset */
<>	128:9bcdf88f62b0	70	/* - sequencer rank bits position into the selected register */
<>	128:9bcdf88f62b0	71
<>	128:9bcdf88f62b0	72	/* Internal register offset for ADC group regular sequencer configuration */
<>	128:9bcdf88f62b0	73	/* (offset placed into a spare area of literal definition) */
<>	128:9bcdf88f62b0	74	#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	75	#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
<>	128:9bcdf88f62b0	76	#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
<>	128:9bcdf88f62b0	77	#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
<>	128:9bcdf88f62b0	78	#define ADC_SQR5_REGOFFSET ((uint32_t)0x00000400U)
<>	128:9bcdf88f62b0	79
<>	128:9bcdf88f62b0	80	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET \| ADC_SQR5_REGOFFSET)
<>	128:9bcdf88f62b0	81	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	128:9bcdf88f62b0	82
<>	128:9bcdf88f62b0	83	/* Definition of ADC group regular sequencer bits information to be inserted */
<>	128:9bcdf88f62b0	84	/* into ADC group regular sequencer ranks literals definition. */
<>	128:9bcdf88f62b0	85	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */
<>	128:9bcdf88f62b0	86	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */
<>	128:9bcdf88f62b0	87	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */
<>	128:9bcdf88f62b0	88	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */
<>	128:9bcdf88f62b0	89	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */
<>	128:9bcdf88f62b0	90	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */
<>	128:9bcdf88f62b0	91	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */
<>	128:9bcdf88f62b0	92	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */
<>	128:9bcdf88f62b0	93	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */
<>	128:9bcdf88f62b0	94	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */
<>	128:9bcdf88f62b0	95	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */
<>	128:9bcdf88f62b0	96	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */
<>	128:9bcdf88f62b0	97	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
<>	128:9bcdf88f62b0	98	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
<>	128:9bcdf88f62b0	99	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */
<>	128:9bcdf88f62b0	100	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */
<>	128:9bcdf88f62b0	101	#define ADC_REG_RANK_17_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */
<>	128:9bcdf88f62b0	102	#define ADC_REG_RANK_18_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */
<>	128:9bcdf88f62b0	103	#define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */
<>	128:9bcdf88f62b0	104	#define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */
<>	128:9bcdf88f62b0	105	#define ADC_REG_RANK_21_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */
<>	128:9bcdf88f62b0	106	#define ADC_REG_RANK_22_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */
<>	128:9bcdf88f62b0	107	#define ADC_REG_RANK_23_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */
<>	128:9bcdf88f62b0	108	#define ADC_REG_RANK_24_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */
<>	128:9bcdf88f62b0	109	#define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */
<>	128:9bcdf88f62b0	110	#define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */
<>	128:9bcdf88f62b0	111	#define ADC_REG_RANK_27_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */
<>	128:9bcdf88f62b0	112	#if defined(ADC_SQR1_SQ28)
<>	128:9bcdf88f62b0	113	#define ADC_REG_RANK_28_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */
<>	128:9bcdf88f62b0	114	#endif
<>	128:9bcdf88f62b0	115
<>	128:9bcdf88f62b0	116
<>	128:9bcdf88f62b0	117
<>	128:9bcdf88f62b0	118	/* Internal mask for ADC group injected sequencer: */
<>	128:9bcdf88f62b0	119	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
<>	128:9bcdf88f62b0	120	/* - data register offset */
<>	128:9bcdf88f62b0	121	/* - offset register offset */
<>	128:9bcdf88f62b0	122	/* - sequencer rank bits position into the selected register */
<>	128:9bcdf88f62b0	123
<>	128:9bcdf88f62b0	124	/* Internal register offset for ADC group injected data register */
<>	128:9bcdf88f62b0	125	/* (offset placed into a spare area of literal definition) */
<>	128:9bcdf88f62b0	126	#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	127	#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
<>	128:9bcdf88f62b0	128	#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
<>	128:9bcdf88f62b0	129	#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
<>	128:9bcdf88f62b0	130
<>	128:9bcdf88f62b0	131	/* Internal register offset for ADC group injected offset configuration */
<>	128:9bcdf88f62b0	132	/* (offset placed into a spare area of literal definition) */
<>	128:9bcdf88f62b0	133	#define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	134	#define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
<>	128:9bcdf88f62b0	135	#define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
<>	128:9bcdf88f62b0	136	#define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
<>	128:9bcdf88f62b0	137
<>	128:9bcdf88f62b0	138	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
<>	128:9bcdf88f62b0	139	#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_JOFR4_REGOFFSET)
<>	128:9bcdf88f62b0	140	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	128:9bcdf88f62b0	141
<>	128:9bcdf88f62b0	142	/* Definition of ADC group injected sequencer bits information to be inserted */
<>	128:9bcdf88f62b0	143	/* into ADC group injected sequencer ranks literals definition. */
<>	128:9bcdf88f62b0	144	#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
<>	128:9bcdf88f62b0	145	#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
<>	128:9bcdf88f62b0	146	#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
<>	128:9bcdf88f62b0	147	#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
<>	128:9bcdf88f62b0	148
<>	128:9bcdf88f62b0	149
<>	128:9bcdf88f62b0	150
<>	128:9bcdf88f62b0	151	/* Internal mask for ADC group regular trigger: */
<>	128:9bcdf88f62b0	152	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<>	128:9bcdf88f62b0	153	/* - regular trigger source */
<>	128:9bcdf88f62b0	154	/* - regular trigger edge */
<>	128:9bcdf88f62b0	155	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	128:9bcdf88f62b0	156
<>	128:9bcdf88f62b0	157	/* Mask containing trigger source masks for each of possible */
<>	128:9bcdf88f62b0	158	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	128:9bcdf88f62b0	159	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	128:9bcdf88f62b0	160	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) \| \
<>	128:9bcdf88f62b0	161	((ADC_CR2_EXTSEL) >> (4U * 1U)) \| \
<>	128:9bcdf88f62b0	162	((ADC_CR2_EXTSEL) >> (4U * 2U)) \| \
<>	128:9bcdf88f62b0	163	((ADC_CR2_EXTSEL) >> (4U * 3U)) )
<>	128:9bcdf88f62b0	164
<>	128:9bcdf88f62b0	165	/* Mask containing trigger edge masks for each of possible */
<>	128:9bcdf88f62b0	166	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	128:9bcdf88f62b0	167	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	128:9bcdf88f62b0	168	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) \| \
<>	128:9bcdf88f62b0	169	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	128:9bcdf88f62b0	170	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	128:9bcdf88f62b0	171	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	128:9bcdf88f62b0	172
<>	128:9bcdf88f62b0	173	/* Definition of ADC group regular trigger bits information. */
<>	128:9bcdf88f62b0	174	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
<>	128:9bcdf88f62b0	175	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
<>	128:9bcdf88f62b0	176
<>	128:9bcdf88f62b0	177
<>	128:9bcdf88f62b0	178
<>	128:9bcdf88f62b0	179	/* Internal mask for ADC group injected trigger: */
<>	128:9bcdf88f62b0	180	/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
<>	128:9bcdf88f62b0	181	/* - injected trigger source */
<>	128:9bcdf88f62b0	182	/* - injected trigger edge */
<>	128:9bcdf88f62b0	183	#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	128:9bcdf88f62b0	184
<>	128:9bcdf88f62b0	185	/* Mask containing trigger source masks for each of possible */
<>	128:9bcdf88f62b0	186	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	128:9bcdf88f62b0	187	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	128:9bcdf88f62b0	188	#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) \| \
<>	128:9bcdf88f62b0	189	((ADC_CR2_JEXTSEL) >> (4U * 1U)) \| \
<>	128:9bcdf88f62b0	190	((ADC_CR2_JEXTSEL) >> (4U * 2U)) \| \
<>	128:9bcdf88f62b0	191	((ADC_CR2_JEXTSEL) >> (4U * 3U)) )
<>	128:9bcdf88f62b0	192
<>	128:9bcdf88f62b0	193	/* Mask containing trigger edge masks for each of possible */
<>	128:9bcdf88f62b0	194	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	128:9bcdf88f62b0	195	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	128:9bcdf88f62b0	196	#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) \| \
<>	128:9bcdf88f62b0	197	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	128:9bcdf88f62b0	198	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	128:9bcdf88f62b0	199	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	128:9bcdf88f62b0	200
<>	128:9bcdf88f62b0	201	/* Definition of ADC group injected trigger bits information. */
<>	128:9bcdf88f62b0	202	#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
<>	128:9bcdf88f62b0	203	#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
<>	128:9bcdf88f62b0	204
<>	128:9bcdf88f62b0	205
<>	128:9bcdf88f62b0	206
<>	128:9bcdf88f62b0	207
<>	128:9bcdf88f62b0	208
<>	128:9bcdf88f62b0	209
<>	128:9bcdf88f62b0	210	/* Internal mask for ADC channel: */
<>	128:9bcdf88f62b0	211	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<>	128:9bcdf88f62b0	212	/* - channel identifier defined by number */
<>	128:9bcdf88f62b0	213	/* - channel differentiation between external channels (connected to */
<>	128:9bcdf88f62b0	214	/* GPIO pins) and internal channels (connected to internal paths) */
<>	128:9bcdf88f62b0	215	/* - channel sampling time defined by SMPRx register offset */
<>	128:9bcdf88f62b0	216	/* and SMPx bits positions into SMPRx register */
<>	128:9bcdf88f62b0	217	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
<>	128:9bcdf88f62b0	218	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<>	128:9bcdf88f62b0	219	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	128:9bcdf88f62b0	220	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<>	128:9bcdf88f62b0	221	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<>	128:9bcdf88f62b0	222
<>	128:9bcdf88f62b0	223	/* Channel differentiation between external and internal channels */
<>	128:9bcdf88f62b0	224	#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
<>	128:9bcdf88f62b0	225	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
<>	128:9bcdf88f62b0	226
<>	128:9bcdf88f62b0	227	/* Internal register offset for ADC channel sampling time configuration */
<>	128:9bcdf88f62b0	228	/* (offset placed into a spare area of literal definition) */
<>	128:9bcdf88f62b0	229	#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	230	#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
<>	128:9bcdf88f62b0	231	#define ADC_SMPR3_REGOFFSET ((uint32_t)0x04000000U)
<>	128:9bcdf88f62b0	232	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	233	#define ADC_SMPR0_REGOFFSET ((uint32_t)0x28000000U) /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
<>	128:9bcdf88f62b0	234	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET \| ADC_SMPR3_REGOFFSET \| ADC_SMPR0_REGOFFSET)
<>	128:9bcdf88f62b0	235	#else
<>	128:9bcdf88f62b0	236	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET \| ADC_SMPR3_REGOFFSET)
<>	128:9bcdf88f62b0	237	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	238
<>	128:9bcdf88f62b0	239	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
<>	128:9bcdf88f62b0	240	#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
<>	128:9bcdf88f62b0	241
<>	128:9bcdf88f62b0	242	/* Definition of channels ID number information to be inserted into */
<>	128:9bcdf88f62b0	243	/* channels literals definition. */
<>	128:9bcdf88f62b0	244	#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	245	#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	246	#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	247	#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	248	#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
<>	128:9bcdf88f62b0	249	#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	250	#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	251	#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	252	#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
<>	128:9bcdf88f62b0	253	#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	254	#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	255	#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	256	#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
<>	128:9bcdf88f62b0	257	#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	258	#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	259	#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	260	#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
<>	128:9bcdf88f62b0	261	#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	262	#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	263	#define ADC_CHANNEL_19_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	264	#define ADC_CHANNEL_20_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_2 )
<>	128:9bcdf88f62b0	265	#define ADC_CHANNEL_21_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	266	#define ADC_CHANNEL_22_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	267	#define ADC_CHANNEL_23_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	268	#define ADC_CHANNEL_24_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 )
<>	128:9bcdf88f62b0	269	#define ADC_CHANNEL_25_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	270	#define ADC_CHANNEL_26_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	271	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	272	#define ADC_CHANNEL_27_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	273	#define ADC_CHANNEL_28_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
<>	128:9bcdf88f62b0	274	#define ADC_CHANNEL_29_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	275	#define ADC_CHANNEL_30_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	128:9bcdf88f62b0	276	#define ADC_CHANNEL_31_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	128:9bcdf88f62b0	277	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	278
<>	128:9bcdf88f62b0	279	/* Definition of channels sampling time information to be inserted into */
<>	128:9bcdf88f62b0	280	/* channels literals definition. */
<>	128:9bcdf88f62b0	281	#define ADC_CHANNEL_0_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */
<>	128:9bcdf88f62b0	282	#define ADC_CHANNEL_1_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */
<>	128:9bcdf88f62b0	283	#define ADC_CHANNEL_2_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */
<>	128:9bcdf88f62b0	284	#define ADC_CHANNEL_3_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */
<>	128:9bcdf88f62b0	285	#define ADC_CHANNEL_4_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */
<>	128:9bcdf88f62b0	286	#define ADC_CHANNEL_5_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */
<>	128:9bcdf88f62b0	287	#define ADC_CHANNEL_6_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */
<>	128:9bcdf88f62b0	288	#define ADC_CHANNEL_7_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */
<>	128:9bcdf88f62b0	289	#define ADC_CHANNEL_8_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */
<>	128:9bcdf88f62b0	290	#define ADC_CHANNEL_9_SMP (ADC_SMPR3_REGOFFSET \| (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */
<>	128:9bcdf88f62b0	291	#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
<>	128:9bcdf88f62b0	292	#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
<>	128:9bcdf88f62b0	293	#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
<>	128:9bcdf88f62b0	294	#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
<>	128:9bcdf88f62b0	295	#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
<>	128:9bcdf88f62b0	296	#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
<>	128:9bcdf88f62b0	297	#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
<>	128:9bcdf88f62b0	298	#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
<>	128:9bcdf88f62b0	299	#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
<>	128:9bcdf88f62b0	300	#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */
<>	128:9bcdf88f62b0	301	#define ADC_CHANNEL_20_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */
<>	128:9bcdf88f62b0	302	#define ADC_CHANNEL_21_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */
<>	128:9bcdf88f62b0	303	#define ADC_CHANNEL_22_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */
<>	128:9bcdf88f62b0	304	#define ADC_CHANNEL_23_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */
<>	128:9bcdf88f62b0	305	#define ADC_CHANNEL_24_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */
<>	128:9bcdf88f62b0	306	#define ADC_CHANNEL_25_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */
<>	128:9bcdf88f62b0	307	#define ADC_CHANNEL_26_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */
<>	128:9bcdf88f62b0	308	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	309	#define ADC_CHANNEL_27_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */
<>	128:9bcdf88f62b0	310	#define ADC_CHANNEL_28_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */
<>	128:9bcdf88f62b0	311	#define ADC_CHANNEL_29_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */
<>	128:9bcdf88f62b0	312	#define ADC_CHANNEL_30_SMP (ADC_SMPR0_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */
<>	128:9bcdf88f62b0	313	#define ADC_CHANNEL_31_SMP (ADC_SMPR0_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */
<>	128:9bcdf88f62b0	314	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	315
<>	128:9bcdf88f62b0	316
<>	128:9bcdf88f62b0	317	/* Internal mask for ADC analog watchdog: */
<>	128:9bcdf88f62b0	318	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<>	128:9bcdf88f62b0	319	/* (concatenation of multiple bits used in different analog watchdogs, */
<>	128:9bcdf88f62b0	320	/* (feature of several watchdogs not available on all STM32 families)). */
<>	128:9bcdf88f62b0	321	/* - analog watchdog 1: monitored channel defined by number, */
<>	128:9bcdf88f62b0	322	/* selection of ADC group (ADC groups regular and-or injected). */
<>	128:9bcdf88f62b0	323
<>	128:9bcdf88f62b0	324	/* Internal register offset for ADC analog watchdog channel configuration */
<>	128:9bcdf88f62b0	325	#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	326
<>	128:9bcdf88f62b0	327	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
<>	128:9bcdf88f62b0	328
<>	128:9bcdf88f62b0	329	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
<>	128:9bcdf88f62b0	330	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
<>	128:9bcdf88f62b0	331
<>	128:9bcdf88f62b0	332	/* Internal register offset for ADC analog watchdog threshold configuration */
<>	128:9bcdf88f62b0	333	#define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
<>	128:9bcdf88f62b0	334	#define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
<>	128:9bcdf88f62b0	335	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET \| ADC_AWD_TR1_LOW_REGOFFSET)
<>	128:9bcdf88f62b0	336
<>	128:9bcdf88f62b0	337
<>	128:9bcdf88f62b0	338	/* ADC registers bits positions */
<>	128:9bcdf88f62b0	339	#define ADC_CR1_RES_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
<>	128:9bcdf88f62b0	340	#define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
<>	128:9bcdf88f62b0	341
<>	128:9bcdf88f62b0	342
<>	128:9bcdf88f62b0	343	/* ADC internal channels related definitions */
<>	128:9bcdf88f62b0	344	/* Internal voltage reference VrefInt */
<>	128:9bcdf88f62b0	345	#define VREFINT_CAL_ADDR ((uint16_t) ((uint32_t)0x1FF800F8U)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	128:9bcdf88f62b0	346	#define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<>	128:9bcdf88f62b0	347	/* Temperature sensor */
<>	128:9bcdf88f62b0	348	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) ((uint32_t)0x1FF800FAU)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	128:9bcdf88f62b0	349	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) ((uint32_t)0x1FF800FEU)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	128:9bcdf88f62b0	350	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	128:9bcdf88f62b0	351	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	128:9bcdf88f62b0	352	#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<>	128:9bcdf88f62b0	353
<>	128:9bcdf88f62b0	354
<>	128:9bcdf88f62b0	355	/**
<>	128:9bcdf88f62b0	356	* @}
<>	128:9bcdf88f62b0	357	*/
<>	128:9bcdf88f62b0	358
<>	128:9bcdf88f62b0	359
<>	128:9bcdf88f62b0	360	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	361	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
<>	128:9bcdf88f62b0	362	* @{
<>	128:9bcdf88f62b0	363	*/
<>	128:9bcdf88f62b0	364
<>	128:9bcdf88f62b0	365	/**
<>	128:9bcdf88f62b0	366	* @brief Driver macro reserved for internal use: isolate bits with the
<>	128:9bcdf88f62b0	367	* selected mask and shift them to the register LSB
<>	128:9bcdf88f62b0	368	* (shift mask on register position bit 0).
<>	128:9bcdf88f62b0	369	* @param __BITS__ Bits in register 32 bits
<>	128:9bcdf88f62b0	370	* @param __MASK__ Mask in register 32 bits
<>	128:9bcdf88f62b0	371	* @retval Bits in register 32 bits
<>	128:9bcdf88f62b0	372	*/
<>	128:9bcdf88f62b0	373	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
<>	128:9bcdf88f62b0	374	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<>	128:9bcdf88f62b0	375
<>	128:9bcdf88f62b0	376	/**
<>	128:9bcdf88f62b0	377	* @brief Driver macro reserved for internal use: set a pointer to
<>	128:9bcdf88f62b0	378	* a register from a register basis from which an offset
<>	128:9bcdf88f62b0	379	* is applied.
<>	128:9bcdf88f62b0	380	* @param __REG__ Register basis from which the offset is applied.
<>	128:9bcdf88f62b0	381	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	128:9bcdf88f62b0	382	* @retval Pointer to register address
<>	128:9bcdf88f62b0	383	*/
<>	128:9bcdf88f62b0	384	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	128:9bcdf88f62b0	385	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	128:9bcdf88f62b0	386
<>	128:9bcdf88f62b0	387	/**
<>	128:9bcdf88f62b0	388	* @}
<>	128:9bcdf88f62b0	389	*/
<>	128:9bcdf88f62b0	390
<>	128:9bcdf88f62b0	391
<>	128:9bcdf88f62b0	392	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	393	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	394	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<>	128:9bcdf88f62b0	395	* @{
<>	128:9bcdf88f62b0	396	*/
<>	128:9bcdf88f62b0	397
<>	128:9bcdf88f62b0	398	/**
<>	128:9bcdf88f62b0	399	* @brief Structure definition of some features of ADC common parameters
<>	128:9bcdf88f62b0	400	* and multimode
<>	128:9bcdf88f62b0	401	* (all ADC instances belonging to the same ADC common instance).
<>	128:9bcdf88f62b0	402	* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
<>	128:9bcdf88f62b0	403	* is conditioned to ADC instances state (all ADC instances
<>	128:9bcdf88f62b0	404	* sharing the same ADC common instance):
<>	128:9bcdf88f62b0	405	* All ADC instances sharing the same ADC common instance must be
<>	128:9bcdf88f62b0	406	* disabled.
<>	128:9bcdf88f62b0	407	*/
<>	128:9bcdf88f62b0	408	typedef struct
<>	128:9bcdf88f62b0	409	{
<>	128:9bcdf88f62b0	410	uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
<>	128:9bcdf88f62b0	411	This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
<>	128:9bcdf88f62b0	412	@note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
<>	128:9bcdf88f62b0	413	Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
<>	128:9bcdf88f62b0	414	@note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
<>	128:9bcdf88f62b0	415	must be respected:
<>	128:9bcdf88f62b0	416	- In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
<>	128:9bcdf88f62b0	417	- If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
<>	128:9bcdf88f62b0	418	Refer to reference manual.
<>	128:9bcdf88f62b0	419
<>	128:9bcdf88f62b0	420	This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
<>	128:9bcdf88f62b0	421
<>	128:9bcdf88f62b0	422	} LL_ADC_CommonInitTypeDef;
<>	128:9bcdf88f62b0	423
<>	128:9bcdf88f62b0	424	/**
<>	128:9bcdf88f62b0	425	* @brief Structure definition of some features of ADC instance.
<>	128:9bcdf88f62b0	426	* @note These parameters have an impact on ADC scope: ADC instance.
<>	128:9bcdf88f62b0	427	* Affects both group regular and group injected (availability
<>	128:9bcdf88f62b0	428	* of ADC group injected depends on STM32 families).
<>	128:9bcdf88f62b0	429	* Refer to corresponding unitary functions into
<>	128:9bcdf88f62b0	430	* @ref ADC_LL_EF_Configuration_ADC_Instance .
<>	128:9bcdf88f62b0	431	* @note The setting of these parameters by function @ref LL_ADC_Init()
<>	128:9bcdf88f62b0	432	* is conditioned to ADC state:
<>	128:9bcdf88f62b0	433	* ADC instance must be disabled.
<>	128:9bcdf88f62b0	434	* This condition is applied to all ADC features, for efficiency
<>	128:9bcdf88f62b0	435	* and compatibility over all STM32 families. However, the different
<>	128:9bcdf88f62b0	436	* features can be set under different ADC state conditions
<>	128:9bcdf88f62b0	437	* (setting possible with ADC enabled without conversion on going,
<>	128:9bcdf88f62b0	438	* ADC enabled with conversion on going, ...)
<>	128:9bcdf88f62b0	439	* Each feature can be updated afterwards with a unitary function
<>	128:9bcdf88f62b0	440	* and potentially with ADC in a different state than disabled,
<>	128:9bcdf88f62b0	441	* refer to description of each function for setting
<>	128:9bcdf88f62b0	442	* conditioned to ADC state.
<>	128:9bcdf88f62b0	443	*/
<>	128:9bcdf88f62b0	444	typedef struct
<>	128:9bcdf88f62b0	445	{
<>	128:9bcdf88f62b0	446	uint32_t Resolution; /*!< Set ADC resolution.
<>	128:9bcdf88f62b0	447	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<>	128:9bcdf88f62b0	448
<>	128:9bcdf88f62b0	449	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<>	128:9bcdf88f62b0	450
<>	128:9bcdf88f62b0	451	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<>	128:9bcdf88f62b0	452	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<>	128:9bcdf88f62b0	453
<>	128:9bcdf88f62b0	454	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<>	128:9bcdf88f62b0	455
<>	128:9bcdf88f62b0	456	uint32_t LowPowerMode; /*!< Set ADC low power mode.
<>	128:9bcdf88f62b0	457	This parameter can be a concatenation of a value of @ref ADC_LL_EC_LP_MODE_AUTOWAIT and a value of @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF
<>	128:9bcdf88f62b0	458
<>	128:9bcdf88f62b0	459	This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerModeAutoWait() and @ref LL_ADC_SetLowPowerModeAutoPowerOff(). */
<>	128:9bcdf88f62b0	460
<>	128:9bcdf88f62b0	461	uint32_t SequencersScanMode; /*!< Set ADC scan selection.
<>	128:9bcdf88f62b0	462	This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
<>	128:9bcdf88f62b0	463
<>	128:9bcdf88f62b0	464	This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
<>	128:9bcdf88f62b0	465
<>	128:9bcdf88f62b0	466	} LL_ADC_InitTypeDef;
<>	128:9bcdf88f62b0	467
<>	128:9bcdf88f62b0	468	/**
<>	128:9bcdf88f62b0	469	* @brief Structure definition of some features of ADC group regular.
<>	128:9bcdf88f62b0	470	* @note These parameters have an impact on ADC scope: ADC group regular.
<>	128:9bcdf88f62b0	471	* Refer to corresponding unitary functions into
<>	128:9bcdf88f62b0	472	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	128:9bcdf88f62b0	473	* (functions with prefix "REG").
<>	128:9bcdf88f62b0	474	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<>	128:9bcdf88f62b0	475	* is conditioned to ADC state:
<>	128:9bcdf88f62b0	476	* ADC instance must be disabled.
<>	128:9bcdf88f62b0	477	* This condition is applied to all ADC features, for efficiency
<>	128:9bcdf88f62b0	478	* and compatibility over all STM32 families. However, the different
<>	128:9bcdf88f62b0	479	* features can be set under different ADC state conditions
<>	128:9bcdf88f62b0	480	* (setting possible with ADC enabled without conversion on going,
<>	128:9bcdf88f62b0	481	* ADC enabled with conversion on going, ...)
<>	128:9bcdf88f62b0	482	* Each feature can be updated afterwards with a unitary function
<>	128:9bcdf88f62b0	483	* and potentially with ADC in a different state than disabled,
<>	128:9bcdf88f62b0	484	* refer to description of each function for setting
<>	128:9bcdf88f62b0	485	* conditioned to ADC state.
<>	128:9bcdf88f62b0	486	*/
<>	128:9bcdf88f62b0	487	typedef struct
<>	128:9bcdf88f62b0	488	{
<>	128:9bcdf88f62b0	489	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	128:9bcdf88f62b0	490	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<>	128:9bcdf88f62b0	491	@note On this STM32 serie, setting of external trigger edge is performed
<>	128:9bcdf88f62b0	492	using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	128:9bcdf88f62b0	493
<>	128:9bcdf88f62b0	494	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<>	128:9bcdf88f62b0	495
<>	128:9bcdf88f62b0	496	uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
<>	128:9bcdf88f62b0	497	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
<>	128:9bcdf88f62b0	498	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	128:9bcdf88f62b0	499
<>	128:9bcdf88f62b0	500	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
<>	128:9bcdf88f62b0	501
<>	128:9bcdf88f62b0	502	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	128:9bcdf88f62b0	503	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<>	128:9bcdf88f62b0	504	@note This parameter has an effect only if group regular sequencer is enabled
<>	128:9bcdf88f62b0	505	(scan length of 2 ranks or more).
<>	128:9bcdf88f62b0	506
<>	128:9bcdf88f62b0	507	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<>	128:9bcdf88f62b0	508
<>	128:9bcdf88f62b0	509	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<>	128:9bcdf88f62b0	510	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<>	128:9bcdf88f62b0	511	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<>	128:9bcdf88f62b0	512
<>	128:9bcdf88f62b0	513	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<>	128:9bcdf88f62b0	514
<>	128:9bcdf88f62b0	515	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<>	128:9bcdf88f62b0	516	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<>	128:9bcdf88f62b0	517
<>	128:9bcdf88f62b0	518	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<>	128:9bcdf88f62b0	519
<>	128:9bcdf88f62b0	520	} LL_ADC_REG_InitTypeDef;
<>	128:9bcdf88f62b0	521
<>	128:9bcdf88f62b0	522	/**
<>	128:9bcdf88f62b0	523	* @brief Structure definition of some features of ADC group injected.
<>	128:9bcdf88f62b0	524	* @note These parameters have an impact on ADC scope: ADC group injected.
<>	128:9bcdf88f62b0	525	* Refer to corresponding unitary functions into
<>	128:9bcdf88f62b0	526	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	128:9bcdf88f62b0	527	* (functions with prefix "INJ").
<>	128:9bcdf88f62b0	528	* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
<>	128:9bcdf88f62b0	529	* is conditioned to ADC state:
<>	128:9bcdf88f62b0	530	* ADC instance must be disabled.
<>	128:9bcdf88f62b0	531	* This condition is applied to all ADC features, for efficiency
<>	128:9bcdf88f62b0	532	* and compatibility over all STM32 families. However, the different
<>	128:9bcdf88f62b0	533	* features can be set under different ADC state conditions
<>	128:9bcdf88f62b0	534	* (setting possible with ADC enabled without conversion on going,
<>	128:9bcdf88f62b0	535	* ADC enabled with conversion on going, ...)
<>	128:9bcdf88f62b0	536	* Each feature can be updated afterwards with a unitary function
<>	128:9bcdf88f62b0	537	* and potentially with ADC in a different state than disabled,
<>	128:9bcdf88f62b0	538	* refer to description of each function for setting
<>	128:9bcdf88f62b0	539	* conditioned to ADC state.
<>	128:9bcdf88f62b0	540	*/
<>	128:9bcdf88f62b0	541	typedef struct
<>	128:9bcdf88f62b0	542	{
<>	128:9bcdf88f62b0	543	uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	128:9bcdf88f62b0	544	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
<>	128:9bcdf88f62b0	545	@note On this STM32 serie, setting of external trigger edge is performed
<>	128:9bcdf88f62b0	546	using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	128:9bcdf88f62b0	547
<>	128:9bcdf88f62b0	548	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
<>	128:9bcdf88f62b0	549
<>	128:9bcdf88f62b0	550	uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
<>	128:9bcdf88f62b0	551	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
<>	128:9bcdf88f62b0	552	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	128:9bcdf88f62b0	553
<>	128:9bcdf88f62b0	554	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
<>	128:9bcdf88f62b0	555
<>	128:9bcdf88f62b0	556	uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	128:9bcdf88f62b0	557	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
<>	128:9bcdf88f62b0	558	@note This parameter has an effect only if group injected sequencer is enabled
<>	128:9bcdf88f62b0	559	(scan length of 2 ranks or more).
<>	128:9bcdf88f62b0	560
<>	128:9bcdf88f62b0	561	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
<>	128:9bcdf88f62b0	562
<>	128:9bcdf88f62b0	563	uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
<>	128:9bcdf88f62b0	564	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
<>	128:9bcdf88f62b0	565	Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
<>	128:9bcdf88f62b0	566
<>	128:9bcdf88f62b0	567	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
<>	128:9bcdf88f62b0	568
<>	128:9bcdf88f62b0	569	} LL_ADC_INJ_InitTypeDef;
<>	128:9bcdf88f62b0	570
<>	128:9bcdf88f62b0	571	/**
<>	128:9bcdf88f62b0	572	* @}
<>	128:9bcdf88f62b0	573	*/
<>	128:9bcdf88f62b0	574	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	575
<>	128:9bcdf88f62b0	576	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	577	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<>	128:9bcdf88f62b0	578	* @{
<>	128:9bcdf88f62b0	579	*/
<>	128:9bcdf88f62b0	580
<>	128:9bcdf88f62b0	581	/** @defgroup ADC_LL_EC_FLAG ADC flags
<>	128:9bcdf88f62b0	582	* @brief Flags defines which can be used with LL_ADC_ReadReg function
<>	128:9bcdf88f62b0	583	* @{
<>	128:9bcdf88f62b0	584	*/
<>	128:9bcdf88f62b0	585	#define LL_ADC_FLAG_ADRDY ADC_SR_ADONS /!< ADC flag ADC instance ready /
<>	128:9bcdf88f62b0	586	#define LL_ADC_FLAG_STRT ADC_SR_STRT /!< ADC flag ADC group regular conversion start /
<>	128:9bcdf88f62b0	587	#define LL_ADC_FLAG_EOCS ADC_SR_EOC /!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	128:9bcdf88f62b0	588	#define LL_ADC_FLAG_OVR ADC_SR_OVR /!< ADC flag ADC group regular overrun /
<>	128:9bcdf88f62b0	589	#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC flag ADC group injected conversion start /
<>	128:9bcdf88f62b0	590	#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	128:9bcdf88f62b0	591	#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /!< ADC flag ADC analog watchdog 1 /
<>	128:9bcdf88f62b0	592	/**
<>	128:9bcdf88f62b0	593	* @}
<>	128:9bcdf88f62b0	594	*/
<>	128:9bcdf88f62b0	595
<>	128:9bcdf88f62b0	596	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<>	128:9bcdf88f62b0	597	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<>	128:9bcdf88f62b0	598	* @{
<>	128:9bcdf88f62b0	599	*/
<>	128:9bcdf88f62b0	600	#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	128:9bcdf88f62b0	601	#define LL_ADC_IT_OVR ADC_CR1_OVRIE /!< ADC interruption ADC group regular overrun /
<>	128:9bcdf88f62b0	602	#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	128:9bcdf88f62b0	603	#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /!< ADC interruption ADC analog watchdog 1 /
<>	128:9bcdf88f62b0	604	/**
<>	128:9bcdf88f62b0	605	* @}
<>	128:9bcdf88f62b0	606	*/
<>	128:9bcdf88f62b0	607
<>	128:9bcdf88f62b0	608	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<>	128:9bcdf88f62b0	609	* @{
<>	128:9bcdf88f62b0	610	*/
<>	128:9bcdf88f62b0	611	/* List of ADC registers intended to be used (most commonly) with */
<>	128:9bcdf88f62b0	612	/* DMA transfer. */
<>	128:9bcdf88f62b0	613	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<>	128:9bcdf88f62b0	614	#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<>	128:9bcdf88f62b0	615	/**
<>	128:9bcdf88f62b0	616	* @}
<>	128:9bcdf88f62b0	617	*/
<>	128:9bcdf88f62b0	618
<>	128:9bcdf88f62b0	619	/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
<>	128:9bcdf88f62b0	620	* @{
<>	128:9bcdf88f62b0	621	*/
<>	128:9bcdf88f62b0	622	#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /!< ADC asynchronous clock without prescaler /
<>	128:9bcdf88f62b0	623	#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_ADCPRE_0) /!< ADC asynchronous clock with prescaler division by 2 /
<>	128:9bcdf88f62b0	624	#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_ADCPRE_1) /!< ADC asynchronous clock with prescaler division by 4 /
<>	128:9bcdf88f62b0	625	/**
<>	128:9bcdf88f62b0	626	* @}
<>	128:9bcdf88f62b0	627	*/
<>	128:9bcdf88f62b0	628
<>	128:9bcdf88f62b0	629	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<>	128:9bcdf88f62b0	630	* @{
<>	128:9bcdf88f62b0	631	*/
<>	128:9bcdf88f62b0	632	/* Note: Other measurement paths to internal channels may be available */
<>	128:9bcdf88f62b0	633	/* (connections to other peripherals). */
<>	128:9bcdf88f62b0	634	/* If they are not listed below, they do not require any specific */
<>	128:9bcdf88f62b0	635	/* path enable. In this case, Access to measurement path is done */
<>	128:9bcdf88f62b0	636	/* only by selecting the corresponding ADC internal channel. */
<>	128:9bcdf88f62b0	637	#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/!< ADC measurement pathes all disabled /
<>	128:9bcdf88f62b0	638	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel VrefInt /
<>	128:9bcdf88f62b0	639	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel temperature sensor /
<>	128:9bcdf88f62b0	640	/**
<>	128:9bcdf88f62b0	641	* @}
<>	128:9bcdf88f62b0	642	*/
<>	128:9bcdf88f62b0	643
<>	128:9bcdf88f62b0	644	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<>	128:9bcdf88f62b0	645	* @{
<>	128:9bcdf88f62b0	646	*/
<>	128:9bcdf88f62b0	647	#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC resolution 12 bits /
<>	128:9bcdf88f62b0	648	#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /!< ADC resolution 10 bits /
<>	128:9bcdf88f62b0	649	#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /!< ADC resolution 8 bits /
<>	128:9bcdf88f62b0	650	#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 \| ADC_CR1_RES_0) /!< ADC resolution 6 bits /
<>	128:9bcdf88f62b0	651	/**
<>	128:9bcdf88f62b0	652	* @}
<>	128:9bcdf88f62b0	653	*/
<>	128:9bcdf88f62b0	654
<>	128:9bcdf88f62b0	655	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<>	128:9bcdf88f62b0	656	* @{
<>	128:9bcdf88f62b0	657	*/
<>	128:9bcdf88f62b0	658	#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
<>	128:9bcdf88f62b0	659	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
<>	128:9bcdf88f62b0	660	/**
<>	128:9bcdf88f62b0	661	* @}
<>	128:9bcdf88f62b0	662	*/
<>	128:9bcdf88f62b0	663
<>	128:9bcdf88f62b0	664	/** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT ADC instance - Low power mode auto wait (auto delay)
<>	128:9bcdf88f62b0	665	* @{
<>	128:9bcdf88f62b0	666	*/
<>	128:9bcdf88f62b0	667	#define LL_ADC_LP_AUTOWAIT_NONE ((uint32_t)0x00000000U) /!< ADC low power mode auto wait not activated /
<>	128:9bcdf88f62b0	668	#define LL_ADC_LP_AUTOWAIT ( ADC_CR2_DELS_0) /!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). /
<>	128:9bcdf88f62b0	669	#define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES ( ADC_CR2_DELS_1 ) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles /
<>	128:9bcdf88f62b0	670	#define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES ( ADC_CR2_DELS_1 \| ADC_CR2_DELS_0) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles /
<>	128:9bcdf88f62b0	671	#define LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES (ADC_CR2_DELS_2 ) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 31 APB clock cycles /
<>	128:9bcdf88f62b0	672	#define LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES (ADC_CR2_DELS_2 \| ADC_CR2_DELS_0) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 63 APB clock cycles /
<>	128:9bcdf88f62b0	673	#define LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES (ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 ) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 127 APB clock cycles /
<>	128:9bcdf88f62b0	674	#define LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES (ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 \| ADC_CR2_DELS_0) /!< ADC low power mode auto wait: Insert a delay between ADC conversions: 255 APB clock cycles /
<>	128:9bcdf88f62b0	675	/**
<>	128:9bcdf88f62b0	676	* @}
<>	128:9bcdf88f62b0	677	*/
<>	128:9bcdf88f62b0	678
<>	128:9bcdf88f62b0	679	/** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF ADC instance - Low power mode auto power-off
<>	128:9bcdf88f62b0	680	* @{
<>	128:9bcdf88f62b0	681	*/
<>	128:9bcdf88f62b0	682	#define LL_ADC_LP_AUTOPOWEROFF_NONE ((uint32_t)0x00000000U) /!< ADC low power mode auto power-off not activated /
<>	128:9bcdf88f62b0	683	#define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE (ADC_CR1_PDI) /!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) /
<>	128:9bcdf88f62b0	684	#define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE (ADC_CR1_PDD) /!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) /
<>	128:9bcdf88f62b0	685	#define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI \| ADC_CR1_PDD) /!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) /
<>	128:9bcdf88f62b0	686	/**
<>	128:9bcdf88f62b0	687	* @}
<>	128:9bcdf88f62b0	688	*/
<>	128:9bcdf88f62b0	689
<>	128:9bcdf88f62b0	690	/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
<>	128:9bcdf88f62b0	691	* @{
<>	128:9bcdf88f62b0	692	*/
<>	128:9bcdf88f62b0	693	#define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank./
<>	128:9bcdf88f62b0	694	#define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). /
<>	128:9bcdf88f62b0	695	/**
<>	128:9bcdf88f62b0	696	* @}
<>	128:9bcdf88f62b0	697	*/
<>	128:9bcdf88f62b0	698
<>	128:9bcdf88f62b0	699	#if defined(ADC_CR2_CFG)
<>	128:9bcdf88f62b0	700	/** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank
<>	128:9bcdf88f62b0	701	* @{
<>	128:9bcdf88f62b0	702	*/
<>	128:9bcdf88f62b0	703	#define LL_ADC_CHANNELS_BANK_A ((uint32_t)0x00000000U) /!< ADC channels bank A /
<>	128:9bcdf88f62b0	704	#define LL_ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) /!< ADC channels bank B, available in devices categories 3, 4, 5. /
<>	128:9bcdf88f62b0	705	/**
<>	128:9bcdf88f62b0	706	* @}
<>	128:9bcdf88f62b0	707	*/
<>	128:9bcdf88f62b0	708	#endif
<>	128:9bcdf88f62b0	709
<>	128:9bcdf88f62b0	710	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<>	128:9bcdf88f62b0	711	* @{
<>	128:9bcdf88f62b0	712	*/
<>	128:9bcdf88f62b0	713	#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /!< ADC group regular (available on all STM32 devices) /
<>	128:9bcdf88f62b0	714	#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /!< ADC group injected (not available on all STM32 devices)/
<>	128:9bcdf88f62b0	715	#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /!< ADC both groups regular and injected /
<>	128:9bcdf88f62b0	716	/**
<>	128:9bcdf88f62b0	717	* @}
<>	128:9bcdf88f62b0	718	*/
<>	128:9bcdf88f62b0	719
<>	128:9bcdf88f62b0	720	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<>	128:9bcdf88f62b0	721	* @{
<>	128:9bcdf88f62b0	722	*/
<>	128:9bcdf88f62b0	723	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	724	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	725	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	726	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	727	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 . Direct (fast) channel. /
<>	128:9bcdf88f62b0	728	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 . Direct (fast) channel. /
<>	128:9bcdf88f62b0	729	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	730	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	731	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	732	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 . Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	733	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10. Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	734	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11. Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	735	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12. Channel different in bank A and bank B. /
<>	128:9bcdf88f62b0	736	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	737	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	738	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	739	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	740	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	741	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	742	#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER \| ADC_CHANNEL_19_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN19. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	743	#define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER \| ADC_CHANNEL_20_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN20. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	744	#define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER \| ADC_CHANNEL_21_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN21. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	745	#define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER \| ADC_CHANNEL_22_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN22. Direct (fast) channel. /
<>	128:9bcdf88f62b0	746	#define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER \| ADC_CHANNEL_23_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN23. Direct (fast) channel. /
<>	128:9bcdf88f62b0	747	#define LL_ADC_CHANNEL_24 (ADC_CHANNEL_24_NUMBER \| ADC_CHANNEL_24_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN24. Direct (fast) channel. /
<>	128:9bcdf88f62b0	748	#define LL_ADC_CHANNEL_25 (ADC_CHANNEL_25_NUMBER \| ADC_CHANNEL_25_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN25. Direct (fast) channel. /
<>	128:9bcdf88f62b0	749	#define LL_ADC_CHANNEL_26 (ADC_CHANNEL_26_NUMBER \| ADC_CHANNEL_26_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN26. Direct (fast) channel. /
<>	128:9bcdf88f62b0	750	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	751	#define LL_ADC_CHANNEL_27 (ADC_CHANNEL_27_NUMBER \| ADC_CHANNEL_27_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN27. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	752	#define LL_ADC_CHANNEL_28 (ADC_CHANNEL_28_NUMBER \| ADC_CHANNEL_28_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN28. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	753	#define LL_ADC_CHANNEL_29 (ADC_CHANNEL_29_NUMBER \| ADC_CHANNEL_29_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN29. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	754	#define LL_ADC_CHANNEL_30 (ADC_CHANNEL_30_NUMBER \| ADC_CHANNEL_30_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN30. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	755	#define LL_ADC_CHANNEL_31 (ADC_CHANNEL_31_NUMBER \| ADC_CHANNEL_31_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN31. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	756	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	757	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	758	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	759	#define LL_ADC_CHANNEL_VCOMP (LL_ADC_CHANNEL_26 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	760	#if defined(OPAMP_CSR_OPA1PD) \|\| defined (OPAMP_CSR_OPA2PD) \|\| defined (OPAMP_CSR_OPA3PD)
<>	128:9bcdf88f62b0	761	#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_3 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	762	#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_8 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	763	#if defined(OPAMP_CSR_OPA3PD)
<>	128:9bcdf88f62b0	764	#define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_13 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	765	#endif /* OPAMP_CSR_OPA3PD */
<>	128:9bcdf88f62b0	766	#endif /* OPAMP_CSR_OPA1PD \|\| OPAMP_CSR_OPA2PD \|\| OPAMP_CSR_OPA3PD */
<>	128:9bcdf88f62b0	767	/**
<>	128:9bcdf88f62b0	768	* @}
<>	128:9bcdf88f62b0	769	*/
<>	128:9bcdf88f62b0	770
<>	128:9bcdf88f62b0	771	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<>	128:9bcdf88f62b0	772	* @{
<>	128:9bcdf88f62b0	773	*/
<>	128:9bcdf88f62b0	774	#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
<>	128:9bcdf88f62b0	775	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	776	#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	777	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	778	#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	779	#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	780	#define LL_ADC_REG_TRIG_EXT_TIM3_CH3 (ADC_CR2_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	781	#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	782	#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	783	#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	784	#define LL_ADC_REG_TRIG_EXT_TIM9_CH2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	785	#define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	786	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	787	/**
<>	128:9bcdf88f62b0	788	* @}
<>	128:9bcdf88f62b0	789	*/
<>	128:9bcdf88f62b0	790
<>	128:9bcdf88f62b0	791	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<>	128:9bcdf88f62b0	792	* @{
<>	128:9bcdf88f62b0	793	*/
<>	128:9bcdf88f62b0	794	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
<>	128:9bcdf88f62b0	795	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
<>	128:9bcdf88f62b0	796	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 \| ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
<>	128:9bcdf88f62b0	797	/**
<>	128:9bcdf88f62b0	798	* @}
<>	128:9bcdf88f62b0	799	*/
<>	128:9bcdf88f62b0	800
<>	128:9bcdf88f62b0	801	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<>	128:9bcdf88f62b0	802	* @{
<>	128:9bcdf88f62b0	803	*/
<>	128:9bcdf88f62b0	804	#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
<>	128:9bcdf88f62b0	805	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
<>	128:9bcdf88f62b0	806	/**
<>	128:9bcdf88f62b0	807	* @}
<>	128:9bcdf88f62b0	808	*/
<>	128:9bcdf88f62b0	809
<>	128:9bcdf88f62b0	810	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<>	128:9bcdf88f62b0	811	* @{
<>	128:9bcdf88f62b0	812	*/
<>	128:9bcdf88f62b0	813	#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /!< ADC conversions are not transferred by DMA /
<>	128:9bcdf88f62b0	814	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
<>	128:9bcdf88f62b0	815	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS \| ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
<>	128:9bcdf88f62b0	816	/**
<>	128:9bcdf88f62b0	817	* @}
<>	128:9bcdf88f62b0	818	*/
<>	128:9bcdf88f62b0	819
<>	128:9bcdf88f62b0	820	/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
<>	128:9bcdf88f62b0	821	* @{
<>	128:9bcdf88f62b0	822	*/
<>	128:9bcdf88f62b0	823	#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV ((uint32_t)0x00000000U) /!< ADC flag EOC (end of unitary conversion) selected /
<>	128:9bcdf88f62b0	824	#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV ((uint32_t)ADC_CR2_EOCS) /!< ADC flag EOS (end of sequence conversions) selected /
<>	128:9bcdf88f62b0	825	/**
<>	128:9bcdf88f62b0	826	* @}
<>	128:9bcdf88f62b0	827	*/
<>	128:9bcdf88f62b0	828
<>	128:9bcdf88f62b0	829	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
<>	128:9bcdf88f62b0	830	* @{
<>	128:9bcdf88f62b0	831	*/
<>	128:9bcdf88f62b0	832	#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	128:9bcdf88f62b0	833	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
<>	128:9bcdf88f62b0	834	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
<>	128:9bcdf88f62b0	835	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
<>	128:9bcdf88f62b0	836	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
<>	128:9bcdf88f62b0	837	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
<>	128:9bcdf88f62b0	838	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
<>	128:9bcdf88f62b0	839	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
<>	128:9bcdf88f62b0	840	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
<>	128:9bcdf88f62b0	841	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
<>	128:9bcdf88f62b0	842	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
<>	128:9bcdf88f62b0	843	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
<>	128:9bcdf88f62b0	844	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
<>	128:9bcdf88f62b0	845	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
<>	128:9bcdf88f62b0	846	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
<>	128:9bcdf88f62b0	847	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
<>	128:9bcdf88f62b0	848	/**
<>	128:9bcdf88f62b0	849	* @}
<>	128:9bcdf88f62b0	850	*/
<>	128:9bcdf88f62b0	851
<>	128:9bcdf88f62b0	852	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<>	128:9bcdf88f62b0	853	* @{
<>	128:9bcdf88f62b0	854	*/
<>	128:9bcdf88f62b0	855	#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
<>	128:9bcdf88f62b0	856	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
<>	128:9bcdf88f62b0	857	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
<>	128:9bcdf88f62b0	858	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
<>	128:9bcdf88f62b0	859	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
<>	128:9bcdf88f62b0	860	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
<>	128:9bcdf88f62b0	861	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
<>	128:9bcdf88f62b0	862	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
<>	128:9bcdf88f62b0	863	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
<>	128:9bcdf88f62b0	864	/**
<>	128:9bcdf88f62b0	865	* @}
<>	128:9bcdf88f62b0	866	*/
<>	128:9bcdf88f62b0	867
<>	128:9bcdf88f62b0	868	/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
<>	128:9bcdf88f62b0	869	* @{
<>	128:9bcdf88f62b0	870	*/
<>	128:9bcdf88f62b0	871	#define LL_ADC_REG_RANK_1 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
<>	128:9bcdf88f62b0	872	#define LL_ADC_REG_RANK_2 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
<>	128:9bcdf88f62b0	873	#define LL_ADC_REG_RANK_3 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
<>	128:9bcdf88f62b0	874	#define LL_ADC_REG_RANK_4 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
<>	128:9bcdf88f62b0	875	#define LL_ADC_REG_RANK_5 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
<>	128:9bcdf88f62b0	876	#define LL_ADC_REG_RANK_6 (ADC_SQR5_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
<>	128:9bcdf88f62b0	877	#define LL_ADC_REG_RANK_7 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
<>	128:9bcdf88f62b0	878	#define LL_ADC_REG_RANK_8 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
<>	128:9bcdf88f62b0	879	#define LL_ADC_REG_RANK_9 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
<>	128:9bcdf88f62b0	880	#define LL_ADC_REG_RANK_10 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
<>	128:9bcdf88f62b0	881	#define LL_ADC_REG_RANK_11 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
<>	128:9bcdf88f62b0	882	#define LL_ADC_REG_RANK_12 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
<>	128:9bcdf88f62b0	883	#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
<>	128:9bcdf88f62b0	884	#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
<>	128:9bcdf88f62b0	885	#define LL_ADC_REG_RANK_15 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
<>	128:9bcdf88f62b0	886	#define LL_ADC_REG_RANK_16 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
<>	128:9bcdf88f62b0	887	#define LL_ADC_REG_RANK_17 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_17_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 17 /
<>	128:9bcdf88f62b0	888	#define LL_ADC_REG_RANK_18 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_18_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 18 /
<>	128:9bcdf88f62b0	889	#define LL_ADC_REG_RANK_19 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_19_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 19 /
<>	128:9bcdf88f62b0	890	#define LL_ADC_REG_RANK_20 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_20_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 20 /
<>	128:9bcdf88f62b0	891	#define LL_ADC_REG_RANK_21 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_21_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 21 /
<>	128:9bcdf88f62b0	892	#define LL_ADC_REG_RANK_22 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_22_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 22 /
<>	128:9bcdf88f62b0	893	#define LL_ADC_REG_RANK_23 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_23_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 23 /
<>	128:9bcdf88f62b0	894	#define LL_ADC_REG_RANK_24 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_24_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 24 /
<>	128:9bcdf88f62b0	895	#define LL_ADC_REG_RANK_25 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_25_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 25 /
<>	128:9bcdf88f62b0	896	#define LL_ADC_REG_RANK_26 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_26_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 26 /
<>	128:9bcdf88f62b0	897	#define LL_ADC_REG_RANK_27 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_27_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 27 /
<>	128:9bcdf88f62b0	898	#if defined(ADC_SQR1_SQ28)
<>	128:9bcdf88f62b0	899	#define LL_ADC_REG_RANK_28 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_28_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 28 /
<>	128:9bcdf88f62b0	900	#endif
<>	128:9bcdf88f62b0	901	/**
<>	128:9bcdf88f62b0	902	* @}
<>	128:9bcdf88f62b0	903	*/
<>	128:9bcdf88f62b0	904
<>	128:9bcdf88f62b0	905	/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
<>	128:9bcdf88f62b0	906	* @{
<>	128:9bcdf88f62b0	907	*/
<>	128:9bcdf88f62b0	908	#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /!< ADC group injected conversion trigger internal: SW start. /
<>	128:9bcdf88f62b0	909	#define LL_ADC_INJ_TRIG_EXT_TIM9_CH1 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	910	#define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	911	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	912	#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	913	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	914	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	915	#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	916	#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	917	#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	918	#define LL_ADC_INJ_TRIG_EXT_TIM10_CH1 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	919	#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	920	#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). /
<>	128:9bcdf88f62b0	921	/**
<>	128:9bcdf88f62b0	922	* @}
<>	128:9bcdf88f62b0	923	*/
<>	128:9bcdf88f62b0	924
<>	128:9bcdf88f62b0	925	/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
<>	128:9bcdf88f62b0	926	* @{
<>	128:9bcdf88f62b0	927	*/
<>	128:9bcdf88f62b0	928	#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to rising edge /
<>	128:9bcdf88f62b0	929	#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /!< ADC group injected conversion trigger polarity set to falling edge /
<>	128:9bcdf88f62b0	930	#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 \| ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to both rising and falling edges /
<>	128:9bcdf88f62b0	931	/**
<>	128:9bcdf88f62b0	932	* @}
<>	128:9bcdf88f62b0	933	*/
<>	128:9bcdf88f62b0	934
<>	128:9bcdf88f62b0	935	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
<>	128:9bcdf88f62b0	936	* @{
<>	128:9bcdf88f62b0	937	*/
<>	128:9bcdf88f62b0	938	#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. /
<>	128:9bcdf88f62b0	939	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. /
<>	128:9bcdf88f62b0	940	/**
<>	128:9bcdf88f62b0	941	* @}
<>	128:9bcdf88f62b0	942	*/
<>	128:9bcdf88f62b0	943
<>	128:9bcdf88f62b0	944
<>	128:9bcdf88f62b0	945	/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
<>	128:9bcdf88f62b0	946	* @{
<>	128:9bcdf88f62b0	947	*/
<>	128:9bcdf88f62b0	948	#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	128:9bcdf88f62b0	949	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
<>	128:9bcdf88f62b0	950	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
<>	128:9bcdf88f62b0	951	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
<>	128:9bcdf88f62b0	952	/**
<>	128:9bcdf88f62b0	953	* @}
<>	128:9bcdf88f62b0	954	*/
<>	128:9bcdf88f62b0	955
<>	128:9bcdf88f62b0	956	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
<>	128:9bcdf88f62b0	957	* @{
<>	128:9bcdf88f62b0	958	*/
<>	128:9bcdf88f62b0	959	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/!< ADC group injected sequencer discontinuous mode disable /
<>	128:9bcdf88f62b0	960	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
<>	128:9bcdf88f62b0	961	/**
<>	128:9bcdf88f62b0	962	* @}
<>	128:9bcdf88f62b0	963	*/
<>	128:9bcdf88f62b0	964
<>	128:9bcdf88f62b0	965	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
<>	128:9bcdf88f62b0	966	* @{
<>	128:9bcdf88f62b0	967	*/
<>	128:9bcdf88f62b0	968	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_JOFR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 1 /
<>	128:9bcdf88f62b0	969	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 2 /
<>	128:9bcdf88f62b0	970	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 3 /
<>	128:9bcdf88f62b0	971	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_JOFR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 4 /
<>	128:9bcdf88f62b0	972	/**
<>	128:9bcdf88f62b0	973	* @}
<>	128:9bcdf88f62b0	974	*/
<>	128:9bcdf88f62b0	975
<>	128:9bcdf88f62b0	976	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<>	128:9bcdf88f62b0	977	* @{
<>	128:9bcdf88f62b0	978	*/
<>	128:9bcdf88f62b0	979	#define LL_ADC_SAMPLINGTIME_4CYCLES ((uint32_t)0x00000000U) /!< Sampling time 4 ADC clock cycles /
<>	128:9bcdf88f62b0	980	#define LL_ADC_SAMPLINGTIME_9CYCLES (ADC_SMPR3_SMP0_0) /!< Sampling time 9 ADC clock cycles /
<>	128:9bcdf88f62b0	981	#define LL_ADC_SAMPLINGTIME_16CYCLES (ADC_SMPR3_SMP0_1) /!< Sampling time 16 ADC clock cycles /
<>	128:9bcdf88f62b0	982	#define LL_ADC_SAMPLINGTIME_24CYCLES (ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0) /!< Sampling time 24 ADC clock cycles /
<>	128:9bcdf88f62b0	983	#define LL_ADC_SAMPLINGTIME_48CYCLES (ADC_SMPR3_SMP0_2) /!< Sampling time 48 ADC clock cycles /
<>	128:9bcdf88f62b0	984	#define LL_ADC_SAMPLINGTIME_96CYCLES (ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_0) /!< Sampling time 96 ADC clock cycles /
<>	128:9bcdf88f62b0	985	#define LL_ADC_SAMPLINGTIME_192CYCLES (ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1) /!< Sampling time 192 ADC clock cycles /
<>	128:9bcdf88f62b0	986	#define LL_ADC_SAMPLINGTIME_384CYCLES (ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0) /!< Sampling time 384 ADC clock cycles /
<>	128:9bcdf88f62b0	987	/**
<>	128:9bcdf88f62b0	988	* @}
<>	128:9bcdf88f62b0	989	*/
<>	128:9bcdf88f62b0	990
<>	128:9bcdf88f62b0	991	#if defined(COMP_CSR_FCH3)
<>	128:9bcdf88f62b0	992	/** @defgroup ADC_LL_EC_CHANNEL_ROUTING_LIST Channel - Routing channels list
<>	128:9bcdf88f62b0	993	* @{
<>	128:9bcdf88f62b0	994	*/
<>	128:9bcdf88f62b0	995	#define LL_ADC_CHANNEL_3_ROUTING (COMP_CSR_FCH3) /!< ADC channel 3 routing. Used as ADC direct channel (fast channel) if OPAMP1 is in power down mode. /
<>	128:9bcdf88f62b0	996	#define LL_ADC_CHANNEL_8_ROUTING (COMP_CSR_FCH8) /!< ADC channel 8 routing. Used as ADC direct channel (fast channel) if OPAMP2 is in power down mode. /
<>	128:9bcdf88f62b0	997	#define LL_ADC_CHANNEL_13_ROUTING (COMP_CSR_RCH13) /!< ADC channel 13 routing. Used as ADC re-routed channel if OPAMP3 is in power down mode. Otherwise, channel 13 is connected to OPAMP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is available on STM32L1 Cat.4 only). /
<>	128:9bcdf88f62b0	998	/**
<>	128:9bcdf88f62b0	999	* @}
<>	128:9bcdf88f62b0	1000	*/
<>	128:9bcdf88f62b0	1001
<>	128:9bcdf88f62b0	1002	/** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION Channel - Routing selection
<>	128:9bcdf88f62b0	1003	* @{
<>	128:9bcdf88f62b0	1004	*/
<>	128:9bcdf88f62b0	1005	#define LL_ADC_CHANNEL_ROUTING_DEFAULT ((uint32_t)0x00000000U) /!< ADC channel routing default: slow channel /
<>	128:9bcdf88f62b0	1006	#define LL_ADC_CHANNEL_ROUTING_DIRECT ((uint32_t)0x00000001U) /!< ADC channel routing direct: fast channel. /
<>	128:9bcdf88f62b0	1007	/**
<>	128:9bcdf88f62b0	1008	* @}
<>	128:9bcdf88f62b0	1009	*/
<>	128:9bcdf88f62b0	1010	#endif
<>	128:9bcdf88f62b0	1011
<>	128:9bcdf88f62b0	1012	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<>	128:9bcdf88f62b0	1013	* @{
<>	128:9bcdf88f62b0	1014	*/
<>	128:9bcdf88f62b0	1015	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
<>	128:9bcdf88f62b0	1016	/**
<>	128:9bcdf88f62b0	1017	* @}
<>	128:9bcdf88f62b0	1018	*/
<>	128:9bcdf88f62b0	1019
<>	128:9bcdf88f62b0	1020	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<>	128:9bcdf88f62b0	1021	* @{
<>	128:9bcdf88f62b0	1022	*/
<>	128:9bcdf88f62b0	1023	#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /!< ADC analog watchdog monitoring disabled /
<>	128:9bcdf88f62b0	1024	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
<>	128:9bcdf88f62b0	1025	#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
<>	128:9bcdf88f62b0	1026	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN \| ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1027	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
<>	128:9bcdf88f62b0	1028	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
<>	128:9bcdf88f62b0	1029	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1030	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
<>	128:9bcdf88f62b0	1031	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
<>	128:9bcdf88f62b0	1032	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1033	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
<>	128:9bcdf88f62b0	1034	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
<>	128:9bcdf88f62b0	1035	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1036	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
<>	128:9bcdf88f62b0	1037	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
<>	128:9bcdf88f62b0	1038	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1039	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
<>	128:9bcdf88f62b0	1040	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
<>	128:9bcdf88f62b0	1041	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1042	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
<>	128:9bcdf88f62b0	1043	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
<>	128:9bcdf88f62b0	1044	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1045	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
<>	128:9bcdf88f62b0	1046	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
<>	128:9bcdf88f62b0	1047	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1048	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
<>	128:9bcdf88f62b0	1049	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
<>	128:9bcdf88f62b0	1050	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1051	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
<>	128:9bcdf88f62b0	1052	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
<>	128:9bcdf88f62b0	1053	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1054	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
<>	128:9bcdf88f62b0	1055	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
<>	128:9bcdf88f62b0	1056	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1057	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
<>	128:9bcdf88f62b0	1058	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
<>	128:9bcdf88f62b0	1059	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1060	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
<>	128:9bcdf88f62b0	1061	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
<>	128:9bcdf88f62b0	1062	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1063	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
<>	128:9bcdf88f62b0	1064	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
<>	128:9bcdf88f62b0	1065	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1066	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
<>	128:9bcdf88f62b0	1067	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
<>	128:9bcdf88f62b0	1068	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1069	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
<>	128:9bcdf88f62b0	1070	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
<>	128:9bcdf88f62b0	1071	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1072	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
<>	128:9bcdf88f62b0	1073	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
<>	128:9bcdf88f62b0	1074	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1075	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
<>	128:9bcdf88f62b0	1076	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
<>	128:9bcdf88f62b0	1077	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1078	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
<>	128:9bcdf88f62b0	1079	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
<>	128:9bcdf88f62b0	1080	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1081	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
<>	128:9bcdf88f62b0	1082	#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only /
<>	128:9bcdf88f62b0	1083	#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1084	#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only /
<>	128:9bcdf88f62b0	1085	#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only /
<>	128:9bcdf88f62b0	1086	#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1087	#define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group regular only /
<>	128:9bcdf88f62b0	1088	#define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group injected only /
<>	128:9bcdf88f62b0	1089	#define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1090	#define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group regular only /
<>	128:9bcdf88f62b0	1091	#define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group injected only /
<>	128:9bcdf88f62b0	1092	#define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1093	#define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group regular only /
<>	128:9bcdf88f62b0	1094	#define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group injected only /
<>	128:9bcdf88f62b0	1095	#define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1096	#define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group regular only /
<>	128:9bcdf88f62b0	1097	#define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group injected only /
<>	128:9bcdf88f62b0	1098	#define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1099	#define LL_ADC_AWD_CHANNEL_24_REG ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group regular only /
<>	128:9bcdf88f62b0	1100	#define LL_ADC_AWD_CHANNEL_24_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group injected only /
<>	128:9bcdf88f62b0	1101	#define LL_ADC_AWD_CHANNEL_24_REG_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1102	#define LL_ADC_AWD_CHANNEL_25_REG ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group regular only /
<>	128:9bcdf88f62b0	1103	#define LL_ADC_AWD_CHANNEL_25_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group injected only /
<>	128:9bcdf88f62b0	1104	#define LL_ADC_AWD_CHANNEL_25_REG_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1105	#define LL_ADC_AWD_CHANNEL_26_REG ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group regular only /
<>	128:9bcdf88f62b0	1106	#define LL_ADC_AWD_CHANNEL_26_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group injected only /
<>	128:9bcdf88f62b0	1107	#define LL_ADC_AWD_CHANNEL_26_REG_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by either group regular or injected /
<>	128:9bcdf88f62b0	1108	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	1109	#define LL_ADC_AWD_CHANNEL_27_REG ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1110	#define LL_ADC_AWD_CHANNEL_27_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1111	#define LL_ADC_AWD_CHANNEL_27_REG_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1112	#define LL_ADC_AWD_CHANNEL_28_REG ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1113	#define LL_ADC_AWD_CHANNEL_28_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1114	#define LL_ADC_AWD_CHANNEL_28_REG_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1115	#define LL_ADC_AWD_CHANNEL_29_REG ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1116	#define LL_ADC_AWD_CHANNEL_29_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1117	#define LL_ADC_AWD_CHANNEL_29_REG_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1118	#define LL_ADC_AWD_CHANNEL_30_REG ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1119	#define LL_ADC_AWD_CHANNEL_30_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1120	#define LL_ADC_AWD_CHANNEL_30_REG_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1121	#define LL_ADC_AWD_CHANNEL_31_REG ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1122	#define LL_ADC_AWD_CHANNEL_31_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1123	#define LL_ADC_AWD_CHANNEL_31_REG_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. /
<>	128:9bcdf88f62b0	1124	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	1125	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1126	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1127	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1128	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1129	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1130	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1131	#define LL_ADC_AWD_CH_VCOMP_REG ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1132	#define LL_ADC_AWD_CH_VCOMP_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1133	#define LL_ADC_AWD_CH_VCOMP_REG_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1134	#if defined(OPAMP_CSR_OPA1PD) \|\| defined (OPAMP_CSR_OPA2PD) \|\| defined (OPAMP_CSR_OPA3PD)
<>	128:9bcdf88f62b0	1135	#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1136	#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1137	#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1138	#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1139	#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1140	#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1141	#if defined(OPAMP_CSR_OPA3PD)
<>	128:9bcdf88f62b0	1142	#define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1143	#define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1144	#define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. /
<>	128:9bcdf88f62b0	1145	#endif /* OPAMP_CSR_OPA3PD */
<>	128:9bcdf88f62b0	1146	#endif /* OPAMP_CSR_OPA1PD \|\| OPAMP_CSR_OPA2PD \|\| OPAMP_CSR_OPA3PD */
<>	128:9bcdf88f62b0	1147	/**
<>	128:9bcdf88f62b0	1148	* @}
<>	128:9bcdf88f62b0	1149	*/
<>	128:9bcdf88f62b0	1150
<>	128:9bcdf88f62b0	1151	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<>	128:9bcdf88f62b0	1152	* @{
<>	128:9bcdf88f62b0	1153	*/
<>	128:9bcdf88f62b0	1154	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /!< ADC analog watchdog threshold high /
<>	128:9bcdf88f62b0	1155	#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /!< ADC analog watchdog threshold low /
<>	128:9bcdf88f62b0	1156	/**
<>	128:9bcdf88f62b0	1157	* @}
<>	128:9bcdf88f62b0	1158	*/
<>	128:9bcdf88f62b0	1159
<>	128:9bcdf88f62b0	1160
<>	128:9bcdf88f62b0	1161	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<>	128:9bcdf88f62b0	1162	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
<>	128:9bcdf88f62b0	1163	* not timeout values.
<>	128:9bcdf88f62b0	1164	* For details on delays values, refer to descriptions in source code
<>	128:9bcdf88f62b0	1165	* above each literal definition.
<>	128:9bcdf88f62b0	1166	* @{
<>	128:9bcdf88f62b0	1167	*/
<>	128:9bcdf88f62b0	1168
<>	128:9bcdf88f62b0	1169	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<>	128:9bcdf88f62b0	1170	/* not timeout values. */
<>	128:9bcdf88f62b0	1171	/* Timeout values for ADC operations are dependent to device clock */
<>	128:9bcdf88f62b0	1172	/* configuration (system clock versus ADC clock), */
<>	128:9bcdf88f62b0	1173	/* and therefore must be defined in user application. */
<>	128:9bcdf88f62b0	1174	/* Indications for estimation of ADC timeout delays, for this */
<>	128:9bcdf88f62b0	1175	/* STM32 serie: */
<>	128:9bcdf88f62b0	1176	/* - ADC enable time: maximum delay is 3.5us */
<>	128:9bcdf88f62b0	1177	/* (refer to device datasheet, parameter "tSTAB") */
<>	128:9bcdf88f62b0	1178	/* - ADC conversion time: duration depending on ADC clock and ADC */
<>	128:9bcdf88f62b0	1179	/* configuration. */
<>	128:9bcdf88f62b0	1180	/* (refer to device reference manual, section "Timing") */
<>	128:9bcdf88f62b0	1181
<>	128:9bcdf88f62b0	1182	/* Delay for internal voltage reference stabilization time. */
<>	128:9bcdf88f62b0	1183	/* Delay set to maximum value (refer to device datasheet, */
<>	128:9bcdf88f62b0	1184	/* parameter "TADC_BUF"). */
<>	128:9bcdf88f62b0	1185	/* Unit: us */
<>	128:9bcdf88f62b0	1186	#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /!< Delay for internal voltage reference stabilization time /
<>	128:9bcdf88f62b0	1187
<>	128:9bcdf88f62b0	1188	/* Delay for temperature sensor stabilization time. */
<>	128:9bcdf88f62b0	1189	/* Literal set to maximum value (refer to device datasheet, */
<>	128:9bcdf88f62b0	1190	/* parameter "tSTART"). */
<>	128:9bcdf88f62b0	1191	/* Unit: us */
<>	128:9bcdf88f62b0	1192	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /!< Delay for internal voltage reference stabilization time /
<>	128:9bcdf88f62b0	1193
<>	128:9bcdf88f62b0	1194	/**
<>	128:9bcdf88f62b0	1195	* @}
<>	128:9bcdf88f62b0	1196	*/
<>	128:9bcdf88f62b0	1197
<>	128:9bcdf88f62b0	1198	/**
<>	128:9bcdf88f62b0	1199	* @}
<>	128:9bcdf88f62b0	1200	*/
<>	128:9bcdf88f62b0	1201
<>	128:9bcdf88f62b0	1202
<>	128:9bcdf88f62b0	1203	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	1204	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<>	128:9bcdf88f62b0	1205	* @{
<>	128:9bcdf88f62b0	1206	*/
<>	128:9bcdf88f62b0	1207
<>	128:9bcdf88f62b0	1208	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<>	128:9bcdf88f62b0	1209	* @{
<>	128:9bcdf88f62b0	1210	*/
<>	128:9bcdf88f62b0	1211
<>	128:9bcdf88f62b0	1212	/**
<>	128:9bcdf88f62b0	1213	* @brief Write a value in ADC register
<>	128:9bcdf88f62b0	1214	* @param __INSTANCE__ ADC Instance
<>	128:9bcdf88f62b0	1215	* @param __REG__ Register to be written
<>	128:9bcdf88f62b0	1216	* @param __VALUE__ Value to be written in the register
<>	128:9bcdf88f62b0	1217	* @retval None
<>	128:9bcdf88f62b0	1218	*/
<>	128:9bcdf88f62b0	1219	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	128:9bcdf88f62b0	1220
<>	128:9bcdf88f62b0	1221	/**
<>	128:9bcdf88f62b0	1222	* @brief Read a value in ADC register
<>	128:9bcdf88f62b0	1223	* @param __INSTANCE__ ADC Instance
<>	128:9bcdf88f62b0	1224	* @param __REG__ Register to be read
<>	128:9bcdf88f62b0	1225	* @retval Register value
<>	128:9bcdf88f62b0	1226	*/
<>	128:9bcdf88f62b0	1227	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	128:9bcdf88f62b0	1228	/**
<>	128:9bcdf88f62b0	1229	* @}
<>	128:9bcdf88f62b0	1230	*/
<>	128:9bcdf88f62b0	1231
<>	128:9bcdf88f62b0	1232	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<>	128:9bcdf88f62b0	1233	* @{
<>	128:9bcdf88f62b0	1234	*/
<>	128:9bcdf88f62b0	1235
<>	128:9bcdf88f62b0	1236	/**
<>	128:9bcdf88f62b0	1237	* @brief Helper macro to get ADC channel number in decimal format
<>	128:9bcdf88f62b0	1238	* from literals LL_ADC_CHANNEL_x.
<>	128:9bcdf88f62b0	1239	* @note Example:
<>	128:9bcdf88f62b0	1240	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<>	128:9bcdf88f62b0	1241	* will return decimal number "4".
<>	128:9bcdf88f62b0	1242	* @note The input can be a value from functions where a channel
<>	128:9bcdf88f62b0	1243	* number is returned, either defined with number
<>	128:9bcdf88f62b0	1244	* or with bitfield (only one bit must be set).
<>	128:9bcdf88f62b0	1245	* @param __CHANNEL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1246	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	1247	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	1248	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	1249	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	1250	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	1251	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	1252	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	1253	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	1254	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	1255	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	1256	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	1257	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	1258	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	1259	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	1260	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	1261	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	1262	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	1263	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	1264	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	1265	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	1266	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	1267	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	1268	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	1269	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	1270	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	1271	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	1272	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	1273	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	1274	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	1275	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	1276	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	1277	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	1278	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	1279	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	1280	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	1281	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1282	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1283	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1284	*
<>	128:9bcdf88f62b0	1285	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1286	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1287	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1288	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1289	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	1290	* @retval Value between Min_Data=0 and Max_Data=18
<>	128:9bcdf88f62b0	1291	*/
<>	128:9bcdf88f62b0	1292	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	128:9bcdf88f62b0	1293	(((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<>	128:9bcdf88f62b0	1294
<>	128:9bcdf88f62b0	1295	/**
<>	128:9bcdf88f62b0	1296	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<>	128:9bcdf88f62b0	1297	* from number in decimal format.
<>	128:9bcdf88f62b0	1298	* @note Example:
<>	128:9bcdf88f62b0	1299	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<>	128:9bcdf88f62b0	1300	* will return a data equivalent to "LL_ADC_CHANNEL_4".
<>	128:9bcdf88f62b0	1301	* @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
<>	128:9bcdf88f62b0	1302	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1303	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	1304	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	1305	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	1306	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	1307	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	1308	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	1309	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	1310	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	1311	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	1312	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	1313	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	1314	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	1315	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	1316	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	1317	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	1318	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	1319	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	1320	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	1321	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	1322	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	1323	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	1324	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	1325	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	1326	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	1327	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	1328	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	1329	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	1330	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	1331	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	1332	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	1333	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	1334	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	1335	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
<>	128:9bcdf88f62b0	1336	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
<>	128:9bcdf88f62b0	1337	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
<>	128:9bcdf88f62b0	1338	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1339	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1340	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1341	*
<>	128:9bcdf88f62b0	1342	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1343	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1344	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1345	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1346	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1347	* (6) For ADC channel read back from ADC register,
<>	128:9bcdf88f62b0	1348	* comparison with internal channel parameter to be done
<>	128:9bcdf88f62b0	1349	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	128:9bcdf88f62b0	1350	*/
<>	128:9bcdf88f62b0	1351	#if defined(ADC_SMPR0_SMP31)
<>	128:9bcdf88f62b0	1352	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	128:9bcdf88f62b0	1353	(((__DECIMAL_NB__) <= 9U) \
<>	128:9bcdf88f62b0	1354	? ( \
<>	128:9bcdf88f62b0	1355	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1356	(ADC_SMPR3_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1357	) \
<>	128:9bcdf88f62b0	1358	: \
<>	128:9bcdf88f62b0	1359	(((__DECIMAL_NB__) <= 19U) \
<>	128:9bcdf88f62b0	1360	? ( \
<>	128:9bcdf88f62b0	1361	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1362	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1363	) \
<>	128:9bcdf88f62b0	1364	: \
<>	128:9bcdf88f62b0	1365	(((__DECIMAL_NB__) <= 28U) \
<>	128:9bcdf88f62b0	1366	? ( \
<>	128:9bcdf88f62b0	1367	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1368	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1369	) \
<>	128:9bcdf88f62b0	1370	: \
<>	128:9bcdf88f62b0	1371	( \
<>	128:9bcdf88f62b0	1372	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1373	(ADC_SMPR0_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1374	) \
<>	128:9bcdf88f62b0	1375	) \
<>	128:9bcdf88f62b0	1376	) \
<>	128:9bcdf88f62b0	1377	)
<>	128:9bcdf88f62b0	1378	#else
<>	128:9bcdf88f62b0	1379	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	128:9bcdf88f62b0	1380	(((__DECIMAL_NB__) <= 9U) \
<>	128:9bcdf88f62b0	1381	? ( \
<>	128:9bcdf88f62b0	1382	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1383	(ADC_SMPR3_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1384	) \
<>	128:9bcdf88f62b0	1385	: \
<>	128:9bcdf88f62b0	1386	(((__DECIMAL_NB__) <= 19U) \
<>	128:9bcdf88f62b0	1387	? ( \
<>	128:9bcdf88f62b0	1388	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1389	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1390	) \
<>	128:9bcdf88f62b0	1391	: \
<>	128:9bcdf88f62b0	1392	( \
<>	128:9bcdf88f62b0	1393	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	128:9bcdf88f62b0	1394	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	128:9bcdf88f62b0	1395	) \
<>	128:9bcdf88f62b0	1396	) \
<>	128:9bcdf88f62b0	1397	)
<>	128:9bcdf88f62b0	1398	#endif /* ADC_SMPR0_SMP31 */
<>	128:9bcdf88f62b0	1399
<>	128:9bcdf88f62b0	1400	/**
<>	128:9bcdf88f62b0	1401	* @brief Helper macro to determine whether the selected channel
<>	128:9bcdf88f62b0	1402	* corresponds to literal definitions of driver.
<>	128:9bcdf88f62b0	1403	* @note The different literal definitions of ADC channels are:
<>	128:9bcdf88f62b0	1404	* - ADC internal channel:
<>	128:9bcdf88f62b0	1405	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<>	128:9bcdf88f62b0	1406	* - ADC external channel (channel connected to a GPIO pin):
<>	128:9bcdf88f62b0	1407	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<>	128:9bcdf88f62b0	1408	* @note The channel parameter must be a value defined from literal
<>	128:9bcdf88f62b0	1409	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	128:9bcdf88f62b0	1410	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	128:9bcdf88f62b0	1411	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<>	128:9bcdf88f62b0	1412	* must not be a value from functions where a channel number is
<>	128:9bcdf88f62b0	1413	* returned from ADC registers,
<>	128:9bcdf88f62b0	1414	* because internal and external channels share the same channel
<>	128:9bcdf88f62b0	1415	* number in ADC registers. The differentiation is made only with
<>	128:9bcdf88f62b0	1416	* parameters definitions of driver.
<>	128:9bcdf88f62b0	1417	* @param __CHANNEL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1418	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	1419	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	1420	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	1421	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	1422	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	1423	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	1424	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	1425	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	1426	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	1427	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	1428	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	1429	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	1430	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	1431	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	1432	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	1433	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	1434	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	1435	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	1436	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	1437	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	1438	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	1439	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	1440	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	1441	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	1442	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	1443	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	1444	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	1445	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	1446	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	1447	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	1448	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	1449	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	1450	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	1451	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	1452	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	1453	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1454	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1455	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1456	*
<>	128:9bcdf88f62b0	1457	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1458	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1459	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1460	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1461	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	1462	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<>	128:9bcdf88f62b0	1463	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<>	128:9bcdf88f62b0	1464	*/
<>	128:9bcdf88f62b0	1465	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<>	128:9bcdf88f62b0	1466	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<>	128:9bcdf88f62b0	1467
<>	128:9bcdf88f62b0	1468	/**
<>	128:9bcdf88f62b0	1469	* @brief Helper macro to convert a channel defined from parameter
<>	128:9bcdf88f62b0	1470	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	128:9bcdf88f62b0	1471	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	128:9bcdf88f62b0	1472	* to its equivalent parameter definition of a ADC external channel
<>	128:9bcdf88f62b0	1473	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<>	128:9bcdf88f62b0	1474	* @note The channel parameter can be, additionally to a value
<>	128:9bcdf88f62b0	1475	* defined from parameter definition of a ADC internal channel
<>	128:9bcdf88f62b0	1476	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	128:9bcdf88f62b0	1477	* a value defined from parameter definition of
<>	128:9bcdf88f62b0	1478	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	128:9bcdf88f62b0	1479	* or a value from functions where a channel number is returned
<>	128:9bcdf88f62b0	1480	* from ADC registers.
<>	128:9bcdf88f62b0	1481	* @param __CHANNEL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1482	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	1483	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	1484	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	1485	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	1486	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	1487	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	1488	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	1489	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	1490	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	1491	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	1492	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	1493	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	1494	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	1495	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	1496	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	1497	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	1498	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	1499	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	1500	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	1501	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	1502	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	1503	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	1504	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	1505	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	1506	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	1507	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	1508	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	1509	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	1510	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	1511	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	1512	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	1513	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	1514	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	1515	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	1516	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	1517	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1518	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1519	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1520	*
<>	128:9bcdf88f62b0	1521	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1522	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1523	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1524	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1525	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	1526	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1527	* @arg @ref LL_ADC_CHANNEL_0
<>	128:9bcdf88f62b0	1528	* @arg @ref LL_ADC_CHANNEL_1
<>	128:9bcdf88f62b0	1529	* @arg @ref LL_ADC_CHANNEL_2
<>	128:9bcdf88f62b0	1530	* @arg @ref LL_ADC_CHANNEL_3
<>	128:9bcdf88f62b0	1531	* @arg @ref LL_ADC_CHANNEL_4
<>	128:9bcdf88f62b0	1532	* @arg @ref LL_ADC_CHANNEL_5
<>	128:9bcdf88f62b0	1533	* @arg @ref LL_ADC_CHANNEL_6
<>	128:9bcdf88f62b0	1534	* @arg @ref LL_ADC_CHANNEL_7
<>	128:9bcdf88f62b0	1535	* @arg @ref LL_ADC_CHANNEL_8
<>	128:9bcdf88f62b0	1536	* @arg @ref LL_ADC_CHANNEL_9
<>	128:9bcdf88f62b0	1537	* @arg @ref LL_ADC_CHANNEL_10
<>	128:9bcdf88f62b0	1538	* @arg @ref LL_ADC_CHANNEL_11
<>	128:9bcdf88f62b0	1539	* @arg @ref LL_ADC_CHANNEL_12
<>	128:9bcdf88f62b0	1540	* @arg @ref LL_ADC_CHANNEL_13
<>	128:9bcdf88f62b0	1541	* @arg @ref LL_ADC_CHANNEL_14
<>	128:9bcdf88f62b0	1542	* @arg @ref LL_ADC_CHANNEL_15
<>	128:9bcdf88f62b0	1543	* @arg @ref LL_ADC_CHANNEL_16
<>	128:9bcdf88f62b0	1544	* @arg @ref LL_ADC_CHANNEL_17
<>	128:9bcdf88f62b0	1545	* @arg @ref LL_ADC_CHANNEL_18
<>	128:9bcdf88f62b0	1546	*/
<>	128:9bcdf88f62b0	1547	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<>	128:9bcdf88f62b0	1548	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	128:9bcdf88f62b0	1549
<>	128:9bcdf88f62b0	1550	/**
<>	128:9bcdf88f62b0	1551	* @brief Helper macro to determine whether the internal channel
<>	128:9bcdf88f62b0	1552	* selected is available on the ADC instance selected.
<>	128:9bcdf88f62b0	1553	* @note The channel parameter must be a value defined from parameter
<>	128:9bcdf88f62b0	1554	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	128:9bcdf88f62b0	1555	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	128:9bcdf88f62b0	1556	* must not be a value defined from parameter definition of
<>	128:9bcdf88f62b0	1557	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	128:9bcdf88f62b0	1558	* or a value from functions where a channel number is
<>	128:9bcdf88f62b0	1559	* returned from ADC registers,
<>	128:9bcdf88f62b0	1560	* because internal and external channels share the same channel
<>	128:9bcdf88f62b0	1561	* number in ADC registers. The differentiation is made only with
<>	128:9bcdf88f62b0	1562	* parameters definitions of driver.
<>	128:9bcdf88f62b0	1563	* @param __ADC_INSTANCE__ ADC instance
<>	128:9bcdf88f62b0	1564	* @param __CHANNEL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1565	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	1566	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	1567	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	1568	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1569	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1570	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1571	*
<>	128:9bcdf88f62b0	1572	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1573	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1574	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1575	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1576	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	1577	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<>	128:9bcdf88f62b0	1578	* Value "1" if the internal channel selected is available on the ADC instance selected.
<>	128:9bcdf88f62b0	1579	*/
<>	128:9bcdf88f62b0	1580	#if defined (OPAMP_CSR_OPA3PD)
<>	128:9bcdf88f62b0	1581	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	1582	( \
<>	128:9bcdf88f62b0	1583	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	128:9bcdf88f62b0	1584	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	128:9bcdf88f62b0	1585	((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) \|\| \
<>	128:9bcdf88f62b0	1586	((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \|\| \
<>	128:9bcdf88f62b0	1587	((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \|\| \
<>	128:9bcdf88f62b0	1588	((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
<>	128:9bcdf88f62b0	1589	)
<>	128:9bcdf88f62b0	1590	#elif defined(OPAMP_CSR_OPA1PD) \|\| defined (OPAMP_CSR_OPA2PD)
<>	128:9bcdf88f62b0	1591	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	1592	( \
<>	128:9bcdf88f62b0	1593	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	128:9bcdf88f62b0	1594	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	128:9bcdf88f62b0	1595	((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) \|\| \
<>	128:9bcdf88f62b0	1596	((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \|\| \
<>	128:9bcdf88f62b0	1597	((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
<>	128:9bcdf88f62b0	1598	)
<>	128:9bcdf88f62b0	1599	#else
<>	128:9bcdf88f62b0	1600	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	1601	( \
<>	128:9bcdf88f62b0	1602	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	128:9bcdf88f62b0	1603	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	128:9bcdf88f62b0	1604	((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) \
<>	128:9bcdf88f62b0	1605	)
<>	128:9bcdf88f62b0	1606	#endif
<>	128:9bcdf88f62b0	1607
<>	128:9bcdf88f62b0	1608	/**
<>	128:9bcdf88f62b0	1609	* @brief Helper macro to define ADC analog watchdog parameter:
<>	128:9bcdf88f62b0	1610	* define a single channel to monitor with analog watchdog
<>	128:9bcdf88f62b0	1611	* from sequencer channel and groups definition.
<>	128:9bcdf88f62b0	1612	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<>	128:9bcdf88f62b0	1613	* Example:
<>	128:9bcdf88f62b0	1614	* LL_ADC_SetAnalogWDMonitChannels(
<>	128:9bcdf88f62b0	1615	* ADC1, LL_ADC_AWD1,
<>	128:9bcdf88f62b0	1616	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<>	128:9bcdf88f62b0	1617	* @param __CHANNEL__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1618	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	1619	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	1620	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	1621	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	1622	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	1623	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	1624	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	1625	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	1626	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	1627	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	1628	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	1629	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	1630	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	1631	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	1632	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	1633	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	1634	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	1635	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	1636	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	1637	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	1638	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	1639	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	1640	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	1641	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	1642	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	1643	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	1644	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	1645	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	1646	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	1647	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	1648	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	1649	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	1650	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
<>	128:9bcdf88f62b0	1651	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
<>	128:9bcdf88f62b0	1652	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
<>	128:9bcdf88f62b0	1653	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	1654	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	1655	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	1656	*
<>	128:9bcdf88f62b0	1657	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1658	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1659	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1660	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1661	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1662	* (6) For ADC channel read back from ADC register,
<>	128:9bcdf88f62b0	1663	* comparison with internal channel parameter to be done
<>	128:9bcdf88f62b0	1664	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	128:9bcdf88f62b0	1665	* @param __GROUP__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1666	* @arg @ref LL_ADC_GROUP_REGULAR
<>	128:9bcdf88f62b0	1667	* @arg @ref LL_ADC_GROUP_INJECTED
<>	128:9bcdf88f62b0	1668	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
<>	128:9bcdf88f62b0	1669	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	1670	* @arg @ref LL_ADC_AWD_DISABLE
<>	128:9bcdf88f62b0	1671	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	128:9bcdf88f62b0	1672	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	128:9bcdf88f62b0	1673	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	128:9bcdf88f62b0	1674	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
<>	128:9bcdf88f62b0	1675	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
<>	128:9bcdf88f62b0	1676	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
<>	128:9bcdf88f62b0	1677	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
<>	128:9bcdf88f62b0	1678	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
<>	128:9bcdf88f62b0	1679	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
<>	128:9bcdf88f62b0	1680	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
<>	128:9bcdf88f62b0	1681	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
<>	128:9bcdf88f62b0	1682	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
<>	128:9bcdf88f62b0	1683	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
<>	128:9bcdf88f62b0	1684	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
<>	128:9bcdf88f62b0	1685	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
<>	128:9bcdf88f62b0	1686	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
<>	128:9bcdf88f62b0	1687	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
<>	128:9bcdf88f62b0	1688	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
<>	128:9bcdf88f62b0	1689	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
<>	128:9bcdf88f62b0	1690	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
<>	128:9bcdf88f62b0	1691	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
<>	128:9bcdf88f62b0	1692	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
<>	128:9bcdf88f62b0	1693	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
<>	128:9bcdf88f62b0	1694	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
<>	128:9bcdf88f62b0	1695	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
<>	128:9bcdf88f62b0	1696	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
<>	128:9bcdf88f62b0	1697	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
<>	128:9bcdf88f62b0	1698	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
<>	128:9bcdf88f62b0	1699	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
<>	128:9bcdf88f62b0	1700	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
<>	128:9bcdf88f62b0	1701	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
<>	128:9bcdf88f62b0	1702	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
<>	128:9bcdf88f62b0	1703	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
<>	128:9bcdf88f62b0	1704	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
<>	128:9bcdf88f62b0	1705	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
<>	128:9bcdf88f62b0	1706	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
<>	128:9bcdf88f62b0	1707	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
<>	128:9bcdf88f62b0	1708	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
<>	128:9bcdf88f62b0	1709	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
<>	128:9bcdf88f62b0	1710	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
<>	128:9bcdf88f62b0	1711	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
<>	128:9bcdf88f62b0	1712	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
<>	128:9bcdf88f62b0	1713	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
<>	128:9bcdf88f62b0	1714	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
<>	128:9bcdf88f62b0	1715	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
<>	128:9bcdf88f62b0	1716	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
<>	128:9bcdf88f62b0	1717	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
<>	128:9bcdf88f62b0	1718	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
<>	128:9bcdf88f62b0	1719	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
<>	128:9bcdf88f62b0	1720	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
<>	128:9bcdf88f62b0	1721	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
<>	128:9bcdf88f62b0	1722	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
<>	128:9bcdf88f62b0	1723	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
<>	128:9bcdf88f62b0	1724	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
<>	128:9bcdf88f62b0	1725	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
<>	128:9bcdf88f62b0	1726	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
<>	128:9bcdf88f62b0	1727	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
<>	128:9bcdf88f62b0	1728	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
<>	128:9bcdf88f62b0	1729	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
<>	128:9bcdf88f62b0	1730	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
<>	128:9bcdf88f62b0	1731	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
<>	128:9bcdf88f62b0	1732	* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
<>	128:9bcdf88f62b0	1733	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
<>	128:9bcdf88f62b0	1734	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
<>	128:9bcdf88f62b0	1735	* @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
<>	128:9bcdf88f62b0	1736	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
<>	128:9bcdf88f62b0	1737	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
<>	128:9bcdf88f62b0	1738	* @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
<>	128:9bcdf88f62b0	1739	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
<>	128:9bcdf88f62b0	1740	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
<>	128:9bcdf88f62b0	1741	* @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
<>	128:9bcdf88f62b0	1742	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
<>	128:9bcdf88f62b0	1743	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
<>	128:9bcdf88f62b0	1744	* @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
<>	128:9bcdf88f62b0	1745	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
<>	128:9bcdf88f62b0	1746	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
<>	128:9bcdf88f62b0	1747	* @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
<>	128:9bcdf88f62b0	1748	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
<>	128:9bcdf88f62b0	1749	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
<>	128:9bcdf88f62b0	1750	* @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
<>	128:9bcdf88f62b0	1751	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
<>	128:9bcdf88f62b0	1752	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
<>	128:9bcdf88f62b0	1753	* @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
<>	128:9bcdf88f62b0	1754	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
<>	128:9bcdf88f62b0	1755	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
<>	128:9bcdf88f62b0	1756	* @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
<>	128:9bcdf88f62b0	1757	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	1758	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
<>	128:9bcdf88f62b0	1759	* @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
<>	128:9bcdf88f62b0	1760	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	1761	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
<>	128:9bcdf88f62b0	1762	* @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
<>	128:9bcdf88f62b0	1763	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	1764	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
<>	128:9bcdf88f62b0	1765	* @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
<>	128:9bcdf88f62b0	1766	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	1767	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
<>	128:9bcdf88f62b0	1768	* @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
<>	128:9bcdf88f62b0	1769	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	1770	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3)
<>	128:9bcdf88f62b0	1771	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3)
<>	128:9bcdf88f62b0	1772	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3)
<>	128:9bcdf88f62b0	1773	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3)
<>	128:9bcdf88f62b0	1774	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3)
<>	128:9bcdf88f62b0	1775	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3)
<>	128:9bcdf88f62b0	1776	* @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3)
<>	128:9bcdf88f62b0	1777	* @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3)
<>	128:9bcdf88f62b0	1778	* @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3)
<>	128:9bcdf88f62b0	1779	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5)
<>	128:9bcdf88f62b0	1780	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5)
<>	128:9bcdf88f62b0	1781	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	1782	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5)
<>	128:9bcdf88f62b0	1783	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5)
<>	128:9bcdf88f62b0	1784	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	1785	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5)
<>	128:9bcdf88f62b0	1786	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5)
<>	128:9bcdf88f62b0	1787	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	1788	*
<>	128:9bcdf88f62b0	1789	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	1790	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	1791	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	1792	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	1793	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	1794	*/
<>	128:9bcdf88f62b0	1795	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<>	128:9bcdf88f62b0	1796	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
<>	128:9bcdf88f62b0	1797	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	128:9bcdf88f62b0	1798	: \
<>	128:9bcdf88f62b0	1799	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
<>	128:9bcdf88f62b0	1800	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) \
<>	128:9bcdf88f62b0	1801	: \
<>	128:9bcdf88f62b0	1802	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	128:9bcdf88f62b0	1803	)
<>	128:9bcdf88f62b0	1804
<>	128:9bcdf88f62b0	1805	/**
<>	128:9bcdf88f62b0	1806	* @brief Helper macro to set the value of ADC analog watchdog threshold high
<>	128:9bcdf88f62b0	1807	* or low in function of ADC resolution, when ADC resolution is
<>	128:9bcdf88f62b0	1808	* different of 12 bits.
<>	128:9bcdf88f62b0	1809	* @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
<>	128:9bcdf88f62b0	1810	* Example, with a ADC resolution of 8 bits, to set the value of
<>	128:9bcdf88f62b0	1811	* analog watchdog threshold high (on 8 bits):
<>	128:9bcdf88f62b0	1812	* LL_ADC_SetAnalogWDThresholds
<>	128:9bcdf88f62b0	1813	* (< ADCx param >,
<>	128:9bcdf88f62b0	1814	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<>	128:9bcdf88f62b0	1815	* );
<>	128:9bcdf88f62b0	1816	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1817	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1818	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1819	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1820	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1821	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	1822	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	1823	*/
<>	128:9bcdf88f62b0	1824	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<>	128:9bcdf88f62b0	1825	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	128:9bcdf88f62b0	1826
<>	128:9bcdf88f62b0	1827	/**
<>	128:9bcdf88f62b0	1828	* @brief Helper macro to get the value of ADC analog watchdog threshold high
<>	128:9bcdf88f62b0	1829	* or low in function of ADC resolution, when ADC resolution is
<>	128:9bcdf88f62b0	1830	* different of 12 bits.
<>	128:9bcdf88f62b0	1831	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	128:9bcdf88f62b0	1832	* Example, with a ADC resolution of 8 bits, to get the value of
<>	128:9bcdf88f62b0	1833	* analog watchdog threshold high (on 8 bits):
<>	128:9bcdf88f62b0	1834	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<>	128:9bcdf88f62b0	1835	* (LL_ADC_RESOLUTION_8B,
<>	128:9bcdf88f62b0	1836	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<>	128:9bcdf88f62b0	1837	* );
<>	128:9bcdf88f62b0	1838	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1839	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1840	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1841	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1842	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1843	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	1844	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	1845	*/
<>	128:9bcdf88f62b0	1846	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<>	128:9bcdf88f62b0	1847	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	128:9bcdf88f62b0	1848
<>	128:9bcdf88f62b0	1849	/**
<>	128:9bcdf88f62b0	1850	* @brief Helper macro to select the ADC common instance
<>	128:9bcdf88f62b0	1851	* to which is belonging the selected ADC instance.
<>	128:9bcdf88f62b0	1852	* @note ADC common register instance can be used for:
<>	128:9bcdf88f62b0	1853	* - Set parameters common to several ADC instances
<>	128:9bcdf88f62b0	1854	* - Multimode (for devices with several ADC instances)
<>	128:9bcdf88f62b0	1855	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	128:9bcdf88f62b0	1856	* @param __ADCx__ ADC instance
<>	128:9bcdf88f62b0	1857	* @retval ADC common register instance
<>	128:9bcdf88f62b0	1858	*/
<>	128:9bcdf88f62b0	1859	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	128:9bcdf88f62b0	1860	(ADC1_COMMON)
<>	128:9bcdf88f62b0	1861
<>	128:9bcdf88f62b0	1862	/**
<>	128:9bcdf88f62b0	1863	* @brief Helper macro to check if all ADC instances sharing the same
<>	128:9bcdf88f62b0	1864	* ADC common instance are disabled.
<>	128:9bcdf88f62b0	1865	* @note This check is required by functions with setting conditioned to
<>	128:9bcdf88f62b0	1866	* ADC state:
<>	128:9bcdf88f62b0	1867	* All ADC instances of the ADC common group must be disabled.
<>	128:9bcdf88f62b0	1868	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	128:9bcdf88f62b0	1869	* @note On devices with only 1 ADC common instance, parameter of this macro
<>	128:9bcdf88f62b0	1870	* is useless and can be ignored (parameter kept for compatibility
<>	128:9bcdf88f62b0	1871	* with devices featuring several ADC common instances).
<>	128:9bcdf88f62b0	1872	* @param __ADCXY_COMMON__ ADC common instance
<>	128:9bcdf88f62b0	1873	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	128:9bcdf88f62b0	1874	* @retval Value "0" if all ADC instances sharing the same ADC common instance
<>	128:9bcdf88f62b0	1875	* are disabled.
<>	128:9bcdf88f62b0	1876	* Value "1" if at least one ADC instance sharing the same ADC common instance
<>	128:9bcdf88f62b0	1877	* is enabled.
<>	128:9bcdf88f62b0	1878	*/
<>	128:9bcdf88f62b0	1879	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	128:9bcdf88f62b0	1880	LL_ADC_IsEnabled(ADC1)
<>	128:9bcdf88f62b0	1881
<>	128:9bcdf88f62b0	1882	/**
<>	128:9bcdf88f62b0	1883	* @brief Helper macro to define the ADC conversion data full-scale digital
<>	128:9bcdf88f62b0	1884	* value corresponding to the selected ADC resolution.
<>	128:9bcdf88f62b0	1885	* @note ADC conversion data full-scale corresponds to voltage range
<>	128:9bcdf88f62b0	1886	* determined by analog voltage references Vref+ and Vref-
<>	128:9bcdf88f62b0	1887	* (refer to reference manual).
<>	128:9bcdf88f62b0	1888	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1889	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1890	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1891	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1892	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1893	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	128:9bcdf88f62b0	1894	*/
<>	128:9bcdf88f62b0	1895	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	1896	(((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
<>	128:9bcdf88f62b0	1897
<>	128:9bcdf88f62b0	1898	/**
<>	128:9bcdf88f62b0	1899	* @brief Helper macro to convert the ADC conversion data from
<>	128:9bcdf88f62b0	1900	* a resolution to another resolution.
<>	128:9bcdf88f62b0	1901	* @param __DATA__ ADC conversion data to be converted
<>	128:9bcdf88f62b0	1902	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<>	128:9bcdf88f62b0	1903	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1904	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1905	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1906	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1907	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1908	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<>	128:9bcdf88f62b0	1909	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1910	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1911	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1912	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1913	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1914	* @retval ADC conversion data to the requested resolution
<>	128:9bcdf88f62b0	1915	*/
<>	128:9bcdf88f62b0	1916	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
<>	128:9bcdf88f62b0	1917	(((__DATA__) \
<>	128:9bcdf88f62b0	1918	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
<>	128:9bcdf88f62b0	1919	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
<>	128:9bcdf88f62b0	1920	)
<>	128:9bcdf88f62b0	1921
<>	128:9bcdf88f62b0	1922	/**
<>	128:9bcdf88f62b0	1923	* @brief Helper macro to calculate the voltage (unit: mVolt)
<>	128:9bcdf88f62b0	1924	* corresponding to a ADC conversion data (unit: digital value).
<>	128:9bcdf88f62b0	1925	* @note Analog reference voltage (Vref+) must be either known from
<>	128:9bcdf88f62b0	1926	* user board environment or can be calculated using ADC measurement
<>	128:9bcdf88f62b0	1927	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	128:9bcdf88f62b0	1928	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	128:9bcdf88f62b0	1929	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	128:9bcdf88f62b0	1930	* (unit: digital value).
<>	128:9bcdf88f62b0	1931	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1932	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1933	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1934	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1935	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1936	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	128:9bcdf88f62b0	1937	*/
<>	128:9bcdf88f62b0	1938	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<>	128:9bcdf88f62b0	1939	__ADC_DATA__,\
<>	128:9bcdf88f62b0	1940	__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	1941	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<>	128:9bcdf88f62b0	1942	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	1943	)
<>	128:9bcdf88f62b0	1944
<>	128:9bcdf88f62b0	1945	/**
<>	128:9bcdf88f62b0	1946	* @brief Helper macro to calculate analog reference voltage (Vref+)
<>	128:9bcdf88f62b0	1947	* (unit: mVolt) from ADC conversion data of internal voltage
<>	128:9bcdf88f62b0	1948	* reference VrefInt.
<>	128:9bcdf88f62b0	1949	* @note Computation is using VrefInt calibration value
<>	128:9bcdf88f62b0	1950	* stored in system memory for each device during production.
<>	128:9bcdf88f62b0	1951	* @note This voltage depends on user board environment: voltage level
<>	128:9bcdf88f62b0	1952	* connected to pin Vref+.
<>	128:9bcdf88f62b0	1953	* On devices with small package, the pin Vref+ is not present
<>	128:9bcdf88f62b0	1954	* and internally bonded to pin Vdda.
<>	128:9bcdf88f62b0	1955	* @note On this STM32 serie, calibration data of internal voltage reference
<>	128:9bcdf88f62b0	1956	* VrefInt corresponds to a resolution of 12 bits,
<>	128:9bcdf88f62b0	1957	* this is the recommended ADC resolution to convert voltage of
<>	128:9bcdf88f62b0	1958	* internal voltage reference VrefInt.
<>	128:9bcdf88f62b0	1959	* Otherwise, this macro performs the processing to scale
<>	128:9bcdf88f62b0	1960	* ADC conversion data to 12 bits.
<>	128:9bcdf88f62b0	1961	* @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
<>	128:9bcdf88f62b0	1962	* of internal voltage reference VrefInt (unit: digital value).
<>	128:9bcdf88f62b0	1963	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1964	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	1965	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	1966	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	1967	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	1968	* @retval Analog reference voltage (unit: mV)
<>	128:9bcdf88f62b0	1969	*/
<>	128:9bcdf88f62b0	1970	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<>	128:9bcdf88f62b0	1971	__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	1972	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
<>	128:9bcdf88f62b0	1973	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<>	128:9bcdf88f62b0	1974	(__ADC_RESOLUTION__), \
<>	128:9bcdf88f62b0	1975	LL_ADC_RESOLUTION_12B) \
<>	128:9bcdf88f62b0	1976	)
<>	128:9bcdf88f62b0	1977
<>	128:9bcdf88f62b0	1978	/**
<>	128:9bcdf88f62b0	1979	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	128:9bcdf88f62b0	1980	* from ADC conversion data of internal temperature sensor.
<>	128:9bcdf88f62b0	1981	* @note Computation is using temperature sensor calibration values
<>	128:9bcdf88f62b0	1982	* stored in system memory for each device during production.
<>	128:9bcdf88f62b0	1983	* @note Calculation formula:
<>	128:9bcdf88f62b0	1984	* Temperature = ((TS_ADC_DATA - TS_CAL1)
<>	128:9bcdf88f62b0	1985	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<>	128:9bcdf88f62b0	1986	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<>	128:9bcdf88f62b0	1987	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	128:9bcdf88f62b0	1988	* Avg_Slope = (TS_CAL2 - TS_CAL1)
<>	128:9bcdf88f62b0	1989	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<>	128:9bcdf88f62b0	1990	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
<>	128:9bcdf88f62b0	1991	* TEMP_DEGC_CAL1 (calibrated in factory)
<>	128:9bcdf88f62b0	1992	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
<>	128:9bcdf88f62b0	1993	* TEMP_DEGC_CAL2 (calibrated in factory)
<>	128:9bcdf88f62b0	1994	* Caution: Calculation relevancy under reserve that calibration
<>	128:9bcdf88f62b0	1995	* parameters are correct (address and data).
<>	128:9bcdf88f62b0	1996	* To calculate temperature using temperature sensor
<>	128:9bcdf88f62b0	1997	* datasheet typical values (generic values less, therefore
<>	128:9bcdf88f62b0	1998	* less accurate than calibrated values),
<>	128:9bcdf88f62b0	1999	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<>	128:9bcdf88f62b0	2000	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	128:9bcdf88f62b0	2001	* defined as it impacts the ADC LSB equivalent voltage.
<>	128:9bcdf88f62b0	2002	* @note Analog reference voltage (Vref+) must be either known from
<>	128:9bcdf88f62b0	2003	* user board environment or can be calculated using ADC measurement
<>	128:9bcdf88f62b0	2004	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	128:9bcdf88f62b0	2005	* @note On this STM32 serie, calibration data of temperature sensor
<>	128:9bcdf88f62b0	2006	* corresponds to a resolution of 12 bits,
<>	128:9bcdf88f62b0	2007	* this is the recommended ADC resolution to convert voltage of
<>	128:9bcdf88f62b0	2008	* temperature sensor.
<>	128:9bcdf88f62b0	2009	* Otherwise, this macro performs the processing to scale
<>	128:9bcdf88f62b0	2010	* ADC conversion data to 12 bits.
<>	128:9bcdf88f62b0	2011	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	128:9bcdf88f62b0	2012	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<>	128:9bcdf88f62b0	2013	* temperature sensor (unit: digital value).
<>	128:9bcdf88f62b0	2014	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<>	128:9bcdf88f62b0	2015	* sensor voltage has been measured.
<>	128:9bcdf88f62b0	2016	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2017	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	2018	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	2019	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	2020	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	2021	* @retval Temperature (unit: degree Celsius)
<>	128:9bcdf88f62b0	2022	*/
<>	128:9bcdf88f62b0	2023	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<>	128:9bcdf88f62b0	2024	__TEMPSENSOR_ADC_DATA__,\
<>	128:9bcdf88f62b0	2025	__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	2026	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<>	128:9bcdf88f62b0	2027	(__ADC_RESOLUTION__), \
<>	128:9bcdf88f62b0	2028	LL_ADC_RESOLUTION_12B) \
<>	128:9bcdf88f62b0	2029	* (__VREFANALOG_VOLTAGE__)) \
<>	128:9bcdf88f62b0	2030	/ TEMPSENSOR_CAL_VREFANALOG) \
<>	128:9bcdf88f62b0	2031	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<>	128:9bcdf88f62b0	2032	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<>	128:9bcdf88f62b0	2033	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
<>	128:9bcdf88f62b0	2034	) + TEMPSENSOR_CAL1_TEMP \
<>	128:9bcdf88f62b0	2035	)
<>	128:9bcdf88f62b0	2036
<>	128:9bcdf88f62b0	2037	/**
<>	128:9bcdf88f62b0	2038	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	128:9bcdf88f62b0	2039	* from ADC conversion data of internal temperature sensor.
<>	128:9bcdf88f62b0	2040	* @note Computation is using temperature sensor typical values
<>	128:9bcdf88f62b0	2041	* (refer to device datasheet).
<>	128:9bcdf88f62b0	2042	* @note Calculation formula:
<>	128:9bcdf88f62b0	2043	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<>	128:9bcdf88f62b0	2044	* / Avg_Slope + CALx_TEMP
<>	128:9bcdf88f62b0	2045	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	128:9bcdf88f62b0	2046	* (unit: digital value)
<>	128:9bcdf88f62b0	2047	* Avg_Slope = temperature sensor slope
<>	128:9bcdf88f62b0	2048	* (unit: uV/Degree Celsius)
<>	128:9bcdf88f62b0	2049	* TS_TYP_CALx_VOLT = temperature sensor digital value at
<>	128:9bcdf88f62b0	2050	* temperature CALx_TEMP (unit: mV)
<>	128:9bcdf88f62b0	2051	* Caution: Calculation relevancy under reserve the temperature sensor
<>	128:9bcdf88f62b0	2052	* of the current device has characteristics in line with
<>	128:9bcdf88f62b0	2053	* datasheet typical values.
<>	128:9bcdf88f62b0	2054	* If temperature sensor calibration values are available on
<>	128:9bcdf88f62b0	2055	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<>	128:9bcdf88f62b0	2056	* temperature calculation will be more accurate using
<>	128:9bcdf88f62b0	2057	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<>	128:9bcdf88f62b0	2058	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	128:9bcdf88f62b0	2059	* defined as it impacts the ADC LSB equivalent voltage.
<>	128:9bcdf88f62b0	2060	* @note Analog reference voltage (Vref+) must be either known from
<>	128:9bcdf88f62b0	2061	* user board environment or can be calculated using ADC measurement
<>	128:9bcdf88f62b0	2062	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	128:9bcdf88f62b0	2063	* @note ADC measurement data must correspond to a resolution of 12bits
<>	128:9bcdf88f62b0	2064	* (full scale digital value 4095). If not the case, the data must be
<>	128:9bcdf88f62b0	2065	* preliminarily rescaled to an equivalent resolution of 12 bits.
<>	128:9bcdf88f62b0	2066	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
<>	128:9bcdf88f62b0	2067	* On STM32L1, refer to device datasheet parameter "Avg_Slope".
<>	128:9bcdf88f62b0	2068	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
<>	128:9bcdf88f62b0	2069	* On STM32L1, refer to device datasheet parameter "V110" (corresponding to TS_CAL2).
<>	128:9bcdf88f62b0	2070	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
<>	128:9bcdf88f62b0	2071	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
<>	128:9bcdf88f62b0	2072	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
<>	128:9bcdf88f62b0	2073	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<>	128:9bcdf88f62b0	2074	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2075	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	2076	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	2077	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	2078	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	2079	* @retval Temperature (unit: degree Celsius)
<>	128:9bcdf88f62b0	2080	*/
<>	128:9bcdf88f62b0	2081	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<>	128:9bcdf88f62b0	2082	__TEMPSENSOR_TYP_CALX_V__,\
<>	128:9bcdf88f62b0	2083	__TEMPSENSOR_CALX_TEMP__,\
<>	128:9bcdf88f62b0	2084	__VREFANALOG_VOLTAGE__,\
<>	128:9bcdf88f62b0	2085	__TEMPSENSOR_ADC_DATA__,\
<>	128:9bcdf88f62b0	2086	__ADC_RESOLUTION__) \
<>	128:9bcdf88f62b0	2087	((( ( \
<>	128:9bcdf88f62b0	2088	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<>	128:9bcdf88f62b0	2089	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<>	128:9bcdf88f62b0	2090	* 1000) \
<>	128:9bcdf88f62b0	2091	- \
<>	128:9bcdf88f62b0	2092	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<>	128:9bcdf88f62b0	2093	* 1000) \
<>	128:9bcdf88f62b0	2094	) \
<>	128:9bcdf88f62b0	2095	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<>	128:9bcdf88f62b0	2096	) + (__TEMPSENSOR_CALX_TEMP__) \
<>	128:9bcdf88f62b0	2097	)
<>	128:9bcdf88f62b0	2098
<>	128:9bcdf88f62b0	2099	/**
<>	128:9bcdf88f62b0	2100	* @}
<>	128:9bcdf88f62b0	2101	*/
<>	128:9bcdf88f62b0	2102
<>	128:9bcdf88f62b0	2103	/**
<>	128:9bcdf88f62b0	2104	* @}
<>	128:9bcdf88f62b0	2105	*/
<>	128:9bcdf88f62b0	2106
<>	128:9bcdf88f62b0	2107
<>	128:9bcdf88f62b0	2108	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	2109	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<>	128:9bcdf88f62b0	2110	* @{
<>	128:9bcdf88f62b0	2111	*/
<>	128:9bcdf88f62b0	2112
<>	128:9bcdf88f62b0	2113	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<>	128:9bcdf88f62b0	2114	* @{
<>	128:9bcdf88f62b0	2115	*/
<>	128:9bcdf88f62b0	2116	/* Note: LL ADC functions to set DMA transfer are located into sections of */
<>	128:9bcdf88f62b0	2117	/* configuration of ADC instance, groups and multimode (if available): */
<>	128:9bcdf88f62b0	2118	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
<>	128:9bcdf88f62b0	2119
<>	128:9bcdf88f62b0	2120	/**
<>	128:9bcdf88f62b0	2121	* @brief Function to help to configure DMA transfer from ADC: retrieve the
<>	128:9bcdf88f62b0	2122	* ADC register address from ADC instance and a list of ADC registers
<>	128:9bcdf88f62b0	2123	* intended to be used (most commonly) with DMA transfer.
<>	128:9bcdf88f62b0	2124	* @note These ADC registers are data registers:
<>	128:9bcdf88f62b0	2125	* when ADC conversion data is available in ADC data registers,
<>	128:9bcdf88f62b0	2126	* ADC generates a DMA transfer request.
<>	128:9bcdf88f62b0	2127	* @note This macro is intended to be used with LL DMA driver, refer to
<>	128:9bcdf88f62b0	2128	* function "LL_DMA_ConfigAddresses()".
<>	128:9bcdf88f62b0	2129	* Example:
<>	128:9bcdf88f62b0	2130	* LL_DMA_ConfigAddresses(DMA1,
<>	128:9bcdf88f62b0	2131	* LL_DMA_CHANNEL_1,
<>	128:9bcdf88f62b0	2132	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<>	128:9bcdf88f62b0	2133	* (uint32_t)&< array or variable >,
<>	128:9bcdf88f62b0	2134	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<>	128:9bcdf88f62b0	2135	* @note For devices with several ADC: in multimode, some devices
<>	128:9bcdf88f62b0	2136	* use a different data register outside of ADC instance scope
<>	128:9bcdf88f62b0	2137	* (common data register). This macro manages this register difference,
<>	128:9bcdf88f62b0	2138	* only ADC instance has to be set as parameter.
<>	128:9bcdf88f62b0	2139	* @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
<>	128:9bcdf88f62b0	2140	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2141	* @param Register This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2142	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<>	128:9bcdf88f62b0	2143	* @retval ADC register address
<>	128:9bcdf88f62b0	2144	*/
<>	128:9bcdf88f62b0	2145	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	128:9bcdf88f62b0	2146	{
<>	128:9bcdf88f62b0	2147	/* Retrieve address of register DR */
<>	128:9bcdf88f62b0	2148	return (uint32_t)&(ADCx->DR);
<>	128:9bcdf88f62b0	2149	}
<>	128:9bcdf88f62b0	2150
<>	128:9bcdf88f62b0	2151	/**
<>	128:9bcdf88f62b0	2152	* @}
<>	128:9bcdf88f62b0	2153	*/
<>	128:9bcdf88f62b0	2154
<>	128:9bcdf88f62b0	2155	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<>	128:9bcdf88f62b0	2156	* @{
<>	128:9bcdf88f62b0	2157	*/
<>	128:9bcdf88f62b0	2158
<>	128:9bcdf88f62b0	2159	/**
<>	128:9bcdf88f62b0	2160	* @brief Set parameter common to several ADC: Clock source and prescaler.
<>	128:9bcdf88f62b0	2161	* @note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
<>	128:9bcdf88f62b0	2162	* Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
<>	128:9bcdf88f62b0	2163	* @note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
<>	128:9bcdf88f62b0	2164	* must be respected:
<>	128:9bcdf88f62b0	2165	* - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
<>	128:9bcdf88f62b0	2166	* - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
<>	128:9bcdf88f62b0	2167	* Refer to reference manual.
<>	128:9bcdf88f62b0	2168	* @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
<>	128:9bcdf88f62b0	2169	* @param ADCxy_COMMON ADC common instance
<>	128:9bcdf88f62b0	2170	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	128:9bcdf88f62b0	2171	* @param CommonClock This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2172	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
<>	128:9bcdf88f62b0	2173	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
<>	128:9bcdf88f62b0	2174	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
<>	128:9bcdf88f62b0	2175	* @retval None
<>	128:9bcdf88f62b0	2176	*/
<>	128:9bcdf88f62b0	2177	__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
<>	128:9bcdf88f62b0	2178	{
<>	128:9bcdf88f62b0	2179	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
<>	128:9bcdf88f62b0	2180	}
<>	128:9bcdf88f62b0	2181
<>	128:9bcdf88f62b0	2182	/**
<>	128:9bcdf88f62b0	2183	* @brief Get parameter common to several ADC: Clock source and prescaler.
<>	128:9bcdf88f62b0	2184	* @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
<>	128:9bcdf88f62b0	2185	* @param ADCxy_COMMON ADC common instance
<>	128:9bcdf88f62b0	2186	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	128:9bcdf88f62b0	2187	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2188	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
<>	128:9bcdf88f62b0	2189	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
<>	128:9bcdf88f62b0	2190	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
<>	128:9bcdf88f62b0	2191	*/
<>	128:9bcdf88f62b0	2192	__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
<>	128:9bcdf88f62b0	2193	{
<>	128:9bcdf88f62b0	2194	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
<>	128:9bcdf88f62b0	2195	}
<>	128:9bcdf88f62b0	2196
<>	128:9bcdf88f62b0	2197	/**
<>	128:9bcdf88f62b0	2198	* @brief Set parameter common to several ADC: measurement path to internal
<>	128:9bcdf88f62b0	2199	* channels (VrefInt, temperature sensor, ...).
<>	128:9bcdf88f62b0	2200	* @note One or several values can be selected.
<>	128:9bcdf88f62b0	2201	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	128:9bcdf88f62b0	2202	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	128:9bcdf88f62b0	2203	* @note Stabilization time of measurement path to internal channel:
<>	128:9bcdf88f62b0	2204	* After enabling internal paths, before starting ADC conversion,
<>	128:9bcdf88f62b0	2205	* a delay is required for internal voltage reference and
<>	128:9bcdf88f62b0	2206	* temperature sensor stabilization time.
<>	128:9bcdf88f62b0	2207	* Refer to device datasheet.
<>	128:9bcdf88f62b0	2208	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<>	128:9bcdf88f62b0	2209	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<>	128:9bcdf88f62b0	2210	* @note ADC internal channel sampling time constraint:
<>	128:9bcdf88f62b0	2211	* For ADC conversion of internal channels,
<>	128:9bcdf88f62b0	2212	* a sampling time minimum value is required.
<>	128:9bcdf88f62b0	2213	* Refer to device datasheet.
<>	128:9bcdf88f62b0	2214	* @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh
<>	128:9bcdf88f62b0	2215	* @param ADCxy_COMMON ADC common instance
<>	128:9bcdf88f62b0	2216	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	128:9bcdf88f62b0	2217	* @param PathInternal This parameter can be a combination of the following values:
<>	128:9bcdf88f62b0	2218	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	128:9bcdf88f62b0	2219	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	128:9bcdf88f62b0	2220	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	128:9bcdf88f62b0	2221	* @retval None
<>	128:9bcdf88f62b0	2222	*/
<>	128:9bcdf88f62b0	2223	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<>	128:9bcdf88f62b0	2224	{
<>	128:9bcdf88f62b0	2225	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE, PathInternal);
<>	128:9bcdf88f62b0	2226	}
<>	128:9bcdf88f62b0	2227
<>	128:9bcdf88f62b0	2228	/**
<>	128:9bcdf88f62b0	2229	* @brief Get parameter common to several ADC: measurement path to internal
<>	128:9bcdf88f62b0	2230	* channels (VrefInt, temperature sensor, ...).
<>	128:9bcdf88f62b0	2231	* @note One or several values can be selected.
<>	128:9bcdf88f62b0	2232	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	128:9bcdf88f62b0	2233	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	128:9bcdf88f62b0	2234	* @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh
<>	128:9bcdf88f62b0	2235	* @param ADCxy_COMMON ADC common instance
<>	128:9bcdf88f62b0	2236	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	128:9bcdf88f62b0	2237	* @retval Returned value can be a combination of the following values:
<>	128:9bcdf88f62b0	2238	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	128:9bcdf88f62b0	2239	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	128:9bcdf88f62b0	2240	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	128:9bcdf88f62b0	2241	*/
<>	128:9bcdf88f62b0	2242	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<>	128:9bcdf88f62b0	2243	{
<>	128:9bcdf88f62b0	2244	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE));
<>	128:9bcdf88f62b0	2245	}
<>	128:9bcdf88f62b0	2246
<>	128:9bcdf88f62b0	2247	/**
<>	128:9bcdf88f62b0	2248	* @}
<>	128:9bcdf88f62b0	2249	*/
<>	128:9bcdf88f62b0	2250
<>	128:9bcdf88f62b0	2251	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<>	128:9bcdf88f62b0	2252	* @{
<>	128:9bcdf88f62b0	2253	*/
<>	128:9bcdf88f62b0	2254
<>	128:9bcdf88f62b0	2255	/**
<>	128:9bcdf88f62b0	2256	* @brief Set ADC resolution.
<>	128:9bcdf88f62b0	2257	* Refer to reference manual for alignments formats
<>	128:9bcdf88f62b0	2258	* dependencies to ADC resolutions.
<>	128:9bcdf88f62b0	2259	* @rmtoll CR1 RES LL_ADC_SetResolution
<>	128:9bcdf88f62b0	2260	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2261	* @param Resolution This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2262	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	2263	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	2264	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	2265	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	2266	* @retval None
<>	128:9bcdf88f62b0	2267	*/
<>	128:9bcdf88f62b0	2268	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<>	128:9bcdf88f62b0	2269	{
<>	128:9bcdf88f62b0	2270	MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
<>	128:9bcdf88f62b0	2271	}
<>	128:9bcdf88f62b0	2272
<>	128:9bcdf88f62b0	2273	/**
<>	128:9bcdf88f62b0	2274	* @brief Get ADC resolution.
<>	128:9bcdf88f62b0	2275	* Refer to reference manual for alignments formats
<>	128:9bcdf88f62b0	2276	* dependencies to ADC resolutions.
<>	128:9bcdf88f62b0	2277	* @rmtoll CR1 RES LL_ADC_GetResolution
<>	128:9bcdf88f62b0	2278	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2279	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2280	* @arg @ref LL_ADC_RESOLUTION_12B
<>	128:9bcdf88f62b0	2281	* @arg @ref LL_ADC_RESOLUTION_10B
<>	128:9bcdf88f62b0	2282	* @arg @ref LL_ADC_RESOLUTION_8B
<>	128:9bcdf88f62b0	2283	* @arg @ref LL_ADC_RESOLUTION_6B
<>	128:9bcdf88f62b0	2284	*/
<>	128:9bcdf88f62b0	2285	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2286	{
<>	128:9bcdf88f62b0	2287	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
<>	128:9bcdf88f62b0	2288	}
<>	128:9bcdf88f62b0	2289
<>	128:9bcdf88f62b0	2290	/**
<>	128:9bcdf88f62b0	2291	* @brief Set ADC conversion data alignment.
<>	128:9bcdf88f62b0	2292	* @note Refer to reference manual for alignments formats
<>	128:9bcdf88f62b0	2293	* dependencies to ADC resolutions.
<>	128:9bcdf88f62b0	2294	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	128:9bcdf88f62b0	2295	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2296	* @param DataAlignment This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2297	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	128:9bcdf88f62b0	2298	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	128:9bcdf88f62b0	2299	* @retval None
<>	128:9bcdf88f62b0	2300	*/
<>	128:9bcdf88f62b0	2301	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<>	128:9bcdf88f62b0	2302	{
<>	128:9bcdf88f62b0	2303	MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
<>	128:9bcdf88f62b0	2304	}
<>	128:9bcdf88f62b0	2305
<>	128:9bcdf88f62b0	2306	/**
<>	128:9bcdf88f62b0	2307	* @brief Get ADC conversion data alignment.
<>	128:9bcdf88f62b0	2308	* @note Refer to reference manual for alignments formats
<>	128:9bcdf88f62b0	2309	* dependencies to ADC resolutions.
<>	128:9bcdf88f62b0	2310	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	128:9bcdf88f62b0	2311	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2312	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2313	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	128:9bcdf88f62b0	2314	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	128:9bcdf88f62b0	2315	*/
<>	128:9bcdf88f62b0	2316	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2317	{
<>	128:9bcdf88f62b0	2318	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
<>	128:9bcdf88f62b0	2319	}
<>	128:9bcdf88f62b0	2320
<>	128:9bcdf88f62b0	2321	/**
<>	128:9bcdf88f62b0	2322	* @brief Set ADC low power mode auto wait.
<>	128:9bcdf88f62b0	2323	* @note Description of ADC low power modes:
<>	128:9bcdf88f62b0	2324	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	128:9bcdf88f62b0	2325	* ADC conversions occurrences are limited to the minimum necessary
<>	128:9bcdf88f62b0	2326	* in order to reduce power consumption.
<>	128:9bcdf88f62b0	2327	* New ADC conversion starts only when the previous
<>	128:9bcdf88f62b0	2328	* unitary conversion data (for ADC group regular)
<>	128:9bcdf88f62b0	2329	* or previous sequence conversions data (for ADC group injected)
<>	128:9bcdf88f62b0	2330	* has been retrieved by user software.
<>	128:9bcdf88f62b0	2331	* In the meantime, ADC remains idle: does not performs any
<>	128:9bcdf88f62b0	2332	* other conversion.
<>	128:9bcdf88f62b0	2333	* This mode allows to automatically adapt the ADC conversions
<>	128:9bcdf88f62b0	2334	* triggers to the speed of the software that reads the data.
<>	128:9bcdf88f62b0	2335	* Moreover, this avoids risk of overrun for low frequency
<>	128:9bcdf88f62b0	2336	* applications.
<>	128:9bcdf88f62b0	2337	* How to use this low power mode:
<>	128:9bcdf88f62b0	2338	* - Do not use with interruption or DMA since these modes
<>	128:9bcdf88f62b0	2339	* have to clear immediately the EOC flag to free the
<>	128:9bcdf88f62b0	2340	* IRQ vector sequencer.
<>	128:9bcdf88f62b0	2341	* - Do use with polling: 1. Start conversion,
<>	128:9bcdf88f62b0	2342	* 2. Later on, when conversion data is needed: poll for end of
<>	128:9bcdf88f62b0	2343	* conversion to ensure that conversion is completed and
<>	128:9bcdf88f62b0	2344	* retrieve ADC conversion data. This will trig another
<>	128:9bcdf88f62b0	2345	* ADC conversion start.
<>	128:9bcdf88f62b0	2346	* - ADC low power mode "auto power-off":
<>	128:9bcdf88f62b0	2347	* refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
<>	128:9bcdf88f62b0	2348	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	128:9bcdf88f62b0	2349	* is corresponding to previous ADC conversion start, independently
<>	128:9bcdf88f62b0	2350	* of delay during which ADC was idle.
<>	128:9bcdf88f62b0	2351	* Therefore, the ADC conversion data may be outdated: does not
<>	128:9bcdf88f62b0	2352	* correspond to the current voltage level on the selected
<>	128:9bcdf88f62b0	2353	* ADC channel.
<>	128:9bcdf88f62b0	2354	* @rmtoll CR2 DELS LL_ADC_SetLowPowerModeAutoWait
<>	128:9bcdf88f62b0	2355	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2356	* @param LowPowerModeAutoWait This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2357	* @arg @ref LL_ADC_LP_AUTOWAIT_NONE
<>	128:9bcdf88f62b0	2358	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	128:9bcdf88f62b0	2359	* @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2360	* @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2361	* @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2362	* @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2363	* @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2364	* @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2365	* @retval None
<>	128:9bcdf88f62b0	2366	*/
<>	128:9bcdf88f62b0	2367	__STATIC_INLINE void LL_ADC_SetLowPowerModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoWait)
<>	128:9bcdf88f62b0	2368	{
<>	128:9bcdf88f62b0	2369	MODIFY_REG(ADCx->CR2, ADC_CR2_DELS, LowPowerModeAutoWait);
<>	128:9bcdf88f62b0	2370	}
<>	128:9bcdf88f62b0	2371
<>	128:9bcdf88f62b0	2372	/**
<>	128:9bcdf88f62b0	2373	* @brief Get ADC low power mode auto wait.
<>	128:9bcdf88f62b0	2374	* @note Description of ADC low power modes:
<>	128:9bcdf88f62b0	2375	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	128:9bcdf88f62b0	2376	* ADC conversions occurrences are limited to the minimum necessary
<>	128:9bcdf88f62b0	2377	* in order to reduce power consumption.
<>	128:9bcdf88f62b0	2378	* New ADC conversion starts only when the previous
<>	128:9bcdf88f62b0	2379	* unitary conversion data (for ADC group regular)
<>	128:9bcdf88f62b0	2380	* or previous sequence conversions data (for ADC group injected)
<>	128:9bcdf88f62b0	2381	* has been retrieved by user software.
<>	128:9bcdf88f62b0	2382	* In the meantime, ADC remains idle: does not performs any
<>	128:9bcdf88f62b0	2383	* other conversion.
<>	128:9bcdf88f62b0	2384	* This mode allows to automatically adapt the ADC conversions
<>	128:9bcdf88f62b0	2385	* triggers to the speed of the software that reads the data.
<>	128:9bcdf88f62b0	2386	* Moreover, this avoids risk of overrun for low frequency
<>	128:9bcdf88f62b0	2387	* applications.
<>	128:9bcdf88f62b0	2388	* How to use this low power mode:
<>	128:9bcdf88f62b0	2389	* - Do not use with interruption or DMA since these modes
<>	128:9bcdf88f62b0	2390	* have to clear immediately the EOC flag to free the
<>	128:9bcdf88f62b0	2391	* IRQ vector sequencer.
<>	128:9bcdf88f62b0	2392	* - Do use with polling: 1. Start conversion,
<>	128:9bcdf88f62b0	2393	* 2. Later on, when conversion data is needed: poll for end of
<>	128:9bcdf88f62b0	2394	* conversion to ensure that conversion is completed and
<>	128:9bcdf88f62b0	2395	* retrieve ADC conversion data. This will trig another
<>	128:9bcdf88f62b0	2396	* ADC conversion start.
<>	128:9bcdf88f62b0	2397	* - ADC low power mode "auto power-off":
<>	128:9bcdf88f62b0	2398	* refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
<>	128:9bcdf88f62b0	2399	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	128:9bcdf88f62b0	2400	* is corresponding to previous ADC conversion start, independently
<>	128:9bcdf88f62b0	2401	* of delay during which ADC was idle.
<>	128:9bcdf88f62b0	2402	* Therefore, the ADC conversion data may be outdated: does not
<>	128:9bcdf88f62b0	2403	* correspond to the current voltage level on the selected
<>	128:9bcdf88f62b0	2404	* ADC channel.
<>	128:9bcdf88f62b0	2405	* @rmtoll CR2 DELS LL_ADC_GetLowPowerModeAutoWait
<>	128:9bcdf88f62b0	2406	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2407	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2408	* @arg @ref LL_ADC_LP_AUTOWAIT_NONE
<>	128:9bcdf88f62b0	2409	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	128:9bcdf88f62b0	2410	* @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2411	* @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2412	* @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2413	* @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2414	* @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2415	* @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
<>	128:9bcdf88f62b0	2416	*/
<>	128:9bcdf88f62b0	2417	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoWait(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2418	{
<>	128:9bcdf88f62b0	2419	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DELS));
<>	128:9bcdf88f62b0	2420	}
<>	128:9bcdf88f62b0	2421
<>	128:9bcdf88f62b0	2422	/**
<>	128:9bcdf88f62b0	2423	* @brief Set ADC low power mode auto power-off.
<>	128:9bcdf88f62b0	2424	* @note Description of ADC low power modes:
<>	128:9bcdf88f62b0	2425	* - ADC low power mode "auto wait":
<>	128:9bcdf88f62b0	2426	* refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
<>	128:9bcdf88f62b0	2427	* - ADC low power mode "auto power-off":
<>	128:9bcdf88f62b0	2428	* the ADC automatically powers-off after a conversion and
<>	128:9bcdf88f62b0	2429	* automatically wakes up when a new conversion is triggered
<>	128:9bcdf88f62b0	2430	* (with startup time between trigger and start of sampling).
<>	128:9bcdf88f62b0	2431	* This feature can be combined with low power mode "auto wait".
<>	128:9bcdf88f62b0	2432	* @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n
<>	128:9bcdf88f62b0	2433	* CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff
<>	128:9bcdf88f62b0	2434	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2435	* @param LowPowerModeAutoPowerOff This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2436	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
<>	128:9bcdf88f62b0	2437	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
<>	128:9bcdf88f62b0	2438	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
<>	128:9bcdf88f62b0	2439	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
<>	128:9bcdf88f62b0	2440	* @retval None
<>	128:9bcdf88f62b0	2441	*/
<>	128:9bcdf88f62b0	2442	__STATIC_INLINE void LL_ADC_SetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoPowerOff)
<>	128:9bcdf88f62b0	2443	{
<>	128:9bcdf88f62b0	2444	MODIFY_REG(ADCx->CR1, (ADC_CR1_PDI \| ADC_CR1_PDD), LowPowerModeAutoPowerOff);
<>	128:9bcdf88f62b0	2445	}
<>	128:9bcdf88f62b0	2446
<>	128:9bcdf88f62b0	2447	/**
<>	128:9bcdf88f62b0	2448	* @brief Get ADC low power mode auto power-off.
<>	128:9bcdf88f62b0	2449	* @note Description of ADC low power modes:
<>	128:9bcdf88f62b0	2450	* - ADC low power mode "auto wait":
<>	128:9bcdf88f62b0	2451	* refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
<>	128:9bcdf88f62b0	2452	* - ADC low power mode "auto power-off":
<>	128:9bcdf88f62b0	2453	* the ADC automatically powers-off after a conversion and
<>	128:9bcdf88f62b0	2454	* automatically wakes up when a new conversion is triggered
<>	128:9bcdf88f62b0	2455	* (with startup time between trigger and start of sampling).
<>	128:9bcdf88f62b0	2456	* This feature can be combined with low power mode "auto wait".
<>	128:9bcdf88f62b0	2457	* @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n
<>	128:9bcdf88f62b0	2458	* CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff
<>	128:9bcdf88f62b0	2459	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2460	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2461	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
<>	128:9bcdf88f62b0	2462	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
<>	128:9bcdf88f62b0	2463	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
<>	128:9bcdf88f62b0	2464	* @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
<>	128:9bcdf88f62b0	2465	*/
<>	128:9bcdf88f62b0	2466	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2467	{
<>	128:9bcdf88f62b0	2468	return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_PDI \| ADC_CR1_PDD)));
<>	128:9bcdf88f62b0	2469	}
<>	128:9bcdf88f62b0	2470
<>	128:9bcdf88f62b0	2471	/**
<>	128:9bcdf88f62b0	2472	* @brief Set ADC sequencers scan mode, for all ADC groups
<>	128:9bcdf88f62b0	2473	* (group regular, group injected).
<>	128:9bcdf88f62b0	2474	* @note According to sequencers scan mode :
<>	128:9bcdf88f62b0	2475	* - If disabled: ADC conversion is performed in unitary conversion
<>	128:9bcdf88f62b0	2476	* mode (one channel converted, that defined in rank 1).
<>	128:9bcdf88f62b0	2477	* Configuration of sequencers of all ADC groups
<>	128:9bcdf88f62b0	2478	* (sequencer scan length, ...) is discarded: equivalent to
<>	128:9bcdf88f62b0	2479	* scan length of 1 rank.
<>	128:9bcdf88f62b0	2480	* - If enabled: ADC conversions are performed in sequence conversions
<>	128:9bcdf88f62b0	2481	* mode, according to configuration of sequencers of
<>	128:9bcdf88f62b0	2482	* each ADC group (sequencer scan length, ...).
<>	128:9bcdf88f62b0	2483	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	128:9bcdf88f62b0	2484	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	128:9bcdf88f62b0	2485	* @note On this STM32 serie, setting of this feature is conditioned to
<>	128:9bcdf88f62b0	2486	* ADC state:
<>	128:9bcdf88f62b0	2487	* ADC must be disabled or enabled without conversion on going
<>	128:9bcdf88f62b0	2488	* on either groups regular or injected.
<>	128:9bcdf88f62b0	2489	* @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
<>	128:9bcdf88f62b0	2490	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2491	* @param ScanMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2492	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	2493	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	128:9bcdf88f62b0	2494	* @retval None
<>	128:9bcdf88f62b0	2495	*/
<>	128:9bcdf88f62b0	2496	__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
<>	128:9bcdf88f62b0	2497	{
<>	128:9bcdf88f62b0	2498	MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
<>	128:9bcdf88f62b0	2499	}
<>	128:9bcdf88f62b0	2500
<>	128:9bcdf88f62b0	2501	/**
<>	128:9bcdf88f62b0	2502	* @brief Get ADC sequencers scan mode, for all ADC groups
<>	128:9bcdf88f62b0	2503	* (group regular, group injected).
<>	128:9bcdf88f62b0	2504	* @note According to sequencers scan mode :
<>	128:9bcdf88f62b0	2505	* - If disabled: ADC conversion is performed in unitary conversion
<>	128:9bcdf88f62b0	2506	* mode (one channel converted, that defined in rank 1).
<>	128:9bcdf88f62b0	2507	* Configuration of sequencers of all ADC groups
<>	128:9bcdf88f62b0	2508	* (sequencer scan length, ...) is discarded: equivalent to
<>	128:9bcdf88f62b0	2509	* scan length of 1 rank.
<>	128:9bcdf88f62b0	2510	* - If enabled: ADC conversions are performed in sequence conversions
<>	128:9bcdf88f62b0	2511	* mode, according to configuration of sequencers of
<>	128:9bcdf88f62b0	2512	* each ADC group (sequencer scan length, ...).
<>	128:9bcdf88f62b0	2513	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	128:9bcdf88f62b0	2514	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	128:9bcdf88f62b0	2515	* @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
<>	128:9bcdf88f62b0	2516	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2517	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2518	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	2519	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	128:9bcdf88f62b0	2520	*/
<>	128:9bcdf88f62b0	2521	__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2522	{
<>	128:9bcdf88f62b0	2523	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
<>	128:9bcdf88f62b0	2524	}
<>	128:9bcdf88f62b0	2525
<>	128:9bcdf88f62b0	2526	#if defined(ADC_CR2_CFG)
<>	128:9bcdf88f62b0	2527	/**
<>	128:9bcdf88f62b0	2528	* @brief Set ADC channels bank.
<>	128:9bcdf88f62b0	2529	* @note Bank selected applies to ADC scope, on all channels
<>	128:9bcdf88f62b0	2530	* (independently of channel mapped on ADC group regular
<>	128:9bcdf88f62b0	2531	* or group injected).
<>	128:9bcdf88f62b0	2532	* @note Banks availability depends on devices categories.
<>	128:9bcdf88f62b0	2533	* @note On this STM32 serie, setting of this feature is conditioned to
<>	128:9bcdf88f62b0	2534	* ADC state:
<>	128:9bcdf88f62b0	2535	* ADC must be disabled or enabled without conversion on going
<>	128:9bcdf88f62b0	2536	* on either groups regular or injected.
<>	128:9bcdf88f62b0	2537	* @rmtoll CR2 ADC_CFG LL_ADC_SetChannelsBank
<>	128:9bcdf88f62b0	2538	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2539	* @param ChannelsBank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2540	* @arg @ref LL_ADC_CHANNELS_BANK_A
<>	128:9bcdf88f62b0	2541	* @arg @ref LL_ADC_CHANNELS_BANK_B
<>	128:9bcdf88f62b0	2542	* @retval None
<>	128:9bcdf88f62b0	2543	*/
<>	128:9bcdf88f62b0	2544	__STATIC_INLINE void LL_ADC_SetChannelsBank(ADC_TypeDef *ADCx, uint32_t ChannelsBank)
<>	128:9bcdf88f62b0	2545	{
<>	128:9bcdf88f62b0	2546	MODIFY_REG(ADCx->CR2, ADC_CR2_CFG, ChannelsBank);
<>	128:9bcdf88f62b0	2547	}
<>	128:9bcdf88f62b0	2548
<>	128:9bcdf88f62b0	2549	/**
<>	128:9bcdf88f62b0	2550	* @brief Get ADC channels bank.
<>	128:9bcdf88f62b0	2551	* @note Bank selected applies to ADC scope, on all channels
<>	128:9bcdf88f62b0	2552	* (independently of channel mapped on ADC group regular
<>	128:9bcdf88f62b0	2553	* or group injected).
<>	128:9bcdf88f62b0	2554	* @note Banks availability depends on devices categories.
<>	128:9bcdf88f62b0	2555	* @rmtoll CR2 ADC_CFG LL_ADC_GetChannelsBank
<>	128:9bcdf88f62b0	2556	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2557	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2558	* @arg @ref LL_ADC_CHANNELS_BANK_A
<>	128:9bcdf88f62b0	2559	* @arg @ref LL_ADC_CHANNELS_BANK_B
<>	128:9bcdf88f62b0	2560	*/
<>	128:9bcdf88f62b0	2561	__STATIC_INLINE uint32_t LL_ADC_GetChannelsBank(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2562	{
<>	128:9bcdf88f62b0	2563	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CFG));
<>	128:9bcdf88f62b0	2564	}
<>	128:9bcdf88f62b0	2565	#endif
<>	128:9bcdf88f62b0	2566
<>	128:9bcdf88f62b0	2567	/**
<>	128:9bcdf88f62b0	2568	* @}
<>	128:9bcdf88f62b0	2569	*/
<>	128:9bcdf88f62b0	2570
<>	128:9bcdf88f62b0	2571	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<>	128:9bcdf88f62b0	2572	* @{
<>	128:9bcdf88f62b0	2573	*/
<>	128:9bcdf88f62b0	2574
<>	128:9bcdf88f62b0	2575	/**
<>	128:9bcdf88f62b0	2576	* @brief Set ADC group regular conversion trigger source:
<>	128:9bcdf88f62b0	2577	* internal (SW start) or from external IP (timer event,
<>	128:9bcdf88f62b0	2578	* external interrupt line).
<>	128:9bcdf88f62b0	2579	* @note On this STM32 serie, setting of external trigger edge is performed
<>	128:9bcdf88f62b0	2580	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	128:9bcdf88f62b0	2581	* @note Availability of parameters of trigger sources from timer
<>	128:9bcdf88f62b0	2582	* depends on timers availability on the selected device.
<>	128:9bcdf88f62b0	2583	* @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
<>	128:9bcdf88f62b0	2584	* CR2 EXTEN LL_ADC_REG_SetTriggerSource
<>	128:9bcdf88f62b0	2585	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2586	* @param TriggerSource This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2587	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	128:9bcdf88f62b0	2588	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	128:9bcdf88f62b0	2589	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
<>	128:9bcdf88f62b0	2590	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	128:9bcdf88f62b0	2591	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	128:9bcdf88f62b0	2592	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
<>	128:9bcdf88f62b0	2593	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
<>	128:9bcdf88f62b0	2594	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	128:9bcdf88f62b0	2595	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	128:9bcdf88f62b0	2596	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	128:9bcdf88f62b0	2597	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
<>	128:9bcdf88f62b0	2598	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
<>	128:9bcdf88f62b0	2599	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	128:9bcdf88f62b0	2600	* @retval None
<>	128:9bcdf88f62b0	2601	*/
<>	128:9bcdf88f62b0	2602	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	128:9bcdf88f62b0	2603	{
<>	128:9bcdf88f62b0	2604	/* Note: On this STM32 serie, ADC group regular external trigger edge */
<>	128:9bcdf88f62b0	2605	/* is used to perform a ADC conversion start. */
<>	128:9bcdf88f62b0	2606	/* This function does not set external trigger edge. */
<>	128:9bcdf88f62b0	2607	/* This feature is set using function */
<>	128:9bcdf88f62b0	2608	/* @ref LL_ADC_REG_StartConversionExtTrig(). */
<>	128:9bcdf88f62b0	2609	MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
<>	128:9bcdf88f62b0	2610	}
<>	128:9bcdf88f62b0	2611
<>	128:9bcdf88f62b0	2612	/**
<>	128:9bcdf88f62b0	2613	* @brief Get ADC group regular conversion trigger source:
<>	128:9bcdf88f62b0	2614	* internal (SW start) or from external IP (timer event,
<>	128:9bcdf88f62b0	2615	* external interrupt line).
<>	128:9bcdf88f62b0	2616	* @note To determine whether group regular trigger source is
<>	128:9bcdf88f62b0	2617	* internal (SW start) or external, without detail
<>	128:9bcdf88f62b0	2618	* of which peripheral is selected as external trigger,
<>	128:9bcdf88f62b0	2619	* (equivalent to
<>	128:9bcdf88f62b0	2620	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<>	128:9bcdf88f62b0	2621	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<>	128:9bcdf88f62b0	2622	* @note Availability of parameters of trigger sources from timer
<>	128:9bcdf88f62b0	2623	* depends on timers availability on the selected device.
<>	128:9bcdf88f62b0	2624	* @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
<>	128:9bcdf88f62b0	2625	* CR2 EXTEN LL_ADC_REG_GetTriggerSource
<>	128:9bcdf88f62b0	2626	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2627	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2628	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	128:9bcdf88f62b0	2629	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	128:9bcdf88f62b0	2630	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
<>	128:9bcdf88f62b0	2631	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	128:9bcdf88f62b0	2632	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	128:9bcdf88f62b0	2633	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
<>	128:9bcdf88f62b0	2634	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
<>	128:9bcdf88f62b0	2635	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	128:9bcdf88f62b0	2636	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	128:9bcdf88f62b0	2637	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	128:9bcdf88f62b0	2638	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
<>	128:9bcdf88f62b0	2639	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
<>	128:9bcdf88f62b0	2640	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	128:9bcdf88f62b0	2641	*/
<>	128:9bcdf88f62b0	2642	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2643	{
<>	128:9bcdf88f62b0	2644	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL \| ADC_CR2_EXTEN);
<>	128:9bcdf88f62b0	2645
<>	128:9bcdf88f62b0	2646	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	128:9bcdf88f62b0	2647	/* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
<>	128:9bcdf88f62b0	2648	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	128:9bcdf88f62b0	2649
<>	128:9bcdf88f62b0	2650	/* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
<>	128:9bcdf88f62b0	2651	/* to match with triggers literals definition. */
<>	128:9bcdf88f62b0	2652	return ((TriggerSource
<>	128:9bcdf88f62b0	2653	& (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
<>	128:9bcdf88f62b0	2654	\| ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
<>	128:9bcdf88f62b0	2655	);
<>	128:9bcdf88f62b0	2656	}
<>	128:9bcdf88f62b0	2657
<>	128:9bcdf88f62b0	2658	/**
<>	128:9bcdf88f62b0	2659	* @brief Get ADC group regular conversion trigger source internal (SW start)
<>	128:9bcdf88f62b0	2660	or external.
<>	128:9bcdf88f62b0	2661	* @note In case of group regular trigger source set to external trigger,
<>	128:9bcdf88f62b0	2662	* to determine which peripheral is selected as external trigger,
<>	128:9bcdf88f62b0	2663	* use function @ref LL_ADC_REG_GetTriggerSource().
<>	128:9bcdf88f62b0	2664	* @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<>	128:9bcdf88f62b0	2665	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2666	* @retval Value "0" if trigger source external trigger
<>	128:9bcdf88f62b0	2667	* Value "1" if trigger source SW start.
<>	128:9bcdf88f62b0	2668	*/
<>	128:9bcdf88f62b0	2669	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2670	{
<>	128:9bcdf88f62b0	2671	return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
<>	128:9bcdf88f62b0	2672	}
<>	128:9bcdf88f62b0	2673
<>	128:9bcdf88f62b0	2674	/**
<>	128:9bcdf88f62b0	2675	* @brief Get ADC group regular conversion trigger polarity.
<>	128:9bcdf88f62b0	2676	* @note Applicable only for trigger source set to external trigger.
<>	128:9bcdf88f62b0	2677	* @note On this STM32 serie, setting of external trigger edge is performed
<>	128:9bcdf88f62b0	2678	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	128:9bcdf88f62b0	2679	* @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
<>	128:9bcdf88f62b0	2680	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2681	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2682	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	128:9bcdf88f62b0	2683	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	128:9bcdf88f62b0	2684	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	128:9bcdf88f62b0	2685	*/
<>	128:9bcdf88f62b0	2686	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2687	{
<>	128:9bcdf88f62b0	2688	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
<>	128:9bcdf88f62b0	2689	}
<>	128:9bcdf88f62b0	2690
<>	128:9bcdf88f62b0	2691
<>	128:9bcdf88f62b0	2692	/**
<>	128:9bcdf88f62b0	2693	* @brief Set ADC group regular sequencer length and scan direction.
<>	128:9bcdf88f62b0	2694	* @note Description of ADC group regular sequencer features:
<>	128:9bcdf88f62b0	2695	* - For devices with sequencer fully configurable
<>	128:9bcdf88f62b0	2696	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	128:9bcdf88f62b0	2697	* sequencer length and each rank affectation to a channel
<>	128:9bcdf88f62b0	2698	* are configurable.
<>	128:9bcdf88f62b0	2699	* This function performs configuration of:
<>	128:9bcdf88f62b0	2700	* - Sequence length: Number of ranks in the scan sequence.
<>	128:9bcdf88f62b0	2701	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	2702	* scan direction is forward (from rank 1 to rank n).
<>	128:9bcdf88f62b0	2703	* Sequencer ranks are selected using
<>	128:9bcdf88f62b0	2704	* function "LL_ADC_REG_SetSequencerRanks()".
<>	128:9bcdf88f62b0	2705	* - For devices with sequencer not fully configurable
<>	128:9bcdf88f62b0	2706	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	128:9bcdf88f62b0	2707	* sequencer length and each rank affectation to a channel
<>	128:9bcdf88f62b0	2708	* are defined by channel number.
<>	128:9bcdf88f62b0	2709	* This function performs configuration of:
<>	128:9bcdf88f62b0	2710	* - Sequence length: Number of ranks in the scan sequence is
<>	128:9bcdf88f62b0	2711	* defined by number of channels set in the sequence,
<>	128:9bcdf88f62b0	2712	* rank of each channel is fixed by channel HW number.
<>	128:9bcdf88f62b0	2713	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	128:9bcdf88f62b0	2714	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	2715	* scan direction is forward (from lowest channel number to
<>	128:9bcdf88f62b0	2716	* highest channel number).
<>	128:9bcdf88f62b0	2717	* Sequencer ranks are selected using
<>	128:9bcdf88f62b0	2718	* function "LL_ADC_REG_SetSequencerChannels()".
<>	128:9bcdf88f62b0	2719	* @note On this STM32 serie, group regular sequencer configuration
<>	128:9bcdf88f62b0	2720	* is conditioned to ADC instance sequencer mode.
<>	128:9bcdf88f62b0	2721	* If ADC instance sequencer mode is disabled, sequencers of
<>	128:9bcdf88f62b0	2722	* all groups (group regular, group injected) can be configured
<>	128:9bcdf88f62b0	2723	* but their execution is disabled (limited to rank 1).
<>	128:9bcdf88f62b0	2724	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	128:9bcdf88f62b0	2725	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	128:9bcdf88f62b0	2726	* ADC conversion on only 1 channel.
<>	128:9bcdf88f62b0	2727	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	128:9bcdf88f62b0	2728	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2729	* @param SequencerNbRanks This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2730	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	2731	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	128:9bcdf88f62b0	2732	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	128:9bcdf88f62b0	2733	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	128:9bcdf88f62b0	2734	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	128:9bcdf88f62b0	2735	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	128:9bcdf88f62b0	2736	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	128:9bcdf88f62b0	2737	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	128:9bcdf88f62b0	2738	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	128:9bcdf88f62b0	2739	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	128:9bcdf88f62b0	2740	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	128:9bcdf88f62b0	2741	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	128:9bcdf88f62b0	2742	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	128:9bcdf88f62b0	2743	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	128:9bcdf88f62b0	2744	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	128:9bcdf88f62b0	2745	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	128:9bcdf88f62b0	2746	* @retval None
<>	128:9bcdf88f62b0	2747	*/
<>	128:9bcdf88f62b0	2748	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	128:9bcdf88f62b0	2749	{
<>	128:9bcdf88f62b0	2750	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
<>	128:9bcdf88f62b0	2751	}
<>	128:9bcdf88f62b0	2752
<>	128:9bcdf88f62b0	2753	/**
<>	128:9bcdf88f62b0	2754	* @brief Get ADC group regular sequencer length and scan direction.
<>	128:9bcdf88f62b0	2755	* @note Description of ADC group regular sequencer features:
<>	128:9bcdf88f62b0	2756	* - For devices with sequencer fully configurable
<>	128:9bcdf88f62b0	2757	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	128:9bcdf88f62b0	2758	* sequencer length and each rank affectation to a channel
<>	128:9bcdf88f62b0	2759	* are configurable.
<>	128:9bcdf88f62b0	2760	* This function retrieves:
<>	128:9bcdf88f62b0	2761	* - Sequence length: Number of ranks in the scan sequence.
<>	128:9bcdf88f62b0	2762	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	2763	* scan direction is forward (from rank 1 to rank n).
<>	128:9bcdf88f62b0	2764	* Sequencer ranks are selected using
<>	128:9bcdf88f62b0	2765	* function "LL_ADC_REG_SetSequencerRanks()".
<>	128:9bcdf88f62b0	2766	* - For devices with sequencer not fully configurable
<>	128:9bcdf88f62b0	2767	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	128:9bcdf88f62b0	2768	* sequencer length and each rank affectation to a channel
<>	128:9bcdf88f62b0	2769	* are defined by channel number.
<>	128:9bcdf88f62b0	2770	* This function retrieves:
<>	128:9bcdf88f62b0	2771	* - Sequence length: Number of ranks in the scan sequence is
<>	128:9bcdf88f62b0	2772	* defined by number of channels set in the sequence,
<>	128:9bcdf88f62b0	2773	* rank of each channel is fixed by channel HW number.
<>	128:9bcdf88f62b0	2774	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	128:9bcdf88f62b0	2775	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	2776	* scan direction is forward (from lowest channel number to
<>	128:9bcdf88f62b0	2777	* highest channel number).
<>	128:9bcdf88f62b0	2778	* Sequencer ranks are selected using
<>	128:9bcdf88f62b0	2779	* function "LL_ADC_REG_SetSequencerChannels()".
<>	128:9bcdf88f62b0	2780	* @note On this STM32 serie, group regular sequencer configuration
<>	128:9bcdf88f62b0	2781	* is conditioned to ADC instance sequencer mode.
<>	128:9bcdf88f62b0	2782	* If ADC instance sequencer mode is disabled, sequencers of
<>	128:9bcdf88f62b0	2783	* all groups (group regular, group injected) can be configured
<>	128:9bcdf88f62b0	2784	* but their execution is disabled (limited to rank 1).
<>	128:9bcdf88f62b0	2785	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	128:9bcdf88f62b0	2786	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	128:9bcdf88f62b0	2787	* ADC conversion on only 1 channel.
<>	128:9bcdf88f62b0	2788	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	128:9bcdf88f62b0	2789	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2790	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2791	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	2792	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	128:9bcdf88f62b0	2793	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	128:9bcdf88f62b0	2794	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	128:9bcdf88f62b0	2795	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	128:9bcdf88f62b0	2796	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	128:9bcdf88f62b0	2797	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	128:9bcdf88f62b0	2798	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	128:9bcdf88f62b0	2799	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	128:9bcdf88f62b0	2800	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	128:9bcdf88f62b0	2801	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	128:9bcdf88f62b0	2802	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	128:9bcdf88f62b0	2803	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	128:9bcdf88f62b0	2804	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	128:9bcdf88f62b0	2805	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	128:9bcdf88f62b0	2806	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	128:9bcdf88f62b0	2807	*/
<>	128:9bcdf88f62b0	2808	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2809	{
<>	128:9bcdf88f62b0	2810	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
<>	128:9bcdf88f62b0	2811	}
<>	128:9bcdf88f62b0	2812
<>	128:9bcdf88f62b0	2813	/**
<>	128:9bcdf88f62b0	2814	* @brief Set ADC group regular sequencer discontinuous mode:
<>	128:9bcdf88f62b0	2815	* sequence subdivided and scan conversions interrupted every selected
<>	128:9bcdf88f62b0	2816	* number of ranks.
<>	128:9bcdf88f62b0	2817	* @note It is not possible to enable both ADC group regular
<>	128:9bcdf88f62b0	2818	* continuous mode and sequencer discontinuous mode.
<>	128:9bcdf88f62b0	2819	* @note It is not possible to enable both ADC auto-injected mode
<>	128:9bcdf88f62b0	2820	* and ADC group regular sequencer discontinuous mode.
<>	128:9bcdf88f62b0	2821	* @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
<>	128:9bcdf88f62b0	2822	* CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
<>	128:9bcdf88f62b0	2823	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2824	* @param SeqDiscont This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2825	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	128:9bcdf88f62b0	2826	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	128:9bcdf88f62b0	2827	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	128:9bcdf88f62b0	2828	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	128:9bcdf88f62b0	2829	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	128:9bcdf88f62b0	2830	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	128:9bcdf88f62b0	2831	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	128:9bcdf88f62b0	2832	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	128:9bcdf88f62b0	2833	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	128:9bcdf88f62b0	2834	* @retval None
<>	128:9bcdf88f62b0	2835	*/
<>	128:9bcdf88f62b0	2836	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	128:9bcdf88f62b0	2837	{
<>	128:9bcdf88f62b0	2838	MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM, SeqDiscont);
<>	128:9bcdf88f62b0	2839	}
<>	128:9bcdf88f62b0	2840
<>	128:9bcdf88f62b0	2841	/**
<>	128:9bcdf88f62b0	2842	* @brief Get ADC group regular sequencer discontinuous mode:
<>	128:9bcdf88f62b0	2843	* sequence subdivided and scan conversions interrupted every selected
<>	128:9bcdf88f62b0	2844	* number of ranks.
<>	128:9bcdf88f62b0	2845	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
<>	128:9bcdf88f62b0	2846	* CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
<>	128:9bcdf88f62b0	2847	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2848	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	2849	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	128:9bcdf88f62b0	2850	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	128:9bcdf88f62b0	2851	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	128:9bcdf88f62b0	2852	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	128:9bcdf88f62b0	2853	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	128:9bcdf88f62b0	2854	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	128:9bcdf88f62b0	2855	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	128:9bcdf88f62b0	2856	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	128:9bcdf88f62b0	2857	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	128:9bcdf88f62b0	2858	*/
<>	128:9bcdf88f62b0	2859	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	2860	{
<>	128:9bcdf88f62b0	2861	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM));
<>	128:9bcdf88f62b0	2862	}
<>	128:9bcdf88f62b0	2863
<>	128:9bcdf88f62b0	2864	/**
<>	128:9bcdf88f62b0	2865	* @brief Set ADC group regular sequence: channel on the selected
<>	128:9bcdf88f62b0	2866	* scan sequence rank.
<>	128:9bcdf88f62b0	2867	* @note This function performs configuration of:
<>	128:9bcdf88f62b0	2868	* - Channels ordering into each rank of scan sequence:
<>	128:9bcdf88f62b0	2869	* whatever channel can be placed into whatever rank.
<>	128:9bcdf88f62b0	2870	* @note On this STM32 serie, ADC group regular sequencer is
<>	128:9bcdf88f62b0	2871	* fully configurable: sequencer length and each rank
<>	128:9bcdf88f62b0	2872	* affectation to a channel are configurable.
<>	128:9bcdf88f62b0	2873	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	128:9bcdf88f62b0	2874	* @note Depending on devices and packages, some channels may not be available.
<>	128:9bcdf88f62b0	2875	* Refer to device datasheet for channels availability.
<>	128:9bcdf88f62b0	2876	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	128:9bcdf88f62b0	2877	* TempSensor, ...), measurement paths to internal channels must be
<>	128:9bcdf88f62b0	2878	* enabled separately.
<>	128:9bcdf88f62b0	2879	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	128:9bcdf88f62b0	2880	* @rmtoll SQR5 SQ1 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2881	* SQR5 SQ2 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2882	* SQR5 SQ3 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2883	* SQR5 SQ4 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2884	* SQR5 SQ5 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2885	* SQR5 SQ6 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2886	* SQR4 SQ7 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2887	* SQR4 SQ8 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2888	* SQR4 SQ9 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2889	* SQR4 SQ10 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2890	* SQR4 SQ11 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2891	* SQR4 SQ12 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2892	* SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2893	* SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2894	* SQR3 SQ15 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2895	* SQR3 SQ16 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2896	* SQR3 SQ17 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2897	* SQR3 SQ18 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2898	* SQR2 SQ19 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2899	* SQR2 SQ20 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2900	* SQR2 SQ21 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2901	* SQR2 SQ22 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2902	* SQR2 SQ23 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2903	* SQR2 SQ24 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2904	* SQR1 SQ25 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2905	* SQR1 SQ26 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2906	* SQR1 SQ27 LL_ADC_REG_SetSequencerRanks\n
<>	128:9bcdf88f62b0	2907	* SQR1 SQ28 LL_ADC_REG_SetSequencerRanks
<>	128:9bcdf88f62b0	2908	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	2909	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2910	* @arg @ref LL_ADC_REG_RANK_1
<>	128:9bcdf88f62b0	2911	* @arg @ref LL_ADC_REG_RANK_2
<>	128:9bcdf88f62b0	2912	* @arg @ref LL_ADC_REG_RANK_3
<>	128:9bcdf88f62b0	2913	* @arg @ref LL_ADC_REG_RANK_4
<>	128:9bcdf88f62b0	2914	* @arg @ref LL_ADC_REG_RANK_5
<>	128:9bcdf88f62b0	2915	* @arg @ref LL_ADC_REG_RANK_6
<>	128:9bcdf88f62b0	2916	* @arg @ref LL_ADC_REG_RANK_7
<>	128:9bcdf88f62b0	2917	* @arg @ref LL_ADC_REG_RANK_8
<>	128:9bcdf88f62b0	2918	* @arg @ref LL_ADC_REG_RANK_9
<>	128:9bcdf88f62b0	2919	* @arg @ref LL_ADC_REG_RANK_10
<>	128:9bcdf88f62b0	2920	* @arg @ref LL_ADC_REG_RANK_11
<>	128:9bcdf88f62b0	2921	* @arg @ref LL_ADC_REG_RANK_12
<>	128:9bcdf88f62b0	2922	* @arg @ref LL_ADC_REG_RANK_13
<>	128:9bcdf88f62b0	2923	* @arg @ref LL_ADC_REG_RANK_14
<>	128:9bcdf88f62b0	2924	* @arg @ref LL_ADC_REG_RANK_15
<>	128:9bcdf88f62b0	2925	* @arg @ref LL_ADC_REG_RANK_16
<>	128:9bcdf88f62b0	2926	* @arg @ref LL_ADC_REG_RANK_17
<>	128:9bcdf88f62b0	2927	* @arg @ref LL_ADC_REG_RANK_18
<>	128:9bcdf88f62b0	2928	* @arg @ref LL_ADC_REG_RANK_19
<>	128:9bcdf88f62b0	2929	* @arg @ref LL_ADC_REG_RANK_20
<>	128:9bcdf88f62b0	2930	* @arg @ref LL_ADC_REG_RANK_21
<>	128:9bcdf88f62b0	2931	* @arg @ref LL_ADC_REG_RANK_22
<>	128:9bcdf88f62b0	2932	* @arg @ref LL_ADC_REG_RANK_23
<>	128:9bcdf88f62b0	2933	* @arg @ref LL_ADC_REG_RANK_24
<>	128:9bcdf88f62b0	2934	* @arg @ref LL_ADC_REG_RANK_25
<>	128:9bcdf88f62b0	2935	* @arg @ref LL_ADC_REG_RANK_26
<>	128:9bcdf88f62b0	2936	* @arg @ref LL_ADC_REG_RANK_27
<>	128:9bcdf88f62b0	2937	* @arg @ref LL_ADC_REG_RANK_28 (1)
<>	128:9bcdf88f62b0	2938	*
<>	128:9bcdf88f62b0	2939	* (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
<>	128:9bcdf88f62b0	2940	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	2941	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	2942	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	2943	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	2944	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	2945	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	2946	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	2947	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	2948	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	2949	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	2950	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	2951	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	2952	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	2953	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	2954	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	2955	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	2956	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	2957	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	2958	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	2959	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	2960	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	2961	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	2962	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	2963	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	2964	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	2965	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	2966	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	2967	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	2968	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	2969	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	2970	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	2971	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	2972	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	2973	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	2974	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	2975	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	2976	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	2977	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	2978	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	2979	*
<>	128:9bcdf88f62b0	2980	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	2981	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	2982	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	2983	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	2984	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	2985	* @retval None
<>	128:9bcdf88f62b0	2986	*/
<>	128:9bcdf88f62b0	2987	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	128:9bcdf88f62b0	2988	{
<>	128:9bcdf88f62b0	2989	/* Set bits with content of parameter "Channel" with bits position */
<>	128:9bcdf88f62b0	2990	/* in register and register position depending on parameter "Rank". */
<>	128:9bcdf88f62b0	2991	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	128:9bcdf88f62b0	2992	/* other bits reserved for other purpose. */
<>	128:9bcdf88f62b0	2993	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	2994
<>	128:9bcdf88f62b0	2995	MODIFY_REG(*preg,
<>	128:9bcdf88f62b0	2996	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
<>	128:9bcdf88f62b0	2997	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
<>	128:9bcdf88f62b0	2998	}
<>	128:9bcdf88f62b0	2999
<>	128:9bcdf88f62b0	3000	/**
<>	128:9bcdf88f62b0	3001	* @brief Get ADC group regular sequence: channel on the selected
<>	128:9bcdf88f62b0	3002	* scan sequence rank.
<>	128:9bcdf88f62b0	3003	* @note On this STM32 serie, ADC group regular sequencer is
<>	128:9bcdf88f62b0	3004	* fully configurable: sequencer length and each rank
<>	128:9bcdf88f62b0	3005	* affectation to a channel are configurable.
<>	128:9bcdf88f62b0	3006	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	128:9bcdf88f62b0	3007	* @note Depending on devices and packages, some channels may not be available.
<>	128:9bcdf88f62b0	3008	* Refer to device datasheet for channels availability.
<>	128:9bcdf88f62b0	3009	* @note Usage of the returned channel number:
<>	128:9bcdf88f62b0	3010	* - To reinject this channel into another function LL_ADC_xxx:
<>	128:9bcdf88f62b0	3011	* the returned channel number is only partly formatted on definition
<>	128:9bcdf88f62b0	3012	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	128:9bcdf88f62b0	3013	* with parts of literals LL_ADC_CHANNEL_x or using
<>	128:9bcdf88f62b0	3014	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	3015	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	128:9bcdf88f62b0	3016	* as parameter for another function.
<>	128:9bcdf88f62b0	3017	* - To get the channel number in decimal format:
<>	128:9bcdf88f62b0	3018	* process the returned value with the helper macro
<>	128:9bcdf88f62b0	3019	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	3020	* @rmtoll SQR5 SQ1 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3021	* SQR5 SQ2 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3022	* SQR5 SQ3 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3023	* SQR5 SQ4 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3024	* SQR5 SQ5 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3025	* SQR5 SQ6 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3026	* SQR4 SQ7 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3027	* SQR4 SQ8 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3028	* SQR4 SQ9 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3029	* SQR4 SQ10 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3030	* SQR4 SQ11 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3031	* SQR4 SQ12 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3032	* SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3033	* SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3034	* SQR3 SQ15 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3035	* SQR3 SQ16 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3036	* SQR3 SQ17 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3037	* SQR3 SQ18 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3038	* SQR2 SQ19 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3039	* SQR2 SQ20 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3040	* SQR2 SQ21 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3041	* SQR2 SQ22 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3042	* SQR2 SQ23 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3043	* SQR2 SQ24 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3044	* SQR1 SQ25 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3045	* SQR1 SQ26 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3046	* SQR1 SQ27 LL_ADC_REG_GetSequencerRanks\n
<>	128:9bcdf88f62b0	3047	* SQR1 SQ28 LL_ADC_REG_GetSequencerRanks
<>	128:9bcdf88f62b0	3048	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3049	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3050	* @arg @ref LL_ADC_REG_RANK_1
<>	128:9bcdf88f62b0	3051	* @arg @ref LL_ADC_REG_RANK_2
<>	128:9bcdf88f62b0	3052	* @arg @ref LL_ADC_REG_RANK_3
<>	128:9bcdf88f62b0	3053	* @arg @ref LL_ADC_REG_RANK_4
<>	128:9bcdf88f62b0	3054	* @arg @ref LL_ADC_REG_RANK_5
<>	128:9bcdf88f62b0	3055	* @arg @ref LL_ADC_REG_RANK_6
<>	128:9bcdf88f62b0	3056	* @arg @ref LL_ADC_REG_RANK_7
<>	128:9bcdf88f62b0	3057	* @arg @ref LL_ADC_REG_RANK_8
<>	128:9bcdf88f62b0	3058	* @arg @ref LL_ADC_REG_RANK_9
<>	128:9bcdf88f62b0	3059	* @arg @ref LL_ADC_REG_RANK_10
<>	128:9bcdf88f62b0	3060	* @arg @ref LL_ADC_REG_RANK_11
<>	128:9bcdf88f62b0	3061	* @arg @ref LL_ADC_REG_RANK_12
<>	128:9bcdf88f62b0	3062	* @arg @ref LL_ADC_REG_RANK_13
<>	128:9bcdf88f62b0	3063	* @arg @ref LL_ADC_REG_RANK_14
<>	128:9bcdf88f62b0	3064	* @arg @ref LL_ADC_REG_RANK_15
<>	128:9bcdf88f62b0	3065	* @arg @ref LL_ADC_REG_RANK_16
<>	128:9bcdf88f62b0	3066	* @arg @ref LL_ADC_REG_RANK_17
<>	128:9bcdf88f62b0	3067	* @arg @ref LL_ADC_REG_RANK_18
<>	128:9bcdf88f62b0	3068	* @arg @ref LL_ADC_REG_RANK_19
<>	128:9bcdf88f62b0	3069	* @arg @ref LL_ADC_REG_RANK_20
<>	128:9bcdf88f62b0	3070	* @arg @ref LL_ADC_REG_RANK_21
<>	128:9bcdf88f62b0	3071	* @arg @ref LL_ADC_REG_RANK_22
<>	128:9bcdf88f62b0	3072	* @arg @ref LL_ADC_REG_RANK_23
<>	128:9bcdf88f62b0	3073	* @arg @ref LL_ADC_REG_RANK_24
<>	128:9bcdf88f62b0	3074	* @arg @ref LL_ADC_REG_RANK_25
<>	128:9bcdf88f62b0	3075	* @arg @ref LL_ADC_REG_RANK_26
<>	128:9bcdf88f62b0	3076	* @arg @ref LL_ADC_REG_RANK_27
<>	128:9bcdf88f62b0	3077	* @arg @ref LL_ADC_REG_RANK_28 (1)
<>	128:9bcdf88f62b0	3078	*
<>	128:9bcdf88f62b0	3079	* (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
<>	128:9bcdf88f62b0	3080	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3081	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	3082	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	3083	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	3084	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	3085	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	3086	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	3087	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	3088	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	3089	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	3090	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	3091	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	3092	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	3093	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	3094	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	3095	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	3096	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	3097	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	3098	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	3099	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	3100	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	3101	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	3102	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	3103	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	3104	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	3105	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	3106	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	3107	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	3108	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	3109	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	3110	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	3111	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	3112	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	3113	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
<>	128:9bcdf88f62b0	3114	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
<>	128:9bcdf88f62b0	3115	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
<>	128:9bcdf88f62b0	3116	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	3117	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	3118	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	3119	*
<>	128:9bcdf88f62b0	3120	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	3121	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	3122	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	3123	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3124	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3125	* (6) For ADC channel read back from ADC register,
<>	128:9bcdf88f62b0	3126	* comparison with internal channel parameter to be done
<>	128:9bcdf88f62b0	3127	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	128:9bcdf88f62b0	3128	*/
<>	128:9bcdf88f62b0	3129	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	3130	{
<>	128:9bcdf88f62b0	3131	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	3132
<>	128:9bcdf88f62b0	3133	return (uint32_t) (READ_BIT(*preg,
<>	128:9bcdf88f62b0	3134	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<>	128:9bcdf88f62b0	3135	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
<>	128:9bcdf88f62b0	3136	);
<>	128:9bcdf88f62b0	3137	}
<>	128:9bcdf88f62b0	3138
<>	128:9bcdf88f62b0	3139	/**
<>	128:9bcdf88f62b0	3140	* @brief Set ADC continuous conversion mode on ADC group regular.
<>	128:9bcdf88f62b0	3141	* @note Description of ADC continuous conversion mode:
<>	128:9bcdf88f62b0	3142	* - single mode: one conversion per trigger
<>	128:9bcdf88f62b0	3143	* - continuous mode: after the first trigger, following
<>	128:9bcdf88f62b0	3144	* conversions launched successively automatically.
<>	128:9bcdf88f62b0	3145	* @note It is not possible to enable both ADC group regular
<>	128:9bcdf88f62b0	3146	* continuous mode and sequencer discontinuous mode.
<>	128:9bcdf88f62b0	3147	* @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
<>	128:9bcdf88f62b0	3148	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3149	* @param Continuous This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3150	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	128:9bcdf88f62b0	3151	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	128:9bcdf88f62b0	3152	* @retval None
<>	128:9bcdf88f62b0	3153	*/
<>	128:9bcdf88f62b0	3154	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<>	128:9bcdf88f62b0	3155	{
<>	128:9bcdf88f62b0	3156	MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
<>	128:9bcdf88f62b0	3157	}
<>	128:9bcdf88f62b0	3158
<>	128:9bcdf88f62b0	3159	/**
<>	128:9bcdf88f62b0	3160	* @brief Get ADC continuous conversion mode on ADC group regular.
<>	128:9bcdf88f62b0	3161	* @note Description of ADC continuous conversion mode:
<>	128:9bcdf88f62b0	3162	* - single mode: one conversion per trigger
<>	128:9bcdf88f62b0	3163	* - continuous mode: after the first trigger, following
<>	128:9bcdf88f62b0	3164	* conversions launched successively automatically.
<>	128:9bcdf88f62b0	3165	* @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
<>	128:9bcdf88f62b0	3166	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3167	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3168	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	128:9bcdf88f62b0	3169	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	128:9bcdf88f62b0	3170	*/
<>	128:9bcdf88f62b0	3171	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3172	{
<>	128:9bcdf88f62b0	3173	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
<>	128:9bcdf88f62b0	3174	}
<>	128:9bcdf88f62b0	3175
<>	128:9bcdf88f62b0	3176	/**
<>	128:9bcdf88f62b0	3177	* @brief Set ADC group regular conversion data transfer: no transfer or
<>	128:9bcdf88f62b0	3178	* transfer by DMA, and DMA requests mode.
<>	128:9bcdf88f62b0	3179	* @note If transfer by DMA selected, specifies the DMA requests
<>	128:9bcdf88f62b0	3180	* mode:
<>	128:9bcdf88f62b0	3181	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	128:9bcdf88f62b0	3182	* when number of DMA data transfers (number of
<>	128:9bcdf88f62b0	3183	* ADC conversions) is reached.
<>	128:9bcdf88f62b0	3184	* This ADC mode is intended to be used with DMA mode non-circular.
<>	128:9bcdf88f62b0	3185	* - Unlimited mode: DMA transfer requests are unlimited,
<>	128:9bcdf88f62b0	3186	* whatever number of DMA data transfers (number of
<>	128:9bcdf88f62b0	3187	* ADC conversions).
<>	128:9bcdf88f62b0	3188	* This ADC mode is intended to be used with DMA mode circular.
<>	128:9bcdf88f62b0	3189	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	128:9bcdf88f62b0	3190	* mode non-circular:
<>	128:9bcdf88f62b0	3191	* when DMA transfers size will be reached, DMA will stop transfers of
<>	128:9bcdf88f62b0	3192	* ADC conversions data ADC will raise an overrun error
<>	128:9bcdf88f62b0	3193	* (overrun flag and interruption if enabled).
<>	128:9bcdf88f62b0	3194	* @note To configure DMA source address (peripheral address),
<>	128:9bcdf88f62b0	3195	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	128:9bcdf88f62b0	3196	* @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
<>	128:9bcdf88f62b0	3197	* CR2 DDS LL_ADC_REG_SetDMATransfer
<>	128:9bcdf88f62b0	3198	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3199	* @param DMATransfer This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3200	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	128:9bcdf88f62b0	3201	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	128:9bcdf88f62b0	3202	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	128:9bcdf88f62b0	3203	* @retval None
<>	128:9bcdf88f62b0	3204	*/
<>	128:9bcdf88f62b0	3205	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<>	128:9bcdf88f62b0	3206	{
<>	128:9bcdf88f62b0	3207	MODIFY_REG(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS, DMATransfer);
<>	128:9bcdf88f62b0	3208	}
<>	128:9bcdf88f62b0	3209
<>	128:9bcdf88f62b0	3210	/**
<>	128:9bcdf88f62b0	3211	* @brief Get ADC group regular conversion data transfer: no transfer or
<>	128:9bcdf88f62b0	3212	* transfer by DMA, and DMA requests mode.
<>	128:9bcdf88f62b0	3213	* @note If transfer by DMA selected, specifies the DMA requests
<>	128:9bcdf88f62b0	3214	* mode:
<>	128:9bcdf88f62b0	3215	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	128:9bcdf88f62b0	3216	* when number of DMA data transfers (number of
<>	128:9bcdf88f62b0	3217	* ADC conversions) is reached.
<>	128:9bcdf88f62b0	3218	* This ADC mode is intended to be used with DMA mode non-circular.
<>	128:9bcdf88f62b0	3219	* - Unlimited mode: DMA transfer requests are unlimited,
<>	128:9bcdf88f62b0	3220	* whatever number of DMA data transfers (number of
<>	128:9bcdf88f62b0	3221	* ADC conversions).
<>	128:9bcdf88f62b0	3222	* This ADC mode is intended to be used with DMA mode circular.
<>	128:9bcdf88f62b0	3223	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	128:9bcdf88f62b0	3224	* mode non-circular:
<>	128:9bcdf88f62b0	3225	* when DMA transfers size will be reached, DMA will stop transfers of
<>	128:9bcdf88f62b0	3226	* ADC conversions data ADC will raise an overrun error
<>	128:9bcdf88f62b0	3227	* (overrun flag and interruption if enabled).
<>	128:9bcdf88f62b0	3228	* @note To configure DMA source address (peripheral address),
<>	128:9bcdf88f62b0	3229	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	128:9bcdf88f62b0	3230	* @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
<>	128:9bcdf88f62b0	3231	* CR2 DDS LL_ADC_REG_GetDMATransfer
<>	128:9bcdf88f62b0	3232	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3233	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3234	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	128:9bcdf88f62b0	3235	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	128:9bcdf88f62b0	3236	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	128:9bcdf88f62b0	3237	*/
<>	128:9bcdf88f62b0	3238	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3239	{
<>	128:9bcdf88f62b0	3240	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS));
<>	128:9bcdf88f62b0	3241	}
<>	128:9bcdf88f62b0	3242
<>	128:9bcdf88f62b0	3243	/**
<>	128:9bcdf88f62b0	3244	* @brief Specify which ADC flag between EOC (end of unitary conversion)
<>	128:9bcdf88f62b0	3245	* or EOS (end of sequence conversions) is used to indicate
<>	128:9bcdf88f62b0	3246	* the end of conversion.
<>	128:9bcdf88f62b0	3247	* @note This feature is aimed to be set when using ADC with
<>	128:9bcdf88f62b0	3248	* programming model by polling or interruption
<>	128:9bcdf88f62b0	3249	* (programming model by DMA usually uses DMA interruptions
<>	128:9bcdf88f62b0	3250	* to indicate end of conversion and data transfer).
<>	128:9bcdf88f62b0	3251	* @note For ADC group injected, end of conversion (flag&IT) is raised
<>	128:9bcdf88f62b0	3252	* only at the end of the sequence.
<>	128:9bcdf88f62b0	3253	* @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
<>	128:9bcdf88f62b0	3254	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3255	* @param EocSelection This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3256	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	128:9bcdf88f62b0	3257	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	128:9bcdf88f62b0	3258	* @retval None
<>	128:9bcdf88f62b0	3259	*/
<>	128:9bcdf88f62b0	3260	__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
<>	128:9bcdf88f62b0	3261	{
<>	128:9bcdf88f62b0	3262	MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
<>	128:9bcdf88f62b0	3263	}
<>	128:9bcdf88f62b0	3264
<>	128:9bcdf88f62b0	3265	/**
<>	128:9bcdf88f62b0	3266	* @brief Get which ADC flag between EOC (end of unitary conversion)
<>	128:9bcdf88f62b0	3267	* or EOS (end of sequence conversions) is used to indicate
<>	128:9bcdf88f62b0	3268	* the end of conversion.
<>	128:9bcdf88f62b0	3269	* @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
<>	128:9bcdf88f62b0	3270	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3271	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3272	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	128:9bcdf88f62b0	3273	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	128:9bcdf88f62b0	3274	*/
<>	128:9bcdf88f62b0	3275	__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3276	{
<>	128:9bcdf88f62b0	3277	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
<>	128:9bcdf88f62b0	3278	}
<>	128:9bcdf88f62b0	3279
<>	128:9bcdf88f62b0	3280	/**
<>	128:9bcdf88f62b0	3281	* @}
<>	128:9bcdf88f62b0	3282	*/
<>	128:9bcdf88f62b0	3283
<>	128:9bcdf88f62b0	3284	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
<>	128:9bcdf88f62b0	3285	* @{
<>	128:9bcdf88f62b0	3286	*/
<>	128:9bcdf88f62b0	3287
<>	128:9bcdf88f62b0	3288	/**
<>	128:9bcdf88f62b0	3289	* @brief Set ADC group injected conversion trigger source:
<>	128:9bcdf88f62b0	3290	* internal (SW start) or from external IP (timer event,
<>	128:9bcdf88f62b0	3291	* external interrupt line).
<>	128:9bcdf88f62b0	3292	* @note On this STM32 serie, setting of external trigger edge is performed
<>	128:9bcdf88f62b0	3293	* using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	128:9bcdf88f62b0	3294	* @note Availability of parameters of trigger sources from timer
<>	128:9bcdf88f62b0	3295	* depends on timers availability on the selected device.
<>	128:9bcdf88f62b0	3296	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
<>	128:9bcdf88f62b0	3297	* CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
<>	128:9bcdf88f62b0	3298	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3299	* @param TriggerSource This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3300	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	128:9bcdf88f62b0	3301	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
<>	128:9bcdf88f62b0	3302	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
<>	128:9bcdf88f62b0	3303	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	128:9bcdf88f62b0	3304	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	128:9bcdf88f62b0	3305	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	128:9bcdf88f62b0	3306	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	128:9bcdf88f62b0	3307	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
<>	128:9bcdf88f62b0	3308	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
<>	128:9bcdf88f62b0	3309	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
<>	128:9bcdf88f62b0	3310	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
<>	128:9bcdf88f62b0	3311	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
<>	128:9bcdf88f62b0	3312	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
<>	128:9bcdf88f62b0	3313	* @retval None
<>	128:9bcdf88f62b0	3314	*/
<>	128:9bcdf88f62b0	3315	__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	128:9bcdf88f62b0	3316	{
<>	128:9bcdf88f62b0	3317	/* Note: On this STM32 serie, ADC group injected external trigger edge */
<>	128:9bcdf88f62b0	3318	/* is used to perform a ADC conversion start. */
<>	128:9bcdf88f62b0	3319	/* This function does not set external trigger edge. */
<>	128:9bcdf88f62b0	3320	/* This feature is set using function */
<>	128:9bcdf88f62b0	3321	/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
<>	128:9bcdf88f62b0	3322	MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
<>	128:9bcdf88f62b0	3323	}
<>	128:9bcdf88f62b0	3324
<>	128:9bcdf88f62b0	3325	/**
<>	128:9bcdf88f62b0	3326	* @brief Get ADC group injected conversion trigger source:
<>	128:9bcdf88f62b0	3327	* internal (SW start) or from external IP (timer event,
<>	128:9bcdf88f62b0	3328	* external interrupt line).
<>	128:9bcdf88f62b0	3329	* @note To determine whether group injected trigger source is
<>	128:9bcdf88f62b0	3330	* internal (SW start) or external, without detail
<>	128:9bcdf88f62b0	3331	* of which peripheral is selected as external trigger,
<>	128:9bcdf88f62b0	3332	* (equivalent to
<>	128:9bcdf88f62b0	3333	* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
<>	128:9bcdf88f62b0	3334	* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
<>	128:9bcdf88f62b0	3335	* @note Availability of parameters of trigger sources from timer
<>	128:9bcdf88f62b0	3336	* depends on timers availability on the selected device.
<>	128:9bcdf88f62b0	3337	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
<>	128:9bcdf88f62b0	3338	* CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
<>	128:9bcdf88f62b0	3339	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3340	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3341	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	128:9bcdf88f62b0	3342	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
<>	128:9bcdf88f62b0	3343	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
<>	128:9bcdf88f62b0	3344	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	128:9bcdf88f62b0	3345	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	128:9bcdf88f62b0	3346	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	128:9bcdf88f62b0	3347	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	128:9bcdf88f62b0	3348	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
<>	128:9bcdf88f62b0	3349	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
<>	128:9bcdf88f62b0	3350	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
<>	128:9bcdf88f62b0	3351	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
<>	128:9bcdf88f62b0	3352	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
<>	128:9bcdf88f62b0	3353	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
<>	128:9bcdf88f62b0	3354	*/
<>	128:9bcdf88f62b0	3355	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3356	{
<>	128:9bcdf88f62b0	3357	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL \| ADC_CR2_JEXTEN);
<>	128:9bcdf88f62b0	3358
<>	128:9bcdf88f62b0	3359	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	128:9bcdf88f62b0	3360	/* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
<>	128:9bcdf88f62b0	3361	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	128:9bcdf88f62b0	3362
<>	128:9bcdf88f62b0	3363	/* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
<>	128:9bcdf88f62b0	3364	/* to match with triggers literals definition. */
<>	128:9bcdf88f62b0	3365	return ((TriggerSource
<>	128:9bcdf88f62b0	3366	& (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
<>	128:9bcdf88f62b0	3367	\| ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
<>	128:9bcdf88f62b0	3368	);
<>	128:9bcdf88f62b0	3369	}
<>	128:9bcdf88f62b0	3370
<>	128:9bcdf88f62b0	3371	/**
<>	128:9bcdf88f62b0	3372	* @brief Get ADC group injected conversion trigger source internal (SW start)
<>	128:9bcdf88f62b0	3373	or external
<>	128:9bcdf88f62b0	3374	* @note In case of group injected trigger source set to external trigger,
<>	128:9bcdf88f62b0	3375	* to determine which peripheral is selected as external trigger,
<>	128:9bcdf88f62b0	3376	* use function @ref LL_ADC_INJ_GetTriggerSource.
<>	128:9bcdf88f62b0	3377	* @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
<>	128:9bcdf88f62b0	3378	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3379	* @retval Value "0" if trigger source external trigger
<>	128:9bcdf88f62b0	3380	* Value "1" if trigger source SW start.
<>	128:9bcdf88f62b0	3381	*/
<>	128:9bcdf88f62b0	3382	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3383	{
<>	128:9bcdf88f62b0	3384	return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
<>	128:9bcdf88f62b0	3385	}
<>	128:9bcdf88f62b0	3386
<>	128:9bcdf88f62b0	3387	/**
<>	128:9bcdf88f62b0	3388	* @brief Get ADC group injected conversion trigger polarity.
<>	128:9bcdf88f62b0	3389	* Applicable only for trigger source set to external trigger.
<>	128:9bcdf88f62b0	3390	* @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
<>	128:9bcdf88f62b0	3391	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3392	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3393	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	128:9bcdf88f62b0	3394	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	128:9bcdf88f62b0	3395	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	128:9bcdf88f62b0	3396	*/
<>	128:9bcdf88f62b0	3397	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3398	{
<>	128:9bcdf88f62b0	3399	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
<>	128:9bcdf88f62b0	3400	}
<>	128:9bcdf88f62b0	3401
<>	128:9bcdf88f62b0	3402	/**
<>	128:9bcdf88f62b0	3403	* @brief Set ADC group injected sequencer length and scan direction.
<>	128:9bcdf88f62b0	3404	* @note This function performs configuration of:
<>	128:9bcdf88f62b0	3405	* - Sequence length: Number of ranks in the scan sequence.
<>	128:9bcdf88f62b0	3406	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	3407	* scan direction is forward (from rank 1 to rank n).
<>	128:9bcdf88f62b0	3408	* @note On this STM32 serie, group injected sequencer configuration
<>	128:9bcdf88f62b0	3409	* is conditioned to ADC instance sequencer mode.
<>	128:9bcdf88f62b0	3410	* If ADC instance sequencer mode is disabled, sequencers of
<>	128:9bcdf88f62b0	3411	* all groups (group regular, group injected) can be configured
<>	128:9bcdf88f62b0	3412	* but their execution is disabled (limited to rank 1).
<>	128:9bcdf88f62b0	3413	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	128:9bcdf88f62b0	3414	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	128:9bcdf88f62b0	3415	* ADC conversion on only 1 channel.
<>	128:9bcdf88f62b0	3416	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
<>	128:9bcdf88f62b0	3417	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3418	* @param SequencerNbRanks This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3419	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	3420	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	128:9bcdf88f62b0	3421	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	128:9bcdf88f62b0	3422	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	128:9bcdf88f62b0	3423	* @retval None
<>	128:9bcdf88f62b0	3424	*/
<>	128:9bcdf88f62b0	3425	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	128:9bcdf88f62b0	3426	{
<>	128:9bcdf88f62b0	3427	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
<>	128:9bcdf88f62b0	3428	}
<>	128:9bcdf88f62b0	3429
<>	128:9bcdf88f62b0	3430	/**
<>	128:9bcdf88f62b0	3431	* @brief Get ADC group injected sequencer length and scan direction.
<>	128:9bcdf88f62b0	3432	* @note This function retrieves:
<>	128:9bcdf88f62b0	3433	* - Sequence length: Number of ranks in the scan sequence.
<>	128:9bcdf88f62b0	3434	* - Sequence direction: Unless specified in parameters, sequencer
<>	128:9bcdf88f62b0	3435	* scan direction is forward (from rank 1 to rank n).
<>	128:9bcdf88f62b0	3436	* @note On this STM32 serie, group injected sequencer configuration
<>	128:9bcdf88f62b0	3437	* is conditioned to ADC instance sequencer mode.
<>	128:9bcdf88f62b0	3438	* If ADC instance sequencer mode is disabled, sequencers of
<>	128:9bcdf88f62b0	3439	* all groups (group regular, group injected) can be configured
<>	128:9bcdf88f62b0	3440	* but their execution is disabled (limited to rank 1).
<>	128:9bcdf88f62b0	3441	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	128:9bcdf88f62b0	3442	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	128:9bcdf88f62b0	3443	* ADC conversion on only 1 channel.
<>	128:9bcdf88f62b0	3444	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
<>	128:9bcdf88f62b0	3445	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3446	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3447	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	128:9bcdf88f62b0	3448	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	128:9bcdf88f62b0	3449	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	128:9bcdf88f62b0	3450	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	128:9bcdf88f62b0	3451	*/
<>	128:9bcdf88f62b0	3452	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3453	{
<>	128:9bcdf88f62b0	3454	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
<>	128:9bcdf88f62b0	3455	}
<>	128:9bcdf88f62b0	3456
<>	128:9bcdf88f62b0	3457	/**
<>	128:9bcdf88f62b0	3458	* @brief Set ADC group injected sequencer discontinuous mode:
<>	128:9bcdf88f62b0	3459	* sequence subdivided and scan conversions interrupted every selected
<>	128:9bcdf88f62b0	3460	* number of ranks.
<>	128:9bcdf88f62b0	3461	* @note It is not possible to enable both ADC group injected
<>	128:9bcdf88f62b0	3462	* auto-injected mode and sequencer discontinuous mode.
<>	128:9bcdf88f62b0	3463	* @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
<>	128:9bcdf88f62b0	3464	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3465	* @param SeqDiscont This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3466	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	128:9bcdf88f62b0	3467	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	128:9bcdf88f62b0	3468	* @retval None
<>	128:9bcdf88f62b0	3469	*/
<>	128:9bcdf88f62b0	3470	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	128:9bcdf88f62b0	3471	{
<>	128:9bcdf88f62b0	3472	MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
<>	128:9bcdf88f62b0	3473	}
<>	128:9bcdf88f62b0	3474
<>	128:9bcdf88f62b0	3475	/**
<>	128:9bcdf88f62b0	3476	* @brief Get ADC group injected sequencer discontinuous mode:
<>	128:9bcdf88f62b0	3477	* sequence subdivided and scan conversions interrupted every selected
<>	128:9bcdf88f62b0	3478	* number of ranks.
<>	128:9bcdf88f62b0	3479	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
<>	128:9bcdf88f62b0	3480	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3481	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3482	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	128:9bcdf88f62b0	3483	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	128:9bcdf88f62b0	3484	*/
<>	128:9bcdf88f62b0	3485	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3486	{
<>	128:9bcdf88f62b0	3487	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
<>	128:9bcdf88f62b0	3488	}
<>	128:9bcdf88f62b0	3489
<>	128:9bcdf88f62b0	3490	/**
<>	128:9bcdf88f62b0	3491	* @brief Set ADC group injected sequence: channel on the selected
<>	128:9bcdf88f62b0	3492	* sequence rank.
<>	128:9bcdf88f62b0	3493	* @note Depending on devices and packages, some channels may not be available.
<>	128:9bcdf88f62b0	3494	* Refer to device datasheet for channels availability.
<>	128:9bcdf88f62b0	3495	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	128:9bcdf88f62b0	3496	* TempSensor, ...), measurement paths to internal channels must be
<>	128:9bcdf88f62b0	3497	* enabled separately.
<>	128:9bcdf88f62b0	3498	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	128:9bcdf88f62b0	3499	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3500	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3501	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3502	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	128:9bcdf88f62b0	3503	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3504	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3505	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	3506	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	3507	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	3508	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	3509	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3510	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	3511	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	3512	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	3513	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	3514	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	3515	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	3516	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	3517	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	3518	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	3519	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	3520	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	3521	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	3522	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	3523	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	3524	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	3525	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	3526	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	3527	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	3528	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	3529	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	3530	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	3531	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	3532	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	3533	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	3534	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	3535	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	3536	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	3537	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	3538	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	3539	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	3540	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	3541	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	3542	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	3543	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	3544	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	3545	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	3546	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	3547	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	3548	*
<>	128:9bcdf88f62b0	3549	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	3550	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	3551	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	3552	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3553	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	3554	* @retval None
<>	128:9bcdf88f62b0	3555	*/
<>	128:9bcdf88f62b0	3556	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	128:9bcdf88f62b0	3557	{
<>	128:9bcdf88f62b0	3558	/* Set bits with content of parameter "Channel" with bits position */
<>	128:9bcdf88f62b0	3559	/* in register depending on parameter "Rank". */
<>	128:9bcdf88f62b0	3560	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	128:9bcdf88f62b0	3561	/* other bits reserved for other purpose. */
<>	128:9bcdf88f62b0	3562	MODIFY_REG(ADCx->JSQR,
<>	128:9bcdf88f62b0	3563	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
<>	128:9bcdf88f62b0	3564	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
<>	128:9bcdf88f62b0	3565	}
<>	128:9bcdf88f62b0	3566
<>	128:9bcdf88f62b0	3567	/**
<>	128:9bcdf88f62b0	3568	* @brief Get ADC group injected sequence: channel on the selected
<>	128:9bcdf88f62b0	3569	* sequence rank.
<>	128:9bcdf88f62b0	3570	* @note Depending on devices and packages, some channels may not be available.
<>	128:9bcdf88f62b0	3571	* Refer to device datasheet for channels availability.
<>	128:9bcdf88f62b0	3572	* @note Usage of the returned channel number:
<>	128:9bcdf88f62b0	3573	* - To reinject this channel into another function LL_ADC_xxx:
<>	128:9bcdf88f62b0	3574	* the returned channel number is only partly formatted on definition
<>	128:9bcdf88f62b0	3575	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	128:9bcdf88f62b0	3576	* with parts of literals LL_ADC_CHANNEL_x or using
<>	128:9bcdf88f62b0	3577	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	3578	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	128:9bcdf88f62b0	3579	* as parameter for another function.
<>	128:9bcdf88f62b0	3580	* - To get the channel number in decimal format:
<>	128:9bcdf88f62b0	3581	* process the returned value with the helper macro
<>	128:9bcdf88f62b0	3582	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	3583	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3584	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3585	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	128:9bcdf88f62b0	3586	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	128:9bcdf88f62b0	3587	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3588	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3589	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	3590	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	3591	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	3592	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	3593	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3594	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	3595	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	3596	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	3597	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	3598	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	3599	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	3600	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	3601	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	3602	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	3603	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	3604	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	3605	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	3606	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	3607	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	3608	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	3609	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	3610	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	3611	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	3612	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	3613	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	3614	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	3615	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	3616	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	3617	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	3618	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	3619	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	3620	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	3621	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	3622	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	3623	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	3624	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	3625	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	3626	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
<>	128:9bcdf88f62b0	3627	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
<>	128:9bcdf88f62b0	3628	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
<>	128:9bcdf88f62b0	3629	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	3630	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	3631	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	3632	*
<>	128:9bcdf88f62b0	3633	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	3634	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	3635	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	3636	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3637	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3638	* (6) For ADC channel read back from ADC register,
<>	128:9bcdf88f62b0	3639	* comparison with internal channel parameter to be done
<>	128:9bcdf88f62b0	3640	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	128:9bcdf88f62b0	3641	*/
<>	128:9bcdf88f62b0	3642	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	3643	{
<>	128:9bcdf88f62b0	3644	return (uint32_t)(READ_BIT(ADCx->JSQR,
<>	128:9bcdf88f62b0	3645	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
<>	128:9bcdf88f62b0	3646	>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
<>	128:9bcdf88f62b0	3647	);
<>	128:9bcdf88f62b0	3648	}
<>	128:9bcdf88f62b0	3649
<>	128:9bcdf88f62b0	3650	/**
<>	128:9bcdf88f62b0	3651	* @brief Set ADC group injected conversion trigger:
<>	128:9bcdf88f62b0	3652	* independent or from ADC group regular.
<>	128:9bcdf88f62b0	3653	* @note This mode can be used to extend number of data registers
<>	128:9bcdf88f62b0	3654	* updated after one ADC conversion trigger and with data
<>	128:9bcdf88f62b0	3655	* permanently kept (not erased by successive conversions of scan of
<>	128:9bcdf88f62b0	3656	* ADC sequencer ranks), up to 5 data registers:
<>	128:9bcdf88f62b0	3657	* 1 data register on ADC group regular, 4 data registers
<>	128:9bcdf88f62b0	3658	* on ADC group injected.
<>	128:9bcdf88f62b0	3659	* @note If ADC group injected injected trigger source is set to an
<>	128:9bcdf88f62b0	3660	* external trigger, this feature must be must be set to
<>	128:9bcdf88f62b0	3661	* independent trigger.
<>	128:9bcdf88f62b0	3662	* ADC group injected automatic trigger is compliant only with
<>	128:9bcdf88f62b0	3663	* group injected trigger source set to SW start, without any
<>	128:9bcdf88f62b0	3664	* further action on ADC group injected conversion start or stop:
<>	128:9bcdf88f62b0	3665	* in this case, ADC group injected is controlled only
<>	128:9bcdf88f62b0	3666	* from ADC group regular.
<>	128:9bcdf88f62b0	3667	* @note It is not possible to enable both ADC group injected
<>	128:9bcdf88f62b0	3668	* auto-injected mode and sequencer discontinuous mode.
<>	128:9bcdf88f62b0	3669	* @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
<>	128:9bcdf88f62b0	3670	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3671	* @param TrigAuto This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3672	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	128:9bcdf88f62b0	3673	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	128:9bcdf88f62b0	3674	* @retval None
<>	128:9bcdf88f62b0	3675	*/
<>	128:9bcdf88f62b0	3676	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
<>	128:9bcdf88f62b0	3677	{
<>	128:9bcdf88f62b0	3678	MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
<>	128:9bcdf88f62b0	3679	}
<>	128:9bcdf88f62b0	3680
<>	128:9bcdf88f62b0	3681	/**
<>	128:9bcdf88f62b0	3682	* @brief Get ADC group injected conversion trigger:
<>	128:9bcdf88f62b0	3683	* independent or from ADC group regular.
<>	128:9bcdf88f62b0	3684	* @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
<>	128:9bcdf88f62b0	3685	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3686	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3687	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	128:9bcdf88f62b0	3688	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	128:9bcdf88f62b0	3689	*/
<>	128:9bcdf88f62b0	3690	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	3691	{
<>	128:9bcdf88f62b0	3692	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
<>	128:9bcdf88f62b0	3693	}
<>	128:9bcdf88f62b0	3694
<>	128:9bcdf88f62b0	3695	/**
<>	128:9bcdf88f62b0	3696	* @brief Set ADC group injected offset.
<>	128:9bcdf88f62b0	3697	* @note It sets:
<>	128:9bcdf88f62b0	3698	* - ADC group injected rank to which the offset programmed
<>	128:9bcdf88f62b0	3699	* will be applied
<>	128:9bcdf88f62b0	3700	* - Offset level (offset to be subtracted from the raw
<>	128:9bcdf88f62b0	3701	* converted data).
<>	128:9bcdf88f62b0	3702	* Caution: Offset format is dependent to ADC resolution:
<>	128:9bcdf88f62b0	3703	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	128:9bcdf88f62b0	3704	* are set to 0.
<>	128:9bcdf88f62b0	3705	* @note Offset cannot be enabled or disabled.
<>	128:9bcdf88f62b0	3706	* To emulate offset disabled, set an offset value equal to 0.
<>	128:9bcdf88f62b0	3707	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
<>	128:9bcdf88f62b0	3708	* JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
<>	128:9bcdf88f62b0	3709	* JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
<>	128:9bcdf88f62b0	3710	* JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
<>	128:9bcdf88f62b0	3711	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3712	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3713	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	3714	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	3715	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	3716	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	3717	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	3718	* @retval None
<>	128:9bcdf88f62b0	3719	*/
<>	128:9bcdf88f62b0	3720	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
<>	128:9bcdf88f62b0	3721	{
<>	128:9bcdf88f62b0	3722	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	3723
<>	128:9bcdf88f62b0	3724	MODIFY_REG(*preg,
<>	128:9bcdf88f62b0	3725	ADC_JOFR1_JOFFSET1,
<>	128:9bcdf88f62b0	3726	OffsetLevel);
<>	128:9bcdf88f62b0	3727	}
<>	128:9bcdf88f62b0	3728
<>	128:9bcdf88f62b0	3729	/**
<>	128:9bcdf88f62b0	3730	* @brief Get ADC group injected offset.
<>	128:9bcdf88f62b0	3731	* @note It gives offset level (offset to be subtracted from the raw converted data).
<>	128:9bcdf88f62b0	3732	* Caution: Offset format is dependent to ADC resolution:
<>	128:9bcdf88f62b0	3733	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	128:9bcdf88f62b0	3734	* are set to 0.
<>	128:9bcdf88f62b0	3735	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
<>	128:9bcdf88f62b0	3736	* JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
<>	128:9bcdf88f62b0	3737	* JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
<>	128:9bcdf88f62b0	3738	* JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
<>	128:9bcdf88f62b0	3739	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3740	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3741	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	3742	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	3743	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	3744	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	3745	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	3746	*/
<>	128:9bcdf88f62b0	3747	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	3748	{
<>	128:9bcdf88f62b0	3749	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	3750
<>	128:9bcdf88f62b0	3751	return (uint32_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	3752	ADC_JOFR1_JOFFSET1)
<>	128:9bcdf88f62b0	3753	);
<>	128:9bcdf88f62b0	3754	}
<>	128:9bcdf88f62b0	3755
<>	128:9bcdf88f62b0	3756	/**
<>	128:9bcdf88f62b0	3757	* @}
<>	128:9bcdf88f62b0	3758	*/
<>	128:9bcdf88f62b0	3759
<>	128:9bcdf88f62b0	3760	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
<>	128:9bcdf88f62b0	3761	* @{
<>	128:9bcdf88f62b0	3762	*/
<>	128:9bcdf88f62b0	3763
<>	128:9bcdf88f62b0	3764	/**
<>	128:9bcdf88f62b0	3765	* @brief Set sampling time of the selected ADC channel
<>	128:9bcdf88f62b0	3766	* Unit: ADC clock cycles.
<>	128:9bcdf88f62b0	3767	* @note On this device, sampling time is on channel scope: independently
<>	128:9bcdf88f62b0	3768	* of channel mapped on ADC group regular or injected.
<>	128:9bcdf88f62b0	3769	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
<>	128:9bcdf88f62b0	3770	* converted:
<>	128:9bcdf88f62b0	3771	* sampling time constraints must be respected (sampling time can be
<>	128:9bcdf88f62b0	3772	* adjusted in function of ADC clock frequency and sampling time
<>	128:9bcdf88f62b0	3773	* setting).
<>	128:9bcdf88f62b0	3774	* Refer to device datasheet for timings values (parameters TS_vrefint,
<>	128:9bcdf88f62b0	3775	* TS_temp, ...).
<>	128:9bcdf88f62b0	3776	* @note Conversion time is the addition of sampling time and processing time.
<>	128:9bcdf88f62b0	3777	* Refer to reference manual for ADC processing time of
<>	128:9bcdf88f62b0	3778	* this STM32 serie.
<>	128:9bcdf88f62b0	3779	* @note In case of ADC conversion of internal channel (VrefInt,
<>	128:9bcdf88f62b0	3780	* temperature sensor, ...), a sampling time minimum value
<>	128:9bcdf88f62b0	3781	* is required.
<>	128:9bcdf88f62b0	3782	* Refer to device datasheet.
<>	128:9bcdf88f62b0	3783	* @rmtoll SMPR0 SMP31 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3784	* SMPR0 SMP30 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3785	* SMPR1 SMP29 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3786	* SMPR1 SMP28 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3787	* SMPR1 SMP27 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3788	* SMPR1 SMP26 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3789	* SMPR1 SMP25 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3790	* SMPR1 SMP24 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3791	* SMPR1 SMP23 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3792	* SMPR1 SMP22 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3793	* SMPR1 SMP21 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3794	* SMPR1 SMP20 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3795	* SMPR2 SMP19 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3796	* SMPR2 SMP18 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3797	* SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3798	* SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3799	* SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3800	* SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3801	* SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3802	* SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3803	* SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3804	* SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3805	* SMPR3 SMP9 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3806	* SMPR3 SMP8 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3807	* SMPR3 SMP7 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3808	* SMPR3 SMP6 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3809	* SMPR3 SMP5 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3810	* SMPR3 SMP4 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3811	* SMPR3 SMP3 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3812	* SMPR3 SMP2 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3813	* SMPR3 SMP1 LL_ADC_SetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3814	* SMPR3 SMP0 LL_ADC_SetChannelSamplingTime
<>	128:9bcdf88f62b0	3815	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3816	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3817	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	3818	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	3819	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	3820	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	3821	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	3822	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	3823	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	3824	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	3825	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	3826	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	3827	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	3828	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	3829	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	3830	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	3831	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	3832	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	3833	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	3834	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	3835	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	3836	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	3837	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	3838	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	3839	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	3840	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	3841	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	3842	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	3843	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	3844	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	3845	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	3846	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	3847	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	3848	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	3849	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	3850	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	3851	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	3852	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	3853	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	3854	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	3855	*
<>	128:9bcdf88f62b0	3856	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	3857	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	3858	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	3859	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3860	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	3861	* @param SamplingTime This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3862	* @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
<>	128:9bcdf88f62b0	3863	* @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
<>	128:9bcdf88f62b0	3864	* @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
<>	128:9bcdf88f62b0	3865	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
<>	128:9bcdf88f62b0	3866	* @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
<>	128:9bcdf88f62b0	3867	* @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
<>	128:9bcdf88f62b0	3868	* @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
<>	128:9bcdf88f62b0	3869	* @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
<>	128:9bcdf88f62b0	3870	* @retval None
<>	128:9bcdf88f62b0	3871	*/
<>	128:9bcdf88f62b0	3872	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
<>	128:9bcdf88f62b0	3873	{
<>	128:9bcdf88f62b0	3874	/* Set bits with content of parameter "SamplingTime" with bits position */
<>	128:9bcdf88f62b0	3875	/* in register and register position depending on parameter "Channel". */
<>	128:9bcdf88f62b0	3876	/* Parameter "Channel" is used with masks because containing */
<>	128:9bcdf88f62b0	3877	/* other bits reserved for other purpose. */
<>	128:9bcdf88f62b0	3878	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	3879
<>	128:9bcdf88f62b0	3880	MODIFY_REG(*preg,
<>	128:9bcdf88f62b0	3881	ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
<>	128:9bcdf88f62b0	3882	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
<>	128:9bcdf88f62b0	3883	}
<>	128:9bcdf88f62b0	3884
<>	128:9bcdf88f62b0	3885	/**
<>	128:9bcdf88f62b0	3886	* @brief Get sampling time of the selected ADC channel
<>	128:9bcdf88f62b0	3887	* Unit: ADC clock cycles.
<>	128:9bcdf88f62b0	3888	* @note On this device, sampling time is on channel scope: independently
<>	128:9bcdf88f62b0	3889	* of channel mapped on ADC group regular or injected.
<>	128:9bcdf88f62b0	3890	* @note Conversion time is the addition of sampling time and processing time.
<>	128:9bcdf88f62b0	3891	* Refer to reference manual for ADC processing time of
<>	128:9bcdf88f62b0	3892	* this STM32 serie.
<>	128:9bcdf88f62b0	3893	* @rmtoll SMPR0 SMP31 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3894	* SMPR0 SMP30 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3895	* SMPR1 SMP29 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3896	* SMPR1 SMP28 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3897	* SMPR1 SMP27 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3898	* SMPR1 SMP26 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3899	* SMPR1 SMP25 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3900	* SMPR1 SMP24 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3901	* SMPR1 SMP23 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3902	* SMPR1 SMP22 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3903	* SMPR1 SMP21 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3904	* SMPR1 SMP20 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3905	* SMPR2 SMP19 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3906	* SMPR2 SMP18 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3907	* SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3908	* SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3909	* SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3910	* SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3911	* SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3912	* SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3913	* SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3914	* SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3915	* SMPR3 SMP9 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3916	* SMPR3 SMP8 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3917	* SMPR3 SMP7 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3918	* SMPR3 SMP6 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3919	* SMPR3 SMP5 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3920	* SMPR3 SMP4 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3921	* SMPR3 SMP3 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3922	* SMPR3 SMP2 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3923	* SMPR3 SMP1 LL_ADC_GetChannelSamplingTime\n
<>	128:9bcdf88f62b0	3924	* SMPR3 SMP0 LL_ADC_GetChannelSamplingTime
<>	128:9bcdf88f62b0	3925	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	3926	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	3927	* @arg @ref LL_ADC_CHANNEL_0 (2)
<>	128:9bcdf88f62b0	3928	* @arg @ref LL_ADC_CHANNEL_1 (2)
<>	128:9bcdf88f62b0	3929	* @arg @ref LL_ADC_CHANNEL_2 (2)
<>	128:9bcdf88f62b0	3930	* @arg @ref LL_ADC_CHANNEL_3 (2)
<>	128:9bcdf88f62b0	3931	* @arg @ref LL_ADC_CHANNEL_4 (1)
<>	128:9bcdf88f62b0	3932	* @arg @ref LL_ADC_CHANNEL_5 (1)
<>	128:9bcdf88f62b0	3933	* @arg @ref LL_ADC_CHANNEL_6 (2)
<>	128:9bcdf88f62b0	3934	* @arg @ref LL_ADC_CHANNEL_7 (2)
<>	128:9bcdf88f62b0	3935	* @arg @ref LL_ADC_CHANNEL_8 (2)
<>	128:9bcdf88f62b0	3936	* @arg @ref LL_ADC_CHANNEL_9 (2)
<>	128:9bcdf88f62b0	3937	* @arg @ref LL_ADC_CHANNEL_10 (2)
<>	128:9bcdf88f62b0	3938	* @arg @ref LL_ADC_CHANNEL_11 (2)
<>	128:9bcdf88f62b0	3939	* @arg @ref LL_ADC_CHANNEL_12 (2)
<>	128:9bcdf88f62b0	3940	* @arg @ref LL_ADC_CHANNEL_13 (3)
<>	128:9bcdf88f62b0	3941	* @arg @ref LL_ADC_CHANNEL_14 (3)
<>	128:9bcdf88f62b0	3942	* @arg @ref LL_ADC_CHANNEL_15 (3)
<>	128:9bcdf88f62b0	3943	* @arg @ref LL_ADC_CHANNEL_16 (3)
<>	128:9bcdf88f62b0	3944	* @arg @ref LL_ADC_CHANNEL_17 (3)
<>	128:9bcdf88f62b0	3945	* @arg @ref LL_ADC_CHANNEL_18 (3)
<>	128:9bcdf88f62b0	3946	* @arg @ref LL_ADC_CHANNEL_19 (3)
<>	128:9bcdf88f62b0	3947	* @arg @ref LL_ADC_CHANNEL_20 (3)
<>	128:9bcdf88f62b0	3948	* @arg @ref LL_ADC_CHANNEL_21 (3)
<>	128:9bcdf88f62b0	3949	* @arg @ref LL_ADC_CHANNEL_22 (1)
<>	128:9bcdf88f62b0	3950	* @arg @ref LL_ADC_CHANNEL_23 (1)
<>	128:9bcdf88f62b0	3951	* @arg @ref LL_ADC_CHANNEL_24 (1)
<>	128:9bcdf88f62b0	3952	* @arg @ref LL_ADC_CHANNEL_25 (1)
<>	128:9bcdf88f62b0	3953	* @arg @ref LL_ADC_CHANNEL_26 (3)
<>	128:9bcdf88f62b0	3954	* @arg @ref LL_ADC_CHANNEL_27 (3)(4)
<>	128:9bcdf88f62b0	3955	* @arg @ref LL_ADC_CHANNEL_28 (3)(4)
<>	128:9bcdf88f62b0	3956	* @arg @ref LL_ADC_CHANNEL_29 (3)(4)
<>	128:9bcdf88f62b0	3957	* @arg @ref LL_ADC_CHANNEL_30 (3)(4)
<>	128:9bcdf88f62b0	3958	* @arg @ref LL_ADC_CHANNEL_31 (3)(4)
<>	128:9bcdf88f62b0	3959	* @arg @ref LL_ADC_CHANNEL_VREFINT (3)
<>	128:9bcdf88f62b0	3960	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
<>	128:9bcdf88f62b0	3961	* @arg @ref LL_ADC_CHANNEL_VCOMP (3)
<>	128:9bcdf88f62b0	3962	* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
<>	128:9bcdf88f62b0	3963	* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
<>	128:9bcdf88f62b0	3964	* @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
<>	128:9bcdf88f62b0	3965	*
<>	128:9bcdf88f62b0	3966	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	3967	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	3968	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	3969	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	3970	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	3971	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	3972	* @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
<>	128:9bcdf88f62b0	3973	* @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
<>	128:9bcdf88f62b0	3974	* @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
<>	128:9bcdf88f62b0	3975	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
<>	128:9bcdf88f62b0	3976	* @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
<>	128:9bcdf88f62b0	3977	* @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
<>	128:9bcdf88f62b0	3978	* @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
<>	128:9bcdf88f62b0	3979	* @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
<>	128:9bcdf88f62b0	3980	*/
<>	128:9bcdf88f62b0	3981	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
<>	128:9bcdf88f62b0	3982	{
<>	128:9bcdf88f62b0	3983	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	3984
<>	128:9bcdf88f62b0	3985	return (uint32_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	3986	ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
<>	128:9bcdf88f62b0	3987	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
<>	128:9bcdf88f62b0	3988	);
<>	128:9bcdf88f62b0	3989	}
<>	128:9bcdf88f62b0	3990
<>	128:9bcdf88f62b0	3991	#if defined(COMP_CSR_FCH3)
<>	128:9bcdf88f62b0	3992	/**
<>	128:9bcdf88f62b0	3993	* @brief Set ADC channels routing.
<>	128:9bcdf88f62b0	3994	* @note Channel routing set configuration between ADC IP and GPIO pads,
<>	128:9bcdf88f62b0	3995	* it is used to increase ADC channels speed (setting of
<>	128:9bcdf88f62b0	3996	* direct channel).
<>	128:9bcdf88f62b0	3997	* @note This feature is specific to STM32L1, on devices
<>	128:9bcdf88f62b0	3998	* category Cat.3, Cat.4, Cat.5.
<>	128:9bcdf88f62b0	3999	* To use this function, COMP RCC clock domain must be enabled.
<>	128:9bcdf88f62b0	4000	* Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
<>	128:9bcdf88f62b0	4001	* @rmtoll CSR FCH3 LL_ADC_SetChannelRouting
<>	128:9bcdf88f62b0	4002	* @rmtoll CSR FCH8 LL_ADC_SetChannelRouting
<>	128:9bcdf88f62b0	4003	* @rmtoll CSR RCH13 LL_ADC_SetChannelRouting
<>	128:9bcdf88f62b0	4004	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4005	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4006	* @arg @ref LL_ADC_CHANNEL_3_ROUTING (1)
<>	128:9bcdf88f62b0	4007	* @arg @ref LL_ADC_CHANNEL_8_ROUTING (2)
<>	128:9bcdf88f62b0	4008	* @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
<>	128:9bcdf88f62b0	4009	*
<>	128:9bcdf88f62b0	4010	* (1) Used as ADC direct channel (fast channel) if OPAMP1 is
<>	128:9bcdf88f62b0	4011	* in power down mode.\n
<>	128:9bcdf88f62b0	4012	* (2) Used as ADC direct channel (fast channel) if OPAMP2 is
<>	128:9bcdf88f62b0	4013	* in power down mode.\n
<>	128:9bcdf88f62b0	4014	* (3) Used as ADC re-routed channel if OPAMP3 is
<>	128:9bcdf88f62b0	4015	* in power down mode.
<>	128:9bcdf88f62b0	4016	* Otherwise, channel 13 is connected to OPAMP3 output and routed
<>	128:9bcdf88f62b0	4017	* through switches COMP1_SW1 and VCOMP to ADC switch matrix.
<>	128:9bcdf88f62b0	4018	* (Note: OPAMP3 is available on STM32L1 Cat.4 only).
<>	128:9bcdf88f62b0	4019	* @param Routing This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4020	* @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
<>	128:9bcdf88f62b0	4021	* @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
<>	128:9bcdf88f62b0	4022	*/
<>	128:9bcdf88f62b0	4023	__STATIC_INLINE void LL_ADC_SetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Routing)
<>	128:9bcdf88f62b0	4024	{
<>	128:9bcdf88f62b0	4025	/* Note: Bit is located in comparator IP, but dedicated to ADC */
<>	128:9bcdf88f62b0	4026	MODIFY_REG(COMP->CSR, Channel, (Routing << POSITION_VAL(Channel)));
<>	128:9bcdf88f62b0	4027	}
<>	128:9bcdf88f62b0	4028
<>	128:9bcdf88f62b0	4029	/**
<>	128:9bcdf88f62b0	4030	* @brief Get ADC channels speed.
<>	128:9bcdf88f62b0	4031	* @note Channel routing set configuration between ADC IP and GPIO pads,
<>	128:9bcdf88f62b0	4032	* it is used to increase ADC channels speed (setting of
<>	128:9bcdf88f62b0	4033	* direct channel).
<>	128:9bcdf88f62b0	4034	* @note This feature is specific to STM32L1, on devices
<>	128:9bcdf88f62b0	4035	* category Cat.3, Cat.4, Cat.5.
<>	128:9bcdf88f62b0	4036	* To use this function, COMP RCC clock domain must be enabled.
<>	128:9bcdf88f62b0	4037	* Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
<>	128:9bcdf88f62b0	4038	* @rmtoll CSR FCH3 LL_ADC_GetChannelRouting
<>	128:9bcdf88f62b0	4039	* @rmtoll CSR FCH8 LL_ADC_GetChannelRouting
<>	128:9bcdf88f62b0	4040	* @rmtoll CSR RCH13 LL_ADC_GetChannelRouting
<>	128:9bcdf88f62b0	4041	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4042	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4043	* @arg @ref LL_ADC_CHANNEL_3_ROUTING (1)
<>	128:9bcdf88f62b0	4044	* @arg @ref LL_ADC_CHANNEL_8_ROUTING (2)
<>	128:9bcdf88f62b0	4045	* @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
<>	128:9bcdf88f62b0	4046	*
<>	128:9bcdf88f62b0	4047	* (1) Used as ADC direct channel (fast channel) if OPAMP1 is
<>	128:9bcdf88f62b0	4048	* in power down mode.\n
<>	128:9bcdf88f62b0	4049	* (2) Used as ADC direct channel (fast channel) if OPAMP2 is
<>	128:9bcdf88f62b0	4050	* in power down mode.\n
<>	128:9bcdf88f62b0	4051	* (3) Used as ADC re-routed channel if OPAMP3 is
<>	128:9bcdf88f62b0	4052	* in power down mode.
<>	128:9bcdf88f62b0	4053	* Otherwise, channel 13 is connected to OPAMP3 output and routed
<>	128:9bcdf88f62b0	4054	* through switches COMP1_SW1 and VCOMP to ADC switch matrix.
<>	128:9bcdf88f62b0	4055	* (Note: OPAMP3 is available on STM32L1 Cat.4 only).
<>	128:9bcdf88f62b0	4056	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	4057	* @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
<>	128:9bcdf88f62b0	4058	* @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
<>	128:9bcdf88f62b0	4059	*/
<>	128:9bcdf88f62b0	4060	__STATIC_INLINE uint32_t LL_ADC_GetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel)
<>	128:9bcdf88f62b0	4061	{
<>	128:9bcdf88f62b0	4062	/* Note: Bit is located in comparator IP, but dedicated to ADC */
<>	128:9bcdf88f62b0	4063	return (uint32_t)(READ_BIT(COMP->CSR, Channel) >> POSITION_VAL(Channel));
<>	128:9bcdf88f62b0	4064	}
<>	128:9bcdf88f62b0	4065	#endif
<>	128:9bcdf88f62b0	4066
<>	128:9bcdf88f62b0	4067	/**
<>	128:9bcdf88f62b0	4068	* @}
<>	128:9bcdf88f62b0	4069	*/
<>	128:9bcdf88f62b0	4070
<>	128:9bcdf88f62b0	4071	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<>	128:9bcdf88f62b0	4072	* @{
<>	128:9bcdf88f62b0	4073	*/
<>	128:9bcdf88f62b0	4074
<>	128:9bcdf88f62b0	4075	/**
<>	128:9bcdf88f62b0	4076	* @brief Set ADC analog watchdog monitored channels:
<>	128:9bcdf88f62b0	4077	* a single channel or all channels,
<>	128:9bcdf88f62b0	4078	* on ADC groups regular and-or injected.
<>	128:9bcdf88f62b0	4079	* @note Once monitored channels are selected, analog watchdog
<>	128:9bcdf88f62b0	4080	* is enabled.
<>	128:9bcdf88f62b0	4081	* @note In case of need to define a single channel to monitor
<>	128:9bcdf88f62b0	4082	* with analog watchdog from sequencer channel definition,
<>	128:9bcdf88f62b0	4083	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<>	128:9bcdf88f62b0	4084	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	128:9bcdf88f62b0	4085	* instance:
<>	128:9bcdf88f62b0	4086	* - AWD standard (instance AWD1):
<>	128:9bcdf88f62b0	4087	* - channels monitored: can monitor 1 channel or all channels.
<>	128:9bcdf88f62b0	4088	* - groups monitored: ADC groups regular and-or injected.
<>	128:9bcdf88f62b0	4089	* - resolution: resolution is not limited (corresponds to
<>	128:9bcdf88f62b0	4090	* ADC resolution configured).
<>	128:9bcdf88f62b0	4091	* @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
<>	128:9bcdf88f62b0	4092	* CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
<>	128:9bcdf88f62b0	4093	* CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
<>	128:9bcdf88f62b0	4094	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4095	* @param AWDChannelGroup This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4096	* @arg @ref LL_ADC_AWD_DISABLE
<>	128:9bcdf88f62b0	4097	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	128:9bcdf88f62b0	4098	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	128:9bcdf88f62b0	4099	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	128:9bcdf88f62b0	4100	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
<>	128:9bcdf88f62b0	4101	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
<>	128:9bcdf88f62b0	4102	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
<>	128:9bcdf88f62b0	4103	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
<>	128:9bcdf88f62b0	4104	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
<>	128:9bcdf88f62b0	4105	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
<>	128:9bcdf88f62b0	4106	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
<>	128:9bcdf88f62b0	4107	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
<>	128:9bcdf88f62b0	4108	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
<>	128:9bcdf88f62b0	4109	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
<>	128:9bcdf88f62b0	4110	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
<>	128:9bcdf88f62b0	4111	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
<>	128:9bcdf88f62b0	4112	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
<>	128:9bcdf88f62b0	4113	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
<>	128:9bcdf88f62b0	4114	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
<>	128:9bcdf88f62b0	4115	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
<>	128:9bcdf88f62b0	4116	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
<>	128:9bcdf88f62b0	4117	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
<>	128:9bcdf88f62b0	4118	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
<>	128:9bcdf88f62b0	4119	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
<>	128:9bcdf88f62b0	4120	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
<>	128:9bcdf88f62b0	4121	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
<>	128:9bcdf88f62b0	4122	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
<>	128:9bcdf88f62b0	4123	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
<>	128:9bcdf88f62b0	4124	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
<>	128:9bcdf88f62b0	4125	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
<>	128:9bcdf88f62b0	4126	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
<>	128:9bcdf88f62b0	4127	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
<>	128:9bcdf88f62b0	4128	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
<>	128:9bcdf88f62b0	4129	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
<>	128:9bcdf88f62b0	4130	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
<>	128:9bcdf88f62b0	4131	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
<>	128:9bcdf88f62b0	4132	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
<>	128:9bcdf88f62b0	4133	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
<>	128:9bcdf88f62b0	4134	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
<>	128:9bcdf88f62b0	4135	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
<>	128:9bcdf88f62b0	4136	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
<>	128:9bcdf88f62b0	4137	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
<>	128:9bcdf88f62b0	4138	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
<>	128:9bcdf88f62b0	4139	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
<>	128:9bcdf88f62b0	4140	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
<>	128:9bcdf88f62b0	4141	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
<>	128:9bcdf88f62b0	4142	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
<>	128:9bcdf88f62b0	4143	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
<>	128:9bcdf88f62b0	4144	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
<>	128:9bcdf88f62b0	4145	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
<>	128:9bcdf88f62b0	4146	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
<>	128:9bcdf88f62b0	4147	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
<>	128:9bcdf88f62b0	4148	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
<>	128:9bcdf88f62b0	4149	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
<>	128:9bcdf88f62b0	4150	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
<>	128:9bcdf88f62b0	4151	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
<>	128:9bcdf88f62b0	4152	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
<>	128:9bcdf88f62b0	4153	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
<>	128:9bcdf88f62b0	4154	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
<>	128:9bcdf88f62b0	4155	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
<>	128:9bcdf88f62b0	4156	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
<>	128:9bcdf88f62b0	4157	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
<>	128:9bcdf88f62b0	4158	* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
<>	128:9bcdf88f62b0	4159	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
<>	128:9bcdf88f62b0	4160	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
<>	128:9bcdf88f62b0	4161	* @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
<>	128:9bcdf88f62b0	4162	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
<>	128:9bcdf88f62b0	4163	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
<>	128:9bcdf88f62b0	4164	* @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
<>	128:9bcdf88f62b0	4165	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
<>	128:9bcdf88f62b0	4166	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
<>	128:9bcdf88f62b0	4167	* @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
<>	128:9bcdf88f62b0	4168	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
<>	128:9bcdf88f62b0	4169	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
<>	128:9bcdf88f62b0	4170	* @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
<>	128:9bcdf88f62b0	4171	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
<>	128:9bcdf88f62b0	4172	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
<>	128:9bcdf88f62b0	4173	* @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
<>	128:9bcdf88f62b0	4174	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
<>	128:9bcdf88f62b0	4175	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
<>	128:9bcdf88f62b0	4176	* @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
<>	128:9bcdf88f62b0	4177	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
<>	128:9bcdf88f62b0	4178	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
<>	128:9bcdf88f62b0	4179	* @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
<>	128:9bcdf88f62b0	4180	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
<>	128:9bcdf88f62b0	4181	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
<>	128:9bcdf88f62b0	4182	* @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
<>	128:9bcdf88f62b0	4183	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4184	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
<>	128:9bcdf88f62b0	4185	* @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
<>	128:9bcdf88f62b0	4186	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4187	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
<>	128:9bcdf88f62b0	4188	* @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
<>	128:9bcdf88f62b0	4189	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4190	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
<>	128:9bcdf88f62b0	4191	* @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
<>	128:9bcdf88f62b0	4192	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4193	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
<>	128:9bcdf88f62b0	4194	* @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
<>	128:9bcdf88f62b0	4195	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4196	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3)
<>	128:9bcdf88f62b0	4197	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3)
<>	128:9bcdf88f62b0	4198	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3)
<>	128:9bcdf88f62b0	4199	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3)
<>	128:9bcdf88f62b0	4200	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3)
<>	128:9bcdf88f62b0	4201	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3)
<>	128:9bcdf88f62b0	4202	* @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3)
<>	128:9bcdf88f62b0	4203	* @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3)
<>	128:9bcdf88f62b0	4204	* @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3)
<>	128:9bcdf88f62b0	4205	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5)
<>	128:9bcdf88f62b0	4206	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5)
<>	128:9bcdf88f62b0	4207	* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	4208	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5)
<>	128:9bcdf88f62b0	4209	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5)
<>	128:9bcdf88f62b0	4210	* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	4211	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5)
<>	128:9bcdf88f62b0	4212	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5)
<>	128:9bcdf88f62b0	4213	* @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5)
<>	128:9bcdf88f62b0	4214	*
<>	128:9bcdf88f62b0	4215	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	4216	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	4217	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	4218	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
<>	128:9bcdf88f62b0	4219	* (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
<>	128:9bcdf88f62b0	4220	* @retval None
<>	128:9bcdf88f62b0	4221	*/
<>	128:9bcdf88f62b0	4222	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
<>	128:9bcdf88f62b0	4223	{
<>	128:9bcdf88f62b0	4224	MODIFY_REG(ADCx->CR1,
<>	128:9bcdf88f62b0	4225	(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH),
<>	128:9bcdf88f62b0	4226	AWDChannelGroup);
<>	128:9bcdf88f62b0	4227	}
<>	128:9bcdf88f62b0	4228
<>	128:9bcdf88f62b0	4229	/**
<>	128:9bcdf88f62b0	4230	* @brief Get ADC analog watchdog monitored channel.
<>	128:9bcdf88f62b0	4231	* @note Usage of the returned channel number:
<>	128:9bcdf88f62b0	4232	* - To reinject this channel into another function LL_ADC_xxx:
<>	128:9bcdf88f62b0	4233	* the returned channel number is only partly formatted on definition
<>	128:9bcdf88f62b0	4234	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	128:9bcdf88f62b0	4235	* with parts of literals LL_ADC_CHANNEL_x or using
<>	128:9bcdf88f62b0	4236	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	4237	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	128:9bcdf88f62b0	4238	* as parameter for another function.
<>	128:9bcdf88f62b0	4239	* - To get the channel number in decimal format:
<>	128:9bcdf88f62b0	4240	* process the returned value with the helper macro
<>	128:9bcdf88f62b0	4241	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	128:9bcdf88f62b0	4242	* Applicable only when the analog watchdog is set to monitor
<>	128:9bcdf88f62b0	4243	* one channel.
<>	128:9bcdf88f62b0	4244	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	128:9bcdf88f62b0	4245	* instance:
<>	128:9bcdf88f62b0	4246	* - AWD standard (instance AWD1):
<>	128:9bcdf88f62b0	4247	* - channels monitored: can monitor 1 channel or all channels.
<>	128:9bcdf88f62b0	4248	* - groups monitored: ADC groups regular and-or injected.
<>	128:9bcdf88f62b0	4249	* - resolution: resolution is not limited (corresponds to
<>	128:9bcdf88f62b0	4250	* ADC resolution configured).
<>	128:9bcdf88f62b0	4251	* @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
<>	128:9bcdf88f62b0	4252	* CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
<>	128:9bcdf88f62b0	4253	* CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
<>	128:9bcdf88f62b0	4254	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4255	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	4256	* @arg @ref LL_ADC_AWD_DISABLE
<>	128:9bcdf88f62b0	4257	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	128:9bcdf88f62b0	4258	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	128:9bcdf88f62b0	4259	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	128:9bcdf88f62b0	4260	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
<>	128:9bcdf88f62b0	4261	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
<>	128:9bcdf88f62b0	4262	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
<>	128:9bcdf88f62b0	4263	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
<>	128:9bcdf88f62b0	4264	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
<>	128:9bcdf88f62b0	4265	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
<>	128:9bcdf88f62b0	4266	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
<>	128:9bcdf88f62b0	4267	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
<>	128:9bcdf88f62b0	4268	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
<>	128:9bcdf88f62b0	4269	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
<>	128:9bcdf88f62b0	4270	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
<>	128:9bcdf88f62b0	4271	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
<>	128:9bcdf88f62b0	4272	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
<>	128:9bcdf88f62b0	4273	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
<>	128:9bcdf88f62b0	4274	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
<>	128:9bcdf88f62b0	4275	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
<>	128:9bcdf88f62b0	4276	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
<>	128:9bcdf88f62b0	4277	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
<>	128:9bcdf88f62b0	4278	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
<>	128:9bcdf88f62b0	4279	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
<>	128:9bcdf88f62b0	4280	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
<>	128:9bcdf88f62b0	4281	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
<>	128:9bcdf88f62b0	4282	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
<>	128:9bcdf88f62b0	4283	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
<>	128:9bcdf88f62b0	4284	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
<>	128:9bcdf88f62b0	4285	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
<>	128:9bcdf88f62b0	4286	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
<>	128:9bcdf88f62b0	4287	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
<>	128:9bcdf88f62b0	4288	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
<>	128:9bcdf88f62b0	4289	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
<>	128:9bcdf88f62b0	4290	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
<>	128:9bcdf88f62b0	4291	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
<>	128:9bcdf88f62b0	4292	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
<>	128:9bcdf88f62b0	4293	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
<>	128:9bcdf88f62b0	4294	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
<>	128:9bcdf88f62b0	4295	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
<>	128:9bcdf88f62b0	4296	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
<>	128:9bcdf88f62b0	4297	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
<>	128:9bcdf88f62b0	4298	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
<>	128:9bcdf88f62b0	4299	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
<>	128:9bcdf88f62b0	4300	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
<>	128:9bcdf88f62b0	4301	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
<>	128:9bcdf88f62b0	4302	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
<>	128:9bcdf88f62b0	4303	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
<>	128:9bcdf88f62b0	4304	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
<>	128:9bcdf88f62b0	4305	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
<>	128:9bcdf88f62b0	4306	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
<>	128:9bcdf88f62b0	4307	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
<>	128:9bcdf88f62b0	4308	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
<>	128:9bcdf88f62b0	4309	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
<>	128:9bcdf88f62b0	4310	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
<>	128:9bcdf88f62b0	4311	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
<>	128:9bcdf88f62b0	4312	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
<>	128:9bcdf88f62b0	4313	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
<>	128:9bcdf88f62b0	4314	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
<>	128:9bcdf88f62b0	4315	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
<>	128:9bcdf88f62b0	4316	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
<>	128:9bcdf88f62b0	4317	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
<>	128:9bcdf88f62b0	4318	* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
<>	128:9bcdf88f62b0	4319	* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
<>	128:9bcdf88f62b0	4320	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
<>	128:9bcdf88f62b0	4321	* @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
<>	128:9bcdf88f62b0	4322	* @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
<>	128:9bcdf88f62b0	4323	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
<>	128:9bcdf88f62b0	4324	* @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
<>	128:9bcdf88f62b0	4325	* @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
<>	128:9bcdf88f62b0	4326	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
<>	128:9bcdf88f62b0	4327	* @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
<>	128:9bcdf88f62b0	4328	* @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
<>	128:9bcdf88f62b0	4329	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
<>	128:9bcdf88f62b0	4330	* @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
<>	128:9bcdf88f62b0	4331	* @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
<>	128:9bcdf88f62b0	4332	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
<>	128:9bcdf88f62b0	4333	* @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
<>	128:9bcdf88f62b0	4334	* @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
<>	128:9bcdf88f62b0	4335	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
<>	128:9bcdf88f62b0	4336	* @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
<>	128:9bcdf88f62b0	4337	* @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
<>	128:9bcdf88f62b0	4338	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
<>	128:9bcdf88f62b0	4339	* @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
<>	128:9bcdf88f62b0	4340	* @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
<>	128:9bcdf88f62b0	4341	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
<>	128:9bcdf88f62b0	4342	* @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
<>	128:9bcdf88f62b0	4343	* @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4344	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
<>	128:9bcdf88f62b0	4345	* @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
<>	128:9bcdf88f62b0	4346	* @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4347	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
<>	128:9bcdf88f62b0	4348	* @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
<>	128:9bcdf88f62b0	4349	* @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4350	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
<>	128:9bcdf88f62b0	4351	* @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
<>	128:9bcdf88f62b0	4352	* @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4353	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
<>	128:9bcdf88f62b0	4354	* @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
<>	128:9bcdf88f62b0	4355	* @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
<>	128:9bcdf88f62b0	4356	*
<>	128:9bcdf88f62b0	4357	* (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
<>	128:9bcdf88f62b0	4358	* (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
<>	128:9bcdf88f62b0	4359	* (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
<>	128:9bcdf88f62b0	4360	* (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.
<>	128:9bcdf88f62b0	4361	*/
<>	128:9bcdf88f62b0	4362	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4363	{
<>	128:9bcdf88f62b0	4364	return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH)));
<>	128:9bcdf88f62b0	4365	}
<>	128:9bcdf88f62b0	4366
<>	128:9bcdf88f62b0	4367	/**
<>	128:9bcdf88f62b0	4368	* @brief Set ADC analog watchdog threshold value of threshold
<>	128:9bcdf88f62b0	4369	* high or low.
<>	128:9bcdf88f62b0	4370	* @note In case of ADC resolution different of 12 bits,
<>	128:9bcdf88f62b0	4371	* analog watchdog thresholds data require a specific shift.
<>	128:9bcdf88f62b0	4372	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	128:9bcdf88f62b0	4373	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	128:9bcdf88f62b0	4374	* instance:
<>	128:9bcdf88f62b0	4375	* - AWD standard (instance AWD1):
<>	128:9bcdf88f62b0	4376	* - channels monitored: can monitor 1 channel or all channels.
<>	128:9bcdf88f62b0	4377	* - groups monitored: ADC groups regular and-or injected.
<>	128:9bcdf88f62b0	4378	* - resolution: resolution is not limited (corresponds to
<>	128:9bcdf88f62b0	4379	* ADC resolution configured).
<>	128:9bcdf88f62b0	4380	* @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
<>	128:9bcdf88f62b0	4381	* LTR LT LL_ADC_SetAnalogWDThresholds
<>	128:9bcdf88f62b0	4382	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4383	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4384	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	128:9bcdf88f62b0	4385	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	128:9bcdf88f62b0	4386	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	4387	* @retval None
<>	128:9bcdf88f62b0	4388	*/
<>	128:9bcdf88f62b0	4389	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<>	128:9bcdf88f62b0	4390	{
<>	128:9bcdf88f62b0	4391	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	128:9bcdf88f62b0	4392
<>	128:9bcdf88f62b0	4393	MODIFY_REG(*preg,
<>	128:9bcdf88f62b0	4394	ADC_HTR_HT,
<>	128:9bcdf88f62b0	4395	AWDThresholdValue);
<>	128:9bcdf88f62b0	4396	}
<>	128:9bcdf88f62b0	4397
<>	128:9bcdf88f62b0	4398	/**
<>	128:9bcdf88f62b0	4399	* @brief Get ADC analog watchdog threshold value of threshold high or
<>	128:9bcdf88f62b0	4400	* threshold low.
<>	128:9bcdf88f62b0	4401	* @note In case of ADC resolution different of 12 bits,
<>	128:9bcdf88f62b0	4402	* analog watchdog thresholds data require a specific shift.
<>	128:9bcdf88f62b0	4403	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<>	128:9bcdf88f62b0	4404	* @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
<>	128:9bcdf88f62b0	4405	* LTR LT LL_ADC_GetAnalogWDThresholds
<>	128:9bcdf88f62b0	4406	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4407	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4408	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	128:9bcdf88f62b0	4409	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	128:9bcdf88f62b0	4410	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	4411	*/
<>	128:9bcdf88f62b0	4412	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
<>	128:9bcdf88f62b0	4413	{
<>	128:9bcdf88f62b0	4414	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	128:9bcdf88f62b0	4415
<>	128:9bcdf88f62b0	4416	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
<>	128:9bcdf88f62b0	4417	}
<>	128:9bcdf88f62b0	4418
<>	128:9bcdf88f62b0	4419	/**
<>	128:9bcdf88f62b0	4420	* @}
<>	128:9bcdf88f62b0	4421	*/
<>	128:9bcdf88f62b0	4422
<>	128:9bcdf88f62b0	4423	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<>	128:9bcdf88f62b0	4424	* @{
<>	128:9bcdf88f62b0	4425	*/
<>	128:9bcdf88f62b0	4426
<>	128:9bcdf88f62b0	4427	/**
<>	128:9bcdf88f62b0	4428	* @brief Enable the selected ADC instance.
<>	128:9bcdf88f62b0	4429	* @note On this STM32 serie, after ADC enable, a delay for
<>	128:9bcdf88f62b0	4430	* ADC internal analog stabilization is required before performing a
<>	128:9bcdf88f62b0	4431	* ADC conversion start.
<>	128:9bcdf88f62b0	4432	* Refer to device datasheet, parameter tSTAB.
<>	128:9bcdf88f62b0	4433	* @note Due to the latency introduced by the synchronization between
<>	128:9bcdf88f62b0	4434	* two clock domains (ADC clock source asynchronous),
<>	128:9bcdf88f62b0	4435	* some hardware constraints must be respected:
<>	128:9bcdf88f62b0	4436	* - ADC must be enabled (@ref LL_ADC_Enable() ) only
<>	128:9bcdf88f62b0	4437	* when ADC is not ready to convert.
<>	128:9bcdf88f62b0	4438	* - ADC must be disabled (@ref LL_ADC_Disable() ) only
<>	128:9bcdf88f62b0	4439	* when ADC is ready to convert.
<>	128:9bcdf88f62b0	4440	* Status of ADC ready to convert can be checked using function
<>	128:9bcdf88f62b0	4441	* @ref LL_ADC_IsActiveFlag_ADRDY().
<>	128:9bcdf88f62b0	4442	* @rmtoll CR2 ADON LL_ADC_Enable
<>	128:9bcdf88f62b0	4443	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4444	* @retval None
<>	128:9bcdf88f62b0	4445	*/
<>	128:9bcdf88f62b0	4446	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4447	{
<>	128:9bcdf88f62b0	4448	SET_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	128:9bcdf88f62b0	4449	}
<>	128:9bcdf88f62b0	4450
<>	128:9bcdf88f62b0	4451	/**
<>	128:9bcdf88f62b0	4452	* @brief Disable the selected ADC instance.
<>	128:9bcdf88f62b0	4453	* @note Due to the latency introduced by the synchronization between
<>	128:9bcdf88f62b0	4454	* two clock domains (ADC clock source asynchronous),
<>	128:9bcdf88f62b0	4455	* some hardware constraints must be respected:
<>	128:9bcdf88f62b0	4456	* - ADC must be enabled (@ref LL_ADC_Enable() ) only
<>	128:9bcdf88f62b0	4457	* when ADC is not ready to convert.
<>	128:9bcdf88f62b0	4458	* - ADC must be disabled (@ref LL_ADC_Disable() ) only
<>	128:9bcdf88f62b0	4459	* when ADC is ready to convert.
<>	128:9bcdf88f62b0	4460	* Status of ADC ready to convert can be checked using function
<>	128:9bcdf88f62b0	4461	* @ref LL_ADC_IsActiveFlag_ADRDY().
<>	128:9bcdf88f62b0	4462	* @rmtoll CR2 ADON LL_ADC_Disable
<>	128:9bcdf88f62b0	4463	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4464	* @retval None
<>	128:9bcdf88f62b0	4465	*/
<>	128:9bcdf88f62b0	4466	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4467	{
<>	128:9bcdf88f62b0	4468	CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	128:9bcdf88f62b0	4469	}
<>	128:9bcdf88f62b0	4470
<>	128:9bcdf88f62b0	4471	/**
<>	128:9bcdf88f62b0	4472	* @brief Get the selected ADC instance enable state.
<>	128:9bcdf88f62b0	4473	* @rmtoll CR2 ADON LL_ADC_IsEnabled
<>	128:9bcdf88f62b0	4474	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4475	* @retval 0: ADC is disabled, 1: ADC is enabled.
<>	128:9bcdf88f62b0	4476	*/
<>	128:9bcdf88f62b0	4477	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4478	{
<>	128:9bcdf88f62b0	4479	return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
<>	128:9bcdf88f62b0	4480	}
<>	128:9bcdf88f62b0	4481
<>	128:9bcdf88f62b0	4482	/**
<>	128:9bcdf88f62b0	4483	* @}
<>	128:9bcdf88f62b0	4484	*/
<>	128:9bcdf88f62b0	4485
<>	128:9bcdf88f62b0	4486	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<>	128:9bcdf88f62b0	4487	* @{
<>	128:9bcdf88f62b0	4488	*/
<>	128:9bcdf88f62b0	4489
<>	128:9bcdf88f62b0	4490	/**
<>	128:9bcdf88f62b0	4491	* @brief Start ADC group regular conversion.
<>	128:9bcdf88f62b0	4492	* @note On this STM32 serie, this function is relevant only for
<>	128:9bcdf88f62b0	4493	* internal trigger (SW start), not for external trigger:
<>	128:9bcdf88f62b0	4494	* - If ADC trigger has been set to software start, ADC conversion
<>	128:9bcdf88f62b0	4495	* starts immediately.
<>	128:9bcdf88f62b0	4496	* - If ADC trigger has been set to external trigger, ADC conversion
<>	128:9bcdf88f62b0	4497	* start must be performed using function
<>	128:9bcdf88f62b0	4498	* @ref LL_ADC_REG_StartConversionExtTrig().
<>	128:9bcdf88f62b0	4499	* (if external trigger edge would have been set during ADC other
<>	128:9bcdf88f62b0	4500	* settings, ADC conversion would start at trigger event
<>	128:9bcdf88f62b0	4501	* as soon as ADC is enabled).
<>	128:9bcdf88f62b0	4502	* @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
<>	128:9bcdf88f62b0	4503	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4504	* @retval None
<>	128:9bcdf88f62b0	4505	*/
<>	128:9bcdf88f62b0	4506	__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4507	{
<>	128:9bcdf88f62b0	4508	SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
<>	128:9bcdf88f62b0	4509	}
<>	128:9bcdf88f62b0	4510
<>	128:9bcdf88f62b0	4511	/**
<>	128:9bcdf88f62b0	4512	* @brief Start ADC group regular conversion from external trigger.
<>	128:9bcdf88f62b0	4513	* @note ADC conversion will start at next trigger event (on the selected
<>	128:9bcdf88f62b0	4514	* trigger edge) following the ADC start conversion command.
<>	128:9bcdf88f62b0	4515	* @note On this STM32 serie, this function is relevant for
<>	128:9bcdf88f62b0	4516	* ADC conversion start from external trigger.
<>	128:9bcdf88f62b0	4517	* If internal trigger (SW start) is needed, perform ADC conversion
<>	128:9bcdf88f62b0	4518	* start using function @ref LL_ADC_REG_StartConversionSWStart().
<>	128:9bcdf88f62b0	4519	* @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
<>	128:9bcdf88f62b0	4520	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4521	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	128:9bcdf88f62b0	4522	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	128:9bcdf88f62b0	4523	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	128:9bcdf88f62b0	4524	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4525	* @retval None
<>	128:9bcdf88f62b0	4526	*/
<>	128:9bcdf88f62b0	4527	__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	128:9bcdf88f62b0	4528	{
<>	128:9bcdf88f62b0	4529	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	128:9bcdf88f62b0	4530	}
<>	128:9bcdf88f62b0	4531
<>	128:9bcdf88f62b0	4532	/**
<>	128:9bcdf88f62b0	4533	* @brief Stop ADC group regular conversion from external trigger.
<>	128:9bcdf88f62b0	4534	* @note No more ADC conversion will start at next trigger event
<>	128:9bcdf88f62b0	4535	* following the ADC stop conversion command.
<>	128:9bcdf88f62b0	4536	* If a conversion is on-going, it will be completed.
<>	128:9bcdf88f62b0	4537	* @note On this STM32 serie, there is no specific command
<>	128:9bcdf88f62b0	4538	* to stop a conversion on-going or to stop ADC converting
<>	128:9bcdf88f62b0	4539	* in continuous mode. These actions can be performed
<>	128:9bcdf88f62b0	4540	* using function @ref LL_ADC_Disable().
<>	128:9bcdf88f62b0	4541	* @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
<>	128:9bcdf88f62b0	4542	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4543	* @retval None
<>	128:9bcdf88f62b0	4544	*/
<>	128:9bcdf88f62b0	4545	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4546	{
<>	128:9bcdf88f62b0	4547	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
<>	128:9bcdf88f62b0	4548	}
<>	128:9bcdf88f62b0	4549
<>	128:9bcdf88f62b0	4550	/**
<>	128:9bcdf88f62b0	4551	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4552	* all ADC configurations: all ADC resolutions and
<>	128:9bcdf88f62b0	4553	* all oversampling increased data width (for devices
<>	128:9bcdf88f62b0	4554	* with feature oversampling).
<>	128:9bcdf88f62b0	4555	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
<>	128:9bcdf88f62b0	4556	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4557	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	128:9bcdf88f62b0	4558	*/
<>	128:9bcdf88f62b0	4559	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4560	{
<>	128:9bcdf88f62b0	4561	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	128:9bcdf88f62b0	4562	}
<>	128:9bcdf88f62b0	4563
<>	128:9bcdf88f62b0	4564	/**
<>	128:9bcdf88f62b0	4565	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4566	* ADC resolution 12 bits.
<>	128:9bcdf88f62b0	4567	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4568	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4569	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	128:9bcdf88f62b0	4570	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
<>	128:9bcdf88f62b0	4571	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4572	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	4573	*/
<>	128:9bcdf88f62b0	4574	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4575	{
<>	128:9bcdf88f62b0	4576	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	128:9bcdf88f62b0	4577	}
<>	128:9bcdf88f62b0	4578
<>	128:9bcdf88f62b0	4579	/**
<>	128:9bcdf88f62b0	4580	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4581	* ADC resolution 10 bits.
<>	128:9bcdf88f62b0	4582	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4583	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4584	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	128:9bcdf88f62b0	4585	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
<>	128:9bcdf88f62b0	4586	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4587	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	128:9bcdf88f62b0	4588	*/
<>	128:9bcdf88f62b0	4589	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4590	{
<>	128:9bcdf88f62b0	4591	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	128:9bcdf88f62b0	4592	}
<>	128:9bcdf88f62b0	4593
<>	128:9bcdf88f62b0	4594	/**
<>	128:9bcdf88f62b0	4595	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4596	* ADC resolution 8 bits.
<>	128:9bcdf88f62b0	4597	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4598	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4599	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	128:9bcdf88f62b0	4600	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
<>	128:9bcdf88f62b0	4601	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4602	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	4603	*/
<>	128:9bcdf88f62b0	4604	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4605	{
<>	128:9bcdf88f62b0	4606	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	128:9bcdf88f62b0	4607	}
<>	128:9bcdf88f62b0	4608
<>	128:9bcdf88f62b0	4609	/**
<>	128:9bcdf88f62b0	4610	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4611	* ADC resolution 6 bits.
<>	128:9bcdf88f62b0	4612	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4613	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4614	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	128:9bcdf88f62b0	4615	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
<>	128:9bcdf88f62b0	4616	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4617	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	128:9bcdf88f62b0	4618	*/
<>	128:9bcdf88f62b0	4619	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4620	{
<>	128:9bcdf88f62b0	4621	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	128:9bcdf88f62b0	4622	}
<>	128:9bcdf88f62b0	4623
<>	128:9bcdf88f62b0	4624	/**
<>	128:9bcdf88f62b0	4625	* @}
<>	128:9bcdf88f62b0	4626	*/
<>	128:9bcdf88f62b0	4627
<>	128:9bcdf88f62b0	4628	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
<>	128:9bcdf88f62b0	4629	* @{
<>	128:9bcdf88f62b0	4630	*/
<>	128:9bcdf88f62b0	4631
<>	128:9bcdf88f62b0	4632	/**
<>	128:9bcdf88f62b0	4633	* @brief Start ADC group injected conversion.
<>	128:9bcdf88f62b0	4634	* @note On this STM32 serie, this function is relevant only for
<>	128:9bcdf88f62b0	4635	* internal trigger (SW start), not for external trigger:
<>	128:9bcdf88f62b0	4636	* - If ADC trigger has been set to software start, ADC conversion
<>	128:9bcdf88f62b0	4637	* starts immediately.
<>	128:9bcdf88f62b0	4638	* - If ADC trigger has been set to external trigger, ADC conversion
<>	128:9bcdf88f62b0	4639	* start must be performed using function
<>	128:9bcdf88f62b0	4640	* @ref LL_ADC_INJ_StartConversionExtTrig().
<>	128:9bcdf88f62b0	4641	* (if external trigger edge would have been set during ADC other
<>	128:9bcdf88f62b0	4642	* settings, ADC conversion would start at trigger event
<>	128:9bcdf88f62b0	4643	* as soon as ADC is enabled).
<>	128:9bcdf88f62b0	4644	* @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
<>	128:9bcdf88f62b0	4645	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4646	* @retval None
<>	128:9bcdf88f62b0	4647	*/
<>	128:9bcdf88f62b0	4648	__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4649	{
<>	128:9bcdf88f62b0	4650	SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
<>	128:9bcdf88f62b0	4651	}
<>	128:9bcdf88f62b0	4652
<>	128:9bcdf88f62b0	4653	/**
<>	128:9bcdf88f62b0	4654	* @brief Start ADC group injected conversion from external trigger.
<>	128:9bcdf88f62b0	4655	* @note ADC conversion will start at next trigger event (on the selected
<>	128:9bcdf88f62b0	4656	* trigger edge) following the ADC start conversion command.
<>	128:9bcdf88f62b0	4657	* @note On this STM32 serie, this function is relevant for
<>	128:9bcdf88f62b0	4658	* ADC conversion start from external trigger.
<>	128:9bcdf88f62b0	4659	* If internal trigger (SW start) is needed, perform ADC conversion
<>	128:9bcdf88f62b0	4660	* start using function @ref LL_ADC_INJ_StartConversionSWStart().
<>	128:9bcdf88f62b0	4661	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
<>	128:9bcdf88f62b0	4662	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4663	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	128:9bcdf88f62b0	4664	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	128:9bcdf88f62b0	4665	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	128:9bcdf88f62b0	4666	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4667	* @retval None
<>	128:9bcdf88f62b0	4668	*/
<>	128:9bcdf88f62b0	4669	__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	128:9bcdf88f62b0	4670	{
<>	128:9bcdf88f62b0	4671	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	128:9bcdf88f62b0	4672	}
<>	128:9bcdf88f62b0	4673
<>	128:9bcdf88f62b0	4674	/**
<>	128:9bcdf88f62b0	4675	* @brief Stop ADC group injected conversion from external trigger.
<>	128:9bcdf88f62b0	4676	* @note No more ADC conversion will start at next trigger event
<>	128:9bcdf88f62b0	4677	* following the ADC stop conversion command.
<>	128:9bcdf88f62b0	4678	* If a conversion is on-going, it will be completed.
<>	128:9bcdf88f62b0	4679	* @note On this STM32 serie, there is no specific command
<>	128:9bcdf88f62b0	4680	* to stop a conversion on-going or to stop ADC converting
<>	128:9bcdf88f62b0	4681	* in continuous mode. These actions can be performed
<>	128:9bcdf88f62b0	4682	* using function @ref LL_ADC_Disable().
<>	128:9bcdf88f62b0	4683	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
<>	128:9bcdf88f62b0	4684	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4685	* @retval None
<>	128:9bcdf88f62b0	4686	*/
<>	128:9bcdf88f62b0	4687	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4688	{
<>	128:9bcdf88f62b0	4689	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
<>	128:9bcdf88f62b0	4690	}
<>	128:9bcdf88f62b0	4691
<>	128:9bcdf88f62b0	4692	/**
<>	128:9bcdf88f62b0	4693	* @brief Get ADC group regular conversion data, range fit for
<>	128:9bcdf88f62b0	4694	* all ADC configurations: all ADC resolutions and
<>	128:9bcdf88f62b0	4695	* all oversampling increased data width (for devices
<>	128:9bcdf88f62b0	4696	* with feature oversampling).
<>	128:9bcdf88f62b0	4697	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	128:9bcdf88f62b0	4698	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	128:9bcdf88f62b0	4699	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	128:9bcdf88f62b0	4700	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
<>	128:9bcdf88f62b0	4701	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4702	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4703	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	4704	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	4705	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	4706	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	4707	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	128:9bcdf88f62b0	4708	*/
<>	128:9bcdf88f62b0	4709	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	4710	{
<>	128:9bcdf88f62b0	4711	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	4712
<>	128:9bcdf88f62b0	4713	return (uint32_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	4714	ADC_JDR1_JDATA)
<>	128:9bcdf88f62b0	4715	);
<>	128:9bcdf88f62b0	4716	}
<>	128:9bcdf88f62b0	4717
<>	128:9bcdf88f62b0	4718	/**
<>	128:9bcdf88f62b0	4719	* @brief Get ADC group injected conversion data, range fit for
<>	128:9bcdf88f62b0	4720	* ADC resolution 12 bits.
<>	128:9bcdf88f62b0	4721	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4722	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4723	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	128:9bcdf88f62b0	4724	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	128:9bcdf88f62b0	4725	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	128:9bcdf88f62b0	4726	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	128:9bcdf88f62b0	4727	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
<>	128:9bcdf88f62b0	4728	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4729	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4730	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	4731	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	4732	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	4733	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	4734	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	128:9bcdf88f62b0	4735	*/
<>	128:9bcdf88f62b0	4736	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	4737	{
<>	128:9bcdf88f62b0	4738	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	4739
<>	128:9bcdf88f62b0	4740	return (uint16_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	4741	ADC_JDR1_JDATA)
<>	128:9bcdf88f62b0	4742	);
<>	128:9bcdf88f62b0	4743	}
<>	128:9bcdf88f62b0	4744
<>	128:9bcdf88f62b0	4745	/**
<>	128:9bcdf88f62b0	4746	* @brief Get ADC group injected conversion data, range fit for
<>	128:9bcdf88f62b0	4747	* ADC resolution 10 bits.
<>	128:9bcdf88f62b0	4748	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4749	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4750	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	128:9bcdf88f62b0	4751	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	128:9bcdf88f62b0	4752	* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	128:9bcdf88f62b0	4753	* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	128:9bcdf88f62b0	4754	* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
<>	128:9bcdf88f62b0	4755	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4756	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4757	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	4758	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	4759	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	4760	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	4761	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	128:9bcdf88f62b0	4762	*/
<>	128:9bcdf88f62b0	4763	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	4764	{
<>	128:9bcdf88f62b0	4765	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	4766
<>	128:9bcdf88f62b0	4767	return (uint16_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	4768	ADC_JDR1_JDATA)
<>	128:9bcdf88f62b0	4769	);
<>	128:9bcdf88f62b0	4770	}
<>	128:9bcdf88f62b0	4771
<>	128:9bcdf88f62b0	4772	/**
<>	128:9bcdf88f62b0	4773	* @brief Get ADC group injected conversion data, range fit for
<>	128:9bcdf88f62b0	4774	* ADC resolution 8 bits.
<>	128:9bcdf88f62b0	4775	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4776	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4777	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	128:9bcdf88f62b0	4778	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	128:9bcdf88f62b0	4779	* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	128:9bcdf88f62b0	4780	* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	128:9bcdf88f62b0	4781	* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
<>	128:9bcdf88f62b0	4782	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4783	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4784	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	4785	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	4786	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	4787	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	4788	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	128:9bcdf88f62b0	4789	*/
<>	128:9bcdf88f62b0	4790	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	4791	{
<>	128:9bcdf88f62b0	4792	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	4793
<>	128:9bcdf88f62b0	4794	return (uint8_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	4795	ADC_JDR1_JDATA)
<>	128:9bcdf88f62b0	4796	);
<>	128:9bcdf88f62b0	4797	}
<>	128:9bcdf88f62b0	4798
<>	128:9bcdf88f62b0	4799	/**
<>	128:9bcdf88f62b0	4800	* @brief Get ADC group injected conversion data, range fit for
<>	128:9bcdf88f62b0	4801	* ADC resolution 6 bits.
<>	128:9bcdf88f62b0	4802	* @note For devices with feature oversampling: Oversampling
<>	128:9bcdf88f62b0	4803	* can increase data width, function for extended range
<>	128:9bcdf88f62b0	4804	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	128:9bcdf88f62b0	4805	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	128:9bcdf88f62b0	4806	* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	128:9bcdf88f62b0	4807	* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	128:9bcdf88f62b0	4808	* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
<>	128:9bcdf88f62b0	4809	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4810	* @param Rank This parameter can be one of the following values:
<>	128:9bcdf88f62b0	4811	* @arg @ref LL_ADC_INJ_RANK_1
<>	128:9bcdf88f62b0	4812	* @arg @ref LL_ADC_INJ_RANK_2
<>	128:9bcdf88f62b0	4813	* @arg @ref LL_ADC_INJ_RANK_3
<>	128:9bcdf88f62b0	4814	* @arg @ref LL_ADC_INJ_RANK_4
<>	128:9bcdf88f62b0	4815	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	128:9bcdf88f62b0	4816	*/
<>	128:9bcdf88f62b0	4817	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
<>	128:9bcdf88f62b0	4818	{
<>	128:9bcdf88f62b0	4819	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	128:9bcdf88f62b0	4820
<>	128:9bcdf88f62b0	4821	return (uint8_t)(READ_BIT(*preg,
<>	128:9bcdf88f62b0	4822	ADC_JDR1_JDATA)
<>	128:9bcdf88f62b0	4823	);
<>	128:9bcdf88f62b0	4824	}
<>	128:9bcdf88f62b0	4825
<>	128:9bcdf88f62b0	4826	/**
<>	128:9bcdf88f62b0	4827	* @}
<>	128:9bcdf88f62b0	4828	*/
<>	128:9bcdf88f62b0	4829
<>	128:9bcdf88f62b0	4830	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<>	128:9bcdf88f62b0	4831	* @{
<>	128:9bcdf88f62b0	4832	*/
<>	128:9bcdf88f62b0	4833
<>	128:9bcdf88f62b0	4834	/**
<>	128:9bcdf88f62b0	4835	* @brief Get flag ADC ready.
<>	128:9bcdf88f62b0	4836	* @rmtoll SR ADONS LL_ADC_IsActiveFlag_ADRDY
<>	128:9bcdf88f62b0	4837	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4838	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	4839	*/
<>	128:9bcdf88f62b0	4840	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4841	{
<>	128:9bcdf88f62b0	4842	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
<>	128:9bcdf88f62b0	4843	}
<>	128:9bcdf88f62b0	4844
<>	128:9bcdf88f62b0	4845	/**
<>	128:9bcdf88f62b0	4846	* @brief Get flag ADC group regular end of unitary conversion
<>	128:9bcdf88f62b0	4847	* or end of sequence conversions, depending on
<>	128:9bcdf88f62b0	4848	* ADC configuration.
<>	128:9bcdf88f62b0	4849	* @note To configure flag of end of conversion,
<>	128:9bcdf88f62b0	4850	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	128:9bcdf88f62b0	4851	* @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
<>	128:9bcdf88f62b0	4852	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4853	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	4854	*/
<>	128:9bcdf88f62b0	4855	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4856	{
<>	128:9bcdf88f62b0	4857	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
<>	128:9bcdf88f62b0	4858	}
<>	128:9bcdf88f62b0	4859
<>	128:9bcdf88f62b0	4860	/**
<>	128:9bcdf88f62b0	4861	* @brief Get flag ADC group regular overrun.
<>	128:9bcdf88f62b0	4862	* @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
<>	128:9bcdf88f62b0	4863	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4864	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	4865	*/
<>	128:9bcdf88f62b0	4866	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4867	{
<>	128:9bcdf88f62b0	4868	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<>	128:9bcdf88f62b0	4869	}
<>	128:9bcdf88f62b0	4870
<>	128:9bcdf88f62b0	4871
<>	128:9bcdf88f62b0	4872	/**
<>	128:9bcdf88f62b0	4873	* @brief Get flag ADC group injected end of sequence conversions.
<>	128:9bcdf88f62b0	4874	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
<>	128:9bcdf88f62b0	4875	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4876	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	4877	*/
<>	128:9bcdf88f62b0	4878	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4879	{
<>	128:9bcdf88f62b0	4880	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	128:9bcdf88f62b0	4881	/* end of unitary conversion. */
<>	128:9bcdf88f62b0	4882	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	128:9bcdf88f62b0	4883	/* in other STM32 families). */
<>	128:9bcdf88f62b0	4884	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
<>	128:9bcdf88f62b0	4885	}
<>	128:9bcdf88f62b0	4886
<>	128:9bcdf88f62b0	4887	/**
<>	128:9bcdf88f62b0	4888	* @brief Get flag ADC analog watchdog 1 flag
<>	128:9bcdf88f62b0	4889	* @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
<>	128:9bcdf88f62b0	4890	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4891	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	4892	*/
<>	128:9bcdf88f62b0	4893	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4894	{
<>	128:9bcdf88f62b0	4895	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<>	128:9bcdf88f62b0	4896	}
<>	128:9bcdf88f62b0	4897
<>	128:9bcdf88f62b0	4898	/**
<>	128:9bcdf88f62b0	4899	* @brief Clear flag ADC group regular end of unitary conversion
<>	128:9bcdf88f62b0	4900	* or end of sequence conversions, depending on
<>	128:9bcdf88f62b0	4901	* ADC configuration.
<>	128:9bcdf88f62b0	4902	* @note To configure flag of end of conversion,
<>	128:9bcdf88f62b0	4903	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	128:9bcdf88f62b0	4904	* @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
<>	128:9bcdf88f62b0	4905	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4906	* @retval None
<>	128:9bcdf88f62b0	4907	*/
<>	128:9bcdf88f62b0	4908	__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4909	{
<>	128:9bcdf88f62b0	4910	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
<>	128:9bcdf88f62b0	4911	}
<>	128:9bcdf88f62b0	4912
<>	128:9bcdf88f62b0	4913	/**
<>	128:9bcdf88f62b0	4914	* @brief Clear flag ADC group regular overrun.
<>	128:9bcdf88f62b0	4915	* @rmtoll SR OVR LL_ADC_ClearFlag_OVR
<>	128:9bcdf88f62b0	4916	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4917	* @retval None
<>	128:9bcdf88f62b0	4918	*/
<>	128:9bcdf88f62b0	4919	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4920	{
<>	128:9bcdf88f62b0	4921	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
<>	128:9bcdf88f62b0	4922	}
<>	128:9bcdf88f62b0	4923
<>	128:9bcdf88f62b0	4924
<>	128:9bcdf88f62b0	4925	/**
<>	128:9bcdf88f62b0	4926	* @brief Clear flag ADC group injected end of sequence conversions.
<>	128:9bcdf88f62b0	4927	* @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
<>	128:9bcdf88f62b0	4928	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4929	* @retval None
<>	128:9bcdf88f62b0	4930	*/
<>	128:9bcdf88f62b0	4931	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4932	{
<>	128:9bcdf88f62b0	4933	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	128:9bcdf88f62b0	4934	/* end of unitary conversion. */
<>	128:9bcdf88f62b0	4935	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	128:9bcdf88f62b0	4936	/* in other STM32 families). */
<>	128:9bcdf88f62b0	4937	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
<>	128:9bcdf88f62b0	4938	}
<>	128:9bcdf88f62b0	4939
<>	128:9bcdf88f62b0	4940	/**
<>	128:9bcdf88f62b0	4941	* @brief Clear flag ADC analog watchdog 1.
<>	128:9bcdf88f62b0	4942	* @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
<>	128:9bcdf88f62b0	4943	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4944	* @retval None
<>	128:9bcdf88f62b0	4945	*/
<>	128:9bcdf88f62b0	4946	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4947	{
<>	128:9bcdf88f62b0	4948	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
<>	128:9bcdf88f62b0	4949	}
<>	128:9bcdf88f62b0	4950
<>	128:9bcdf88f62b0	4951	/**
<>	128:9bcdf88f62b0	4952	* @}
<>	128:9bcdf88f62b0	4953	*/
<>	128:9bcdf88f62b0	4954
<>	128:9bcdf88f62b0	4955	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
<>	128:9bcdf88f62b0	4956	* @{
<>	128:9bcdf88f62b0	4957	*/
<>	128:9bcdf88f62b0	4958
<>	128:9bcdf88f62b0	4959	/**
<>	128:9bcdf88f62b0	4960	* @brief Enable interruption ADC group regular end of unitary conversion
<>	128:9bcdf88f62b0	4961	* or end of sequence conversions, depending on
<>	128:9bcdf88f62b0	4962	* ADC configuration.
<>	128:9bcdf88f62b0	4963	* @note To configure flag of end of conversion,
<>	128:9bcdf88f62b0	4964	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	128:9bcdf88f62b0	4965	* @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
<>	128:9bcdf88f62b0	4966	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4967	* @retval None
<>	128:9bcdf88f62b0	4968	*/
<>	128:9bcdf88f62b0	4969	__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4970	{
<>	128:9bcdf88f62b0	4971	SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	128:9bcdf88f62b0	4972	}
<>	128:9bcdf88f62b0	4973
<>	128:9bcdf88f62b0	4974	/**
<>	128:9bcdf88f62b0	4975	* @brief Enable ADC group regular interruption overrun.
<>	128:9bcdf88f62b0	4976	* @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
<>	128:9bcdf88f62b0	4977	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4978	* @retval None
<>	128:9bcdf88f62b0	4979	*/
<>	128:9bcdf88f62b0	4980	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4981	{
<>	128:9bcdf88f62b0	4982	SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	128:9bcdf88f62b0	4983	}
<>	128:9bcdf88f62b0	4984
<>	128:9bcdf88f62b0	4985
<>	128:9bcdf88f62b0	4986	/**
<>	128:9bcdf88f62b0	4987	* @brief Enable interruption ADC group injected end of sequence conversions.
<>	128:9bcdf88f62b0	4988	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	128:9bcdf88f62b0	4989	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	4990	* @retval None
<>	128:9bcdf88f62b0	4991	*/
<>	128:9bcdf88f62b0	4992	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	4993	{
<>	128:9bcdf88f62b0	4994	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	128:9bcdf88f62b0	4995	/* end of unitary conversion. */
<>	128:9bcdf88f62b0	4996	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	128:9bcdf88f62b0	4997	/* in other STM32 families). */
<>	128:9bcdf88f62b0	4998	SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	128:9bcdf88f62b0	4999	}
<>	128:9bcdf88f62b0	5000
<>	128:9bcdf88f62b0	5001	/**
<>	128:9bcdf88f62b0	5002	* @brief Enable interruption ADC analog watchdog 1.
<>	128:9bcdf88f62b0	5003	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	128:9bcdf88f62b0	5004	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5005	* @retval None
<>	128:9bcdf88f62b0	5006	*/
<>	128:9bcdf88f62b0	5007	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5008	{
<>	128:9bcdf88f62b0	5009	SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	128:9bcdf88f62b0	5010	}
<>	128:9bcdf88f62b0	5011
<>	128:9bcdf88f62b0	5012	/**
<>	128:9bcdf88f62b0	5013	* @brief Disable interruption ADC group regular end of unitary conversion
<>	128:9bcdf88f62b0	5014	* or end of sequence conversions, depending on
<>	128:9bcdf88f62b0	5015	* ADC configuration.
<>	128:9bcdf88f62b0	5016	* @note To configure flag of end of conversion,
<>	128:9bcdf88f62b0	5017	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	128:9bcdf88f62b0	5018	* @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
<>	128:9bcdf88f62b0	5019	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5020	* @retval None
<>	128:9bcdf88f62b0	5021	*/
<>	128:9bcdf88f62b0	5022	__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5023	{
<>	128:9bcdf88f62b0	5024	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	128:9bcdf88f62b0	5025	}
<>	128:9bcdf88f62b0	5026
<>	128:9bcdf88f62b0	5027	/**
<>	128:9bcdf88f62b0	5028	* @brief Disable interruption ADC group regular overrun.
<>	128:9bcdf88f62b0	5029	* @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
<>	128:9bcdf88f62b0	5030	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5031	* @retval None
<>	128:9bcdf88f62b0	5032	*/
<>	128:9bcdf88f62b0	5033	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5034	{
<>	128:9bcdf88f62b0	5035	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	128:9bcdf88f62b0	5036	}
<>	128:9bcdf88f62b0	5037
<>	128:9bcdf88f62b0	5038
<>	128:9bcdf88f62b0	5039	/**
<>	128:9bcdf88f62b0	5040	* @brief Disable interruption ADC group injected end of sequence conversions.
<>	128:9bcdf88f62b0	5041	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	128:9bcdf88f62b0	5042	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5043	* @retval None
<>	128:9bcdf88f62b0	5044	*/
<>	128:9bcdf88f62b0	5045	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5046	{
<>	128:9bcdf88f62b0	5047	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	128:9bcdf88f62b0	5048	/* end of unitary conversion. */
<>	128:9bcdf88f62b0	5049	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	128:9bcdf88f62b0	5050	/* in other STM32 families). */
<>	128:9bcdf88f62b0	5051	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	128:9bcdf88f62b0	5052	}
<>	128:9bcdf88f62b0	5053
<>	128:9bcdf88f62b0	5054	/**
<>	128:9bcdf88f62b0	5055	* @brief Disable interruption ADC analog watchdog 1.
<>	128:9bcdf88f62b0	5056	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	128:9bcdf88f62b0	5057	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5058	* @retval None
<>	128:9bcdf88f62b0	5059	*/
<>	128:9bcdf88f62b0	5060	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5061	{
<>	128:9bcdf88f62b0	5062	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	128:9bcdf88f62b0	5063	}
<>	128:9bcdf88f62b0	5064
<>	128:9bcdf88f62b0	5065	/**
<>	128:9bcdf88f62b0	5066	* @brief Get state of interruption ADC group regular end of unitary conversion
<>	128:9bcdf88f62b0	5067	* or end of sequence conversions, depending on
<>	128:9bcdf88f62b0	5068	* ADC configuration.
<>	128:9bcdf88f62b0	5069	* @note To configure flag of end of conversion,
<>	128:9bcdf88f62b0	5070	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	128:9bcdf88f62b0	5071	* (0: interrupt disabled, 1: interrupt enabled)
<>	128:9bcdf88f62b0	5072	* @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
<>	128:9bcdf88f62b0	5073	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5074	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	5075	*/
<>	128:9bcdf88f62b0	5076	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5077	{
<>	128:9bcdf88f62b0	5078	return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
<>	128:9bcdf88f62b0	5079	}
<>	128:9bcdf88f62b0	5080
<>	128:9bcdf88f62b0	5081	/**
<>	128:9bcdf88f62b0	5082	* @brief Get state of interruption ADC group regular overrun
<>	128:9bcdf88f62b0	5083	* (0: interrupt disabled, 1: interrupt enabled).
<>	128:9bcdf88f62b0	5084	* @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
<>	128:9bcdf88f62b0	5085	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5086	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	5087	*/
<>	128:9bcdf88f62b0	5088	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5089	{
<>	128:9bcdf88f62b0	5090	return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<>	128:9bcdf88f62b0	5091	}
<>	128:9bcdf88f62b0	5092
<>	128:9bcdf88f62b0	5093
<>	128:9bcdf88f62b0	5094	/**
<>	128:9bcdf88f62b0	5095	* @brief Get state of interruption ADC group injected end of sequence conversions
<>	128:9bcdf88f62b0	5096	* (0: interrupt disabled, 1: interrupt enabled).
<>	128:9bcdf88f62b0	5097	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	128:9bcdf88f62b0	5098	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5099	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	5100	*/
<>	128:9bcdf88f62b0	5101	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5102	{
<>	128:9bcdf88f62b0	5103	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	128:9bcdf88f62b0	5104	/* end of unitary conversion. */
<>	128:9bcdf88f62b0	5105	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	128:9bcdf88f62b0	5106	/* in other STM32 families). */
<>	128:9bcdf88f62b0	5107	return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
<>	128:9bcdf88f62b0	5108	}
<>	128:9bcdf88f62b0	5109
<>	128:9bcdf88f62b0	5110	/**
<>	128:9bcdf88f62b0	5111	* @brief Get state of interruption ADC analog watchdog 1
<>	128:9bcdf88f62b0	5112	* (0: interrupt disabled, 1: interrupt enabled).
<>	128:9bcdf88f62b0	5113	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	128:9bcdf88f62b0	5114	* @param ADCx ADC instance
<>	128:9bcdf88f62b0	5115	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	5116	*/
<>	128:9bcdf88f62b0	5117	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<>	128:9bcdf88f62b0	5118	{
<>	128:9bcdf88f62b0	5119	return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<>	128:9bcdf88f62b0	5120	}
<>	128:9bcdf88f62b0	5121
<>	128:9bcdf88f62b0	5122	/**
<>	128:9bcdf88f62b0	5123	* @}
<>	128:9bcdf88f62b0	5124	*/
<>	128:9bcdf88f62b0	5125
<>	128:9bcdf88f62b0	5126	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	5127	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<>	128:9bcdf88f62b0	5128	* @{
<>	128:9bcdf88f62b0	5129	*/
<>	128:9bcdf88f62b0	5130
<>	128:9bcdf88f62b0	5131	/* Initialization of some features of ADC common parameters and multimode */
<>	128:9bcdf88f62b0	5132	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<>	128:9bcdf88f62b0	5133	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct);
<>	128:9bcdf88f62b0	5134	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
<>	128:9bcdf88f62b0	5135
<>	128:9bcdf88f62b0	5136	/* De-initialization of ADC instance, ADC group regular and ADC group injected */
<>	128:9bcdf88f62b0	5137	/* (availability of ADC group injected depends on STM32 families) */
<>	128:9bcdf88f62b0	5138	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<>	128:9bcdf88f62b0	5139
<>	128:9bcdf88f62b0	5140	/* Initialization of some features of ADC instance */
<>	128:9bcdf88f62b0	5141	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
<>	128:9bcdf88f62b0	5142	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<>	128:9bcdf88f62b0	5143
<>	128:9bcdf88f62b0	5144	/* Initialization of some features of ADC instance and ADC group regular */
<>	128:9bcdf88f62b0	5145	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
<>	128:9bcdf88f62b0	5146	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<>	128:9bcdf88f62b0	5147
<>	128:9bcdf88f62b0	5148	/* Initialization of some features of ADC instance and ADC group injected */
<>	128:9bcdf88f62b0	5149	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct);
<>	128:9bcdf88f62b0	5150	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
<>	128:9bcdf88f62b0	5151
<>	128:9bcdf88f62b0	5152	/**
<>	128:9bcdf88f62b0	5153	* @}
<>	128:9bcdf88f62b0	5154	*/
<>	128:9bcdf88f62b0	5155	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	5156
<>	128:9bcdf88f62b0	5157	/**
<>	128:9bcdf88f62b0	5158	* @}
<>	128:9bcdf88f62b0	5159	*/
<>	128:9bcdf88f62b0	5160
<>	128:9bcdf88f62b0	5161	/**
<>	128:9bcdf88f62b0	5162	* @}
<>	128:9bcdf88f62b0	5163	*/
<>	128:9bcdf88f62b0	5164
<>	128:9bcdf88f62b0	5165	#endif /* ADC1 */
<>	128:9bcdf88f62b0	5166
<>	128:9bcdf88f62b0	5167	/**
<>	128:9bcdf88f62b0	5168	* @}
<>	128:9bcdf88f62b0	5169	*/
<>	128:9bcdf88f62b0	5170
<>	128:9bcdf88f62b0	5171	#ifdef __cplusplus
<>	128:9bcdf88f62b0	5172	}
<>	128:9bcdf88f62b0	5173	#endif
<>	128:9bcdf88f62b0	5174
<>	128:9bcdf88f62b0	5175	#endif /* __STM32L1xx_LL_ADC_H */
<>	128:9bcdf88f62b0	5176
<>	128:9bcdf88f62b0	5177	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/