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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_uart.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_uart.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief This file contains all the functions prototypes for the UART
<> 128:9bcdf88f62b0 8 * firmware library.
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 * @attention
<> 128:9bcdf88f62b0 11 *
<> 128:9bcdf88f62b0 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 15 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 17 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 19 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 20 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 22 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 23 * without specific prior written permission.
<> 128:9bcdf88f62b0 24 *
<> 128:9bcdf88f62b0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 35 *
<> 128:9bcdf88f62b0 36 ******************************************************************************
<> 128:9bcdf88f62b0 37 */
<> 128:9bcdf88f62b0 38
<> 128:9bcdf88f62b0 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 40 #ifndef __STM32L1xx_HAL_UART_H
<> 128:9bcdf88f62b0 41 #define __STM32L1xx_HAL_UART_H
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 #ifdef __cplusplus
<> 128:9bcdf88f62b0 44 extern "C" {
<> 128:9bcdf88f62b0 45 #endif
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 48 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 49
<> 128:9bcdf88f62b0 50 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 51 * @{
<> 128:9bcdf88f62b0 52 */
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /** @addtogroup UART
<> 128:9bcdf88f62b0 55 * @{
<> 128:9bcdf88f62b0 56 */
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 59 /** @defgroup UART_Exported_Types UART Exported Types
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /**
<> 128:9bcdf88f62b0 65 * @brief UART Init Structure definition
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67 typedef struct
<> 128:9bcdf88f62b0 68 {
<> 128:9bcdf88f62b0 69 uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
<> 128:9bcdf88f62b0 70 The baud rate is computed using the following formula:
<> 128:9bcdf88f62b0 71 - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
<> 128:9bcdf88f62b0 72 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
<> 128:9bcdf88f62b0 73 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 128:9bcdf88f62b0 76 This parameter can be a value of @ref UART_Word_Length */
<> 128:9bcdf88f62b0 77
<> 128:9bcdf88f62b0 78 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<> 128:9bcdf88f62b0 79 This parameter can be a value of @ref UART_Stop_Bits */
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 uint32_t Parity; /*!< Specifies the parity mode.
<> 128:9bcdf88f62b0 82 This parameter can be a value of @ref UART_Parity
<> 128:9bcdf88f62b0 83 @note When parity is enabled, the computed parity is inserted
<> 128:9bcdf88f62b0 84 at the MSB position of the transmitted data (9th bit when
<> 128:9bcdf88f62b0 85 the word length is set to 9 data bits; 8th bit when the
<> 128:9bcdf88f62b0 86 word length is set to 8 data bits). */
<> 128:9bcdf88f62b0 87
<> 128:9bcdf88f62b0 88 uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
<> 128:9bcdf88f62b0 89 This parameter can be a value of @ref UART_Mode */
<> 128:9bcdf88f62b0 90
<> 128:9bcdf88f62b0 91 uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
<> 128:9bcdf88f62b0 92 or disabled.
<> 128:9bcdf88f62b0 93 This parameter can be a value of @ref UART_Hardware_Flow_Control */
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
<> 128:9bcdf88f62b0 96 This parameter can be a value of @ref UART_Over_Sampling */
<> 128:9bcdf88f62b0 97 }UART_InitTypeDef;
<> 128:9bcdf88f62b0 98
<> 128:9bcdf88f62b0 99 /**
<> 128:9bcdf88f62b0 100 * @brief HAL UART State structures definition
<> 128:9bcdf88f62b0 101 */
<> 128:9bcdf88f62b0 102 typedef enum
<> 128:9bcdf88f62b0 103 {
<> 128:9bcdf88f62b0 104 HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
<> 128:9bcdf88f62b0 105 HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 128:9bcdf88f62b0 106 HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
<> 128:9bcdf88f62b0 107 HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 128:9bcdf88f62b0 108 HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 128:9bcdf88f62b0 109 HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
<> 128:9bcdf88f62b0 110 HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 128:9bcdf88f62b0 111 HAL_UART_STATE_ERROR = 0x04 /*!< Error */
<> 128:9bcdf88f62b0 112 }HAL_UART_StateTypeDef;
<> 128:9bcdf88f62b0 113
<> 128:9bcdf88f62b0 114 /**
<> 128:9bcdf88f62b0 115 * @brief UART handle Structure definition
<> 128:9bcdf88f62b0 116 */
<> 128:9bcdf88f62b0 117 typedef struct
<> 128:9bcdf88f62b0 118 {
<> 128:9bcdf88f62b0 119 USART_TypeDef *Instance; /*!< UART registers base address */
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 UART_InitTypeDef Init; /*!< UART communication parameters */
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 uint16_t TxXferSize; /*!< UART Tx Transfer size */
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 uint16_t RxXferSize; /*!< UART Rx Transfer size */
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133 uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
<> 128:9bcdf88f62b0 134
<> 128:9bcdf88f62b0 135 DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
<> 128:9bcdf88f62b0 136
<> 128:9bcdf88f62b0 137 DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
<> 128:9bcdf88f62b0 138
<> 128:9bcdf88f62b0 139 HAL_LockTypeDef Lock; /*!< Locking object */
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 __IO uint32_t ErrorCode; /*!< UART Error code */
<> 128:9bcdf88f62b0 144
<> 128:9bcdf88f62b0 145 }UART_HandleTypeDef;
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /**
<> 128:9bcdf88f62b0 148 * @}
<> 128:9bcdf88f62b0 149 */
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 152 /** @defgroup UART_Exported_Constants UART Exported constants
<> 128:9bcdf88f62b0 153 * @{
<> 128:9bcdf88f62b0 154 */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /** @defgroup UART_Error_Codes UART Error Codes
<> 128:9bcdf88f62b0 157 * @{
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 #define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 128:9bcdf88f62b0 161 #define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
<> 128:9bcdf88f62b0 162 #define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
<> 128:9bcdf88f62b0 163 #define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
<> 128:9bcdf88f62b0 164 #define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
<> 128:9bcdf88f62b0 165 #define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
<> 128:9bcdf88f62b0 166
<> 128:9bcdf88f62b0 167 /**
<> 128:9bcdf88f62b0 168 * @}
<> 128:9bcdf88f62b0 169 */
<> 128:9bcdf88f62b0 170
<> 128:9bcdf88f62b0 171 /** @defgroup UART_Word_Length UART Word Length
<> 128:9bcdf88f62b0 172 * @{
<> 128:9bcdf88f62b0 173 */
<> 128:9bcdf88f62b0 174 #define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 175 #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
<> 128:9bcdf88f62b0 176 /**
<> 128:9bcdf88f62b0 177 * @}
<> 128:9bcdf88f62b0 178 */
<> 128:9bcdf88f62b0 179
<> 128:9bcdf88f62b0 180 /** @defgroup UART_Stop_Bits UART Number of Stop Bits
<> 128:9bcdf88f62b0 181 * @{
<> 128:9bcdf88f62b0 182 */
<> 128:9bcdf88f62b0 183 #define UART_STOPBITS_1 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 184 #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
<> 128:9bcdf88f62b0 185 /**
<> 128:9bcdf88f62b0 186 * @}
<> 128:9bcdf88f62b0 187 */
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 /** @defgroup UART_Parity UART Parity
<> 128:9bcdf88f62b0 190 * @{
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192 #define UART_PARITY_NONE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 193 #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<> 128:9bcdf88f62b0 194 #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<> 128:9bcdf88f62b0 195 /**
<> 128:9bcdf88f62b0 196 * @}
<> 128:9bcdf88f62b0 197 */
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
<> 128:9bcdf88f62b0 200 * @{
<> 128:9bcdf88f62b0 201 */
<> 128:9bcdf88f62b0 202 #define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 203 #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
<> 128:9bcdf88f62b0 204 #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
<> 128:9bcdf88f62b0 205 #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
<> 128:9bcdf88f62b0 206 /**
<> 128:9bcdf88f62b0 207 * @}
<> 128:9bcdf88f62b0 208 */
<> 128:9bcdf88f62b0 209
<> 128:9bcdf88f62b0 210 /** @defgroup UART_Mode UART Transfer Mode
<> 128:9bcdf88f62b0 211 * @{
<> 128:9bcdf88f62b0 212 */
<> 128:9bcdf88f62b0 213 #define UART_MODE_RX ((uint32_t)USART_CR1_RE)
<> 128:9bcdf88f62b0 214 #define UART_MODE_TX ((uint32_t)USART_CR1_TE)
<> 128:9bcdf88f62b0 215 #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 /**
<> 128:9bcdf88f62b0 218 * @}
<> 128:9bcdf88f62b0 219 */
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 /** @defgroup UART_State UART State
<> 128:9bcdf88f62b0 222 * @{
<> 128:9bcdf88f62b0 223 */
<> 128:9bcdf88f62b0 224 #define UART_STATE_DISABLE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 225 #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
<> 128:9bcdf88f62b0 226 /**
<> 128:9bcdf88f62b0 227 * @}
<> 128:9bcdf88f62b0 228 */
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 /** @defgroup UART_Over_Sampling UART Over Sampling
<> 128:9bcdf88f62b0 231 * @{
<> 128:9bcdf88f62b0 232 */
<> 128:9bcdf88f62b0 233 #define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 234 #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
<> 128:9bcdf88f62b0 235 /**
<> 128:9bcdf88f62b0 236 * @}
<> 128:9bcdf88f62b0 237 */
<> 128:9bcdf88f62b0 238
<> 128:9bcdf88f62b0 239 /** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
<> 128:9bcdf88f62b0 240 * @{
<> 128:9bcdf88f62b0 241 */
<> 128:9bcdf88f62b0 242 #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 243 #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
<> 128:9bcdf88f62b0 244 /**
<> 128:9bcdf88f62b0 245 * @}
<> 128:9bcdf88f62b0 246 */
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 /** @defgroup UART_WakeUp_functions UART Wakeup Functions
<> 128:9bcdf88f62b0 249 * @{
<> 128:9bcdf88f62b0 250 */
<> 128:9bcdf88f62b0 251 #define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 252 #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
<> 128:9bcdf88f62b0 253 /**
<> 128:9bcdf88f62b0 254 * @}
<> 128:9bcdf88f62b0 255 */
<> 128:9bcdf88f62b0 256
<> 128:9bcdf88f62b0 257 /** @defgroup UART_Flags UART FLags
<> 128:9bcdf88f62b0 258 * Elements values convention: 0xXXXX
<> 128:9bcdf88f62b0 259 * - 0xXXXX : Flag mask in the SR register
<> 128:9bcdf88f62b0 260 * @{
<> 128:9bcdf88f62b0 261 */
<> 128:9bcdf88f62b0 262 #define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
<> 128:9bcdf88f62b0 263 #define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
<> 128:9bcdf88f62b0 264 #define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
<> 128:9bcdf88f62b0 265 #define UART_FLAG_TC ((uint32_t)USART_SR_TC)
<> 128:9bcdf88f62b0 266 #define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
<> 128:9bcdf88f62b0 267 #define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
<> 128:9bcdf88f62b0 268 #define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
<> 128:9bcdf88f62b0 269 #define UART_FLAG_NE ((uint32_t)USART_SR_NE)
<> 128:9bcdf88f62b0 270 #define UART_FLAG_FE ((uint32_t)USART_SR_FE)
<> 128:9bcdf88f62b0 271 #define UART_FLAG_PE ((uint32_t)USART_SR_PE)
<> 128:9bcdf88f62b0 272 /**
<> 128:9bcdf88f62b0 273 * @}
<> 128:9bcdf88f62b0 274 */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 /** @defgroup UART_Interrupt_definition UART Interrupt Definitions
<> 128:9bcdf88f62b0 277 * Elements values convention: 0xY000XXXX
<> 128:9bcdf88f62b0 278 * - XXXX : Interrupt mask (16 bits) in the Y register
<> 128:9bcdf88f62b0 279 * - Y : Interrupt source register (2bits)
<> 128:9bcdf88f62b0 280 * - 0001: CR1 register
<> 128:9bcdf88f62b0 281 * - 0010: CR2 register
<> 128:9bcdf88f62b0 282 * - 0011: CR3 register
<> 128:9bcdf88f62b0 283 *
<> 128:9bcdf88f62b0 284 * @{
<> 128:9bcdf88f62b0 285 */
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 #define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
<> 128:9bcdf88f62b0 288 #define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
<> 128:9bcdf88f62b0 289 #define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
<> 128:9bcdf88f62b0 290 #define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
<> 128:9bcdf88f62b0 291 #define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
<> 128:9bcdf88f62b0 292
<> 128:9bcdf88f62b0 293 #define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
<> 128:9bcdf88f62b0 294
<> 128:9bcdf88f62b0 295 #define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
<> 128:9bcdf88f62b0 296 #define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 /**
<> 128:9bcdf88f62b0 299 * @}
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /**
<> 128:9bcdf88f62b0 303 * @}
<> 128:9bcdf88f62b0 304 */
<> 128:9bcdf88f62b0 305
<> 128:9bcdf88f62b0 306
<> 128:9bcdf88f62b0 307 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 308 /** @defgroup UART_Exported_Macros UART Exported Macros
<> 128:9bcdf88f62b0 309 * @{
<> 128:9bcdf88f62b0 310 */
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /** @brief Reset UART handle state
<> 128:9bcdf88f62b0 314 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 315 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 316 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 317 * @retval None
<> 128:9bcdf88f62b0 318 */
<> 128:9bcdf88f62b0 319 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 /** @brief Flush the UART DR register
<> 128:9bcdf88f62b0 322 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 323 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 324 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 325 */
<> 128:9bcdf88f62b0 326 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
<> 128:9bcdf88f62b0 327
<> 128:9bcdf88f62b0 328 /** @brief Check whether the specified UART flag is set or not.
<> 128:9bcdf88f62b0 329 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 330 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 331 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 332 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 333 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 334 * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
<> 128:9bcdf88f62b0 335 * @arg UART_FLAG_LBD: LIN Break detection flag
<> 128:9bcdf88f62b0 336 * @arg UART_FLAG_TXE: Transmit data register empty flag
<> 128:9bcdf88f62b0 337 * @arg UART_FLAG_TC: Transmission Complete flag
<> 128:9bcdf88f62b0 338 * @arg UART_FLAG_RXNE: Receive data register not empty flag
<> 128:9bcdf88f62b0 339 * @arg UART_FLAG_IDLE: Idle Line detection flag
<> 128:9bcdf88f62b0 340 * @arg UART_FLAG_ORE: OverRun Error flag
<> 128:9bcdf88f62b0 341 * @arg UART_FLAG_NE: Noise Error flag
<> 128:9bcdf88f62b0 342 * @arg UART_FLAG_FE: Framing Error flag
<> 128:9bcdf88f62b0 343 * @arg UART_FLAG_PE: Parity Error flag
<> 128:9bcdf88f62b0 344 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 347
<> 128:9bcdf88f62b0 348 /** @brief Clear the specified UART pending flag.
<> 128:9bcdf88f62b0 349 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 350 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 351 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 352 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 353 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 354 * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
<> 128:9bcdf88f62b0 355 * @arg UART_FLAG_LBD: LIN Break detection flag.
<> 128:9bcdf88f62b0 356 * @arg UART_FLAG_TC: Transmission Complete flag.
<> 128:9bcdf88f62b0 357 * @arg UART_FLAG_RXNE: Receive data register not empty flag.
<> 128:9bcdf88f62b0 358 *
<> 128:9bcdf88f62b0 359 * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
<> 128:9bcdf88f62b0 360 * error) and IDLE (Idle line detected) flags are cleared by software
<> 128:9bcdf88f62b0 361 * sequence: a read operation to USART_SR register followed by a read
<> 128:9bcdf88f62b0 362 * operation to USART_DR register.
<> 128:9bcdf88f62b0 363 * @note RXNE flag can be also cleared by a read to the USART_DR register.
<> 128:9bcdf88f62b0 364 * @note TC flag can be also cleared by software sequence: a read operation to
<> 128:9bcdf88f62b0 365 * USART_SR register followed by a write operation to USART_DR register.
<> 128:9bcdf88f62b0 366 * @note TXE flag is cleared only by a write to the USART_DR register.
<> 128:9bcdf88f62b0 367 *
<> 128:9bcdf88f62b0 368 * @retval None
<> 128:9bcdf88f62b0 369 */
<> 128:9bcdf88f62b0 370 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 128:9bcdf88f62b0 371
<> 128:9bcdf88f62b0 372 /** @brief Clear the UART PE pending flag.
<> 128:9bcdf88f62b0 373 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 374 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 375 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 376 * @retval None
<> 128:9bcdf88f62b0 377 */
<> 128:9bcdf88f62b0 378 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 379 do{ \
<> 128:9bcdf88f62b0 380 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 381 tmpreg = (__HANDLE__)->Instance->SR; \
<> 128:9bcdf88f62b0 382 tmpreg = (__HANDLE__)->Instance->DR; \
<> 128:9bcdf88f62b0 383 UNUSED(tmpreg); \
<> 128:9bcdf88f62b0 384 }while(0)
<> 128:9bcdf88f62b0 385
<> 128:9bcdf88f62b0 386
<> 128:9bcdf88f62b0 387
<> 128:9bcdf88f62b0 388 /** @brief Clear the UART FE pending flag.
<> 128:9bcdf88f62b0 389 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 390 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 391 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 392 * @retval None
<> 128:9bcdf88f62b0 393 */
<> 128:9bcdf88f62b0 394 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<> 128:9bcdf88f62b0 395
<> 128:9bcdf88f62b0 396 /** @brief Clear the UART NE pending flag.
<> 128:9bcdf88f62b0 397 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 398 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 399 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 400 * @retval None
<> 128:9bcdf88f62b0 401 */
<> 128:9bcdf88f62b0 402 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 /** @brief Clear the UART ORE pending flag.
<> 128:9bcdf88f62b0 405 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 406 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 407 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 408 * @retval None
<> 128:9bcdf88f62b0 409 */
<> 128:9bcdf88f62b0 410 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<> 128:9bcdf88f62b0 411
<> 128:9bcdf88f62b0 412 /** @brief Clear the UART IDLE pending flag.
<> 128:9bcdf88f62b0 413 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 414 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 415 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 416 * @retval None
<> 128:9bcdf88f62b0 417 */
<> 128:9bcdf88f62b0 418 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<> 128:9bcdf88f62b0 419
<> 128:9bcdf88f62b0 420 /** @brief Enable the specified UART interrupt.
<> 128:9bcdf88f62b0 421 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 422 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 423 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 424 * @param __INTERRUPT__: specifies the UART interrupt source to enable.
<> 128:9bcdf88f62b0 425 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 426 * @arg UART_IT_CTS: CTS change interrupt
<> 128:9bcdf88f62b0 427 * @arg UART_IT_LBD: LIN Break detection interrupt
<> 128:9bcdf88f62b0 428 * @arg UART_IT_TXE: Transmit Data Register empty interrupt
<> 128:9bcdf88f62b0 429 * @arg UART_IT_TC: Transmission complete interrupt
<> 128:9bcdf88f62b0 430 * @arg UART_IT_RXNE: Receive Data register not empty interrupt
<> 128:9bcdf88f62b0 431 * @arg UART_IT_IDLE: Idle line detection interrupt
<> 128:9bcdf88f62b0 432 * @arg UART_IT_PE: Parity Error interrupt
<> 128:9bcdf88f62b0 433 * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 128:9bcdf88f62b0 434 * @retval None
<> 128:9bcdf88f62b0 435 */
<> 128:9bcdf88f62b0 436 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
<> 128:9bcdf88f62b0 437 (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
<> 128:9bcdf88f62b0 438 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
<> 128:9bcdf88f62b0 439
<> 128:9bcdf88f62b0 440
<> 128:9bcdf88f62b0 441 /** @brief Disable the specified UART interrupt.
<> 128:9bcdf88f62b0 442 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 443 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 444 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 445 * @param __INTERRUPT__: specifies the UART interrupt source to disable.
<> 128:9bcdf88f62b0 446 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 447 * @arg UART_IT_CTS: CTS change interrupt
<> 128:9bcdf88f62b0 448 * @arg UART_IT_LBD: LIN Break detection interrupt
<> 128:9bcdf88f62b0 449 * @arg UART_IT_TXE: Transmit Data Register empty interrupt
<> 128:9bcdf88f62b0 450 * @arg UART_IT_TC: Transmission complete interrupt
<> 128:9bcdf88f62b0 451 * @arg UART_IT_RXNE: Receive Data register not empty interrupt
<> 128:9bcdf88f62b0 452 * @arg UART_IT_IDLE: Idle line detection interrupt
<> 128:9bcdf88f62b0 453 * @arg UART_IT_PE: Parity Error interrupt
<> 128:9bcdf88f62b0 454 * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 128:9bcdf88f62b0 455 * @retval None
<> 128:9bcdf88f62b0 456 */
<> 128:9bcdf88f62b0 457 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
<> 128:9bcdf88f62b0 458 (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
<> 128:9bcdf88f62b0 459 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /** @brief Check whether the specified UART interrupt has occurred or not.
<> 128:9bcdf88f62b0 462 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 463 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 464 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 465 * @param __IT__: specifies the UART interrupt source to check.
<> 128:9bcdf88f62b0 466 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 467 * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
<> 128:9bcdf88f62b0 468 * @arg UART_IT_LBD: LIN Break detection interrupt
<> 128:9bcdf88f62b0 469 * @arg UART_IT_TXE: Transmit Data Register empty interrupt
<> 128:9bcdf88f62b0 470 * @arg UART_IT_TC: Transmission complete interrupt
<> 128:9bcdf88f62b0 471 * @arg UART_IT_RXNE: Receive Data register not empty interrupt
<> 128:9bcdf88f62b0 472 * @arg UART_IT_IDLE: Idle line detection interrupt
<> 128:9bcdf88f62b0 473 * @arg UART_IT_ERR: Error interrupt
<> 128:9bcdf88f62b0 474 * @retval The new state of __IT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 475 */
<> 128:9bcdf88f62b0 476 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \
<> 128:9bcdf88f62b0 477 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
<> 128:9bcdf88f62b0 478
<> 128:9bcdf88f62b0 479 /** @brief macros to enables or disables the UART's one bit sampling method
<> 128:9bcdf88f62b0 480 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 481 * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or
<> 128:9bcdf88f62b0 482 * UART peripheral (availability depending on device for UARTy).
<> 128:9bcdf88f62b0 483 * @retval None
<> 128:9bcdf88f62b0 484 */
<> 128:9bcdf88f62b0 485 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
<> 128:9bcdf88f62b0 486 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
<> 128:9bcdf88f62b0 487
<> 128:9bcdf88f62b0 488 /** @brief Enable CTS flow control
<> 128:9bcdf88f62b0 489 * This macro allows to enable CTS hardware flow control for a given UART instance,
<> 128:9bcdf88f62b0 490 * without need to call HAL_UART_Init() function.
<> 128:9bcdf88f62b0 491 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 128:9bcdf88f62b0 492 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<> 128:9bcdf88f62b0 493 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 128:9bcdf88f62b0 494 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 128:9bcdf88f62b0 495 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<> 128:9bcdf88f62b0 496 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<> 128:9bcdf88f62b0 497 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 498 * This parameter can be any USARTx (supporting the HW Flow control feature).
<> 128:9bcdf88f62b0 499 * It is used to select the USART peripheral (USART availability and x value depending on device).
<> 128:9bcdf88f62b0 500 * @retval None
<> 128:9bcdf88f62b0 501 */
<> 128:9bcdf88f62b0 502 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 503 do{ \
<> 128:9bcdf88f62b0 504 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<> 128:9bcdf88f62b0 505 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
<> 128:9bcdf88f62b0 506 } while(0)
<> 128:9bcdf88f62b0 507
<> 128:9bcdf88f62b0 508 /** @brief Disable CTS flow control
<> 128:9bcdf88f62b0 509 * This macro allows to disable CTS hardware flow control for a given UART instance,
<> 128:9bcdf88f62b0 510 * without need to call HAL_UART_Init() function.
<> 128:9bcdf88f62b0 511 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 128:9bcdf88f62b0 512 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<> 128:9bcdf88f62b0 513 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 128:9bcdf88f62b0 514 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 128:9bcdf88f62b0 515 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<> 128:9bcdf88f62b0 516 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<> 128:9bcdf88f62b0 517 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 518 * This parameter can be any USARTx (supporting the HW Flow control feature).
<> 128:9bcdf88f62b0 519 * It is used to select the USART peripheral (USART availability and x value depending on device).
<> 128:9bcdf88f62b0 520 * @retval None
<> 128:9bcdf88f62b0 521 */
<> 128:9bcdf88f62b0 522 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 523 do{ \
<> 128:9bcdf88f62b0 524 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<> 128:9bcdf88f62b0 525 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
<> 128:9bcdf88f62b0 526 } while(0)
<> 128:9bcdf88f62b0 527
<> 128:9bcdf88f62b0 528 /** @brief Enable RTS flow control
<> 128:9bcdf88f62b0 529 * This macro allows to enable RTS hardware flow control for a given UART instance,
<> 128:9bcdf88f62b0 530 * without need to call HAL_UART_Init() function.
<> 128:9bcdf88f62b0 531 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 128:9bcdf88f62b0 532 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<> 128:9bcdf88f62b0 533 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 128:9bcdf88f62b0 534 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 128:9bcdf88f62b0 535 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<> 128:9bcdf88f62b0 536 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<> 128:9bcdf88f62b0 537 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 538 * This parameter can be any USARTx (supporting the HW Flow control feature).
<> 128:9bcdf88f62b0 539 * It is used to select the USART peripheral (USART availability and x value depending on device).
<> 128:9bcdf88f62b0 540 * @retval None
<> 128:9bcdf88f62b0 541 */
<> 128:9bcdf88f62b0 542 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 543 do{ \
<> 128:9bcdf88f62b0 544 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
<> 128:9bcdf88f62b0 545 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
<> 128:9bcdf88f62b0 546 } while(0)
<> 128:9bcdf88f62b0 547
<> 128:9bcdf88f62b0 548 /** @brief Disable RTS flow control
<> 128:9bcdf88f62b0 549 * This macro allows to disable RTS hardware flow control for a given UART instance,
<> 128:9bcdf88f62b0 550 * without need to call HAL_UART_Init() function.
<> 128:9bcdf88f62b0 551 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 128:9bcdf88f62b0 552 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<> 128:9bcdf88f62b0 553 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 128:9bcdf88f62b0 554 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 128:9bcdf88f62b0 555 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<> 128:9bcdf88f62b0 556 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<> 128:9bcdf88f62b0 557 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 558 * This parameter can be any USARTx (supporting the HW Flow control feature).
<> 128:9bcdf88f62b0 559 * It is used to select the USART peripheral (USART availability and x value depending on device).
<> 128:9bcdf88f62b0 560 * @retval None
<> 128:9bcdf88f62b0 561 */
<> 128:9bcdf88f62b0 562 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 563 do{ \
<> 128:9bcdf88f62b0 564 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
<> 128:9bcdf88f62b0 565 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
<> 128:9bcdf88f62b0 566 } while(0)
<> 128:9bcdf88f62b0 567
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569 /** @brief Enable UART
<> 128:9bcdf88f62b0 570 * @param __HANDLE__: specifies the UART Handle.
<> 128:9bcdf88f62b0 571 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 572 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 573 * @retval None
<> 128:9bcdf88f62b0 574 */
<> 128:9bcdf88f62b0 575 #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 128:9bcdf88f62b0 576
<> 128:9bcdf88f62b0 577 /** @brief Disable UART
<> 128:9bcdf88f62b0 578 * UART Handle selects the USARTx or UARTy peripheral
<> 128:9bcdf88f62b0 579 * (USART,UART availability and x,y values depending on device).
<> 128:9bcdf88f62b0 580 * @retval None
<> 128:9bcdf88f62b0 581 */
<> 128:9bcdf88f62b0 582 #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 128:9bcdf88f62b0 583
<> 128:9bcdf88f62b0 584 /**
<> 128:9bcdf88f62b0 585 * @}
<> 128:9bcdf88f62b0 586 */
<> 128:9bcdf88f62b0 587
<> 128:9bcdf88f62b0 588
<> 128:9bcdf88f62b0 589 /* Private macros --------------------------------------------------------*/
<> 128:9bcdf88f62b0 590 /** @defgroup UART_Private_Macros UART Private Macros
<> 128:9bcdf88f62b0 591 * @{
<> 128:9bcdf88f62b0 592 */
<> 128:9bcdf88f62b0 593
<> 128:9bcdf88f62b0 594 #define UART_CR1_REG_INDEX 1
<> 128:9bcdf88f62b0 595 #define UART_CR2_REG_INDEX 2
<> 128:9bcdf88f62b0 596 #define UART_CR3_REG_INDEX 3
<> 128:9bcdf88f62b0 597
<> 128:9bcdf88f62b0 598 #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
<> 128:9bcdf88f62b0 599 #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
<> 128:9bcdf88f62b0 600 #define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
<> 128:9bcdf88f62b0 601 /* UART BRR = mantissa + overflow + fraction
<> 128:9bcdf88f62b0 602 = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
<> 128:9bcdf88f62b0 603 #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \
<> 128:9bcdf88f62b0 604 (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \
<> 128:9bcdf88f62b0 605 (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
<> 128:9bcdf88f62b0 606 #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
<> 128:9bcdf88f62b0 607 #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
<> 128:9bcdf88f62b0 608 #define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 8 + 50) / 100)
<> 128:9bcdf88f62b0 609 /* UART BRR = mantissa + overflow + fraction
<> 128:9bcdf88f62b0 610 = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
<> 128:9bcdf88f62b0 611 #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4) + \
<> 128:9bcdf88f62b0 612 ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8) << 1)) + \
<> 128:9bcdf88f62b0 613 (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07))
<> 128:9bcdf88f62b0 614 #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
<> 128:9bcdf88f62b0 615 ((LENGTH) == UART_WORDLENGTH_9B))
<> 128:9bcdf88f62b0 616 #define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B)
<> 128:9bcdf88f62b0 617
<> 128:9bcdf88f62b0 618 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
<> 128:9bcdf88f62b0 619 ((STOPBITS) == UART_STOPBITS_2))
<> 128:9bcdf88f62b0 620
<> 128:9bcdf88f62b0 621 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
<> 128:9bcdf88f62b0 622 ((PARITY) == UART_PARITY_EVEN) || \
<> 128:9bcdf88f62b0 623 ((PARITY) == UART_PARITY_ODD))
<> 128:9bcdf88f62b0 624
<> 128:9bcdf88f62b0 625 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
<> 128:9bcdf88f62b0 626 (((CONTROL) == UART_HWCONTROL_NONE) || \
<> 128:9bcdf88f62b0 627 ((CONTROL) == UART_HWCONTROL_RTS) || \
<> 128:9bcdf88f62b0 628 ((CONTROL) == UART_HWCONTROL_CTS) || \
<> 128:9bcdf88f62b0 629 ((CONTROL) == UART_HWCONTROL_RTS_CTS))
<> 128:9bcdf88f62b0 630
<> 128:9bcdf88f62b0 631 #define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \
<> 128:9bcdf88f62b0 632 ((MODE) != (uint32_t)0x00000000))
<> 128:9bcdf88f62b0 633
<> 128:9bcdf88f62b0 634 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
<> 128:9bcdf88f62b0 635 ((STATE) == UART_STATE_ENABLE))
<> 128:9bcdf88f62b0 636
<> 128:9bcdf88f62b0 637 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
<> 128:9bcdf88f62b0 638 ((SAMPLING) == UART_OVERSAMPLING_8))
<> 128:9bcdf88f62b0 639 #define IS_UART_LIN_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16)
<> 128:9bcdf88f62b0 640
<> 128:9bcdf88f62b0 641 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
<> 128:9bcdf88f62b0 642 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
<> 128:9bcdf88f62b0 643
<> 128:9bcdf88f62b0 644 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
<> 128:9bcdf88f62b0 645 ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
<> 128:9bcdf88f62b0 646
<> 128:9bcdf88f62b0 647
<> 128:9bcdf88f62b0 648 /** Check UART Baud rate
<> 128:9bcdf88f62b0 649 * __BAUDRATE__: Baudrate specified by the user
<> 128:9bcdf88f62b0 650 * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz)
<> 128:9bcdf88f62b0 651 * divided by the smallest oversampling used on the USART (i.e. 8)
<> 128:9bcdf88f62b0 652 * Return : TRUE or FALSE
<> 128:9bcdf88f62b0 653 */
<> 128:9bcdf88f62b0 654 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001)
<> 128:9bcdf88f62b0 655
<> 128:9bcdf88f62b0 656 /** Check UART Node Address
<> 128:9bcdf88f62b0 657 * __ADDRESS__: UART Node address specified by the user
<> 128:9bcdf88f62b0 658 * UART Node address is used in Multi processor communication for wakeup
<> 128:9bcdf88f62b0 659 * with address mark detection.
<> 128:9bcdf88f62b0 660 * This parameter must be a number between Min_Data = 0 and Max_Data = 15
<> 128:9bcdf88f62b0 661 * Return : TRUE or FALSE
<> 128:9bcdf88f62b0 662 */
<> 128:9bcdf88f62b0 663 #define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
<> 128:9bcdf88f62b0 664
<> 128:9bcdf88f62b0 665 /** UART interruptions flag mask
<> 128:9bcdf88f62b0 666 */
<> 128:9bcdf88f62b0 667 #define UART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
<> 128:9bcdf88f62b0 668 USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
<> 128:9bcdf88f62b0 669
<> 128:9bcdf88f62b0 670 /**
<> 128:9bcdf88f62b0 671 * @}
<> 128:9bcdf88f62b0 672 */
<> 128:9bcdf88f62b0 673
<> 128:9bcdf88f62b0 674 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 675
<> 128:9bcdf88f62b0 676 /** @addtogroup UART_Exported_Functions UART Exported Functions
<> 128:9bcdf88f62b0 677 * @{
<> 128:9bcdf88f62b0 678 */
<> 128:9bcdf88f62b0 679
<> 128:9bcdf88f62b0 680 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 128:9bcdf88f62b0 681 * @{
<> 128:9bcdf88f62b0 682 */
<> 128:9bcdf88f62b0 683
<> 128:9bcdf88f62b0 684 /* Initialization and de-initialization functions ****************************/
<> 128:9bcdf88f62b0 685 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 686 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 687 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
<> 128:9bcdf88f62b0 688 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
<> 128:9bcdf88f62b0 689 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 690 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 691 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 692
<> 128:9bcdf88f62b0 693 /**
<> 128:9bcdf88f62b0 694 * @}
<> 128:9bcdf88f62b0 695 */
<> 128:9bcdf88f62b0 696
<> 128:9bcdf88f62b0 697 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
<> 128:9bcdf88f62b0 698 * @{
<> 128:9bcdf88f62b0 699 */
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 /* IO operation functions *****************************************************/
<> 128:9bcdf88f62b0 702 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 703 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 704 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 705 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 706 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 707 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 708 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 709 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 710 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 711 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 712 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 713 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 714 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 715 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 716 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 717
<> 128:9bcdf88f62b0 718 /**
<> 128:9bcdf88f62b0 719 * @}
<> 128:9bcdf88f62b0 720 */
<> 128:9bcdf88f62b0 721
<> 128:9bcdf88f62b0 722 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
<> 128:9bcdf88f62b0 723 * @{
<> 128:9bcdf88f62b0 724 */
<> 128:9bcdf88f62b0 725
<> 128:9bcdf88f62b0 726 /* Peripheral Control functions ************************************************/
<> 128:9bcdf88f62b0 727 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 728 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 729 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 730 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 731 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 732
<> 128:9bcdf88f62b0 733 /**
<> 128:9bcdf88f62b0 734 * @}
<> 128:9bcdf88f62b0 735 */
<> 128:9bcdf88f62b0 736
<> 128:9bcdf88f62b0 737 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
<> 128:9bcdf88f62b0 738 * @{
<> 128:9bcdf88f62b0 739 */
<> 128:9bcdf88f62b0 740
<> 128:9bcdf88f62b0 741 /* Peripheral State and Errors functions **************************************************/
<> 128:9bcdf88f62b0 742 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 743 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
<> 128:9bcdf88f62b0 744
<> 128:9bcdf88f62b0 745 /**
<> 128:9bcdf88f62b0 746 * @}
<> 128:9bcdf88f62b0 747 */
<> 128:9bcdf88f62b0 748
<> 128:9bcdf88f62b0 749 /**
<> 128:9bcdf88f62b0 750 * @}
<> 128:9bcdf88f62b0 751 */
<> 128:9bcdf88f62b0 752
<> 128:9bcdf88f62b0 753 /**
<> 128:9bcdf88f62b0 754 * @}
<> 128:9bcdf88f62b0 755 */
<> 128:9bcdf88f62b0 756
<> 128:9bcdf88f62b0 757 /**
<> 128:9bcdf88f62b0 758 * @}
<> 128:9bcdf88f62b0 759 */
<> 128:9bcdf88f62b0 760
<> 128:9bcdf88f62b0 761 #ifdef __cplusplus
<> 128:9bcdf88f62b0 762 }
<> 128:9bcdf88f62b0 763 #endif
<> 128:9bcdf88f62b0 764
<> 128:9bcdf88f62b0 765 #endif /* __STM32L1xx_HAL_UART_H */
<> 128:9bcdf88f62b0 766
<> 128:9bcdf88f62b0 767 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/