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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_tim_ex.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of TIM HAL Extension module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_TIM_EX_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_TIM_EX_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup TIMEx
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /**
<> 128:9bcdf88f62b0 63 * @brief TIM Master configuration Structure definition
<> 128:9bcdf88f62b0 64 */
<> 128:9bcdf88f62b0 65 typedef struct {
<> 128:9bcdf88f62b0 66 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<> 128:9bcdf88f62b0 67 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 128:9bcdf88f62b0 68 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<> 128:9bcdf88f62b0 69 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 128:9bcdf88f62b0 70 }TIM_MasterConfigTypeDef;
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /**
<> 128:9bcdf88f62b0 73 * @}
<> 128:9bcdf88f62b0 74 */
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 77 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
<> 128:9bcdf88f62b0 78 * @{
<> 128:9bcdf88f62b0 79 */
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 /** @defgroup TIMEx_Remap TIMEx Remap
<> 128:9bcdf88f62b0 82 * @{
<> 128:9bcdf88f62b0 83 */
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 86 #define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */
<> 128:9bcdf88f62b0 87 #define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */
<> 128:9bcdf88f62b0 88 #endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 91 #define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */
<> 128:9bcdf88f62b0 92 #define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */
<> 128:9bcdf88f62b0 93 #endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 96 #define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */
<> 128:9bcdf88f62b0 97 #define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */
<> 128:9bcdf88f62b0 98 #endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 99 #define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 100 #define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */
<> 128:9bcdf88f62b0 101 #define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 102 #define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104
<> 128:9bcdf88f62b0 105 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 106 #define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */
<> 128:9bcdf88f62b0 107 #define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */
<> 128:9bcdf88f62b0 108 #define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */
<> 128:9bcdf88f62b0 109 #define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */
<> 128:9bcdf88f62b0 110 #endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 111 #define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 112 #define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */
<> 128:9bcdf88f62b0 113 #define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */
<> 128:9bcdf88f62b0 114 #define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 117 #define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */
<> 128:9bcdf88f62b0 118 #define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */
<> 128:9bcdf88f62b0 119 #define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */
<> 128:9bcdf88f62b0 120 #define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */
<> 128:9bcdf88f62b0 121 #endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 122 #define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 123 #define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */
<> 128:9bcdf88f62b0 124 #define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */
<> 128:9bcdf88f62b0 125 #define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 129 #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
<> 128:9bcdf88f62b0 130 ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \
<> 128:9bcdf88f62b0 131 (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \
<> 128:9bcdf88f62b0 132 (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \
<> 128:9bcdf88f62b0 133 (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \
<> 128:9bcdf88f62b0 134 (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \
<> 128:9bcdf88f62b0 135 )
<> 128:9bcdf88f62b0 136 #else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */
<> 128:9bcdf88f62b0 137 #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
<> 128:9bcdf88f62b0 138 ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \
<> 128:9bcdf88f62b0 139 (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \
<> 128:9bcdf88f62b0 140 (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \
<> 128:9bcdf88f62b0 141 )
<> 128:9bcdf88f62b0 142 #endif
<> 128:9bcdf88f62b0 143
<> 128:9bcdf88f62b0 144
<> 128:9bcdf88f62b0 145 /**
<> 128:9bcdf88f62b0 146 * @}
<> 128:9bcdf88f62b0 147 */
<> 128:9bcdf88f62b0 148
<> 128:9bcdf88f62b0 149 /**
<> 128:9bcdf88f62b0 150 * @}
<> 128:9bcdf88f62b0 151 */
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 154
<> 128:9bcdf88f62b0 155 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 156 /** @addtogroup TIMEx_Exported_Functions
<> 128:9bcdf88f62b0 157 * @{
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 /** @addtogroup TIMEx_Exported_Functions_Group1
<> 128:9bcdf88f62b0 161 * @{
<> 128:9bcdf88f62b0 162 */
<> 128:9bcdf88f62b0 163 /* Extension Control functions ************************************************/
<> 128:9bcdf88f62b0 164 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
<> 128:9bcdf88f62b0 165 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
<> 128:9bcdf88f62b0 166 /**
<> 128:9bcdf88f62b0 167 * @}
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 /* Extension Peripheral State functions **************************************/
<> 128:9bcdf88f62b0 171 /**
<> 128:9bcdf88f62b0 172 * @}
<> 128:9bcdf88f62b0 173 */
<> 128:9bcdf88f62b0 174
<> 128:9bcdf88f62b0 175 /**
<> 128:9bcdf88f62b0 176 * @}
<> 128:9bcdf88f62b0 177 */
<> 128:9bcdf88f62b0 178
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @}
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /**
<> 128:9bcdf88f62b0 184 * @}
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186
<> 128:9bcdf88f62b0 187 #ifdef __cplusplus
<> 128:9bcdf88f62b0 188 }
<> 128:9bcdf88f62b0 189 #endif
<> 128:9bcdf88f62b0 190
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 #endif /* __STM32L1xx_HAL_TIM_EX_H */
<> 128:9bcdf88f62b0 193
<> 128:9bcdf88f62b0 194 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/