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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_spi.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of SPI HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_SPI_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_SPI_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup SPI
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /**
<> 128:9bcdf88f62b0 63 * @brief SPI Configuration Structure definition
<> 128:9bcdf88f62b0 64 */
<> 128:9bcdf88f62b0 65 typedef struct
<> 128:9bcdf88f62b0 66 {
<> 128:9bcdf88f62b0 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 128:9bcdf88f62b0 68 This parameter can be a value of @ref SPI_mode */
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
<> 128:9bcdf88f62b0 71 This parameter can be a value of @ref SPI_Direction_mode */
<> 128:9bcdf88f62b0 72
<> 128:9bcdf88f62b0 73 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 128:9bcdf88f62b0 74 This parameter can be a value of @ref SPI_data_size */
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 128:9bcdf88f62b0 77 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 128:9bcdf88f62b0 80 This parameter can be a value of @ref SPI_Clock_Phase */
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 128:9bcdf88f62b0 83 hardware (NSS pin) or by software using the SSI bit.
<> 128:9bcdf88f62b0 84 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 128:9bcdf88f62b0 87 used to configure the transmit and receive SCK clock.
<> 128:9bcdf88f62b0 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 128:9bcdf88f62b0 89 @note The communication clock is derived from the master
<> 128:9bcdf88f62b0 90 clock. The slave clock does not need to be set */
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 128:9bcdf88f62b0 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 128:9bcdf88f62b0 96 This parameter can be a value of @ref SPI_TI_mode */
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 128:9bcdf88f62b0 99 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 128:9bcdf88f62b0 100
<> 128:9bcdf88f62b0 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 128:9bcdf88f62b0 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104 }SPI_InitTypeDef;
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 /**
<> 128:9bcdf88f62b0 107 * @brief HAL SPI State structure definition
<> 128:9bcdf88f62b0 108 */
<> 128:9bcdf88f62b0 109 typedef enum
<> 128:9bcdf88f62b0 110 {
<> 128:9bcdf88f62b0 111 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
<> 128:9bcdf88f62b0 112 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
<> 128:9bcdf88f62b0 113 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
<> 128:9bcdf88f62b0 114 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 128:9bcdf88f62b0 115 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 128:9bcdf88f62b0 116 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
<> 128:9bcdf88f62b0 117 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 }HAL_SPI_StateTypeDef;
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 /**
<> 128:9bcdf88f62b0 122 * @brief SPI handle Structure definition
<> 128:9bcdf88f62b0 123 */
<> 128:9bcdf88f62b0 124 typedef struct __SPI_HandleTypeDef
<> 128:9bcdf88f62b0 125 {
<> 128:9bcdf88f62b0 126 SPI_TypeDef *Instance; /* SPI registers base address */
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 SPI_InitTypeDef Init; /* SPI communication parameters */
<> 128:9bcdf88f62b0 129
<> 128:9bcdf88f62b0 130 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 uint16_t TxXferSize; /* SPI Tx transfer size */
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
<> 128:9bcdf88f62b0 137
<> 128:9bcdf88f62b0 138 uint16_t RxXferSize; /* SPI Rx transfer size */
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
<> 128:9bcdf88f62b0 143
<> 128:9bcdf88f62b0 144 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
<> 128:9bcdf88f62b0 147
<> 128:9bcdf88f62b0 148 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
<> 128:9bcdf88f62b0 149
<> 128:9bcdf88f62b0 150 HAL_LockTypeDef Lock; /* SPI locking object */
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
<> 128:9bcdf88f62b0 153
<> 128:9bcdf88f62b0 154 __IO uint32_t ErrorCode; /* SPI Error code */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 }SPI_HandleTypeDef;
<> 128:9bcdf88f62b0 157 /**
<> 128:9bcdf88f62b0 158 * @}
<> 128:9bcdf88f62b0 159 */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 128:9bcdf88f62b0 165 * @{
<> 128:9bcdf88f62b0 166 */
<> 128:9bcdf88f62b0 167
<> 128:9bcdf88f62b0 168 /** @defgroup SPI_Error_Codes SPI Error Codes
<> 128:9bcdf88f62b0 169 * @{
<> 128:9bcdf88f62b0 170 */
<> 128:9bcdf88f62b0 171 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 128:9bcdf88f62b0 172 #define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */
<> 128:9bcdf88f62b0 173 #define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */
<> 128:9bcdf88f62b0 174 #define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */
<> 128:9bcdf88f62b0 175 #define HAL_SPI_ERROR_FRE ((uint32_t)0x08) /*!< FRE error */
<> 128:9bcdf88f62b0 176 #define HAL_SPI_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
<> 128:9bcdf88f62b0 177 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x20) /*!< Flag: RXNE,TXE, BSY */
<> 128:9bcdf88f62b0 178
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @}
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /** @defgroup SPI_mode SPI mode
<> 128:9bcdf88f62b0 184 * @{
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 187 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
<> 128:9bcdf88f62b0 190 ((MODE) == SPI_MODE_MASTER))
<> 128:9bcdf88f62b0 191 /**
<> 128:9bcdf88f62b0 192 * @}
<> 128:9bcdf88f62b0 193 */
<> 128:9bcdf88f62b0 194
<> 128:9bcdf88f62b0 195 /** @defgroup SPI_Direction_mode SPI Direction mode
<> 128:9bcdf88f62b0 196 * @{
<> 128:9bcdf88f62b0 197 */
<> 128:9bcdf88f62b0 198 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 199 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 128:9bcdf88f62b0 200 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 128:9bcdf88f62b0 203 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 128:9bcdf88f62b0 204 ((MODE) == SPI_DIRECTION_1LINE))
<> 128:9bcdf88f62b0 205
<> 128:9bcdf88f62b0 206 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 128:9bcdf88f62b0 207 ((MODE) == SPI_DIRECTION_1LINE))
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
<> 128:9bcdf88f62b0 210
<> 128:9bcdf88f62b0 211 /**
<> 128:9bcdf88f62b0 212 * @}
<> 128:9bcdf88f62b0 213 */
<> 128:9bcdf88f62b0 214
<> 128:9bcdf88f62b0 215 /** @defgroup SPI_data_size SPI data size
<> 128:9bcdf88f62b0 216 * @{
<> 128:9bcdf88f62b0 217 */
<> 128:9bcdf88f62b0 218 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 219 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
<> 128:9bcdf88f62b0 222 ((DATASIZE) == SPI_DATASIZE_8BIT))
<> 128:9bcdf88f62b0 223 /**
<> 128:9bcdf88f62b0 224 * @}
<> 128:9bcdf88f62b0 225 */
<> 128:9bcdf88f62b0 226
<> 128:9bcdf88f62b0 227 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 128:9bcdf88f62b0 228 * @{
<> 128:9bcdf88f62b0 229 */
<> 128:9bcdf88f62b0 230 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 231 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
<> 128:9bcdf88f62b0 234 ((CPOL) == SPI_POLARITY_HIGH))
<> 128:9bcdf88f62b0 235 /**
<> 128:9bcdf88f62b0 236 * @}
<> 128:9bcdf88f62b0 237 */
<> 128:9bcdf88f62b0 238
<> 128:9bcdf88f62b0 239 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 128:9bcdf88f62b0 240 * @{
<> 128:9bcdf88f62b0 241 */
<> 128:9bcdf88f62b0 242 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 243 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 128:9bcdf88f62b0 244
<> 128:9bcdf88f62b0 245 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
<> 128:9bcdf88f62b0 246 ((CPHA) == SPI_PHASE_2EDGE))
<> 128:9bcdf88f62b0 247 /**
<> 128:9bcdf88f62b0 248 * @}
<> 128:9bcdf88f62b0 249 */
<> 128:9bcdf88f62b0 250
<> 128:9bcdf88f62b0 251 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
<> 128:9bcdf88f62b0 252 * @{
<> 128:9bcdf88f62b0 253 */
<> 128:9bcdf88f62b0 254 #define SPI_NSS_SOFT SPI_CR1_SSM
<> 128:9bcdf88f62b0 255 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 256 #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
<> 128:9bcdf88f62b0 259 ((NSS) == SPI_NSS_HARD_INPUT) || \
<> 128:9bcdf88f62b0 260 ((NSS) == SPI_NSS_HARD_OUTPUT))
<> 128:9bcdf88f62b0 261 /**
<> 128:9bcdf88f62b0 262 * @}
<> 128:9bcdf88f62b0 263 */
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 128:9bcdf88f62b0 266 * @{
<> 128:9bcdf88f62b0 267 */
<> 128:9bcdf88f62b0 268 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 269 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
<> 128:9bcdf88f62b0 270 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
<> 128:9bcdf88f62b0 271 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 128:9bcdf88f62b0 272 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
<> 128:9bcdf88f62b0 273 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
<> 128:9bcdf88f62b0 274 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
<> 128:9bcdf88f62b0 275 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 128:9bcdf88f62b0 276
<> 128:9bcdf88f62b0 277 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 128:9bcdf88f62b0 278 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 128:9bcdf88f62b0 279 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 128:9bcdf88f62b0 280 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 128:9bcdf88f62b0 281 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 128:9bcdf88f62b0 282 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
<> 128:9bcdf88f62b0 283 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
<> 128:9bcdf88f62b0 284 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
<> 128:9bcdf88f62b0 285 /**
<> 128:9bcdf88f62b0 286 * @}
<> 128:9bcdf88f62b0 287 */
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
<> 128:9bcdf88f62b0 290 * @{
<> 128:9bcdf88f62b0 291 */
<> 128:9bcdf88f62b0 292 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 293 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 128:9bcdf88f62b0 294
<> 128:9bcdf88f62b0 295 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
<> 128:9bcdf88f62b0 296 ((BIT) == SPI_FIRSTBIT_LSB))
<> 128:9bcdf88f62b0 297 /**
<> 128:9bcdf88f62b0 298 * @}
<> 128:9bcdf88f62b0 299 */
<> 128:9bcdf88f62b0 300
<> 128:9bcdf88f62b0 301 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 128:9bcdf88f62b0 302 * @{
<> 128:9bcdf88f62b0 303 */
<> 128:9bcdf88f62b0 304 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 305 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 128:9bcdf88f62b0 306
<> 128:9bcdf88f62b0 307 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
<> 128:9bcdf88f62b0 308 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
<> 128:9bcdf88f62b0 309
<> 128:9bcdf88f62b0 310 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
<> 128:9bcdf88f62b0 311 /**
<> 128:9bcdf88f62b0 312 * @}
<> 128:9bcdf88f62b0 313 */
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
<> 128:9bcdf88f62b0 316 * @{
<> 128:9bcdf88f62b0 317 */
<> 128:9bcdf88f62b0 318 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 128:9bcdf88f62b0 319 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 128:9bcdf88f62b0 320 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 128:9bcdf88f62b0 321 /**
<> 128:9bcdf88f62b0 322 * @}
<> 128:9bcdf88f62b0 323 */
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 /** @defgroup SPI_Flag_definition SPI Flag definition
<> 128:9bcdf88f62b0 326 * @{
<> 128:9bcdf88f62b0 327 */
<> 128:9bcdf88f62b0 328 #define SPI_FLAG_RXNE SPI_SR_RXNE
<> 128:9bcdf88f62b0 329 #define SPI_FLAG_TXE SPI_SR_TXE
<> 128:9bcdf88f62b0 330 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
<> 128:9bcdf88f62b0 331 #define SPI_FLAG_MODF SPI_SR_MODF
<> 128:9bcdf88f62b0 332 #define SPI_FLAG_OVR SPI_SR_OVR
<> 128:9bcdf88f62b0 333 #define SPI_FLAG_BSY SPI_SR_BSY
<> 128:9bcdf88f62b0 334 #define SPI_FLAG_FRE SPI_SR_FRE
<> 128:9bcdf88f62b0 335
<> 128:9bcdf88f62b0 336 /**
<> 128:9bcdf88f62b0 337 * @}
<> 128:9bcdf88f62b0 338 */
<> 128:9bcdf88f62b0 339
<> 128:9bcdf88f62b0 340 /**
<> 128:9bcdf88f62b0 341 * @}
<> 128:9bcdf88f62b0 342 */
<> 128:9bcdf88f62b0 343
<> 128:9bcdf88f62b0 344
<> 128:9bcdf88f62b0 345 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 346 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 128:9bcdf88f62b0 347 * @{
<> 128:9bcdf88f62b0 348 */
<> 128:9bcdf88f62b0 349
<> 128:9bcdf88f62b0 350 /** @brief Reset SPI handle state
<> 128:9bcdf88f62b0 351 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 352 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 353 * @retval None
<> 128:9bcdf88f62b0 354 */
<> 128:9bcdf88f62b0 355 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 128:9bcdf88f62b0 356
<> 128:9bcdf88f62b0 357 /** @brief Enable or disable the specified SPI interrupts.
<> 128:9bcdf88f62b0 358 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 359 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 360 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 128:9bcdf88f62b0 361 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 362 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 128:9bcdf88f62b0 363 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 128:9bcdf88f62b0 364 * @arg SPI_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 365 * @retval None
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 128:9bcdf88f62b0 368 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 128:9bcdf88f62b0 369
<> 128:9bcdf88f62b0 370 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
<> 128:9bcdf88f62b0 371 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 372 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 373 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 128:9bcdf88f62b0 374 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 375 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 128:9bcdf88f62b0 376 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 128:9bcdf88f62b0 377 * @arg SPI_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 378 * @retval The new state of __IT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 379 */
<> 128:9bcdf88f62b0 380 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 128:9bcdf88f62b0 381
<> 128:9bcdf88f62b0 382 /** @brief Check whether the specified SPI flag is set or not.
<> 128:9bcdf88f62b0 383 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 384 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 385 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 386 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 387 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 128:9bcdf88f62b0 388 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 128:9bcdf88f62b0 389 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 128:9bcdf88f62b0 390 * @arg SPI_FLAG_MODF: Mode fault flag
<> 128:9bcdf88f62b0 391 * @arg SPI_FLAG_OVR: Overrun flag
<> 128:9bcdf88f62b0 392 * @arg SPI_FLAG_BSY: Busy flag
<> 128:9bcdf88f62b0 393 * @arg SPI_FLAG_FRE: Frame format error flag
<> 128:9bcdf88f62b0 394 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 397
<> 128:9bcdf88f62b0 398 /** @brief Clear the SPI CRCERR pending flag.
<> 128:9bcdf88f62b0 399 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 400 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 401 * @retval None
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
<> 128:9bcdf88f62b0 404
<> 128:9bcdf88f62b0 405 /** @brief Clear the SPI MODF pending flag.
<> 128:9bcdf88f62b0 406 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 407 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 408 * @retval None
<> 128:9bcdf88f62b0 409 */
<> 128:9bcdf88f62b0 410 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 411 do{ \
<> 128:9bcdf88f62b0 412 __IO uint32_t tmpreg_modf; \
<> 128:9bcdf88f62b0 413 tmpreg_modf = (__HANDLE__)->Instance->SR; \
<> 128:9bcdf88f62b0 414 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
<> 128:9bcdf88f62b0 415 UNUSED(tmpreg_modf); \
<> 128:9bcdf88f62b0 416 }while(0)
<> 128:9bcdf88f62b0 417
<> 128:9bcdf88f62b0 418 /** @brief Clear the SPI OVR pending flag.
<> 128:9bcdf88f62b0 419 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 420 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 421 * @retval None
<> 128:9bcdf88f62b0 422 */
<> 128:9bcdf88f62b0 423 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 424 do{ \
<> 128:9bcdf88f62b0 425 __IO uint32_t tmpreg_ovr; \
<> 128:9bcdf88f62b0 426 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 128:9bcdf88f62b0 427 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 128:9bcdf88f62b0 428 UNUSED(tmpreg_ovr); \
<> 128:9bcdf88f62b0 429 }while(0)
<> 128:9bcdf88f62b0 430
<> 128:9bcdf88f62b0 431 /** @brief Clear the SPI FRE pending flag.
<> 128:9bcdf88f62b0 432 * @param __HANDLE__: specifies the SPI handle.
<> 128:9bcdf88f62b0 433 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 434 * @retval None
<> 128:9bcdf88f62b0 435 */
<> 128:9bcdf88f62b0 436 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 437 do{ \
<> 128:9bcdf88f62b0 438 __IO uint32_t tmpreg_fre; \
<> 128:9bcdf88f62b0 439 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 128:9bcdf88f62b0 440 UNUSED(tmpreg_fre); \
<> 128:9bcdf88f62b0 441 }while(0)
<> 128:9bcdf88f62b0 442
<> 128:9bcdf88f62b0 443 /** @brief Enables the SPI.
<> 128:9bcdf88f62b0 444 * @param __HANDLE__: specifies the SPI Handle.
<> 128:9bcdf88f62b0 445 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 446 * @retval None
<> 128:9bcdf88f62b0 447 */
<> 128:9bcdf88f62b0 448 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 128:9bcdf88f62b0 449
<> 128:9bcdf88f62b0 450 /** @brief Disables the SPI.
<> 128:9bcdf88f62b0 451 * @param __HANDLE__: specifies the SPI Handle.
<> 128:9bcdf88f62b0 452 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 453 * @retval None
<> 128:9bcdf88f62b0 454 */
<> 128:9bcdf88f62b0 455 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 128:9bcdf88f62b0 456 /**
<> 128:9bcdf88f62b0 457 * @}
<> 128:9bcdf88f62b0 458 */
<> 128:9bcdf88f62b0 459
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /* Private macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 462 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 128:9bcdf88f62b0 463 * @{
<> 128:9bcdf88f62b0 464 */
<> 128:9bcdf88f62b0 465
<> 128:9bcdf88f62b0 466 /** @brief Sets the SPI transmit-only mode.
<> 128:9bcdf88f62b0 467 * @param __HANDLE__: specifies the SPI Handle.
<> 128:9bcdf88f62b0 468 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 469 * @retval None
<> 128:9bcdf88f62b0 470 */
<> 128:9bcdf88f62b0 471 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 128:9bcdf88f62b0 472
<> 128:9bcdf88f62b0 473 /** @brief Sets the SPI receive-only mode.
<> 128:9bcdf88f62b0 474 * @param __HANDLE__: specifies the SPI Handle.
<> 128:9bcdf88f62b0 475 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 476 * @retval None
<> 128:9bcdf88f62b0 477 */
<> 128:9bcdf88f62b0 478 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 128:9bcdf88f62b0 479
<> 128:9bcdf88f62b0 480 /** @brief Resets the CRC calculation of the SPI.
<> 128:9bcdf88f62b0 481 * @param __HANDLE__: specifies the SPI Handle.
<> 128:9bcdf88f62b0 482 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 128:9bcdf88f62b0 483 * @retval None
<> 128:9bcdf88f62b0 484 */
<> 128:9bcdf88f62b0 485 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
<> 128:9bcdf88f62b0 486 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
<> 128:9bcdf88f62b0 487 /**
<> 128:9bcdf88f62b0 488 * @}
<> 128:9bcdf88f62b0 489 */
<> 128:9bcdf88f62b0 490
<> 128:9bcdf88f62b0 491 /* Include SPI HAL Extension module */
<> 128:9bcdf88f62b0 492 #include "stm32l1xx_hal_spi_ex.h"
<> 128:9bcdf88f62b0 493
<> 128:9bcdf88f62b0 494 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 495 /** @addtogroup SPI_Exported_Functions
<> 128:9bcdf88f62b0 496 * @{
<> 128:9bcdf88f62b0 497 */
<> 128:9bcdf88f62b0 498
<> 128:9bcdf88f62b0 499 /* Initialization/de-initialization functions **********************************/
<> 128:9bcdf88f62b0 500 /** @addtogroup SPI_Exported_Functions_Group1
<> 128:9bcdf88f62b0 501 * @{
<> 128:9bcdf88f62b0 502 */
<> 128:9bcdf88f62b0 503 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 504 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 505 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 506 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 507 /**
<> 128:9bcdf88f62b0 508 * @}
<> 128:9bcdf88f62b0 509 */
<> 128:9bcdf88f62b0 510
<> 128:9bcdf88f62b0 511 /* I/O operation functions *****************************************************/
<> 128:9bcdf88f62b0 512 /** @addtogroup SPI_Exported_Functions_Group2
<> 128:9bcdf88f62b0 513 * @{
<> 128:9bcdf88f62b0 514 */
<> 128:9bcdf88f62b0 515 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 516 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 517 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 518 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 519 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 520 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 128:9bcdf88f62b0 521 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 522 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 523 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 128:9bcdf88f62b0 524 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 525 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 526 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 527
<> 128:9bcdf88f62b0 528 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 529 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 530 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 531 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 532 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 533 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 534 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 535 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 536 /**
<> 128:9bcdf88f62b0 537 * @}
<> 128:9bcdf88f62b0 538 */
<> 128:9bcdf88f62b0 539
<> 128:9bcdf88f62b0 540
<> 128:9bcdf88f62b0 541 /* Peripheral State and Control functions **************************************/
<> 128:9bcdf88f62b0 542 /** @addtogroup SPI_Exported_Functions_Group3
<> 128:9bcdf88f62b0 543 * @{
<> 128:9bcdf88f62b0 544 */
<> 128:9bcdf88f62b0 545 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 546 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 128:9bcdf88f62b0 547
<> 128:9bcdf88f62b0 548 /**
<> 128:9bcdf88f62b0 549 * @}
<> 128:9bcdf88f62b0 550 */
<> 128:9bcdf88f62b0 551
<> 128:9bcdf88f62b0 552 /**
<> 128:9bcdf88f62b0 553 * @}
<> 128:9bcdf88f62b0 554 */
<> 128:9bcdf88f62b0 555
<> 128:9bcdf88f62b0 556
<> 128:9bcdf88f62b0 557 /**
<> 128:9bcdf88f62b0 558 * @}
<> 128:9bcdf88f62b0 559 */
<> 128:9bcdf88f62b0 560
<> 128:9bcdf88f62b0 561 /**
<> 128:9bcdf88f62b0 562 * @}
<> 128:9bcdf88f62b0 563 */
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 #ifdef __cplusplus
<> 128:9bcdf88f62b0 566 }
<> 128:9bcdf88f62b0 567 #endif
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569 #endif /* __STM32L1xx_HAL_SPI_H */
<> 128:9bcdf88f62b0 570
<> 128:9bcdf88f62b0 571 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/