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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_pwr.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of PWR HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_PWR_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_PWR_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup PWR
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /**
<> 128:9bcdf88f62b0 64 * @brief PWR PVD configuration structure definition
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66 typedef struct
<> 128:9bcdf88f62b0 67 {
<> 128:9bcdf88f62b0 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 128:9bcdf88f62b0 69 This parameter can be a value of @ref PWR_PVD_detection_level */
<> 128:9bcdf88f62b0 70
<> 128:9bcdf88f62b0 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 128:9bcdf88f62b0 72 This parameter can be a value of @ref PWR_PVD_Mode */
<> 128:9bcdf88f62b0 73 }PWR_PVDTypeDef;
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 /**
<> 128:9bcdf88f62b0 76 * @}
<> 128:9bcdf88f62b0 77 */
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /* Internal constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 /** @addtogroup PWR_Private_Constants
<> 128:9bcdf88f62b0 82 * @{
<> 128:9bcdf88f62b0 83 */
<> 128:9bcdf88f62b0 84 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 /**
<> 128:9bcdf88f62b0 87 * @}
<> 128:9bcdf88f62b0 88 */
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 128:9bcdf88f62b0 95 * @{
<> 128:9bcdf88f62b0 96 */
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /** @defgroup PWR_register_alias_address PWR Register alias address
<> 128:9bcdf88f62b0 99 * @{
<> 128:9bcdf88f62b0 100 */
<> 128:9bcdf88f62b0 101 /* ------------- PWR registers bit address in the alias region ---------------*/
<> 128:9bcdf88f62b0 102 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
<> 128:9bcdf88f62b0 103 #define PWR_CR_OFFSET 0x00
<> 128:9bcdf88f62b0 104 #define PWR_CSR_OFFSET 0x04
<> 128:9bcdf88f62b0 105 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
<> 128:9bcdf88f62b0 106 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
<> 128:9bcdf88f62b0 107 /**
<> 128:9bcdf88f62b0 108 * @}
<> 128:9bcdf88f62b0 109 */
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
<> 128:9bcdf88f62b0 112 * @{
<> 128:9bcdf88f62b0 113 */
<> 128:9bcdf88f62b0 114 /* --- CR Register ---*/
<> 128:9bcdf88f62b0 115 /* Alias word address of LPSDSR bit */
<> 128:9bcdf88f62b0 116 #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR)
<> 128:9bcdf88f62b0 117 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 /* Alias word address of DBP bit */
<> 128:9bcdf88f62b0 120 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
<> 128:9bcdf88f62b0 121 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 /* Alias word address of LPRUN bit */
<> 128:9bcdf88f62b0 124 #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN)
<> 128:9bcdf88f62b0 125 #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 /* Alias word address of PVDE bit */
<> 128:9bcdf88f62b0 128 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
<> 128:9bcdf88f62b0 129 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 /* Alias word address of FWU bit */
<> 128:9bcdf88f62b0 132 #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU)
<> 128:9bcdf88f62b0 133 #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 134
<> 128:9bcdf88f62b0 135 /* Alias word address of ULP bit */
<> 128:9bcdf88f62b0 136 #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP)
<> 128:9bcdf88f62b0 137 #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
<> 128:9bcdf88f62b0 138 /**
<> 128:9bcdf88f62b0 139 * @}
<> 128:9bcdf88f62b0 140 */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
<> 128:9bcdf88f62b0 143 * @{
<> 128:9bcdf88f62b0 144 */
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 /* --- CSR Register ---*/
<> 128:9bcdf88f62b0 147 /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
<> 128:9bcdf88f62b0 148 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
<> 128:9bcdf88f62b0 149 /**
<> 128:9bcdf88f62b0 150 * @}
<> 128:9bcdf88f62b0 151 */
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
<> 128:9bcdf88f62b0 154 * @{
<> 128:9bcdf88f62b0 155 */
<> 128:9bcdf88f62b0 156 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 128:9bcdf88f62b0 157 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 128:9bcdf88f62b0 158 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 128:9bcdf88f62b0 159 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 128:9bcdf88f62b0 160 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 128:9bcdf88f62b0 161 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 128:9bcdf88f62b0 162 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 128:9bcdf88f62b0 163 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
<> 128:9bcdf88f62b0 164 (Compare internally to VREFINT) */
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 /**
<> 128:9bcdf88f62b0 167 * @}
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 /** @defgroup PWR_PVD_Mode PWR PVD Mode
<> 128:9bcdf88f62b0 171 * @{
<> 128:9bcdf88f62b0 172 */
<> 128:9bcdf88f62b0 173 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
<> 128:9bcdf88f62b0 174 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 128:9bcdf88f62b0 175 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 128:9bcdf88f62b0 176 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 128:9bcdf88f62b0 177 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 128:9bcdf88f62b0 178 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 128:9bcdf88f62b0 179 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 /**
<> 128:9bcdf88f62b0 182 * @}
<> 128:9bcdf88f62b0 183 */
<> 128:9bcdf88f62b0 184
<> 128:9bcdf88f62b0 185 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
<> 128:9bcdf88f62b0 186 * @{
<> 128:9bcdf88f62b0 187 */
<> 128:9bcdf88f62b0 188 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 189 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
<> 128:9bcdf88f62b0 190
<> 128:9bcdf88f62b0 191 /**
<> 128:9bcdf88f62b0 192 * @}
<> 128:9bcdf88f62b0 193 */
<> 128:9bcdf88f62b0 194
<> 128:9bcdf88f62b0 195 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 128:9bcdf88f62b0 196 * @{
<> 128:9bcdf88f62b0 197 */
<> 128:9bcdf88f62b0 198 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
<> 128:9bcdf88f62b0 199 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 /**
<> 128:9bcdf88f62b0 202 * @}
<> 128:9bcdf88f62b0 203 */
<> 128:9bcdf88f62b0 204
<> 128:9bcdf88f62b0 205 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 128:9bcdf88f62b0 206 * @{
<> 128:9bcdf88f62b0 207 */
<> 128:9bcdf88f62b0 208 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
<> 128:9bcdf88f62b0 209 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
<> 128:9bcdf88f62b0 210
<> 128:9bcdf88f62b0 211 /**
<> 128:9bcdf88f62b0 212 * @}
<> 128:9bcdf88f62b0 213 */
<> 128:9bcdf88f62b0 214
<> 128:9bcdf88f62b0 215 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
<> 128:9bcdf88f62b0 216 * @{
<> 128:9bcdf88f62b0 217 */
<> 128:9bcdf88f62b0 218
<> 128:9bcdf88f62b0 219 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
<> 128:9bcdf88f62b0 220 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
<> 128:9bcdf88f62b0 221 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
<> 128:9bcdf88f62b0 222
<> 128:9bcdf88f62b0 223
<> 128:9bcdf88f62b0 224 /**
<> 128:9bcdf88f62b0 225 * @}
<> 128:9bcdf88f62b0 226 */
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 /** @defgroup PWR_Flag PWR Flag
<> 128:9bcdf88f62b0 229 * @{
<> 128:9bcdf88f62b0 230 */
<> 128:9bcdf88f62b0 231 #define PWR_FLAG_WU PWR_CSR_WUF
<> 128:9bcdf88f62b0 232 #define PWR_FLAG_SB PWR_CSR_SBF
<> 128:9bcdf88f62b0 233 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 128:9bcdf88f62b0 234 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 128:9bcdf88f62b0 235 #define PWR_FLAG_VOS PWR_CSR_VOSF
<> 128:9bcdf88f62b0 236 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 /**
<> 128:9bcdf88f62b0 239 * @}
<> 128:9bcdf88f62b0 240 */
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 /**
<> 128:9bcdf88f62b0 243 * @}
<> 128:9bcdf88f62b0 244 */
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 247 /** @defgroup PWR_Exported_Macros PWR Exported Macros
<> 128:9bcdf88f62b0 248 * @{
<> 128:9bcdf88f62b0 249 */
<> 128:9bcdf88f62b0 250
<> 128:9bcdf88f62b0 251 /** @brief macros configure the main internal regulator output voltage.
<> 128:9bcdf88f62b0 252 * @param __REGULATOR__: specifies the regulator output voltage to achieve
<> 128:9bcdf88f62b0 253 * a tradeoff between performance and power consumption when the device does
<> 128:9bcdf88f62b0 254 * not operate at the maximum frequency (refer to the datasheets for more details).
<> 128:9bcdf88f62b0 255 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 256 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
<> 128:9bcdf88f62b0 257 * System frequency up to 32 MHz.
<> 128:9bcdf88f62b0 258 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
<> 128:9bcdf88f62b0 259 * System frequency up to 16 MHz.
<> 128:9bcdf88f62b0 260 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
<> 128:9bcdf88f62b0 261 * System frequency up to 4.2 MHz
<> 128:9bcdf88f62b0 262 * @retval None
<> 128:9bcdf88f62b0 263 */
<> 128:9bcdf88f62b0 264 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 /** @brief Check PWR flag is set or not.
<> 128:9bcdf88f62b0 267 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 268 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 269 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
<> 128:9bcdf88f62b0 270 * was received from the WKUP pin or from the RTC alarm (Alarm B),
<> 128:9bcdf88f62b0 271 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
<> 128:9bcdf88f62b0 272 * An additional wakeup event is detected if the WKUP pin is enabled
<> 128:9bcdf88f62b0 273 * (by setting the EWUP bit) when the WKUP pin level is already high.
<> 128:9bcdf88f62b0 274 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
<> 128:9bcdf88f62b0 275 * resumed from StandBy mode.
<> 128:9bcdf88f62b0 276 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
<> 128:9bcdf88f62b0 277 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
<> 128:9bcdf88f62b0 278 * For this reason, this bit is equal to 0 after Standby or reset
<> 128:9bcdf88f62b0 279 * until the PVDE bit is set.
<> 128:9bcdf88f62b0 280 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
<> 128:9bcdf88f62b0 281 * This bit indicates the state of the internal voltage reference, VREFINT.
<> 128:9bcdf88f62b0 282 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
<> 128:9bcdf88f62b0 283 * the internal regulator to be ready after the voltage range is changed.
<> 128:9bcdf88f62b0 284 * The VOSF bit indicates that the regulator has reached the voltage level
<> 128:9bcdf88f62b0 285 * defined with bits VOS of PWR_CR register.
<> 128:9bcdf88f62b0 286 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
<> 128:9bcdf88f62b0 287 * mode, this bit stays at 1 until the regulator is ready in main mode.
<> 128:9bcdf88f62b0 288 * A polling on this bit is recommended to wait for the regulator main mode.
<> 128:9bcdf88f62b0 289 * This bit is reset by hardware when the regulator is ready.
<> 128:9bcdf88f62b0 290 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 291 */
<> 128:9bcdf88f62b0 292 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 293
<> 128:9bcdf88f62b0 294 /** @brief Clear the PWR's pending flags.
<> 128:9bcdf88f62b0 295 * @param __FLAG__: specifies the flag to clear.
<> 128:9bcdf88f62b0 296 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 297 * @arg PWR_FLAG_WU: Wake Up flag
<> 128:9bcdf88f62b0 298 * @arg PWR_FLAG_SB: StandBy flag
<> 128:9bcdf88f62b0 299 */
<> 128:9bcdf88f62b0 300 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /**
<> 128:9bcdf88f62b0 303 * @brief Enable interrupt on PVD Exti Line 16.
<> 128:9bcdf88f62b0 304 * @retval None.
<> 128:9bcdf88f62b0 305 */
<> 128:9bcdf88f62b0 306 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 307
<> 128:9bcdf88f62b0 308 /**
<> 128:9bcdf88f62b0 309 * @brief Disable interrupt on PVD Exti Line 16.
<> 128:9bcdf88f62b0 310 * @retval None.
<> 128:9bcdf88f62b0 311 */
<> 128:9bcdf88f62b0 312 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 313
<> 128:9bcdf88f62b0 314 /**
<> 128:9bcdf88f62b0 315 * @brief Enable event on PVD Exti Line 16.
<> 128:9bcdf88f62b0 316 * @retval None.
<> 128:9bcdf88f62b0 317 */
<> 128:9bcdf88f62b0 318 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 319
<> 128:9bcdf88f62b0 320 /**
<> 128:9bcdf88f62b0 321 * @brief Disable event on PVD Exti Line 16.
<> 128:9bcdf88f62b0 322 * @retval None.
<> 128:9bcdf88f62b0 323 */
<> 128:9bcdf88f62b0 324 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326
<> 128:9bcdf88f62b0 327 /**
<> 128:9bcdf88f62b0 328 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 128:9bcdf88f62b0 329 * @retval None.
<> 128:9bcdf88f62b0 330 */
<> 128:9bcdf88f62b0 331 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 332
<> 128:9bcdf88f62b0 333
<> 128:9bcdf88f62b0 334 /**
<> 128:9bcdf88f62b0 335 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 128:9bcdf88f62b0 336 * @retval None.
<> 128:9bcdf88f62b0 337 */
<> 128:9bcdf88f62b0 338 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 339
<> 128:9bcdf88f62b0 340
<> 128:9bcdf88f62b0 341 /**
<> 128:9bcdf88f62b0 342 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 128:9bcdf88f62b0 343 * @retval None.
<> 128:9bcdf88f62b0 344 */
<> 128:9bcdf88f62b0 345 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 /**
<> 128:9bcdf88f62b0 348 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 128:9bcdf88f62b0 349 * @retval None.
<> 128:9bcdf88f62b0 350 */
<> 128:9bcdf88f62b0 351 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 352
<> 128:9bcdf88f62b0 353 /**
<> 128:9bcdf88f62b0 354 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
<> 128:9bcdf88f62b0 355 * @retval None.
<> 128:9bcdf88f62b0 356 */
<> 128:9bcdf88f62b0 357 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 128:9bcdf88f62b0 358 do { \
<> 128:9bcdf88f62b0 359 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
<> 128:9bcdf88f62b0 360 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
<> 128:9bcdf88f62b0 361 } while(0)
<> 128:9bcdf88f62b0 362
<> 128:9bcdf88f62b0 363 /**
<> 128:9bcdf88f62b0 364 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 128:9bcdf88f62b0 365 * @retval None.
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 128:9bcdf88f62b0 368 do { \
<> 128:9bcdf88f62b0 369 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
<> 128:9bcdf88f62b0 370 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
<> 128:9bcdf88f62b0 371 } while(0)
<> 128:9bcdf88f62b0 372
<> 128:9bcdf88f62b0 373
<> 128:9bcdf88f62b0 374
<> 128:9bcdf88f62b0 375 /**
<> 128:9bcdf88f62b0 376 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 128:9bcdf88f62b0 377 * @retval EXTI PVD Line Status.
<> 128:9bcdf88f62b0 378 */
<> 128:9bcdf88f62b0 379 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 128:9bcdf88f62b0 380
<> 128:9bcdf88f62b0 381 /**
<> 128:9bcdf88f62b0 382 * @brief Clear the PVD EXTI flag.
<> 128:9bcdf88f62b0 383 * @retval None.
<> 128:9bcdf88f62b0 384 */
<> 128:9bcdf88f62b0 385 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 128:9bcdf88f62b0 386
<> 128:9bcdf88f62b0 387 /**
<> 128:9bcdf88f62b0 388 * @brief Generate a Software interrupt on selected EXTI line.
<> 128:9bcdf88f62b0 389 * @retval None.
<> 128:9bcdf88f62b0 390 */
<> 128:9bcdf88f62b0 391 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /**
<> 128:9bcdf88f62b0 394 * @}
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396
<> 128:9bcdf88f62b0 397 /* Private macro -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 398 /** @defgroup PWR_Private_Macros PWR Private Macros
<> 128:9bcdf88f62b0 399 * @{
<> 128:9bcdf88f62b0 400 */
<> 128:9bcdf88f62b0 401
<> 128:9bcdf88f62b0 402 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 128:9bcdf88f62b0 403 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 128:9bcdf88f62b0 404 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 128:9bcdf88f62b0 405 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 128:9bcdf88f62b0 406
<> 128:9bcdf88f62b0 407
<> 128:9bcdf88f62b0 408 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 128:9bcdf88f62b0 409 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 128:9bcdf88f62b0 410 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 128:9bcdf88f62b0 411 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 128:9bcdf88f62b0 412
<> 128:9bcdf88f62b0 413 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 128:9bcdf88f62b0 414 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 128:9bcdf88f62b0 415
<> 128:9bcdf88f62b0 416
<> 128:9bcdf88f62b0 417 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 128:9bcdf88f62b0 418
<> 128:9bcdf88f62b0 419 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
<> 128:9bcdf88f62b0 420
<> 128:9bcdf88f62b0 421 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
<> 128:9bcdf88f62b0 422 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
<> 128:9bcdf88f62b0 423 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
<> 128:9bcdf88f62b0 424
<> 128:9bcdf88f62b0 425
<> 128:9bcdf88f62b0 426 /**
<> 128:9bcdf88f62b0 427 * @}
<> 128:9bcdf88f62b0 428 */
<> 128:9bcdf88f62b0 429
<> 128:9bcdf88f62b0 430
<> 128:9bcdf88f62b0 431
<> 128:9bcdf88f62b0 432 /* Include PWR HAL Extension module */
<> 128:9bcdf88f62b0 433 #include "stm32l1xx_hal_pwr_ex.h"
<> 128:9bcdf88f62b0 434
<> 128:9bcdf88f62b0 435 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 436
<> 128:9bcdf88f62b0 437 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
<> 128:9bcdf88f62b0 438 * @{
<> 128:9bcdf88f62b0 439 */
<> 128:9bcdf88f62b0 440
<> 128:9bcdf88f62b0 441 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 128:9bcdf88f62b0 442 * @{
<> 128:9bcdf88f62b0 443 */
<> 128:9bcdf88f62b0 444
<> 128:9bcdf88f62b0 445 /* Initialization and de-initialization functions *******************************/
<> 128:9bcdf88f62b0 446 void HAL_PWR_DeInit(void);
<> 128:9bcdf88f62b0 447 void HAL_PWR_EnableBkUpAccess(void);
<> 128:9bcdf88f62b0 448 void HAL_PWR_DisableBkUpAccess(void);
<> 128:9bcdf88f62b0 449
<> 128:9bcdf88f62b0 450 /**
<> 128:9bcdf88f62b0 451 * @}
<> 128:9bcdf88f62b0 452 */
<> 128:9bcdf88f62b0 453
<> 128:9bcdf88f62b0 454 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 128:9bcdf88f62b0 455 * @{
<> 128:9bcdf88f62b0 456 */
<> 128:9bcdf88f62b0 457
<> 128:9bcdf88f62b0 458 /* Peripheral Control functions ************************************************/
<> 128:9bcdf88f62b0 459 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 128:9bcdf88f62b0 460 void HAL_PWR_EnablePVD(void);
<> 128:9bcdf88f62b0 461 void HAL_PWR_DisablePVD(void);
<> 128:9bcdf88f62b0 462
<> 128:9bcdf88f62b0 463 /* WakeUp pins configuration functions ****************************************/
<> 128:9bcdf88f62b0 464 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
<> 128:9bcdf88f62b0 465 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 128:9bcdf88f62b0 466
<> 128:9bcdf88f62b0 467 /* Low Power modes configuration functions ************************************/
<> 128:9bcdf88f62b0 468 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 128:9bcdf88f62b0 469 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 128:9bcdf88f62b0 470 void HAL_PWR_EnterSTANDBYMode(void);
<> 128:9bcdf88f62b0 471
<> 128:9bcdf88f62b0 472 void HAL_PWR_EnableSleepOnExit(void);
<> 128:9bcdf88f62b0 473 void HAL_PWR_DisableSleepOnExit(void);
<> 128:9bcdf88f62b0 474 void HAL_PWR_EnableSEVOnPend(void);
<> 128:9bcdf88f62b0 475 void HAL_PWR_DisableSEVOnPend(void);
<> 128:9bcdf88f62b0 476
<> 128:9bcdf88f62b0 477
<> 128:9bcdf88f62b0 478
<> 128:9bcdf88f62b0 479 void HAL_PWR_PVD_IRQHandler(void);
<> 128:9bcdf88f62b0 480 void HAL_PWR_PVDCallback(void);
<> 128:9bcdf88f62b0 481 /**
<> 128:9bcdf88f62b0 482 * @}
<> 128:9bcdf88f62b0 483 */
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485 /**
<> 128:9bcdf88f62b0 486 * @}
<> 128:9bcdf88f62b0 487 */
<> 128:9bcdf88f62b0 488
<> 128:9bcdf88f62b0 489 /**
<> 128:9bcdf88f62b0 490 * @}
<> 128:9bcdf88f62b0 491 */
<> 128:9bcdf88f62b0 492
<> 128:9bcdf88f62b0 493 /**
<> 128:9bcdf88f62b0 494 * @}
<> 128:9bcdf88f62b0 495 */
<> 128:9bcdf88f62b0 496
<> 128:9bcdf88f62b0 497 #ifdef __cplusplus
<> 128:9bcdf88f62b0 498 }
<> 128:9bcdf88f62b0 499 #endif
<> 128:9bcdf88f62b0 500
<> 128:9bcdf88f62b0 501
<> 128:9bcdf88f62b0 502 #endif /* __STM32L1xx_HAL_PWR_H */
<> 128:9bcdf88f62b0 503
<> 128:9bcdf88f62b0 504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/