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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_lcd.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_lcd.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of LCD Controller HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_LCD_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_LCD_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 47 * @{
<> 128:9bcdf88f62b0 48 */
<> 128:9bcdf88f62b0 49
<> 128:9bcdf88f62b0 50 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
<> 128:9bcdf88f62b0 51 defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
<> 128:9bcdf88f62b0 52 defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 55 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /** @addtogroup LCD
<> 128:9bcdf88f62b0 58 * @{
<> 128:9bcdf88f62b0 59 */
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /** @defgroup LCD_Exported_Types LCD Exported Types
<> 128:9bcdf88f62b0 64 * @{
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 /**
<> 128:9bcdf88f62b0 68 * @brief LCD Init structure definition
<> 128:9bcdf88f62b0 69 */
<> 128:9bcdf88f62b0 70
<> 128:9bcdf88f62b0 71 typedef struct
<> 128:9bcdf88f62b0 72 {
<> 128:9bcdf88f62b0 73 uint32_t Prescaler; /*!< Configures the LCD Prescaler.
<> 128:9bcdf88f62b0 74 This parameter can be one value of @ref LCD_Prescaler */
<> 128:9bcdf88f62b0 75 uint32_t Divider; /*!< Configures the LCD Divider.
<> 128:9bcdf88f62b0 76 This parameter can be one value of @ref LCD_Divider */
<> 128:9bcdf88f62b0 77 uint32_t Duty; /*!< Configures the LCD Duty.
<> 128:9bcdf88f62b0 78 This parameter can be one value of @ref LCD_Duty */
<> 128:9bcdf88f62b0 79 uint32_t Bias; /*!< Configures the LCD Bias.
<> 128:9bcdf88f62b0 80 This parameter can be one value of @ref LCD_Bias */
<> 128:9bcdf88f62b0 81 uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
<> 128:9bcdf88f62b0 82 This parameter can be one value of @ref LCD_Voltage_Source */
<> 128:9bcdf88f62b0 83 uint32_t Contrast; /*!< Configures the LCD Contrast.
<> 128:9bcdf88f62b0 84 This parameter can be one value of @ref LCD_Contrast */
<> 128:9bcdf88f62b0 85 uint32_t DeadTime; /*!< Configures the LCD Dead Time.
<> 128:9bcdf88f62b0 86 This parameter can be one value of @ref LCD_DeadTime */
<> 128:9bcdf88f62b0 87 uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
<> 128:9bcdf88f62b0 88 This parameter can be one value of @ref LCD_PulseOnDuration */
<> 128:9bcdf88f62b0 89 uint32_t HighDrive; /*!< Configures the LCD High Drive.
<> 128:9bcdf88f62b0 90 This parameter can be one value of @ref LCD_HighDrive */
<> 128:9bcdf88f62b0 91 uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
<> 128:9bcdf88f62b0 92 This parameter can be one value of @ref LCD_BlinkMode */
<> 128:9bcdf88f62b0 93 uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency.
<> 128:9bcdf88f62b0 94 This parameter can be one value of @ref LCD_BlinkFrequency */
<> 128:9bcdf88f62b0 95 uint32_t MuxSegment; /*!< Enable or disable mux segment.
<> 128:9bcdf88f62b0 96 This parameter can be set to ENABLE or DISABLE. */
<> 128:9bcdf88f62b0 97 }LCD_InitTypeDef;
<> 128:9bcdf88f62b0 98
<> 128:9bcdf88f62b0 99 /**
<> 128:9bcdf88f62b0 100 * @brief HAL LCD State structures definition
<> 128:9bcdf88f62b0 101 */
<> 128:9bcdf88f62b0 102 typedef enum
<> 128:9bcdf88f62b0 103 {
<> 128:9bcdf88f62b0 104 HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
<> 128:9bcdf88f62b0 105 HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 128:9bcdf88f62b0 106 HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
<> 128:9bcdf88f62b0 107 HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 128:9bcdf88f62b0 108 HAL_LCD_STATE_ERROR = 0x04 /*!< Error */
<> 128:9bcdf88f62b0 109 }HAL_LCD_StateTypeDef;
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 /**
<> 128:9bcdf88f62b0 112 * @brief UART handle Structure definition
<> 128:9bcdf88f62b0 113 */
<> 128:9bcdf88f62b0 114 typedef struct
<> 128:9bcdf88f62b0 115 {
<> 128:9bcdf88f62b0 116 LCD_TypeDef *Instance; /* LCD registers base address */
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 LCD_InitTypeDef Init; /* LCD communication parameters */
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 HAL_LockTypeDef Lock; /* Locking object */
<> 128:9bcdf88f62b0 121
<> 128:9bcdf88f62b0 122 __IO HAL_LCD_StateTypeDef State; /* LCD communication state */
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124 __IO uint32_t ErrorCode; /* LCD Error code */
<> 128:9bcdf88f62b0 125
<> 128:9bcdf88f62b0 126 }LCD_HandleTypeDef;
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 /**
<> 128:9bcdf88f62b0 129 * @}
<> 128:9bcdf88f62b0 130 */
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 /** @defgroup LCD_Exported_Constants LCD Exported Constants
<> 128:9bcdf88f62b0 135 * @{
<> 128:9bcdf88f62b0 136 */
<> 128:9bcdf88f62b0 137
<> 128:9bcdf88f62b0 138 /** @defgroup LCD_Error_Codes LCD Error Codes
<> 128:9bcdf88f62b0 139 * @{
<> 128:9bcdf88f62b0 140 */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 #define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 128:9bcdf88f62b0 143 #define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */
<> 128:9bcdf88f62b0 144 #define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */
<> 128:9bcdf88f62b0 145 #define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */
<> 128:9bcdf88f62b0 146 #define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */
<> 128:9bcdf88f62b0 147 #define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */
<> 128:9bcdf88f62b0 148
<> 128:9bcdf88f62b0 149 /**
<> 128:9bcdf88f62b0 150 * @}
<> 128:9bcdf88f62b0 151 */
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /** @defgroup LCD_Prescaler LCD Prescaler
<> 128:9bcdf88f62b0 154 * @{
<> 128:9bcdf88f62b0 155 */
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 #define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */
<> 128:9bcdf88f62b0 158 #define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */
<> 128:9bcdf88f62b0 159 #define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */
<> 128:9bcdf88f62b0 160 #define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */
<> 128:9bcdf88f62b0 161 #define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */
<> 128:9bcdf88f62b0 162 #define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */
<> 128:9bcdf88f62b0 163 #define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */
<> 128:9bcdf88f62b0 164 #define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */
<> 128:9bcdf88f62b0 165 #define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */
<> 128:9bcdf88f62b0 166 #define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */
<> 128:9bcdf88f62b0 167 #define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */
<> 128:9bcdf88f62b0 168 #define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */
<> 128:9bcdf88f62b0 169 #define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */
<> 128:9bcdf88f62b0 170 #define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */
<> 128:9bcdf88f62b0 171 #define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */
<> 128:9bcdf88f62b0 172 #define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
<> 128:9bcdf88f62b0 175 ((__PRESCALER__) == LCD_PRESCALER_2) || \
<> 128:9bcdf88f62b0 176 ((__PRESCALER__) == LCD_PRESCALER_4) || \
<> 128:9bcdf88f62b0 177 ((__PRESCALER__) == LCD_PRESCALER_8) || \
<> 128:9bcdf88f62b0 178 ((__PRESCALER__) == LCD_PRESCALER_16) || \
<> 128:9bcdf88f62b0 179 ((__PRESCALER__) == LCD_PRESCALER_32) || \
<> 128:9bcdf88f62b0 180 ((__PRESCALER__) == LCD_PRESCALER_64) || \
<> 128:9bcdf88f62b0 181 ((__PRESCALER__) == LCD_PRESCALER_128) || \
<> 128:9bcdf88f62b0 182 ((__PRESCALER__) == LCD_PRESCALER_256) || \
<> 128:9bcdf88f62b0 183 ((__PRESCALER__) == LCD_PRESCALER_512) || \
<> 128:9bcdf88f62b0 184 ((__PRESCALER__) == LCD_PRESCALER_1024) || \
<> 128:9bcdf88f62b0 185 ((__PRESCALER__) == LCD_PRESCALER_2048) || \
<> 128:9bcdf88f62b0 186 ((__PRESCALER__) == LCD_PRESCALER_4096) || \
<> 128:9bcdf88f62b0 187 ((__PRESCALER__) == LCD_PRESCALER_8192) || \
<> 128:9bcdf88f62b0 188 ((__PRESCALER__) == LCD_PRESCALER_16384) || \
<> 128:9bcdf88f62b0 189 ((__PRESCALER__) == LCD_PRESCALER_32768))
<> 128:9bcdf88f62b0 190
<> 128:9bcdf88f62b0 191 /**
<> 128:9bcdf88f62b0 192 * @}
<> 128:9bcdf88f62b0 193 */
<> 128:9bcdf88f62b0 194
<> 128:9bcdf88f62b0 195 /** @defgroup LCD_Divider LCD Divider
<> 128:9bcdf88f62b0 196 * @{
<> 128:9bcdf88f62b0 197 */
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 #define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */
<> 128:9bcdf88f62b0 200 #define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */
<> 128:9bcdf88f62b0 201 #define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */
<> 128:9bcdf88f62b0 202 #define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */
<> 128:9bcdf88f62b0 203 #define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */
<> 128:9bcdf88f62b0 204 #define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */
<> 128:9bcdf88f62b0 205 #define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */
<> 128:9bcdf88f62b0 206 #define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */
<> 128:9bcdf88f62b0 207 #define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */
<> 128:9bcdf88f62b0 208 #define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */
<> 128:9bcdf88f62b0 209 #define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */
<> 128:9bcdf88f62b0 210 #define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */
<> 128:9bcdf88f62b0 211 #define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */
<> 128:9bcdf88f62b0 212 #define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */
<> 128:9bcdf88f62b0 213 #define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */
<> 128:9bcdf88f62b0 214 #define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
<> 128:9bcdf88f62b0 217 ((__DIVIDER__) == LCD_DIVIDER_17) || \
<> 128:9bcdf88f62b0 218 ((__DIVIDER__) == LCD_DIVIDER_18) || \
<> 128:9bcdf88f62b0 219 ((__DIVIDER__) == LCD_DIVIDER_19) || \
<> 128:9bcdf88f62b0 220 ((__DIVIDER__) == LCD_DIVIDER_20) || \
<> 128:9bcdf88f62b0 221 ((__DIVIDER__) == LCD_DIVIDER_21) || \
<> 128:9bcdf88f62b0 222 ((__DIVIDER__) == LCD_DIVIDER_22) || \
<> 128:9bcdf88f62b0 223 ((__DIVIDER__) == LCD_DIVIDER_23) || \
<> 128:9bcdf88f62b0 224 ((__DIVIDER__) == LCD_DIVIDER_24) || \
<> 128:9bcdf88f62b0 225 ((__DIVIDER__) == LCD_DIVIDER_25) || \
<> 128:9bcdf88f62b0 226 ((__DIVIDER__) == LCD_DIVIDER_26) || \
<> 128:9bcdf88f62b0 227 ((__DIVIDER__) == LCD_DIVIDER_27) || \
<> 128:9bcdf88f62b0 228 ((__DIVIDER__) == LCD_DIVIDER_28) || \
<> 128:9bcdf88f62b0 229 ((__DIVIDER__) == LCD_DIVIDER_29) || \
<> 128:9bcdf88f62b0 230 ((__DIVIDER__) == LCD_DIVIDER_30) || \
<> 128:9bcdf88f62b0 231 ((__DIVIDER__) == LCD_DIVIDER_31))
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 /**
<> 128:9bcdf88f62b0 234 * @}
<> 128:9bcdf88f62b0 235 */
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 /** @defgroup LCD_Duty LCD Duty
<> 128:9bcdf88f62b0 239 * @{
<> 128:9bcdf88f62b0 240 */
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 #define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */
<> 128:9bcdf88f62b0 243 #define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
<> 128:9bcdf88f62b0 244 #define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
<> 128:9bcdf88f62b0 245 #define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
<> 128:9bcdf88f62b0 246 #define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 #define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \
<> 128:9bcdf88f62b0 249 ((__DUTY__) == LCD_DUTY_1_2) || \
<> 128:9bcdf88f62b0 250 ((__DUTY__) == LCD_DUTY_1_3) || \
<> 128:9bcdf88f62b0 251 ((__DUTY__) == LCD_DUTY_1_4) || \
<> 128:9bcdf88f62b0 252 ((__DUTY__) == LCD_DUTY_1_8))
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 /**
<> 128:9bcdf88f62b0 255 * @}
<> 128:9bcdf88f62b0 256 */
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258
<> 128:9bcdf88f62b0 259 /** @defgroup LCD_Bias LCD Bias
<> 128:9bcdf88f62b0 260 * @{
<> 128:9bcdf88f62b0 261 */
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 #define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */
<> 128:9bcdf88f62b0 264 #define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
<> 128:9bcdf88f62b0 265 #define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
<> 128:9bcdf88f62b0 266
<> 128:9bcdf88f62b0 267 #define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
<> 128:9bcdf88f62b0 268 ((__BIAS__) == LCD_BIAS_1_2) || \
<> 128:9bcdf88f62b0 269 ((__BIAS__) == LCD_BIAS_1_3))
<> 128:9bcdf88f62b0 270 /**
<> 128:9bcdf88f62b0 271 * @}
<> 128:9bcdf88f62b0 272 */
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 /** @defgroup LCD_Voltage_Source LCD Voltage Source
<> 128:9bcdf88f62b0 275 * @{
<> 128:9bcdf88f62b0 276 */
<> 128:9bcdf88f62b0 277
<> 128:9bcdf88f62b0 278 #define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */
<> 128:9bcdf88f62b0 279 #define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
<> 128:9bcdf88f62b0 280
<> 128:9bcdf88f62b0 281 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
<> 128:9bcdf88f62b0 282 ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
<> 128:9bcdf88f62b0 283
<> 128:9bcdf88f62b0 284 /**
<> 128:9bcdf88f62b0 285 * @}
<> 128:9bcdf88f62b0 286 */
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 /** @defgroup LCD_Interrupts LCD Interrupts
<> 128:9bcdf88f62b0 289 * @{
<> 128:9bcdf88f62b0 290 */
<> 128:9bcdf88f62b0 291 #define LCD_IT_SOF LCD_FCR_SOFIE
<> 128:9bcdf88f62b0 292 #define LCD_IT_UDD LCD_FCR_UDDIE
<> 128:9bcdf88f62b0 293
<> 128:9bcdf88f62b0 294 /**
<> 128:9bcdf88f62b0 295 * @}
<> 128:9bcdf88f62b0 296 */
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
<> 128:9bcdf88f62b0 299 * @{
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 #define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */
<> 128:9bcdf88f62b0 303 #define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
<> 128:9bcdf88f62b0 304 #define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
<> 128:9bcdf88f62b0 305 #define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
<> 128:9bcdf88f62b0 306 #define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */
<> 128:9bcdf88f62b0 307 #define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */
<> 128:9bcdf88f62b0 308 #define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */
<> 128:9bcdf88f62b0 309 #define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */
<> 128:9bcdf88f62b0 310
<> 128:9bcdf88f62b0 311 #define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
<> 128:9bcdf88f62b0 312 ((__DURATION__) == LCD_PULSEONDURATION_1) || \
<> 128:9bcdf88f62b0 313 ((__DURATION__) == LCD_PULSEONDURATION_2) || \
<> 128:9bcdf88f62b0 314 ((__DURATION__) == LCD_PULSEONDURATION_3) || \
<> 128:9bcdf88f62b0 315 ((__DURATION__) == LCD_PULSEONDURATION_4) || \
<> 128:9bcdf88f62b0 316 ((__DURATION__) == LCD_PULSEONDURATION_5) || \
<> 128:9bcdf88f62b0 317 ((__DURATION__) == LCD_PULSEONDURATION_6) || \
<> 128:9bcdf88f62b0 318 ((__DURATION__) == LCD_PULSEONDURATION_7))
<> 128:9bcdf88f62b0 319 /**
<> 128:9bcdf88f62b0 320 * @}
<> 128:9bcdf88f62b0 321 */
<> 128:9bcdf88f62b0 322
<> 128:9bcdf88f62b0 323 /** @defgroup LCD_HighDrive LCD HighDrive
<> 128:9bcdf88f62b0 324 * @{
<> 128:9bcdf88f62b0 325 */
<> 128:9bcdf88f62b0 326
<> 128:9bcdf88f62b0 327 #define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */
<> 128:9bcdf88f62b0 328 #define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */
<> 128:9bcdf88f62b0 329
<> 128:9bcdf88f62b0 330 #define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
<> 128:9bcdf88f62b0 331 ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1))
<> 128:9bcdf88f62b0 332 /**
<> 128:9bcdf88f62b0 333 * @}
<> 128:9bcdf88f62b0 334 */
<> 128:9bcdf88f62b0 335
<> 128:9bcdf88f62b0 336 /** @defgroup LCD_DeadTime LCD Dead Time
<> 128:9bcdf88f62b0 337 * @{
<> 128:9bcdf88f62b0 338 */
<> 128:9bcdf88f62b0 339
<> 128:9bcdf88f62b0 340 #define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */
<> 128:9bcdf88f62b0 341 #define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
<> 128:9bcdf88f62b0 342 #define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
<> 128:9bcdf88f62b0 343 #define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
<> 128:9bcdf88f62b0 344 #define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */
<> 128:9bcdf88f62b0 345 #define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */
<> 128:9bcdf88f62b0 346 #define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */
<> 128:9bcdf88f62b0 347 #define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */
<> 128:9bcdf88f62b0 348
<> 128:9bcdf88f62b0 349 #define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
<> 128:9bcdf88f62b0 350 ((__TIME__) == LCD_DEADTIME_1) || \
<> 128:9bcdf88f62b0 351 ((__TIME__) == LCD_DEADTIME_2) || \
<> 128:9bcdf88f62b0 352 ((__TIME__) == LCD_DEADTIME_3) || \
<> 128:9bcdf88f62b0 353 ((__TIME__) == LCD_DEADTIME_4) || \
<> 128:9bcdf88f62b0 354 ((__TIME__) == LCD_DEADTIME_5) || \
<> 128:9bcdf88f62b0 355 ((__TIME__) == LCD_DEADTIME_6) || \
<> 128:9bcdf88f62b0 356 ((__TIME__) == LCD_DEADTIME_7))
<> 128:9bcdf88f62b0 357 /**
<> 128:9bcdf88f62b0 358 * @}
<> 128:9bcdf88f62b0 359 */
<> 128:9bcdf88f62b0 360
<> 128:9bcdf88f62b0 361 /** @defgroup LCD_BlinkMode LCD Blink Mode
<> 128:9bcdf88f62b0 362 * @{
<> 128:9bcdf88f62b0 363 */
<> 128:9bcdf88f62b0 364
<> 128:9bcdf88f62b0 365 #define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */
<> 128:9bcdf88f62b0 366 #define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
<> 128:9bcdf88f62b0 367 #define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
<> 128:9bcdf88f62b0 368 8 pixels according to the programmed duty) */
<> 128:9bcdf88f62b0 369 #define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */
<> 128:9bcdf88f62b0 370
<> 128:9bcdf88f62b0 371 #define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \
<> 128:9bcdf88f62b0 372 ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \
<> 128:9bcdf88f62b0 373 ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \
<> 128:9bcdf88f62b0 374 ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
<> 128:9bcdf88f62b0 375 /**
<> 128:9bcdf88f62b0 376 * @}
<> 128:9bcdf88f62b0 377 */
<> 128:9bcdf88f62b0 378
<> 128:9bcdf88f62b0 379 /** @defgroup LCD_BlinkFrequency LCD Blink Frequency
<> 128:9bcdf88f62b0 380 * @{
<> 128:9bcdf88f62b0 381 */
<> 128:9bcdf88f62b0 382
<> 128:9bcdf88f62b0 383 #define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */
<> 128:9bcdf88f62b0 384 #define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
<> 128:9bcdf88f62b0 385 #define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
<> 128:9bcdf88f62b0 386 #define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
<> 128:9bcdf88f62b0 387 #define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */
<> 128:9bcdf88f62b0 388 #define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */
<> 128:9bcdf88f62b0 389 #define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */
<> 128:9bcdf88f62b0 390 #define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */
<> 128:9bcdf88f62b0 391
<> 128:9bcdf88f62b0 392 #define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \
<> 128:9bcdf88f62b0 393 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \
<> 128:9bcdf88f62b0 394 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \
<> 128:9bcdf88f62b0 395 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \
<> 128:9bcdf88f62b0 396 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
<> 128:9bcdf88f62b0 397 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
<> 128:9bcdf88f62b0 398 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
<> 128:9bcdf88f62b0 399 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
<> 128:9bcdf88f62b0 400 /**
<> 128:9bcdf88f62b0 401 * @}
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 /** @defgroup LCD_Contrast LCD Contrast
<> 128:9bcdf88f62b0 405 * @{
<> 128:9bcdf88f62b0 406 */
<> 128:9bcdf88f62b0 407
<> 128:9bcdf88f62b0 408 #define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */
<> 128:9bcdf88f62b0 409 #define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
<> 128:9bcdf88f62b0 410 #define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
<> 128:9bcdf88f62b0 411 #define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
<> 128:9bcdf88f62b0 412 #define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */
<> 128:9bcdf88f62b0 413 #define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V */
<> 128:9bcdf88f62b0 414 #define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V */
<> 128:9bcdf88f62b0 415 #define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.51V */
<> 128:9bcdf88f62b0 416
<> 128:9bcdf88f62b0 417 #define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
<> 128:9bcdf88f62b0 418 ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
<> 128:9bcdf88f62b0 419 ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
<> 128:9bcdf88f62b0 420 ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
<> 128:9bcdf88f62b0 421 ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
<> 128:9bcdf88f62b0 422 ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
<> 128:9bcdf88f62b0 423 ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
<> 128:9bcdf88f62b0 424 ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
<> 128:9bcdf88f62b0 425 /**
<> 128:9bcdf88f62b0 426 * @}
<> 128:9bcdf88f62b0 427 */
<> 128:9bcdf88f62b0 428
<> 128:9bcdf88f62b0 429 /** @defgroup LCD_MuxSegment LCD Mux Segment
<> 128:9bcdf88f62b0 430 * @{
<> 128:9bcdf88f62b0 431 */
<> 128:9bcdf88f62b0 432
<> 128:9bcdf88f62b0 433 #define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */
<> 128:9bcdf88f62b0 434 #define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 #define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
<> 128:9bcdf88f62b0 437 ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
<> 128:9bcdf88f62b0 438 /**
<> 128:9bcdf88f62b0 439 * @}
<> 128:9bcdf88f62b0 440 */
<> 128:9bcdf88f62b0 441
<> 128:9bcdf88f62b0 442 /** @defgroup LCD_Flag LCD Flag
<> 128:9bcdf88f62b0 443 * @{
<> 128:9bcdf88f62b0 444 */
<> 128:9bcdf88f62b0 445
<> 128:9bcdf88f62b0 446 #define LCD_FLAG_ENS LCD_SR_ENS
<> 128:9bcdf88f62b0 447 #define LCD_FLAG_SOF LCD_SR_SOF
<> 128:9bcdf88f62b0 448 #define LCD_FLAG_UDR LCD_SR_UDR
<> 128:9bcdf88f62b0 449 #define LCD_FLAG_UDD LCD_SR_UDD
<> 128:9bcdf88f62b0 450 #define LCD_FLAG_RDY LCD_SR_RDY
<> 128:9bcdf88f62b0 451 #define LCD_FLAG_FCRSF LCD_SR_FCRSR
<> 128:9bcdf88f62b0 452
<> 128:9bcdf88f62b0 453 /**
<> 128:9bcdf88f62b0 454 * @}
<> 128:9bcdf88f62b0 455 */
<> 128:9bcdf88f62b0 456
<> 128:9bcdf88f62b0 457 /** @defgroup LCD_RAMRegister LCD RAMRegister
<> 128:9bcdf88f62b0 458 * @{
<> 128:9bcdf88f62b0 459 */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 #define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */
<> 128:9bcdf88f62b0 462 #define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */
<> 128:9bcdf88f62b0 463 #define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */
<> 128:9bcdf88f62b0 464 #define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */
<> 128:9bcdf88f62b0 465 #define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */
<> 128:9bcdf88f62b0 466 #define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */
<> 128:9bcdf88f62b0 467 #define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */
<> 128:9bcdf88f62b0 468 #define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */
<> 128:9bcdf88f62b0 469 #define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */
<> 128:9bcdf88f62b0 470 #define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */
<> 128:9bcdf88f62b0 471 #define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
<> 128:9bcdf88f62b0 472 #define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
<> 128:9bcdf88f62b0 473 #define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
<> 128:9bcdf88f62b0 474 #define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
<> 128:9bcdf88f62b0 475 #define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
<> 128:9bcdf88f62b0 476 #define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
<> 128:9bcdf88f62b0 477
<> 128:9bcdf88f62b0 478 #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
<> 128:9bcdf88f62b0 479 ((__REGISTER__) == LCD_RAM_REGISTER1) || \
<> 128:9bcdf88f62b0 480 ((__REGISTER__) == LCD_RAM_REGISTER2) || \
<> 128:9bcdf88f62b0 481 ((__REGISTER__) == LCD_RAM_REGISTER3) || \
<> 128:9bcdf88f62b0 482 ((__REGISTER__) == LCD_RAM_REGISTER4) || \
<> 128:9bcdf88f62b0 483 ((__REGISTER__) == LCD_RAM_REGISTER5) || \
<> 128:9bcdf88f62b0 484 ((__REGISTER__) == LCD_RAM_REGISTER6) || \
<> 128:9bcdf88f62b0 485 ((__REGISTER__) == LCD_RAM_REGISTER7) || \
<> 128:9bcdf88f62b0 486 ((__REGISTER__) == LCD_RAM_REGISTER8) || \
<> 128:9bcdf88f62b0 487 ((__REGISTER__) == LCD_RAM_REGISTER9) || \
<> 128:9bcdf88f62b0 488 ((__REGISTER__) == LCD_RAM_REGISTER10) || \
<> 128:9bcdf88f62b0 489 ((__REGISTER__) == LCD_RAM_REGISTER11) || \
<> 128:9bcdf88f62b0 490 ((__REGISTER__) == LCD_RAM_REGISTER12) || \
<> 128:9bcdf88f62b0 491 ((__REGISTER__) == LCD_RAM_REGISTER13) || \
<> 128:9bcdf88f62b0 492 ((__REGISTER__) == LCD_RAM_REGISTER14) || \
<> 128:9bcdf88f62b0 493 ((__REGISTER__) == LCD_RAM_REGISTER15))
<> 128:9bcdf88f62b0 494
<> 128:9bcdf88f62b0 495 /**
<> 128:9bcdf88f62b0 496 * @}
<> 128:9bcdf88f62b0 497 */
<> 128:9bcdf88f62b0 498
<> 128:9bcdf88f62b0 499 /**
<> 128:9bcdf88f62b0 500 * @}
<> 128:9bcdf88f62b0 501 */
<> 128:9bcdf88f62b0 502
<> 128:9bcdf88f62b0 503 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 504
<> 128:9bcdf88f62b0 505 /** @defgroup LCD_Exported_Macros LCD Exported Macros
<> 128:9bcdf88f62b0 506 * @{
<> 128:9bcdf88f62b0 507 */
<> 128:9bcdf88f62b0 508
<> 128:9bcdf88f62b0 509 /** @brief Reset LCD handle state
<> 128:9bcdf88f62b0 510 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 511 * @retval None
<> 128:9bcdf88f62b0 512 */
<> 128:9bcdf88f62b0 513 #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
<> 128:9bcdf88f62b0 514
<> 128:9bcdf88f62b0 515 /** @brief macros to enables or disables the LCD
<> 128:9bcdf88f62b0 516 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 517 * @retval None
<> 128:9bcdf88f62b0 518 */
<> 128:9bcdf88f62b0 519 #define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
<> 128:9bcdf88f62b0 520 #define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
<> 128:9bcdf88f62b0 521
<> 128:9bcdf88f62b0 522 /** @brief Macros to enable or disable the low resistance divider. Displays with high
<> 128:9bcdf88f62b0 523 * internal resistance may need a longer drive time to achieve
<> 128:9bcdf88f62b0 524 * satisfactory contrast. This function is useful in this case if some
<> 128:9bcdf88f62b0 525 * additional power consumption can be tolerated.
<> 128:9bcdf88f62b0 526 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 527 * @note When this mode is enabled, the PulseOn Duration (PON) have to be
<> 128:9bcdf88f62b0 528 * programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
<> 128:9bcdf88f62b0 529 * @retval None
<> 128:9bcdf88f62b0 530 */
<> 128:9bcdf88f62b0 531 #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 532 do{ \
<> 128:9bcdf88f62b0 533 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
<> 128:9bcdf88f62b0 534 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 535 }while(0)
<> 128:9bcdf88f62b0 536
<> 128:9bcdf88f62b0 537 #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 538 do{ \
<> 128:9bcdf88f62b0 539 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
<> 128:9bcdf88f62b0 540 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 541 }while(0)
<> 128:9bcdf88f62b0 542
<> 128:9bcdf88f62b0 543 /**
<> 128:9bcdf88f62b0 544 * @brief Macro to configure the LCD pulses on duration.
<> 128:9bcdf88f62b0 545 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 546 * @param __DURATION__: specifies the LCD pulse on duration in terms of
<> 128:9bcdf88f62b0 547 * CK_PS (prescaled LCD clock period) pulses.
<> 128:9bcdf88f62b0 548 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 549 * @arg LCD_PULSEONDURATION_0: 0 pulse
<> 128:9bcdf88f62b0 550 * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
<> 128:9bcdf88f62b0 551 * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
<> 128:9bcdf88f62b0 552 * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
<> 128:9bcdf88f62b0 553 * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
<> 128:9bcdf88f62b0 554 * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
<> 128:9bcdf88f62b0 555 * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
<> 128:9bcdf88f62b0 556 * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
<> 128:9bcdf88f62b0 557 * @retval None
<> 128:9bcdf88f62b0 558 */
<> 128:9bcdf88f62b0 559 #define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \
<> 128:9bcdf88f62b0 560 do{ \
<> 128:9bcdf88f62b0 561 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
<> 128:9bcdf88f62b0 562 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 563 }while(0)
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /**
<> 128:9bcdf88f62b0 566 * @brief Macro to configure the LCD dead time.
<> 128:9bcdf88f62b0 567 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 568 * @param __DEADTIME__: specifies the LCD dead time.
<> 128:9bcdf88f62b0 569 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 570 * @arg LCD_DEADTIME_0: No dead Time
<> 128:9bcdf88f62b0 571 * @arg LCD_DEADTIME_1: One Phase between different couple of Frame
<> 128:9bcdf88f62b0 572 * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
<> 128:9bcdf88f62b0 573 * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
<> 128:9bcdf88f62b0 574 * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
<> 128:9bcdf88f62b0 575 * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
<> 128:9bcdf88f62b0 576 * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
<> 128:9bcdf88f62b0 577 * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
<> 128:9bcdf88f62b0 578 * @retval None
<> 128:9bcdf88f62b0 579 */
<> 128:9bcdf88f62b0 580 #define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \
<> 128:9bcdf88f62b0 581 do{ \
<> 128:9bcdf88f62b0 582 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
<> 128:9bcdf88f62b0 583 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 584 }while(0)
<> 128:9bcdf88f62b0 585
<> 128:9bcdf88f62b0 586 /**
<> 128:9bcdf88f62b0 587 * @brief Macro to configure the LCD Contrast.
<> 128:9bcdf88f62b0 588 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 589 * @param __CONTRAST__: specifies the LCD Contrast.
<> 128:9bcdf88f62b0 590 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 591 * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
<> 128:9bcdf88f62b0 592 * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
<> 128:9bcdf88f62b0 593 * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
<> 128:9bcdf88f62b0 594 * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
<> 128:9bcdf88f62b0 595 * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
<> 128:9bcdf88f62b0 596 * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
<> 128:9bcdf88f62b0 597 * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
<> 128:9bcdf88f62b0 598 * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
<> 128:9bcdf88f62b0 599 * @retval None
<> 128:9bcdf88f62b0 600 */
<> 128:9bcdf88f62b0 601 #define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \
<> 128:9bcdf88f62b0 602 do{ \
<> 128:9bcdf88f62b0 603 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
<> 128:9bcdf88f62b0 604 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 605 } while(0)
<> 128:9bcdf88f62b0 606
<> 128:9bcdf88f62b0 607 /**
<> 128:9bcdf88f62b0 608 * @brief Macro to configure the LCD Blink mode and Blink frequency.
<> 128:9bcdf88f62b0 609 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 610 * @param __BLINKMODE__: specifies the LCD blink mode.
<> 128:9bcdf88f62b0 611 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 612 * @arg LCD_BLINKMODE_OFF: Blink disabled
<> 128:9bcdf88f62b0 613 * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
<> 128:9bcdf88f62b0 614 * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8
<> 128:9bcdf88f62b0 615 * pixels according to the programmed duty)
<> 128:9bcdf88f62b0 616 * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
<> 128:9bcdf88f62b0 617 * (all pixels)
<> 128:9bcdf88f62b0 618 * @param __BLINKFREQUENCY__: specifies the LCD blink frequency.
<> 128:9bcdf88f62b0 619 * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
<> 128:9bcdf88f62b0 620 * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
<> 128:9bcdf88f62b0 621 * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
<> 128:9bcdf88f62b0 622 * @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
<> 128:9bcdf88f62b0 623 * @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
<> 128:9bcdf88f62b0 624 * @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
<> 128:9bcdf88f62b0 625 * @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
<> 128:9bcdf88f62b0 626 * @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
<> 128:9bcdf88f62b0 627 * @retval None
<> 128:9bcdf88f62b0 628 */
<> 128:9bcdf88f62b0 629 #define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \
<> 128:9bcdf88f62b0 630 do{ \
<> 128:9bcdf88f62b0 631 MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
<> 128:9bcdf88f62b0 632 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 633 }while(0)
<> 128:9bcdf88f62b0 634
<> 128:9bcdf88f62b0 635 /** @brief Enables or disables the specified LCD interrupt.
<> 128:9bcdf88f62b0 636 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 637 * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled.
<> 128:9bcdf88f62b0 638 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 639 * @arg LCD_IT_SOF: Start of Frame Interrupt
<> 128:9bcdf88f62b0 640 * @arg LCD_IT_UDD: Update Display Done Interrupt
<> 128:9bcdf88f62b0 641 * @retval None
<> 128:9bcdf88f62b0 642 */
<> 128:9bcdf88f62b0 643 #define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 128:9bcdf88f62b0 644 do{ \
<> 128:9bcdf88f62b0 645 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
<> 128:9bcdf88f62b0 646 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 647 }while(0)
<> 128:9bcdf88f62b0 648 #define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 128:9bcdf88f62b0 649 do{ \
<> 128:9bcdf88f62b0 650 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
<> 128:9bcdf88f62b0 651 LCD_WaitForSynchro(__HANDLE__); \
<> 128:9bcdf88f62b0 652 }while(0)
<> 128:9bcdf88f62b0 653
<> 128:9bcdf88f62b0 654 /** @brief Checks whether the specified LCD interrupt is enabled or not.
<> 128:9bcdf88f62b0 655 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 656 * @param __IT__: specifies the LCD interrupt source to check.
<> 128:9bcdf88f62b0 657 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 658 * @arg LCD_IT_SOF: Start of Frame Interrupt
<> 128:9bcdf88f62b0 659 * @arg LCD_IT_UDD: Update Display Done Interrupt.
<> 128:9bcdf88f62b0 660 * @note If the device is in STOP mode (PCLK not provided) UDD will not
<> 128:9bcdf88f62b0 661 * generate an interrupt even if UDDIE = 1.
<> 128:9bcdf88f62b0 662 * If the display is not enabled the UDD interrupt will never occur.
<> 128:9bcdf88f62b0 663 * @retval The state of __IT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 664 */
<> 128:9bcdf88f62b0 665 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
<> 128:9bcdf88f62b0 666
<> 128:9bcdf88f62b0 667 /** @brief Checks whether the specified LCD flag is set or not.
<> 128:9bcdf88f62b0 668 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 669 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 670 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 671 * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
<> 128:9bcdf88f62b0 672 * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
<> 128:9bcdf88f62b0 673 * goes from 0 to 1. On deactivation it reflects the real status of
<> 128:9bcdf88f62b0 674 * LCD so it becomes 0 at the end of the last displayed frame.
<> 128:9bcdf88f62b0 675 * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
<> 128:9bcdf88f62b0 676 * the beginning of a new frame, at the same time as the display data is
<> 128:9bcdf88f62b0 677 * updated.
<> 128:9bcdf88f62b0 678 * @arg LCD_FLAG_UDR: Update Display Request flag.
<> 128:9bcdf88f62b0 679 * @arg LCD_FLAG_UDD: Update Display Done flag.
<> 128:9bcdf88f62b0 680 * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
<> 128:9bcdf88f62b0 681 * of the step-up converter.
<> 128:9bcdf88f62b0 682 * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
<> 128:9bcdf88f62b0 683 * This flag is set by hardware each time the LCD_FCR register is updated
<> 128:9bcdf88f62b0 684 * in the LCDCLK domain.
<> 128:9bcdf88f62b0 685 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 686 */
<> 128:9bcdf88f62b0 687 #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 688
<> 128:9bcdf88f62b0 689 /** @brief Clears the specified LCD pending flag.
<> 128:9bcdf88f62b0 690 * @param __HANDLE__: specifies the LCD Handle.
<> 128:9bcdf88f62b0 691 * @param __FLAG__: specifies the flag to clear.
<> 128:9bcdf88f62b0 692 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 693 * @arg LCD_FLAG_SOF: Start of Frame Interrupt
<> 128:9bcdf88f62b0 694 * @arg LCD_FLAG_UDD: Update Display Done Interrupt
<> 128:9bcdf88f62b0 695 * @retval None
<> 128:9bcdf88f62b0 696 */
<> 128:9bcdf88f62b0 697 #define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__))
<> 128:9bcdf88f62b0 698
<> 128:9bcdf88f62b0 699 /**
<> 128:9bcdf88f62b0 700 * @}
<> 128:9bcdf88f62b0 701 */
<> 128:9bcdf88f62b0 702
<> 128:9bcdf88f62b0 703 /* Exported functions ------------------------------------------------------- */
<> 128:9bcdf88f62b0 704
<> 128:9bcdf88f62b0 705 /** @addtogroup LCD_Exported_Functions
<> 128:9bcdf88f62b0 706 * @{
<> 128:9bcdf88f62b0 707 */
<> 128:9bcdf88f62b0 708
<> 128:9bcdf88f62b0 709 /** @addtogroup LCD_Exported_Functions_Group1
<> 128:9bcdf88f62b0 710 * @{
<> 128:9bcdf88f62b0 711 */
<> 128:9bcdf88f62b0 712
<> 128:9bcdf88f62b0 713 /* Initialization/de-initialization methods **********************************/
<> 128:9bcdf88f62b0 714 HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 715 HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 716 void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 717 void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 718
<> 128:9bcdf88f62b0 719 /**
<> 128:9bcdf88f62b0 720 * @}
<> 128:9bcdf88f62b0 721 */
<> 128:9bcdf88f62b0 722
<> 128:9bcdf88f62b0 723 /** @addtogroup LCD_Exported_Functions_Group2
<> 128:9bcdf88f62b0 724 * @{
<> 128:9bcdf88f62b0 725 */
<> 128:9bcdf88f62b0 726
<> 128:9bcdf88f62b0 727 /* IO operation methods *******************************************************/
<> 128:9bcdf88f62b0 728 HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
<> 128:9bcdf88f62b0 729 HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 730 HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 731
<> 128:9bcdf88f62b0 732 /**
<> 128:9bcdf88f62b0 733 * @}
<> 128:9bcdf88f62b0 734 */
<> 128:9bcdf88f62b0 735
<> 128:9bcdf88f62b0 736 /** @addtogroup LCD_Exported_Functions_Group3
<> 128:9bcdf88f62b0 737 * @{
<> 128:9bcdf88f62b0 738 */
<> 128:9bcdf88f62b0 739
<> 128:9bcdf88f62b0 740 /* Peripheral State methods **************************************************/
<> 128:9bcdf88f62b0 741 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 742 uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 743
<> 128:9bcdf88f62b0 744 /**
<> 128:9bcdf88f62b0 745 * @}
<> 128:9bcdf88f62b0 746 */
<> 128:9bcdf88f62b0 747
<> 128:9bcdf88f62b0 748 /**
<> 128:9bcdf88f62b0 749 * @}
<> 128:9bcdf88f62b0 750 */
<> 128:9bcdf88f62b0 751
<> 128:9bcdf88f62b0 752 /** @addtogroup LCD_Private_Functions
<> 128:9bcdf88f62b0 753 * @{
<> 128:9bcdf88f62b0 754 */
<> 128:9bcdf88f62b0 755
<> 128:9bcdf88f62b0 756 /* Private functions ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 757 HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
<> 128:9bcdf88f62b0 758
<> 128:9bcdf88f62b0 759 /**
<> 128:9bcdf88f62b0 760 * @}
<> 128:9bcdf88f62b0 761 */
<> 128:9bcdf88f62b0 762
<> 128:9bcdf88f62b0 763 /**
<> 128:9bcdf88f62b0 764 * @}
<> 128:9bcdf88f62b0 765 */
<> 128:9bcdf88f62b0 766
<> 128:9bcdf88f62b0 767 #endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 768
<> 128:9bcdf88f62b0 769 /**
<> 128:9bcdf88f62b0 770 * @}
<> 128:9bcdf88f62b0 771 */
<> 128:9bcdf88f62b0 772
<> 128:9bcdf88f62b0 773 #ifdef __cplusplus
<> 128:9bcdf88f62b0 774 }
<> 128:9bcdf88f62b0 775 #endif
<> 128:9bcdf88f62b0 776
<> 128:9bcdf88f62b0 777 #endif /* __STM32L1xx_HAL_LCD_H */
<> 128:9bcdf88f62b0 778
<> 128:9bcdf88f62b0 779 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/