mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_i2s.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of I2S HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_I2S_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_I2S_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 #if defined(STM32L100xC) || \
<> 128:9bcdf88f62b0 47 defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || defined(STM32L151xDX) || \
<> 128:9bcdf88f62b0 48 defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L151xE) || defined(STM32L151xDX) || \
<> 128:9bcdf88f62b0 49 defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 52 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 55 * @{
<> 128:9bcdf88f62b0 56 */
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 /** @addtogroup I2S
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 63 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 128:9bcdf88f62b0 64 * @{
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 /**
<> 128:9bcdf88f62b0 68 * @brief I2S Init structure definition
<> 128:9bcdf88f62b0 69 */
<> 128:9bcdf88f62b0 70 typedef struct
<> 128:9bcdf88f62b0 71 {
<> 128:9bcdf88f62b0 72 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 128:9bcdf88f62b0 73 This parameter can be a value of @ref I2S_Mode */
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 128:9bcdf88f62b0 76 This parameter can be a value of @ref I2S_Standard */
<> 128:9bcdf88f62b0 77
<> 128:9bcdf88f62b0 78 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 128:9bcdf88f62b0 79 This parameter can be a value of @ref I2S_Data_Format */
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 128:9bcdf88f62b0 82 This parameter can be a value of @ref I2S_MCLK_Output */
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 128:9bcdf88f62b0 85 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 128:9bcdf88f62b0 88 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 }I2S_InitTypeDef;
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 /**
<> 128:9bcdf88f62b0 93 * @brief HAL State structures definition
<> 128:9bcdf88f62b0 94 */
<> 128:9bcdf88f62b0 95 typedef enum
<> 128:9bcdf88f62b0 96 {
<> 128:9bcdf88f62b0 97 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
<> 128:9bcdf88f62b0 98 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
<> 128:9bcdf88f62b0 99 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
<> 128:9bcdf88f62b0 100 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 128:9bcdf88f62b0 101 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 128:9bcdf88f62b0 102 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S pause state: used in case of DMA */
<> 128:9bcdf88f62b0 103 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
<> 128:9bcdf88f62b0 104 }HAL_I2S_StateTypeDef;
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 /**
<> 128:9bcdf88f62b0 107 * @brief I2S handle Structure definition
<> 128:9bcdf88f62b0 108 */
<> 128:9bcdf88f62b0 109 typedef struct
<> 128:9bcdf88f62b0 110 {
<> 128:9bcdf88f62b0 111 SPI_TypeDef *Instance; /* I2S registers base address */
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 I2S_InitTypeDef Init; /* I2S communication parameters */
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
<> 128:9bcdf88f62b0 116
<> 128:9bcdf88f62b0 117 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 __IO uint16_t RxXferCount; /* I2S Rx transfer counter
<> 128:9bcdf88f62b0 126 (This field is initialized at the
<> 128:9bcdf88f62b0 127 same value as transfer size at the
<> 128:9bcdf88f62b0 128 beginning of the transfer and
<> 128:9bcdf88f62b0 129 decremented when a sample is received.
<> 128:9bcdf88f62b0 130 NbSamplesReceived = RxBufferSize-RxBufferCount) */
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 __IO HAL_LockTypeDef Lock; /* I2S locking object */
<> 128:9bcdf88f62b0 137
<> 128:9bcdf88f62b0 138 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 __IO uint32_t ErrorCode; /* I2S Error code */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 }I2S_HandleTypeDef;
<> 128:9bcdf88f62b0 143 /**
<> 128:9bcdf88f62b0 144 * @}
<> 128:9bcdf88f62b0 145 */
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 148 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 128:9bcdf88f62b0 149 * @{
<> 128:9bcdf88f62b0 150 */
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /** @defgroup I2S_Error_Codes I2S Error Codes
<> 128:9bcdf88f62b0 153 * @{
<> 128:9bcdf88f62b0 154 */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 #define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 128:9bcdf88f62b0 157 #define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */
<> 128:9bcdf88f62b0 158 #define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */
<> 128:9bcdf88f62b0 159 #define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */
<> 128:9bcdf88f62b0 160 #define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /**
<> 128:9bcdf88f62b0 163 * @}
<> 128:9bcdf88f62b0 164 */
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 /** @defgroup I2S_Mode I2S Mode
<> 128:9bcdf88f62b0 167 * @{
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169 #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 170 #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
<> 128:9bcdf88f62b0 171 #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
<> 128:9bcdf88f62b0 172 #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 128:9bcdf88f62b0 175 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 128:9bcdf88f62b0 176 ((MODE) == I2S_MODE_MASTER_TX) || \
<> 128:9bcdf88f62b0 177 ((MODE) == I2S_MODE_MASTER_RX))
<> 128:9bcdf88f62b0 178 /**
<> 128:9bcdf88f62b0 179 * @}
<> 128:9bcdf88f62b0 180 */
<> 128:9bcdf88f62b0 181
<> 128:9bcdf88f62b0 182 /** @defgroup I2S_Standard I2S Standard
<> 128:9bcdf88f62b0 183 * @{
<> 128:9bcdf88f62b0 184 */
<> 128:9bcdf88f62b0 185 #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 186 #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
<> 128:9bcdf88f62b0 187 #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
<> 128:9bcdf88f62b0 188 #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 128:9bcdf88f62b0 189 SPI_I2SCFGR_I2SSTD_1))
<> 128:9bcdf88f62b0 190 #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 128:9bcdf88f62b0 191 SPI_I2SCFGR_I2SSTD_1 |\
<> 128:9bcdf88f62b0 192 SPI_I2SCFGR_PCMSYNC))
<> 128:9bcdf88f62b0 193
<> 128:9bcdf88f62b0 194 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 128:9bcdf88f62b0 195 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 128:9bcdf88f62b0 196 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 128:9bcdf88f62b0 197 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 128:9bcdf88f62b0 198 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 128:9bcdf88f62b0 199
<> 128:9bcdf88f62b0 200 /**
<> 128:9bcdf88f62b0 201 * @}
<> 128:9bcdf88f62b0 202 */
<> 128:9bcdf88f62b0 203
<> 128:9bcdf88f62b0 204 /** @defgroup I2S_Data_Format I2S Data Format
<> 128:9bcdf88f62b0 205 * @{
<> 128:9bcdf88f62b0 206 */
<> 128:9bcdf88f62b0 207 #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 208 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
<> 128:9bcdf88f62b0 209 #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
<> 128:9bcdf88f62b0 210 #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
<> 128:9bcdf88f62b0 211
<> 128:9bcdf88f62b0 212 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 128:9bcdf88f62b0 213 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 128:9bcdf88f62b0 214 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 128:9bcdf88f62b0 215 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 128:9bcdf88f62b0 216 /**
<> 128:9bcdf88f62b0 217 * @}
<> 128:9bcdf88f62b0 218 */
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220 /** @defgroup I2S_MCLK_Output I2S MCLK Output
<> 128:9bcdf88f62b0 221 * @{
<> 128:9bcdf88f62b0 222 */
<> 128:9bcdf88f62b0 223 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
<> 128:9bcdf88f62b0 224 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 128:9bcdf88f62b0 227 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
<> 128:9bcdf88f62b0 228 /**
<> 128:9bcdf88f62b0 229 * @}
<> 128:9bcdf88f62b0 230 */
<> 128:9bcdf88f62b0 231
<> 128:9bcdf88f62b0 232 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 128:9bcdf88f62b0 233 * @{
<> 128:9bcdf88f62b0 234 */
<> 128:9bcdf88f62b0 235 #define I2S_AUDIOFREQ_192K ((uint32_t)192000)
<> 128:9bcdf88f62b0 236 #define I2S_AUDIOFREQ_96K ((uint32_t)96000)
<> 128:9bcdf88f62b0 237 #define I2S_AUDIOFREQ_48K ((uint32_t)48000)
<> 128:9bcdf88f62b0 238 #define I2S_AUDIOFREQ_44K ((uint32_t)44100)
<> 128:9bcdf88f62b0 239 #define I2S_AUDIOFREQ_32K ((uint32_t)32000)
<> 128:9bcdf88f62b0 240 #define I2S_AUDIOFREQ_22K ((uint32_t)22050)
<> 128:9bcdf88f62b0 241 #define I2S_AUDIOFREQ_16K ((uint32_t)16000)
<> 128:9bcdf88f62b0 242 #define I2S_AUDIOFREQ_11K ((uint32_t)11025)
<> 128:9bcdf88f62b0 243 #define I2S_AUDIOFREQ_8K ((uint32_t)8000)
<> 128:9bcdf88f62b0 244 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 128:9bcdf88f62b0 247 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 128:9bcdf88f62b0 248 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 128:9bcdf88f62b0 249 /**
<> 128:9bcdf88f62b0 250 * @}
<> 128:9bcdf88f62b0 251 */
<> 128:9bcdf88f62b0 252
<> 128:9bcdf88f62b0 253 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 128:9bcdf88f62b0 254 * @{
<> 128:9bcdf88f62b0 255 */
<> 128:9bcdf88f62b0 256 #define I2S_CPOL_LOW ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 257 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 128:9bcdf88f62b0 258
<> 128:9bcdf88f62b0 259 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 128:9bcdf88f62b0 260 ((CPOL) == I2S_CPOL_HIGH))
<> 128:9bcdf88f62b0 261 /**
<> 128:9bcdf88f62b0 262 * @}
<> 128:9bcdf88f62b0 263 */
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
<> 128:9bcdf88f62b0 266 * @{
<> 128:9bcdf88f62b0 267 */
<> 128:9bcdf88f62b0 268 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 128:9bcdf88f62b0 269 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 128:9bcdf88f62b0 270 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 128:9bcdf88f62b0 271 /**
<> 128:9bcdf88f62b0 272 * @}
<> 128:9bcdf88f62b0 273 */
<> 128:9bcdf88f62b0 274
<> 128:9bcdf88f62b0 275 /** @defgroup I2S_Flag_definition I2S Flag definition
<> 128:9bcdf88f62b0 276 * @{
<> 128:9bcdf88f62b0 277 */
<> 128:9bcdf88f62b0 278 #define I2S_FLAG_TXE SPI_SR_TXE
<> 128:9bcdf88f62b0 279 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 128:9bcdf88f62b0 280
<> 128:9bcdf88f62b0 281 #define I2S_FLAG_UDR SPI_SR_UDR
<> 128:9bcdf88f62b0 282 #define I2S_FLAG_OVR SPI_SR_OVR
<> 128:9bcdf88f62b0 283 #define I2S_FLAG_FRE SPI_SR_FRE
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 128:9bcdf88f62b0 286 #define I2S_FLAG_BSY SPI_SR_BSY
<> 128:9bcdf88f62b0 287 /**
<> 128:9bcdf88f62b0 288 * @}
<> 128:9bcdf88f62b0 289 */
<> 128:9bcdf88f62b0 290
<> 128:9bcdf88f62b0 291 /**
<> 128:9bcdf88f62b0 292 * @}
<> 128:9bcdf88f62b0 293 */
<> 128:9bcdf88f62b0 294
<> 128:9bcdf88f62b0 295 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 296 /** @defgroup I2S_Exported_macros I2S Exported Macros
<> 128:9bcdf88f62b0 297 * @{
<> 128:9bcdf88f62b0 298 */
<> 128:9bcdf88f62b0 299
<> 128:9bcdf88f62b0 300 /** @brief Reset I2S handle state
<> 128:9bcdf88f62b0 301 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 302 * @retval None
<> 128:9bcdf88f62b0 303 */
<> 128:9bcdf88f62b0 304 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 128:9bcdf88f62b0 305
<> 128:9bcdf88f62b0 306 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
<> 128:9bcdf88f62b0 307 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 308 * @retval None
<> 128:9bcdf88f62b0 309 */
<> 128:9bcdf88f62b0 310 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 128:9bcdf88f62b0 311 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /** @brief Enable or disable the specified I2S interrupts.
<> 128:9bcdf88f62b0 314 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 315 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 128:9bcdf88f62b0 316 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 317 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 128:9bcdf88f62b0 318 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 128:9bcdf88f62b0 319 * @arg I2S_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 320 * @retval None
<> 128:9bcdf88f62b0 321 */
<> 128:9bcdf88f62b0 322 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 128:9bcdf88f62b0 323 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
<> 128:9bcdf88f62b0 326 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 327 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
<> 128:9bcdf88f62b0 328 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
<> 128:9bcdf88f62b0 329 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 330 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 128:9bcdf88f62b0 331 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 128:9bcdf88f62b0 332 * @arg I2S_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 333 * @retval The new state of __IT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 334 */
<> 128:9bcdf88f62b0 335 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 128:9bcdf88f62b0 336
<> 128:9bcdf88f62b0 337 /** @brief Checks whether the specified I2S flag is set or not.
<> 128:9bcdf88f62b0 338 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 339 * @param __FLAG__: specifies the flag to check.
<> 128:9bcdf88f62b0 340 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 341 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 128:9bcdf88f62b0 342 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 128:9bcdf88f62b0 343 * @arg I2S_FLAG_UDR: Underrun flag
<> 128:9bcdf88f62b0 344 * @arg I2S_FLAG_OVR: Overrun flag
<> 128:9bcdf88f62b0 345 * @arg I2S_FLAG_FRE: Frame error flag
<> 128:9bcdf88f62b0 346 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 128:9bcdf88f62b0 347 * @arg I2S_FLAG_BSY: Busy flag
<> 128:9bcdf88f62b0 348 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 349 */
<> 128:9bcdf88f62b0 350 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 351
<> 128:9bcdf88f62b0 352 /** @brief Clears the I2S OVR pending flag.
<> 128:9bcdf88f62b0 353 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 354 * @retval None
<> 128:9bcdf88f62b0 355 */
<> 128:9bcdf88f62b0 356 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
<> 128:9bcdf88f62b0 357 tmpreg = (__HANDLE__)->Instance->SR;\
<> 128:9bcdf88f62b0 358 UNUSED(tmpreg); \
<> 128:9bcdf88f62b0 359 }while(0)
<> 128:9bcdf88f62b0 360 /** @brief Clears the I2S UDR pending flag.
<> 128:9bcdf88f62b0 361 * @param __HANDLE__: specifies the I2S Handle.
<> 128:9bcdf88f62b0 362 * @retval None
<> 128:9bcdf88f62b0 363 */
<> 128:9bcdf88f62b0 364 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
<> 128:9bcdf88f62b0 365 /**
<> 128:9bcdf88f62b0 366 * @}
<> 128:9bcdf88f62b0 367 */
<> 128:9bcdf88f62b0 368
<> 128:9bcdf88f62b0 369 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 370 /** @addtogroup I2S_Exported_Functions
<> 128:9bcdf88f62b0 371 * @{
<> 128:9bcdf88f62b0 372 */
<> 128:9bcdf88f62b0 373
<> 128:9bcdf88f62b0 374 /** @addtogroup I2S_Exported_Functions_Group1
<> 128:9bcdf88f62b0 375 * @{
<> 128:9bcdf88f62b0 376 */
<> 128:9bcdf88f62b0 377 /* Initialization/de-initialization functions ********************************/
<> 128:9bcdf88f62b0 378 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 379 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 380 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 381 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 382 /**
<> 128:9bcdf88f62b0 383 * @}
<> 128:9bcdf88f62b0 384 */
<> 128:9bcdf88f62b0 385
<> 128:9bcdf88f62b0 386 /** @addtogroup I2S_Exported_Functions_Group2
<> 128:9bcdf88f62b0 387 * @{
<> 128:9bcdf88f62b0 388 */
<> 128:9bcdf88f62b0 389 /* I/O operation functions ***************************************************/
<> 128:9bcdf88f62b0 390 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 391 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 392 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 393
<> 128:9bcdf88f62b0 394 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 395 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 396 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 397 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 398
<> 128:9bcdf88f62b0 399 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 400 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 401 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 402
<> 128:9bcdf88f62b0 403 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 404 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 405 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 406
<> 128:9bcdf88f62b0 407 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 128:9bcdf88f62b0 408 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 409 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 410 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 411 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 412 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 413 /**
<> 128:9bcdf88f62b0 414 * @}
<> 128:9bcdf88f62b0 415 */
<> 128:9bcdf88f62b0 416
<> 128:9bcdf88f62b0 417 /** @addtogroup I2S_Exported_Functions_Group3
<> 128:9bcdf88f62b0 418 * @{
<> 128:9bcdf88f62b0 419 */
<> 128:9bcdf88f62b0 420 /* Peripheral Control and State functions ************************************/
<> 128:9bcdf88f62b0 421 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 422 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 128:9bcdf88f62b0 423 /**
<> 128:9bcdf88f62b0 424 * @}
<> 128:9bcdf88f62b0 425 */
<> 128:9bcdf88f62b0 426
<> 128:9bcdf88f62b0 427 /**
<> 128:9bcdf88f62b0 428 * @}
<> 128:9bcdf88f62b0 429 */
<> 128:9bcdf88f62b0 430
<> 128:9bcdf88f62b0 431
<> 128:9bcdf88f62b0 432 /**
<> 128:9bcdf88f62b0 433 * @}
<> 128:9bcdf88f62b0 434 */
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 /**
<> 128:9bcdf88f62b0 437 * @}
<> 128:9bcdf88f62b0 438 */
<> 128:9bcdf88f62b0 439 #endif /* STM32L100xC ||
<> 128:9bcdf88f62b0 440 STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE || STM32L151xDX ||\\
<> 128:9bcdf88f62b0 441 STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L152xDX || STM32L151xE || STM32L151xDX ||\\
<> 128:9bcdf88f62b0 442 STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 443
<> 128:9bcdf88f62b0 444 #ifdef __cplusplus
<> 128:9bcdf88f62b0 445 }
<> 128:9bcdf88f62b0 446 #endif
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 #endif /* __STM32L1xx_HAL_I2S_H */
<> 128:9bcdf88f62b0 449
<> 128:9bcdf88f62b0 450 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/