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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_i2c.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of I2C HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_I2C_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_I2C_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup I2C
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
<> 128:9bcdf88f62b0 63 * @brief I2C Configuration Structure definition
<> 128:9bcdf88f62b0 64 * @{
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66 typedef struct
<> 128:9bcdf88f62b0 67 {
<> 128:9bcdf88f62b0 68 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
<> 128:9bcdf88f62b0 69 This parameter must be set to a value lower than 400kHz */
<> 128:9bcdf88f62b0 70
<> 128:9bcdf88f62b0 71 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
<> 128:9bcdf88f62b0 72 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 128:9bcdf88f62b0 75 This parameter can be a 7-bit or 10-bit address. */
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 128:9bcdf88f62b0 78 This parameter can be a value of @ref I2C_addressing_mode */
<> 128:9bcdf88f62b0 79
<> 128:9bcdf88f62b0 80 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 128:9bcdf88f62b0 81 This parameter can be a value of @ref I2C_dual_addressing_mode */
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 128:9bcdf88f62b0 84 This parameter can be a 7-bit address. */
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 128:9bcdf88f62b0 87 This parameter can be a value of @ref I2C_general_call_addressing_mode */
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 128:9bcdf88f62b0 90 This parameter can be a value of @ref I2C_nostretch_mode */
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 }I2C_InitTypeDef;
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 /**
<> 128:9bcdf88f62b0 95 * @}
<> 128:9bcdf88f62b0 96 */
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /** @defgroup HAL_state_structure_definition HAL state structure definition
<> 128:9bcdf88f62b0 99 * @brief HAL State structure definition
<> 128:9bcdf88f62b0 100 * @note HAL I2C State value coding follow below described bitmap :
<> 128:9bcdf88f62b0 101 * b7-b6 Error information
<> 128:9bcdf88f62b0 102 * 00 : No Error
<> 128:9bcdf88f62b0 103 * 01 : Abort (Abort user request on going)
<> 128:9bcdf88f62b0 104 * 10 : Timeout
<> 128:9bcdf88f62b0 105 * 11 : Error
<> 128:9bcdf88f62b0 106 * b5 IP initilisation status
<> 128:9bcdf88f62b0 107 * 0 : Reset (IP not initialized)
<> 128:9bcdf88f62b0 108 * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
<> 128:9bcdf88f62b0 109 * b4 (not used)
<> 128:9bcdf88f62b0 110 * x : Should be set to 0
<> 128:9bcdf88f62b0 111 * b3
<> 128:9bcdf88f62b0 112 * 0 : Ready or Busy (No Listen mode ongoing)
<> 128:9bcdf88f62b0 113 * 1 : Listen (IP in Address Listen Mode)
<> 128:9bcdf88f62b0 114 * b2 Intrinsic process state
<> 128:9bcdf88f62b0 115 * 0 : Ready
<> 128:9bcdf88f62b0 116 * 1 : Busy (IP busy with some configuration or internal operations)
<> 128:9bcdf88f62b0 117 * b1 Rx state
<> 128:9bcdf88f62b0 118 * 0 : Ready (no Rx operation ongoing)
<> 128:9bcdf88f62b0 119 * 1 : Busy (Rx operation ongoing)
<> 128:9bcdf88f62b0 120 * b0 Tx state
<> 128:9bcdf88f62b0 121 * 0 : Ready (no Tx operation ongoing)
<> 128:9bcdf88f62b0 122 * 1 : Busy (Tx operation ongoing)
<> 128:9bcdf88f62b0 123 * @{
<> 128:9bcdf88f62b0 124 */
<> 128:9bcdf88f62b0 125 typedef enum
<> 128:9bcdf88f62b0 126 {
<> 128:9bcdf88f62b0 127 HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
<> 128:9bcdf88f62b0 128 HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
<> 128:9bcdf88f62b0 129 HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
<> 128:9bcdf88f62b0 130 HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
<> 128:9bcdf88f62b0 131 HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 128:9bcdf88f62b0 132 HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
<> 128:9bcdf88f62b0 133 HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
<> 128:9bcdf88f62b0 134 process is ongoing */
<> 128:9bcdf88f62b0 135 HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
<> 128:9bcdf88f62b0 136 process is ongoing */
<> 128:9bcdf88f62b0 137 HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
<> 128:9bcdf88f62b0 138 HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
<> 128:9bcdf88f62b0 139 HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 }HAL_I2C_StateTypeDef;
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 /**
<> 128:9bcdf88f62b0 144 * @}
<> 128:9bcdf88f62b0 145 */
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
<> 128:9bcdf88f62b0 148 * @brief HAL Mode structure definition
<> 128:9bcdf88f62b0 149 * @note HAL I2C Mode value coding follow below described bitmap :
<> 128:9bcdf88f62b0 150 * b7 (not used)
<> 128:9bcdf88f62b0 151 * x : Should be set to 0
<> 128:9bcdf88f62b0 152 * b6
<> 128:9bcdf88f62b0 153 * 0 : None
<> 128:9bcdf88f62b0 154 * 1 : Memory (HAL I2C communication is in Memory Mode)
<> 128:9bcdf88f62b0 155 * b5
<> 128:9bcdf88f62b0 156 * 0 : None
<> 128:9bcdf88f62b0 157 * 1 : Slave (HAL I2C communication is in Slave Mode)
<> 128:9bcdf88f62b0 158 * b4
<> 128:9bcdf88f62b0 159 * 0 : None
<> 128:9bcdf88f62b0 160 * 1 : Master (HAL I2C communication is in Master Mode)
<> 128:9bcdf88f62b0 161 * b3-b2-b1-b0 (not used)
<> 128:9bcdf88f62b0 162 * xxxx : Should be set to 0000
<> 128:9bcdf88f62b0 163 * @{
<> 128:9bcdf88f62b0 164 */
<> 128:9bcdf88f62b0 165 typedef enum
<> 128:9bcdf88f62b0 166 {
<> 128:9bcdf88f62b0 167 HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
<> 128:9bcdf88f62b0 168 HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
<> 128:9bcdf88f62b0 169 HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
<> 128:9bcdf88f62b0 170 HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
<> 128:9bcdf88f62b0 171
<> 128:9bcdf88f62b0 172 }HAL_I2C_ModeTypeDef;
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 /**
<> 128:9bcdf88f62b0 175 * @}
<> 128:9bcdf88f62b0 176 */
<> 128:9bcdf88f62b0 177
<> 128:9bcdf88f62b0 178 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
<> 128:9bcdf88f62b0 179 * @brief I2C Error Code definition
<> 128:9bcdf88f62b0 180 * @{
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182 #define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 128:9bcdf88f62b0 183 #define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
<> 128:9bcdf88f62b0 184 #define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
<> 128:9bcdf88f62b0 185 #define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
<> 128:9bcdf88f62b0 186 #define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
<> 128:9bcdf88f62b0 187 #define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
<> 128:9bcdf88f62b0 188 #define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
<> 128:9bcdf88f62b0 189 /**
<> 128:9bcdf88f62b0 190 * @}
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
<> 128:9bcdf88f62b0 194 * @brief I2C handle Structure definition
<> 128:9bcdf88f62b0 195 * @{
<> 128:9bcdf88f62b0 196 */
<> 128:9bcdf88f62b0 197 typedef struct
<> 128:9bcdf88f62b0 198 {
<> 128:9bcdf88f62b0 199 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 128:9bcdf88f62b0 202
<> 128:9bcdf88f62b0 203 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 128:9bcdf88f62b0 204
<> 128:9bcdf88f62b0 205 uint16_t XferSize; /*!< I2C transfer size */
<> 128:9bcdf88f62b0 206
<> 128:9bcdf88f62b0 207 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 __IO uint32_t XferOptions; /*!< I2C transfer options */
<> 128:9bcdf88f62b0 210
<> 128:9bcdf88f62b0 211 __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
<> 128:9bcdf88f62b0 212 context for internal usage */
<> 128:9bcdf88f62b0 213
<> 128:9bcdf88f62b0 214 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
<> 128:9bcdf88f62b0 223
<> 128:9bcdf88f62b0 224 __IO uint32_t ErrorCode; /*!< I2C Error code */
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 __IO uint32_t Devaddress; /*!< I2C Target device address */
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 __IO uint32_t Memaddress; /*!< I2C Target memory address */
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
<> 128:9bcdf88f62b0 231
<> 128:9bcdf88f62b0 232 __IO uint32_t EventCount; /*!< I2C Event counter */
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 }I2C_HandleTypeDef;
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 /**
<> 128:9bcdf88f62b0 237 * @}
<> 128:9bcdf88f62b0 238 */
<> 128:9bcdf88f62b0 239
<> 128:9bcdf88f62b0 240 /**
<> 128:9bcdf88f62b0 241 * @}
<> 128:9bcdf88f62b0 242 */
<> 128:9bcdf88f62b0 243 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 244 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 128:9bcdf88f62b0 245 * @{
<> 128:9bcdf88f62b0 246 */
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
<> 128:9bcdf88f62b0 249 * @{
<> 128:9bcdf88f62b0 250 */
<> 128:9bcdf88f62b0 251 #define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 252 #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
<> 128:9bcdf88f62b0 253 /**
<> 128:9bcdf88f62b0 254 * @}
<> 128:9bcdf88f62b0 255 */
<> 128:9bcdf88f62b0 256
<> 128:9bcdf88f62b0 257 /** @defgroup I2C_addressing_mode I2C addressing mode
<> 128:9bcdf88f62b0 258 * @{
<> 128:9bcdf88f62b0 259 */
<> 128:9bcdf88f62b0 260 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
<> 128:9bcdf88f62b0 261 #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
<> 128:9bcdf88f62b0 262 /**
<> 128:9bcdf88f62b0 263 * @}
<> 128:9bcdf88f62b0 264 */
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
<> 128:9bcdf88f62b0 267 * @{
<> 128:9bcdf88f62b0 268 */
<> 128:9bcdf88f62b0 269 #define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 270 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
<> 128:9bcdf88f62b0 271 /**
<> 128:9bcdf88f62b0 272 * @}
<> 128:9bcdf88f62b0 273 */
<> 128:9bcdf88f62b0 274
<> 128:9bcdf88f62b0 275 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
<> 128:9bcdf88f62b0 276 * @{
<> 128:9bcdf88f62b0 277 */
<> 128:9bcdf88f62b0 278 #define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 279 #define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
<> 128:9bcdf88f62b0 280 /**
<> 128:9bcdf88f62b0 281 * @}
<> 128:9bcdf88f62b0 282 */
<> 128:9bcdf88f62b0 283
<> 128:9bcdf88f62b0 284 /** @defgroup I2C_nostretch_mode I2C nostretch mode
<> 128:9bcdf88f62b0 285 * @{
<> 128:9bcdf88f62b0 286 */
<> 128:9bcdf88f62b0 287 #define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 288 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 128:9bcdf88f62b0 289 /**
<> 128:9bcdf88f62b0 290 * @}
<> 128:9bcdf88f62b0 291 */
<> 128:9bcdf88f62b0 292
<> 128:9bcdf88f62b0 293 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
<> 128:9bcdf88f62b0 294 * @{
<> 128:9bcdf88f62b0 295 */
<> 128:9bcdf88f62b0 296 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
<> 128:9bcdf88f62b0 297 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
<> 128:9bcdf88f62b0 298 /**
<> 128:9bcdf88f62b0 299 * @}
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition Master Point of View
<> 128:9bcdf88f62b0 303 * @{
<> 128:9bcdf88f62b0 304 */
<> 128:9bcdf88f62b0 305 #define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 306 #define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
<> 128:9bcdf88f62b0 307 /**
<> 128:9bcdf88f62b0 308 * @}
<> 128:9bcdf88f62b0 309 */
<> 128:9bcdf88f62b0 310
<> 128:9bcdf88f62b0 311 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
<> 128:9bcdf88f62b0 312 * @{
<> 128:9bcdf88f62b0 313 */
<> 128:9bcdf88f62b0 314 #define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
<> 128:9bcdf88f62b0 315 #define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
<> 128:9bcdf88f62b0 316 #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
<> 128:9bcdf88f62b0 317 #define I2C_LAST_FRAME ((uint32_t)0x00000008U)
<> 128:9bcdf88f62b0 318 /**
<> 128:9bcdf88f62b0 319 * @}
<> 128:9bcdf88f62b0 320 */
<> 128:9bcdf88f62b0 321
<> 128:9bcdf88f62b0 322 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 128:9bcdf88f62b0 323 * @brief I2C Interrupt definition
<> 128:9bcdf88f62b0 324 * Elements values convention: 0xXXXXXXXX
<> 128:9bcdf88f62b0 325 * - XXXXXXXX : Interrupt control mask
<> 128:9bcdf88f62b0 326 * @{
<> 128:9bcdf88f62b0 327 */
<> 128:9bcdf88f62b0 328 #define I2C_IT_BUF I2C_CR2_ITBUFEN
<> 128:9bcdf88f62b0 329 #define I2C_IT_EVT I2C_CR2_ITEVTEN
<> 128:9bcdf88f62b0 330 #define I2C_IT_ERR I2C_CR2_ITERREN
<> 128:9bcdf88f62b0 331 /**
<> 128:9bcdf88f62b0 332 * @}
<> 128:9bcdf88f62b0 333 */
<> 128:9bcdf88f62b0 334
<> 128:9bcdf88f62b0 335 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 128:9bcdf88f62b0 336 * @{
<> 128:9bcdf88f62b0 337 */
<> 128:9bcdf88f62b0 338 #define I2C_FLAG_OVR ((uint32_t)(1U << 16U | I2C_SR1_OVR))
<> 128:9bcdf88f62b0 339 #define I2C_FLAG_AF ((uint32_t)(1U << 16U | I2C_SR1_AF))
<> 128:9bcdf88f62b0 340 #define I2C_FLAG_ARLO ((uint32_t)(1U << 16U | I2C_SR1_ARLO))
<> 128:9bcdf88f62b0 341 #define I2C_FLAG_BERR ((uint32_t)(1U << 16U | I2C_SR1_BERR))
<> 128:9bcdf88f62b0 342 #define I2C_FLAG_TXE ((uint32_t)(1U << 16U | I2C_SR1_TXE))
<> 128:9bcdf88f62b0 343 #define I2C_FLAG_RXNE ((uint32_t)(1U << 16U | I2C_SR1_RXNE))
<> 128:9bcdf88f62b0 344 #define I2C_FLAG_STOPF ((uint32_t)(1U << 16U | I2C_SR1_STOPF))
<> 128:9bcdf88f62b0 345 #define I2C_FLAG_ADD10 ((uint32_t)(1U << 16U | I2C_SR1_ADD10))
<> 128:9bcdf88f62b0 346 #define I2C_FLAG_BTF ((uint32_t)(1U << 16U | I2C_SR1_BTF))
<> 128:9bcdf88f62b0 347 #define I2C_FLAG_ADDR ((uint32_t)(1U << 16U | I2C_SR1_ADDR))
<> 128:9bcdf88f62b0 348 #define I2C_FLAG_SB ((uint32_t)(1U << 16U | I2C_SR1_SB))
<> 128:9bcdf88f62b0 349 #define I2C_FLAG_DUALF ((uint32_t)(2U << 16U | I2C_SR2_DUALF))
<> 128:9bcdf88f62b0 350 #define I2C_FLAG_GENCALL ((uint32_t)(2U << 16U | I2C_SR2_GENCALL))
<> 128:9bcdf88f62b0 351 #define I2C_FLAG_TRA ((uint32_t)(2U << 16U | I2C_SR2_TRA))
<> 128:9bcdf88f62b0 352 #define I2C_FLAG_BUSY ((uint32_t)(2U << 16U | I2C_SR2_BUSY))
<> 128:9bcdf88f62b0 353 #define I2C_FLAG_MSL ((uint32_t)(2U << 16U | I2C_SR2_MSL))
<> 128:9bcdf88f62b0 354 /**
<> 128:9bcdf88f62b0 355 * @}
<> 128:9bcdf88f62b0 356 */
<> 128:9bcdf88f62b0 357
<> 128:9bcdf88f62b0 358 /**
<> 128:9bcdf88f62b0 359 * @}
<> 128:9bcdf88f62b0 360 */
<> 128:9bcdf88f62b0 361
<> 128:9bcdf88f62b0 362 /* Exported macros -----------------------------------------------------------*/
<> 128:9bcdf88f62b0 363 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 128:9bcdf88f62b0 364 * @{
<> 128:9bcdf88f62b0 365 */
<> 128:9bcdf88f62b0 366
<> 128:9bcdf88f62b0 367 /** @brief Reset I2C handle state.
<> 128:9bcdf88f62b0 368 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 369 * @retval None
<> 128:9bcdf88f62b0 370 */
<> 128:9bcdf88f62b0 371 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 128:9bcdf88f62b0 372
<> 128:9bcdf88f62b0 373 /** @brief Enable the specified I2C interrupt.
<> 128:9bcdf88f62b0 374 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 375 * @param __INTERRUPT__: specifies the interrupt source to enable.
<> 128:9bcdf88f62b0 376 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 377 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 128:9bcdf88f62b0 378 * @arg I2C_IT_EVT: Event interrupt enable
<> 128:9bcdf88f62b0 379 * @arg I2C_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 380 * @retval None
<> 128:9bcdf88f62b0 381 */
<> 128:9bcdf88f62b0 382 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
<> 128:9bcdf88f62b0 383
<> 128:9bcdf88f62b0 384 /** @brief Disable the specified I2C interrupt.
<> 128:9bcdf88f62b0 385 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 386 * @param __INTERRUPT__: specifies the interrupt source to disable.
<> 128:9bcdf88f62b0 387 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 388 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 128:9bcdf88f62b0 389 * @arg I2C_IT_EVT: Event interrupt enable
<> 128:9bcdf88f62b0 390 * @arg I2C_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 391 *
<> 128:9bcdf88f62b0 392 * @retval None
<> 128:9bcdf88f62b0 393 */
<> 128:9bcdf88f62b0 394 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 128:9bcdf88f62b0 395
<> 128:9bcdf88f62b0 396 /** @brief Check whether the specified I2C interrupt source is enabled or not.
<> 128:9bcdf88f62b0 397 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 398 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
<> 128:9bcdf88f62b0 399 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 400 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 128:9bcdf88f62b0 401 * @arg I2C_IT_EVT: Event interrupt enable
<> 128:9bcdf88f62b0 402 * @arg I2C_IT_ERR: Error interrupt enable
<> 128:9bcdf88f62b0 403 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 404 */
<> 128:9bcdf88f62b0 405 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 128:9bcdf88f62b0 406
<> 128:9bcdf88f62b0 407 /** @brief Check whether the specified I2C flag is set or not.
<> 128:9bcdf88f62b0 408 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 409 * @param __FLAG__ specifies the flag to check.
<> 128:9bcdf88f62b0 410 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 411 * @arg I2C_FLAG_OVR: Overrun/Underrun flag
<> 128:9bcdf88f62b0 412 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 128:9bcdf88f62b0 413 * @arg I2C_FLAG_ARLO: Arbitration lost flag
<> 128:9bcdf88f62b0 414 * @arg I2C_FLAG_BERR: Bus error flag
<> 128:9bcdf88f62b0 415 * @arg I2C_FLAG_TXE: Data register empty flag
<> 128:9bcdf88f62b0 416 * @arg I2C_FLAG_RXNE: Data register not empty flag
<> 128:9bcdf88f62b0 417 * @arg I2C_FLAG_STOPF: Stop detection flag
<> 128:9bcdf88f62b0 418 * @arg I2C_FLAG_ADD10: 10-bit header sent flag
<> 128:9bcdf88f62b0 419 * @arg I2C_FLAG_BTF: Byte transfer finished flag
<> 128:9bcdf88f62b0 420 * @arg I2C_FLAG_ADDR: Address sent flag
<> 128:9bcdf88f62b0 421 * Address matched flag
<> 128:9bcdf88f62b0 422 * @arg I2C_FLAG_SB: Start bit flag
<> 128:9bcdf88f62b0 423 * @arg I2C_FLAG_DUALF: Dual flag
<> 128:9bcdf88f62b0 424 * @arg I2C_FLAG_GENCALL: General call header flag
<> 128:9bcdf88f62b0 425 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
<> 128:9bcdf88f62b0 426 * @arg I2C_FLAG_BUSY: Bus busy flag
<> 128:9bcdf88f62b0 427 * @arg I2C_FLAG_MSL: Master/Slave flag
<> 128:9bcdf88f62b0 428 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 429 */
<> 128:9bcdf88f62b0 430 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET): \
<> 128:9bcdf88f62b0 431 (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
<> 128:9bcdf88f62b0 432
<> 128:9bcdf88f62b0 433 /** @brief Clear the I2C pending flags which are cleared by writing 0 in a specific bit.
<> 128:9bcdf88f62b0 434 * @param __HANDLE__ specifies the I2C Handle.
<> 128:9bcdf88f62b0 435 * @param __FLAG__ specifies the flag to clear.
<> 128:9bcdf88f62b0 436 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 437 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
<> 128:9bcdf88f62b0 438 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 128:9bcdf88f62b0 439 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
<> 128:9bcdf88f62b0 440 * @arg I2C_FLAG_BERR: Bus error flag
<> 128:9bcdf88f62b0 441 * @retval None
<> 128:9bcdf88f62b0 442 */
<> 128:9bcdf88f62b0 443 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
<> 128:9bcdf88f62b0 444
<> 128:9bcdf88f62b0 445 /** @brief Clears the I2C ADDR pending flag.
<> 128:9bcdf88f62b0 446 * @param __HANDLE__: specifies the I2C Handle.
<> 128:9bcdf88f62b0 447 * @retval None
<> 128:9bcdf88f62b0 448 */
<> 128:9bcdf88f62b0 449 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 450 do{ \
<> 128:9bcdf88f62b0 451 __IO uint32_t tmpreg = 0x00U; \
<> 128:9bcdf88f62b0 452 tmpreg = (__HANDLE__)->Instance->SR1; \
<> 128:9bcdf88f62b0 453 tmpreg = (__HANDLE__)->Instance->SR2; \
<> 128:9bcdf88f62b0 454 UNUSED(tmpreg); \
<> 128:9bcdf88f62b0 455 }while(0)
<> 128:9bcdf88f62b0 456
<> 128:9bcdf88f62b0 457 /** @brief Clears the I2C STOPF pending flag.
<> 128:9bcdf88f62b0 458 * @param __HANDLE__: specifies the I2C Handle.
<> 128:9bcdf88f62b0 459 * @retval None
<> 128:9bcdf88f62b0 460 */
<> 128:9bcdf88f62b0 461 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
<> 128:9bcdf88f62b0 462 do{ \
<> 128:9bcdf88f62b0 463 __IO uint32_t tmpreg = 0x00U; \
<> 128:9bcdf88f62b0 464 tmpreg = (__HANDLE__)->Instance->SR1; \
<> 128:9bcdf88f62b0 465 SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
<> 128:9bcdf88f62b0 466 UNUSED(tmpreg); \
<> 128:9bcdf88f62b0 467 }while(0)
<> 128:9bcdf88f62b0 468
<> 128:9bcdf88f62b0 469 /** @brief Enable the I2C peripheral.
<> 128:9bcdf88f62b0 470 * @param __HANDLE__: specifies the I2C Handle.
<> 128:9bcdf88f62b0 471 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 128:9bcdf88f62b0 472 * @retval None
<> 128:9bcdf88f62b0 473 */
<> 128:9bcdf88f62b0 474 #define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
<> 128:9bcdf88f62b0 475
<> 128:9bcdf88f62b0 476 /** @brief Disable the I2C peripheral.
<> 128:9bcdf88f62b0 477 * @param __HANDLE__: specifies the I2C Handle.
<> 128:9bcdf88f62b0 478 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 128:9bcdf88f62b0 479 * @retval None
<> 128:9bcdf88f62b0 480 */
<> 128:9bcdf88f62b0 481 #define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
<> 128:9bcdf88f62b0 482
<> 128:9bcdf88f62b0 483 /**
<> 128:9bcdf88f62b0 484 * @}
<> 128:9bcdf88f62b0 485 */
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 488 /** @addtogroup I2C_Exported_Functions
<> 128:9bcdf88f62b0 489 * @{
<> 128:9bcdf88f62b0 490 */
<> 128:9bcdf88f62b0 491
<> 128:9bcdf88f62b0 492 /** @addtogroup I2C_Exported_Functions_Group1
<> 128:9bcdf88f62b0 493 * @{
<> 128:9bcdf88f62b0 494 */
<> 128:9bcdf88f62b0 495 /* Initialization and de-initialization functions******************************/
<> 128:9bcdf88f62b0 496 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 497 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 498 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 499 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 500
<> 128:9bcdf88f62b0 501 /**
<> 128:9bcdf88f62b0 502 * @}
<> 128:9bcdf88f62b0 503 */
<> 128:9bcdf88f62b0 504
<> 128:9bcdf88f62b0 505 /** @addtogroup I2C_Exported_Functions_Group2
<> 128:9bcdf88f62b0 506 * @{
<> 128:9bcdf88f62b0 507 */
<> 128:9bcdf88f62b0 508 /* IO operation functions ****************************************************/
<> 128:9bcdf88f62b0 509 /******* Blocking mode: Polling */
<> 128:9bcdf88f62b0 510 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 511 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 512 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 513 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 514 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 515 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 128:9bcdf88f62b0 516 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 128:9bcdf88f62b0 517
<> 128:9bcdf88f62b0 518 /******* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 519 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 520 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 521 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 522 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 523 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 524 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 525
<> 128:9bcdf88f62b0 526 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 128:9bcdf88f62b0 527 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 128:9bcdf88f62b0 528 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 128:9bcdf88f62b0 529 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 128:9bcdf88f62b0 530 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
<> 128:9bcdf88f62b0 531 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 532 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 533
<> 128:9bcdf88f62b0 534 /******* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 535 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 536 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 537 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 538 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 539 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 540 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 128:9bcdf88f62b0 541 /**
<> 128:9bcdf88f62b0 542 * @}
<> 128:9bcdf88f62b0 543 */
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 128:9bcdf88f62b0 546 * @{
<> 128:9bcdf88f62b0 547 */
<> 128:9bcdf88f62b0 548 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 128:9bcdf88f62b0 549 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 550 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 551 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 552 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 553 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 554 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 555 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 128:9bcdf88f62b0 556 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 557 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 558 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 559 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 560 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 561 /**
<> 128:9bcdf88f62b0 562 * @}
<> 128:9bcdf88f62b0 563 */
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /** @addtogroup I2C_Exported_Functions_Group3
<> 128:9bcdf88f62b0 566 * @{
<> 128:9bcdf88f62b0 567 */
<> 128:9bcdf88f62b0 568 /* Peripheral State, Mode and Error functions *********************************/
<> 128:9bcdf88f62b0 569 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 570 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 571 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 128:9bcdf88f62b0 572
<> 128:9bcdf88f62b0 573 /**
<> 128:9bcdf88f62b0 574 * @}
<> 128:9bcdf88f62b0 575 */
<> 128:9bcdf88f62b0 576 /**
<> 128:9bcdf88f62b0 577 * @}
<> 128:9bcdf88f62b0 578 */
<> 128:9bcdf88f62b0 579
<> 128:9bcdf88f62b0 580 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 581 /** @defgroup I2C_Private_Constants I2C Private Constants
<> 128:9bcdf88f62b0 582 * @{
<> 128:9bcdf88f62b0 583 */
<> 128:9bcdf88f62b0 584 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
<> 128:9bcdf88f62b0 585 /**
<> 128:9bcdf88f62b0 586 * @}
<> 128:9bcdf88f62b0 587 */
<> 128:9bcdf88f62b0 588
<> 128:9bcdf88f62b0 589 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 590 /** @defgroup I2C_Private_Macro I2C Private Macros
<> 128:9bcdf88f62b0 591 * @{
<> 128:9bcdf88f62b0 592 */
<> 128:9bcdf88f62b0 593
<> 128:9bcdf88f62b0 594 #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
<> 128:9bcdf88f62b0 595 ((MODE) == I2C_ADDRESSINGMODE_10BIT))
<> 128:9bcdf88f62b0 596
<> 128:9bcdf88f62b0 597
<> 128:9bcdf88f62b0 598 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 128:9bcdf88f62b0 599 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 128:9bcdf88f62b0 600
<> 128:9bcdf88f62b0 601 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
<> 128:9bcdf88f62b0 602 ((CYCLE) == I2C_DUTYCYCLE_16_9))
<> 128:9bcdf88f62b0 603 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (0xFFFFFF01U)) == 0U)
<> 128:9bcdf88f62b0 604 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (0xFFFFFC00U)) == 0U)
<> 128:9bcdf88f62b0 605 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 128:9bcdf88f62b0 606 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 128:9bcdf88f62b0 607
<> 128:9bcdf88f62b0 608 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 128:9bcdf88f62b0 609 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 128:9bcdf88f62b0 610
<> 128:9bcdf88f62b0 611 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 128:9bcdf88f62b0 612 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 128:9bcdf88f62b0 613
<> 128:9bcdf88f62b0 614 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
<> 128:9bcdf88f62b0 615
<> 128:9bcdf88f62b0 616
<> 128:9bcdf88f62b0 617 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
<> 128:9bcdf88f62b0 618 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 128:9bcdf88f62b0 619
<> 128:9bcdf88f62b0 620
<> 128:9bcdf88f62b0 621 #define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000U)
<> 128:9bcdf88f62b0 622 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
<> 128:9bcdf88f62b0 623 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
<> 128:9bcdf88f62b0 624 #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
<> 128:9bcdf88f62b0 625 #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
<> 128:9bcdf88f62b0 626 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
<> 128:9bcdf88f62b0 627 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
<> 128:9bcdf88f62b0 628
<> 128:9bcdf88f62b0 629 #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
<> 128:9bcdf88f62b0 630 #define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
<> 128:9bcdf88f62b0 631
<> 128:9bcdf88f62b0 632 #define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 128:9bcdf88f62b0 633 #define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF0U))))
<> 128:9bcdf88f62b0 634 #define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF1U))))
<> 128:9bcdf88f62b0 635
<> 128:9bcdf88f62b0 636 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
<> 128:9bcdf88f62b0 637 ((REQUEST) == I2C_NEXT_FRAME) || \
<> 128:9bcdf88f62b0 638 ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
<> 128:9bcdf88f62b0 639 ((REQUEST) == I2C_LAST_FRAME))
<> 128:9bcdf88f62b0 640 /**
<> 128:9bcdf88f62b0 641 * @}
<> 128:9bcdf88f62b0 642 */
<> 128:9bcdf88f62b0 643
<> 128:9bcdf88f62b0 644 /* Private Functions ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 645 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 128:9bcdf88f62b0 646 * @{
<> 128:9bcdf88f62b0 647 */
<> 128:9bcdf88f62b0 648 /* Private functions are defined in stm32f0xx_hal_i2c.c file */
<> 128:9bcdf88f62b0 649 /**
<> 128:9bcdf88f62b0 650 * @}
<> 128:9bcdf88f62b0 651 */
<> 128:9bcdf88f62b0 652
<> 128:9bcdf88f62b0 653 /**
<> 128:9bcdf88f62b0 654 * @}
<> 128:9bcdf88f62b0 655 */
<> 128:9bcdf88f62b0 656
<> 128:9bcdf88f62b0 657 /**
<> 128:9bcdf88f62b0 658 * @}
<> 128:9bcdf88f62b0 659 */
<> 128:9bcdf88f62b0 660
<> 128:9bcdf88f62b0 661 #ifdef __cplusplus
<> 128:9bcdf88f62b0 662 }
<> 128:9bcdf88f62b0 663 #endif
<> 128:9bcdf88f62b0 664
<> 128:9bcdf88f62b0 665
<> 128:9bcdf88f62b0 666 #endif /* __STM32L1xx_HAL_I2C_H */
<> 128:9bcdf88f62b0 667
<> 128:9bcdf88f62b0 668 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 128:9bcdf88f62b0 669