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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_flash.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of Flash HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_FLASH_EX_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_FLASH_EX_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup FLASHEx
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /** @addtogroup FLASHEx_Private_Constants
<> 128:9bcdf88f62b0 58 * @{
<> 128:9bcdf88f62b0 59 */
<> 128:9bcdf88f62b0 60 #if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 128:9bcdf88f62b0 63 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 128:9bcdf88f62b0 64 FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 #elif defined(FLASH_SR_RDERR)
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 128:9bcdf88f62b0 69 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 128:9bcdf88f62b0 70 FLASH_FLAG_RDERR)
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 #elif defined(FLASH_SR_OPTVERRUSR)
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 128:9bcdf88f62b0 75 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 128:9bcdf88f62b0 76 FLASH_FLAG_OPTVERRUSR)
<> 128:9bcdf88f62b0 77
<> 128:9bcdf88f62b0 78 #else
<> 128:9bcdf88f62b0 79
<> 128:9bcdf88f62b0 80 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 128:9bcdf88f62b0 81 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 #endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
<> 128:9bcdf88f62b0 86 || defined(STM32L151xBA) || defined(STM32L152xBA)
<> 128:9bcdf88f62b0 87
<> 128:9bcdf88f62b0 88 /******* Devices with FLASH 128K *******/
<> 128:9bcdf88f62b0 89 #define FLASH_NBPAGES_MAX 512 /* 512 pages from page 0 to page 511 */
<> 128:9bcdf88f62b0 90
<> 128:9bcdf88f62b0 91 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 128:9bcdf88f62b0 92 || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 /******* Devices with FLASH 256K *******/
<> 128:9bcdf88f62b0 95 #define FLASH_NBPAGES_MAX 1025 /* 1025 pages from page 0 to page 1024 */
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 128:9bcdf88f62b0 98 || defined(STM32L162xD) || defined(STM32L162xDX)
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /******* Devices with FLASH 384K *******/
<> 128:9bcdf88f62b0 101 #define FLASH_NBPAGES_MAX 1536 /* 1536 pages from page 0 to page 1535 */
<> 128:9bcdf88f62b0 102
<> 128:9bcdf88f62b0 103 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 128:9bcdf88f62b0 104
<> 128:9bcdf88f62b0 105 /******* Devices with FLASH 512K *******/
<> 128:9bcdf88f62b0 106 #define FLASH_NBPAGES_MAX 2048 /* 2048 pages from page 0 to page 2047 */
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
<> 128:9bcdf88f62b0 109
<> 128:9bcdf88f62b0 110 #define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
<> 128:9bcdf88f62b0 111 #define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /**
<> 128:9bcdf88f62b0 114 * @}
<> 128:9bcdf88f62b0 115 */
<> 128:9bcdf88f62b0 116
<> 128:9bcdf88f62b0 117 /** @addtogroup FLASHEx_Private_Macros
<> 128:9bcdf88f62b0 118 * @{
<> 128:9bcdf88f62b0 119 */
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
<> 128:9bcdf88f62b0 126 ((__VALUE__) == OB_WRPSTATE_ENABLE))
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
<> 128:9bcdf88f62b0 129
<> 128:9bcdf88f62b0 130 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
<> 128:9bcdf88f62b0 131 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
<> 128:9bcdf88f62b0 132 ((__LEVEL__) == OB_RDP_LEVEL_2))
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
<> 128:9bcdf88f62b0 135 ((__LEVEL__) == OB_BOR_LEVEL1) || \
<> 128:9bcdf88f62b0 136 ((__LEVEL__) == OB_BOR_LEVEL2) || \
<> 128:9bcdf88f62b0 137 ((__LEVEL__) == OB_BOR_LEVEL3) || \
<> 128:9bcdf88f62b0 138 ((__LEVEL__) == OB_BOR_LEVEL4) || \
<> 128:9bcdf88f62b0 139 ((__LEVEL__) == OB_BOR_LEVEL5))
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
<> 128:9bcdf88f62b0 144
<> 128:9bcdf88f62b0 145 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 #if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 148
<> 128:9bcdf88f62b0 149 #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 #elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
<> 128:9bcdf88f62b0 154
<> 128:9bcdf88f62b0 155 #elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
<> 128:9bcdf88f62b0 158
<> 128:9bcdf88f62b0 159 #endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 #if defined(FLASH_OBR_SPRMOD)
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
<> 128:9bcdf88f62b0 164 ((__VALUE__) == OB_PCROP_STATE_ENABLE))
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
<> 128:9bcdf88f62b0 167 #endif /* FLASH_OBR_SPRMOD */
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 #if defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 170
<> 128:9bcdf88f62b0 171 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 #endif /* FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 174
<> 128:9bcdf88f62b0 175 #define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
<> 128:9bcdf88f62b0 176 ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
<> 128:9bcdf88f62b0 177 ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
<> 128:9bcdf88f62b0 178
<> 128:9bcdf88f62b0 179 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
<> 128:9bcdf88f62b0 180 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
<> 128:9bcdf88f62b0 181 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
<> 128:9bcdf88f62b0 182 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
<> 128:9bcdf88f62b0 183 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
<> 128:9bcdf88f62b0 184 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
<> 128:9bcdf88f62b0 185
<> 128:9bcdf88f62b0 186 /** @defgroup FLASHEx_Address FLASHEx Address
<> 128:9bcdf88f62b0 187 * @{
<> 128:9bcdf88f62b0 188 */
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
<> 128:9bcdf88f62b0 193 || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
<> 128:9bcdf88f62b0 194 || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
<> 128:9bcdf88f62b0 195 || defined(STM32L162xCA)
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 #else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
<> 128:9bcdf88f62b0 202 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))
<> 128:9bcdf88f62b0 203 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
<> 128:9bcdf88f62b0 204
<> 128:9bcdf88f62b0 205 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
<> 128:9bcdf88f62b0 206
<> 128:9bcdf88f62b0 207 #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 /**
<> 128:9bcdf88f62b0 210 * @}
<> 128:9bcdf88f62b0 211 */
<> 128:9bcdf88f62b0 212
<> 128:9bcdf88f62b0 213 /**
<> 128:9bcdf88f62b0 214 * @}
<> 128:9bcdf88f62b0 215 */
<> 128:9bcdf88f62b0 216 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 128:9bcdf88f62b0 219 * @{
<> 128:9bcdf88f62b0 220 */
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 /**
<> 128:9bcdf88f62b0 223 * @brief FLASH Erase structure definition
<> 128:9bcdf88f62b0 224 */
<> 128:9bcdf88f62b0 225 typedef struct
<> 128:9bcdf88f62b0 226 {
<> 128:9bcdf88f62b0 227 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
<> 128:9bcdf88f62b0 228 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
<> 128:9bcdf88f62b0 231 This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
<> 128:9bcdf88f62b0 234 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 } FLASH_EraseInitTypeDef;
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 /**
<> 128:9bcdf88f62b0 239 * @brief FLASH Option Bytes PROGRAM structure definition
<> 128:9bcdf88f62b0 240 */
<> 128:9bcdf88f62b0 241 typedef struct
<> 128:9bcdf88f62b0 242 {
<> 128:9bcdf88f62b0 243 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 128:9bcdf88f62b0 244 This parameter can be a value of @ref FLASHEx_Option_Type */
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 128:9bcdf88f62b0 247 This parameter can be a value of @ref FLASHEx_WRP_State */
<> 128:9bcdf88f62b0 248
<> 128:9bcdf88f62b0 249 uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
<> 128:9bcdf88f62b0 250 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */
<> 128:9bcdf88f62b0 251
<> 128:9bcdf88f62b0 252 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 128:9bcdf88f62b0 253 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
<> 128:9bcdf88f62b0 254 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
<> 128:9bcdf88f62b0 255 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 128:9bcdf88f62b0 256 uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
<> 128:9bcdf88f62b0 257 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
<> 128:9bcdf88f62b0 258 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 128:9bcdf88f62b0 261 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 128:9bcdf88f62b0 262 || defined(STM32L162xE)
<> 128:9bcdf88f62b0 263 uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
<> 128:9bcdf88f62b0 264 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */
<> 128:9bcdf88f62b0 265 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 266
<> 128:9bcdf88f62b0 267 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
<> 128:9bcdf88f62b0 268 || defined(STM32L152xDX) || defined(STM32L162xDX)
<> 128:9bcdf88f62b0 269 uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
<> 128:9bcdf88f62b0 270 Sectors 96 to 111 for STM32L1xxxDX devices.
<> 128:9bcdf88f62b0 271 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
<> 128:9bcdf88f62b0 272 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
<> 128:9bcdf88f62b0 275 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
<> 128:9bcdf88f62b0 276
<> 128:9bcdf88f62b0 277 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
<> 128:9bcdf88f62b0 278 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
<> 128:9bcdf88f62b0 279
<> 128:9bcdf88f62b0 280 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
<> 128:9bcdf88f62b0 281 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
<> 128:9bcdf88f62b0 282 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
<> 128:9bcdf88f62b0 283 } FLASH_OBProgramInitTypeDef;
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 286 /**
<> 128:9bcdf88f62b0 287 * @brief FLASH Advanced Option Bytes Program structure definition
<> 128:9bcdf88f62b0 288 */
<> 128:9bcdf88f62b0 289 typedef struct
<> 128:9bcdf88f62b0 290 {
<> 128:9bcdf88f62b0 291 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
<> 128:9bcdf88f62b0 292 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
<> 128:9bcdf88f62b0 293
<> 128:9bcdf88f62b0 294 #if defined(FLASH_OBR_SPRMOD)
<> 128:9bcdf88f62b0 295 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
<> 128:9bcdf88f62b0 296 This parameter can be a value of @ref FLASHEx_PCROP_State */
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
<> 128:9bcdf88f62b0 299 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
<> 128:9bcdf88f62b0 300
<> 128:9bcdf88f62b0 301 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
<> 128:9bcdf88f62b0 302 uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
<> 128:9bcdf88f62b0 303 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
<> 128:9bcdf88f62b0 304 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
<> 128:9bcdf88f62b0 305 #endif /* FLASH_OBR_SPRMOD */
<> 128:9bcdf88f62b0 306
<> 128:9bcdf88f62b0 307 #if defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 308 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
<> 128:9bcdf88f62b0 309 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
<> 128:9bcdf88f62b0 310 #endif /* FLASH_OBR_nRST_BFB2*/
<> 128:9bcdf88f62b0 311 } FLASH_AdvOBProgramInitTypeDef;
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /**
<> 128:9bcdf88f62b0 314 * @}
<> 128:9bcdf88f62b0 315 */
<> 128:9bcdf88f62b0 316 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 319
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 128:9bcdf88f62b0 322 * @{
<> 128:9bcdf88f62b0 323 */
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
<> 128:9bcdf88f62b0 326 * @{
<> 128:9bcdf88f62b0 327 */
<> 128:9bcdf88f62b0 328 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
<> 128:9bcdf88f62b0 329
<> 128:9bcdf88f62b0 330 /**
<> 128:9bcdf88f62b0 331 * @}
<> 128:9bcdf88f62b0 332 */
<> 128:9bcdf88f62b0 333
<> 128:9bcdf88f62b0 334 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
<> 128:9bcdf88f62b0 335 * @{
<> 128:9bcdf88f62b0 336 */
<> 128:9bcdf88f62b0 337 #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
<> 128:9bcdf88f62b0 338 #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
<> 128:9bcdf88f62b0 339 #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
<> 128:9bcdf88f62b0 340 #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
<> 128:9bcdf88f62b0 341
<> 128:9bcdf88f62b0 342 /**
<> 128:9bcdf88f62b0 343 * @}
<> 128:9bcdf88f62b0 344 */
<> 128:9bcdf88f62b0 345
<> 128:9bcdf88f62b0 346 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
<> 128:9bcdf88f62b0 347 * @{
<> 128:9bcdf88f62b0 348 */
<> 128:9bcdf88f62b0 349 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
<> 128:9bcdf88f62b0 350 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
<> 128:9bcdf88f62b0 351
<> 128:9bcdf88f62b0 352 /**
<> 128:9bcdf88f62b0 353 * @}
<> 128:9bcdf88f62b0 354 */
<> 128:9bcdf88f62b0 355
<> 128:9bcdf88f62b0 356 /** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
<> 128:9bcdf88f62b0 357 * @{
<> 128:9bcdf88f62b0 358 */
<> 128:9bcdf88f62b0 359
<> 128:9bcdf88f62b0 360 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
<> 128:9bcdf88f62b0 361 #define OB_WRP1_PAGES0TO15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
<> 128:9bcdf88f62b0 362 #define OB_WRP1_PAGES16TO31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
<> 128:9bcdf88f62b0 363 #define OB_WRP1_PAGES32TO47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
<> 128:9bcdf88f62b0 364 #define OB_WRP1_PAGES48TO63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
<> 128:9bcdf88f62b0 365 #define OB_WRP1_PAGES64TO79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
<> 128:9bcdf88f62b0 366 #define OB_WRP1_PAGES80TO95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
<> 128:9bcdf88f62b0 367 #define OB_WRP1_PAGES96TO111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
<> 128:9bcdf88f62b0 368 #define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
<> 128:9bcdf88f62b0 369 #define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
<> 128:9bcdf88f62b0 370 #define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
<> 128:9bcdf88f62b0 371 #define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
<> 128:9bcdf88f62b0 372 #define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
<> 128:9bcdf88f62b0 373 #define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
<> 128:9bcdf88f62b0 374 #define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
<> 128:9bcdf88f62b0 375 #define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
<> 128:9bcdf88f62b0 376 #define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
<> 128:9bcdf88f62b0 377 #define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
<> 128:9bcdf88f62b0 378 #define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
<> 128:9bcdf88f62b0 379 #define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
<> 128:9bcdf88f62b0 380 #define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
<> 128:9bcdf88f62b0 381 #define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
<> 128:9bcdf88f62b0 382 #define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
<> 128:9bcdf88f62b0 383 #define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
<> 128:9bcdf88f62b0 384 #define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
<> 128:9bcdf88f62b0 385 #define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
<> 128:9bcdf88f62b0 386 #define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
<> 128:9bcdf88f62b0 387 #define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
<> 128:9bcdf88f62b0 388 #define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
<> 128:9bcdf88f62b0 389 #define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
<> 128:9bcdf88f62b0 390 #define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
<> 128:9bcdf88f62b0 391 #define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
<> 128:9bcdf88f62b0 392 #define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
<> 128:9bcdf88f62b0 393
<> 128:9bcdf88f62b0 394 #define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
<> 128:9bcdf88f62b0 395
<> 128:9bcdf88f62b0 396 /**
<> 128:9bcdf88f62b0 397 * @}
<> 128:9bcdf88f62b0 398 */
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 128:9bcdf88f62b0 401 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
<> 128:9bcdf88f62b0 402 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
<> 128:9bcdf88f62b0 403 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 128:9bcdf88f62b0 404
<> 128:9bcdf88f62b0 405 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
<> 128:9bcdf88f62b0 406 * @{
<> 128:9bcdf88f62b0 407 */
<> 128:9bcdf88f62b0 408
<> 128:9bcdf88f62b0 409 /* Pages for Cat3, Cat4 & Cat5 devices*/
<> 128:9bcdf88f62b0 410 #define OB_WRP2_PAGES512TO527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
<> 128:9bcdf88f62b0 411 #define OB_WRP2_PAGES528TO543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
<> 128:9bcdf88f62b0 412 #define OB_WRP2_PAGES544TO559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
<> 128:9bcdf88f62b0 413 #define OB_WRP2_PAGES560TO575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
<> 128:9bcdf88f62b0 414 #define OB_WRP2_PAGES576TO591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
<> 128:9bcdf88f62b0 415 #define OB_WRP2_PAGES592TO607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
<> 128:9bcdf88f62b0 416 #define OB_WRP2_PAGES608TO623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
<> 128:9bcdf88f62b0 417 #define OB_WRP2_PAGES624TO639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
<> 128:9bcdf88f62b0 418 #define OB_WRP2_PAGES640TO655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
<> 128:9bcdf88f62b0 419 #define OB_WRP2_PAGES656TO671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
<> 128:9bcdf88f62b0 420 #define OB_WRP2_PAGES672TO687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
<> 128:9bcdf88f62b0 421 #define OB_WRP2_PAGES688TO703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
<> 128:9bcdf88f62b0 422 #define OB_WRP2_PAGES704TO719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
<> 128:9bcdf88f62b0 423 #define OB_WRP2_PAGES720TO735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
<> 128:9bcdf88f62b0 424 #define OB_WRP2_PAGES736TO751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
<> 128:9bcdf88f62b0 425 #define OB_WRP2_PAGES752TO767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
<> 128:9bcdf88f62b0 426
<> 128:9bcdf88f62b0 427 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 128:9bcdf88f62b0 428 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
<> 128:9bcdf88f62b0 429 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 128:9bcdf88f62b0 430 || defined(STM32L162xE)
<> 128:9bcdf88f62b0 431
<> 128:9bcdf88f62b0 432 #define OB_WRP2_PAGES768TO783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
<> 128:9bcdf88f62b0 433 #define OB_WRP2_PAGES784TO799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
<> 128:9bcdf88f62b0 434 #define OB_WRP2_PAGES800TO815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
<> 128:9bcdf88f62b0 435 #define OB_WRP2_PAGES816TO831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
<> 128:9bcdf88f62b0 436 #define OB_WRP2_PAGES832TO847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
<> 128:9bcdf88f62b0 437 #define OB_WRP2_PAGES848TO863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
<> 128:9bcdf88f62b0 438 #define OB_WRP2_PAGES864TO879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
<> 128:9bcdf88f62b0 439 #define OB_WRP2_PAGES880TO895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
<> 128:9bcdf88f62b0 440 #define OB_WRP2_PAGES896TO911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
<> 128:9bcdf88f62b0 441 #define OB_WRP2_PAGES912TO927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
<> 128:9bcdf88f62b0 442 #define OB_WRP2_PAGES928TO943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
<> 128:9bcdf88f62b0 443 #define OB_WRP2_PAGES944TO959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
<> 128:9bcdf88f62b0 444 #define OB_WRP2_PAGES960TO975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
<> 128:9bcdf88f62b0 445 #define OB_WRP2_PAGES976TO991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
<> 128:9bcdf88f62b0 446 #define OB_WRP2_PAGES992TO1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
<> 128:9bcdf88f62b0 447 #define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* Write protection of Sector63 */
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 450
<> 128:9bcdf88f62b0 451 #define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
<> 128:9bcdf88f62b0 452
<> 128:9bcdf88f62b0 453 /**
<> 128:9bcdf88f62b0 454 * @}
<> 128:9bcdf88f62b0 455 */
<> 128:9bcdf88f62b0 456
<> 128:9bcdf88f62b0 457 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 458
<> 128:9bcdf88f62b0 459 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 128:9bcdf88f62b0 460 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 128:9bcdf88f62b0 461 || defined(STM32L162xE)
<> 128:9bcdf88f62b0 462
<> 128:9bcdf88f62b0 463 /** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
<> 128:9bcdf88f62b0 464 * @{
<> 128:9bcdf88f62b0 465 */
<> 128:9bcdf88f62b0 466
<> 128:9bcdf88f62b0 467 /* Pages for devices with FLASH >= 256KB*/
<> 128:9bcdf88f62b0 468 #define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
<> 128:9bcdf88f62b0 469 #define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
<> 128:9bcdf88f62b0 470 #define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
<> 128:9bcdf88f62b0 471 #define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
<> 128:9bcdf88f62b0 472 #define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
<> 128:9bcdf88f62b0 473 #define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
<> 128:9bcdf88f62b0 474 #define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
<> 128:9bcdf88f62b0 475 #define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
<> 128:9bcdf88f62b0 476 #define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
<> 128:9bcdf88f62b0 477 #define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
<> 128:9bcdf88f62b0 478 #define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
<> 128:9bcdf88f62b0 479 #define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
<> 128:9bcdf88f62b0 480 #define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
<> 128:9bcdf88f62b0 481 #define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
<> 128:9bcdf88f62b0 482 #define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
<> 128:9bcdf88f62b0 483 #define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
<> 128:9bcdf88f62b0 484 #define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
<> 128:9bcdf88f62b0 485 #define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
<> 128:9bcdf88f62b0 486 #define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
<> 128:9bcdf88f62b0 487 #define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
<> 128:9bcdf88f62b0 488 #define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
<> 128:9bcdf88f62b0 489 #define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
<> 128:9bcdf88f62b0 490 #define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
<> 128:9bcdf88f62b0 491 #define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
<> 128:9bcdf88f62b0 492 #define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
<> 128:9bcdf88f62b0 493 #define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
<> 128:9bcdf88f62b0 494 #define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
<> 128:9bcdf88f62b0 495 #define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
<> 128:9bcdf88f62b0 496 #define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
<> 128:9bcdf88f62b0 497 #define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
<> 128:9bcdf88f62b0 498 #define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
<> 128:9bcdf88f62b0 499 #define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000U) /* Write protection of Sector95 */
<> 128:9bcdf88f62b0 500
<> 128:9bcdf88f62b0 501 #define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
<> 128:9bcdf88f62b0 502
<> 128:9bcdf88f62b0 503 /**
<> 128:9bcdf88f62b0 504 * @}
<> 128:9bcdf88f62b0 505 */
<> 128:9bcdf88f62b0 506
<> 128:9bcdf88f62b0 507 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
<> 128:9bcdf88f62b0 508
<> 128:9bcdf88f62b0 509 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
<> 128:9bcdf88f62b0 510 || defined(STM32L152xDX) || defined(STM32L162xDX)
<> 128:9bcdf88f62b0 511
<> 128:9bcdf88f62b0 512 /** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
<> 128:9bcdf88f62b0 513 * @{
<> 128:9bcdf88f62b0 514 */
<> 128:9bcdf88f62b0 515
<> 128:9bcdf88f62b0 516 /* Pages for Cat5 devices*/
<> 128:9bcdf88f62b0 517 #define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/
<> 128:9bcdf88f62b0 518 #define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/
<> 128:9bcdf88f62b0 519 #define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/
<> 128:9bcdf88f62b0 520 #define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/
<> 128:9bcdf88f62b0 521 #define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/
<> 128:9bcdf88f62b0 522 #define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/
<> 128:9bcdf88f62b0 523 #define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/
<> 128:9bcdf88f62b0 524 #define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/
<> 128:9bcdf88f62b0 525 #define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/
<> 128:9bcdf88f62b0 526 #define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/
<> 128:9bcdf88f62b0 527 #define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/
<> 128:9bcdf88f62b0 528 #define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/
<> 128:9bcdf88f62b0 529 #define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/
<> 128:9bcdf88f62b0 530 #define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/
<> 128:9bcdf88f62b0 531 #define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/
<> 128:9bcdf88f62b0 532 #define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/
<> 128:9bcdf88f62b0 533
<> 128:9bcdf88f62b0 534 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 128:9bcdf88f62b0 535
<> 128:9bcdf88f62b0 536 #define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/
<> 128:9bcdf88f62b0 537 #define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/
<> 128:9bcdf88f62b0 538 #define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/
<> 128:9bcdf88f62b0 539 #define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/
<> 128:9bcdf88f62b0 540 #define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/
<> 128:9bcdf88f62b0 541 #define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/
<> 128:9bcdf88f62b0 542 #define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/
<> 128:9bcdf88f62b0 543 #define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/
<> 128:9bcdf88f62b0 544 #define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/
<> 128:9bcdf88f62b0 545 #define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/
<> 128:9bcdf88f62b0 546 #define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/
<> 128:9bcdf88f62b0 547 #define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/
<> 128:9bcdf88f62b0 548 #define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/
<> 128:9bcdf88f62b0 549 #define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/
<> 128:9bcdf88f62b0 550 #define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/
<> 128:9bcdf88f62b0 551 #define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000U) /* Write protection of Sector127*/
<> 128:9bcdf88f62b0 552
<> 128:9bcdf88f62b0 553 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */
<> 128:9bcdf88f62b0 554
<> 128:9bcdf88f62b0 555 #define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
<> 128:9bcdf88f62b0 556
<> 128:9bcdf88f62b0 557 /**
<> 128:9bcdf88f62b0 558 * @}
<> 128:9bcdf88f62b0 559 */
<> 128:9bcdf88f62b0 560
<> 128:9bcdf88f62b0 561 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
<> 128:9bcdf88f62b0 562
<> 128:9bcdf88f62b0 563 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
<> 128:9bcdf88f62b0 564 * @{
<> 128:9bcdf88f62b0 565 */
<> 128:9bcdf88f62b0 566 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
<> 128:9bcdf88f62b0 567 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
<> 128:9bcdf88f62b0 568 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
<> 128:9bcdf88f62b0 569 it is no more possible to go back to level 1 or 0 */
<> 128:9bcdf88f62b0 570
<> 128:9bcdf88f62b0 571 /**
<> 128:9bcdf88f62b0 572 * @}
<> 128:9bcdf88f62b0 573 */
<> 128:9bcdf88f62b0 574
<> 128:9bcdf88f62b0 575 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
<> 128:9bcdf88f62b0 576 * @{
<> 128:9bcdf88f62b0 577 */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
<> 128:9bcdf88f62b0 580 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
<> 128:9bcdf88f62b0 581 #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
<> 128:9bcdf88f62b0 582 #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
<> 128:9bcdf88f62b0 583 #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
<> 128:9bcdf88f62b0 584 #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
<> 128:9bcdf88f62b0 585 #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
<> 128:9bcdf88f62b0 586
<> 128:9bcdf88f62b0 587 /**
<> 128:9bcdf88f62b0 588 * @}
<> 128:9bcdf88f62b0 589 */
<> 128:9bcdf88f62b0 590
<> 128:9bcdf88f62b0 591 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
<> 128:9bcdf88f62b0 592 * @{
<> 128:9bcdf88f62b0 593 */
<> 128:9bcdf88f62b0 594
<> 128:9bcdf88f62b0 595 #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
<> 128:9bcdf88f62b0 596 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
<> 128:9bcdf88f62b0 597
<> 128:9bcdf88f62b0 598 /**
<> 128:9bcdf88f62b0 599 * @}
<> 128:9bcdf88f62b0 600 */
<> 128:9bcdf88f62b0 601
<> 128:9bcdf88f62b0 602 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
<> 128:9bcdf88f62b0 603 * @{
<> 128:9bcdf88f62b0 604 */
<> 128:9bcdf88f62b0 605
<> 128:9bcdf88f62b0 606 #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
<> 128:9bcdf88f62b0 607 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
<> 128:9bcdf88f62b0 608 /**
<> 128:9bcdf88f62b0 609 * @}
<> 128:9bcdf88f62b0 610 */
<> 128:9bcdf88f62b0 611
<> 128:9bcdf88f62b0 612 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
<> 128:9bcdf88f62b0 613 * @{
<> 128:9bcdf88f62b0 614 */
<> 128:9bcdf88f62b0 615
<> 128:9bcdf88f62b0 616 #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
<> 128:9bcdf88f62b0 617 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
<> 128:9bcdf88f62b0 618
<> 128:9bcdf88f62b0 619 /**
<> 128:9bcdf88f62b0 620 * @}
<> 128:9bcdf88f62b0 621 */
<> 128:9bcdf88f62b0 622
<> 128:9bcdf88f62b0 623 #if defined(FLASH_OBR_SPRMOD)
<> 128:9bcdf88f62b0 624
<> 128:9bcdf88f62b0 625 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
<> 128:9bcdf88f62b0 626 * @{
<> 128:9bcdf88f62b0 627 */
<> 128:9bcdf88f62b0 628
<> 128:9bcdf88f62b0 629 #define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
<> 128:9bcdf88f62b0 630
<> 128:9bcdf88f62b0 631 /**
<> 128:9bcdf88f62b0 632 * @}
<> 128:9bcdf88f62b0 633 */
<> 128:9bcdf88f62b0 634
<> 128:9bcdf88f62b0 635 #endif /* FLASH_OBR_SPRMOD */
<> 128:9bcdf88f62b0 636
<> 128:9bcdf88f62b0 637 #if defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 638
<> 128:9bcdf88f62b0 639 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
<> 128:9bcdf88f62b0 640 * @{
<> 128:9bcdf88f62b0 641 */
<> 128:9bcdf88f62b0 642
<> 128:9bcdf88f62b0 643 #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
<> 128:9bcdf88f62b0 644
<> 128:9bcdf88f62b0 645 /**
<> 128:9bcdf88f62b0 646 * @}
<> 128:9bcdf88f62b0 647 */
<> 128:9bcdf88f62b0 648
<> 128:9bcdf88f62b0 649 #endif /* FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 650
<> 128:9bcdf88f62b0 651 #if defined(FLASH_OBR_SPRMOD)
<> 128:9bcdf88f62b0 652
<> 128:9bcdf88f62b0 653 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
<> 128:9bcdf88f62b0 654 * @{
<> 128:9bcdf88f62b0 655 */
<> 128:9bcdf88f62b0 656 #define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
<> 128:9bcdf88f62b0 657 #define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
<> 128:9bcdf88f62b0 658
<> 128:9bcdf88f62b0 659 /**
<> 128:9bcdf88f62b0 660 * @}
<> 128:9bcdf88f62b0 661 */
<> 128:9bcdf88f62b0 662
<> 128:9bcdf88f62b0 663 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
<> 128:9bcdf88f62b0 664 * @{
<> 128:9bcdf88f62b0 665 */
<> 128:9bcdf88f62b0 666 #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
<> 128:9bcdf88f62b0 667 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
<> 128:9bcdf88f62b0 668
<> 128:9bcdf88f62b0 669 /**
<> 128:9bcdf88f62b0 670 * @}
<> 128:9bcdf88f62b0 671 */
<> 128:9bcdf88f62b0 672 #endif /* FLASH_OBR_SPRMOD */
<> 128:9bcdf88f62b0 673
<> 128:9bcdf88f62b0 674 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 128:9bcdf88f62b0 675 || defined(STM32L162xC)
<> 128:9bcdf88f62b0 676 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
<> 128:9bcdf88f62b0 677 * @{
<> 128:9bcdf88f62b0 678 */
<> 128:9bcdf88f62b0 679
<> 128:9bcdf88f62b0 680 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
<> 128:9bcdf88f62b0 681 #define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
<> 128:9bcdf88f62b0 682 #define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
<> 128:9bcdf88f62b0 683 #define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
<> 128:9bcdf88f62b0 684 #define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
<> 128:9bcdf88f62b0 685 #define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
<> 128:9bcdf88f62b0 686 #define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
<> 128:9bcdf88f62b0 687 #define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
<> 128:9bcdf88f62b0 688 #define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
<> 128:9bcdf88f62b0 689 #define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
<> 128:9bcdf88f62b0 690 #define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
<> 128:9bcdf88f62b0 691 #define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
<> 128:9bcdf88f62b0 692 #define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
<> 128:9bcdf88f62b0 693 #define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
<> 128:9bcdf88f62b0 694 #define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
<> 128:9bcdf88f62b0 695 #define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
<> 128:9bcdf88f62b0 696 #define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
<> 128:9bcdf88f62b0 697 #define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
<> 128:9bcdf88f62b0 698 #define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
<> 128:9bcdf88f62b0 699 #define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
<> 128:9bcdf88f62b0 700 #define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
<> 128:9bcdf88f62b0 701 #define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
<> 128:9bcdf88f62b0 702 #define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
<> 128:9bcdf88f62b0 703 #define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
<> 128:9bcdf88f62b0 704 #define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
<> 128:9bcdf88f62b0 705 #define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
<> 128:9bcdf88f62b0 706 #define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
<> 128:9bcdf88f62b0 707 #define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
<> 128:9bcdf88f62b0 708 #define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
<> 128:9bcdf88f62b0 709 #define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
<> 128:9bcdf88f62b0 710 #define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
<> 128:9bcdf88f62b0 711 #define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
<> 128:9bcdf88f62b0 712 #define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
<> 128:9bcdf88f62b0 713
<> 128:9bcdf88f62b0 714 #define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 /**
<> 128:9bcdf88f62b0 717 * @}
<> 128:9bcdf88f62b0 718 */
<> 128:9bcdf88f62b0 719 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 128:9bcdf88f62b0 720
<> 128:9bcdf88f62b0 721 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
<> 128:9bcdf88f62b0 722
<> 128:9bcdf88f62b0 723 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
<> 128:9bcdf88f62b0 724 * @{
<> 128:9bcdf88f62b0 725 */
<> 128:9bcdf88f62b0 726
<> 128:9bcdf88f62b0 727 /* Pages for Cat3, Cat4 & Cat5 devices*/
<> 128:9bcdf88f62b0 728 #define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
<> 128:9bcdf88f62b0 729 #define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
<> 128:9bcdf88f62b0 730 #define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
<> 128:9bcdf88f62b0 731 #define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
<> 128:9bcdf88f62b0 732 #define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
<> 128:9bcdf88f62b0 733 #define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
<> 128:9bcdf88f62b0 734 #define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
<> 128:9bcdf88f62b0 735 #define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
<> 128:9bcdf88f62b0 736 #define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
<> 128:9bcdf88f62b0 737 #define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
<> 128:9bcdf88f62b0 738 #define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
<> 128:9bcdf88f62b0 739 #define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
<> 128:9bcdf88f62b0 740 #define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
<> 128:9bcdf88f62b0 741 #define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
<> 128:9bcdf88f62b0 742 #define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
<> 128:9bcdf88f62b0 743 #define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
<> 128:9bcdf88f62b0 744 #define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector48 */
<> 128:9bcdf88f62b0 745 #define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector49 */
<> 128:9bcdf88f62b0 746 #define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector50 */
<> 128:9bcdf88f62b0 747 #define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector51 */
<> 128:9bcdf88f62b0 748 #define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector52 */
<> 128:9bcdf88f62b0 749 #define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector53 */
<> 128:9bcdf88f62b0 750 #define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector54 */
<> 128:9bcdf88f62b0 751 #define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector55 */
<> 128:9bcdf88f62b0 752 #define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector56 */
<> 128:9bcdf88f62b0 753 #define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector57 */
<> 128:9bcdf88f62b0 754 #define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector58 */
<> 128:9bcdf88f62b0 755 #define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector59 */
<> 128:9bcdf88f62b0 756 #define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector60 */
<> 128:9bcdf88f62b0 757 #define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector61 */
<> 128:9bcdf88f62b0 758 #define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector62 */
<> 128:9bcdf88f62b0 759 #define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector63 */
<> 128:9bcdf88f62b0 760
<> 128:9bcdf88f62b0 761 #define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
<> 128:9bcdf88f62b0 762
<> 128:9bcdf88f62b0 763 /**
<> 128:9bcdf88f62b0 764 * @}
<> 128:9bcdf88f62b0 765 */
<> 128:9bcdf88f62b0 766 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
<> 128:9bcdf88f62b0 767
<> 128:9bcdf88f62b0 768 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
<> 128:9bcdf88f62b0 769 * @{
<> 128:9bcdf88f62b0 770 */
<> 128:9bcdf88f62b0 771 #define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00U) /*!<Erase byte (8-bit) at a specified address.*/
<> 128:9bcdf88f62b0 772 #define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
<> 128:9bcdf88f62b0 773 #define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02U) /*!<Erase a word (32-bit) at a specified address.*/
<> 128:9bcdf88f62b0 774
<> 128:9bcdf88f62b0 775 /**
<> 128:9bcdf88f62b0 776 * @}
<> 128:9bcdf88f62b0 777 */
<> 128:9bcdf88f62b0 778
<> 128:9bcdf88f62b0 779 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
<> 128:9bcdf88f62b0 780 * @{
<> 128:9bcdf88f62b0 781 */
<> 128:9bcdf88f62b0 782 #define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
<> 128:9bcdf88f62b0 783 #define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
<> 128:9bcdf88f62b0 784 #define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
<> 128:9bcdf88f62b0 785 #define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
<> 128:9bcdf88f62b0 786 #define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
<> 128:9bcdf88f62b0 787 #define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
<> 128:9bcdf88f62b0 788
<> 128:9bcdf88f62b0 789 /**
<> 128:9bcdf88f62b0 790 * @}
<> 128:9bcdf88f62b0 791 */
<> 128:9bcdf88f62b0 792
<> 128:9bcdf88f62b0 793 #if defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 794
<> 128:9bcdf88f62b0 795 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
<> 128:9bcdf88f62b0 796 * @{
<> 128:9bcdf88f62b0 797 */
<> 128:9bcdf88f62b0 798
<> 128:9bcdf88f62b0 799 #define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
<> 128:9bcdf88f62b0 800 and this parameter is selected the device will boot from Bank 2
<> 128:9bcdf88f62b0 801 or Bank 1, depending on the activation of the bank */
<> 128:9bcdf88f62b0 802 #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
<> 128:9bcdf88f62b0 803 and this parameter is selected the device will boot from Bank1(Default) */
<> 128:9bcdf88f62b0 804
<> 128:9bcdf88f62b0 805 /**
<> 128:9bcdf88f62b0 806 * @}
<> 128:9bcdf88f62b0 807 */
<> 128:9bcdf88f62b0 808 #endif /* FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 809
<> 128:9bcdf88f62b0 810 /**
<> 128:9bcdf88f62b0 811 * @}
<> 128:9bcdf88f62b0 812 */
<> 128:9bcdf88f62b0 813
<> 128:9bcdf88f62b0 814 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 815
<> 128:9bcdf88f62b0 816 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
<> 128:9bcdf88f62b0 817 * @{
<> 128:9bcdf88f62b0 818 */
<> 128:9bcdf88f62b0 819
<> 128:9bcdf88f62b0 820 /**
<> 128:9bcdf88f62b0 821 * @brief Set the FLASH Latency.
<> 128:9bcdf88f62b0 822 * @param __LATENCY__ FLASH Latency
<> 128:9bcdf88f62b0 823 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 824 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
<> 128:9bcdf88f62b0 825 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
<> 128:9bcdf88f62b0 826 * @retval none
<> 128:9bcdf88f62b0 827 */
<> 128:9bcdf88f62b0 828 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
<> 128:9bcdf88f62b0 829 if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
<> 128:9bcdf88f62b0 830 MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
<> 128:9bcdf88f62b0 831 } while(0)
<> 128:9bcdf88f62b0 832
<> 128:9bcdf88f62b0 833 /**
<> 128:9bcdf88f62b0 834 * @brief Get the FLASH Latency.
<> 128:9bcdf88f62b0 835 * @retval FLASH Latency
<> 128:9bcdf88f62b0 836 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 837 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
<> 128:9bcdf88f62b0 838 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
<> 128:9bcdf88f62b0 839 */
<> 128:9bcdf88f62b0 840 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
<> 128:9bcdf88f62b0 841
<> 128:9bcdf88f62b0 842 /**
<> 128:9bcdf88f62b0 843 * @brief Enable the FLASH 64-bit access.
<> 128:9bcdf88f62b0 844 * @note Read access 64 bit is used.
<> 128:9bcdf88f62b0 845 * @note This bit cannot be written at the same time as the LATENCY and
<> 128:9bcdf88f62b0 846 * PRFTEN bits.
<> 128:9bcdf88f62b0 847 * @retval none
<> 128:9bcdf88f62b0 848 */
<> 128:9bcdf88f62b0 849 #define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
<> 128:9bcdf88f62b0 850
<> 128:9bcdf88f62b0 851 /**
<> 128:9bcdf88f62b0 852 * @brief Disable the FLASH 64-bit access.
<> 128:9bcdf88f62b0 853 * @note Read access 32 bit is used
<> 128:9bcdf88f62b0 854 * @note To reset this bit, the LATENCY should be zero wait state and the
<> 128:9bcdf88f62b0 855 * prefetch off.
<> 128:9bcdf88f62b0 856 * @retval none
<> 128:9bcdf88f62b0 857 */
<> 128:9bcdf88f62b0 858 #define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
<> 128:9bcdf88f62b0 859
<> 128:9bcdf88f62b0 860 /**
<> 128:9bcdf88f62b0 861 * @brief Enable the FLASH prefetch buffer.
<> 128:9bcdf88f62b0 862 * @retval none
<> 128:9bcdf88f62b0 863 */
<> 128:9bcdf88f62b0 864 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
<> 128:9bcdf88f62b0 865 SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
<> 128:9bcdf88f62b0 866 } while(0)
<> 128:9bcdf88f62b0 867
<> 128:9bcdf88f62b0 868 /**
<> 128:9bcdf88f62b0 869 * @brief Disable the FLASH prefetch buffer.
<> 128:9bcdf88f62b0 870 * @retval none
<> 128:9bcdf88f62b0 871 */
<> 128:9bcdf88f62b0 872 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
<> 128:9bcdf88f62b0 873
<> 128:9bcdf88f62b0 874 /**
<> 128:9bcdf88f62b0 875 * @brief Enable the FLASH power down during Sleep mode
<> 128:9bcdf88f62b0 876 * @retval none
<> 128:9bcdf88f62b0 877 */
<> 128:9bcdf88f62b0 878 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 /**
<> 128:9bcdf88f62b0 881 * @brief Disable the FLASH power down during Sleep mode
<> 128:9bcdf88f62b0 882 * @retval none
<> 128:9bcdf88f62b0 883 */
<> 128:9bcdf88f62b0 884 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 128:9bcdf88f62b0 885
<> 128:9bcdf88f62b0 886 /**
<> 128:9bcdf88f62b0 887 * @brief Enable the Flash Run power down mode.
<> 128:9bcdf88f62b0 888 * @note Writing this bit to 0 this bit, automatically the keys are
<> 128:9bcdf88f62b0 889 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 128:9bcdf88f62b0 890 */
<> 128:9bcdf88f62b0 891 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 128:9bcdf88f62b0 892 FLASH->PDKEYR = FLASH_PDKEY2; \
<> 128:9bcdf88f62b0 893 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 128:9bcdf88f62b0 894 } while (0)
<> 128:9bcdf88f62b0 895
<> 128:9bcdf88f62b0 896 /**
<> 128:9bcdf88f62b0 897 * @brief Disable the Flash Run power down mode.
<> 128:9bcdf88f62b0 898 * @note Writing this bit to 0 this bit, automatically the keys are
<> 128:9bcdf88f62b0 899 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 128:9bcdf88f62b0 900 */
<> 128:9bcdf88f62b0 901 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 128:9bcdf88f62b0 902 FLASH->PDKEYR = FLASH_PDKEY2; \
<> 128:9bcdf88f62b0 903 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 128:9bcdf88f62b0 904 } while (0)
<> 128:9bcdf88f62b0 905
<> 128:9bcdf88f62b0 906 /**
<> 128:9bcdf88f62b0 907 * @}
<> 128:9bcdf88f62b0 908 */
<> 128:9bcdf88f62b0 909
<> 128:9bcdf88f62b0 910 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 911
<> 128:9bcdf88f62b0 912 /** @addtogroup FLASHEx_Exported_Functions
<> 128:9bcdf88f62b0 913 * @{
<> 128:9bcdf88f62b0 914 */
<> 128:9bcdf88f62b0 915
<> 128:9bcdf88f62b0 916 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 128:9bcdf88f62b0 917 * @{
<> 128:9bcdf88f62b0 918 */
<> 128:9bcdf88f62b0 919
<> 128:9bcdf88f62b0 920 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 128:9bcdf88f62b0 921 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 128:9bcdf88f62b0 922
<> 128:9bcdf88f62b0 923 /**
<> 128:9bcdf88f62b0 924 * @}
<> 128:9bcdf88f62b0 925 */
<> 128:9bcdf88f62b0 926
<> 128:9bcdf88f62b0 927 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 128:9bcdf88f62b0 928 * @{
<> 128:9bcdf88f62b0 929 */
<> 128:9bcdf88f62b0 930
<> 128:9bcdf88f62b0 931 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 128:9bcdf88f62b0 932 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 128:9bcdf88f62b0 933
<> 128:9bcdf88f62b0 934 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
<> 128:9bcdf88f62b0 935
<> 128:9bcdf88f62b0 936 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
<> 128:9bcdf88f62b0 937 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
<> 128:9bcdf88f62b0 938
<> 128:9bcdf88f62b0 939 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
<> 128:9bcdf88f62b0 940
<> 128:9bcdf88f62b0 941 #if defined(FLASH_OBR_SPRMOD)
<> 128:9bcdf88f62b0 942
<> 128:9bcdf88f62b0 943 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
<> 128:9bcdf88f62b0 944 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
<> 128:9bcdf88f62b0 945
<> 128:9bcdf88f62b0 946 #endif /* FLASH_OBR_SPRMOD */
<> 128:9bcdf88f62b0 947
<> 128:9bcdf88f62b0 948 /**
<> 128:9bcdf88f62b0 949 * @}
<> 128:9bcdf88f62b0 950 */
<> 128:9bcdf88f62b0 951
<> 128:9bcdf88f62b0 952 /** @addtogroup FLASHEx_Exported_Functions_Group3
<> 128:9bcdf88f62b0 953 * @{
<> 128:9bcdf88f62b0 954 */
<> 128:9bcdf88f62b0 955
<> 128:9bcdf88f62b0 956 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
<> 128:9bcdf88f62b0 957 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
<> 128:9bcdf88f62b0 958
<> 128:9bcdf88f62b0 959 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
<> 128:9bcdf88f62b0 960 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
<> 128:9bcdf88f62b0 961 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
<> 128:9bcdf88f62b0 962 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
<> 128:9bcdf88f62b0 963
<> 128:9bcdf88f62b0 964 /**
<> 128:9bcdf88f62b0 965 * @}
<> 128:9bcdf88f62b0 966 */
<> 128:9bcdf88f62b0 967
<> 128:9bcdf88f62b0 968 /**
<> 128:9bcdf88f62b0 969 * @}
<> 128:9bcdf88f62b0 970 */
<> 128:9bcdf88f62b0 971
<> 128:9bcdf88f62b0 972 /**
<> 128:9bcdf88f62b0 973 * @}
<> 128:9bcdf88f62b0 974 */
<> 128:9bcdf88f62b0 975
<> 128:9bcdf88f62b0 976 /**
<> 128:9bcdf88f62b0 977 * @}
<> 128:9bcdf88f62b0 978 */
<> 128:9bcdf88f62b0 979
<> 128:9bcdf88f62b0 980 #ifdef __cplusplus
<> 128:9bcdf88f62b0 981 }
<> 128:9bcdf88f62b0 982 #endif
<> 128:9bcdf88f62b0 983
<> 128:9bcdf88f62b0 984 #endif /* __STM32L1xx_HAL_FLASH_EX_H */
<> 128:9bcdf88f62b0 985
<> 128:9bcdf88f62b0 986 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/