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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_hal_dma.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of DMA HAL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_HAL_DMA_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_HAL_DMA_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx_hal_def.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_HAL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	/** @addtogroup DMA
<>	128:9bcdf88f62b0	54	* @{
<>	128:9bcdf88f62b0	55	*/
<>	128:9bcdf88f62b0	56
<>	128:9bcdf88f62b0	57	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/** @defgroup DMA_Exported_Types DMA Exported Types
<>	128:9bcdf88f62b0	60	* @{
<>	128:9bcdf88f62b0	61	*/
<>	128:9bcdf88f62b0	62
<>	128:9bcdf88f62b0	63	/**
<>	128:9bcdf88f62b0	64	* @brief DMA Configuration Structure definition
<>	128:9bcdf88f62b0	65	*/
<>	128:9bcdf88f62b0	66	typedef struct
<>	128:9bcdf88f62b0	67	{
<>	128:9bcdf88f62b0	68	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	128:9bcdf88f62b0	69	from memory to memory or from peripheral to memory.
<>	128:9bcdf88f62b0	70	This parameter can be a value of @ref DMA_Data_transfer_direction */
<>	128:9bcdf88f62b0	71
<>	128:9bcdf88f62b0	72	uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<>	128:9bcdf88f62b0	73	This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<>	128:9bcdf88f62b0	74
<>	128:9bcdf88f62b0	75	uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<>	128:9bcdf88f62b0	76	This parameter can be a value of @ref DMA_Memory_incremented_mode */
<>	128:9bcdf88f62b0	77
<>	128:9bcdf88f62b0	78	uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<>	128:9bcdf88f62b0	79	This parameter can be a value of @ref DMA_Peripheral_data_size */
<>	128:9bcdf88f62b0	80
<>	128:9bcdf88f62b0	81	uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<>	128:9bcdf88f62b0	82	This parameter can be a value of @ref DMA_Memory_data_size */
<>	128:9bcdf88f62b0	83
<>	128:9bcdf88f62b0	84	uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<>	128:9bcdf88f62b0	85	This parameter can be a value of @ref DMA_mode
<>	128:9bcdf88f62b0	86	@note The circular buffer mode cannot be used if the memory-to-memory
<>	128:9bcdf88f62b0	87	data transfer is configured on the selected Channel */
<>	128:9bcdf88f62b0	88
<>	128:9bcdf88f62b0	89	uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<>	128:9bcdf88f62b0	90	This parameter can be a value of @ref DMA_Priority_level */
<>	128:9bcdf88f62b0	91	} DMA_InitTypeDef;
<>	128:9bcdf88f62b0	92
<>	128:9bcdf88f62b0	93	/**
<>	128:9bcdf88f62b0	94	* @brief HAL DMA State structures definition
<>	128:9bcdf88f62b0	95	*/
<>	128:9bcdf88f62b0	96	typedef enum
<>	128:9bcdf88f62b0	97	{
<>	128:9bcdf88f62b0	98	HAL_DMA_STATE_RESET = 0x00, /!< DMA not yet initialized or disabled /
<>	128:9bcdf88f62b0	99	HAL_DMA_STATE_READY = 0x01, /!< DMA initialized and ready for use /
<>	128:9bcdf88f62b0	100	HAL_DMA_STATE_BUSY = 0x02, /!< DMA process is ongoing /
<>	128:9bcdf88f62b0	101	HAL_DMA_STATE_TIMEOUT = 0x03, /!< DMA timeout state /
<>	128:9bcdf88f62b0	102	}HAL_DMA_StateTypeDef;
<>	128:9bcdf88f62b0	103
<>	128:9bcdf88f62b0	104	/**
<>	128:9bcdf88f62b0	105	* @brief HAL DMA Error Code structure definition
<>	128:9bcdf88f62b0	106	*/
<>	128:9bcdf88f62b0	107	typedef enum
<>	128:9bcdf88f62b0	108	{
<>	128:9bcdf88f62b0	109	HAL_DMA_FULL_TRANSFER = 0x00, /!< Full transfer /
<>	128:9bcdf88f62b0	110	HAL_DMA_HALF_TRANSFER = 0x01 /!< Half Transfer /
<>	128:9bcdf88f62b0	111	}HAL_DMA_LevelCompleteTypeDef;
<>	128:9bcdf88f62b0	112
<>	128:9bcdf88f62b0	113
<>	128:9bcdf88f62b0	114	/**
<>	128:9bcdf88f62b0	115	* @brief HAL DMA Callback ID structure definition
<>	128:9bcdf88f62b0	116	*/
<>	128:9bcdf88f62b0	117	typedef enum
<>	128:9bcdf88f62b0	118	{
<>	128:9bcdf88f62b0	119	HAL_DMA_XFER_CPLT_CB_ID = 0x00, /!< Full transfer /
<>	128:9bcdf88f62b0	120	HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /!< Half transfer /
<>	128:9bcdf88f62b0	121	HAL_DMA_XFER_ERROR_CB_ID = 0x02, /!< Error /
<>	128:9bcdf88f62b0	122	HAL_DMA_XFER_ABORT_CB_ID = 0x03, /!< Abort /
<>	128:9bcdf88f62b0	123	HAL_DMA_XFER_ALL_CB_ID = 0x04 /!< All /
<>	128:9bcdf88f62b0	124
<>	128:9bcdf88f62b0	125	}HAL_DMA_CallbackIDTypeDef;
<>	128:9bcdf88f62b0	126
<>	128:9bcdf88f62b0	127	/**
<>	128:9bcdf88f62b0	128	* @brief DMA handle Structure definition
<>	128:9bcdf88f62b0	129	*/
<>	128:9bcdf88f62b0	130	typedef struct __DMA_HandleTypeDef
<>	128:9bcdf88f62b0	131	{
<>	128:9bcdf88f62b0	132	DMA_Channel_TypeDef Instance; /!< Register base address */
<>	128:9bcdf88f62b0	133
<>	128:9bcdf88f62b0	134	DMA_InitTypeDef Init; /!< DMA communication parameters /
<>	128:9bcdf88f62b0	135
<>	128:9bcdf88f62b0	136	HAL_LockTypeDef Lock; /!< DMA locking object /
<>	128:9bcdf88f62b0	137
<>	128:9bcdf88f62b0	138	__IO HAL_DMA_StateTypeDef State; /!< DMA transfer state /
<>	128:9bcdf88f62b0	139
<>	128:9bcdf88f62b0	140	void Parent; /!< Parent object state */
<>	128:9bcdf88f62b0	141
<>	128:9bcdf88f62b0	142	void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete callback /
<>	128:9bcdf88f62b0	143
<>	128:9bcdf88f62b0	144	void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA Half transfer complete callback /
<>	128:9bcdf88f62b0	145
<>	128:9bcdf88f62b0	146	void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer error callback /
<>	128:9bcdf88f62b0	147
<>	128:9bcdf88f62b0	148	void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer abort callback /
<>	128:9bcdf88f62b0	149
<>	128:9bcdf88f62b0	150	__IO uint32_t ErrorCode; /!< DMA Error code /
<>	128:9bcdf88f62b0	151
<>	128:9bcdf88f62b0	152	DMA_TypeDef DmaBaseAddress; /!< DMA Channel Base Address */
<>	128:9bcdf88f62b0	153
<>	128:9bcdf88f62b0	154	uint32_t ChannelIndex; /!< DMA Channel Index /
<>	128:9bcdf88f62b0	155
<>	128:9bcdf88f62b0	156	} DMA_HandleTypeDef;
<>	128:9bcdf88f62b0	157	/**
<>	128:9bcdf88f62b0	158	* @}
<>	128:9bcdf88f62b0	159	*/
<>	128:9bcdf88f62b0	160
<>	128:9bcdf88f62b0	161	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	162
<>	128:9bcdf88f62b0	163	/** @defgroup DMA_Exported_Constants DMA Exported Constants
<>	128:9bcdf88f62b0	164	* @{
<>	128:9bcdf88f62b0	165	*/
<>	128:9bcdf88f62b0	166
<>	128:9bcdf88f62b0	167	/** @defgroup DMA_Error_Code DMA Error Code
<>	128:9bcdf88f62b0	168	* @{
<>	128:9bcdf88f62b0	169	*/
<>	128:9bcdf88f62b0	170	#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
<>	128:9bcdf88f62b0	171	#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /!< Transfer error /
<>	128:9bcdf88f62b0	172	#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /!< no ongoing transfer /
<>	128:9bcdf88f62b0	173	#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /!< Timeout error /
<>	128:9bcdf88f62b0	174	#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /!< Not supported mode /
<>	128:9bcdf88f62b0	175	/**
<>	128:9bcdf88f62b0	176	* @}
<>	128:9bcdf88f62b0	177	*/
<>	128:9bcdf88f62b0	178
<>	128:9bcdf88f62b0	179	/** @defgroup DMA_request DMA request
<>	128:9bcdf88f62b0	180	* @{
<>	128:9bcdf88f62b0	181	*/
<>	128:9bcdf88f62b0	182	#define DMA_REQUEST_0 ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	183	#define DMA_REQUEST_1 ((uint32_t)0x00000001)
<>	128:9bcdf88f62b0	184	#define DMA_REQUEST_2 ((uint32_t)0x00000002)
<>	128:9bcdf88f62b0	185	#define DMA_REQUEST_3 ((uint32_t)0x00000003)
<>	128:9bcdf88f62b0	186	#define DMA_REQUEST_4 ((uint32_t)0x00000004)
<>	128:9bcdf88f62b0	187	#define DMA_REQUEST_5 ((uint32_t)0x00000005)
<>	128:9bcdf88f62b0	188	#define DMA_REQUEST_6 ((uint32_t)0x00000006)
<>	128:9bcdf88f62b0	189	#define DMA_REQUEST_7 ((uint32_t)0x00000007)
<>	128:9bcdf88f62b0	190
<>	128:9bcdf88f62b0	191	/**
<>	128:9bcdf88f62b0	192	* @}
<>	128:9bcdf88f62b0	193	*/
<>	128:9bcdf88f62b0	194
<>	128:9bcdf88f62b0	195	/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<>	128:9bcdf88f62b0	196	* @{
<>	128:9bcdf88f62b0	197	*/
<>	128:9bcdf88f62b0	198	#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /!< Peripheral to memory direction /
<>	128:9bcdf88f62b0	199	#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /!< Memory to peripheral direction /
<>	128:9bcdf88f62b0	200	#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /!< Memory to memory direction /
<>	128:9bcdf88f62b0	201
<>	128:9bcdf88f62b0	202	/**
<>	128:9bcdf88f62b0	203	* @}
<>	128:9bcdf88f62b0	204	*/
<>	128:9bcdf88f62b0	205
<>	128:9bcdf88f62b0	206	/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<>	128:9bcdf88f62b0	207	* @{
<>	128:9bcdf88f62b0	208	*/
<>	128:9bcdf88f62b0	209	#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /!< Peripheral increment mode Enable /
<>	128:9bcdf88f62b0	210	#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /!< Peripheral increment mode Disable /
<>	128:9bcdf88f62b0	211	/**
<>	128:9bcdf88f62b0	212	* @}
<>	128:9bcdf88f62b0	213	*/
<>	128:9bcdf88f62b0	214
<>	128:9bcdf88f62b0	215	/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<>	128:9bcdf88f62b0	216	* @{
<>	128:9bcdf88f62b0	217	*/
<>	128:9bcdf88f62b0	218	#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /!< Memory increment mode Enable /
<>	128:9bcdf88f62b0	219	#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /!< Memory increment mode Disable /
<>	128:9bcdf88f62b0	220	/**
<>	128:9bcdf88f62b0	221	* @}
<>	128:9bcdf88f62b0	222	*/
<>	128:9bcdf88f62b0	223
<>	128:9bcdf88f62b0	224	/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<>	128:9bcdf88f62b0	225	* @{
<>	128:9bcdf88f62b0	226	*/
<>	128:9bcdf88f62b0	227	#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /!< Peripheral data alignment: Byte /
<>	128:9bcdf88f62b0	228	#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /!< Peripheral data alignment: HalfWord /
<>	128:9bcdf88f62b0	229	#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /!< Peripheral data alignment: Word /
<>	128:9bcdf88f62b0	230	/**
<>	128:9bcdf88f62b0	231	* @}
<>	128:9bcdf88f62b0	232	*/
<>	128:9bcdf88f62b0	233
<>	128:9bcdf88f62b0	234	/** @defgroup DMA_Memory_data_size DMA Memory data size
<>	128:9bcdf88f62b0	235	* @{
<>	128:9bcdf88f62b0	236	*/
<>	128:9bcdf88f62b0	237	#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /!< Memory data alignment: Byte /
<>	128:9bcdf88f62b0	238	#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /!< Memory data alignment: HalfWord /
<>	128:9bcdf88f62b0	239	#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /!< Memory data alignment: Word /
<>	128:9bcdf88f62b0	240	/**
<>	128:9bcdf88f62b0	241	* @}
<>	128:9bcdf88f62b0	242	*/
<>	128:9bcdf88f62b0	243
<>	128:9bcdf88f62b0	244	/** @defgroup DMA_mode DMA mode
<>	128:9bcdf88f62b0	245	* @{
<>	128:9bcdf88f62b0	246	*/
<>	128:9bcdf88f62b0	247	#define DMA_NORMAL ((uint32_t)0x00000000) /!< Normal mode /
<>	128:9bcdf88f62b0	248	#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /!< Circular mode /
<>	128:9bcdf88f62b0	249	/**
<>	128:9bcdf88f62b0	250	* @}
<>	128:9bcdf88f62b0	251	*/
<>	128:9bcdf88f62b0	252
<>	128:9bcdf88f62b0	253	/** @defgroup DMA_Priority_level DMA Priority level
<>	128:9bcdf88f62b0	254	* @{
<>	128:9bcdf88f62b0	255	*/
<>	128:9bcdf88f62b0	256	#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /!< Priority level : Low /
<>	128:9bcdf88f62b0	257	#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /!< Priority level : Medium /
<>	128:9bcdf88f62b0	258	#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /!< Priority level : High /
<>	128:9bcdf88f62b0	259	#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /!< Priority level : Very_High /
<>	128:9bcdf88f62b0	260	/**
<>	128:9bcdf88f62b0	261	* @}
<>	128:9bcdf88f62b0	262	*/
<>	128:9bcdf88f62b0	263
<>	128:9bcdf88f62b0	264
<>	128:9bcdf88f62b0	265	/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<>	128:9bcdf88f62b0	266	* @{
<>	128:9bcdf88f62b0	267	*/
<>	128:9bcdf88f62b0	268	#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<>	128:9bcdf88f62b0	269	#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<>	128:9bcdf88f62b0	270	#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<>	128:9bcdf88f62b0	271	/**
<>	128:9bcdf88f62b0	272	* @}
<>	128:9bcdf88f62b0	273	*/
<>	128:9bcdf88f62b0	274
<>	128:9bcdf88f62b0	275	/** @defgroup DMA_flag_definitions DMA flag definitions
<>	128:9bcdf88f62b0	276	* @{
<>	128:9bcdf88f62b0	277	*/
<>	128:9bcdf88f62b0	278	#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
<>	128:9bcdf88f62b0	279	#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
<>	128:9bcdf88f62b0	280	#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
<>	128:9bcdf88f62b0	281	#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
<>	128:9bcdf88f62b0	282	#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
<>	128:9bcdf88f62b0	283	#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
<>	128:9bcdf88f62b0	284	#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
<>	128:9bcdf88f62b0	285	#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
<>	128:9bcdf88f62b0	286	#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
<>	128:9bcdf88f62b0	287	#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
<>	128:9bcdf88f62b0	288	#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
<>	128:9bcdf88f62b0	289	#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
<>	128:9bcdf88f62b0	290	#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
<>	128:9bcdf88f62b0	291	#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
<>	128:9bcdf88f62b0	292	#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
<>	128:9bcdf88f62b0	293	#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
<>	128:9bcdf88f62b0	294	#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
<>	128:9bcdf88f62b0	295	#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
<>	128:9bcdf88f62b0	296	#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
<>	128:9bcdf88f62b0	297	#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
<>	128:9bcdf88f62b0	298	#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
<>	128:9bcdf88f62b0	299	#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
<>	128:9bcdf88f62b0	300	#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
<>	128:9bcdf88f62b0	301	#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
<>	128:9bcdf88f62b0	302	#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
<>	128:9bcdf88f62b0	303	#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
<>	128:9bcdf88f62b0	304	#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
<>	128:9bcdf88f62b0	305	#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
<>	128:9bcdf88f62b0	306	/**
<>	128:9bcdf88f62b0	307	* @}
<>	128:9bcdf88f62b0	308	*/
<>	128:9bcdf88f62b0	309
<>	128:9bcdf88f62b0	310	/**
<>	128:9bcdf88f62b0	311	* @}
<>	128:9bcdf88f62b0	312	*/
<>	128:9bcdf88f62b0	313
<>	128:9bcdf88f62b0	314	/* Exported macros -----------------------------------------------------------*/
<>	128:9bcdf88f62b0	315	/** @defgroup DMA_Exported_Macros DMA Exported Macros
<>	128:9bcdf88f62b0	316	* @{
<>	128:9bcdf88f62b0	317	*/
<>	128:9bcdf88f62b0	318
<>	128:9bcdf88f62b0	319	/** @brief Reset DMA handle state
<>	128:9bcdf88f62b0	320	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	321	* @retval None
<>	128:9bcdf88f62b0	322	*/
<>	128:9bcdf88f62b0	323	#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<>	128:9bcdf88f62b0	324
<>	128:9bcdf88f62b0	325	/**
<>	128:9bcdf88f62b0	326	* @brief Enable the specified DMA Channel.
<>	128:9bcdf88f62b0	327	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	328	* @retval None
<>	128:9bcdf88f62b0	329	*/
<>	128:9bcdf88f62b0	330	#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR \|= DMA_CCR_EN)
<>	128:9bcdf88f62b0	331
<>	128:9bcdf88f62b0	332	/**
<>	128:9bcdf88f62b0	333	* @brief Disable the specified DMA Channel.
<>	128:9bcdf88f62b0	334	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	335	* @retval None
<>	128:9bcdf88f62b0	336	*/
<>	128:9bcdf88f62b0	337	#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
<>	128:9bcdf88f62b0	338
<>	128:9bcdf88f62b0	339
<>	128:9bcdf88f62b0	340	/* Interrupt & Flag management */
<>	128:9bcdf88f62b0	341	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| \
<>	128:9bcdf88f62b0	342	defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| \
<>	128:9bcdf88f62b0	343	defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	344
<>	128:9bcdf88f62b0	345	/**
<>	128:9bcdf88f62b0	346	* @brief Return the current DMA Channel transfer complete flag.
<>	128:9bcdf88f62b0	347	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	348	* @retval The specified transfer complete flag index.
<>	128:9bcdf88f62b0	349	*/
<>	128:9bcdf88f62b0	350
<>	128:9bcdf88f62b0	351	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<>	128:9bcdf88f62b0	352	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<>	128:9bcdf88f62b0	353	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
<>	128:9bcdf88f62b0	354	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<>	128:9bcdf88f62b0	355	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
<>	128:9bcdf88f62b0	356	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<>	128:9bcdf88f62b0	357	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
<>	128:9bcdf88f62b0	358	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<>	128:9bcdf88f62b0	359	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
<>	128:9bcdf88f62b0	360	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<>	128:9bcdf88f62b0	361	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
<>	128:9bcdf88f62b0	362	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<>	128:9bcdf88f62b0	363	DMA_FLAG_TC7)
<>	128:9bcdf88f62b0	364
<>	128:9bcdf88f62b0	365	/**
<>	128:9bcdf88f62b0	366	* @brief Return the current DMA Channel half transfer complete flag.
<>	128:9bcdf88f62b0	367	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	368	* @retval The specified half transfer complete flag index.
<>	128:9bcdf88f62b0	369	*/
<>	128:9bcdf88f62b0	370	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	371	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<>	128:9bcdf88f62b0	372	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
<>	128:9bcdf88f62b0	373	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<>	128:9bcdf88f62b0	374	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
<>	128:9bcdf88f62b0	375	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<>	128:9bcdf88f62b0	376	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
<>	128:9bcdf88f62b0	377	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<>	128:9bcdf88f62b0	378	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
<>	128:9bcdf88f62b0	379	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<>	128:9bcdf88f62b0	380	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
<>	128:9bcdf88f62b0	381	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<>	128:9bcdf88f62b0	382	DMA_FLAG_HT7)
<>	128:9bcdf88f62b0	383
<>	128:9bcdf88f62b0	384	/**
<>	128:9bcdf88f62b0	385	* @brief Return the current DMA Channel transfer error flag.
<>	128:9bcdf88f62b0	386	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	387	* @retval The specified transfer error flag index.
<>	128:9bcdf88f62b0	388	*/
<>	128:9bcdf88f62b0	389	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	390	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<>	128:9bcdf88f62b0	391	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
<>	128:9bcdf88f62b0	392	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<>	128:9bcdf88f62b0	393	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
<>	128:9bcdf88f62b0	394	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<>	128:9bcdf88f62b0	395	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
<>	128:9bcdf88f62b0	396	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<>	128:9bcdf88f62b0	397	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
<>	128:9bcdf88f62b0	398	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<>	128:9bcdf88f62b0	399	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
<>	128:9bcdf88f62b0	400	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<>	128:9bcdf88f62b0	401	DMA_FLAG_TE7)
<>	128:9bcdf88f62b0	402
<>	128:9bcdf88f62b0	403	/**
<>	128:9bcdf88f62b0	404	* @brief Return the current DMA Channel Global interrupt flag.
<>	128:9bcdf88f62b0	405	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	406	* @retval The specified transfer error flag index.
<>	128:9bcdf88f62b0	407	*/
<>	128:9bcdf88f62b0	408	#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	409	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<>	128:9bcdf88f62b0	410	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
<>	128:9bcdf88f62b0	411	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<>	128:9bcdf88f62b0	412	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
<>	128:9bcdf88f62b0	413	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<>	128:9bcdf88f62b0	414	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
<>	128:9bcdf88f62b0	415	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<>	128:9bcdf88f62b0	416	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
<>	128:9bcdf88f62b0	417	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
<>	128:9bcdf88f62b0	418	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
<>	128:9bcdf88f62b0	419	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
<>	128:9bcdf88f62b0	420	DMA_ISR_GIF7)
<>	128:9bcdf88f62b0	421
<>	128:9bcdf88f62b0	422	/**
<>	128:9bcdf88f62b0	423	* @brief Get the DMA Channel pending flags.
<>	128:9bcdf88f62b0	424	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	425	* @param __FLAG__: Get the specified flag.
<>	128:9bcdf88f62b0	426	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	427	* @arg DMA_FLAG_TCx: Transfer complete flag
<>	128:9bcdf88f62b0	428	* @arg DMA_FLAG_HTx: Half transfer complete flag
<>	128:9bcdf88f62b0	429	* @arg DMA_FLAG_TEx: Transfer error flag
<>	128:9bcdf88f62b0	430	* @arg DMA_FLAG_GLx: Global interrupt flag
<>	128:9bcdf88f62b0	431	* Where x can be from 1 to 7 to select the DMA Channel x flag.
<>	128:9bcdf88f62b0	432	* @retval The state of FLAG (SET or RESET).
<>	128:9bcdf88f62b0	433	*/
<>	128:9bcdf88f62b0	434	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
<>	128:9bcdf88f62b0	435	(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
<>	128:9bcdf88f62b0	436
<>	128:9bcdf88f62b0	437	/**
<>	128:9bcdf88f62b0	438	* @brief Clear the DMA Channel pending flags.
<>	128:9bcdf88f62b0	439	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	440	* @param __FLAG__: specifies the flag to clear.
<>	128:9bcdf88f62b0	441	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	442	* @arg DMA_FLAG_TCx: Transfer complete flag
<>	128:9bcdf88f62b0	443	* @arg DMA_FLAG_HTx: Half transfer complete flag
<>	128:9bcdf88f62b0	444	* @arg DMA_FLAG_TEx: Transfer error flag
<>	128:9bcdf88f62b0	445	* @arg DMA_FLAG_GLx: Global interrupt flag
<>	128:9bcdf88f62b0	446	* Where x can be from 1 to 7 to select the DMA Channel x flag.
<>	128:9bcdf88f62b0	447	* @retval None
<>	128:9bcdf88f62b0	448	*/
<>	128:9bcdf88f62b0	449	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
<>	128:9bcdf88f62b0	450	(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
<>	128:9bcdf88f62b0	451
<>	128:9bcdf88f62b0	452	#else
<>	128:9bcdf88f62b0	453	/**
<>	128:9bcdf88f62b0	454	* @brief Return the current DMA Channel transfer complete flag.
<>	128:9bcdf88f62b0	455	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	456	* @retval The specified transfer complete flag index.
<>	128:9bcdf88f62b0	457	*/
<>	128:9bcdf88f62b0	458
<>	128:9bcdf88f62b0	459	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<>	128:9bcdf88f62b0	460	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<>	128:9bcdf88f62b0	461	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<>	128:9bcdf88f62b0	462	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<>	128:9bcdf88f62b0	463	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<>	128:9bcdf88f62b0	464	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<>	128:9bcdf88f62b0	465	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<>	128:9bcdf88f62b0	466	DMA_FLAG_TC7)
<>	128:9bcdf88f62b0	467
<>	128:9bcdf88f62b0	468	/**
<>	128:9bcdf88f62b0	469	* @brief Return the current DMA Channel half transfer complete flag.
<>	128:9bcdf88f62b0	470	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	471	* @retval The specified half transfer complete flag index.
<>	128:9bcdf88f62b0	472	*/
<>	128:9bcdf88f62b0	473	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	474	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<>	128:9bcdf88f62b0	475	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<>	128:9bcdf88f62b0	476	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<>	128:9bcdf88f62b0	477	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<>	128:9bcdf88f62b0	478	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<>	128:9bcdf88f62b0	479	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<>	128:9bcdf88f62b0	480	DMA_FLAG_HT7)
<>	128:9bcdf88f62b0	481
<>	128:9bcdf88f62b0	482	/**
<>	128:9bcdf88f62b0	483	* @brief Return the current DMA Channel transfer error flag.
<>	128:9bcdf88f62b0	484	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	485	* @retval The specified transfer error flag index.
<>	128:9bcdf88f62b0	486	*/
<>	128:9bcdf88f62b0	487	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	488	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<>	128:9bcdf88f62b0	489	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<>	128:9bcdf88f62b0	490	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<>	128:9bcdf88f62b0	491	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<>	128:9bcdf88f62b0	492	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<>	128:9bcdf88f62b0	493	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<>	128:9bcdf88f62b0	494	DMA_FLAG_TE7)
<>	128:9bcdf88f62b0	495
<>	128:9bcdf88f62b0	496	/**
<>	128:9bcdf88f62b0	497	* @brief Return the current DMA Channel Global interrupt flag.
<>	128:9bcdf88f62b0	498	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	499	* @retval The specified transfer error flag index.
<>	128:9bcdf88f62b0	500	*/
<>	128:9bcdf88f62b0	501	#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<>	128:9bcdf88f62b0	502	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<>	128:9bcdf88f62b0	503	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<>	128:9bcdf88f62b0	504	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<>	128:9bcdf88f62b0	505	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<>	128:9bcdf88f62b0	506	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
<>	128:9bcdf88f62b0	507	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
<>	128:9bcdf88f62b0	508	DMA_ISR_GIF7)
<>	128:9bcdf88f62b0	509
<>	128:9bcdf88f62b0	510	/**
<>	128:9bcdf88f62b0	511	* @brief Get the DMA Channel pending flags.
<>	128:9bcdf88f62b0	512	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	513	* @param __FLAG__: Get the specified flag.
<>	128:9bcdf88f62b0	514	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	515	* @arg DMA_FLAG_TCx: Transfer complete flag
<>	128:9bcdf88f62b0	516	* @arg DMA_FLAG_HTx: Half transfer complete flag
<>	128:9bcdf88f62b0	517	* @arg DMA_FLAG_TEx: Transfer error flag
<>	128:9bcdf88f62b0	518	* @arg DMA_FLAG_GLx: Global interrupt flag
<>	128:9bcdf88f62b0	519	* Where x can be from 1 to 7 to select the DMA Channel x flag.
<>	128:9bcdf88f62b0	520	* @retval The state of FLAG (SET or RESET).
<>	128:9bcdf88f62b0	521	*/
<>	128:9bcdf88f62b0	522	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<>	128:9bcdf88f62b0	523
<>	128:9bcdf88f62b0	524	/**
<>	128:9bcdf88f62b0	525	* @brief Clear the DMA Channel pending flags.
<>	128:9bcdf88f62b0	526	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	527	* @param __FLAG__: specifies the flag to clear.
<>	128:9bcdf88f62b0	528	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	529	* @arg DMA_FLAG_TCx: Transfer complete flag
<>	128:9bcdf88f62b0	530	* @arg DMA_FLAG_HTx: Half transfer complete flag
<>	128:9bcdf88f62b0	531	* @arg DMA_FLAG_TEx: Transfer error flag
<>	128:9bcdf88f62b0	532	* @arg DMA_FLAG_GLx: Global interrupt flag
<>	128:9bcdf88f62b0	533	* Where x can be from 1 to 7 to select the DMA Channel x flag.
<>	128:9bcdf88f62b0	534	* @retval None
<>	128:9bcdf88f62b0	535	*/
<>	128:9bcdf88f62b0	536	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<>	128:9bcdf88f62b0	537
<>	128:9bcdf88f62b0	538	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	539
<>	128:9bcdf88f62b0	540	/**
<>	128:9bcdf88f62b0	541	* @brief Enable the specified DMA Channel interrupts.
<>	128:9bcdf88f62b0	542	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	543	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<>	128:9bcdf88f62b0	544	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	545	* @arg DMA_IT_TC: Transfer complete interrupt mask
<>	128:9bcdf88f62b0	546	* @arg DMA_IT_HT: Half transfer complete interrupt mask
<>	128:9bcdf88f62b0	547	* @arg DMA_IT_TE: Transfer error interrupt mask
<>	128:9bcdf88f62b0	548	* @retval None
<>	128:9bcdf88f62b0	549	*/
<>	128:9bcdf88f62b0	550	#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR \|= (__INTERRUPT__))
<>	128:9bcdf88f62b0	551
<>	128:9bcdf88f62b0	552	/**
<>	128:9bcdf88f62b0	553	* @brief Disable the specified DMA Channel interrupts.
<>	128:9bcdf88f62b0	554	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	555	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<>	128:9bcdf88f62b0	556	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	557	* @arg DMA_IT_TC: Transfer complete interrupt mask
<>	128:9bcdf88f62b0	558	* @arg DMA_IT_HT: Half transfer complete interrupt mask
<>	128:9bcdf88f62b0	559	* @arg DMA_IT_TE: Transfer error interrupt mask
<>	128:9bcdf88f62b0	560	* @retval None
<>	128:9bcdf88f62b0	561	*/
<>	128:9bcdf88f62b0	562	#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
<>	128:9bcdf88f62b0	563
<>	128:9bcdf88f62b0	564	/**
<>	128:9bcdf88f62b0	565	* @brief Check whether the specified DMA Channel interrupt is enabled or not.
<>	128:9bcdf88f62b0	566	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	567	* @param __INTERRUPT__: specifies the DMA interrupt source to check.
<>	128:9bcdf88f62b0	568	* This parameter can be one of the following values:
<>	128:9bcdf88f62b0	569	* @arg DMA_IT_TC: Transfer complete interrupt mask
<>	128:9bcdf88f62b0	570	* @arg DMA_IT_HT: Half transfer complete interrupt mask
<>	128:9bcdf88f62b0	571	* @arg DMA_IT_TE: Transfer error interrupt mask
<>	128:9bcdf88f62b0	572	* @retval The state of DMA_IT (SET or RESET).
<>	128:9bcdf88f62b0	573	*/
<>	128:9bcdf88f62b0	574	#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
<>	128:9bcdf88f62b0	575
<>	128:9bcdf88f62b0	576	/**
<>	128:9bcdf88f62b0	577	* @brief Return the number of remaining data units in the current DMA Channel transfer.
<>	128:9bcdf88f62b0	578	* @param __HANDLE__: DMA handle
<>	128:9bcdf88f62b0	579	* @retval The number of remaining data units in the current DMA Channel transfer.
<>	128:9bcdf88f62b0	580	*/
<>	128:9bcdf88f62b0	581	#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<>	128:9bcdf88f62b0	582
<>	128:9bcdf88f62b0	583	/**
<>	128:9bcdf88f62b0	584	* @}
<>	128:9bcdf88f62b0	585	*/
<>	128:9bcdf88f62b0	586
<>	128:9bcdf88f62b0	587	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	588
<>	128:9bcdf88f62b0	589	/** @addtogroup DMA_Exported_Functions
<>	128:9bcdf88f62b0	590	* @{
<>	128:9bcdf88f62b0	591	*/
<>	128:9bcdf88f62b0	592
<>	128:9bcdf88f62b0	593	/** @addtogroup DMA_Exported_Functions_Group1
<>	128:9bcdf88f62b0	594	* @{
<>	128:9bcdf88f62b0	595	*/
<>	128:9bcdf88f62b0	596	/* Initialization and de-initialization functions *****************************/
<>	128:9bcdf88f62b0	597	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	598	HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	599	/**
<>	128:9bcdf88f62b0	600	* @}
<>	128:9bcdf88f62b0	601	*/
<>	128:9bcdf88f62b0	602
<>	128:9bcdf88f62b0	603	/** @addtogroup DMA_Exported_Functions_Group2
<>	128:9bcdf88f62b0	604	* @{
<>	128:9bcdf88f62b0	605	*/
<>	128:9bcdf88f62b0	606	/* IO operation functions *****************************************************/
<>	128:9bcdf88f62b0	607	HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<>	128:9bcdf88f62b0	608	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<>	128:9bcdf88f62b0	609	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	610	HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	611	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<>	128:9bcdf88f62b0	612	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	613	HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void ( pCallback)( DMA_HandleTypeDef * _hdma));
<>	128:9bcdf88f62b0	614	HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<>	128:9bcdf88f62b0	615
<>	128:9bcdf88f62b0	616	/**
<>	128:9bcdf88f62b0	617	* @}
<>	128:9bcdf88f62b0	618	*/
<>	128:9bcdf88f62b0	619
<>	128:9bcdf88f62b0	620	/** @addtogroup DMA_Exported_Functions_Group3
<>	128:9bcdf88f62b0	621	* @{
<>	128:9bcdf88f62b0	622	*/
<>	128:9bcdf88f62b0	623	/* Peripheral State and Error functions ***************************************/
<>	128:9bcdf88f62b0	624	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	625	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<>	128:9bcdf88f62b0	626	/**
<>	128:9bcdf88f62b0	627	* @}
<>	128:9bcdf88f62b0	628	*/
<>	128:9bcdf88f62b0	629
<>	128:9bcdf88f62b0	630	/**
<>	128:9bcdf88f62b0	631	* @}
<>	128:9bcdf88f62b0	632	*/
<>	128:9bcdf88f62b0	633
<>	128:9bcdf88f62b0	634	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	635	/** @defgroup DMA_Private_Macros DMA Private Macros
<>	128:9bcdf88f62b0	636	* @{
<>	128:9bcdf88f62b0	637	*/
<>	128:9bcdf88f62b0	638
<>	128:9bcdf88f62b0	639	#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) \|\| \
<>	128:9bcdf88f62b0	640	((DIRECTION) == DMA_MEMORY_TO_PERIPH) \|\| \
<>	128:9bcdf88f62b0	641	((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<>	128:9bcdf88f62b0	642
<>	128:9bcdf88f62b0	643	#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
<>	128:9bcdf88f62b0	644
<>	128:9bcdf88f62b0	645	#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) \|\| \
<>	128:9bcdf88f62b0	646	((STATE) == DMA_PINC_DISABLE))
<>	128:9bcdf88f62b0	647
<>	128:9bcdf88f62b0	648	#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) \|\| \
<>	128:9bcdf88f62b0	649	((STATE) == DMA_MINC_DISABLE))
<>	128:9bcdf88f62b0	650
<>	128:9bcdf88f62b0	651	#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) \|\| \
<>	128:9bcdf88f62b0	652	((REQUEST) == DMA_REQUEST_1) \|\| \
<>	128:9bcdf88f62b0	653	((REQUEST) == DMA_REQUEST_2) \|\| \
<>	128:9bcdf88f62b0	654	((REQUEST) == DMA_REQUEST_3) \|\| \
<>	128:9bcdf88f62b0	655	((REQUEST) == DMA_REQUEST_4) \|\| \
<>	128:9bcdf88f62b0	656	((REQUEST) == DMA_REQUEST_5) \|\| \
<>	128:9bcdf88f62b0	657	((REQUEST) == DMA_REQUEST_6) \|\| \
<>	128:9bcdf88f62b0	658	((REQUEST) == DMA_REQUEST_7))
<>	128:9bcdf88f62b0	659	#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) \|\| \
<>	128:9bcdf88f62b0	660	((SIZE) == DMA_PDATAALIGN_HALFWORD) \|\| \
<>	128:9bcdf88f62b0	661	((SIZE) == DMA_PDATAALIGN_WORD))
<>	128:9bcdf88f62b0	662
<>	128:9bcdf88f62b0	663	#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) \|\| \
<>	128:9bcdf88f62b0	664	((SIZE) == DMA_MDATAALIGN_HALFWORD) \|\| \
<>	128:9bcdf88f62b0	665	((SIZE) == DMA_MDATAALIGN_WORD ))
<>	128:9bcdf88f62b0	666
<>	128:9bcdf88f62b0	667	#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) \|\| \
<>	128:9bcdf88f62b0	668	((MODE) == DMA_CIRCULAR))
<>	128:9bcdf88f62b0	669
<>	128:9bcdf88f62b0	670	#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) \|\| \
<>	128:9bcdf88f62b0	671	((PRIORITY) == DMA_PRIORITY_MEDIUM) \|\| \
<>	128:9bcdf88f62b0	672	((PRIORITY) == DMA_PRIORITY_HIGH) \|\| \
<>	128:9bcdf88f62b0	673	((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<>	128:9bcdf88f62b0	674
<>	128:9bcdf88f62b0	675	/**
<>	128:9bcdf88f62b0	676	* @}
<>	128:9bcdf88f62b0	677	*/
<>	128:9bcdf88f62b0	678
<>	128:9bcdf88f62b0	679	/* Private functions ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	680
<>	128:9bcdf88f62b0	681	/**
<>	128:9bcdf88f62b0	682	* @}
<>	128:9bcdf88f62b0	683	*/
<>	128:9bcdf88f62b0	684
<>	128:9bcdf88f62b0	685	/**
<>	128:9bcdf88f62b0	686	* @}
<>	128:9bcdf88f62b0	687	*/
<>	128:9bcdf88f62b0	688
<>	128:9bcdf88f62b0	689	#ifdef __cplusplus
<>	128:9bcdf88f62b0	690	}
<>	128:9bcdf88f62b0	691	#endif
<>	128:9bcdf88f62b0	692
<>	128:9bcdf88f62b0	693	#endif /* __STM32L1xx_HAL_DMA_H */
<>	128:9bcdf88f62b0	694
<>	128:9bcdf88f62b0	695	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/