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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_dac.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of DAC HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_DAC_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_DAC_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup DAC
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /** @defgroup DAC_Exported_Types DAC Exported Types
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /**
<> 128:9bcdf88f62b0 64 * @brief HAL State structures definition
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66 typedef enum
<> 128:9bcdf88f62b0 67 {
<> 128:9bcdf88f62b0 68 HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
<> 128:9bcdf88f62b0 69 HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
<> 128:9bcdf88f62b0 70 HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
<> 128:9bcdf88f62b0 71 HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
<> 128:9bcdf88f62b0 72 HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 }HAL_DAC_StateTypeDef;
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 /**
<> 128:9bcdf88f62b0 77 * @brief DAC handle Structure definition
<> 128:9bcdf88f62b0 78 */
<> 128:9bcdf88f62b0 79 typedef struct
<> 128:9bcdf88f62b0 80 {
<> 128:9bcdf88f62b0 81 DAC_TypeDef *Instance; /*!< Register base address */
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 HAL_LockTypeDef Lock; /*!< DAC locking object */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
<> 128:9bcdf88f62b0 90
<> 128:9bcdf88f62b0 91 __IO uint32_t ErrorCode; /*!< DAC Error code */
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 }DAC_HandleTypeDef;
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 /**
<> 128:9bcdf88f62b0 96 * @brief DAC Configuration regular Channel structure definition
<> 128:9bcdf88f62b0 97 */
<> 128:9bcdf88f62b0 98 typedef struct
<> 128:9bcdf88f62b0 99 {
<> 128:9bcdf88f62b0 100 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
<> 128:9bcdf88f62b0 101 This parameter can be a value of @ref DAC_trigger_selection */
<> 128:9bcdf88f62b0 102
<> 128:9bcdf88f62b0 103 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
<> 128:9bcdf88f62b0 104 This parameter can be a value of @ref DAC_output_buffer */
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 }DAC_ChannelConfTypeDef;
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 /**
<> 128:9bcdf88f62b0 109 * @}
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 113
<> 128:9bcdf88f62b0 114 /** @defgroup DAC_Exported_Constants DAC Exported Constants
<> 128:9bcdf88f62b0 115 * @{
<> 128:9bcdf88f62b0 116 */
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 /** @defgroup DAC_Error_Code DAC Error Code
<> 128:9bcdf88f62b0 119 * @{
<> 128:9bcdf88f62b0 120 */
<> 128:9bcdf88f62b0 121 #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
<> 128:9bcdf88f62b0 122 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
<> 128:9bcdf88f62b0 123 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
<> 128:9bcdf88f62b0 124 #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
<> 128:9bcdf88f62b0 125 /**
<> 128:9bcdf88f62b0 126 * @}
<> 128:9bcdf88f62b0 127 */
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 /** @defgroup DAC_trigger_selection DAC trigger selection
<> 128:9bcdf88f62b0 130 * @{
<> 128:9bcdf88f62b0 131 */
<> 128:9bcdf88f62b0 132 #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
<> 128:9bcdf88f62b0 133 has been loaded, and not by external trigger */
<> 128:9bcdf88f62b0 134 #define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 135 #define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 136 #define DAC_TRIGGER_T9_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 137 #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 138 #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 139 #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
<> 128:9bcdf88f62b0 140 #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 /**
<> 128:9bcdf88f62b0 143 * @}
<> 128:9bcdf88f62b0 144 */
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 /** @defgroup DAC_output_buffer DAC output buffer
<> 128:9bcdf88f62b0 147 * @{
<> 128:9bcdf88f62b0 148 */
<> 128:9bcdf88f62b0 149 #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 150 #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /**
<> 128:9bcdf88f62b0 153 * @}
<> 128:9bcdf88f62b0 154 */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /** @defgroup DAC_Channel_selection DAC Channel selection
<> 128:9bcdf88f62b0 157 * @{
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159 #define DAC_CHANNEL_1 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 160 #define DAC_CHANNEL_2 ((uint32_t)0x00000010)
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /**
<> 128:9bcdf88f62b0 163 * @}
<> 128:9bcdf88f62b0 164 */
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 /** @defgroup DAC_data_alignement DAC data alignement
<> 128:9bcdf88f62b0 167 * @{
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169 #define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 170 #define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
<> 128:9bcdf88f62b0 171 #define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 /**
<> 128:9bcdf88f62b0 174 * @}
<> 128:9bcdf88f62b0 175 */
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177 /** @defgroup DAC_flags_definition DAC flags definition
<> 128:9bcdf88f62b0 178 * @{
<> 128:9bcdf88f62b0 179 */
<> 128:9bcdf88f62b0 180 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 128:9bcdf88f62b0 181 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /**
<> 128:9bcdf88f62b0 184 * @}
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186
<> 128:9bcdf88f62b0 187 /** @defgroup DAC_IT_definition DAC IT definition
<> 128:9bcdf88f62b0 188 * @{
<> 128:9bcdf88f62b0 189 */
<> 128:9bcdf88f62b0 190 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 128:9bcdf88f62b0 191 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /**
<> 128:9bcdf88f62b0 194 * @}
<> 128:9bcdf88f62b0 195 */
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 /**
<> 128:9bcdf88f62b0 198 * @}
<> 128:9bcdf88f62b0 199 */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 202
<> 128:9bcdf88f62b0 203 /** @defgroup DAC_Exported_Macros DAC Exported Macros
<> 128:9bcdf88f62b0 204 * @{
<> 128:9bcdf88f62b0 205 */
<> 128:9bcdf88f62b0 206
<> 128:9bcdf88f62b0 207 /** @brief Reset DAC handle state
<> 128:9bcdf88f62b0 208 * @param __HANDLE__: specifies the DAC handle.
<> 128:9bcdf88f62b0 209 * @retval None
<> 128:9bcdf88f62b0 210 */
<> 128:9bcdf88f62b0 211 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
<> 128:9bcdf88f62b0 212
<> 128:9bcdf88f62b0 213 /** @brief Enable the DAC channel
<> 128:9bcdf88f62b0 214 * @param __HANDLE__: specifies the DAC handle.
<> 128:9bcdf88f62b0 215 * @param __DAC_Channel__: specifies the DAC channel
<> 128:9bcdf88f62b0 216 * @retval None
<> 128:9bcdf88f62b0 217 */
<> 128:9bcdf88f62b0 218 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
<> 128:9bcdf88f62b0 219 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 /** @brief Disable the DAC channel
<> 128:9bcdf88f62b0 222 * @param __HANDLE__: specifies the DAC handle
<> 128:9bcdf88f62b0 223 * @param __DAC_Channel__: specifies the DAC channel.
<> 128:9bcdf88f62b0 224 * @retval None
<> 128:9bcdf88f62b0 225 */
<> 128:9bcdf88f62b0 226 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
<> 128:9bcdf88f62b0 227 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
<> 128:9bcdf88f62b0 228
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 /** @brief Enable the DAC interrupt
<> 128:9bcdf88f62b0 231 * @param __HANDLE__: specifies the DAC handle
<> 128:9bcdf88f62b0 232 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 128:9bcdf88f62b0 233 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 234 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 128:9bcdf88f62b0 235 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 128:9bcdf88f62b0 236 * @retval None
<> 128:9bcdf88f62b0 237 */
<> 128:9bcdf88f62b0 238 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
<> 128:9bcdf88f62b0 239
<> 128:9bcdf88f62b0 240 /** @brief Disable the DAC interrupt
<> 128:9bcdf88f62b0 241 * @param __HANDLE__: specifies the DAC handle
<> 128:9bcdf88f62b0 242 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 128:9bcdf88f62b0 243 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 244 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 128:9bcdf88f62b0 245 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 128:9bcdf88f62b0 246 * @retval None
<> 128:9bcdf88f62b0 247 */
<> 128:9bcdf88f62b0 248 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
<> 128:9bcdf88f62b0 249
<> 128:9bcdf88f62b0 250 /** @brief Checks if the specified DAC interrupt source is enabled or disabled.
<> 128:9bcdf88f62b0 251 * @param __HANDLE__: DAC handle
<> 128:9bcdf88f62b0 252 * @param __INTERRUPT__: DAC interrupt source to check
<> 128:9bcdf88f62b0 253 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 254 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 128:9bcdf88f62b0 255 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 128:9bcdf88f62b0 256 * @retval State of interruption (SET or RESET)
<> 128:9bcdf88f62b0 257 */
<> 128:9bcdf88f62b0 258 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 /** @brief Get the selected DAC's flag status.
<> 128:9bcdf88f62b0 261 * @param __HANDLE__: specifies the DAC handle.
<> 128:9bcdf88f62b0 262 * @param __FLAG__: specifies the DAC flag to get.
<> 128:9bcdf88f62b0 263 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 264 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 128:9bcdf88f62b0 265 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 128:9bcdf88f62b0 266 * @retval None
<> 128:9bcdf88f62b0 267 */
<> 128:9bcdf88f62b0 268 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 /** @brief Clear the DAC's flag.
<> 128:9bcdf88f62b0 271 * @param __HANDLE__: specifies the DAC handle.
<> 128:9bcdf88f62b0 272 * @param __FLAG__: specifies the DAC flag to clear.
<> 128:9bcdf88f62b0 273 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 274 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 128:9bcdf88f62b0 275 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 128:9bcdf88f62b0 276 * @retval None
<> 128:9bcdf88f62b0 277 */
<> 128:9bcdf88f62b0 278 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 128:9bcdf88f62b0 279
<> 128:9bcdf88f62b0 280 /**
<> 128:9bcdf88f62b0 281 * @}
<> 128:9bcdf88f62b0 282 */
<> 128:9bcdf88f62b0 283
<> 128:9bcdf88f62b0 284 /* Private macro -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 285
<> 128:9bcdf88f62b0 286 /** @defgroup DAC_Private_Macros DAC Private Macros
<> 128:9bcdf88f62b0 287 * @{
<> 128:9bcdf88f62b0 288 */
<> 128:9bcdf88f62b0 289 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 128:9bcdf88f62b0 290 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 128:9bcdf88f62b0 291 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 128:9bcdf88f62b0 292 ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \
<> 128:9bcdf88f62b0 293 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 128:9bcdf88f62b0 294 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
<> 128:9bcdf88f62b0 295 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 128:9bcdf88f62b0 296 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
<> 128:9bcdf88f62b0 299 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
<> 128:9bcdf88f62b0 300
<> 128:9bcdf88f62b0 301 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
<> 128:9bcdf88f62b0 302 ((CHANNEL) == DAC_CHANNEL_2))
<> 128:9bcdf88f62b0 303
<> 128:9bcdf88f62b0 304 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
<> 128:9bcdf88f62b0 305 ((ALIGN) == DAC_ALIGN_12B_L) || \
<> 128:9bcdf88f62b0 306 ((ALIGN) == DAC_ALIGN_8B_R))
<> 128:9bcdf88f62b0 307
<> 128:9bcdf88f62b0 308 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
<> 128:9bcdf88f62b0 309
<> 128:9bcdf88f62b0 310 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
<> 128:9bcdf88f62b0 313
<> 128:9bcdf88f62b0 314 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
<> 128:9bcdf88f62b0 315
<> 128:9bcdf88f62b0 316 /**
<> 128:9bcdf88f62b0 317 * @}
<> 128:9bcdf88f62b0 318 */
<> 128:9bcdf88f62b0 319
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 /* Include DAC HAL Extension module */
<> 128:9bcdf88f62b0 322 #include "stm32l1xx_hal_dac_ex.h"
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /** @addtogroup DAC_Exported_Functions
<> 128:9bcdf88f62b0 327 * @{
<> 128:9bcdf88f62b0 328 */
<> 128:9bcdf88f62b0 329
<> 128:9bcdf88f62b0 330 /** @addtogroup DAC_Exported_Functions_Group1
<> 128:9bcdf88f62b0 331 * @{
<> 128:9bcdf88f62b0 332 */
<> 128:9bcdf88f62b0 333 /* Initialization and de-initialization functions *****************************/
<> 128:9bcdf88f62b0 334 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 335 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 336 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 337 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 338
<> 128:9bcdf88f62b0 339 /**
<> 128:9bcdf88f62b0 340 * @}
<> 128:9bcdf88f62b0 341 */
<> 128:9bcdf88f62b0 342
<> 128:9bcdf88f62b0 343 /** @addtogroup DAC_Exported_Functions_Group2
<> 128:9bcdf88f62b0 344 * @{
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346 /* IO operation functions *****************************************************/
<> 128:9bcdf88f62b0 347 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 128:9bcdf88f62b0 348 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 128:9bcdf88f62b0 349 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
<> 128:9bcdf88f62b0 350 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 128:9bcdf88f62b0 351 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
<> 128:9bcdf88f62b0 352 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 128:9bcdf88f62b0 353
<> 128:9bcdf88f62b0 354 /**
<> 128:9bcdf88f62b0 355 * @}
<> 128:9bcdf88f62b0 356 */
<> 128:9bcdf88f62b0 357
<> 128:9bcdf88f62b0 358 /** @addtogroup DAC_Exported_Functions_Group2
<> 128:9bcdf88f62b0 359 * @{
<> 128:9bcdf88f62b0 360 */
<> 128:9bcdf88f62b0 361 /* Peripheral Control functions ***********************************************/
<> 128:9bcdf88f62b0 362 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
<> 128:9bcdf88f62b0 363
<> 128:9bcdf88f62b0 364 /**
<> 128:9bcdf88f62b0 365 * @}
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367
<> 128:9bcdf88f62b0 368 /** @addtogroup DAC_Exported_Functions_Group2
<> 128:9bcdf88f62b0 369 * @{
<> 128:9bcdf88f62b0 370 */
<> 128:9bcdf88f62b0 371 /* Peripheral State functions *************************************************/
<> 128:9bcdf88f62b0 372 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 373 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 374 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
<> 128:9bcdf88f62b0 375
<> 128:9bcdf88f62b0 376 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 377 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 128:9bcdf88f62b0 378 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
<> 128:9bcdf88f62b0 379 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 128:9bcdf88f62b0 380
<> 128:9bcdf88f62b0 381 /**
<> 128:9bcdf88f62b0 382 * @}
<> 128:9bcdf88f62b0 383 */
<> 128:9bcdf88f62b0 384
<> 128:9bcdf88f62b0 385 /**
<> 128:9bcdf88f62b0 386 * @}
<> 128:9bcdf88f62b0 387 */
<> 128:9bcdf88f62b0 388
<> 128:9bcdf88f62b0 389 /**
<> 128:9bcdf88f62b0 390 * @}
<> 128:9bcdf88f62b0 391 */
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /**
<> 128:9bcdf88f62b0 394 * @}
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396
<> 128:9bcdf88f62b0 397 #ifdef __cplusplus
<> 128:9bcdf88f62b0 398 }
<> 128:9bcdf88f62b0 399 #endif
<> 128:9bcdf88f62b0 400
<> 128:9bcdf88f62b0 401 #endif /*__STM32L1xx_HAL_DAC_H */
<> 128:9bcdf88f62b0 402
<> 128:9bcdf88f62b0 403 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 128:9bcdf88f62b0 404