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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_cortex.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of CORTEX HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_CORTEX_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_CORTEX_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup CORTEX
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 63 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
<> 128:9bcdf88f62b0 64 * @brief MPU Region initialization structure
<> 128:9bcdf88f62b0 65 * @{
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67 typedef struct
<> 128:9bcdf88f62b0 68 {
<> 128:9bcdf88f62b0 69 uint8_t Enable; /*!< Specifies the status of the region.
<> 128:9bcdf88f62b0 70 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
<> 128:9bcdf88f62b0 71 uint8_t Number; /*!< Specifies the number of the region to protect.
<> 128:9bcdf88f62b0 72 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
<> 128:9bcdf88f62b0 73 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
<> 128:9bcdf88f62b0 74 uint8_t Size; /*!< Specifies the size of the region to protect.
<> 128:9bcdf88f62b0 75 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
<> 128:9bcdf88f62b0 76 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
<> 128:9bcdf88f62b0 77 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 128:9bcdf88f62b0 78 uint8_t TypeExtField; /*!< Specifies the TEX field level.
<> 128:9bcdf88f62b0 79 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
<> 128:9bcdf88f62b0 80 uint8_t AccessPermission; /*!< Specifies the region access permission type.
<> 128:9bcdf88f62b0 81 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
<> 128:9bcdf88f62b0 82 uint8_t DisableExec; /*!< Specifies the instruction access status.
<> 128:9bcdf88f62b0 83 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
<> 128:9bcdf88f62b0 84 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
<> 128:9bcdf88f62b0 85 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
<> 128:9bcdf88f62b0 86 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
<> 128:9bcdf88f62b0 87 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
<> 128:9bcdf88f62b0 88 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
<> 128:9bcdf88f62b0 89 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
<> 128:9bcdf88f62b0 90 }MPU_Region_InitTypeDef;
<> 128:9bcdf88f62b0 91 /**
<> 128:9bcdf88f62b0 92 * @}
<> 128:9bcdf88f62b0 93 */
<> 128:9bcdf88f62b0 94 #endif /* __MPU_PRESENT */
<> 128:9bcdf88f62b0 95
<> 128:9bcdf88f62b0 96 /**
<> 128:9bcdf88f62b0 97 * @}
<> 128:9bcdf88f62b0 98 */
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
<> 128:9bcdf88f62b0 103 * @{
<> 128:9bcdf88f62b0 104 */
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106
<> 128:9bcdf88f62b0 107 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
<> 128:9bcdf88f62b0 108 * @{
<> 128:9bcdf88f62b0 109 */
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
<> 128:9bcdf88f62b0 112 4 bits for subpriority */
<> 128:9bcdf88f62b0 113 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
<> 128:9bcdf88f62b0 114 3 bits for subpriority */
<> 128:9bcdf88f62b0 115 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
<> 128:9bcdf88f62b0 116 2 bits for subpriority */
<> 128:9bcdf88f62b0 117 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
<> 128:9bcdf88f62b0 118 1 bits for subpriority */
<> 128:9bcdf88f62b0 119 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
<> 128:9bcdf88f62b0 120 0 bits for subpriority */
<> 128:9bcdf88f62b0 121 /**
<> 128:9bcdf88f62b0 122 * @}
<> 128:9bcdf88f62b0 123 */
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
<> 128:9bcdf88f62b0 126 * @{
<> 128:9bcdf88f62b0 127 */
<> 128:9bcdf88f62b0 128 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 129 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 /**
<> 128:9bcdf88f62b0 132 * @}
<> 128:9bcdf88f62b0 133 */
<> 128:9bcdf88f62b0 134
<> 128:9bcdf88f62b0 135 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 136 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
<> 128:9bcdf88f62b0 137 * @{
<> 128:9bcdf88f62b0 138 */
<> 128:9bcdf88f62b0 139 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 140 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
<> 128:9bcdf88f62b0 141 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
<> 128:9bcdf88f62b0 142 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
<> 128:9bcdf88f62b0 143 /**
<> 128:9bcdf88f62b0 144 * @}
<> 128:9bcdf88f62b0 145 */
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
<> 128:9bcdf88f62b0 148 * @{
<> 128:9bcdf88f62b0 149 */
<> 128:9bcdf88f62b0 150 #define MPU_REGION_ENABLE ((uint8_t)0x01)
<> 128:9bcdf88f62b0 151 #define MPU_REGION_DISABLE ((uint8_t)0x00)
<> 128:9bcdf88f62b0 152 /**
<> 128:9bcdf88f62b0 153 * @}
<> 128:9bcdf88f62b0 154 */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
<> 128:9bcdf88f62b0 157 * @{
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
<> 128:9bcdf88f62b0 160 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
<> 128:9bcdf88f62b0 161 /**
<> 128:9bcdf88f62b0 162 * @}
<> 128:9bcdf88f62b0 163 */
<> 128:9bcdf88f62b0 164
<> 128:9bcdf88f62b0 165 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
<> 128:9bcdf88f62b0 166 * @{
<> 128:9bcdf88f62b0 167 */
<> 128:9bcdf88f62b0 168 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
<> 128:9bcdf88f62b0 169 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
<> 128:9bcdf88f62b0 170 /**
<> 128:9bcdf88f62b0 171 * @}
<> 128:9bcdf88f62b0 172 */
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
<> 128:9bcdf88f62b0 175 * @{
<> 128:9bcdf88f62b0 176 */
<> 128:9bcdf88f62b0 177 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
<> 128:9bcdf88f62b0 178 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @}
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
<> 128:9bcdf88f62b0 184 * @{
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
<> 128:9bcdf88f62b0 187 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
<> 128:9bcdf88f62b0 188 /**
<> 128:9bcdf88f62b0 189 * @}
<> 128:9bcdf88f62b0 190 */
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
<> 128:9bcdf88f62b0 193 * @{
<> 128:9bcdf88f62b0 194 */
<> 128:9bcdf88f62b0 195 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
<> 128:9bcdf88f62b0 196 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
<> 128:9bcdf88f62b0 197 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
<> 128:9bcdf88f62b0 198 /**
<> 128:9bcdf88f62b0 199 * @}
<> 128:9bcdf88f62b0 200 */
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
<> 128:9bcdf88f62b0 203 * @{
<> 128:9bcdf88f62b0 204 */
<> 128:9bcdf88f62b0 205 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
<> 128:9bcdf88f62b0 206 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
<> 128:9bcdf88f62b0 207 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
<> 128:9bcdf88f62b0 208 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
<> 128:9bcdf88f62b0 209 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
<> 128:9bcdf88f62b0 210 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
<> 128:9bcdf88f62b0 211 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
<> 128:9bcdf88f62b0 212 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
<> 128:9bcdf88f62b0 213 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
<> 128:9bcdf88f62b0 214 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
<> 128:9bcdf88f62b0 215 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
<> 128:9bcdf88f62b0 216 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
<> 128:9bcdf88f62b0 217 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
<> 128:9bcdf88f62b0 218 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
<> 128:9bcdf88f62b0 219 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
<> 128:9bcdf88f62b0 220 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
<> 128:9bcdf88f62b0 221 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
<> 128:9bcdf88f62b0 222 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
<> 128:9bcdf88f62b0 223 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
<> 128:9bcdf88f62b0 224 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
<> 128:9bcdf88f62b0 225 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
<> 128:9bcdf88f62b0 226 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
<> 128:9bcdf88f62b0 227 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
<> 128:9bcdf88f62b0 228 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
<> 128:9bcdf88f62b0 229 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
<> 128:9bcdf88f62b0 230 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
<> 128:9bcdf88f62b0 231 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
<> 128:9bcdf88f62b0 232 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
<> 128:9bcdf88f62b0 233 /**
<> 128:9bcdf88f62b0 234 * @}
<> 128:9bcdf88f62b0 235 */
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
<> 128:9bcdf88f62b0 238 * @{
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
<> 128:9bcdf88f62b0 241 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
<> 128:9bcdf88f62b0 242 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
<> 128:9bcdf88f62b0 243 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
<> 128:9bcdf88f62b0 244 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
<> 128:9bcdf88f62b0 245 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
<> 128:9bcdf88f62b0 246 /**
<> 128:9bcdf88f62b0 247 * @}
<> 128:9bcdf88f62b0 248 */
<> 128:9bcdf88f62b0 249
<> 128:9bcdf88f62b0 250 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
<> 128:9bcdf88f62b0 251 * @{
<> 128:9bcdf88f62b0 252 */
<> 128:9bcdf88f62b0 253 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
<> 128:9bcdf88f62b0 254 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
<> 128:9bcdf88f62b0 255 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
<> 128:9bcdf88f62b0 256 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
<> 128:9bcdf88f62b0 257 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
<> 128:9bcdf88f62b0 258 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
<> 128:9bcdf88f62b0 259 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
<> 128:9bcdf88f62b0 260 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
<> 128:9bcdf88f62b0 261 /**
<> 128:9bcdf88f62b0 262 * @}
<> 128:9bcdf88f62b0 263 */
<> 128:9bcdf88f62b0 264 #endif /* __MPU_PRESENT */
<> 128:9bcdf88f62b0 265 /**
<> 128:9bcdf88f62b0 266 * @}
<> 128:9bcdf88f62b0 267 */
<> 128:9bcdf88f62b0 268
<> 128:9bcdf88f62b0 269 /* Exported Macros -----------------------------------------------------------*/
<> 128:9bcdf88f62b0 270 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
<> 128:9bcdf88f62b0 271 * @{
<> 128:9bcdf88f62b0 272 */
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 /** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
<> 128:9bcdf88f62b0 275 * @{
<> 128:9bcdf88f62b0 276 */
<> 128:9bcdf88f62b0 277 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
<> 128:9bcdf88f62b0 278 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
<> 128:9bcdf88f62b0 279 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
<> 128:9bcdf88f62b0 280 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
<> 128:9bcdf88f62b0 281 ((GROUP) == NVIC_PRIORITYGROUP_4))
<> 128:9bcdf88f62b0 282
<> 128:9bcdf88f62b0 283 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 /**
<> 128:9bcdf88f62b0 290 * @}
<> 128:9bcdf88f62b0 291 */
<> 128:9bcdf88f62b0 292
<> 128:9bcdf88f62b0 293 /**
<> 128:9bcdf88f62b0 294 * @}
<> 128:9bcdf88f62b0 295 */
<> 128:9bcdf88f62b0 296
<> 128:9bcdf88f62b0 297 /* Private macro -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 298 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
<> 128:9bcdf88f62b0 299 * @{
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
<> 128:9bcdf88f62b0 303 * @{
<> 128:9bcdf88f62b0 304 */
<> 128:9bcdf88f62b0 305 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
<> 128:9bcdf88f62b0 306 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<> 128:9bcdf88f62b0 307 /**
<> 128:9bcdf88f62b0 308 * @}
<> 128:9bcdf88f62b0 309 */
<> 128:9bcdf88f62b0 310
<> 128:9bcdf88f62b0 311 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 312 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
<> 128:9bcdf88f62b0 313 ((STATE) == MPU_REGION_DISABLE))
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
<> 128:9bcdf88f62b0 316 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
<> 128:9bcdf88f62b0 319 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
<> 128:9bcdf88f62b0 322 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
<> 128:9bcdf88f62b0 325 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<> 128:9bcdf88f62b0 326
<> 128:9bcdf88f62b0 327 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
<> 128:9bcdf88f62b0 328 ((TYPE) == MPU_TEX_LEVEL1) || \
<> 128:9bcdf88f62b0 329 ((TYPE) == MPU_TEX_LEVEL2))
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
<> 128:9bcdf88f62b0 332 ((TYPE) == MPU_REGION_PRIV_RW) || \
<> 128:9bcdf88f62b0 333 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
<> 128:9bcdf88f62b0 334 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
<> 128:9bcdf88f62b0 335 ((TYPE) == MPU_REGION_PRIV_RO) || \
<> 128:9bcdf88f62b0 336 ((TYPE) == MPU_REGION_PRIV_RO_URO))
<> 128:9bcdf88f62b0 337
<> 128:9bcdf88f62b0 338 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
<> 128:9bcdf88f62b0 339 ((NUMBER) == MPU_REGION_NUMBER1) || \
<> 128:9bcdf88f62b0 340 ((NUMBER) == MPU_REGION_NUMBER2) || \
<> 128:9bcdf88f62b0 341 ((NUMBER) == MPU_REGION_NUMBER3) || \
<> 128:9bcdf88f62b0 342 ((NUMBER) == MPU_REGION_NUMBER4) || \
<> 128:9bcdf88f62b0 343 ((NUMBER) == MPU_REGION_NUMBER5) || \
<> 128:9bcdf88f62b0 344 ((NUMBER) == MPU_REGION_NUMBER6) || \
<> 128:9bcdf88f62b0 345 ((NUMBER) == MPU_REGION_NUMBER7))
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
<> 128:9bcdf88f62b0 348 ((SIZE) == MPU_REGION_SIZE_64B) || \
<> 128:9bcdf88f62b0 349 ((SIZE) == MPU_REGION_SIZE_128B) || \
<> 128:9bcdf88f62b0 350 ((SIZE) == MPU_REGION_SIZE_256B) || \
<> 128:9bcdf88f62b0 351 ((SIZE) == MPU_REGION_SIZE_512B) || \
<> 128:9bcdf88f62b0 352 ((SIZE) == MPU_REGION_SIZE_1KB) || \
<> 128:9bcdf88f62b0 353 ((SIZE) == MPU_REGION_SIZE_2KB) || \
<> 128:9bcdf88f62b0 354 ((SIZE) == MPU_REGION_SIZE_4KB) || \
<> 128:9bcdf88f62b0 355 ((SIZE) == MPU_REGION_SIZE_8KB) || \
<> 128:9bcdf88f62b0 356 ((SIZE) == MPU_REGION_SIZE_16KB) || \
<> 128:9bcdf88f62b0 357 ((SIZE) == MPU_REGION_SIZE_32KB) || \
<> 128:9bcdf88f62b0 358 ((SIZE) == MPU_REGION_SIZE_64KB) || \
<> 128:9bcdf88f62b0 359 ((SIZE) == MPU_REGION_SIZE_128KB) || \
<> 128:9bcdf88f62b0 360 ((SIZE) == MPU_REGION_SIZE_256KB) || \
<> 128:9bcdf88f62b0 361 ((SIZE) == MPU_REGION_SIZE_512KB) || \
<> 128:9bcdf88f62b0 362 ((SIZE) == MPU_REGION_SIZE_1MB) || \
<> 128:9bcdf88f62b0 363 ((SIZE) == MPU_REGION_SIZE_2MB) || \
<> 128:9bcdf88f62b0 364 ((SIZE) == MPU_REGION_SIZE_4MB) || \
<> 128:9bcdf88f62b0 365 ((SIZE) == MPU_REGION_SIZE_8MB) || \
<> 128:9bcdf88f62b0 366 ((SIZE) == MPU_REGION_SIZE_16MB) || \
<> 128:9bcdf88f62b0 367 ((SIZE) == MPU_REGION_SIZE_32MB) || \
<> 128:9bcdf88f62b0 368 ((SIZE) == MPU_REGION_SIZE_64MB) || \
<> 128:9bcdf88f62b0 369 ((SIZE) == MPU_REGION_SIZE_128MB) || \
<> 128:9bcdf88f62b0 370 ((SIZE) == MPU_REGION_SIZE_256MB) || \
<> 128:9bcdf88f62b0 371 ((SIZE) == MPU_REGION_SIZE_512MB) || \
<> 128:9bcdf88f62b0 372 ((SIZE) == MPU_REGION_SIZE_1GB) || \
<> 128:9bcdf88f62b0 373 ((SIZE) == MPU_REGION_SIZE_2GB) || \
<> 128:9bcdf88f62b0 374 ((SIZE) == MPU_REGION_SIZE_4GB))
<> 128:9bcdf88f62b0 375
<> 128:9bcdf88f62b0 376 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
<> 128:9bcdf88f62b0 377 #endif /* __MPU_PRESENT */
<> 128:9bcdf88f62b0 378
<> 128:9bcdf88f62b0 379 /**
<> 128:9bcdf88f62b0 380 * @}
<> 128:9bcdf88f62b0 381 */
<> 128:9bcdf88f62b0 382
<> 128:9bcdf88f62b0 383 /* Private functions ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 384 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
<> 128:9bcdf88f62b0 385 * @brief CORTEX private functions
<> 128:9bcdf88f62b0 386 * @{
<> 128:9bcdf88f62b0 387 */
<> 128:9bcdf88f62b0 388
<> 128:9bcdf88f62b0 389 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 390 /**
<> 128:9bcdf88f62b0 391 * @brief Disables the MPU
<> 128:9bcdf88f62b0 392 * @retval None
<> 128:9bcdf88f62b0 393 */
<> 128:9bcdf88f62b0 394 __STATIC_INLINE void HAL_MPU_Disable(void)
<> 128:9bcdf88f62b0 395 {
<> 128:9bcdf88f62b0 396 /* Disable fault exceptions */
<> 128:9bcdf88f62b0 397 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
<> 128:9bcdf88f62b0 398
<> 128:9bcdf88f62b0 399 /* Disable the MPU */
<> 128:9bcdf88f62b0 400 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
<> 128:9bcdf88f62b0 401 }
<> 128:9bcdf88f62b0 402
<> 128:9bcdf88f62b0 403 /**
<> 128:9bcdf88f62b0 404 * @brief Enables the MPU
<> 128:9bcdf88f62b0 405 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
<> 128:9bcdf88f62b0 406 * NMI, FAULTMASK and privileged accessto the default memory
<> 128:9bcdf88f62b0 407 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 408 * @arg MPU_HFNMI_PRIVDEF_NONE
<> 128:9bcdf88f62b0 409 * @arg MPU_HARDFAULT_NMI
<> 128:9bcdf88f62b0 410 * @arg MPU_PRIVILEGED_DEFAULT
<> 128:9bcdf88f62b0 411 * @arg MPU_HFNMI_PRIVDEF
<> 128:9bcdf88f62b0 412 * @retval None
<> 128:9bcdf88f62b0 413 */
<> 128:9bcdf88f62b0 414 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
<> 128:9bcdf88f62b0 415 {
<> 128:9bcdf88f62b0 416 /* Enable the MPU */
<> 128:9bcdf88f62b0 417 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
<> 128:9bcdf88f62b0 418
<> 128:9bcdf88f62b0 419 /* Enable fault exceptions */
<> 128:9bcdf88f62b0 420 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
<> 128:9bcdf88f62b0 421 }
<> 128:9bcdf88f62b0 422 #endif /* __MPU_PRESENT */
<> 128:9bcdf88f62b0 423
<> 128:9bcdf88f62b0 424 /**
<> 128:9bcdf88f62b0 425 * @}
<> 128:9bcdf88f62b0 426 */
<> 128:9bcdf88f62b0 427
<> 128:9bcdf88f62b0 428 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 429 /** @addtogroup CORTEX_Exported_Functions
<> 128:9bcdf88f62b0 430 * @{
<> 128:9bcdf88f62b0 431 */
<> 128:9bcdf88f62b0 432
<> 128:9bcdf88f62b0 433 /** @addtogroup CORTEX_Exported_Functions_Group1
<> 128:9bcdf88f62b0 434 * @{
<> 128:9bcdf88f62b0 435 */
<> 128:9bcdf88f62b0 436 /* Initialization and de-initialization functions *****************************/
<> 128:9bcdf88f62b0 437 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
<> 128:9bcdf88f62b0 438 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
<> 128:9bcdf88f62b0 439 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 440 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 441 void HAL_NVIC_SystemReset(void);
<> 128:9bcdf88f62b0 442 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
<> 128:9bcdf88f62b0 443 /**
<> 128:9bcdf88f62b0 444 * @}
<> 128:9bcdf88f62b0 445 */
<> 128:9bcdf88f62b0 446
<> 128:9bcdf88f62b0 447 /** @addtogroup CORTEX_Exported_Functions_Group2
<> 128:9bcdf88f62b0 448 * @{
<> 128:9bcdf88f62b0 449 */
<> 128:9bcdf88f62b0 450 /* Peripheral Control functions ***********************************************/
<> 128:9bcdf88f62b0 451 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 452 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
<> 128:9bcdf88f62b0 453 #endif /* __MPU_PRESENT */
<> 128:9bcdf88f62b0 454 uint32_t HAL_NVIC_GetPriorityGrouping(void);
<> 128:9bcdf88f62b0 455 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
<> 128:9bcdf88f62b0 456 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 457 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 458 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 459 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
<> 128:9bcdf88f62b0 460 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
<> 128:9bcdf88f62b0 461 void HAL_SYSTICK_IRQHandler(void);
<> 128:9bcdf88f62b0 462 void HAL_SYSTICK_Callback(void);
<> 128:9bcdf88f62b0 463 /**
<> 128:9bcdf88f62b0 464 * @}
<> 128:9bcdf88f62b0 465 */
<> 128:9bcdf88f62b0 466
<> 128:9bcdf88f62b0 467 /**
<> 128:9bcdf88f62b0 468 * @}
<> 128:9bcdf88f62b0 469 */
<> 128:9bcdf88f62b0 470
<> 128:9bcdf88f62b0 471 /**
<> 128:9bcdf88f62b0 472 * @}
<> 128:9bcdf88f62b0 473 */
<> 128:9bcdf88f62b0 474
<> 128:9bcdf88f62b0 475 /**
<> 128:9bcdf88f62b0 476 * @}
<> 128:9bcdf88f62b0 477 */
<> 128:9bcdf88f62b0 478
<> 128:9bcdf88f62b0 479 #ifdef __cplusplus
<> 128:9bcdf88f62b0 480 }
<> 128:9bcdf88f62b0 481 #endif
<> 128:9bcdf88f62b0 482
<> 128:9bcdf88f62b0 483 #endif /* __STM32L1xx_HAL_CORTEX_H */
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485
<> 128:9bcdf88f62b0 486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/