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mbed 2

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TARGET_NUCLEO_L011K4/core_cm0.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file core_cm0.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.3
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 157:e7ca05fa8600 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 157:e7ca05fa8600 29 #endif
AnnaBridge 157:e7ca05fa8600 30
AnnaBridge 157:e7ca05fa8600 31 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 157:e7ca05fa8600 32 #define __CORE_CM0_H_GENERIC
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 #include <stdint.h>
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 37 extern "C" {
AnnaBridge 157:e7ca05fa8600 38 #endif
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 /**
AnnaBridge 157:e7ca05fa8600 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 157:e7ca05fa8600 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 157:e7ca05fa8600 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 157:e7ca05fa8600 48 Unions are used for effective representation of core registers.
AnnaBridge 157:e7ca05fa8600 49
AnnaBridge 157:e7ca05fa8600 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 157:e7ca05fa8600 51 Function-like macros are used to allow more efficient code.
AnnaBridge 157:e7ca05fa8600 52 */
AnnaBridge 157:e7ca05fa8600 53
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 56 * CMSIS definitions
AnnaBridge 157:e7ca05fa8600 57 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 \ingroup Cortex_M0
AnnaBridge 157:e7ca05fa8600 60 @{
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
AnnaBridge 157:e7ca05fa8600 65 /* CMSIS CM0 definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 157:e7ca05fa8600 68 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 157:e7ca05fa8600 72
AnnaBridge 157:e7ca05fa8600 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 157:e7ca05fa8600 74 This core does not support an FPU at all
AnnaBridge 157:e7ca05fa8600 75 */
AnnaBridge 157:e7ca05fa8600 76 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 77
AnnaBridge 157:e7ca05fa8600 78 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 79 #if defined __TARGET_FPU_VFP
AnnaBridge 157:e7ca05fa8600 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 81 #endif
AnnaBridge 157:e7ca05fa8600 82
AnnaBridge 157:e7ca05fa8600 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 84 #if defined __ARM_PCS_VFP
AnnaBridge 157:e7ca05fa8600 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 86 #endif
AnnaBridge 157:e7ca05fa8600 87
AnnaBridge 157:e7ca05fa8600 88 #elif defined ( __GNUC__ )
AnnaBridge 157:e7ca05fa8600 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 157:e7ca05fa8600 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 91 #endif
AnnaBridge 157:e7ca05fa8600 92
AnnaBridge 157:e7ca05fa8600 93 #elif defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 94 #if defined __ARMVFP__
AnnaBridge 157:e7ca05fa8600 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 96 #endif
AnnaBridge 157:e7ca05fa8600 97
AnnaBridge 157:e7ca05fa8600 98 #elif defined ( __TI_ARM__ )
AnnaBridge 157:e7ca05fa8600 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 157:e7ca05fa8600 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 101 #endif
AnnaBridge 157:e7ca05fa8600 102
AnnaBridge 157:e7ca05fa8600 103 #elif defined ( __TASKING__ )
AnnaBridge 157:e7ca05fa8600 104 #if defined __FPU_VFP__
AnnaBridge 157:e7ca05fa8600 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 106 #endif
AnnaBridge 157:e7ca05fa8600 107
AnnaBridge 157:e7ca05fa8600 108 #elif defined ( __CSMC__ )
AnnaBridge 157:e7ca05fa8600 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 157:e7ca05fa8600 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 111 #endif
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 #endif
AnnaBridge 157:e7ca05fa8600 114
AnnaBridge 157:e7ca05fa8600 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 116
AnnaBridge 157:e7ca05fa8600 117
AnnaBridge 157:e7ca05fa8600 118 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 119 }
AnnaBridge 157:e7ca05fa8600 120 #endif
AnnaBridge 157:e7ca05fa8600 121
AnnaBridge 157:e7ca05fa8600 122 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #ifndef __CMSIS_GENERIC
AnnaBridge 157:e7ca05fa8600 125
AnnaBridge 157:e7ca05fa8600 126 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 127 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 128
AnnaBridge 157:e7ca05fa8600 129 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 130 extern "C" {
AnnaBridge 157:e7ca05fa8600 131 #endif
AnnaBridge 157:e7ca05fa8600 132
AnnaBridge 157:e7ca05fa8600 133 /* check device defines and use defaults */
AnnaBridge 157:e7ca05fa8600 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 157:e7ca05fa8600 135 #ifndef __CM0_REV
AnnaBridge 157:e7ca05fa8600 136 #define __CM0_REV 0x0000U
AnnaBridge 157:e7ca05fa8600 137 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 138 #endif
AnnaBridge 157:e7ca05fa8600 139
AnnaBridge 157:e7ca05fa8600 140 #ifndef __NVIC_PRIO_BITS
AnnaBridge 157:e7ca05fa8600 141 #define __NVIC_PRIO_BITS 2U
AnnaBridge 157:e7ca05fa8600 142 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 143 #endif
AnnaBridge 157:e7ca05fa8600 144
AnnaBridge 157:e7ca05fa8600 145 #ifndef __Vendor_SysTickConfig
AnnaBridge 157:e7ca05fa8600 146 #define __Vendor_SysTickConfig 0U
AnnaBridge 157:e7ca05fa8600 147 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 148 #endif
AnnaBridge 157:e7ca05fa8600 149 #endif
AnnaBridge 157:e7ca05fa8600 150
AnnaBridge 157:e7ca05fa8600 151 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 157:e7ca05fa8600 152 /**
AnnaBridge 157:e7ca05fa8600 153 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 157:e7ca05fa8600 154
AnnaBridge 157:e7ca05fa8600 155 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 157:e7ca05fa8600 156 \li to specify the access to peripheral variables.
AnnaBridge 157:e7ca05fa8600 157 \li for automatic generation of peripheral register debug information.
AnnaBridge 157:e7ca05fa8600 158 */
AnnaBridge 157:e7ca05fa8600 159 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 160 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 161 #else
AnnaBridge 157:e7ca05fa8600 162 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 163 #endif
AnnaBridge 157:e7ca05fa8600 164 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 157:e7ca05fa8600 165 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 157:e7ca05fa8600 166
AnnaBridge 157:e7ca05fa8600 167 /* following defines should be used for structure members */
AnnaBridge 157:e7ca05fa8600 168 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 169 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 157:e7ca05fa8600 171
AnnaBridge 157:e7ca05fa8600 172 /*@} end of group Cortex_M0 */
AnnaBridge 157:e7ca05fa8600 173
AnnaBridge 157:e7ca05fa8600 174
AnnaBridge 157:e7ca05fa8600 175
AnnaBridge 157:e7ca05fa8600 176 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 177 * Register Abstraction
AnnaBridge 157:e7ca05fa8600 178 Core Register contain:
AnnaBridge 157:e7ca05fa8600 179 - Core Register
AnnaBridge 157:e7ca05fa8600 180 - Core NVIC Register
AnnaBridge 157:e7ca05fa8600 181 - Core SCB Register
AnnaBridge 157:e7ca05fa8600 182 - Core SysTick Register
AnnaBridge 157:e7ca05fa8600 183 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 184 /**
AnnaBridge 157:e7ca05fa8600 185 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 157:e7ca05fa8600 186 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 157:e7ca05fa8600 187 */
AnnaBridge 157:e7ca05fa8600 188
AnnaBridge 157:e7ca05fa8600 189 /**
AnnaBridge 157:e7ca05fa8600 190 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 191 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 157:e7ca05fa8600 192 \brief Core Register type definitions.
AnnaBridge 157:e7ca05fa8600 193 @{
AnnaBridge 157:e7ca05fa8600 194 */
AnnaBridge 157:e7ca05fa8600 195
AnnaBridge 157:e7ca05fa8600 196 /**
AnnaBridge 157:e7ca05fa8600 197 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 157:e7ca05fa8600 198 */
AnnaBridge 157:e7ca05fa8600 199 typedef union
AnnaBridge 157:e7ca05fa8600 200 {
AnnaBridge 157:e7ca05fa8600 201 struct
AnnaBridge 157:e7ca05fa8600 202 {
AnnaBridge 157:e7ca05fa8600 203 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 157:e7ca05fa8600 204 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 205 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 206 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 207 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 208 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 209 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 210 } APSR_Type;
AnnaBridge 157:e7ca05fa8600 211
AnnaBridge 157:e7ca05fa8600 212 /* APSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 213 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 157:e7ca05fa8600 214 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 157:e7ca05fa8600 215
AnnaBridge 157:e7ca05fa8600 216 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 157:e7ca05fa8600 217 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 218
AnnaBridge 157:e7ca05fa8600 219 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 157:e7ca05fa8600 220 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 157:e7ca05fa8600 221
AnnaBridge 157:e7ca05fa8600 222 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 157:e7ca05fa8600 223 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 157:e7ca05fa8600 224
AnnaBridge 157:e7ca05fa8600 225
AnnaBridge 157:e7ca05fa8600 226 /**
AnnaBridge 157:e7ca05fa8600 227 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 157:e7ca05fa8600 228 */
AnnaBridge 157:e7ca05fa8600 229 typedef union
AnnaBridge 157:e7ca05fa8600 230 {
AnnaBridge 157:e7ca05fa8600 231 struct
AnnaBridge 157:e7ca05fa8600 232 {
AnnaBridge 157:e7ca05fa8600 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 157:e7ca05fa8600 235 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 236 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 237 } IPSR_Type;
AnnaBridge 157:e7ca05fa8600 238
AnnaBridge 157:e7ca05fa8600 239 /* IPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 240 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 241 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 242
AnnaBridge 157:e7ca05fa8600 243
AnnaBridge 157:e7ca05fa8600 244 /**
AnnaBridge 157:e7ca05fa8600 245 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 157:e7ca05fa8600 246 */
AnnaBridge 157:e7ca05fa8600 247 typedef union
AnnaBridge 157:e7ca05fa8600 248 {
AnnaBridge 157:e7ca05fa8600 249 struct
AnnaBridge 157:e7ca05fa8600 250 {
AnnaBridge 157:e7ca05fa8600 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 252 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 157:e7ca05fa8600 253 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 157:e7ca05fa8600 254 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 157:e7ca05fa8600 255 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 256 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 257 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 258 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 259 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 260 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 261 } xPSR_Type;
AnnaBridge 157:e7ca05fa8600 262
AnnaBridge 157:e7ca05fa8600 263 /* xPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 264 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 157:e7ca05fa8600 265 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 157:e7ca05fa8600 266
AnnaBridge 157:e7ca05fa8600 267 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 157:e7ca05fa8600 268 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 269
AnnaBridge 157:e7ca05fa8600 270 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 157:e7ca05fa8600 271 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 157:e7ca05fa8600 272
AnnaBridge 157:e7ca05fa8600 273 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 157:e7ca05fa8600 274 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 157:e7ca05fa8600 275
AnnaBridge 157:e7ca05fa8600 276 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 157:e7ca05fa8600 277 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 157:e7ca05fa8600 278
AnnaBridge 157:e7ca05fa8600 279 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 280 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 281
AnnaBridge 157:e7ca05fa8600 282
AnnaBridge 157:e7ca05fa8600 283 /**
AnnaBridge 157:e7ca05fa8600 284 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 157:e7ca05fa8600 285 */
AnnaBridge 157:e7ca05fa8600 286 typedef union
AnnaBridge 157:e7ca05fa8600 287 {
AnnaBridge 157:e7ca05fa8600 288 struct
AnnaBridge 157:e7ca05fa8600 289 {
AnnaBridge 157:e7ca05fa8600 290 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 157:e7ca05fa8600 291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 157:e7ca05fa8600 292 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 157:e7ca05fa8600 293 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 294 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 295 } CONTROL_Type;
AnnaBridge 157:e7ca05fa8600 296
AnnaBridge 157:e7ca05fa8600 297 /* CONTROL Register Definitions */
AnnaBridge 157:e7ca05fa8600 298 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 157:e7ca05fa8600 299 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 157:e7ca05fa8600 300
AnnaBridge 157:e7ca05fa8600 301 /*@} end of group CMSIS_CORE */
AnnaBridge 157:e7ca05fa8600 302
AnnaBridge 157:e7ca05fa8600 303
AnnaBridge 157:e7ca05fa8600 304 /**
AnnaBridge 157:e7ca05fa8600 305 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 306 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 157:e7ca05fa8600 307 \brief Type definitions for the NVIC Registers
AnnaBridge 157:e7ca05fa8600 308 @{
AnnaBridge 157:e7ca05fa8600 309 */
AnnaBridge 157:e7ca05fa8600 310
AnnaBridge 157:e7ca05fa8600 311 /**
AnnaBridge 157:e7ca05fa8600 312 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 157:e7ca05fa8600 313 */
AnnaBridge 157:e7ca05fa8600 314 typedef struct
AnnaBridge 157:e7ca05fa8600 315 {
AnnaBridge 157:e7ca05fa8600 316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 157:e7ca05fa8600 317 uint32_t RESERVED0[31U];
AnnaBridge 157:e7ca05fa8600 318 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 157:e7ca05fa8600 319 uint32_t RSERVED1[31U];
AnnaBridge 157:e7ca05fa8600 320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 157:e7ca05fa8600 321 uint32_t RESERVED2[31U];
AnnaBridge 157:e7ca05fa8600 322 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 157:e7ca05fa8600 323 uint32_t RESERVED3[31U];
AnnaBridge 157:e7ca05fa8600 324 uint32_t RESERVED4[64U];
AnnaBridge 157:e7ca05fa8600 325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 157:e7ca05fa8600 326 } NVIC_Type;
AnnaBridge 157:e7ca05fa8600 327
AnnaBridge 157:e7ca05fa8600 328 /*@} end of group CMSIS_NVIC */
AnnaBridge 157:e7ca05fa8600 329
AnnaBridge 157:e7ca05fa8600 330
AnnaBridge 157:e7ca05fa8600 331 /**
AnnaBridge 157:e7ca05fa8600 332 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 333 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 157:e7ca05fa8600 334 \brief Type definitions for the System Control Block Registers
AnnaBridge 157:e7ca05fa8600 335 @{
AnnaBridge 157:e7ca05fa8600 336 */
AnnaBridge 157:e7ca05fa8600 337
AnnaBridge 157:e7ca05fa8600 338 /**
AnnaBridge 157:e7ca05fa8600 339 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 157:e7ca05fa8600 340 */
AnnaBridge 157:e7ca05fa8600 341 typedef struct
AnnaBridge 157:e7ca05fa8600 342 {
AnnaBridge 157:e7ca05fa8600 343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 157:e7ca05fa8600 344 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 157:e7ca05fa8600 345 uint32_t RESERVED0;
AnnaBridge 157:e7ca05fa8600 346 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 157:e7ca05fa8600 347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 157:e7ca05fa8600 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 157:e7ca05fa8600 349 uint32_t RESERVED1;
AnnaBridge 157:e7ca05fa8600 350 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 157:e7ca05fa8600 351 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 157:e7ca05fa8600 352 } SCB_Type;
AnnaBridge 157:e7ca05fa8600 353
AnnaBridge 157:e7ca05fa8600 354 /* SCB CPUID Register Definitions */
AnnaBridge 157:e7ca05fa8600 355 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 157:e7ca05fa8600 356 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 157:e7ca05fa8600 357
AnnaBridge 157:e7ca05fa8600 358 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 157:e7ca05fa8600 359 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 157:e7ca05fa8600 360
AnnaBridge 157:e7ca05fa8600 361 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 157:e7ca05fa8600 362 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 157:e7ca05fa8600 363
AnnaBridge 157:e7ca05fa8600 364 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 157:e7ca05fa8600 365 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 157:e7ca05fa8600 366
AnnaBridge 157:e7ca05fa8600 367 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 157:e7ca05fa8600 368 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 157:e7ca05fa8600 369
AnnaBridge 157:e7ca05fa8600 370 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 371 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 157:e7ca05fa8600 372 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 157:e7ca05fa8600 373
AnnaBridge 157:e7ca05fa8600 374 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 157:e7ca05fa8600 375 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 157:e7ca05fa8600 376
AnnaBridge 157:e7ca05fa8600 377 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 157:e7ca05fa8600 378 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 157:e7ca05fa8600 379
AnnaBridge 157:e7ca05fa8600 380 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 157:e7ca05fa8600 381 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 157:e7ca05fa8600 382
AnnaBridge 157:e7ca05fa8600 383 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 157:e7ca05fa8600 384 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 157:e7ca05fa8600 385
AnnaBridge 157:e7ca05fa8600 386 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 157:e7ca05fa8600 387 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 157:e7ca05fa8600 388
AnnaBridge 157:e7ca05fa8600 389 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 157:e7ca05fa8600 390 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 157:e7ca05fa8600 391
AnnaBridge 157:e7ca05fa8600 392 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 157:e7ca05fa8600 393 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 157:e7ca05fa8600 394
AnnaBridge 157:e7ca05fa8600 395 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 157:e7ca05fa8600 396 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 399 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 157:e7ca05fa8600 400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 157:e7ca05fa8600 401
AnnaBridge 157:e7ca05fa8600 402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 157:e7ca05fa8600 403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 157:e7ca05fa8600 404
AnnaBridge 157:e7ca05fa8600 405 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 157:e7ca05fa8600 406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 157:e7ca05fa8600 407
AnnaBridge 157:e7ca05fa8600 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 157:e7ca05fa8600 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 157:e7ca05fa8600 410
AnnaBridge 157:e7ca05fa8600 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 157:e7ca05fa8600 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 413
AnnaBridge 157:e7ca05fa8600 414 /* SCB System Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 415 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 157:e7ca05fa8600 416 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 157:e7ca05fa8600 417
AnnaBridge 157:e7ca05fa8600 418 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 157:e7ca05fa8600 419 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 157:e7ca05fa8600 420
AnnaBridge 157:e7ca05fa8600 421 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 157:e7ca05fa8600 422 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 157:e7ca05fa8600 423
AnnaBridge 157:e7ca05fa8600 424 /* SCB Configuration Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 425 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 157:e7ca05fa8600 426 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 157:e7ca05fa8600 427
AnnaBridge 157:e7ca05fa8600 428 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 157:e7ca05fa8600 429 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 157:e7ca05fa8600 430
AnnaBridge 157:e7ca05fa8600 431 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 157:e7ca05fa8600 432 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 157:e7ca05fa8600 433 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 157:e7ca05fa8600 434
AnnaBridge 157:e7ca05fa8600 435 /*@} end of group CMSIS_SCB */
AnnaBridge 157:e7ca05fa8600 436
AnnaBridge 157:e7ca05fa8600 437
AnnaBridge 157:e7ca05fa8600 438 /**
AnnaBridge 157:e7ca05fa8600 439 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 440 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 157:e7ca05fa8600 441 \brief Type definitions for the System Timer Registers.
AnnaBridge 157:e7ca05fa8600 442 @{
AnnaBridge 157:e7ca05fa8600 443 */
AnnaBridge 157:e7ca05fa8600 444
AnnaBridge 157:e7ca05fa8600 445 /**
AnnaBridge 157:e7ca05fa8600 446 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 157:e7ca05fa8600 447 */
AnnaBridge 157:e7ca05fa8600 448 typedef struct
AnnaBridge 157:e7ca05fa8600 449 {
AnnaBridge 157:e7ca05fa8600 450 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 157:e7ca05fa8600 451 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 157:e7ca05fa8600 452 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 157:e7ca05fa8600 453 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 157:e7ca05fa8600 454 } SysTick_Type;
AnnaBridge 157:e7ca05fa8600 455
AnnaBridge 157:e7ca05fa8600 456 /* SysTick Control / Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 457 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 157:e7ca05fa8600 458 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 157:e7ca05fa8600 459
AnnaBridge 157:e7ca05fa8600 460 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 157:e7ca05fa8600 461 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 157:e7ca05fa8600 462
AnnaBridge 157:e7ca05fa8600 463 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 157:e7ca05fa8600 464 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 157:e7ca05fa8600 465
AnnaBridge 157:e7ca05fa8600 466 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 467 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 468
AnnaBridge 157:e7ca05fa8600 469 /* SysTick Reload Register Definitions */
AnnaBridge 157:e7ca05fa8600 470 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 157:e7ca05fa8600 471 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 157:e7ca05fa8600 472
AnnaBridge 157:e7ca05fa8600 473 /* SysTick Current Register Definitions */
AnnaBridge 157:e7ca05fa8600 474 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 157:e7ca05fa8600 475 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 157:e7ca05fa8600 476
AnnaBridge 157:e7ca05fa8600 477 /* SysTick Calibration Register Definitions */
AnnaBridge 157:e7ca05fa8600 478 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 157:e7ca05fa8600 479 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 157:e7ca05fa8600 480
AnnaBridge 157:e7ca05fa8600 481 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 157:e7ca05fa8600 482 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 157:e7ca05fa8600 483
AnnaBridge 157:e7ca05fa8600 484 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 157:e7ca05fa8600 485 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 157:e7ca05fa8600 486
AnnaBridge 157:e7ca05fa8600 487 /*@} end of group CMSIS_SysTick */
AnnaBridge 157:e7ca05fa8600 488
AnnaBridge 157:e7ca05fa8600 489
AnnaBridge 157:e7ca05fa8600 490 /**
AnnaBridge 157:e7ca05fa8600 491 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 492 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 157:e7ca05fa8600 493 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 157:e7ca05fa8600 494 Therefore they are not covered by the Cortex-M0 header file.
AnnaBridge 157:e7ca05fa8600 495 @{
AnnaBridge 157:e7ca05fa8600 496 */
AnnaBridge 157:e7ca05fa8600 497 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 157:e7ca05fa8600 498
AnnaBridge 157:e7ca05fa8600 499
AnnaBridge 157:e7ca05fa8600 500 /**
AnnaBridge 157:e7ca05fa8600 501 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 502 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 157:e7ca05fa8600 503 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 157:e7ca05fa8600 504 @{
AnnaBridge 157:e7ca05fa8600 505 */
AnnaBridge 157:e7ca05fa8600 506
AnnaBridge 157:e7ca05fa8600 507 /**
AnnaBridge 157:e7ca05fa8600 508 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 157:e7ca05fa8600 509 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 510 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 511 \return Masked and shifted value.
AnnaBridge 157:e7ca05fa8600 512 */
AnnaBridge 157:e7ca05fa8600 513 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 157:e7ca05fa8600 514
AnnaBridge 157:e7ca05fa8600 515 /**
AnnaBridge 157:e7ca05fa8600 516 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 157:e7ca05fa8600 517 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 518 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 519 \return Masked and shifted bit field value.
AnnaBridge 157:e7ca05fa8600 520 */
AnnaBridge 157:e7ca05fa8600 521 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 157:e7ca05fa8600 522
AnnaBridge 157:e7ca05fa8600 523 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 157:e7ca05fa8600 524
AnnaBridge 157:e7ca05fa8600 525
AnnaBridge 157:e7ca05fa8600 526 /**
AnnaBridge 157:e7ca05fa8600 527 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 528 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 157:e7ca05fa8600 529 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 157:e7ca05fa8600 530 @{
AnnaBridge 157:e7ca05fa8600 531 */
AnnaBridge 157:e7ca05fa8600 532
AnnaBridge 157:e7ca05fa8600 533 /* Memory mapping of Core Hardware */
AnnaBridge 157:e7ca05fa8600 534 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 157:e7ca05fa8600 535 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 157:e7ca05fa8600 536 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 157:e7ca05fa8600 537 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 157:e7ca05fa8600 538
AnnaBridge 157:e7ca05fa8600 539 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 157:e7ca05fa8600 540 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 157:e7ca05fa8600 541 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 157:e7ca05fa8600 542
AnnaBridge 157:e7ca05fa8600 543
AnnaBridge 157:e7ca05fa8600 544 /*@} */
AnnaBridge 157:e7ca05fa8600 545
AnnaBridge 157:e7ca05fa8600 546
AnnaBridge 157:e7ca05fa8600 547
AnnaBridge 157:e7ca05fa8600 548 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 549 * Hardware Abstraction Layer
AnnaBridge 157:e7ca05fa8600 550 Core Function Interface contains:
AnnaBridge 157:e7ca05fa8600 551 - Core NVIC Functions
AnnaBridge 157:e7ca05fa8600 552 - Core SysTick Functions
AnnaBridge 157:e7ca05fa8600 553 - Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 554 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 555 /**
AnnaBridge 157:e7ca05fa8600 556 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 157:e7ca05fa8600 557 */
AnnaBridge 157:e7ca05fa8600 558
AnnaBridge 157:e7ca05fa8600 559
AnnaBridge 157:e7ca05fa8600 560
AnnaBridge 157:e7ca05fa8600 561 /* ########################## NVIC functions #################################### */
AnnaBridge 157:e7ca05fa8600 562 /**
AnnaBridge 157:e7ca05fa8600 563 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 564 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 157:e7ca05fa8600 565 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 157:e7ca05fa8600 566 @{
AnnaBridge 157:e7ca05fa8600 567 */
AnnaBridge 157:e7ca05fa8600 568
AnnaBridge 157:e7ca05fa8600 569 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 157:e7ca05fa8600 570 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 571 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 157:e7ca05fa8600 572 #endif
AnnaBridge 157:e7ca05fa8600 573 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 574 #else
AnnaBridge 157:e7ca05fa8600 575 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 576 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 577 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 157:e7ca05fa8600 578 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 157:e7ca05fa8600 579 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 157:e7ca05fa8600 580 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 157:e7ca05fa8600 581 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 157:e7ca05fa8600 582 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 157:e7ca05fa8600 583 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 584 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 157:e7ca05fa8600 585 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 157:e7ca05fa8600 586 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 157:e7ca05fa8600 587 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 157:e7ca05fa8600 590 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 591 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 157:e7ca05fa8600 592 #endif
AnnaBridge 157:e7ca05fa8600 593 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 594 #else
AnnaBridge 157:e7ca05fa8600 595 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 157:e7ca05fa8600 596 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 157:e7ca05fa8600 597 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 157:e7ca05fa8600 598
AnnaBridge 157:e7ca05fa8600 599 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 157:e7ca05fa8600 600
AnnaBridge 157:e7ca05fa8600 601
Anna Bridge 169:a7c7b631e539 602 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 157:e7ca05fa8600 603 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 157:e7ca05fa8600 604 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 157:e7ca05fa8600 605 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 606 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 607
AnnaBridge 157:e7ca05fa8600 608
AnnaBridge 157:e7ca05fa8600 609 /**
AnnaBridge 157:e7ca05fa8600 610 \brief Enable Interrupt
AnnaBridge 157:e7ca05fa8600 611 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 612 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 613 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 614 */
AnnaBridge 157:e7ca05fa8600 615 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 616 {
AnnaBridge 157:e7ca05fa8600 617 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 618 {
Anna Bridge 169:a7c7b631e539 619 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 620 }
AnnaBridge 157:e7ca05fa8600 621 }
AnnaBridge 157:e7ca05fa8600 622
AnnaBridge 157:e7ca05fa8600 623
AnnaBridge 157:e7ca05fa8600 624 /**
AnnaBridge 157:e7ca05fa8600 625 \brief Get Interrupt Enable status
AnnaBridge 157:e7ca05fa8600 626 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 627 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 628 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 629 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 630 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 631 */
AnnaBridge 157:e7ca05fa8600 632 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 633 {
AnnaBridge 157:e7ca05fa8600 634 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 635 {
Anna Bridge 169:a7c7b631e539 636 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 637 }
AnnaBridge 157:e7ca05fa8600 638 else
AnnaBridge 157:e7ca05fa8600 639 {
AnnaBridge 157:e7ca05fa8600 640 return(0U);
AnnaBridge 157:e7ca05fa8600 641 }
AnnaBridge 157:e7ca05fa8600 642 }
AnnaBridge 157:e7ca05fa8600 643
AnnaBridge 157:e7ca05fa8600 644
AnnaBridge 157:e7ca05fa8600 645 /**
AnnaBridge 157:e7ca05fa8600 646 \brief Disable Interrupt
AnnaBridge 157:e7ca05fa8600 647 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 648 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 649 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 650 */
AnnaBridge 157:e7ca05fa8600 651 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 652 {
AnnaBridge 157:e7ca05fa8600 653 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 654 {
Anna Bridge 169:a7c7b631e539 655 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 656 __DSB();
AnnaBridge 157:e7ca05fa8600 657 __ISB();
AnnaBridge 157:e7ca05fa8600 658 }
AnnaBridge 157:e7ca05fa8600 659 }
AnnaBridge 157:e7ca05fa8600 660
AnnaBridge 157:e7ca05fa8600 661
AnnaBridge 157:e7ca05fa8600 662 /**
AnnaBridge 157:e7ca05fa8600 663 \brief Get Pending Interrupt
AnnaBridge 157:e7ca05fa8600 664 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 665 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 666 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 667 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 668 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 669 */
AnnaBridge 157:e7ca05fa8600 670 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 671 {
AnnaBridge 157:e7ca05fa8600 672 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 673 {
Anna Bridge 169:a7c7b631e539 674 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 675 }
AnnaBridge 157:e7ca05fa8600 676 else
AnnaBridge 157:e7ca05fa8600 677 {
AnnaBridge 157:e7ca05fa8600 678 return(0U);
AnnaBridge 157:e7ca05fa8600 679 }
AnnaBridge 157:e7ca05fa8600 680 }
AnnaBridge 157:e7ca05fa8600 681
AnnaBridge 157:e7ca05fa8600 682
AnnaBridge 157:e7ca05fa8600 683 /**
AnnaBridge 157:e7ca05fa8600 684 \brief Set Pending Interrupt
AnnaBridge 157:e7ca05fa8600 685 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 686 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 687 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 688 */
AnnaBridge 157:e7ca05fa8600 689 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 690 {
AnnaBridge 157:e7ca05fa8600 691 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 692 {
Anna Bridge 169:a7c7b631e539 693 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 694 }
AnnaBridge 157:e7ca05fa8600 695 }
AnnaBridge 157:e7ca05fa8600 696
AnnaBridge 157:e7ca05fa8600 697
AnnaBridge 157:e7ca05fa8600 698 /**
AnnaBridge 157:e7ca05fa8600 699 \brief Clear Pending Interrupt
AnnaBridge 157:e7ca05fa8600 700 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 701 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 702 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 703 */
AnnaBridge 157:e7ca05fa8600 704 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 705 {
AnnaBridge 157:e7ca05fa8600 706 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 707 {
Anna Bridge 169:a7c7b631e539 708 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 709 }
AnnaBridge 157:e7ca05fa8600 710 }
AnnaBridge 157:e7ca05fa8600 711
AnnaBridge 157:e7ca05fa8600 712
AnnaBridge 157:e7ca05fa8600 713 /**
AnnaBridge 157:e7ca05fa8600 714 \brief Set Interrupt Priority
AnnaBridge 157:e7ca05fa8600 715 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 716 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 717 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 718 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 719 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 720 \note The priority cannot be set for every processor exception.
AnnaBridge 157:e7ca05fa8600 721 */
AnnaBridge 157:e7ca05fa8600 722 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 723 {
AnnaBridge 157:e7ca05fa8600 724 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 725 {
AnnaBridge 157:e7ca05fa8600 726 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 727 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 728 }
AnnaBridge 157:e7ca05fa8600 729 else
AnnaBridge 157:e7ca05fa8600 730 {
AnnaBridge 157:e7ca05fa8600 731 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 732 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 733 }
AnnaBridge 157:e7ca05fa8600 734 }
AnnaBridge 157:e7ca05fa8600 735
AnnaBridge 157:e7ca05fa8600 736
AnnaBridge 157:e7ca05fa8600 737 /**
AnnaBridge 157:e7ca05fa8600 738 \brief Get Interrupt Priority
AnnaBridge 157:e7ca05fa8600 739 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 740 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 741 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 742 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 743 \return Interrupt Priority.
AnnaBridge 157:e7ca05fa8600 744 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 745 */
AnnaBridge 157:e7ca05fa8600 746 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 747 {
AnnaBridge 157:e7ca05fa8600 748
AnnaBridge 157:e7ca05fa8600 749 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 750 {
AnnaBridge 157:e7ca05fa8600 751 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 752 }
AnnaBridge 157:e7ca05fa8600 753 else
AnnaBridge 157:e7ca05fa8600 754 {
AnnaBridge 157:e7ca05fa8600 755 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 756 }
AnnaBridge 157:e7ca05fa8600 757 }
AnnaBridge 157:e7ca05fa8600 758
AnnaBridge 157:e7ca05fa8600 759
AnnaBridge 157:e7ca05fa8600 760 /**
AnnaBridge 157:e7ca05fa8600 761 \brief Set Interrupt Vector
AnnaBridge 157:e7ca05fa8600 762 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 157:e7ca05fa8600 763 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 764 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 765 Address 0 must be mapped to SRAM.
AnnaBridge 157:e7ca05fa8600 766 \param [in] IRQn Interrupt number
AnnaBridge 157:e7ca05fa8600 767 \param [in] vector Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 768 */
AnnaBridge 157:e7ca05fa8600 769 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 157:e7ca05fa8600 770 {
AnnaBridge 157:e7ca05fa8600 771 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 772 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 157:e7ca05fa8600 773 }
AnnaBridge 157:e7ca05fa8600 774
AnnaBridge 157:e7ca05fa8600 775
AnnaBridge 157:e7ca05fa8600 776 /**
AnnaBridge 157:e7ca05fa8600 777 \brief Get Interrupt Vector
AnnaBridge 157:e7ca05fa8600 778 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 157:e7ca05fa8600 779 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 780 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 781 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 782 \return Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 783 */
AnnaBridge 157:e7ca05fa8600 784 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 785 {
AnnaBridge 157:e7ca05fa8600 786 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 787 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 157:e7ca05fa8600 788 }
AnnaBridge 157:e7ca05fa8600 789
AnnaBridge 157:e7ca05fa8600 790
AnnaBridge 157:e7ca05fa8600 791 /**
AnnaBridge 157:e7ca05fa8600 792 \brief System Reset
AnnaBridge 157:e7ca05fa8600 793 \details Initiates a system reset request to reset the MCU.
AnnaBridge 157:e7ca05fa8600 794 */
AnnaBridge 157:e7ca05fa8600 795 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 157:e7ca05fa8600 796 {
AnnaBridge 157:e7ca05fa8600 797 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 157:e7ca05fa8600 798 buffered write are completed before reset */
AnnaBridge 157:e7ca05fa8600 799 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 157:e7ca05fa8600 800 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 157:e7ca05fa8600 801 __DSB(); /* Ensure completion of memory access */
AnnaBridge 157:e7ca05fa8600 802
AnnaBridge 157:e7ca05fa8600 803 for(;;) /* wait until reset */
AnnaBridge 157:e7ca05fa8600 804 {
AnnaBridge 157:e7ca05fa8600 805 __NOP();
AnnaBridge 157:e7ca05fa8600 806 }
AnnaBridge 157:e7ca05fa8600 807 }
AnnaBridge 157:e7ca05fa8600 808
AnnaBridge 157:e7ca05fa8600 809 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 157:e7ca05fa8600 810
AnnaBridge 157:e7ca05fa8600 811
AnnaBridge 157:e7ca05fa8600 812 /* ########################## FPU functions #################################### */
AnnaBridge 157:e7ca05fa8600 813 /**
AnnaBridge 157:e7ca05fa8600 814 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 815 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 157:e7ca05fa8600 816 \brief Function that provides FPU type.
AnnaBridge 157:e7ca05fa8600 817 @{
AnnaBridge 157:e7ca05fa8600 818 */
AnnaBridge 157:e7ca05fa8600 819
AnnaBridge 157:e7ca05fa8600 820 /**
AnnaBridge 157:e7ca05fa8600 821 \brief get FPU type
AnnaBridge 157:e7ca05fa8600 822 \details returns the FPU type
AnnaBridge 157:e7ca05fa8600 823 \returns
AnnaBridge 157:e7ca05fa8600 824 - \b 0: No FPU
AnnaBridge 157:e7ca05fa8600 825 - \b 1: Single precision FPU
AnnaBridge 157:e7ca05fa8600 826 - \b 2: Double + Single precision FPU
AnnaBridge 157:e7ca05fa8600 827 */
AnnaBridge 157:e7ca05fa8600 828 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 157:e7ca05fa8600 829 {
AnnaBridge 157:e7ca05fa8600 830 return 0U; /* No FPU */
AnnaBridge 157:e7ca05fa8600 831 }
AnnaBridge 157:e7ca05fa8600 832
AnnaBridge 157:e7ca05fa8600 833
AnnaBridge 157:e7ca05fa8600 834 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 157:e7ca05fa8600 835
AnnaBridge 157:e7ca05fa8600 836
AnnaBridge 157:e7ca05fa8600 837
AnnaBridge 157:e7ca05fa8600 838 /* ################################## SysTick function ############################################ */
AnnaBridge 157:e7ca05fa8600 839 /**
AnnaBridge 157:e7ca05fa8600 840 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 841 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 157:e7ca05fa8600 842 \brief Functions that configure the System.
AnnaBridge 157:e7ca05fa8600 843 @{
AnnaBridge 157:e7ca05fa8600 844 */
AnnaBridge 157:e7ca05fa8600 845
AnnaBridge 157:e7ca05fa8600 846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 157:e7ca05fa8600 847
AnnaBridge 157:e7ca05fa8600 848 /**
AnnaBridge 157:e7ca05fa8600 849 \brief System Tick Configuration
AnnaBridge 157:e7ca05fa8600 850 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 851 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 852 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 853 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 854 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 856 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 857 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 858 */
AnnaBridge 157:e7ca05fa8600 859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 860 {
AnnaBridge 157:e7ca05fa8600 861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 862 {
AnnaBridge 157:e7ca05fa8600 863 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 864 }
AnnaBridge 157:e7ca05fa8600 865
AnnaBridge 157:e7ca05fa8600 866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 870 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 872 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 873 }
AnnaBridge 157:e7ca05fa8600 874
AnnaBridge 157:e7ca05fa8600 875 #endif
AnnaBridge 157:e7ca05fa8600 876
AnnaBridge 157:e7ca05fa8600 877 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 157:e7ca05fa8600 878
AnnaBridge 157:e7ca05fa8600 879
AnnaBridge 157:e7ca05fa8600 880
AnnaBridge 157:e7ca05fa8600 881
AnnaBridge 157:e7ca05fa8600 882 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 883 }
AnnaBridge 157:e7ca05fa8600 884 #endif
AnnaBridge 157:e7ca05fa8600 885
AnnaBridge 157:e7ca05fa8600 886 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 157:e7ca05fa8600 887
AnnaBridge 157:e7ca05fa8600 888 #endif /* __CMSIS_GENERIC */