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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L011K4/core_cm0.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file core_cm0.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 157:e7ca05fa8600 4 * @version V5.0.2
AnnaBridge 157:e7ca05fa8600 5 * @date 13. February 2017
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
AnnaBridge 157:e7ca05fa8600 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #if defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 157:e7ca05fa8600 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 157:e7ca05fa8600 29 #endif
AnnaBridge 157:e7ca05fa8600 30
AnnaBridge 157:e7ca05fa8600 31 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 157:e7ca05fa8600 32 #define __CORE_CM0_H_GENERIC
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 #include <stdint.h>
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 37 extern "C" {
AnnaBridge 157:e7ca05fa8600 38 #endif
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 /**
AnnaBridge 157:e7ca05fa8600 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 157:e7ca05fa8600 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 157:e7ca05fa8600 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 157:e7ca05fa8600 48 Unions are used for effective representation of core registers.
AnnaBridge 157:e7ca05fa8600 49
AnnaBridge 157:e7ca05fa8600 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 157:e7ca05fa8600 51 Function-like macros are used to allow more efficient code.
AnnaBridge 157:e7ca05fa8600 52 */
AnnaBridge 157:e7ca05fa8600 53
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 56 * CMSIS definitions
AnnaBridge 157:e7ca05fa8600 57 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 \ingroup Cortex_M0
AnnaBridge 157:e7ca05fa8600 60 @{
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62
AnnaBridge 157:e7ca05fa8600 63 /* CMSIS CM0 definitions */
AnnaBridge 157:e7ca05fa8600 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 157:e7ca05fa8600 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 157:e7ca05fa8600 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 157:e7ca05fa8600 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 157:e7ca05fa8600 68
AnnaBridge 157:e7ca05fa8600 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 157:e7ca05fa8600 72 This core does not support an FPU at all
AnnaBridge 157:e7ca05fa8600 73 */
AnnaBridge 157:e7ca05fa8600 74 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 75
AnnaBridge 157:e7ca05fa8600 76 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 77 #if defined __TARGET_FPU_VFP
AnnaBridge 157:e7ca05fa8600 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 79 #endif
AnnaBridge 157:e7ca05fa8600 80
AnnaBridge 157:e7ca05fa8600 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 82 #if defined __ARM_PCS_VFP
AnnaBridge 157:e7ca05fa8600 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 84 #endif
AnnaBridge 157:e7ca05fa8600 85
AnnaBridge 157:e7ca05fa8600 86 #elif defined ( __GNUC__ )
AnnaBridge 157:e7ca05fa8600 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 157:e7ca05fa8600 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 89 #endif
AnnaBridge 157:e7ca05fa8600 90
AnnaBridge 157:e7ca05fa8600 91 #elif defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 92 #if defined __ARMVFP__
AnnaBridge 157:e7ca05fa8600 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 94 #endif
AnnaBridge 157:e7ca05fa8600 95
AnnaBridge 157:e7ca05fa8600 96 #elif defined ( __TI_ARM__ )
AnnaBridge 157:e7ca05fa8600 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 157:e7ca05fa8600 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 99 #endif
AnnaBridge 157:e7ca05fa8600 100
AnnaBridge 157:e7ca05fa8600 101 #elif defined ( __TASKING__ )
AnnaBridge 157:e7ca05fa8600 102 #if defined __FPU_VFP__
AnnaBridge 157:e7ca05fa8600 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 104 #endif
AnnaBridge 157:e7ca05fa8600 105
AnnaBridge 157:e7ca05fa8600 106 #elif defined ( __CSMC__ )
AnnaBridge 157:e7ca05fa8600 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 157:e7ca05fa8600 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 109 #endif
AnnaBridge 157:e7ca05fa8600 110
AnnaBridge 157:e7ca05fa8600 111 #endif
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 114
AnnaBridge 157:e7ca05fa8600 115
AnnaBridge 157:e7ca05fa8600 116 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 117 }
AnnaBridge 157:e7ca05fa8600 118 #endif
AnnaBridge 157:e7ca05fa8600 119
AnnaBridge 157:e7ca05fa8600 120 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 157:e7ca05fa8600 121
AnnaBridge 157:e7ca05fa8600 122 #ifndef __CMSIS_GENERIC
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 125 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 126
AnnaBridge 157:e7ca05fa8600 127 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 128 extern "C" {
AnnaBridge 157:e7ca05fa8600 129 #endif
AnnaBridge 157:e7ca05fa8600 130
AnnaBridge 157:e7ca05fa8600 131 /* check device defines and use defaults */
AnnaBridge 157:e7ca05fa8600 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 157:e7ca05fa8600 133 #ifndef __CM0_REV
AnnaBridge 157:e7ca05fa8600 134 #define __CM0_REV 0x0000U
AnnaBridge 157:e7ca05fa8600 135 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 136 #endif
AnnaBridge 157:e7ca05fa8600 137
AnnaBridge 157:e7ca05fa8600 138 #ifndef __NVIC_PRIO_BITS
AnnaBridge 157:e7ca05fa8600 139 #define __NVIC_PRIO_BITS 2U
AnnaBridge 157:e7ca05fa8600 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 141 #endif
AnnaBridge 157:e7ca05fa8600 142
AnnaBridge 157:e7ca05fa8600 143 #ifndef __Vendor_SysTickConfig
AnnaBridge 157:e7ca05fa8600 144 #define __Vendor_SysTickConfig 0U
AnnaBridge 157:e7ca05fa8600 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 146 #endif
AnnaBridge 157:e7ca05fa8600 147 #endif
AnnaBridge 157:e7ca05fa8600 148
AnnaBridge 157:e7ca05fa8600 149 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 157:e7ca05fa8600 150 /**
AnnaBridge 157:e7ca05fa8600 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 157:e7ca05fa8600 152
AnnaBridge 157:e7ca05fa8600 153 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 157:e7ca05fa8600 154 \li to specify the access to peripheral variables.
AnnaBridge 157:e7ca05fa8600 155 \li for automatic generation of peripheral register debug information.
AnnaBridge 157:e7ca05fa8600 156 */
AnnaBridge 157:e7ca05fa8600 157 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 158 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 159 #else
AnnaBridge 157:e7ca05fa8600 160 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 161 #endif
AnnaBridge 157:e7ca05fa8600 162 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 157:e7ca05fa8600 163 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 157:e7ca05fa8600 164
AnnaBridge 157:e7ca05fa8600 165 /* following defines should be used for structure members */
AnnaBridge 157:e7ca05fa8600 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 157:e7ca05fa8600 169
AnnaBridge 157:e7ca05fa8600 170 /*@} end of group Cortex_M0 */
AnnaBridge 157:e7ca05fa8600 171
AnnaBridge 157:e7ca05fa8600 172
AnnaBridge 157:e7ca05fa8600 173
AnnaBridge 157:e7ca05fa8600 174 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 175 * Register Abstraction
AnnaBridge 157:e7ca05fa8600 176 Core Register contain:
AnnaBridge 157:e7ca05fa8600 177 - Core Register
AnnaBridge 157:e7ca05fa8600 178 - Core NVIC Register
AnnaBridge 157:e7ca05fa8600 179 - Core SCB Register
AnnaBridge 157:e7ca05fa8600 180 - Core SysTick Register
AnnaBridge 157:e7ca05fa8600 181 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 182 /**
AnnaBridge 157:e7ca05fa8600 183 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 157:e7ca05fa8600 184 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 157:e7ca05fa8600 185 */
AnnaBridge 157:e7ca05fa8600 186
AnnaBridge 157:e7ca05fa8600 187 /**
AnnaBridge 157:e7ca05fa8600 188 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 189 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 157:e7ca05fa8600 190 \brief Core Register type definitions.
AnnaBridge 157:e7ca05fa8600 191 @{
AnnaBridge 157:e7ca05fa8600 192 */
AnnaBridge 157:e7ca05fa8600 193
AnnaBridge 157:e7ca05fa8600 194 /**
AnnaBridge 157:e7ca05fa8600 195 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 157:e7ca05fa8600 196 */
AnnaBridge 157:e7ca05fa8600 197 typedef union
AnnaBridge 157:e7ca05fa8600 198 {
AnnaBridge 157:e7ca05fa8600 199 struct
AnnaBridge 157:e7ca05fa8600 200 {
AnnaBridge 157:e7ca05fa8600 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 157:e7ca05fa8600 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 206 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 207 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 208 } APSR_Type;
AnnaBridge 157:e7ca05fa8600 209
AnnaBridge 157:e7ca05fa8600 210 /* APSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 157:e7ca05fa8600 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 157:e7ca05fa8600 213
AnnaBridge 157:e7ca05fa8600 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 157:e7ca05fa8600 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 216
AnnaBridge 157:e7ca05fa8600 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 157:e7ca05fa8600 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 157:e7ca05fa8600 219
AnnaBridge 157:e7ca05fa8600 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 157:e7ca05fa8600 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 157:e7ca05fa8600 222
AnnaBridge 157:e7ca05fa8600 223
AnnaBridge 157:e7ca05fa8600 224 /**
AnnaBridge 157:e7ca05fa8600 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 157:e7ca05fa8600 226 */
AnnaBridge 157:e7ca05fa8600 227 typedef union
AnnaBridge 157:e7ca05fa8600 228 {
AnnaBridge 157:e7ca05fa8600 229 struct
AnnaBridge 157:e7ca05fa8600 230 {
AnnaBridge 157:e7ca05fa8600 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 157:e7ca05fa8600 233 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 234 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 235 } IPSR_Type;
AnnaBridge 157:e7ca05fa8600 236
AnnaBridge 157:e7ca05fa8600 237 /* IPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 240
AnnaBridge 157:e7ca05fa8600 241
AnnaBridge 157:e7ca05fa8600 242 /**
AnnaBridge 157:e7ca05fa8600 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 157:e7ca05fa8600 244 */
AnnaBridge 157:e7ca05fa8600 245 typedef union
AnnaBridge 157:e7ca05fa8600 246 {
AnnaBridge 157:e7ca05fa8600 247 struct
AnnaBridge 157:e7ca05fa8600 248 {
AnnaBridge 157:e7ca05fa8600 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 157:e7ca05fa8600 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 157:e7ca05fa8600 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 157:e7ca05fa8600 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 257 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 258 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 259 } xPSR_Type;
AnnaBridge 157:e7ca05fa8600 260
AnnaBridge 157:e7ca05fa8600 261 /* xPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 157:e7ca05fa8600 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 157:e7ca05fa8600 264
AnnaBridge 157:e7ca05fa8600 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 157:e7ca05fa8600 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 267
AnnaBridge 157:e7ca05fa8600 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 157:e7ca05fa8600 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 157:e7ca05fa8600 270
AnnaBridge 157:e7ca05fa8600 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 157:e7ca05fa8600 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 157:e7ca05fa8600 273
AnnaBridge 157:e7ca05fa8600 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 157:e7ca05fa8600 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 157:e7ca05fa8600 276
AnnaBridge 157:e7ca05fa8600 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 279
AnnaBridge 157:e7ca05fa8600 280
AnnaBridge 157:e7ca05fa8600 281 /**
AnnaBridge 157:e7ca05fa8600 282 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 157:e7ca05fa8600 283 */
AnnaBridge 157:e7ca05fa8600 284 typedef union
AnnaBridge 157:e7ca05fa8600 285 {
AnnaBridge 157:e7ca05fa8600 286 struct
AnnaBridge 157:e7ca05fa8600 287 {
AnnaBridge 157:e7ca05fa8600 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 157:e7ca05fa8600 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 157:e7ca05fa8600 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 157:e7ca05fa8600 291 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 292 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 293 } CONTROL_Type;
AnnaBridge 157:e7ca05fa8600 294
AnnaBridge 157:e7ca05fa8600 295 /* CONTROL Register Definitions */
AnnaBridge 157:e7ca05fa8600 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 157:e7ca05fa8600 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 157:e7ca05fa8600 298
AnnaBridge 157:e7ca05fa8600 299 /*@} end of group CMSIS_CORE */
AnnaBridge 157:e7ca05fa8600 300
AnnaBridge 157:e7ca05fa8600 301
AnnaBridge 157:e7ca05fa8600 302 /**
AnnaBridge 157:e7ca05fa8600 303 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 157:e7ca05fa8600 305 \brief Type definitions for the NVIC Registers
AnnaBridge 157:e7ca05fa8600 306 @{
AnnaBridge 157:e7ca05fa8600 307 */
AnnaBridge 157:e7ca05fa8600 308
AnnaBridge 157:e7ca05fa8600 309 /**
AnnaBridge 157:e7ca05fa8600 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 157:e7ca05fa8600 311 */
AnnaBridge 157:e7ca05fa8600 312 typedef struct
AnnaBridge 157:e7ca05fa8600 313 {
AnnaBridge 157:e7ca05fa8600 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 157:e7ca05fa8600 315 uint32_t RESERVED0[31U];
AnnaBridge 157:e7ca05fa8600 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 157:e7ca05fa8600 317 uint32_t RSERVED1[31U];
AnnaBridge 157:e7ca05fa8600 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 157:e7ca05fa8600 319 uint32_t RESERVED2[31U];
AnnaBridge 157:e7ca05fa8600 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 157:e7ca05fa8600 321 uint32_t RESERVED3[31U];
AnnaBridge 157:e7ca05fa8600 322 uint32_t RESERVED4[64U];
AnnaBridge 157:e7ca05fa8600 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 157:e7ca05fa8600 324 } NVIC_Type;
AnnaBridge 157:e7ca05fa8600 325
AnnaBridge 157:e7ca05fa8600 326 /*@} end of group CMSIS_NVIC */
AnnaBridge 157:e7ca05fa8600 327
AnnaBridge 157:e7ca05fa8600 328
AnnaBridge 157:e7ca05fa8600 329 /**
AnnaBridge 157:e7ca05fa8600 330 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 331 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 157:e7ca05fa8600 332 \brief Type definitions for the System Control Block Registers
AnnaBridge 157:e7ca05fa8600 333 @{
AnnaBridge 157:e7ca05fa8600 334 */
AnnaBridge 157:e7ca05fa8600 335
AnnaBridge 157:e7ca05fa8600 336 /**
AnnaBridge 157:e7ca05fa8600 337 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 157:e7ca05fa8600 338 */
AnnaBridge 157:e7ca05fa8600 339 typedef struct
AnnaBridge 157:e7ca05fa8600 340 {
AnnaBridge 157:e7ca05fa8600 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 157:e7ca05fa8600 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 157:e7ca05fa8600 343 uint32_t RESERVED0;
AnnaBridge 157:e7ca05fa8600 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 157:e7ca05fa8600 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 157:e7ca05fa8600 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 157:e7ca05fa8600 347 uint32_t RESERVED1;
AnnaBridge 157:e7ca05fa8600 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 157:e7ca05fa8600 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 157:e7ca05fa8600 350 } SCB_Type;
AnnaBridge 157:e7ca05fa8600 351
AnnaBridge 157:e7ca05fa8600 352 /* SCB CPUID Register Definitions */
AnnaBridge 157:e7ca05fa8600 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 157:e7ca05fa8600 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 157:e7ca05fa8600 355
AnnaBridge 157:e7ca05fa8600 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 157:e7ca05fa8600 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 157:e7ca05fa8600 358
AnnaBridge 157:e7ca05fa8600 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 157:e7ca05fa8600 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 157:e7ca05fa8600 361
AnnaBridge 157:e7ca05fa8600 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 157:e7ca05fa8600 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 157:e7ca05fa8600 364
AnnaBridge 157:e7ca05fa8600 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 157:e7ca05fa8600 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 157:e7ca05fa8600 367
AnnaBridge 157:e7ca05fa8600 368 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 157:e7ca05fa8600 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 157:e7ca05fa8600 371
AnnaBridge 157:e7ca05fa8600 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 157:e7ca05fa8600 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 157:e7ca05fa8600 374
AnnaBridge 157:e7ca05fa8600 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 157:e7ca05fa8600 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 157:e7ca05fa8600 377
AnnaBridge 157:e7ca05fa8600 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 157:e7ca05fa8600 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 157:e7ca05fa8600 380
AnnaBridge 157:e7ca05fa8600 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 157:e7ca05fa8600 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 157:e7ca05fa8600 383
AnnaBridge 157:e7ca05fa8600 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 157:e7ca05fa8600 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 157:e7ca05fa8600 386
AnnaBridge 157:e7ca05fa8600 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 157:e7ca05fa8600 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 157:e7ca05fa8600 389
AnnaBridge 157:e7ca05fa8600 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 157:e7ca05fa8600 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 157:e7ca05fa8600 392
AnnaBridge 157:e7ca05fa8600 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 157:e7ca05fa8600 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 395
AnnaBridge 157:e7ca05fa8600 396 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 157:e7ca05fa8600 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 157:e7ca05fa8600 399
AnnaBridge 157:e7ca05fa8600 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 157:e7ca05fa8600 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 157:e7ca05fa8600 402
AnnaBridge 157:e7ca05fa8600 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 157:e7ca05fa8600 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 157:e7ca05fa8600 405
AnnaBridge 157:e7ca05fa8600 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 157:e7ca05fa8600 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 157:e7ca05fa8600 408
AnnaBridge 157:e7ca05fa8600 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 157:e7ca05fa8600 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 411
AnnaBridge 157:e7ca05fa8600 412 /* SCB System Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 157:e7ca05fa8600 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 157:e7ca05fa8600 415
AnnaBridge 157:e7ca05fa8600 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 157:e7ca05fa8600 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 157:e7ca05fa8600 418
AnnaBridge 157:e7ca05fa8600 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 157:e7ca05fa8600 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 157:e7ca05fa8600 421
AnnaBridge 157:e7ca05fa8600 422 /* SCB Configuration Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 157:e7ca05fa8600 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 157:e7ca05fa8600 425
AnnaBridge 157:e7ca05fa8600 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 157:e7ca05fa8600 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 157:e7ca05fa8600 428
AnnaBridge 157:e7ca05fa8600 429 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 157:e7ca05fa8600 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 157:e7ca05fa8600 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 157:e7ca05fa8600 432
AnnaBridge 157:e7ca05fa8600 433 /*@} end of group CMSIS_SCB */
AnnaBridge 157:e7ca05fa8600 434
AnnaBridge 157:e7ca05fa8600 435
AnnaBridge 157:e7ca05fa8600 436 /**
AnnaBridge 157:e7ca05fa8600 437 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 157:e7ca05fa8600 439 \brief Type definitions for the System Timer Registers.
AnnaBridge 157:e7ca05fa8600 440 @{
AnnaBridge 157:e7ca05fa8600 441 */
AnnaBridge 157:e7ca05fa8600 442
AnnaBridge 157:e7ca05fa8600 443 /**
AnnaBridge 157:e7ca05fa8600 444 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 157:e7ca05fa8600 445 */
AnnaBridge 157:e7ca05fa8600 446 typedef struct
AnnaBridge 157:e7ca05fa8600 447 {
AnnaBridge 157:e7ca05fa8600 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 157:e7ca05fa8600 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 157:e7ca05fa8600 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 157:e7ca05fa8600 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 157:e7ca05fa8600 452 } SysTick_Type;
AnnaBridge 157:e7ca05fa8600 453
AnnaBridge 157:e7ca05fa8600 454 /* SysTick Control / Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 157:e7ca05fa8600 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 157:e7ca05fa8600 457
AnnaBridge 157:e7ca05fa8600 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 157:e7ca05fa8600 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 157:e7ca05fa8600 460
AnnaBridge 157:e7ca05fa8600 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 157:e7ca05fa8600 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 157:e7ca05fa8600 463
AnnaBridge 157:e7ca05fa8600 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 466
AnnaBridge 157:e7ca05fa8600 467 /* SysTick Reload Register Definitions */
AnnaBridge 157:e7ca05fa8600 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 157:e7ca05fa8600 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 157:e7ca05fa8600 470
AnnaBridge 157:e7ca05fa8600 471 /* SysTick Current Register Definitions */
AnnaBridge 157:e7ca05fa8600 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 157:e7ca05fa8600 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 157:e7ca05fa8600 474
AnnaBridge 157:e7ca05fa8600 475 /* SysTick Calibration Register Definitions */
AnnaBridge 157:e7ca05fa8600 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 157:e7ca05fa8600 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 157:e7ca05fa8600 478
AnnaBridge 157:e7ca05fa8600 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 157:e7ca05fa8600 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 157:e7ca05fa8600 481
AnnaBridge 157:e7ca05fa8600 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 157:e7ca05fa8600 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 157:e7ca05fa8600 484
AnnaBridge 157:e7ca05fa8600 485 /*@} end of group CMSIS_SysTick */
AnnaBridge 157:e7ca05fa8600 486
AnnaBridge 157:e7ca05fa8600 487
AnnaBridge 157:e7ca05fa8600 488 /**
AnnaBridge 157:e7ca05fa8600 489 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 157:e7ca05fa8600 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 157:e7ca05fa8600 492 Therefore they are not covered by the Cortex-M0 header file.
AnnaBridge 157:e7ca05fa8600 493 @{
AnnaBridge 157:e7ca05fa8600 494 */
AnnaBridge 157:e7ca05fa8600 495 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 157:e7ca05fa8600 496
AnnaBridge 157:e7ca05fa8600 497
AnnaBridge 157:e7ca05fa8600 498 /**
AnnaBridge 157:e7ca05fa8600 499 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 500 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 157:e7ca05fa8600 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 157:e7ca05fa8600 502 @{
AnnaBridge 157:e7ca05fa8600 503 */
AnnaBridge 157:e7ca05fa8600 504
AnnaBridge 157:e7ca05fa8600 505 /**
AnnaBridge 157:e7ca05fa8600 506 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 157:e7ca05fa8600 507 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 509 \return Masked and shifted value.
AnnaBridge 157:e7ca05fa8600 510 */
AnnaBridge 157:e7ca05fa8600 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 157:e7ca05fa8600 512
AnnaBridge 157:e7ca05fa8600 513 /**
AnnaBridge 157:e7ca05fa8600 514 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 157:e7ca05fa8600 515 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 517 \return Masked and shifted bit field value.
AnnaBridge 157:e7ca05fa8600 518 */
AnnaBridge 157:e7ca05fa8600 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 157:e7ca05fa8600 520
AnnaBridge 157:e7ca05fa8600 521 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 157:e7ca05fa8600 522
AnnaBridge 157:e7ca05fa8600 523
AnnaBridge 157:e7ca05fa8600 524 /**
AnnaBridge 157:e7ca05fa8600 525 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 526 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 157:e7ca05fa8600 527 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 157:e7ca05fa8600 528 @{
AnnaBridge 157:e7ca05fa8600 529 */
AnnaBridge 157:e7ca05fa8600 530
AnnaBridge 157:e7ca05fa8600 531 /* Memory mapping of Core Hardware */
AnnaBridge 157:e7ca05fa8600 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 157:e7ca05fa8600 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 157:e7ca05fa8600 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 157:e7ca05fa8600 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 157:e7ca05fa8600 536
AnnaBridge 157:e7ca05fa8600 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 157:e7ca05fa8600 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 157:e7ca05fa8600 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 157:e7ca05fa8600 540
AnnaBridge 157:e7ca05fa8600 541
AnnaBridge 157:e7ca05fa8600 542 /*@} */
AnnaBridge 157:e7ca05fa8600 543
AnnaBridge 157:e7ca05fa8600 544
AnnaBridge 157:e7ca05fa8600 545
AnnaBridge 157:e7ca05fa8600 546 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 547 * Hardware Abstraction Layer
AnnaBridge 157:e7ca05fa8600 548 Core Function Interface contains:
AnnaBridge 157:e7ca05fa8600 549 - Core NVIC Functions
AnnaBridge 157:e7ca05fa8600 550 - Core SysTick Functions
AnnaBridge 157:e7ca05fa8600 551 - Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 552 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 553 /**
AnnaBridge 157:e7ca05fa8600 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 157:e7ca05fa8600 555 */
AnnaBridge 157:e7ca05fa8600 556
AnnaBridge 157:e7ca05fa8600 557
AnnaBridge 157:e7ca05fa8600 558
AnnaBridge 157:e7ca05fa8600 559 /* ########################## NVIC functions #################################### */
AnnaBridge 157:e7ca05fa8600 560 /**
AnnaBridge 157:e7ca05fa8600 561 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 157:e7ca05fa8600 563 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 157:e7ca05fa8600 564 @{
AnnaBridge 157:e7ca05fa8600 565 */
AnnaBridge 157:e7ca05fa8600 566
AnnaBridge 157:e7ca05fa8600 567 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 157:e7ca05fa8600 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 157:e7ca05fa8600 570 #endif
AnnaBridge 157:e7ca05fa8600 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 572 #else
AnnaBridge 157:e7ca05fa8600 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 157:e7ca05fa8600 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 157:e7ca05fa8600 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 157:e7ca05fa8600 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 157:e7ca05fa8600 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 157:e7ca05fa8600 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 157:e7ca05fa8600 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 157:e7ca05fa8600 582 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 157:e7ca05fa8600 583 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 157:e7ca05fa8600 584 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 157:e7ca05fa8600 585 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 157:e7ca05fa8600 586
AnnaBridge 157:e7ca05fa8600 587 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 157:e7ca05fa8600 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 157:e7ca05fa8600 590 #endif
AnnaBridge 157:e7ca05fa8600 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 592 #else
AnnaBridge 157:e7ca05fa8600 593 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 157:e7ca05fa8600 594 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 157:e7ca05fa8600 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 157:e7ca05fa8600 596
AnnaBridge 157:e7ca05fa8600 597 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 157:e7ca05fa8600 598
AnnaBridge 157:e7ca05fa8600 599
AnnaBridge 157:e7ca05fa8600 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 157:e7ca05fa8600 601 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 157:e7ca05fa8600 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 157:e7ca05fa8600 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 605
AnnaBridge 157:e7ca05fa8600 606
AnnaBridge 157:e7ca05fa8600 607 /**
AnnaBridge 157:e7ca05fa8600 608 \brief Enable Interrupt
AnnaBridge 157:e7ca05fa8600 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 610 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 611 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 612 */
AnnaBridge 157:e7ca05fa8600 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 614 {
AnnaBridge 157:e7ca05fa8600 615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 616 {
AnnaBridge 157:e7ca05fa8600 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 618 }
AnnaBridge 157:e7ca05fa8600 619 }
AnnaBridge 157:e7ca05fa8600 620
AnnaBridge 157:e7ca05fa8600 621
AnnaBridge 157:e7ca05fa8600 622 /**
AnnaBridge 157:e7ca05fa8600 623 \brief Get Interrupt Enable status
AnnaBridge 157:e7ca05fa8600 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 625 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 626 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 627 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 628 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 629 */
AnnaBridge 157:e7ca05fa8600 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 631 {
AnnaBridge 157:e7ca05fa8600 632 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 633 {
AnnaBridge 157:e7ca05fa8600 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 635 }
AnnaBridge 157:e7ca05fa8600 636 else
AnnaBridge 157:e7ca05fa8600 637 {
AnnaBridge 157:e7ca05fa8600 638 return(0U);
AnnaBridge 157:e7ca05fa8600 639 }
AnnaBridge 157:e7ca05fa8600 640 }
AnnaBridge 157:e7ca05fa8600 641
AnnaBridge 157:e7ca05fa8600 642
AnnaBridge 157:e7ca05fa8600 643 /**
AnnaBridge 157:e7ca05fa8600 644 \brief Disable Interrupt
AnnaBridge 157:e7ca05fa8600 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 646 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 647 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 648 */
AnnaBridge 157:e7ca05fa8600 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 650 {
AnnaBridge 157:e7ca05fa8600 651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 652 {
AnnaBridge 157:e7ca05fa8600 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 654 __DSB();
AnnaBridge 157:e7ca05fa8600 655 __ISB();
AnnaBridge 157:e7ca05fa8600 656 }
AnnaBridge 157:e7ca05fa8600 657 }
AnnaBridge 157:e7ca05fa8600 658
AnnaBridge 157:e7ca05fa8600 659
AnnaBridge 157:e7ca05fa8600 660 /**
AnnaBridge 157:e7ca05fa8600 661 \brief Get Pending Interrupt
AnnaBridge 157:e7ca05fa8600 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 663 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 664 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 665 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 666 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 667 */
AnnaBridge 157:e7ca05fa8600 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 669 {
AnnaBridge 157:e7ca05fa8600 670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 671 {
AnnaBridge 157:e7ca05fa8600 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 673 }
AnnaBridge 157:e7ca05fa8600 674 else
AnnaBridge 157:e7ca05fa8600 675 {
AnnaBridge 157:e7ca05fa8600 676 return(0U);
AnnaBridge 157:e7ca05fa8600 677 }
AnnaBridge 157:e7ca05fa8600 678 }
AnnaBridge 157:e7ca05fa8600 679
AnnaBridge 157:e7ca05fa8600 680
AnnaBridge 157:e7ca05fa8600 681 /**
AnnaBridge 157:e7ca05fa8600 682 \brief Set Pending Interrupt
AnnaBridge 157:e7ca05fa8600 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 684 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 685 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 686 */
AnnaBridge 157:e7ca05fa8600 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 688 {
AnnaBridge 157:e7ca05fa8600 689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 690 {
AnnaBridge 157:e7ca05fa8600 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 692 }
AnnaBridge 157:e7ca05fa8600 693 }
AnnaBridge 157:e7ca05fa8600 694
AnnaBridge 157:e7ca05fa8600 695
AnnaBridge 157:e7ca05fa8600 696 /**
AnnaBridge 157:e7ca05fa8600 697 \brief Clear Pending Interrupt
AnnaBridge 157:e7ca05fa8600 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 699 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 700 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 701 */
AnnaBridge 157:e7ca05fa8600 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 703 {
AnnaBridge 157:e7ca05fa8600 704 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 705 {
AnnaBridge 157:e7ca05fa8600 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 707 }
AnnaBridge 157:e7ca05fa8600 708 }
AnnaBridge 157:e7ca05fa8600 709
AnnaBridge 157:e7ca05fa8600 710
AnnaBridge 157:e7ca05fa8600 711 /**
AnnaBridge 157:e7ca05fa8600 712 \brief Set Interrupt Priority
AnnaBridge 157:e7ca05fa8600 713 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 714 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 715 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 716 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 717 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 718 \note The priority cannot be set for every processor exception.
AnnaBridge 157:e7ca05fa8600 719 */
AnnaBridge 157:e7ca05fa8600 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 721 {
AnnaBridge 157:e7ca05fa8600 722 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 723 {
AnnaBridge 157:e7ca05fa8600 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 726 }
AnnaBridge 157:e7ca05fa8600 727 else
AnnaBridge 157:e7ca05fa8600 728 {
AnnaBridge 157:e7ca05fa8600 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 731 }
AnnaBridge 157:e7ca05fa8600 732 }
AnnaBridge 157:e7ca05fa8600 733
AnnaBridge 157:e7ca05fa8600 734
AnnaBridge 157:e7ca05fa8600 735 /**
AnnaBridge 157:e7ca05fa8600 736 \brief Get Interrupt Priority
AnnaBridge 157:e7ca05fa8600 737 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 739 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 740 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 741 \return Interrupt Priority.
AnnaBridge 157:e7ca05fa8600 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 743 */
AnnaBridge 157:e7ca05fa8600 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 745 {
AnnaBridge 157:e7ca05fa8600 746
AnnaBridge 157:e7ca05fa8600 747 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 748 {
AnnaBridge 157:e7ca05fa8600 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 750 }
AnnaBridge 157:e7ca05fa8600 751 else
AnnaBridge 157:e7ca05fa8600 752 {
AnnaBridge 157:e7ca05fa8600 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 754 }
AnnaBridge 157:e7ca05fa8600 755 }
AnnaBridge 157:e7ca05fa8600 756
AnnaBridge 157:e7ca05fa8600 757
AnnaBridge 157:e7ca05fa8600 758 /**
AnnaBridge 157:e7ca05fa8600 759 \brief Set Interrupt Vector
AnnaBridge 157:e7ca05fa8600 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 157:e7ca05fa8600 761 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 762 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 763 Address 0 must be mapped to SRAM.
AnnaBridge 157:e7ca05fa8600 764 \param [in] IRQn Interrupt number
AnnaBridge 157:e7ca05fa8600 765 \param [in] vector Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 766 */
AnnaBridge 157:e7ca05fa8600 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 157:e7ca05fa8600 768 {
AnnaBridge 157:e7ca05fa8600 769 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 157:e7ca05fa8600 771 }
AnnaBridge 157:e7ca05fa8600 772
AnnaBridge 157:e7ca05fa8600 773
AnnaBridge 157:e7ca05fa8600 774 /**
AnnaBridge 157:e7ca05fa8600 775 \brief Get Interrupt Vector
AnnaBridge 157:e7ca05fa8600 776 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 157:e7ca05fa8600 777 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 778 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 779 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 780 \return Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 781 */
AnnaBridge 157:e7ca05fa8600 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 783 {
AnnaBridge 157:e7ca05fa8600 784 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 157:e7ca05fa8600 786 }
AnnaBridge 157:e7ca05fa8600 787
AnnaBridge 157:e7ca05fa8600 788
AnnaBridge 157:e7ca05fa8600 789 /**
AnnaBridge 157:e7ca05fa8600 790 \brief System Reset
AnnaBridge 157:e7ca05fa8600 791 \details Initiates a system reset request to reset the MCU.
AnnaBridge 157:e7ca05fa8600 792 */
AnnaBridge 157:e7ca05fa8600 793 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 157:e7ca05fa8600 794 {
AnnaBridge 157:e7ca05fa8600 795 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 157:e7ca05fa8600 796 buffered write are completed before reset */
AnnaBridge 157:e7ca05fa8600 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 157:e7ca05fa8600 798 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 157:e7ca05fa8600 799 __DSB(); /* Ensure completion of memory access */
AnnaBridge 157:e7ca05fa8600 800
AnnaBridge 157:e7ca05fa8600 801 for(;;) /* wait until reset */
AnnaBridge 157:e7ca05fa8600 802 {
AnnaBridge 157:e7ca05fa8600 803 __NOP();
AnnaBridge 157:e7ca05fa8600 804 }
AnnaBridge 157:e7ca05fa8600 805 }
AnnaBridge 157:e7ca05fa8600 806
AnnaBridge 157:e7ca05fa8600 807 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 157:e7ca05fa8600 808
AnnaBridge 157:e7ca05fa8600 809
AnnaBridge 157:e7ca05fa8600 810 /* ########################## FPU functions #################################### */
AnnaBridge 157:e7ca05fa8600 811 /**
AnnaBridge 157:e7ca05fa8600 812 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 157:e7ca05fa8600 814 \brief Function that provides FPU type.
AnnaBridge 157:e7ca05fa8600 815 @{
AnnaBridge 157:e7ca05fa8600 816 */
AnnaBridge 157:e7ca05fa8600 817
AnnaBridge 157:e7ca05fa8600 818 /**
AnnaBridge 157:e7ca05fa8600 819 \brief get FPU type
AnnaBridge 157:e7ca05fa8600 820 \details returns the FPU type
AnnaBridge 157:e7ca05fa8600 821 \returns
AnnaBridge 157:e7ca05fa8600 822 - \b 0: No FPU
AnnaBridge 157:e7ca05fa8600 823 - \b 1: Single precision FPU
AnnaBridge 157:e7ca05fa8600 824 - \b 2: Double + Single precision FPU
AnnaBridge 157:e7ca05fa8600 825 */
AnnaBridge 157:e7ca05fa8600 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 157:e7ca05fa8600 827 {
AnnaBridge 157:e7ca05fa8600 828 return 0U; /* No FPU */
AnnaBridge 157:e7ca05fa8600 829 }
AnnaBridge 157:e7ca05fa8600 830
AnnaBridge 157:e7ca05fa8600 831
AnnaBridge 157:e7ca05fa8600 832 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 157:e7ca05fa8600 833
AnnaBridge 157:e7ca05fa8600 834
AnnaBridge 157:e7ca05fa8600 835
AnnaBridge 157:e7ca05fa8600 836 /* ################################## SysTick function ############################################ */
AnnaBridge 157:e7ca05fa8600 837 /**
AnnaBridge 157:e7ca05fa8600 838 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 157:e7ca05fa8600 840 \brief Functions that configure the System.
AnnaBridge 157:e7ca05fa8600 841 @{
AnnaBridge 157:e7ca05fa8600 842 */
AnnaBridge 157:e7ca05fa8600 843
AnnaBridge 157:e7ca05fa8600 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 157:e7ca05fa8600 845
AnnaBridge 157:e7ca05fa8600 846 /**
AnnaBridge 157:e7ca05fa8600 847 \brief System Tick Configuration
AnnaBridge 157:e7ca05fa8600 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 849 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 850 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 851 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 852 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 855 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 856 */
AnnaBridge 157:e7ca05fa8600 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 858 {
AnnaBridge 157:e7ca05fa8600 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 860 {
AnnaBridge 157:e7ca05fa8600 861 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 862 }
AnnaBridge 157:e7ca05fa8600 863
AnnaBridge 157:e7ca05fa8600 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 868 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 870 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 871 }
AnnaBridge 157:e7ca05fa8600 872
AnnaBridge 157:e7ca05fa8600 873 #endif
AnnaBridge 157:e7ca05fa8600 874
AnnaBridge 157:e7ca05fa8600 875 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 157:e7ca05fa8600 876
AnnaBridge 157:e7ca05fa8600 877
AnnaBridge 157:e7ca05fa8600 878
AnnaBridge 157:e7ca05fa8600 879
AnnaBridge 157:e7ca05fa8600 880 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 881 }
AnnaBridge 157:e7ca05fa8600 882 #endif
AnnaBridge 157:e7ca05fa8600 883
AnnaBridge 157:e7ca05fa8600 884 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 157:e7ca05fa8600 885
AnnaBridge 157:e7ca05fa8600 886 #endif /* __CMSIS_GENERIC */