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TARGET_LPC1769/cmsis_gcc.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 09 11:14:10 2017 +0000
Revision:: 157:e7ca05fa8600
Child:: 160:5571c4ff569f

Release 155 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	157:e7ca05fa8600	1	/************************************************************************//
AnnaBridge	157:e7ca05fa8600	2	* @file cmsis_gcc.h
AnnaBridge	157:e7ca05fa8600	3	* @brief CMSIS compiler GCC header file
AnnaBridge	157:e7ca05fa8600	4	* @version V5.0.2
AnnaBridge	157:e7ca05fa8600	5	* @date 13. February 2017
AnnaBridge	157:e7ca05fa8600	6	******************************************************************************/
AnnaBridge	157:e7ca05fa8600	7	/*
AnnaBridge	157:e7ca05fa8600	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	157:e7ca05fa8600	9	*
AnnaBridge	157:e7ca05fa8600	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	157:e7ca05fa8600	11	*
AnnaBridge	157:e7ca05fa8600	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	157:e7ca05fa8600	13	* not use this file except in compliance with the License.
AnnaBridge	157:e7ca05fa8600	14	* You may obtain a copy of the License at
AnnaBridge	157:e7ca05fa8600	15	*
AnnaBridge	157:e7ca05fa8600	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	157:e7ca05fa8600	17	*
AnnaBridge	157:e7ca05fa8600	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	157:e7ca05fa8600	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	157:e7ca05fa8600	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	157:e7ca05fa8600	21	* See the License for the specific language governing permissions and
AnnaBridge	157:e7ca05fa8600	22	* limitations under the License.
AnnaBridge	157:e7ca05fa8600	23	*/
AnnaBridge	157:e7ca05fa8600	24
AnnaBridge	157:e7ca05fa8600	25	#ifndef __CMSIS_GCC_H
AnnaBridge	157:e7ca05fa8600	26	#define __CMSIS_GCC_H
AnnaBridge	157:e7ca05fa8600	27
AnnaBridge	157:e7ca05fa8600	28	/* ignore some GCC warnings */
AnnaBridge	157:e7ca05fa8600	29	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	30	#pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge	157:e7ca05fa8600	31	#pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge	157:e7ca05fa8600	32	#pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge	157:e7ca05fa8600	33
AnnaBridge	157:e7ca05fa8600	34	/* CMSIS compiler specific defines */
AnnaBridge	157:e7ca05fa8600	35	#ifndef __ASM
AnnaBridge	157:e7ca05fa8600	36	#define __ASM __asm
AnnaBridge	157:e7ca05fa8600	37	#endif
AnnaBridge	157:e7ca05fa8600	38	#ifndef __INLINE
AnnaBridge	157:e7ca05fa8600	39	#define __INLINE inline
AnnaBridge	157:e7ca05fa8600	40	#endif
AnnaBridge	157:e7ca05fa8600	41	#ifndef __STATIC_INLINE
AnnaBridge	157:e7ca05fa8600	42	#define __STATIC_INLINE static inline
AnnaBridge	157:e7ca05fa8600	43	#endif
AnnaBridge	157:e7ca05fa8600	44	#ifndef __NO_RETURN
AnnaBridge	157:e7ca05fa8600	45	#define __NO_RETURN __attribute__((noreturn))
AnnaBridge	157:e7ca05fa8600	46	#endif
AnnaBridge	157:e7ca05fa8600	47	#ifndef __USED
AnnaBridge	157:e7ca05fa8600	48	#define __USED __attribute__((used))
AnnaBridge	157:e7ca05fa8600	49	#endif
AnnaBridge	157:e7ca05fa8600	50	#ifndef __WEAK
AnnaBridge	157:e7ca05fa8600	51	#define __WEAK __attribute__((weak))
AnnaBridge	157:e7ca05fa8600	52	#endif
AnnaBridge	157:e7ca05fa8600	53	#ifndef __PACKED
AnnaBridge	157:e7ca05fa8600	54	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	157:e7ca05fa8600	55	#endif
AnnaBridge	157:e7ca05fa8600	56	#ifndef __PACKED_STRUCT
AnnaBridge	157:e7ca05fa8600	57	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	157:e7ca05fa8600	58	#endif
AnnaBridge	157:e7ca05fa8600	59	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	157:e7ca05fa8600	60	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	61	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	157:e7ca05fa8600	62	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	157:e7ca05fa8600	63	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	157:e7ca05fa8600	64	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	65	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	157:e7ca05fa8600	66	#endif
AnnaBridge	157:e7ca05fa8600	67	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	157:e7ca05fa8600	68	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	69	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	157:e7ca05fa8600	70	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	157:e7ca05fa8600	71	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	157:e7ca05fa8600	72	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	73	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	157:e7ca05fa8600	74	#endif
AnnaBridge	157:e7ca05fa8600	75	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	157:e7ca05fa8600	76	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	77	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	157:e7ca05fa8600	78	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	157:e7ca05fa8600	79	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	157:e7ca05fa8600	80	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	81	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	157:e7ca05fa8600	82	#endif
AnnaBridge	157:e7ca05fa8600	83	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	157:e7ca05fa8600	84	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	85	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	157:e7ca05fa8600	86	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	157:e7ca05fa8600	87	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	157:e7ca05fa8600	88	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	89	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	157:e7ca05fa8600	90	#endif
AnnaBridge	157:e7ca05fa8600	91	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	157:e7ca05fa8600	92	#pragma GCC diagnostic push
AnnaBridge	157:e7ca05fa8600	93	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	157:e7ca05fa8600	94	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	157:e7ca05fa8600	95	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	157:e7ca05fa8600	96	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	97	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	157:e7ca05fa8600	98	#endif
AnnaBridge	157:e7ca05fa8600	99	#ifndef __ALIGNED
AnnaBridge	157:e7ca05fa8600	100	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	157:e7ca05fa8600	101	#endif
AnnaBridge	157:e7ca05fa8600	102
AnnaBridge	157:e7ca05fa8600	103
AnnaBridge	157:e7ca05fa8600	104	/* ########################### Core Function Access ########################### */
AnnaBridge	157:e7ca05fa8600	105	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	157:e7ca05fa8600	106	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	157:e7ca05fa8600	107	@{
AnnaBridge	157:e7ca05fa8600	108	*/
AnnaBridge	157:e7ca05fa8600	109
AnnaBridge	157:e7ca05fa8600	110	/**
AnnaBridge	157:e7ca05fa8600	111	\brief Enable IRQ Interrupts
AnnaBridge	157:e7ca05fa8600	112	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	157:e7ca05fa8600	113	Can only be executed in Privileged modes.
AnnaBridge	157:e7ca05fa8600	114	*/
AnnaBridge	157:e7ca05fa8600	115	__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
AnnaBridge	157:e7ca05fa8600	116	{
AnnaBridge	157:e7ca05fa8600	117	__ASM volatile ("cpsie i" : : : "memory");
AnnaBridge	157:e7ca05fa8600	118	}
AnnaBridge	157:e7ca05fa8600	119
AnnaBridge	157:e7ca05fa8600	120
AnnaBridge	157:e7ca05fa8600	121	/**
AnnaBridge	157:e7ca05fa8600	122	\brief Disable IRQ Interrupts
AnnaBridge	157:e7ca05fa8600	123	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	157:e7ca05fa8600	124	Can only be executed in Privileged modes.
AnnaBridge	157:e7ca05fa8600	125	*/
AnnaBridge	157:e7ca05fa8600	126	__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
AnnaBridge	157:e7ca05fa8600	127	{
AnnaBridge	157:e7ca05fa8600	128	__ASM volatile ("cpsid i" : : : "memory");
AnnaBridge	157:e7ca05fa8600	129	}
AnnaBridge	157:e7ca05fa8600	130
AnnaBridge	157:e7ca05fa8600	131
AnnaBridge	157:e7ca05fa8600	132	/**
AnnaBridge	157:e7ca05fa8600	133	\brief Get Control Register
AnnaBridge	157:e7ca05fa8600	134	\details Returns the content of the Control Register.
AnnaBridge	157:e7ca05fa8600	135	\return Control Register value
AnnaBridge	157:e7ca05fa8600	136	*/
AnnaBridge	157:e7ca05fa8600	137	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge	157:e7ca05fa8600	138	{
AnnaBridge	157:e7ca05fa8600	139	uint32_t result;
AnnaBridge	157:e7ca05fa8600	140
AnnaBridge	157:e7ca05fa8600	141	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	142	return(result);
AnnaBridge	157:e7ca05fa8600	143	}
AnnaBridge	157:e7ca05fa8600	144
AnnaBridge	157:e7ca05fa8600	145
AnnaBridge	157:e7ca05fa8600	146	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	147	/**
AnnaBridge	157:e7ca05fa8600	148	\brief Get Control Register (non-secure)
AnnaBridge	157:e7ca05fa8600	149	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	157:e7ca05fa8600	150	\return non-secure Control Register value
AnnaBridge	157:e7ca05fa8600	151	*/
AnnaBridge	157:e7ca05fa8600	152	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	157:e7ca05fa8600	153	{
AnnaBridge	157:e7ca05fa8600	154	uint32_t result;
AnnaBridge	157:e7ca05fa8600	155
AnnaBridge	157:e7ca05fa8600	156	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	157	return(result);
AnnaBridge	157:e7ca05fa8600	158	}
AnnaBridge	157:e7ca05fa8600	159	#endif
AnnaBridge	157:e7ca05fa8600	160
AnnaBridge	157:e7ca05fa8600	161
AnnaBridge	157:e7ca05fa8600	162	/**
AnnaBridge	157:e7ca05fa8600	163	\brief Set Control Register
AnnaBridge	157:e7ca05fa8600	164	\details Writes the given value to the Control Register.
AnnaBridge	157:e7ca05fa8600	165	\param [in] control Control Register value to set
AnnaBridge	157:e7ca05fa8600	166	*/
AnnaBridge	157:e7ca05fa8600	167	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge	157:e7ca05fa8600	168	{
AnnaBridge	157:e7ca05fa8600	169	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	157:e7ca05fa8600	170	}
AnnaBridge	157:e7ca05fa8600	171
AnnaBridge	157:e7ca05fa8600	172
AnnaBridge	157:e7ca05fa8600	173	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	174	/**
AnnaBridge	157:e7ca05fa8600	175	\brief Set Control Register (non-secure)
AnnaBridge	157:e7ca05fa8600	176	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	157:e7ca05fa8600	177	\param [in] control Control Register value to set
AnnaBridge	157:e7ca05fa8600	178	*/
AnnaBridge	157:e7ca05fa8600	179	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	157:e7ca05fa8600	180	{
AnnaBridge	157:e7ca05fa8600	181	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	157:e7ca05fa8600	182	}
AnnaBridge	157:e7ca05fa8600	183	#endif
AnnaBridge	157:e7ca05fa8600	184
AnnaBridge	157:e7ca05fa8600	185
AnnaBridge	157:e7ca05fa8600	186	/**
AnnaBridge	157:e7ca05fa8600	187	\brief Get IPSR Register
AnnaBridge	157:e7ca05fa8600	188	\details Returns the content of the IPSR Register.
AnnaBridge	157:e7ca05fa8600	189	\return IPSR Register value
AnnaBridge	157:e7ca05fa8600	190	*/
AnnaBridge	157:e7ca05fa8600	191	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge	157:e7ca05fa8600	192	{
AnnaBridge	157:e7ca05fa8600	193	uint32_t result;
AnnaBridge	157:e7ca05fa8600	194
AnnaBridge	157:e7ca05fa8600	195	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	196	return(result);
AnnaBridge	157:e7ca05fa8600	197	}
AnnaBridge	157:e7ca05fa8600	198
AnnaBridge	157:e7ca05fa8600	199
AnnaBridge	157:e7ca05fa8600	200	/**
AnnaBridge	157:e7ca05fa8600	201	\brief Get APSR Register
AnnaBridge	157:e7ca05fa8600	202	\details Returns the content of the APSR Register.
AnnaBridge	157:e7ca05fa8600	203	\return APSR Register value
AnnaBridge	157:e7ca05fa8600	204	*/
AnnaBridge	157:e7ca05fa8600	205	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge	157:e7ca05fa8600	206	{
AnnaBridge	157:e7ca05fa8600	207	uint32_t result;
AnnaBridge	157:e7ca05fa8600	208
AnnaBridge	157:e7ca05fa8600	209	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	210	return(result);
AnnaBridge	157:e7ca05fa8600	211	}
AnnaBridge	157:e7ca05fa8600	212
AnnaBridge	157:e7ca05fa8600	213
AnnaBridge	157:e7ca05fa8600	214	/**
AnnaBridge	157:e7ca05fa8600	215	\brief Get xPSR Register
AnnaBridge	157:e7ca05fa8600	216	\details Returns the content of the xPSR Register.
AnnaBridge	157:e7ca05fa8600	217	\return xPSR Register value
AnnaBridge	157:e7ca05fa8600	218	*/
AnnaBridge	157:e7ca05fa8600	219	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge	157:e7ca05fa8600	220	{
AnnaBridge	157:e7ca05fa8600	221	uint32_t result;
AnnaBridge	157:e7ca05fa8600	222
AnnaBridge	157:e7ca05fa8600	223	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	224	return(result);
AnnaBridge	157:e7ca05fa8600	225	}
AnnaBridge	157:e7ca05fa8600	226
AnnaBridge	157:e7ca05fa8600	227
AnnaBridge	157:e7ca05fa8600	228	/**
AnnaBridge	157:e7ca05fa8600	229	\brief Get Process Stack Pointer
AnnaBridge	157:e7ca05fa8600	230	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	157:e7ca05fa8600	231	\return PSP Register value
AnnaBridge	157:e7ca05fa8600	232	*/
AnnaBridge	157:e7ca05fa8600	233	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge	157:e7ca05fa8600	234	{
AnnaBridge	157:e7ca05fa8600	235	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	236
AnnaBridge	157:e7ca05fa8600	237	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	238	return(result);
AnnaBridge	157:e7ca05fa8600	239	}
AnnaBridge	157:e7ca05fa8600	240
AnnaBridge	157:e7ca05fa8600	241
AnnaBridge	157:e7ca05fa8600	242	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	243	/**
AnnaBridge	157:e7ca05fa8600	244	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	245	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	157:e7ca05fa8600	246	\return PSP Register value
AnnaBridge	157:e7ca05fa8600	247	*/
AnnaBridge	157:e7ca05fa8600	248	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	157:e7ca05fa8600	249	{
AnnaBridge	157:e7ca05fa8600	250	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	251
AnnaBridge	157:e7ca05fa8600	252	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	253	return(result);
AnnaBridge	157:e7ca05fa8600	254	}
AnnaBridge	157:e7ca05fa8600	255	#endif
AnnaBridge	157:e7ca05fa8600	256
AnnaBridge	157:e7ca05fa8600	257
AnnaBridge	157:e7ca05fa8600	258	/**
AnnaBridge	157:e7ca05fa8600	259	\brief Set Process Stack Pointer
AnnaBridge	157:e7ca05fa8600	260	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	157:e7ca05fa8600	261	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	262	*/
AnnaBridge	157:e7ca05fa8600	263	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	157:e7ca05fa8600	264	{
AnnaBridge	157:e7ca05fa8600	265	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	157:e7ca05fa8600	266	}
AnnaBridge	157:e7ca05fa8600	267
AnnaBridge	157:e7ca05fa8600	268
AnnaBridge	157:e7ca05fa8600	269	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	270	/**
AnnaBridge	157:e7ca05fa8600	271	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	272	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	157:e7ca05fa8600	273	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	274	*/
AnnaBridge	157:e7ca05fa8600	275	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	157:e7ca05fa8600	276	{
AnnaBridge	157:e7ca05fa8600	277	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	157:e7ca05fa8600	278	}
AnnaBridge	157:e7ca05fa8600	279	#endif
AnnaBridge	157:e7ca05fa8600	280
AnnaBridge	157:e7ca05fa8600	281
AnnaBridge	157:e7ca05fa8600	282	/**
AnnaBridge	157:e7ca05fa8600	283	\brief Get Main Stack Pointer
AnnaBridge	157:e7ca05fa8600	284	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	157:e7ca05fa8600	285	\return MSP Register value
AnnaBridge	157:e7ca05fa8600	286	*/
AnnaBridge	157:e7ca05fa8600	287	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge	157:e7ca05fa8600	288	{
AnnaBridge	157:e7ca05fa8600	289	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	290
AnnaBridge	157:e7ca05fa8600	291	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	292	return(result);
AnnaBridge	157:e7ca05fa8600	293	}
AnnaBridge	157:e7ca05fa8600	294
AnnaBridge	157:e7ca05fa8600	295
AnnaBridge	157:e7ca05fa8600	296	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	297	/**
AnnaBridge	157:e7ca05fa8600	298	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	299	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	157:e7ca05fa8600	300	\return MSP Register value
AnnaBridge	157:e7ca05fa8600	301	*/
AnnaBridge	157:e7ca05fa8600	302	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	157:e7ca05fa8600	303	{
AnnaBridge	157:e7ca05fa8600	304	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	305
AnnaBridge	157:e7ca05fa8600	306	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	307	return(result);
AnnaBridge	157:e7ca05fa8600	308	}
AnnaBridge	157:e7ca05fa8600	309	#endif
AnnaBridge	157:e7ca05fa8600	310
AnnaBridge	157:e7ca05fa8600	311
AnnaBridge	157:e7ca05fa8600	312	/**
AnnaBridge	157:e7ca05fa8600	313	\brief Set Main Stack Pointer
AnnaBridge	157:e7ca05fa8600	314	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	157:e7ca05fa8600	315	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	316	*/
AnnaBridge	157:e7ca05fa8600	317	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	157:e7ca05fa8600	318	{
AnnaBridge	157:e7ca05fa8600	319	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	157:e7ca05fa8600	320	}
AnnaBridge	157:e7ca05fa8600	321
AnnaBridge	157:e7ca05fa8600	322
AnnaBridge	157:e7ca05fa8600	323	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	324	/**
AnnaBridge	157:e7ca05fa8600	325	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	326	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	157:e7ca05fa8600	327	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	328	*/
AnnaBridge	157:e7ca05fa8600	329	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	157:e7ca05fa8600	330	{
AnnaBridge	157:e7ca05fa8600	331	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	157:e7ca05fa8600	332	}
AnnaBridge	157:e7ca05fa8600	333	#endif
AnnaBridge	157:e7ca05fa8600	334
AnnaBridge	157:e7ca05fa8600	335
AnnaBridge	157:e7ca05fa8600	336	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	337	/**
AnnaBridge	157:e7ca05fa8600	338	\brief Get Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	339	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	157:e7ca05fa8600	340	\return SP Register value
AnnaBridge	157:e7ca05fa8600	341	*/
AnnaBridge	157:e7ca05fa8600	342	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	157:e7ca05fa8600	343	{
AnnaBridge	157:e7ca05fa8600	344	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	345
AnnaBridge	157:e7ca05fa8600	346	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	347	return(result);
AnnaBridge	157:e7ca05fa8600	348	}
AnnaBridge	157:e7ca05fa8600	349
AnnaBridge	157:e7ca05fa8600	350
AnnaBridge	157:e7ca05fa8600	351	/**
AnnaBridge	157:e7ca05fa8600	352	\brief Set Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	353	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	157:e7ca05fa8600	354	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	355	*/
AnnaBridge	157:e7ca05fa8600	356	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	157:e7ca05fa8600	357	{
AnnaBridge	157:e7ca05fa8600	358	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	157:e7ca05fa8600	359	}
AnnaBridge	157:e7ca05fa8600	360	#endif
AnnaBridge	157:e7ca05fa8600	361
AnnaBridge	157:e7ca05fa8600	362
AnnaBridge	157:e7ca05fa8600	363	/**
AnnaBridge	157:e7ca05fa8600	364	\brief Get Priority Mask
AnnaBridge	157:e7ca05fa8600	365	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	157:e7ca05fa8600	366	\return Priority Mask value
AnnaBridge	157:e7ca05fa8600	367	*/
AnnaBridge	157:e7ca05fa8600	368	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge	157:e7ca05fa8600	369	{
AnnaBridge	157:e7ca05fa8600	370	uint32_t result;
AnnaBridge	157:e7ca05fa8600	371
AnnaBridge	157:e7ca05fa8600	372	__ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	373	return(result);
AnnaBridge	157:e7ca05fa8600	374	}
AnnaBridge	157:e7ca05fa8600	375
AnnaBridge	157:e7ca05fa8600	376
AnnaBridge	157:e7ca05fa8600	377	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	378	/**
AnnaBridge	157:e7ca05fa8600	379	\brief Get Priority Mask (non-secure)
AnnaBridge	157:e7ca05fa8600	380	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	157:e7ca05fa8600	381	\return Priority Mask value
AnnaBridge	157:e7ca05fa8600	382	*/
AnnaBridge	157:e7ca05fa8600	383	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	157:e7ca05fa8600	384	{
AnnaBridge	157:e7ca05fa8600	385	uint32_t result;
AnnaBridge	157:e7ca05fa8600	386
AnnaBridge	157:e7ca05fa8600	387	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	388	return(result);
AnnaBridge	157:e7ca05fa8600	389	}
AnnaBridge	157:e7ca05fa8600	390	#endif
AnnaBridge	157:e7ca05fa8600	391
AnnaBridge	157:e7ca05fa8600	392
AnnaBridge	157:e7ca05fa8600	393	/**
AnnaBridge	157:e7ca05fa8600	394	\brief Set Priority Mask
AnnaBridge	157:e7ca05fa8600	395	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	157:e7ca05fa8600	396	\param [in] priMask Priority Mask
AnnaBridge	157:e7ca05fa8600	397	*/
AnnaBridge	157:e7ca05fa8600	398	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	157:e7ca05fa8600	399	{
AnnaBridge	157:e7ca05fa8600	400	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	157:e7ca05fa8600	401	}
AnnaBridge	157:e7ca05fa8600	402
AnnaBridge	157:e7ca05fa8600	403
AnnaBridge	157:e7ca05fa8600	404	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	405	/**
AnnaBridge	157:e7ca05fa8600	406	\brief Set Priority Mask (non-secure)
AnnaBridge	157:e7ca05fa8600	407	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	157:e7ca05fa8600	408	\param [in] priMask Priority Mask
AnnaBridge	157:e7ca05fa8600	409	*/
AnnaBridge	157:e7ca05fa8600	410	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	157:e7ca05fa8600	411	{
AnnaBridge	157:e7ca05fa8600	412	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	157:e7ca05fa8600	413	}
AnnaBridge	157:e7ca05fa8600	414	#endif
AnnaBridge	157:e7ca05fa8600	415
AnnaBridge	157:e7ca05fa8600	416
AnnaBridge	157:e7ca05fa8600	417	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	418	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	419	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	420	/**
AnnaBridge	157:e7ca05fa8600	421	\brief Enable FIQ
AnnaBridge	157:e7ca05fa8600	422	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	157:e7ca05fa8600	423	Can only be executed in Privileged modes.
AnnaBridge	157:e7ca05fa8600	424	*/
AnnaBridge	157:e7ca05fa8600	425	__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
AnnaBridge	157:e7ca05fa8600	426	{
AnnaBridge	157:e7ca05fa8600	427	__ASM volatile ("cpsie f" : : : "memory");
AnnaBridge	157:e7ca05fa8600	428	}
AnnaBridge	157:e7ca05fa8600	429
AnnaBridge	157:e7ca05fa8600	430
AnnaBridge	157:e7ca05fa8600	431	/**
AnnaBridge	157:e7ca05fa8600	432	\brief Disable FIQ
AnnaBridge	157:e7ca05fa8600	433	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	157:e7ca05fa8600	434	Can only be executed in Privileged modes.
AnnaBridge	157:e7ca05fa8600	435	*/
AnnaBridge	157:e7ca05fa8600	436	__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
AnnaBridge	157:e7ca05fa8600	437	{
AnnaBridge	157:e7ca05fa8600	438	__ASM volatile ("cpsid f" : : : "memory");
AnnaBridge	157:e7ca05fa8600	439	}
AnnaBridge	157:e7ca05fa8600	440
AnnaBridge	157:e7ca05fa8600	441
AnnaBridge	157:e7ca05fa8600	442	/**
AnnaBridge	157:e7ca05fa8600	443	\brief Get Base Priority
AnnaBridge	157:e7ca05fa8600	444	\details Returns the current value of the Base Priority register.
AnnaBridge	157:e7ca05fa8600	445	\return Base Priority register value
AnnaBridge	157:e7ca05fa8600	446	*/
AnnaBridge	157:e7ca05fa8600	447	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge	157:e7ca05fa8600	448	{
AnnaBridge	157:e7ca05fa8600	449	uint32_t result;
AnnaBridge	157:e7ca05fa8600	450
AnnaBridge	157:e7ca05fa8600	451	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	452	return(result);
AnnaBridge	157:e7ca05fa8600	453	}
AnnaBridge	157:e7ca05fa8600	454
AnnaBridge	157:e7ca05fa8600	455
AnnaBridge	157:e7ca05fa8600	456	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	457	/**
AnnaBridge	157:e7ca05fa8600	458	\brief Get Base Priority (non-secure)
AnnaBridge	157:e7ca05fa8600	459	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	157:e7ca05fa8600	460	\return Base Priority register value
AnnaBridge	157:e7ca05fa8600	461	*/
AnnaBridge	157:e7ca05fa8600	462	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	157:e7ca05fa8600	463	{
AnnaBridge	157:e7ca05fa8600	464	uint32_t result;
AnnaBridge	157:e7ca05fa8600	465
AnnaBridge	157:e7ca05fa8600	466	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	467	return(result);
AnnaBridge	157:e7ca05fa8600	468	}
AnnaBridge	157:e7ca05fa8600	469	#endif
AnnaBridge	157:e7ca05fa8600	470
AnnaBridge	157:e7ca05fa8600	471
AnnaBridge	157:e7ca05fa8600	472	/**
AnnaBridge	157:e7ca05fa8600	473	\brief Set Base Priority
AnnaBridge	157:e7ca05fa8600	474	\details Assigns the given value to the Base Priority register.
AnnaBridge	157:e7ca05fa8600	475	\param [in] basePri Base Priority value to set
AnnaBridge	157:e7ca05fa8600	476	*/
AnnaBridge	157:e7ca05fa8600	477	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	157:e7ca05fa8600	478	{
AnnaBridge	157:e7ca05fa8600	479	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	157:e7ca05fa8600	480	}
AnnaBridge	157:e7ca05fa8600	481
AnnaBridge	157:e7ca05fa8600	482
AnnaBridge	157:e7ca05fa8600	483	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	484	/**
AnnaBridge	157:e7ca05fa8600	485	\brief Set Base Priority (non-secure)
AnnaBridge	157:e7ca05fa8600	486	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	157:e7ca05fa8600	487	\param [in] basePri Base Priority value to set
AnnaBridge	157:e7ca05fa8600	488	*/
AnnaBridge	157:e7ca05fa8600	489	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	157:e7ca05fa8600	490	{
AnnaBridge	157:e7ca05fa8600	491	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	157:e7ca05fa8600	492	}
AnnaBridge	157:e7ca05fa8600	493	#endif
AnnaBridge	157:e7ca05fa8600	494
AnnaBridge	157:e7ca05fa8600	495
AnnaBridge	157:e7ca05fa8600	496	/**
AnnaBridge	157:e7ca05fa8600	497	\brief Set Base Priority with condition
AnnaBridge	157:e7ca05fa8600	498	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	157:e7ca05fa8600	499	or the new value increases the BASEPRI priority level.
AnnaBridge	157:e7ca05fa8600	500	\param [in] basePri Base Priority value to set
AnnaBridge	157:e7ca05fa8600	501	*/
AnnaBridge	157:e7ca05fa8600	502	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	157:e7ca05fa8600	503	{
AnnaBridge	157:e7ca05fa8600	504	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	157:e7ca05fa8600	505	}
AnnaBridge	157:e7ca05fa8600	506
AnnaBridge	157:e7ca05fa8600	507
AnnaBridge	157:e7ca05fa8600	508	/**
AnnaBridge	157:e7ca05fa8600	509	\brief Get Fault Mask
AnnaBridge	157:e7ca05fa8600	510	\details Returns the current value of the Fault Mask register.
AnnaBridge	157:e7ca05fa8600	511	\return Fault Mask register value
AnnaBridge	157:e7ca05fa8600	512	*/
AnnaBridge	157:e7ca05fa8600	513	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	157:e7ca05fa8600	514	{
AnnaBridge	157:e7ca05fa8600	515	uint32_t result;
AnnaBridge	157:e7ca05fa8600	516
AnnaBridge	157:e7ca05fa8600	517	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	518	return(result);
AnnaBridge	157:e7ca05fa8600	519	}
AnnaBridge	157:e7ca05fa8600	520
AnnaBridge	157:e7ca05fa8600	521
AnnaBridge	157:e7ca05fa8600	522	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	523	/**
AnnaBridge	157:e7ca05fa8600	524	\brief Get Fault Mask (non-secure)
AnnaBridge	157:e7ca05fa8600	525	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	157:e7ca05fa8600	526	\return Fault Mask register value
AnnaBridge	157:e7ca05fa8600	527	*/
AnnaBridge	157:e7ca05fa8600	528	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	157:e7ca05fa8600	529	{
AnnaBridge	157:e7ca05fa8600	530	uint32_t result;
AnnaBridge	157:e7ca05fa8600	531
AnnaBridge	157:e7ca05fa8600	532	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	533	return(result);
AnnaBridge	157:e7ca05fa8600	534	}
AnnaBridge	157:e7ca05fa8600	535	#endif
AnnaBridge	157:e7ca05fa8600	536
AnnaBridge	157:e7ca05fa8600	537
AnnaBridge	157:e7ca05fa8600	538	/**
AnnaBridge	157:e7ca05fa8600	539	\brief Set Fault Mask
AnnaBridge	157:e7ca05fa8600	540	\details Assigns the given value to the Fault Mask register.
AnnaBridge	157:e7ca05fa8600	541	\param [in] faultMask Fault Mask value to set
AnnaBridge	157:e7ca05fa8600	542	*/
AnnaBridge	157:e7ca05fa8600	543	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	157:e7ca05fa8600	544	{
AnnaBridge	157:e7ca05fa8600	545	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	157:e7ca05fa8600	546	}
AnnaBridge	157:e7ca05fa8600	547
AnnaBridge	157:e7ca05fa8600	548
AnnaBridge	157:e7ca05fa8600	549	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	157:e7ca05fa8600	550	/**
AnnaBridge	157:e7ca05fa8600	551	\brief Set Fault Mask (non-secure)
AnnaBridge	157:e7ca05fa8600	552	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	157:e7ca05fa8600	553	\param [in] faultMask Fault Mask value to set
AnnaBridge	157:e7ca05fa8600	554	*/
AnnaBridge	157:e7ca05fa8600	555	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	157:e7ca05fa8600	556	{
AnnaBridge	157:e7ca05fa8600	557	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	157:e7ca05fa8600	558	}
AnnaBridge	157:e7ca05fa8600	559	#endif
AnnaBridge	157:e7ca05fa8600	560
AnnaBridge	157:e7ca05fa8600	561	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	562	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	563	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	564
AnnaBridge	157:e7ca05fa8600	565
AnnaBridge	157:e7ca05fa8600	566	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	567	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	157:e7ca05fa8600	568
AnnaBridge	157:e7ca05fa8600	569	/**
AnnaBridge	157:e7ca05fa8600	570	\brief Get Process Stack Pointer Limit
AnnaBridge	157:e7ca05fa8600	571	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	157:e7ca05fa8600	572	\return PSPLIM Register value
AnnaBridge	157:e7ca05fa8600	573	*/
AnnaBridge	157:e7ca05fa8600	574	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge	157:e7ca05fa8600	575	{
AnnaBridge	157:e7ca05fa8600	576	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	577
AnnaBridge	157:e7ca05fa8600	578	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	579	return(result);
AnnaBridge	157:e7ca05fa8600	580	}
AnnaBridge	157:e7ca05fa8600	581
AnnaBridge	157:e7ca05fa8600	582
AnnaBridge	157:e7ca05fa8600	583	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	157:e7ca05fa8600	584	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	585	/**
AnnaBridge	157:e7ca05fa8600	586	\brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge	157:e7ca05fa8600	587	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	157:e7ca05fa8600	588	\return PSPLIM Register value
AnnaBridge	157:e7ca05fa8600	589	*/
AnnaBridge	157:e7ca05fa8600	590	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	157:e7ca05fa8600	591	{
AnnaBridge	157:e7ca05fa8600	592	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	593
AnnaBridge	157:e7ca05fa8600	594	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	595	return(result);
AnnaBridge	157:e7ca05fa8600	596	}
AnnaBridge	157:e7ca05fa8600	597	#endif
AnnaBridge	157:e7ca05fa8600	598
AnnaBridge	157:e7ca05fa8600	599
AnnaBridge	157:e7ca05fa8600	600	/**
AnnaBridge	157:e7ca05fa8600	601	\brief Set Process Stack Pointer Limit
AnnaBridge	157:e7ca05fa8600	602	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	157:e7ca05fa8600	603	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	157:e7ca05fa8600	604	*/
AnnaBridge	157:e7ca05fa8600	605	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	157:e7ca05fa8600	606	{
AnnaBridge	157:e7ca05fa8600	607	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge	157:e7ca05fa8600	608	}
AnnaBridge	157:e7ca05fa8600	609
AnnaBridge	157:e7ca05fa8600	610
AnnaBridge	157:e7ca05fa8600	611	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	157:e7ca05fa8600	612	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	613	/**
AnnaBridge	157:e7ca05fa8600	614	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	157:e7ca05fa8600	615	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	157:e7ca05fa8600	616	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	157:e7ca05fa8600	617	*/
AnnaBridge	157:e7ca05fa8600	618	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	157:e7ca05fa8600	619	{
AnnaBridge	157:e7ca05fa8600	620	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge	157:e7ca05fa8600	621	}
AnnaBridge	157:e7ca05fa8600	622	#endif
AnnaBridge	157:e7ca05fa8600	623
AnnaBridge	157:e7ca05fa8600	624
AnnaBridge	157:e7ca05fa8600	625	/**
AnnaBridge	157:e7ca05fa8600	626	\brief Get Main Stack Pointer Limit
AnnaBridge	157:e7ca05fa8600	627	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	157:e7ca05fa8600	628	\return MSPLIM Register value
AnnaBridge	157:e7ca05fa8600	629	*/
AnnaBridge	157:e7ca05fa8600	630	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge	157:e7ca05fa8600	631	{
AnnaBridge	157:e7ca05fa8600	632	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	633
AnnaBridge	157:e7ca05fa8600	634	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	635
AnnaBridge	157:e7ca05fa8600	636	return(result);
AnnaBridge	157:e7ca05fa8600	637	}
AnnaBridge	157:e7ca05fa8600	638
AnnaBridge	157:e7ca05fa8600	639
AnnaBridge	157:e7ca05fa8600	640	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	157:e7ca05fa8600	641	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	642	/**
AnnaBridge	157:e7ca05fa8600	643	\brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge	157:e7ca05fa8600	644	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	157:e7ca05fa8600	645	\return MSPLIM Register value
AnnaBridge	157:e7ca05fa8600	646	*/
AnnaBridge	157:e7ca05fa8600	647	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	157:e7ca05fa8600	648	{
AnnaBridge	157:e7ca05fa8600	649	register uint32_t result;
AnnaBridge	157:e7ca05fa8600	650
AnnaBridge	157:e7ca05fa8600	651	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	652	return(result);
AnnaBridge	157:e7ca05fa8600	653	}
AnnaBridge	157:e7ca05fa8600	654	#endif
AnnaBridge	157:e7ca05fa8600	655
AnnaBridge	157:e7ca05fa8600	656
AnnaBridge	157:e7ca05fa8600	657	/**
AnnaBridge	157:e7ca05fa8600	658	\brief Set Main Stack Pointer Limit
AnnaBridge	157:e7ca05fa8600	659	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	157:e7ca05fa8600	660	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	157:e7ca05fa8600	661	*/
AnnaBridge	157:e7ca05fa8600	662	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	157:e7ca05fa8600	663	{
AnnaBridge	157:e7ca05fa8600	664	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	157:e7ca05fa8600	665	}
AnnaBridge	157:e7ca05fa8600	666
AnnaBridge	157:e7ca05fa8600	667
AnnaBridge	157:e7ca05fa8600	668	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	157:e7ca05fa8600	669	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	670	/**
AnnaBridge	157:e7ca05fa8600	671	\brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge	157:e7ca05fa8600	672	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	157:e7ca05fa8600	673	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	157:e7ca05fa8600	674	*/
AnnaBridge	157:e7ca05fa8600	675	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	157:e7ca05fa8600	676	{
AnnaBridge	157:e7ca05fa8600	677	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	157:e7ca05fa8600	678	}
AnnaBridge	157:e7ca05fa8600	679	#endif
AnnaBridge	157:e7ca05fa8600	680
AnnaBridge	157:e7ca05fa8600	681	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	682	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	683
AnnaBridge	157:e7ca05fa8600	684
AnnaBridge	157:e7ca05fa8600	685	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	686	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	687
AnnaBridge	157:e7ca05fa8600	688	/**
AnnaBridge	157:e7ca05fa8600	689	\brief Get FPSCR
AnnaBridge	157:e7ca05fa8600	690	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	157:e7ca05fa8600	691	\return Floating Point Status/Control register value
AnnaBridge	157:e7ca05fa8600	692	*/
AnnaBridge	157:e7ca05fa8600	693	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge	157:e7ca05fa8600	694	{
AnnaBridge	157:e7ca05fa8600	695	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	157:e7ca05fa8600	696	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	157:e7ca05fa8600	697	uint32_t result;
AnnaBridge	157:e7ca05fa8600	698
AnnaBridge	157:e7ca05fa8600	699	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge	157:e7ca05fa8600	700	return(result);
AnnaBridge	157:e7ca05fa8600	701	#else
AnnaBridge	157:e7ca05fa8600	702	return(0U);
AnnaBridge	157:e7ca05fa8600	703	#endif
AnnaBridge	157:e7ca05fa8600	704	}
AnnaBridge	157:e7ca05fa8600	705
AnnaBridge	157:e7ca05fa8600	706
AnnaBridge	157:e7ca05fa8600	707	/**
AnnaBridge	157:e7ca05fa8600	708	\brief Set FPSCR
AnnaBridge	157:e7ca05fa8600	709	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	157:e7ca05fa8600	710	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	157:e7ca05fa8600	711	*/
AnnaBridge	157:e7ca05fa8600	712	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge	157:e7ca05fa8600	713	{
AnnaBridge	157:e7ca05fa8600	714	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	157:e7ca05fa8600	715	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	157:e7ca05fa8600	716	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge	157:e7ca05fa8600	717	#else
AnnaBridge	157:e7ca05fa8600	718	(void)fpscr;
AnnaBridge	157:e7ca05fa8600	719	#endif
AnnaBridge	157:e7ca05fa8600	720	}
AnnaBridge	157:e7ca05fa8600	721
AnnaBridge	157:e7ca05fa8600	722	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	723	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	724
AnnaBridge	157:e7ca05fa8600	725
AnnaBridge	157:e7ca05fa8600	726
AnnaBridge	157:e7ca05fa8600	727	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	157:e7ca05fa8600	728
AnnaBridge	157:e7ca05fa8600	729
AnnaBridge	157:e7ca05fa8600	730	/* ########################## Core Instruction Access ######################### */
AnnaBridge	157:e7ca05fa8600	731	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	157:e7ca05fa8600	732	Access to dedicated instructions
AnnaBridge	157:e7ca05fa8600	733	@{
AnnaBridge	157:e7ca05fa8600	734	*/
AnnaBridge	157:e7ca05fa8600	735
AnnaBridge	157:e7ca05fa8600	736	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	157:e7ca05fa8600	737	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	157:e7ca05fa8600	738	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	157:e7ca05fa8600	739	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	157:e7ca05fa8600	740	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	157:e7ca05fa8600	741	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge	157:e7ca05fa8600	742	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	157:e7ca05fa8600	743	#else
AnnaBridge	157:e7ca05fa8600	744	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	157:e7ca05fa8600	745	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge	157:e7ca05fa8600	746	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	157:e7ca05fa8600	747	#endif
AnnaBridge	157:e7ca05fa8600	748
AnnaBridge	157:e7ca05fa8600	749	/**
AnnaBridge	157:e7ca05fa8600	750	\brief No Operation
AnnaBridge	157:e7ca05fa8600	751	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	157:e7ca05fa8600	752	*/
AnnaBridge	157:e7ca05fa8600	753	//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
AnnaBridge	157:e7ca05fa8600	754	//{
AnnaBridge	157:e7ca05fa8600	755	// __ASM volatile ("nop");
AnnaBridge	157:e7ca05fa8600	756	//}
AnnaBridge	157:e7ca05fa8600	757	#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
AnnaBridge	157:e7ca05fa8600	758
AnnaBridge	157:e7ca05fa8600	759	/**
AnnaBridge	157:e7ca05fa8600	760	\brief Wait For Interrupt
AnnaBridge	157:e7ca05fa8600	761	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	157:e7ca05fa8600	762	*/
AnnaBridge	157:e7ca05fa8600	763	//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
AnnaBridge	157:e7ca05fa8600	764	//{
AnnaBridge	157:e7ca05fa8600	765	// __ASM volatile ("wfi");
AnnaBridge	157:e7ca05fa8600	766	//}
AnnaBridge	157:e7ca05fa8600	767	#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
AnnaBridge	157:e7ca05fa8600	768
AnnaBridge	157:e7ca05fa8600	769
AnnaBridge	157:e7ca05fa8600	770	/**
AnnaBridge	157:e7ca05fa8600	771	\brief Wait For Event
AnnaBridge	157:e7ca05fa8600	772	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	157:e7ca05fa8600	773	a low-power state until one of a number of events occurs.
AnnaBridge	157:e7ca05fa8600	774	*/
AnnaBridge	157:e7ca05fa8600	775	//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
AnnaBridge	157:e7ca05fa8600	776	//{
AnnaBridge	157:e7ca05fa8600	777	// __ASM volatile ("wfe");
AnnaBridge	157:e7ca05fa8600	778	//}
AnnaBridge	157:e7ca05fa8600	779	#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
AnnaBridge	157:e7ca05fa8600	780
AnnaBridge	157:e7ca05fa8600	781
AnnaBridge	157:e7ca05fa8600	782	/**
AnnaBridge	157:e7ca05fa8600	783	\brief Send Event
AnnaBridge	157:e7ca05fa8600	784	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	157:e7ca05fa8600	785	*/
AnnaBridge	157:e7ca05fa8600	786	//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
AnnaBridge	157:e7ca05fa8600	787	//{
AnnaBridge	157:e7ca05fa8600	788	// __ASM volatile ("sev");
AnnaBridge	157:e7ca05fa8600	789	//}
AnnaBridge	157:e7ca05fa8600	790	#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
AnnaBridge	157:e7ca05fa8600	791
AnnaBridge	157:e7ca05fa8600	792
AnnaBridge	157:e7ca05fa8600	793	/**
AnnaBridge	157:e7ca05fa8600	794	\brief Instruction Synchronization Barrier
AnnaBridge	157:e7ca05fa8600	795	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	157:e7ca05fa8600	796	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	157:e7ca05fa8600	797	after the instruction has been completed.
AnnaBridge	157:e7ca05fa8600	798	*/
AnnaBridge	157:e7ca05fa8600	799	__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
AnnaBridge	157:e7ca05fa8600	800	{
AnnaBridge	157:e7ca05fa8600	801	__ASM volatile ("isb 0xF":::"memory");
AnnaBridge	157:e7ca05fa8600	802	}
AnnaBridge	157:e7ca05fa8600	803
AnnaBridge	157:e7ca05fa8600	804
AnnaBridge	157:e7ca05fa8600	805	/**
AnnaBridge	157:e7ca05fa8600	806	\brief Data Synchronization Barrier
AnnaBridge	157:e7ca05fa8600	807	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	157:e7ca05fa8600	808	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	157:e7ca05fa8600	809	*/
AnnaBridge	157:e7ca05fa8600	810	__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
AnnaBridge	157:e7ca05fa8600	811	{
AnnaBridge	157:e7ca05fa8600	812	__ASM volatile ("dsb 0xF":::"memory");
AnnaBridge	157:e7ca05fa8600	813	}
AnnaBridge	157:e7ca05fa8600	814
AnnaBridge	157:e7ca05fa8600	815
AnnaBridge	157:e7ca05fa8600	816	/**
AnnaBridge	157:e7ca05fa8600	817	\brief Data Memory Barrier
AnnaBridge	157:e7ca05fa8600	818	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	157:e7ca05fa8600	819	and after the instruction, without ensuring their completion.
AnnaBridge	157:e7ca05fa8600	820	*/
AnnaBridge	157:e7ca05fa8600	821	__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
AnnaBridge	157:e7ca05fa8600	822	{
AnnaBridge	157:e7ca05fa8600	823	__ASM volatile ("dmb 0xF":::"memory");
AnnaBridge	157:e7ca05fa8600	824	}
AnnaBridge	157:e7ca05fa8600	825
AnnaBridge	157:e7ca05fa8600	826
AnnaBridge	157:e7ca05fa8600	827	/**
AnnaBridge	157:e7ca05fa8600	828	\brief Reverse byte order (32 bit)
AnnaBridge	157:e7ca05fa8600	829	\details Reverses the byte order in integer value.
AnnaBridge	157:e7ca05fa8600	830	\param [in] value Value to reverse
AnnaBridge	157:e7ca05fa8600	831	\return Reversed value
AnnaBridge	157:e7ca05fa8600	832	*/
AnnaBridge	157:e7ca05fa8600	833	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
AnnaBridge	157:e7ca05fa8600	834	{
AnnaBridge	157:e7ca05fa8600	835	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge	157:e7ca05fa8600	836	return __builtin_bswap32(value);
AnnaBridge	157:e7ca05fa8600	837	#else
AnnaBridge	157:e7ca05fa8600	838	uint32_t result;
AnnaBridge	157:e7ca05fa8600	839
AnnaBridge	157:e7ca05fa8600	840	__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	157:e7ca05fa8600	841	return(result);
AnnaBridge	157:e7ca05fa8600	842	#endif
AnnaBridge	157:e7ca05fa8600	843	}
AnnaBridge	157:e7ca05fa8600	844
AnnaBridge	157:e7ca05fa8600	845
AnnaBridge	157:e7ca05fa8600	846	/**
AnnaBridge	157:e7ca05fa8600	847	\brief Reverse byte order (16 bit)
AnnaBridge	157:e7ca05fa8600	848	\details Reverses the byte order in two unsigned short values.
AnnaBridge	157:e7ca05fa8600	849	\param [in] value Value to reverse
AnnaBridge	157:e7ca05fa8600	850	\return Reversed value
AnnaBridge	157:e7ca05fa8600	851	*/
AnnaBridge	157:e7ca05fa8600	852	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge	157:e7ca05fa8600	853	{
AnnaBridge	157:e7ca05fa8600	854	uint32_t result;
AnnaBridge	157:e7ca05fa8600	855
AnnaBridge	157:e7ca05fa8600	856	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	157:e7ca05fa8600	857	return(result);
AnnaBridge	157:e7ca05fa8600	858	}
AnnaBridge	157:e7ca05fa8600	859
AnnaBridge	157:e7ca05fa8600	860
AnnaBridge	157:e7ca05fa8600	861	/**
AnnaBridge	157:e7ca05fa8600	862	\brief Reverse byte order in signed short value
AnnaBridge	157:e7ca05fa8600	863	\details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge	157:e7ca05fa8600	864	\param [in] value Value to reverse
AnnaBridge	157:e7ca05fa8600	865	\return Reversed value
AnnaBridge	157:e7ca05fa8600	866	*/
AnnaBridge	157:e7ca05fa8600	867	__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
AnnaBridge	157:e7ca05fa8600	868	{
AnnaBridge	157:e7ca05fa8600	869	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	157:e7ca05fa8600	870	return (short)__builtin_bswap16(value);
AnnaBridge	157:e7ca05fa8600	871	#else
AnnaBridge	157:e7ca05fa8600	872	int32_t result;
AnnaBridge	157:e7ca05fa8600	873
AnnaBridge	157:e7ca05fa8600	874	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	157:e7ca05fa8600	875	return(result);
AnnaBridge	157:e7ca05fa8600	876	#endif
AnnaBridge	157:e7ca05fa8600	877	}
AnnaBridge	157:e7ca05fa8600	878
AnnaBridge	157:e7ca05fa8600	879
AnnaBridge	157:e7ca05fa8600	880	/**
AnnaBridge	157:e7ca05fa8600	881	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	157:e7ca05fa8600	882	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	157:e7ca05fa8600	883	\param [in] op1 Value to rotate
AnnaBridge	157:e7ca05fa8600	884	\param [in] op2 Number of Bits to rotate
AnnaBridge	157:e7ca05fa8600	885	\return Rotated value
AnnaBridge	157:e7ca05fa8600	886	*/
AnnaBridge	157:e7ca05fa8600	887	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	888	{
AnnaBridge	157:e7ca05fa8600	889	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	157:e7ca05fa8600	890	}
AnnaBridge	157:e7ca05fa8600	891
AnnaBridge	157:e7ca05fa8600	892
AnnaBridge	157:e7ca05fa8600	893	/**
AnnaBridge	157:e7ca05fa8600	894	\brief Breakpoint
AnnaBridge	157:e7ca05fa8600	895	\details Causes the processor to enter Debug state.
AnnaBridge	157:e7ca05fa8600	896	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	157:e7ca05fa8600	897	\param [in] value is ignored by the processor.
AnnaBridge	157:e7ca05fa8600	898	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	157:e7ca05fa8600	899	*/
AnnaBridge	157:e7ca05fa8600	900	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	157:e7ca05fa8600	901
AnnaBridge	157:e7ca05fa8600	902
AnnaBridge	157:e7ca05fa8600	903	/**
AnnaBridge	157:e7ca05fa8600	904	\brief Reverse bit order of value
AnnaBridge	157:e7ca05fa8600	905	\details Reverses the bit order of the given value.
AnnaBridge	157:e7ca05fa8600	906	\param [in] value Value to reverse
AnnaBridge	157:e7ca05fa8600	907	\return Reversed value
AnnaBridge	157:e7ca05fa8600	908	*/
AnnaBridge	157:e7ca05fa8600	909	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge	157:e7ca05fa8600	910	{
AnnaBridge	157:e7ca05fa8600	911	uint32_t result;
AnnaBridge	157:e7ca05fa8600	912
AnnaBridge	157:e7ca05fa8600	913	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	914	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	915	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	916	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge	157:e7ca05fa8600	917	#else
AnnaBridge	157:e7ca05fa8600	918	int32_t s = (4 /sizeof(v)/ * 8) - 1; /* extra shift needed at end */
AnnaBridge	157:e7ca05fa8600	919
AnnaBridge	157:e7ca05fa8600	920	result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge	157:e7ca05fa8600	921	for (value >>= 1U; value; value >>= 1U)
AnnaBridge	157:e7ca05fa8600	922	{
AnnaBridge	157:e7ca05fa8600	923	result <<= 1U;
AnnaBridge	157:e7ca05fa8600	924	result \|= value & 1U;
AnnaBridge	157:e7ca05fa8600	925	s--;
AnnaBridge	157:e7ca05fa8600	926	}
AnnaBridge	157:e7ca05fa8600	927	result <<= s; /* shift when v's highest bits are zero */
AnnaBridge	157:e7ca05fa8600	928	#endif
AnnaBridge	157:e7ca05fa8600	929	return(result);
AnnaBridge	157:e7ca05fa8600	930	}
AnnaBridge	157:e7ca05fa8600	931
AnnaBridge	157:e7ca05fa8600	932
AnnaBridge	157:e7ca05fa8600	933	/**
AnnaBridge	157:e7ca05fa8600	934	\brief Count leading zeros
AnnaBridge	157:e7ca05fa8600	935	\details Counts the number of leading zeros of a data value.
AnnaBridge	157:e7ca05fa8600	936	\param [in] value Value to count the leading zeros
AnnaBridge	157:e7ca05fa8600	937	\return number of leading zeros in value
AnnaBridge	157:e7ca05fa8600	938	*/
AnnaBridge	157:e7ca05fa8600	939	#define __CLZ __builtin_clz
AnnaBridge	157:e7ca05fa8600	940
AnnaBridge	157:e7ca05fa8600	941
AnnaBridge	157:e7ca05fa8600	942	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	943	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	944	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	945	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	157:e7ca05fa8600	946	/**
AnnaBridge	157:e7ca05fa8600	947	\brief LDR Exclusive (8 bit)
AnnaBridge	157:e7ca05fa8600	948	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	157:e7ca05fa8600	949	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	950	\return value of type uint8_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	951	*/
AnnaBridge	157:e7ca05fa8600	952	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge	157:e7ca05fa8600	953	{
AnnaBridge	157:e7ca05fa8600	954	uint32_t result;
AnnaBridge	157:e7ca05fa8600	955
AnnaBridge	157:e7ca05fa8600	956	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	157:e7ca05fa8600	957	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	157:e7ca05fa8600	958	#else
AnnaBridge	157:e7ca05fa8600	959	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	157:e7ca05fa8600	960	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	157:e7ca05fa8600	961	*/
AnnaBridge	157:e7ca05fa8600	962	__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	157:e7ca05fa8600	963	#endif
AnnaBridge	157:e7ca05fa8600	964	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	157:e7ca05fa8600	965	}
AnnaBridge	157:e7ca05fa8600	966
AnnaBridge	157:e7ca05fa8600	967
AnnaBridge	157:e7ca05fa8600	968	/**
AnnaBridge	157:e7ca05fa8600	969	\brief LDR Exclusive (16 bit)
AnnaBridge	157:e7ca05fa8600	970	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	971	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	972	\return value of type uint16_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	973	*/
AnnaBridge	157:e7ca05fa8600	974	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge	157:e7ca05fa8600	975	{
AnnaBridge	157:e7ca05fa8600	976	uint32_t result;
AnnaBridge	157:e7ca05fa8600	977
AnnaBridge	157:e7ca05fa8600	978	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	157:e7ca05fa8600	979	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	157:e7ca05fa8600	980	#else
AnnaBridge	157:e7ca05fa8600	981	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	157:e7ca05fa8600	982	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	157:e7ca05fa8600	983	*/
AnnaBridge	157:e7ca05fa8600	984	__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	157:e7ca05fa8600	985	#endif
AnnaBridge	157:e7ca05fa8600	986	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	157:e7ca05fa8600	987	}
AnnaBridge	157:e7ca05fa8600	988
AnnaBridge	157:e7ca05fa8600	989
AnnaBridge	157:e7ca05fa8600	990	/**
AnnaBridge	157:e7ca05fa8600	991	\brief LDR Exclusive (32 bit)
AnnaBridge	157:e7ca05fa8600	992	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	993	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	994	\return value of type uint32_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	995	*/
AnnaBridge	157:e7ca05fa8600	996	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge	157:e7ca05fa8600	997	{
AnnaBridge	157:e7ca05fa8600	998	uint32_t result;
AnnaBridge	157:e7ca05fa8600	999
AnnaBridge	157:e7ca05fa8600	1000	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	157:e7ca05fa8600	1001	return(result);
AnnaBridge	157:e7ca05fa8600	1002	}
AnnaBridge	157:e7ca05fa8600	1003
AnnaBridge	157:e7ca05fa8600	1004
AnnaBridge	157:e7ca05fa8600	1005	/**
AnnaBridge	157:e7ca05fa8600	1006	\brief STR Exclusive (8 bit)
AnnaBridge	157:e7ca05fa8600	1007	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	157:e7ca05fa8600	1008	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1009	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1010	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1011	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1012	*/
AnnaBridge	157:e7ca05fa8600	1013	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge	157:e7ca05fa8600	1014	{
AnnaBridge	157:e7ca05fa8600	1015	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1016
AnnaBridge	157:e7ca05fa8600	1017	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1018	return(result);
AnnaBridge	157:e7ca05fa8600	1019	}
AnnaBridge	157:e7ca05fa8600	1020
AnnaBridge	157:e7ca05fa8600	1021
AnnaBridge	157:e7ca05fa8600	1022	/**
AnnaBridge	157:e7ca05fa8600	1023	\brief STR Exclusive (16 bit)
AnnaBridge	157:e7ca05fa8600	1024	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1025	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1026	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1027	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1028	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1029	*/
AnnaBridge	157:e7ca05fa8600	1030	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge	157:e7ca05fa8600	1031	{
AnnaBridge	157:e7ca05fa8600	1032	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1033
AnnaBridge	157:e7ca05fa8600	1034	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1035	return(result);
AnnaBridge	157:e7ca05fa8600	1036	}
AnnaBridge	157:e7ca05fa8600	1037
AnnaBridge	157:e7ca05fa8600	1038
AnnaBridge	157:e7ca05fa8600	1039	/**
AnnaBridge	157:e7ca05fa8600	1040	\brief STR Exclusive (32 bit)
AnnaBridge	157:e7ca05fa8600	1041	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1042	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1043	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1044	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1045	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1046	*/
AnnaBridge	157:e7ca05fa8600	1047	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge	157:e7ca05fa8600	1048	{
AnnaBridge	157:e7ca05fa8600	1049	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1050
AnnaBridge	157:e7ca05fa8600	1051	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge	157:e7ca05fa8600	1052	return(result);
AnnaBridge	157:e7ca05fa8600	1053	}
AnnaBridge	157:e7ca05fa8600	1054
AnnaBridge	157:e7ca05fa8600	1055
AnnaBridge	157:e7ca05fa8600	1056	/**
AnnaBridge	157:e7ca05fa8600	1057	\brief Remove the exclusive lock
AnnaBridge	157:e7ca05fa8600	1058	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	157:e7ca05fa8600	1059	*/
AnnaBridge	157:e7ca05fa8600	1060	__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
AnnaBridge	157:e7ca05fa8600	1061	{
AnnaBridge	157:e7ca05fa8600	1062	__ASM volatile ("clrex" ::: "memory");
AnnaBridge	157:e7ca05fa8600	1063	}
AnnaBridge	157:e7ca05fa8600	1064
AnnaBridge	157:e7ca05fa8600	1065	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1066	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1067	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1068	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	1069
AnnaBridge	157:e7ca05fa8600	1070
AnnaBridge	157:e7ca05fa8600	1071	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1072	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1073	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	157:e7ca05fa8600	1074	/**
AnnaBridge	157:e7ca05fa8600	1075	\brief Signed Saturate
AnnaBridge	157:e7ca05fa8600	1076	\details Saturates a signed value.
AnnaBridge	157:e7ca05fa8600	1077	\param [in] value Value to be saturated
AnnaBridge	157:e7ca05fa8600	1078	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	157:e7ca05fa8600	1079	\return Saturated value
AnnaBridge	157:e7ca05fa8600	1080	*/
AnnaBridge	157:e7ca05fa8600	1081	#define __SSAT(ARG1,ARG2) \
AnnaBridge	157:e7ca05fa8600	1082	({ \
AnnaBridge	157:e7ca05fa8600	1083	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	157:e7ca05fa8600	1084	__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	157:e7ca05fa8600	1085	__RES; \
AnnaBridge	157:e7ca05fa8600	1086	})
AnnaBridge	157:e7ca05fa8600	1087
AnnaBridge	157:e7ca05fa8600	1088
AnnaBridge	157:e7ca05fa8600	1089	/**
AnnaBridge	157:e7ca05fa8600	1090	\brief Unsigned Saturate
AnnaBridge	157:e7ca05fa8600	1091	\details Saturates an unsigned value.
AnnaBridge	157:e7ca05fa8600	1092	\param [in] value Value to be saturated
AnnaBridge	157:e7ca05fa8600	1093	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	157:e7ca05fa8600	1094	\return Saturated value
AnnaBridge	157:e7ca05fa8600	1095	*/
AnnaBridge	157:e7ca05fa8600	1096	#define __USAT(ARG1,ARG2) \
AnnaBridge	157:e7ca05fa8600	1097	({ \
AnnaBridge	157:e7ca05fa8600	1098	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	157:e7ca05fa8600	1099	__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	157:e7ca05fa8600	1100	__RES; \
AnnaBridge	157:e7ca05fa8600	1101	})
AnnaBridge	157:e7ca05fa8600	1102
AnnaBridge	157:e7ca05fa8600	1103
AnnaBridge	157:e7ca05fa8600	1104	/**
AnnaBridge	157:e7ca05fa8600	1105	\brief Rotate Right with Extend (32 bit)
AnnaBridge	157:e7ca05fa8600	1106	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	157:e7ca05fa8600	1107	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	157:e7ca05fa8600	1108	\param [in] value Value to rotate
AnnaBridge	157:e7ca05fa8600	1109	\return Rotated value
AnnaBridge	157:e7ca05fa8600	1110	*/
AnnaBridge	157:e7ca05fa8600	1111	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge	157:e7ca05fa8600	1112	{
AnnaBridge	157:e7ca05fa8600	1113	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1114
AnnaBridge	157:e7ca05fa8600	1115	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	157:e7ca05fa8600	1116	return(result);
AnnaBridge	157:e7ca05fa8600	1117	}
AnnaBridge	157:e7ca05fa8600	1118
AnnaBridge	157:e7ca05fa8600	1119
AnnaBridge	157:e7ca05fa8600	1120	/**
AnnaBridge	157:e7ca05fa8600	1121	\brief LDRT Unprivileged (8 bit)
AnnaBridge	157:e7ca05fa8600	1122	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	157:e7ca05fa8600	1123	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1124	\return value of type uint8_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1125	*/
AnnaBridge	157:e7ca05fa8600	1126	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1127	{
AnnaBridge	157:e7ca05fa8600	1128	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1129
AnnaBridge	157:e7ca05fa8600	1130	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	157:e7ca05fa8600	1131	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1132	#else
AnnaBridge	157:e7ca05fa8600	1133	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	157:e7ca05fa8600	1134	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	157:e7ca05fa8600	1135	*/
AnnaBridge	157:e7ca05fa8600	1136	__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	157:e7ca05fa8600	1137	#endif
AnnaBridge	157:e7ca05fa8600	1138	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	157:e7ca05fa8600	1139	}
AnnaBridge	157:e7ca05fa8600	1140
AnnaBridge	157:e7ca05fa8600	1141
AnnaBridge	157:e7ca05fa8600	1142	/**
AnnaBridge	157:e7ca05fa8600	1143	\brief LDRT Unprivileged (16 bit)
AnnaBridge	157:e7ca05fa8600	1144	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1145	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1146	\return value of type uint16_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1147	*/
AnnaBridge	157:e7ca05fa8600	1148	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1149	{
AnnaBridge	157:e7ca05fa8600	1150	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1151
AnnaBridge	157:e7ca05fa8600	1152	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	157:e7ca05fa8600	1153	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1154	#else
AnnaBridge	157:e7ca05fa8600	1155	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	157:e7ca05fa8600	1156	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	157:e7ca05fa8600	1157	*/
AnnaBridge	157:e7ca05fa8600	1158	__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	157:e7ca05fa8600	1159	#endif
AnnaBridge	157:e7ca05fa8600	1160	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	157:e7ca05fa8600	1161	}
AnnaBridge	157:e7ca05fa8600	1162
AnnaBridge	157:e7ca05fa8600	1163
AnnaBridge	157:e7ca05fa8600	1164	/**
AnnaBridge	157:e7ca05fa8600	1165	\brief LDRT Unprivileged (32 bit)
AnnaBridge	157:e7ca05fa8600	1166	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1167	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1168	\return value of type uint32_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1169	*/
AnnaBridge	157:e7ca05fa8600	1170	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1171	{
AnnaBridge	157:e7ca05fa8600	1172	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1173
AnnaBridge	157:e7ca05fa8600	1174	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1175	return(result);
AnnaBridge	157:e7ca05fa8600	1176	}
AnnaBridge	157:e7ca05fa8600	1177
AnnaBridge	157:e7ca05fa8600	1178
AnnaBridge	157:e7ca05fa8600	1179	/**
AnnaBridge	157:e7ca05fa8600	1180	\brief STRT Unprivileged (8 bit)
AnnaBridge	157:e7ca05fa8600	1181	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	157:e7ca05fa8600	1182	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1183	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1184	*/
AnnaBridge	157:e7ca05fa8600	1185	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1186	{
AnnaBridge	157:e7ca05fa8600	1187	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1188	}
AnnaBridge	157:e7ca05fa8600	1189
AnnaBridge	157:e7ca05fa8600	1190
AnnaBridge	157:e7ca05fa8600	1191	/**
AnnaBridge	157:e7ca05fa8600	1192	\brief STRT Unprivileged (16 bit)
AnnaBridge	157:e7ca05fa8600	1193	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1194	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1195	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1196	*/
AnnaBridge	157:e7ca05fa8600	1197	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1198	{
AnnaBridge	157:e7ca05fa8600	1199	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1200	}
AnnaBridge	157:e7ca05fa8600	1201
AnnaBridge	157:e7ca05fa8600	1202
AnnaBridge	157:e7ca05fa8600	1203	/**
AnnaBridge	157:e7ca05fa8600	1204	\brief STRT Unprivileged (32 bit)
AnnaBridge	157:e7ca05fa8600	1205	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1206	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1207	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1208	*/
AnnaBridge	157:e7ca05fa8600	1209	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1210	{
AnnaBridge	157:e7ca05fa8600	1211	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	157:e7ca05fa8600	1212	}
AnnaBridge	157:e7ca05fa8600	1213
AnnaBridge	157:e7ca05fa8600	1214	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1215	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1216	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	1217
AnnaBridge	157:e7ca05fa8600	1218
AnnaBridge	157:e7ca05fa8600	1219	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1220	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	157:e7ca05fa8600	1221	/**
AnnaBridge	157:e7ca05fa8600	1222	\brief Load-Acquire (8 bit)
AnnaBridge	157:e7ca05fa8600	1223	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	157:e7ca05fa8600	1224	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1225	\return value of type uint8_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1226	*/
AnnaBridge	157:e7ca05fa8600	1227	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1228	{
AnnaBridge	157:e7ca05fa8600	1229	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1230
AnnaBridge	157:e7ca05fa8600	1231	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1232	return ((uint8_t) result);
AnnaBridge	157:e7ca05fa8600	1233	}
AnnaBridge	157:e7ca05fa8600	1234
AnnaBridge	157:e7ca05fa8600	1235
AnnaBridge	157:e7ca05fa8600	1236	/**
AnnaBridge	157:e7ca05fa8600	1237	\brief Load-Acquire (16 bit)
AnnaBridge	157:e7ca05fa8600	1238	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1239	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1240	\return value of type uint16_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1241	*/
AnnaBridge	157:e7ca05fa8600	1242	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1243	{
AnnaBridge	157:e7ca05fa8600	1244	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1245
AnnaBridge	157:e7ca05fa8600	1246	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1247	return ((uint16_t) result);
AnnaBridge	157:e7ca05fa8600	1248	}
AnnaBridge	157:e7ca05fa8600	1249
AnnaBridge	157:e7ca05fa8600	1250
AnnaBridge	157:e7ca05fa8600	1251	/**
AnnaBridge	157:e7ca05fa8600	1252	\brief Load-Acquire (32 bit)
AnnaBridge	157:e7ca05fa8600	1253	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1254	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1255	\return value of type uint32_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1256	*/
AnnaBridge	157:e7ca05fa8600	1257	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1258	{
AnnaBridge	157:e7ca05fa8600	1259	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1260
AnnaBridge	157:e7ca05fa8600	1261	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1262	return(result);
AnnaBridge	157:e7ca05fa8600	1263	}
AnnaBridge	157:e7ca05fa8600	1264
AnnaBridge	157:e7ca05fa8600	1265
AnnaBridge	157:e7ca05fa8600	1266	/**
AnnaBridge	157:e7ca05fa8600	1267	\brief Store-Release (8 bit)
AnnaBridge	157:e7ca05fa8600	1268	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	157:e7ca05fa8600	1269	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1270	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1271	*/
AnnaBridge	157:e7ca05fa8600	1272	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1273	{
AnnaBridge	157:e7ca05fa8600	1274	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1275	}
AnnaBridge	157:e7ca05fa8600	1276
AnnaBridge	157:e7ca05fa8600	1277
AnnaBridge	157:e7ca05fa8600	1278	/**
AnnaBridge	157:e7ca05fa8600	1279	\brief Store-Release (16 bit)
AnnaBridge	157:e7ca05fa8600	1280	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1281	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1282	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1283	*/
AnnaBridge	157:e7ca05fa8600	1284	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1285	{
AnnaBridge	157:e7ca05fa8600	1286	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1287	}
AnnaBridge	157:e7ca05fa8600	1288
AnnaBridge	157:e7ca05fa8600	1289
AnnaBridge	157:e7ca05fa8600	1290	/**
AnnaBridge	157:e7ca05fa8600	1291	\brief Store-Release (32 bit)
AnnaBridge	157:e7ca05fa8600	1292	\details Executes a STL instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1293	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1294	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1295	*/
AnnaBridge	157:e7ca05fa8600	1296	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1297	{
AnnaBridge	157:e7ca05fa8600	1298	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1299	}
AnnaBridge	157:e7ca05fa8600	1300
AnnaBridge	157:e7ca05fa8600	1301
AnnaBridge	157:e7ca05fa8600	1302	/**
AnnaBridge	157:e7ca05fa8600	1303	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	157:e7ca05fa8600	1304	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	157:e7ca05fa8600	1305	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1306	\return value of type uint8_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1307	*/
AnnaBridge	157:e7ca05fa8600	1308	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1309	{
AnnaBridge	157:e7ca05fa8600	1310	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1311
AnnaBridge	157:e7ca05fa8600	1312	__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1313	return ((uint8_t) result);
AnnaBridge	157:e7ca05fa8600	1314	}
AnnaBridge	157:e7ca05fa8600	1315
AnnaBridge	157:e7ca05fa8600	1316
AnnaBridge	157:e7ca05fa8600	1317	/**
AnnaBridge	157:e7ca05fa8600	1318	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	157:e7ca05fa8600	1319	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1320	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1321	\return value of type uint16_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1322	*/
AnnaBridge	157:e7ca05fa8600	1323	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1324	{
AnnaBridge	157:e7ca05fa8600	1325	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1326
AnnaBridge	157:e7ca05fa8600	1327	__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1328	return ((uint16_t) result);
AnnaBridge	157:e7ca05fa8600	1329	}
AnnaBridge	157:e7ca05fa8600	1330
AnnaBridge	157:e7ca05fa8600	1331
AnnaBridge	157:e7ca05fa8600	1332	/**
AnnaBridge	157:e7ca05fa8600	1333	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	157:e7ca05fa8600	1334	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1335	\param [in] ptr Pointer to data
AnnaBridge	157:e7ca05fa8600	1336	\return value of type uint32_t at (*ptr)
AnnaBridge	157:e7ca05fa8600	1337	*/
AnnaBridge	157:e7ca05fa8600	1338	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1339	{
AnnaBridge	157:e7ca05fa8600	1340	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1341
AnnaBridge	157:e7ca05fa8600	1342	__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	157:e7ca05fa8600	1343	return(result);
AnnaBridge	157:e7ca05fa8600	1344	}
AnnaBridge	157:e7ca05fa8600	1345
AnnaBridge	157:e7ca05fa8600	1346
AnnaBridge	157:e7ca05fa8600	1347	/**
AnnaBridge	157:e7ca05fa8600	1348	\brief Store-Release Exclusive (8 bit)
AnnaBridge	157:e7ca05fa8600	1349	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	157:e7ca05fa8600	1350	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1351	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1352	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1353	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1354	*/
AnnaBridge	157:e7ca05fa8600	1355	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	157:e7ca05fa8600	1356	{
AnnaBridge	157:e7ca05fa8600	1357	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1358
AnnaBridge	157:e7ca05fa8600	1359	__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1360	return(result);
AnnaBridge	157:e7ca05fa8600	1361	}
AnnaBridge	157:e7ca05fa8600	1362
AnnaBridge	157:e7ca05fa8600	1363
AnnaBridge	157:e7ca05fa8600	1364	/**
AnnaBridge	157:e7ca05fa8600	1365	\brief Store-Release Exclusive (16 bit)
AnnaBridge	157:e7ca05fa8600	1366	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	157:e7ca05fa8600	1367	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1368	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1369	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1370	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1371	*/
AnnaBridge	157:e7ca05fa8600	1372	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	157:e7ca05fa8600	1373	{
AnnaBridge	157:e7ca05fa8600	1374	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1375
AnnaBridge	157:e7ca05fa8600	1376	__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1377	return(result);
AnnaBridge	157:e7ca05fa8600	1378	}
AnnaBridge	157:e7ca05fa8600	1379
AnnaBridge	157:e7ca05fa8600	1380
AnnaBridge	157:e7ca05fa8600	1381	/**
AnnaBridge	157:e7ca05fa8600	1382	\brief Store-Release Exclusive (32 bit)
AnnaBridge	157:e7ca05fa8600	1383	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	157:e7ca05fa8600	1384	\param [in] value Value to store
AnnaBridge	157:e7ca05fa8600	1385	\param [in] ptr Pointer to location
AnnaBridge	157:e7ca05fa8600	1386	\return 0 Function succeeded
AnnaBridge	157:e7ca05fa8600	1387	\return 1 Function failed
AnnaBridge	157:e7ca05fa8600	1388	*/
AnnaBridge	157:e7ca05fa8600	1389	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	157:e7ca05fa8600	1390	{
AnnaBridge	157:e7ca05fa8600	1391	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1392
AnnaBridge	157:e7ca05fa8600	1393	__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	157:e7ca05fa8600	1394	return(result);
AnnaBridge	157:e7ca05fa8600	1395	}
AnnaBridge	157:e7ca05fa8600	1396
AnnaBridge	157:e7ca05fa8600	1397	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	157:e7ca05fa8600	1398	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	157:e7ca05fa8600	1399
AnnaBridge	157:e7ca05fa8600	1400	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	157:e7ca05fa8600	1401
AnnaBridge	157:e7ca05fa8600	1402
AnnaBridge	157:e7ca05fa8600	1403	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	157:e7ca05fa8600	1404	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	157:e7ca05fa8600	1405	Access to dedicated SIMD instructions
AnnaBridge	157:e7ca05fa8600	1406	@{
AnnaBridge	157:e7ca05fa8600	1407	*/
AnnaBridge	157:e7ca05fa8600	1408
AnnaBridge	157:e7ca05fa8600	1409	#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
AnnaBridge	157:e7ca05fa8600	1410
AnnaBridge	157:e7ca05fa8600	1411	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1412	{
AnnaBridge	157:e7ca05fa8600	1413	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1414
AnnaBridge	157:e7ca05fa8600	1415	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1416	return(result);
AnnaBridge	157:e7ca05fa8600	1417	}
AnnaBridge	157:e7ca05fa8600	1418
AnnaBridge	157:e7ca05fa8600	1419	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1420	{
AnnaBridge	157:e7ca05fa8600	1421	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1422
AnnaBridge	157:e7ca05fa8600	1423	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1424	return(result);
AnnaBridge	157:e7ca05fa8600	1425	}
AnnaBridge	157:e7ca05fa8600	1426
AnnaBridge	157:e7ca05fa8600	1427	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1428	{
AnnaBridge	157:e7ca05fa8600	1429	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1430
AnnaBridge	157:e7ca05fa8600	1431	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1432	return(result);
AnnaBridge	157:e7ca05fa8600	1433	}
AnnaBridge	157:e7ca05fa8600	1434
AnnaBridge	157:e7ca05fa8600	1435	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1436	{
AnnaBridge	157:e7ca05fa8600	1437	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1438
AnnaBridge	157:e7ca05fa8600	1439	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1440	return(result);
AnnaBridge	157:e7ca05fa8600	1441	}
AnnaBridge	157:e7ca05fa8600	1442
AnnaBridge	157:e7ca05fa8600	1443	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1444	{
AnnaBridge	157:e7ca05fa8600	1445	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1446
AnnaBridge	157:e7ca05fa8600	1447	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1448	return(result);
AnnaBridge	157:e7ca05fa8600	1449	}
AnnaBridge	157:e7ca05fa8600	1450
AnnaBridge	157:e7ca05fa8600	1451	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1452	{
AnnaBridge	157:e7ca05fa8600	1453	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1454
AnnaBridge	157:e7ca05fa8600	1455	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1456	return(result);
AnnaBridge	157:e7ca05fa8600	1457	}
AnnaBridge	157:e7ca05fa8600	1458
AnnaBridge	157:e7ca05fa8600	1459
AnnaBridge	157:e7ca05fa8600	1460	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1461	{
AnnaBridge	157:e7ca05fa8600	1462	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1463
AnnaBridge	157:e7ca05fa8600	1464	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1465	return(result);
AnnaBridge	157:e7ca05fa8600	1466	}
AnnaBridge	157:e7ca05fa8600	1467
AnnaBridge	157:e7ca05fa8600	1468	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1469	{
AnnaBridge	157:e7ca05fa8600	1470	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1471
AnnaBridge	157:e7ca05fa8600	1472	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1473	return(result);
AnnaBridge	157:e7ca05fa8600	1474	}
AnnaBridge	157:e7ca05fa8600	1475
AnnaBridge	157:e7ca05fa8600	1476	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1477	{
AnnaBridge	157:e7ca05fa8600	1478	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1479
AnnaBridge	157:e7ca05fa8600	1480	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1481	return(result);
AnnaBridge	157:e7ca05fa8600	1482	}
AnnaBridge	157:e7ca05fa8600	1483
AnnaBridge	157:e7ca05fa8600	1484	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1485	{
AnnaBridge	157:e7ca05fa8600	1486	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1487
AnnaBridge	157:e7ca05fa8600	1488	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1489	return(result);
AnnaBridge	157:e7ca05fa8600	1490	}
AnnaBridge	157:e7ca05fa8600	1491
AnnaBridge	157:e7ca05fa8600	1492	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1493	{
AnnaBridge	157:e7ca05fa8600	1494	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1495
AnnaBridge	157:e7ca05fa8600	1496	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1497	return(result);
AnnaBridge	157:e7ca05fa8600	1498	}
AnnaBridge	157:e7ca05fa8600	1499
AnnaBridge	157:e7ca05fa8600	1500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1501	{
AnnaBridge	157:e7ca05fa8600	1502	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1503
AnnaBridge	157:e7ca05fa8600	1504	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1505	return(result);
AnnaBridge	157:e7ca05fa8600	1506	}
AnnaBridge	157:e7ca05fa8600	1507
AnnaBridge	157:e7ca05fa8600	1508
AnnaBridge	157:e7ca05fa8600	1509	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1510	{
AnnaBridge	157:e7ca05fa8600	1511	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1512
AnnaBridge	157:e7ca05fa8600	1513	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1514	return(result);
AnnaBridge	157:e7ca05fa8600	1515	}
AnnaBridge	157:e7ca05fa8600	1516
AnnaBridge	157:e7ca05fa8600	1517	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1518	{
AnnaBridge	157:e7ca05fa8600	1519	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1520
AnnaBridge	157:e7ca05fa8600	1521	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1522	return(result);
AnnaBridge	157:e7ca05fa8600	1523	}
AnnaBridge	157:e7ca05fa8600	1524
AnnaBridge	157:e7ca05fa8600	1525	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1526	{
AnnaBridge	157:e7ca05fa8600	1527	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1528
AnnaBridge	157:e7ca05fa8600	1529	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1530	return(result);
AnnaBridge	157:e7ca05fa8600	1531	}
AnnaBridge	157:e7ca05fa8600	1532
AnnaBridge	157:e7ca05fa8600	1533	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1534	{
AnnaBridge	157:e7ca05fa8600	1535	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1536
AnnaBridge	157:e7ca05fa8600	1537	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1538	return(result);
AnnaBridge	157:e7ca05fa8600	1539	}
AnnaBridge	157:e7ca05fa8600	1540
AnnaBridge	157:e7ca05fa8600	1541	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1542	{
AnnaBridge	157:e7ca05fa8600	1543	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1544
AnnaBridge	157:e7ca05fa8600	1545	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1546	return(result);
AnnaBridge	157:e7ca05fa8600	1547	}
AnnaBridge	157:e7ca05fa8600	1548
AnnaBridge	157:e7ca05fa8600	1549	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1550	{
AnnaBridge	157:e7ca05fa8600	1551	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1552
AnnaBridge	157:e7ca05fa8600	1553	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1554	return(result);
AnnaBridge	157:e7ca05fa8600	1555	}
AnnaBridge	157:e7ca05fa8600	1556
AnnaBridge	157:e7ca05fa8600	1557	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1558	{
AnnaBridge	157:e7ca05fa8600	1559	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1560
AnnaBridge	157:e7ca05fa8600	1561	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1562	return(result);
AnnaBridge	157:e7ca05fa8600	1563	}
AnnaBridge	157:e7ca05fa8600	1564
AnnaBridge	157:e7ca05fa8600	1565	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1566	{
AnnaBridge	157:e7ca05fa8600	1567	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1568
AnnaBridge	157:e7ca05fa8600	1569	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1570	return(result);
AnnaBridge	157:e7ca05fa8600	1571	}
AnnaBridge	157:e7ca05fa8600	1572
AnnaBridge	157:e7ca05fa8600	1573	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1574	{
AnnaBridge	157:e7ca05fa8600	1575	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1576
AnnaBridge	157:e7ca05fa8600	1577	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1578	return(result);
AnnaBridge	157:e7ca05fa8600	1579	}
AnnaBridge	157:e7ca05fa8600	1580
AnnaBridge	157:e7ca05fa8600	1581	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1582	{
AnnaBridge	157:e7ca05fa8600	1583	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1584
AnnaBridge	157:e7ca05fa8600	1585	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1586	return(result);
AnnaBridge	157:e7ca05fa8600	1587	}
AnnaBridge	157:e7ca05fa8600	1588
AnnaBridge	157:e7ca05fa8600	1589	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1590	{
AnnaBridge	157:e7ca05fa8600	1591	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1592
AnnaBridge	157:e7ca05fa8600	1593	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1594	return(result);
AnnaBridge	157:e7ca05fa8600	1595	}
AnnaBridge	157:e7ca05fa8600	1596
AnnaBridge	157:e7ca05fa8600	1597	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1598	{
AnnaBridge	157:e7ca05fa8600	1599	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1600
AnnaBridge	157:e7ca05fa8600	1601	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1602	return(result);
AnnaBridge	157:e7ca05fa8600	1603	}
AnnaBridge	157:e7ca05fa8600	1604
AnnaBridge	157:e7ca05fa8600	1605	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1606	{
AnnaBridge	157:e7ca05fa8600	1607	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1608
AnnaBridge	157:e7ca05fa8600	1609	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1610	return(result);
AnnaBridge	157:e7ca05fa8600	1611	}
AnnaBridge	157:e7ca05fa8600	1612
AnnaBridge	157:e7ca05fa8600	1613	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1614	{
AnnaBridge	157:e7ca05fa8600	1615	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1616
AnnaBridge	157:e7ca05fa8600	1617	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1618	return(result);
AnnaBridge	157:e7ca05fa8600	1619	}
AnnaBridge	157:e7ca05fa8600	1620
AnnaBridge	157:e7ca05fa8600	1621	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1622	{
AnnaBridge	157:e7ca05fa8600	1623	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1624
AnnaBridge	157:e7ca05fa8600	1625	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1626	return(result);
AnnaBridge	157:e7ca05fa8600	1627	}
AnnaBridge	157:e7ca05fa8600	1628
AnnaBridge	157:e7ca05fa8600	1629	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1630	{
AnnaBridge	157:e7ca05fa8600	1631	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1632
AnnaBridge	157:e7ca05fa8600	1633	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1634	return(result);
AnnaBridge	157:e7ca05fa8600	1635	}
AnnaBridge	157:e7ca05fa8600	1636
AnnaBridge	157:e7ca05fa8600	1637	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1638	{
AnnaBridge	157:e7ca05fa8600	1639	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1640
AnnaBridge	157:e7ca05fa8600	1641	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1642	return(result);
AnnaBridge	157:e7ca05fa8600	1643	}
AnnaBridge	157:e7ca05fa8600	1644
AnnaBridge	157:e7ca05fa8600	1645	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1646	{
AnnaBridge	157:e7ca05fa8600	1647	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1648
AnnaBridge	157:e7ca05fa8600	1649	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1650	return(result);
AnnaBridge	157:e7ca05fa8600	1651	}
AnnaBridge	157:e7ca05fa8600	1652
AnnaBridge	157:e7ca05fa8600	1653	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1654	{
AnnaBridge	157:e7ca05fa8600	1655	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1656
AnnaBridge	157:e7ca05fa8600	1657	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1658	return(result);
AnnaBridge	157:e7ca05fa8600	1659	}
AnnaBridge	157:e7ca05fa8600	1660
AnnaBridge	157:e7ca05fa8600	1661	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1662	{
AnnaBridge	157:e7ca05fa8600	1663	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1664
AnnaBridge	157:e7ca05fa8600	1665	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1666	return(result);
AnnaBridge	157:e7ca05fa8600	1667	}
AnnaBridge	157:e7ca05fa8600	1668
AnnaBridge	157:e7ca05fa8600	1669	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1670	{
AnnaBridge	157:e7ca05fa8600	1671	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1672
AnnaBridge	157:e7ca05fa8600	1673	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1674	return(result);
AnnaBridge	157:e7ca05fa8600	1675	}
AnnaBridge	157:e7ca05fa8600	1676
AnnaBridge	157:e7ca05fa8600	1677	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1678	{
AnnaBridge	157:e7ca05fa8600	1679	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1680
AnnaBridge	157:e7ca05fa8600	1681	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1682	return(result);
AnnaBridge	157:e7ca05fa8600	1683	}
AnnaBridge	157:e7ca05fa8600	1684
AnnaBridge	157:e7ca05fa8600	1685	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1686	{
AnnaBridge	157:e7ca05fa8600	1687	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1688
AnnaBridge	157:e7ca05fa8600	1689	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1690	return(result);
AnnaBridge	157:e7ca05fa8600	1691	}
AnnaBridge	157:e7ca05fa8600	1692
AnnaBridge	157:e7ca05fa8600	1693	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1694	{
AnnaBridge	157:e7ca05fa8600	1695	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1696
AnnaBridge	157:e7ca05fa8600	1697	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1698	return(result);
AnnaBridge	157:e7ca05fa8600	1699	}
AnnaBridge	157:e7ca05fa8600	1700
AnnaBridge	157:e7ca05fa8600	1701	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1702	{
AnnaBridge	157:e7ca05fa8600	1703	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1704
AnnaBridge	157:e7ca05fa8600	1705	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1706	return(result);
AnnaBridge	157:e7ca05fa8600	1707	}
AnnaBridge	157:e7ca05fa8600	1708
AnnaBridge	157:e7ca05fa8600	1709	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	157:e7ca05fa8600	1710	{
AnnaBridge	157:e7ca05fa8600	1711	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1712
AnnaBridge	157:e7ca05fa8600	1713	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1714	return(result);
AnnaBridge	157:e7ca05fa8600	1715	}
AnnaBridge	157:e7ca05fa8600	1716
AnnaBridge	157:e7ca05fa8600	1717	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	157:e7ca05fa8600	1718	({ \
AnnaBridge	157:e7ca05fa8600	1719	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	157:e7ca05fa8600	1720	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	157:e7ca05fa8600	1721	__RES; \
AnnaBridge	157:e7ca05fa8600	1722	})
AnnaBridge	157:e7ca05fa8600	1723
AnnaBridge	157:e7ca05fa8600	1724	#define __USAT16(ARG1,ARG2) \
AnnaBridge	157:e7ca05fa8600	1725	({ \
AnnaBridge	157:e7ca05fa8600	1726	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	157:e7ca05fa8600	1727	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	157:e7ca05fa8600	1728	__RES; \
AnnaBridge	157:e7ca05fa8600	1729	})
AnnaBridge	157:e7ca05fa8600	1730
AnnaBridge	157:e7ca05fa8600	1731	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	157:e7ca05fa8600	1732	{
AnnaBridge	157:e7ca05fa8600	1733	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1734
AnnaBridge	157:e7ca05fa8600	1735	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	157:e7ca05fa8600	1736	return(result);
AnnaBridge	157:e7ca05fa8600	1737	}
AnnaBridge	157:e7ca05fa8600	1738
AnnaBridge	157:e7ca05fa8600	1739	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1740	{
AnnaBridge	157:e7ca05fa8600	1741	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1742
AnnaBridge	157:e7ca05fa8600	1743	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1744	return(result);
AnnaBridge	157:e7ca05fa8600	1745	}
AnnaBridge	157:e7ca05fa8600	1746
AnnaBridge	157:e7ca05fa8600	1747	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	157:e7ca05fa8600	1748	{
AnnaBridge	157:e7ca05fa8600	1749	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1750
AnnaBridge	157:e7ca05fa8600	1751	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	157:e7ca05fa8600	1752	return(result);
AnnaBridge	157:e7ca05fa8600	1753	}
AnnaBridge	157:e7ca05fa8600	1754
AnnaBridge	157:e7ca05fa8600	1755	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1756	{
AnnaBridge	157:e7ca05fa8600	1757	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1758
AnnaBridge	157:e7ca05fa8600	1759	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1760	return(result);
AnnaBridge	157:e7ca05fa8600	1761	}
AnnaBridge	157:e7ca05fa8600	1762
AnnaBridge	157:e7ca05fa8600	1763	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1764	{
AnnaBridge	157:e7ca05fa8600	1765	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1766
AnnaBridge	157:e7ca05fa8600	1767	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1768	return(result);
AnnaBridge	157:e7ca05fa8600	1769	}
AnnaBridge	157:e7ca05fa8600	1770
AnnaBridge	157:e7ca05fa8600	1771	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1772	{
AnnaBridge	157:e7ca05fa8600	1773	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1774
AnnaBridge	157:e7ca05fa8600	1775	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1776	return(result);
AnnaBridge	157:e7ca05fa8600	1777	}
AnnaBridge	157:e7ca05fa8600	1778
AnnaBridge	157:e7ca05fa8600	1779	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	157:e7ca05fa8600	1780	{
AnnaBridge	157:e7ca05fa8600	1781	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1782
AnnaBridge	157:e7ca05fa8600	1783	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1784	return(result);
AnnaBridge	157:e7ca05fa8600	1785	}
AnnaBridge	157:e7ca05fa8600	1786
AnnaBridge	157:e7ca05fa8600	1787	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	157:e7ca05fa8600	1788	{
AnnaBridge	157:e7ca05fa8600	1789	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1790
AnnaBridge	157:e7ca05fa8600	1791	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1792	return(result);
AnnaBridge	157:e7ca05fa8600	1793	}
AnnaBridge	157:e7ca05fa8600	1794
AnnaBridge	157:e7ca05fa8600	1795	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	157:e7ca05fa8600	1796	{
AnnaBridge	157:e7ca05fa8600	1797	union llreg_u{
AnnaBridge	157:e7ca05fa8600	1798	uint32_t w32[2];
AnnaBridge	157:e7ca05fa8600	1799	uint64_t w64;
AnnaBridge	157:e7ca05fa8600	1800	} llr;
AnnaBridge	157:e7ca05fa8600	1801	llr.w64 = acc;
AnnaBridge	157:e7ca05fa8600	1802
AnnaBridge	157:e7ca05fa8600	1803	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	157:e7ca05fa8600	1804	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	157:e7ca05fa8600	1805	#else /* Big endian */
AnnaBridge	157:e7ca05fa8600	1806	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	157:e7ca05fa8600	1807	#endif
AnnaBridge	157:e7ca05fa8600	1808
AnnaBridge	157:e7ca05fa8600	1809	return(llr.w64);
AnnaBridge	157:e7ca05fa8600	1810	}
AnnaBridge	157:e7ca05fa8600	1811
AnnaBridge	157:e7ca05fa8600	1812	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	157:e7ca05fa8600	1813	{
AnnaBridge	157:e7ca05fa8600	1814	union llreg_u{
AnnaBridge	157:e7ca05fa8600	1815	uint32_t w32[2];
AnnaBridge	157:e7ca05fa8600	1816	uint64_t w64;
AnnaBridge	157:e7ca05fa8600	1817	} llr;
AnnaBridge	157:e7ca05fa8600	1818	llr.w64 = acc;
AnnaBridge	157:e7ca05fa8600	1819
AnnaBridge	157:e7ca05fa8600	1820	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	157:e7ca05fa8600	1821	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	157:e7ca05fa8600	1822	#else /* Big endian */
AnnaBridge	157:e7ca05fa8600	1823	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	157:e7ca05fa8600	1824	#endif
AnnaBridge	157:e7ca05fa8600	1825
AnnaBridge	157:e7ca05fa8600	1826	return(llr.w64);
AnnaBridge	157:e7ca05fa8600	1827	}
AnnaBridge	157:e7ca05fa8600	1828
AnnaBridge	157:e7ca05fa8600	1829	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1830	{
AnnaBridge	157:e7ca05fa8600	1831	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1832
AnnaBridge	157:e7ca05fa8600	1833	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1834	return(result);
AnnaBridge	157:e7ca05fa8600	1835	}
AnnaBridge	157:e7ca05fa8600	1836
AnnaBridge	157:e7ca05fa8600	1837	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1838	{
AnnaBridge	157:e7ca05fa8600	1839	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1840
AnnaBridge	157:e7ca05fa8600	1841	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1842	return(result);
AnnaBridge	157:e7ca05fa8600	1843	}
AnnaBridge	157:e7ca05fa8600	1844
AnnaBridge	157:e7ca05fa8600	1845	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	157:e7ca05fa8600	1846	{
AnnaBridge	157:e7ca05fa8600	1847	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1848
AnnaBridge	157:e7ca05fa8600	1849	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1850	return(result);
AnnaBridge	157:e7ca05fa8600	1851	}
AnnaBridge	157:e7ca05fa8600	1852
AnnaBridge	157:e7ca05fa8600	1853	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	157:e7ca05fa8600	1854	{
AnnaBridge	157:e7ca05fa8600	1855	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1856
AnnaBridge	157:e7ca05fa8600	1857	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1858	return(result);
AnnaBridge	157:e7ca05fa8600	1859	}
AnnaBridge	157:e7ca05fa8600	1860
AnnaBridge	157:e7ca05fa8600	1861	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	157:e7ca05fa8600	1862	{
AnnaBridge	157:e7ca05fa8600	1863	union llreg_u{
AnnaBridge	157:e7ca05fa8600	1864	uint32_t w32[2];
AnnaBridge	157:e7ca05fa8600	1865	uint64_t w64;
AnnaBridge	157:e7ca05fa8600	1866	} llr;
AnnaBridge	157:e7ca05fa8600	1867	llr.w64 = acc;
AnnaBridge	157:e7ca05fa8600	1868
AnnaBridge	157:e7ca05fa8600	1869	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	157:e7ca05fa8600	1870	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	157:e7ca05fa8600	1871	#else /* Big endian */
AnnaBridge	157:e7ca05fa8600	1872	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	157:e7ca05fa8600	1873	#endif
AnnaBridge	157:e7ca05fa8600	1874
AnnaBridge	157:e7ca05fa8600	1875	return(llr.w64);
AnnaBridge	157:e7ca05fa8600	1876	}
AnnaBridge	157:e7ca05fa8600	1877
AnnaBridge	157:e7ca05fa8600	1878	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	157:e7ca05fa8600	1879	{
AnnaBridge	157:e7ca05fa8600	1880	union llreg_u{
AnnaBridge	157:e7ca05fa8600	1881	uint32_t w32[2];
AnnaBridge	157:e7ca05fa8600	1882	uint64_t w64;
AnnaBridge	157:e7ca05fa8600	1883	} llr;
AnnaBridge	157:e7ca05fa8600	1884	llr.w64 = acc;
AnnaBridge	157:e7ca05fa8600	1885
AnnaBridge	157:e7ca05fa8600	1886	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	157:e7ca05fa8600	1887	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	157:e7ca05fa8600	1888	#else /* Big endian */
AnnaBridge	157:e7ca05fa8600	1889	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	157:e7ca05fa8600	1890	#endif
AnnaBridge	157:e7ca05fa8600	1891
AnnaBridge	157:e7ca05fa8600	1892	return(llr.w64);
AnnaBridge	157:e7ca05fa8600	1893	}
AnnaBridge	157:e7ca05fa8600	1894
AnnaBridge	157:e7ca05fa8600	1895	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	157:e7ca05fa8600	1896	{
AnnaBridge	157:e7ca05fa8600	1897	uint32_t result;
AnnaBridge	157:e7ca05fa8600	1898
AnnaBridge	157:e7ca05fa8600	1899	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1900	return(result);
AnnaBridge	157:e7ca05fa8600	1901	}
AnnaBridge	157:e7ca05fa8600	1902
AnnaBridge	157:e7ca05fa8600	1903	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	157:e7ca05fa8600	1904	{
AnnaBridge	157:e7ca05fa8600	1905	int32_t result;
AnnaBridge	157:e7ca05fa8600	1906
AnnaBridge	157:e7ca05fa8600	1907	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1908	return(result);
AnnaBridge	157:e7ca05fa8600	1909	}
AnnaBridge	157:e7ca05fa8600	1910
AnnaBridge	157:e7ca05fa8600	1911	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	157:e7ca05fa8600	1912	{
AnnaBridge	157:e7ca05fa8600	1913	int32_t result;
AnnaBridge	157:e7ca05fa8600	1914
AnnaBridge	157:e7ca05fa8600	1915	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	157:e7ca05fa8600	1916	return(result);
AnnaBridge	157:e7ca05fa8600	1917	}
AnnaBridge	157:e7ca05fa8600	1918
AnnaBridge	157:e7ca05fa8600	1919	#if 0
AnnaBridge	157:e7ca05fa8600	1920	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	157:e7ca05fa8600	1921	({ \
AnnaBridge	157:e7ca05fa8600	1922	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	157:e7ca05fa8600	1923	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	157:e7ca05fa8600	1924	__RES; \
AnnaBridge	157:e7ca05fa8600	1925	})
AnnaBridge	157:e7ca05fa8600	1926
AnnaBridge	157:e7ca05fa8600	1927	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	157:e7ca05fa8600	1928	({ \
AnnaBridge	157:e7ca05fa8600	1929	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	157:e7ca05fa8600	1930	if (ARG3 == 0) \
AnnaBridge	157:e7ca05fa8600	1931	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	157:e7ca05fa8600	1932	else \
AnnaBridge	157:e7ca05fa8600	1933	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	157:e7ca05fa8600	1934	__RES; \
AnnaBridge	157:e7ca05fa8600	1935	})
AnnaBridge	157:e7ca05fa8600	1936	#endif
AnnaBridge	157:e7ca05fa8600	1937
AnnaBridge	157:e7ca05fa8600	1938	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	157:e7ca05fa8600	1939	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	157:e7ca05fa8600	1940
AnnaBridge	157:e7ca05fa8600	1941	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	157:e7ca05fa8600	1942	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	157:e7ca05fa8600	1943
AnnaBridge	157:e7ca05fa8600	1944	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	157:e7ca05fa8600	1945	{
AnnaBridge	157:e7ca05fa8600	1946	int32_t result;
AnnaBridge	157:e7ca05fa8600	1947
AnnaBridge	157:e7ca05fa8600	1948	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	157:e7ca05fa8600	1949	return(result);
AnnaBridge	157:e7ca05fa8600	1950	}
AnnaBridge	157:e7ca05fa8600	1951
AnnaBridge	157:e7ca05fa8600	1952	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	157:e7ca05fa8600	1953	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	157:e7ca05fa8600	1954
AnnaBridge	157:e7ca05fa8600	1955
AnnaBridge	157:e7ca05fa8600	1956	#pragma GCC diagnostic pop
AnnaBridge	157:e7ca05fa8600	1957
AnnaBridge	157:e7ca05fa8600	1958	#endif /* __CMSIS_GCC_H */