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TARGET_NUCLEO_F767ZI/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h@163:e59c8e839560, 2018-03-20 (annotated)

Committer:: AnnaBridge
Date:: Tue Mar 20 13:30:58 2018 +0000
Revision:: 163:e59c8e839560
Parent:: 139:856d2700e60b

mbed library. Release version 160

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User	Revision	Line number	New contents of line
<>	139:856d2700e60b	1	/**
<>	139:856d2700e60b	2	******************************************************************************
<>	139:856d2700e60b	3	* @file stm32f7xx_ll_adc.h
<>	139:856d2700e60b	4	* @author MCD Application Team
<>	139:856d2700e60b	5	* @brief Header file of ADC LL module.
<>	139:856d2700e60b	6	******************************************************************************
<>	139:856d2700e60b	7	* @attention
<>	139:856d2700e60b	8	*
<>	139:856d2700e60b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	139:856d2700e60b	10	*
<>	139:856d2700e60b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	139:856d2700e60b	12	* are permitted provided that the following conditions are met:
<>	139:856d2700e60b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	139:856d2700e60b	14	* this list of conditions and the following disclaimer.
<>	139:856d2700e60b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	139:856d2700e60b	16	* this list of conditions and the following disclaimer in the documentation
<>	139:856d2700e60b	17	* and/or other materials provided with the distribution.
<>	139:856d2700e60b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	139:856d2700e60b	19	* may be used to endorse or promote products derived from this software
<>	139:856d2700e60b	20	* without specific prior written permission.
<>	139:856d2700e60b	21	*
<>	139:856d2700e60b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	139:856d2700e60b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	139:856d2700e60b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	139:856d2700e60b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	139:856d2700e60b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	139:856d2700e60b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	139:856d2700e60b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	139:856d2700e60b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	139:856d2700e60b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	139:856d2700e60b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	139:856d2700e60b	32	*
<>	139:856d2700e60b	33	******************************************************************************
<>	139:856d2700e60b	34	*/
<>	139:856d2700e60b	35
<>	139:856d2700e60b	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	139:856d2700e60b	37	#ifndef __STM32F7xx_LL_ADC_H
<>	139:856d2700e60b	38	#define __STM32F7xx_LL_ADC_H
<>	139:856d2700e60b	39
<>	139:856d2700e60b	40	#ifdef __cplusplus
<>	139:856d2700e60b	41	extern "C" {
<>	139:856d2700e60b	42	#endif
<>	139:856d2700e60b	43
<>	139:856d2700e60b	44	/* Includes ------------------------------------------------------------------*/
<>	139:856d2700e60b	45	#include "stm32f7xx.h"
<>	139:856d2700e60b	46
<>	139:856d2700e60b	47	/** @addtogroup STM32F7xx_LL_Driver
<>	139:856d2700e60b	48	* @{
<>	139:856d2700e60b	49	*/
<>	139:856d2700e60b	50
<>	139:856d2700e60b	51	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
<>	139:856d2700e60b	52
<>	139:856d2700e60b	53	/** @defgroup ADC_LL ADC
<>	139:856d2700e60b	54	* @{
<>	139:856d2700e60b	55	*/
<>	139:856d2700e60b	56
<>	139:856d2700e60b	57	/* Private types -------------------------------------------------------------*/
<>	139:856d2700e60b	58	/* Private variables ---------------------------------------------------------*/
<>	139:856d2700e60b	59
<>	139:856d2700e60b	60	/* Private constants ---------------------------------------------------------*/
<>	139:856d2700e60b	61	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
<>	139:856d2700e60b	62	* @{
<>	139:856d2700e60b	63	*/
<>	139:856d2700e60b	64
<>	139:856d2700e60b	65	/* Internal mask for ADC group regular sequencer: */
<>	139:856d2700e60b	66	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
<>	139:856d2700e60b	67	/* - sequencer register offset */
<>	139:856d2700e60b	68	/* - sequencer rank bits position into the selected register */
<>	139:856d2700e60b	69
<>	139:856d2700e60b	70	/* Internal register offset for ADC group regular sequencer configuration */
<>	139:856d2700e60b	71	/* (offset placed into a spare area of literal definition) */
<>	139:856d2700e60b	72	#define ADC_SQR1_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	73	#define ADC_SQR2_REGOFFSET (0x00000100U)
<>	139:856d2700e60b	74	#define ADC_SQR3_REGOFFSET (0x00000200U)
<>	139:856d2700e60b	75	#define ADC_SQR4_REGOFFSET (0x00000300U)
<>	139:856d2700e60b	76
<>	139:856d2700e60b	77	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
<>	139:856d2700e60b	78	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	139:856d2700e60b	79
<>	139:856d2700e60b	80	/* Definition of ADC group regular sequencer bits information to be inserted */
<>	139:856d2700e60b	81	/* into ADC group regular sequencer ranks literals definition. */
<>	139:856d2700e60b	82	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
<>	139:856d2700e60b	83	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
<>	139:856d2700e60b	84	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
<>	139:856d2700e60b	85	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
<>	139:856d2700e60b	86	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
<>	139:856d2700e60b	87	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
<>	139:856d2700e60b	88	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
<>	139:856d2700e60b	89	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
<>	139:856d2700e60b	90	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
<>	139:856d2700e60b	91	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
<>	139:856d2700e60b	92	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
<>	139:856d2700e60b	93	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
<>	139:856d2700e60b	94	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
<>	139:856d2700e60b	95	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
<>	139:856d2700e60b	96	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
<>	139:856d2700e60b	97	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
<>	139:856d2700e60b	98
<>	139:856d2700e60b	99
<>	139:856d2700e60b	100
<>	139:856d2700e60b	101	/* Internal mask for ADC group injected sequencer: */
<>	139:856d2700e60b	102	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
<>	139:856d2700e60b	103	/* - data register offset */
<>	139:856d2700e60b	104	/* - offset register offset */
<>	139:856d2700e60b	105	/* - sequencer rank bits position into the selected register */
<>	139:856d2700e60b	106
<>	139:856d2700e60b	107	/* Internal register offset for ADC group injected data register */
<>	139:856d2700e60b	108	/* (offset placed into a spare area of literal definition) */
<>	139:856d2700e60b	109	#define ADC_JDR1_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	110	#define ADC_JDR2_REGOFFSET (0x00000100U)
<>	139:856d2700e60b	111	#define ADC_JDR3_REGOFFSET (0x00000200U)
<>	139:856d2700e60b	112	#define ADC_JDR4_REGOFFSET (0x00000300U)
<>	139:856d2700e60b	113
<>	139:856d2700e60b	114	/* Internal register offset for ADC group injected offset configuration */
<>	139:856d2700e60b	115	/* (offset placed into a spare area of literal definition) */
<>	139:856d2700e60b	116	#define ADC_JOFR1_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	117	#define ADC_JOFR2_REGOFFSET (0x00001000U)
<>	139:856d2700e60b	118	#define ADC_JOFR3_REGOFFSET (0x00002000U)
<>	139:856d2700e60b	119	#define ADC_JOFR4_REGOFFSET (0x00003000U)
<>	139:856d2700e60b	120
<>	139:856d2700e60b	121	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
<>	139:856d2700e60b	122	#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_JOFR4_REGOFFSET)
<>	139:856d2700e60b	123	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	139:856d2700e60b	124
<>	139:856d2700e60b	125	/* Definition of ADC group injected sequencer bits information to be inserted */
<>	139:856d2700e60b	126	/* into ADC group injected sequencer ranks literals definition. */
<>	139:856d2700e60b	127	#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
<>	139:856d2700e60b	128	#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
<>	139:856d2700e60b	129	#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
<>	139:856d2700e60b	130	#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
<>	139:856d2700e60b	131
<>	139:856d2700e60b	132
<>	139:856d2700e60b	133
<>	139:856d2700e60b	134	/* Internal mask for ADC group regular trigger: */
<>	139:856d2700e60b	135	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<>	139:856d2700e60b	136	/* - regular trigger source */
<>	139:856d2700e60b	137	/* - regular trigger edge */
<>	139:856d2700e60b	138	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	139:856d2700e60b	139
<>	139:856d2700e60b	140	/* Mask containing trigger source masks for each of possible */
<>	139:856d2700e60b	141	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	139:856d2700e60b	142	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	139:856d2700e60b	143	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) \| \
<>	139:856d2700e60b	144	((ADC_CR2_EXTSEL) >> (4U * 1U)) \| \
<>	139:856d2700e60b	145	((ADC_CR2_EXTSEL) >> (4U * 2U)) \| \
<>	139:856d2700e60b	146	((ADC_CR2_EXTSEL) >> (4U * 3U)) )
<>	139:856d2700e60b	147
<>	139:856d2700e60b	148	/* Mask containing trigger edge masks for each of possible */
<>	139:856d2700e60b	149	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	139:856d2700e60b	150	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	139:856d2700e60b	151	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) \| \
<>	139:856d2700e60b	152	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	139:856d2700e60b	153	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	139:856d2700e60b	154	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	139:856d2700e60b	155
<>	139:856d2700e60b	156	/* Definition of ADC group regular trigger bits information. */
<>	139:856d2700e60b	157	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
<>	139:856d2700e60b	158	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
<>	139:856d2700e60b	159
<>	139:856d2700e60b	160
<>	139:856d2700e60b	161
<>	139:856d2700e60b	162	/* Internal mask for ADC group injected trigger: */
<>	139:856d2700e60b	163	/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
<>	139:856d2700e60b	164	/* - injected trigger source */
<>	139:856d2700e60b	165	/* - injected trigger edge */
<>	139:856d2700e60b	166	#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	139:856d2700e60b	167
<>	139:856d2700e60b	168	/* Mask containing trigger source masks for each of possible */
<>	139:856d2700e60b	169	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	139:856d2700e60b	170	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	139:856d2700e60b	171	#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) \| \
<>	139:856d2700e60b	172	((ADC_CR2_JEXTSEL) >> (4U * 1U)) \| \
<>	139:856d2700e60b	173	((ADC_CR2_JEXTSEL) >> (4U * 2U)) \| \
<>	139:856d2700e60b	174	((ADC_CR2_JEXTSEL) >> (4U * 3U)) )
<>	139:856d2700e60b	175
<>	139:856d2700e60b	176	/* Mask containing trigger edge masks for each of possible */
<>	139:856d2700e60b	177	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	139:856d2700e60b	178	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	139:856d2700e60b	179	#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) \| \
<>	139:856d2700e60b	180	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	139:856d2700e60b	181	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	139:856d2700e60b	182	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	139:856d2700e60b	183
<>	139:856d2700e60b	184	/* Definition of ADC group injected trigger bits information. */
<>	139:856d2700e60b	185	#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
<>	139:856d2700e60b	186	#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
<>	139:856d2700e60b	187
<>	139:856d2700e60b	188
<>	139:856d2700e60b	189
<>	139:856d2700e60b	190
<>	139:856d2700e60b	191
<>	139:856d2700e60b	192
<>	139:856d2700e60b	193	/* Internal mask for ADC channel: */
<>	139:856d2700e60b	194	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<>	139:856d2700e60b	195	/* - channel identifier defined by number */
<>	139:856d2700e60b	196	/* - channel differentiation between external channels (connected to */
<>	139:856d2700e60b	197	/* GPIO pins) and internal channels (connected to internal paths) */
<>	139:856d2700e60b	198	/* - channel sampling time defined by SMPRx register offset */
<>	139:856d2700e60b	199	/* and SMPx bits positions into SMPRx register */
<>	139:856d2700e60b	200	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
<>	139:856d2700e60b	201	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<>	139:856d2700e60b	202	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	139:856d2700e60b	203	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<>	139:856d2700e60b	204	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<>	139:856d2700e60b	205
<>	139:856d2700e60b	206	/* Channel differentiation between external and internal channels */
<>	139:856d2700e60b	207	#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
<>	139:856d2700e60b	208	#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
<>	139:856d2700e60b	209	#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT (0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
<>	139:856d2700e60b	210	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2 \| ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
<>	139:856d2700e60b	211
<>	139:856d2700e60b	212	/* Internal register offset for ADC channel sampling time configuration */
<>	139:856d2700e60b	213	/* (offset placed into a spare area of literal definition) */
<>	139:856d2700e60b	214	#define ADC_SMPR1_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	215	#define ADC_SMPR2_REGOFFSET (0x02000000U)
<>	139:856d2700e60b	216	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
<>	139:856d2700e60b	217
<>	139:856d2700e60b	218	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U)
<>	139:856d2700e60b	219	#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
<>	139:856d2700e60b	220
<>	139:856d2700e60b	221	/* Definition of channels ID number information to be inserted into */
<>	139:856d2700e60b	222	/* channels literals definition. */
<>	139:856d2700e60b	223	#define ADC_CHANNEL_0_NUMBER (0x00000000U)
<>	139:856d2700e60b	224	#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	225	#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
<>	139:856d2700e60b	226	#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	227	#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
<>	139:856d2700e60b	228	#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	229	#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	139:856d2700e60b	230	#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	231	#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
<>	139:856d2700e60b	232	#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	233	#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
<>	139:856d2700e60b	234	#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	235	#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
<>	139:856d2700e60b	236	#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	237	#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	139:856d2700e60b	238	#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	239	#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
<>	139:856d2700e60b	240	#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0)
<>	139:856d2700e60b	241	#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1 )
<>	139:856d2700e60b	242
<>	139:856d2700e60b	243	/* Definition of channels sampling time information to be inserted into */
<>	139:856d2700e60b	244	/* channels literals definition. */
<>	139:856d2700e60b	245	#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
<>	139:856d2700e60b	246	#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
<>	139:856d2700e60b	247	#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
<>	139:856d2700e60b	248	#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
<>	139:856d2700e60b	249	#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
<>	139:856d2700e60b	250	#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
<>	139:856d2700e60b	251	#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
<>	139:856d2700e60b	252	#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
<>	139:856d2700e60b	253	#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
<>	139:856d2700e60b	254	#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET \| ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
<>	139:856d2700e60b	255	#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
<>	139:856d2700e60b	256	#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
<>	139:856d2700e60b	257	#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
<>	139:856d2700e60b	258	#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
<>	139:856d2700e60b	259	#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
<>	139:856d2700e60b	260	#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
<>	139:856d2700e60b	261	#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
<>	139:856d2700e60b	262	#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
<>	139:856d2700e60b	263	#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
<>	139:856d2700e60b	264
<>	139:856d2700e60b	265
<>	139:856d2700e60b	266	/* Internal mask for ADC analog watchdog: */
<>	139:856d2700e60b	267	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<>	139:856d2700e60b	268	/* (concatenation of multiple bits used in different analog watchdogs, */
<>	139:856d2700e60b	269	/* (feature of several watchdogs not available on all STM32 families)). */
<>	139:856d2700e60b	270	/* - analog watchdog 1: monitored channel defined by number, */
<>	139:856d2700e60b	271	/* selection of ADC group (ADC groups regular and-or injected). */
<>	139:856d2700e60b	272
<>	139:856d2700e60b	273	/* Internal register offset for ADC analog watchdog channel configuration */
<>	139:856d2700e60b	274	#define ADC_AWD_CR1_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	275
<>	139:856d2700e60b	276	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
<>	139:856d2700e60b	277
<>	139:856d2700e60b	278	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
<>	139:856d2700e60b	279	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
<>	139:856d2700e60b	280
<>	139:856d2700e60b	281	/* Internal register offset for ADC analog watchdog threshold configuration */
<>	139:856d2700e60b	282	#define ADC_AWD_TR1_HIGH_REGOFFSET (0x00000000U)
<>	139:856d2700e60b	283	#define ADC_AWD_TR1_LOW_REGOFFSET (0x00000001U)
<>	139:856d2700e60b	284	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET \| ADC_AWD_TR1_LOW_REGOFFSET)
<>	139:856d2700e60b	285
<>	139:856d2700e60b	286
<>	139:856d2700e60b	287	/* ADC registers bits positions */
<>	139:856d2700e60b	288	#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
<>	139:856d2700e60b	289	#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
<>	139:856d2700e60b	290
<>	139:856d2700e60b	291
<>	139:856d2700e60b	292	/* ADC internal channels related definitions */
<>	139:856d2700e60b	293	/* Internal voltage reference VrefInt */
<>	139:856d2700e60b	294	#define VREFINT_CAL_ADDR ((uint16_t) (0x1FF07A4A)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	139:856d2700e60b	295	#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<>	139:856d2700e60b	296	/* Temperature sensor */
<>	139:856d2700e60b	297	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FF07A4C)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	139:856d2700e60b	298	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FF07A4E)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	139:856d2700e60b	299	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	139:856d2700e60b	300	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	139:856d2700e60b	301	#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<>	139:856d2700e60b	302
<>	139:856d2700e60b	303	/**
<>	139:856d2700e60b	304	* @}
<>	139:856d2700e60b	305	*/
<>	139:856d2700e60b	306
<>	139:856d2700e60b	307
<>	139:856d2700e60b	308	/* Private macros ------------------------------------------------------------*/
<>	139:856d2700e60b	309	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
<>	139:856d2700e60b	310	* @{
<>	139:856d2700e60b	311	*/
<>	139:856d2700e60b	312
<>	139:856d2700e60b	313	/**
<>	139:856d2700e60b	314	* @brief Driver macro reserved for internal use: isolate bits with the
<>	139:856d2700e60b	315	* selected mask and shift them to the register LSB
<>	139:856d2700e60b	316	* (shift mask on register position bit 0).
<>	139:856d2700e60b	317	* @param __BITS__ Bits in register 32 bits
<>	139:856d2700e60b	318	* @param __MASK__ Mask in register 32 bits
<>	139:856d2700e60b	319	* @retval Bits in register 32 bits
<>	139:856d2700e60b	320	*/
<>	139:856d2700e60b	321	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
<>	139:856d2700e60b	322	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<>	139:856d2700e60b	323
<>	139:856d2700e60b	324	/**
<>	139:856d2700e60b	325	* @brief Driver macro reserved for internal use: set a pointer to
<>	139:856d2700e60b	326	* a register from a register basis from which an offset
<>	139:856d2700e60b	327	* is applied.
<>	139:856d2700e60b	328	* @param __REG__ Register basis from which the offset is applied.
AnnaBridge	163:e59c8e839560	329	* @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
<>	139:856d2700e60b	330	* @retval Pointer to register address
<>	139:856d2700e60b	331	*/
<>	139:856d2700e60b	332	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	139:856d2700e60b	333	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	139:856d2700e60b	334
<>	139:856d2700e60b	335	/**
<>	139:856d2700e60b	336	* @}
<>	139:856d2700e60b	337	*/
<>	139:856d2700e60b	338
<>	139:856d2700e60b	339
<>	139:856d2700e60b	340	/* Exported types ------------------------------------------------------------*/
<>	139:856d2700e60b	341	#if defined(USE_FULL_LL_DRIVER)
<>	139:856d2700e60b	342	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<>	139:856d2700e60b	343	* @{
<>	139:856d2700e60b	344	*/
<>	139:856d2700e60b	345
<>	139:856d2700e60b	346	/**
<>	139:856d2700e60b	347	* @brief Structure definition of some features of ADC common parameters
<>	139:856d2700e60b	348	* and multimode
<>	139:856d2700e60b	349	* (all ADC instances belonging to the same ADC common instance).
<>	139:856d2700e60b	350	* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
<>	139:856d2700e60b	351	* is conditioned to ADC instances state (all ADC instances
<>	139:856d2700e60b	352	* sharing the same ADC common instance):
<>	139:856d2700e60b	353	* All ADC instances sharing the same ADC common instance must be
<>	139:856d2700e60b	354	* disabled.
<>	139:856d2700e60b	355	*/
<>	139:856d2700e60b	356	typedef struct
<>	139:856d2700e60b	357	{
<>	139:856d2700e60b	358	uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
<>	139:856d2700e60b	359	This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
<>	139:856d2700e60b	360
<>	139:856d2700e60b	361	This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
<>	139:856d2700e60b	362
<>	139:856d2700e60b	363	uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
<>	139:856d2700e60b	364	This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
<>	139:856d2700e60b	365
<>	139:856d2700e60b	366	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
<>	139:856d2700e60b	367
<>	139:856d2700e60b	368	uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
<>	139:856d2700e60b	369	This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
<>	139:856d2700e60b	370
<>	139:856d2700e60b	371	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
<>	139:856d2700e60b	372
<>	139:856d2700e60b	373	uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
<>	139:856d2700e60b	374	This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
<>	139:856d2700e60b	375
<>	139:856d2700e60b	376	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
<>	139:856d2700e60b	377
<>	139:856d2700e60b	378	} LL_ADC_CommonInitTypeDef;
<>	139:856d2700e60b	379
<>	139:856d2700e60b	380	/**
<>	139:856d2700e60b	381	* @brief Structure definition of some features of ADC instance.
<>	139:856d2700e60b	382	* @note These parameters have an impact on ADC scope: ADC instance.
<>	139:856d2700e60b	383	* Affects both group regular and group injected (availability
<>	139:856d2700e60b	384	* of ADC group injected depends on STM32 families).
<>	139:856d2700e60b	385	* Refer to corresponding unitary functions into
<>	139:856d2700e60b	386	* @ref ADC_LL_EF_Configuration_ADC_Instance .
<>	139:856d2700e60b	387	* @note The setting of these parameters by function @ref LL_ADC_Init()
<>	139:856d2700e60b	388	* is conditioned to ADC state:
<>	139:856d2700e60b	389	* ADC instance must be disabled.
<>	139:856d2700e60b	390	* This condition is applied to all ADC features, for efficiency
<>	139:856d2700e60b	391	* and compatibility over all STM32 families. However, the different
<>	139:856d2700e60b	392	* features can be set under different ADC state conditions
<>	139:856d2700e60b	393	* (setting possible with ADC enabled without conversion on going,
<>	139:856d2700e60b	394	* ADC enabled with conversion on going, ...)
<>	139:856d2700e60b	395	* Each feature can be updated afterwards with a unitary function
<>	139:856d2700e60b	396	* and potentially with ADC in a different state than disabled,
<>	139:856d2700e60b	397	* refer to description of each function for setting
<>	139:856d2700e60b	398	* conditioned to ADC state.
<>	139:856d2700e60b	399	*/
<>	139:856d2700e60b	400	typedef struct
<>	139:856d2700e60b	401	{
<>	139:856d2700e60b	402	uint32_t Resolution; /*!< Set ADC resolution.
<>	139:856d2700e60b	403	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<>	139:856d2700e60b	404
<>	139:856d2700e60b	405	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<>	139:856d2700e60b	406
<>	139:856d2700e60b	407	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<>	139:856d2700e60b	408	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<>	139:856d2700e60b	409
<>	139:856d2700e60b	410	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<>	139:856d2700e60b	411
<>	139:856d2700e60b	412	uint32_t SequencersScanMode; /*!< Set ADC scan selection.
<>	139:856d2700e60b	413	This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
<>	139:856d2700e60b	414
<>	139:856d2700e60b	415	This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
<>	139:856d2700e60b	416
<>	139:856d2700e60b	417	} LL_ADC_InitTypeDef;
<>	139:856d2700e60b	418
<>	139:856d2700e60b	419	/**
<>	139:856d2700e60b	420	* @brief Structure definition of some features of ADC group regular.
<>	139:856d2700e60b	421	* @note These parameters have an impact on ADC scope: ADC group regular.
<>	139:856d2700e60b	422	* Refer to corresponding unitary functions into
<>	139:856d2700e60b	423	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	139:856d2700e60b	424	* (functions with prefix "REG").
<>	139:856d2700e60b	425	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<>	139:856d2700e60b	426	* is conditioned to ADC state:
<>	139:856d2700e60b	427	* ADC instance must be disabled.
<>	139:856d2700e60b	428	* This condition is applied to all ADC features, for efficiency
<>	139:856d2700e60b	429	* and compatibility over all STM32 families. However, the different
<>	139:856d2700e60b	430	* features can be set under different ADC state conditions
<>	139:856d2700e60b	431	* (setting possible with ADC enabled without conversion on going,
<>	139:856d2700e60b	432	* ADC enabled with conversion on going, ...)
<>	139:856d2700e60b	433	* Each feature can be updated afterwards with a unitary function
<>	139:856d2700e60b	434	* and potentially with ADC in a different state than disabled,
<>	139:856d2700e60b	435	* refer to description of each function for setting
<>	139:856d2700e60b	436	* conditioned to ADC state.
<>	139:856d2700e60b	437	*/
<>	139:856d2700e60b	438	typedef struct
<>	139:856d2700e60b	439	{
<>	139:856d2700e60b	440	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	139:856d2700e60b	441	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<>	139:856d2700e60b	442	@note On this STM32 serie, setting of external trigger edge is performed
<>	139:856d2700e60b	443	using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	139:856d2700e60b	444
<>	139:856d2700e60b	445	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<>	139:856d2700e60b	446
<>	139:856d2700e60b	447	uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
<>	139:856d2700e60b	448	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
<>	139:856d2700e60b	449	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	139:856d2700e60b	450
<>	139:856d2700e60b	451	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
<>	139:856d2700e60b	452
<>	139:856d2700e60b	453	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	139:856d2700e60b	454	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<>	139:856d2700e60b	455	@note This parameter has an effect only if group regular sequencer is enabled
<>	139:856d2700e60b	456	(scan length of 2 ranks or more).
<>	139:856d2700e60b	457
<>	139:856d2700e60b	458	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<>	139:856d2700e60b	459
<>	139:856d2700e60b	460	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<>	139:856d2700e60b	461	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<>	139:856d2700e60b	462	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<>	139:856d2700e60b	463
<>	139:856d2700e60b	464	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<>	139:856d2700e60b	465
<>	139:856d2700e60b	466	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<>	139:856d2700e60b	467	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<>	139:856d2700e60b	468
<>	139:856d2700e60b	469	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<>	139:856d2700e60b	470
<>	139:856d2700e60b	471	} LL_ADC_REG_InitTypeDef;
<>	139:856d2700e60b	472
<>	139:856d2700e60b	473	/**
<>	139:856d2700e60b	474	* @brief Structure definition of some features of ADC group injected.
<>	139:856d2700e60b	475	* @note These parameters have an impact on ADC scope: ADC group injected.
<>	139:856d2700e60b	476	* Refer to corresponding unitary functions into
<>	139:856d2700e60b	477	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	139:856d2700e60b	478	* (functions with prefix "INJ").
<>	139:856d2700e60b	479	* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
<>	139:856d2700e60b	480	* is conditioned to ADC state:
<>	139:856d2700e60b	481	* ADC instance must be disabled.
<>	139:856d2700e60b	482	* This condition is applied to all ADC features, for efficiency
<>	139:856d2700e60b	483	* and compatibility over all STM32 families. However, the different
<>	139:856d2700e60b	484	* features can be set under different ADC state conditions
<>	139:856d2700e60b	485	* (setting possible with ADC enabled without conversion on going,
<>	139:856d2700e60b	486	* ADC enabled with conversion on going, ...)
<>	139:856d2700e60b	487	* Each feature can be updated afterwards with a unitary function
<>	139:856d2700e60b	488	* and potentially with ADC in a different state than disabled,
<>	139:856d2700e60b	489	* refer to description of each function for setting
<>	139:856d2700e60b	490	* conditioned to ADC state.
<>	139:856d2700e60b	491	*/
<>	139:856d2700e60b	492	typedef struct
<>	139:856d2700e60b	493	{
<>	139:856d2700e60b	494	uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	139:856d2700e60b	495	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
<>	139:856d2700e60b	496	@note On this STM32 serie, setting of external trigger edge is performed
<>	139:856d2700e60b	497	using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	139:856d2700e60b	498
<>	139:856d2700e60b	499	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
<>	139:856d2700e60b	500
<>	139:856d2700e60b	501	uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
<>	139:856d2700e60b	502	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
<>	139:856d2700e60b	503	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	139:856d2700e60b	504
<>	139:856d2700e60b	505	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
<>	139:856d2700e60b	506
<>	139:856d2700e60b	507	uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	139:856d2700e60b	508	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
<>	139:856d2700e60b	509	@note This parameter has an effect only if group injected sequencer is enabled
<>	139:856d2700e60b	510	(scan length of 2 ranks or more).
<>	139:856d2700e60b	511
<>	139:856d2700e60b	512	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
<>	139:856d2700e60b	513
<>	139:856d2700e60b	514	uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
<>	139:856d2700e60b	515	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
<>	139:856d2700e60b	516	Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
<>	139:856d2700e60b	517
<>	139:856d2700e60b	518	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
<>	139:856d2700e60b	519
<>	139:856d2700e60b	520	} LL_ADC_INJ_InitTypeDef;
<>	139:856d2700e60b	521
<>	139:856d2700e60b	522	/**
<>	139:856d2700e60b	523	* @}
<>	139:856d2700e60b	524	*/
<>	139:856d2700e60b	525	#endif /* USE_FULL_LL_DRIVER */
<>	139:856d2700e60b	526
<>	139:856d2700e60b	527	/* Exported constants --------------------------------------------------------*/
<>	139:856d2700e60b	528	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<>	139:856d2700e60b	529	* @{
<>	139:856d2700e60b	530	*/
<>	139:856d2700e60b	531
<>	139:856d2700e60b	532	/** @defgroup ADC_LL_EC_FLAG ADC flags
<>	139:856d2700e60b	533	* @brief Flags defines which can be used with LL_ADC_ReadReg function
<>	139:856d2700e60b	534	* @{
<>	139:856d2700e60b	535	*/
<>	139:856d2700e60b	536	#define LL_ADC_FLAG_STRT ADC_SR_STRT /!< ADC flag ADC group regular conversion start /
<>	139:856d2700e60b	537	#define LL_ADC_FLAG_EOCS ADC_SR_EOC /!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	139:856d2700e60b	538	#define LL_ADC_FLAG_OVR ADC_SR_OVR /!< ADC flag ADC group regular overrun /
<>	139:856d2700e60b	539	#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC flag ADC group injected conversion start /
<>	139:856d2700e60b	540	#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	139:856d2700e60b	541	#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /!< ADC flag ADC analog watchdog 1 /
<>	139:856d2700e60b	542	#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	139:856d2700e60b	543	#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	139:856d2700e60b	544	#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	139:856d2700e60b	545	#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /!< ADC flag ADC multimode master group regular overrun /
<>	139:856d2700e60b	546	#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /!< ADC flag ADC multimode slave 1 group regular overrun /
<>	139:856d2700e60b	547	#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /!< ADC flag ADC multimode slave 2 group regular overrun /
<>	139:856d2700e60b	548	#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	139:856d2700e60b	549	#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	139:856d2700e60b	550	#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	139:856d2700e60b	551	#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /!< ADC flag ADC multimode master analog watchdog 1 of the ADC master /
<>	139:856d2700e60b	552	#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /!< ADC flag ADC multimode slave 1 analog watchdog 1 /
<>	139:856d2700e60b	553	#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /!< ADC flag ADC multimode slave 2 analog watchdog 1 /
<>	139:856d2700e60b	554	/**
<>	139:856d2700e60b	555	* @}
<>	139:856d2700e60b	556	*/
<>	139:856d2700e60b	557
<>	139:856d2700e60b	558	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<>	139:856d2700e60b	559	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<>	139:856d2700e60b	560	* @{
<>	139:856d2700e60b	561	*/
<>	139:856d2700e60b	562	#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	139:856d2700e60b	563	#define LL_ADC_IT_OVR ADC_CR1_OVRIE /!< ADC interruption ADC group regular overrun /
<>	139:856d2700e60b	564	#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	139:856d2700e60b	565	#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /!< ADC interruption ADC analog watchdog 1 /
<>	139:856d2700e60b	566	/**
<>	139:856d2700e60b	567	* @}
<>	139:856d2700e60b	568	*/
<>	139:856d2700e60b	569
<>	139:856d2700e60b	570	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<>	139:856d2700e60b	571	* @{
<>	139:856d2700e60b	572	*/
<>	139:856d2700e60b	573	/* List of ADC registers intended to be used (most commonly) with */
<>	139:856d2700e60b	574	/* DMA transfer. */
<>	139:856d2700e60b	575	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<>	139:856d2700e60b	576	#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<>	139:856d2700e60b	577	#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
<>	139:856d2700e60b	578	/**
<>	139:856d2700e60b	579	* @}
<>	139:856d2700e60b	580	*/
<>	139:856d2700e60b	581
<>	139:856d2700e60b	582	/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
<>	139:856d2700e60b	583	* @{
<>	139:856d2700e60b	584	*/
<>	139:856d2700e60b	585	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (0x00000000U) /!< ADC synchronous clock derived from AHB clock with prescaler division by 2 /
<>	139:856d2700e60b	586	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /!< ADC synchronous clock derived from AHB clock with prescaler division by 4 /
<>	139:856d2700e60b	587	#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /!< ADC synchronous clock derived from AHB clock with prescaler division by 6 /
<>	139:856d2700e60b	588	#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 \| ADC_CCR_ADCPRE_0) /!< ADC synchronous clock derived from AHB clock with prescaler division by 8 /
<>	139:856d2700e60b	589	/**
<>	139:856d2700e60b	590	* @}
<>	139:856d2700e60b	591	*/
<>	139:856d2700e60b	592
<>	139:856d2700e60b	593	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<>	139:856d2700e60b	594	* @{
<>	139:856d2700e60b	595	*/
<>	139:856d2700e60b	596	/* Note: Other measurement paths to internal channels may be available */
<>	139:856d2700e60b	597	/* (connections to other peripherals). */
<>	139:856d2700e60b	598	/* If they are not listed below, they do not require any specific */
<>	139:856d2700e60b	599	/* path enable. In this case, Access to measurement path is done */
<>	139:856d2700e60b	600	/* only by selecting the corresponding ADC internal channel. */
<>	139:856d2700e60b	601	#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/!< ADC measurement pathes all disabled /
<>	139:856d2700e60b	602	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel VrefInt /
<>	139:856d2700e60b	603	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel temperature sensor /
<>	139:856d2700e60b	604	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /!< ADC measurement path to internal channel Vbat /
<>	139:856d2700e60b	605	/**
<>	139:856d2700e60b	606	* @}
<>	139:856d2700e60b	607	*/
<>	139:856d2700e60b	608
<>	139:856d2700e60b	609	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<>	139:856d2700e60b	610	* @{
<>	139:856d2700e60b	611	*/
<>	139:856d2700e60b	612	#define LL_ADC_RESOLUTION_12B (0x00000000U) /!< ADC resolution 12 bits /
<>	139:856d2700e60b	613	#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /!< ADC resolution 10 bits /
<>	139:856d2700e60b	614	#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /!< ADC resolution 8 bits /
<>	139:856d2700e60b	615	#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 \| ADC_CR1_RES_0) /!< ADC resolution 6 bits /
<>	139:856d2700e60b	616	/**
<>	139:856d2700e60b	617	* @}
<>	139:856d2700e60b	618	*/
<>	139:856d2700e60b	619
<>	139:856d2700e60b	620	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<>	139:856d2700e60b	621	* @{
<>	139:856d2700e60b	622	*/
<>	139:856d2700e60b	623	#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
<>	139:856d2700e60b	624	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
<>	139:856d2700e60b	625	/**
<>	139:856d2700e60b	626	* @}
<>	139:856d2700e60b	627	*/
<>	139:856d2700e60b	628
<>	139:856d2700e60b	629	/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
<>	139:856d2700e60b	630	* @{
<>	139:856d2700e60b	631	*/
<>	139:856d2700e60b	632	#define LL_ADC_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank./
<>	139:856d2700e60b	633	#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). /
<>	139:856d2700e60b	634	/**
<>	139:856d2700e60b	635	* @}
<>	139:856d2700e60b	636	*/
<>	139:856d2700e60b	637
<>	139:856d2700e60b	638	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<>	139:856d2700e60b	639	* @{
<>	139:856d2700e60b	640	*/
<>	139:856d2700e60b	641	#define LL_ADC_GROUP_REGULAR (0x00000001U) /!< ADC group regular (available on all STM32 devices) /
<>	139:856d2700e60b	642	#define LL_ADC_GROUP_INJECTED (0x00000002U) /!< ADC group injected (not available on all STM32 devices)/
<>	139:856d2700e60b	643	#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /!< ADC both groups regular and injected /
<>	139:856d2700e60b	644	/**
<>	139:856d2700e60b	645	* @}
<>	139:856d2700e60b	646	*/
<>	139:856d2700e60b	647
<>	139:856d2700e60b	648	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<>	139:856d2700e60b	649	* @{
<>	139:856d2700e60b	650	*/
<>	139:856d2700e60b	651	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
<>	139:856d2700e60b	652	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
<>	139:856d2700e60b	653	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
<>	139:856d2700e60b	654	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
<>	139:856d2700e60b	655	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
<>	139:856d2700e60b	656	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
<>	139:856d2700e60b	657	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
<>	139:856d2700e60b	658	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
<>	139:856d2700e60b	659	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
<>	139:856d2700e60b	660	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
<>	139:856d2700e60b	661	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
<>	139:856d2700e60b	662	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
<>	139:856d2700e60b	663	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
<>	139:856d2700e60b	664	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
<>	139:856d2700e60b	665	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
<>	139:856d2700e60b	666	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
<>	139:856d2700e60b	667	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
<>	139:856d2700e60b	668	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
<>	139:856d2700e60b	669	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
<>	139:856d2700e60b	670	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	139:856d2700e60b	671	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	139:856d2700e60b	672	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	139:856d2700e60b	673
<>	139:856d2700e60b	674	/**
<>	139:856d2700e60b	675	* @}
<>	139:856d2700e60b	676	*/
<>	139:856d2700e60b	677
<>	139:856d2700e60b	678	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<>	139:856d2700e60b	679	* @{
<>	139:856d2700e60b	680	*/
<>	139:856d2700e60b	681	#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
<>	139:856d2700e60b	682	#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	683	#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	684	#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	685	#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	686	#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	687	#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	688	#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	689	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	690	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	691	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	692	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	693	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	694	#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	695	#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 \|ADC_CR2_EXTSEL_2\| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	696	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	697
<>	139:856d2700e60b	698	/**
<>	139:856d2700e60b	699	* @}
<>	139:856d2700e60b	700	*/
<>	139:856d2700e60b	701
<>	139:856d2700e60b	702	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<>	139:856d2700e60b	703	* @{
<>	139:856d2700e60b	704	*/
<>	139:856d2700e60b	705	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
<>	139:856d2700e60b	706	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
<>	139:856d2700e60b	707	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 \| ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
<>	139:856d2700e60b	708	/**
<>	139:856d2700e60b	709	* @}
<>	139:856d2700e60b	710	*/
<>	139:856d2700e60b	711
<>	139:856d2700e60b	712	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<>	139:856d2700e60b	713	* @{
<>	139:856d2700e60b	714	*/
<>	139:856d2700e60b	715	#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
<>	139:856d2700e60b	716	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
<>	139:856d2700e60b	717	/**
<>	139:856d2700e60b	718	* @}
<>	139:856d2700e60b	719	*/
<>	139:856d2700e60b	720
<>	139:856d2700e60b	721	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<>	139:856d2700e60b	722	* @{
<>	139:856d2700e60b	723	*/
<>	139:856d2700e60b	724	#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /!< ADC conversions are not transferred by DMA /
<>	139:856d2700e60b	725	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
<>	139:856d2700e60b	726	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS \| ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
<>	139:856d2700e60b	727	/**
<>	139:856d2700e60b	728	* @}
<>	139:856d2700e60b	729	*/
<>	139:856d2700e60b	730
<>	139:856d2700e60b	731	/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
<>	139:856d2700e60b	732	* @{
<>	139:856d2700e60b	733	*/
<>	139:856d2700e60b	734	#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV (0x00000000U) /!< ADC flag EOC (end of unitary conversion) selected /
<>	139:856d2700e60b	735	#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /!< ADC flag EOS (end of sequence conversions) selected /
<>	139:856d2700e60b	736	/**
<>	139:856d2700e60b	737	* @}
<>	139:856d2700e60b	738	*/
<>	139:856d2700e60b	739
<>	139:856d2700e60b	740	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
<>	139:856d2700e60b	741	* @{
<>	139:856d2700e60b	742	*/
<>	139:856d2700e60b	743	#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	139:856d2700e60b	744	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
<>	139:856d2700e60b	745	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
<>	139:856d2700e60b	746	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
<>	139:856d2700e60b	747	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
<>	139:856d2700e60b	748	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
<>	139:856d2700e60b	749	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
<>	139:856d2700e60b	750	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
<>	139:856d2700e60b	751	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
<>	139:856d2700e60b	752	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
<>	139:856d2700e60b	753	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
<>	139:856d2700e60b	754	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
<>	139:856d2700e60b	755	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
<>	139:856d2700e60b	756	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
<>	139:856d2700e60b	757	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
<>	139:856d2700e60b	758	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
<>	139:856d2700e60b	759	/**
<>	139:856d2700e60b	760	* @}
<>	139:856d2700e60b	761	*/
<>	139:856d2700e60b	762
<>	139:856d2700e60b	763	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<>	139:856d2700e60b	764	* @{
<>	139:856d2700e60b	765	*/
<>	139:856d2700e60b	766	#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
<>	139:856d2700e60b	767	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
<>	139:856d2700e60b	768	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
<>	139:856d2700e60b	769	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
<>	139:856d2700e60b	770	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
<>	139:856d2700e60b	771	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
<>	139:856d2700e60b	772	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
<>	139:856d2700e60b	773	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
<>	139:856d2700e60b	774	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
<>	139:856d2700e60b	775	/**
<>	139:856d2700e60b	776	* @}
<>	139:856d2700e60b	777	*/
<>	139:856d2700e60b	778
<>	139:856d2700e60b	779	/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
<>	139:856d2700e60b	780	* @{
<>	139:856d2700e60b	781	*/
<>	139:856d2700e60b	782	#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
<>	139:856d2700e60b	783	#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
<>	139:856d2700e60b	784	#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
<>	139:856d2700e60b	785	#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
<>	139:856d2700e60b	786	#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
<>	139:856d2700e60b	787	#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
<>	139:856d2700e60b	788	#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
<>	139:856d2700e60b	789	#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
<>	139:856d2700e60b	790	#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
<>	139:856d2700e60b	791	#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
<>	139:856d2700e60b	792	#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
<>	139:856d2700e60b	793	#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
<>	139:856d2700e60b	794	#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
<>	139:856d2700e60b	795	#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
<>	139:856d2700e60b	796	#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
<>	139:856d2700e60b	797	#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
<>	139:856d2700e60b	798	/**
<>	139:856d2700e60b	799	* @}
<>	139:856d2700e60b	800	*/
<>	139:856d2700e60b	801
<>	139:856d2700e60b	802	/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
<>	139:856d2700e60b	803	* @{
<>	139:856d2700e60b	804	*/
<>	139:856d2700e60b	805	#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /!< ADC group injected conversion trigger internal: SW start. /
<>	139:856d2700e60b	806	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	807	#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	808	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	809	#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	810	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	811	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	812	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	813	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	814	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	815	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	816	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	817	#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	818	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	819	#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	139:856d2700e60b	820
<>	139:856d2700e60b	821	/**
<>	139:856d2700e60b	822	* @}
<>	139:856d2700e60b	823	*/
<>	139:856d2700e60b	824
<>	139:856d2700e60b	825	/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
<>	139:856d2700e60b	826	* @{
<>	139:856d2700e60b	827	*/
<>	139:856d2700e60b	828	#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to rising edge /
<>	139:856d2700e60b	829	#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /!< ADC group injected conversion trigger polarity set to falling edge /
<>	139:856d2700e60b	830	#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 \| ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to both rising and falling edges /
<>	139:856d2700e60b	831	/**
<>	139:856d2700e60b	832	* @}
<>	139:856d2700e60b	833	*/
<>	139:856d2700e60b	834
<>	139:856d2700e60b	835	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
<>	139:856d2700e60b	836	* @{
<>	139:856d2700e60b	837	*/
<>	139:856d2700e60b	838	#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)/!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. /
<>	139:856d2700e60b	839	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. /
<>	139:856d2700e60b	840	/**
<>	139:856d2700e60b	841	* @}
<>	139:856d2700e60b	842	*/
<>	139:856d2700e60b	843
<>	139:856d2700e60b	844
<>	139:856d2700e60b	845	/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
<>	139:856d2700e60b	846	* @{
<>	139:856d2700e60b	847	*/
<>	139:856d2700e60b	848	#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	139:856d2700e60b	849	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
<>	139:856d2700e60b	850	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
<>	139:856d2700e60b	851	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
<>	139:856d2700e60b	852	/**
<>	139:856d2700e60b	853	* @}
<>	139:856d2700e60b	854	*/
<>	139:856d2700e60b	855
<>	139:856d2700e60b	856	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
<>	139:856d2700e60b	857	* @{
<>	139:856d2700e60b	858	*/
<>	139:856d2700e60b	859	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)/!< ADC group injected sequencer discontinuous mode disable /
<>	139:856d2700e60b	860	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
<>	139:856d2700e60b	861	/**
<>	139:856d2700e60b	862	* @}
<>	139:856d2700e60b	863	*/
<>	139:856d2700e60b	864
<>	139:856d2700e60b	865	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
<>	139:856d2700e60b	866	* @{
<>	139:856d2700e60b	867	*/
<>	139:856d2700e60b	868	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_JOFR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 1 /
<>	139:856d2700e60b	869	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 2 /
<>	139:856d2700e60b	870	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 3 /
<>	139:856d2700e60b	871	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_JOFR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 4 /
<>	139:856d2700e60b	872	/**
<>	139:856d2700e60b	873	* @}
<>	139:856d2700e60b	874	*/
<>	139:856d2700e60b	875
<>	139:856d2700e60b	876	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<>	139:856d2700e60b	877	* @{
<>	139:856d2700e60b	878	*/
<>	139:856d2700e60b	879	#define LL_ADC_SAMPLINGTIME_3CYCLES (0x00000000U) /!< Sampling time 3 ADC clock cycles /
<>	139:856d2700e60b	880	#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /!< Sampling time 15 ADC clock cycles /
<>	139:856d2700e60b	881	#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /!< Sampling time 28 ADC clock cycles /
<>	139:856d2700e60b	882	#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0) /!< Sampling time 56 ADC clock cycles /
<>	139:856d2700e60b	883	#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /!< Sampling time 84 ADC clock cycles /
<>	139:856d2700e60b	884	#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0) /!< Sampling time 112 ADC clock cycles /
<>	139:856d2700e60b	885	#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1) /!< Sampling time 144 ADC clock cycles /
<>	139:856d2700e60b	886	#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /!< Sampling time 480 ADC clock cycles /
<>	139:856d2700e60b	887	/**
<>	139:856d2700e60b	888	* @}
<>	139:856d2700e60b	889	*/
<>	139:856d2700e60b	890
<>	139:856d2700e60b	891	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<>	139:856d2700e60b	892	* @{
<>	139:856d2700e60b	893	*/
<>	139:856d2700e60b	894	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
<>	139:856d2700e60b	895	/**
<>	139:856d2700e60b	896	* @}
<>	139:856d2700e60b	897	*/
<>	139:856d2700e60b	898
<>	139:856d2700e60b	899	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<>	139:856d2700e60b	900	* @{
<>	139:856d2700e60b	901	*/
<>	139:856d2700e60b	902	#define LL_ADC_AWD_DISABLE (0x00000000U) /!< ADC analog watchdog monitoring disabled /
<>	139:856d2700e60b	903	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
<>	139:856d2700e60b	904	#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
<>	139:856d2700e60b	905	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN \| ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
<>	139:856d2700e60b	906	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
<>	139:856d2700e60b	907	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
<>	139:856d2700e60b	908	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
<>	139:856d2700e60b	909	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
<>	139:856d2700e60b	910	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
<>	139:856d2700e60b	911	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
<>	139:856d2700e60b	912	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
<>	139:856d2700e60b	913	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
<>	139:856d2700e60b	914	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
<>	139:856d2700e60b	915	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
<>	139:856d2700e60b	916	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
<>	139:856d2700e60b	917	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
<>	139:856d2700e60b	918	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
<>	139:856d2700e60b	919	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
<>	139:856d2700e60b	920	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
<>	139:856d2700e60b	921	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
<>	139:856d2700e60b	922	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
<>	139:856d2700e60b	923	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
<>	139:856d2700e60b	924	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
<>	139:856d2700e60b	925	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
<>	139:856d2700e60b	926	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
<>	139:856d2700e60b	927	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
<>	139:856d2700e60b	928	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
<>	139:856d2700e60b	929	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
<>	139:856d2700e60b	930	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
<>	139:856d2700e60b	931	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
<>	139:856d2700e60b	932	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
<>	139:856d2700e60b	933	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
<>	139:856d2700e60b	934	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
<>	139:856d2700e60b	935	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
<>	139:856d2700e60b	936	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
<>	139:856d2700e60b	937	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
<>	139:856d2700e60b	938	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
<>	139:856d2700e60b	939	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
<>	139:856d2700e60b	940	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
<>	139:856d2700e60b	941	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
<>	139:856d2700e60b	942	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
<>	139:856d2700e60b	943	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
<>	139:856d2700e60b	944	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
<>	139:856d2700e60b	945	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
<>	139:856d2700e60b	946	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
<>	139:856d2700e60b	947	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
<>	139:856d2700e60b	948	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
<>	139:856d2700e60b	949	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
<>	139:856d2700e60b	950	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
<>	139:856d2700e60b	951	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
<>	139:856d2700e60b	952	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
<>	139:856d2700e60b	953	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
<>	139:856d2700e60b	954	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
<>	139:856d2700e60b	955	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
<>	139:856d2700e60b	956	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
<>	139:856d2700e60b	957	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
<>	139:856d2700e60b	958	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
<>	139:856d2700e60b	959	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
<>	139:856d2700e60b	960	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
<>	139:856d2700e60b	961	#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only /
<>	139:856d2700e60b	962	#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected /
<>	139:856d2700e60b	963	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
<>	139:856d2700e60b	964	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only /
<>	139:856d2700e60b	965	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected /
<>	139:856d2700e60b	966	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
<>	139:856d2700e60b	967	#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only /
<>	139:856d2700e60b	968	#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda /
<>	139:856d2700e60b	969	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	139:856d2700e60b	970	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	139:856d2700e60b	971	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	139:856d2700e60b	972	/**
<>	139:856d2700e60b	973	* @}
<>	139:856d2700e60b	974	*/
<>	139:856d2700e60b	975
<>	139:856d2700e60b	976	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<>	139:856d2700e60b	977	* @{
<>	139:856d2700e60b	978	*/
<>	139:856d2700e60b	979	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /!< ADC analog watchdog threshold high /
<>	139:856d2700e60b	980	#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /!< ADC analog watchdog threshold low /
<>	139:856d2700e60b	981	/**
<>	139:856d2700e60b	982	* @}
<>	139:856d2700e60b	983	*/
<>	139:856d2700e60b	984
<>	139:856d2700e60b	985	/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
<>	139:856d2700e60b	986	* @{
<>	139:856d2700e60b	987	*/
<>	139:856d2700e60b	988	#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /!< ADC dual mode disabled (ADC independent mode) /
<>	139:856d2700e60b	989	#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 ) /!< ADC dual mode enabled: group regular simultaneous /
<>	139:856d2700e60b	990	#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular interleaved /
<>	139:856d2700e60b	991	#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: group injected simultaneous /
<>	139:856d2700e60b	992	#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
<>	139:856d2700e60b	993	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
<>	139:856d2700e60b	994	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
<>	139:856d2700e60b	995	#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous /
<>	139:856d2700e60b	996	#if defined(ADC3)
<>	139:856d2700e60b	997	#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous /
<>	139:856d2700e60b	998	#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_1 ) /!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger /
<>	139:856d2700e60b	999	#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: group injected simultaneous /
<>	139:856d2700e60b	1000	#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 ) /!< ADC triple mode enabled: group regular simultaneous /
<>	139:856d2700e60b	1001	#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: Combined group regular interleaved /
<>	139:856d2700e60b	1002	#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
<>	139:856d2700e60b	1003	#endif
<>	139:856d2700e60b	1004	/**
<>	139:856d2700e60b	1005	* @}
<>	139:856d2700e60b	1006	*/
<>	139:856d2700e60b	1007
<>	139:856d2700e60b	1008	/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
<>	139:856d2700e60b	1009	* @{
<>	139:856d2700e60b	1010	*/
<>	139:856d2700e60b	1011	#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings /
<>	139:856d2700e60b	1012	#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. /
<>	139:856d2700e60b	1013	#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	139:856d2700e60b	1014	#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	139:856d2700e60b	1015	#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. /
<>	139:856d2700e60b	1016	#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS \| ADC_CCR_DMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. /
<>	139:856d2700e60b	1017	#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS \| ADC_CCR_DMA_0 \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	139:856d2700e60b	1018	/**
<>	139:856d2700e60b	1019	* @}
<>	139:856d2700e60b	1020	*/
<>	139:856d2700e60b	1021
<>	139:856d2700e60b	1022	/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
<>	139:856d2700e60b	1023	* @{
<>	139:856d2700e60b	1024	*/
<>	139:856d2700e60b	1025	#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (0x00000000U) /!< ADC multimode delay between two sampling phases: 5 ADC clock cycles/
<>	139:856d2700e60b	1026	#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 6 ADC clock cycles /
<>	139:856d2700e60b	1027	#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 7 ADC clock cycles /
<>	139:856d2700e60b	1028	#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 8 ADC clock cycles /
<>	139:856d2700e60b	1029	#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 9 ADC clock cycles /
<>	139:856d2700e60b	1030	#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 10 ADC clock cycles /
<>	139:856d2700e60b	1031	#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 11 ADC clock cycles /
<>	139:856d2700e60b	1032	#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 12 ADC clock cycles /
<>	139:856d2700e60b	1033	#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /!< ADC multimode delay between two sampling phases: 13 ADC clock cycles /
<>	139:856d2700e60b	1034	#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 14 ADC clock cycles /
<>	139:856d2700e60b	1035	#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 15 ADC clock cycles /
<>	139:856d2700e60b	1036	#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 16 ADC clock cycles /
<>	139:856d2700e60b	1037	#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 17 ADC clock cycles /
<>	139:856d2700e60b	1038	#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 18 ADC clock cycles /
<>	139:856d2700e60b	1039	#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 19 ADC clock cycles /
<>	139:856d2700e60b	1040	#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 20 ADC clock cycles /
<>	139:856d2700e60b	1041	/**
<>	139:856d2700e60b	1042	* @}
<>	139:856d2700e60b	1043	*/
<>	139:856d2700e60b	1044
<>	139:856d2700e60b	1045	/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
<>	139:856d2700e60b	1046	* @{
<>	139:856d2700e60b	1047	*/
<>	139:856d2700e60b	1048	#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: ADC master /
<>	139:856d2700e60b	1049	#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /!< In multimode, selection among several ADC instances: ADC slave /
<>	139:856d2700e60b	1050	#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: both ADC master and ADC slave /
<>	139:856d2700e60b	1051	/**
<>	139:856d2700e60b	1052	* @}
<>	139:856d2700e60b	1053	*/
<>	139:856d2700e60b	1054
<>	139:856d2700e60b	1055
<>	139:856d2700e60b	1056
<>	139:856d2700e60b	1057	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<>	139:856d2700e60b	1058	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
<>	139:856d2700e60b	1059	* not timeout values.
<>	139:856d2700e60b	1060	* For details on delays values, refer to descriptions in source code
<>	139:856d2700e60b	1061	* above each literal definition.
<>	139:856d2700e60b	1062	* @{
<>	139:856d2700e60b	1063	*/
<>	139:856d2700e60b	1064
<>	139:856d2700e60b	1065	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<>	139:856d2700e60b	1066	/* not timeout values. */
<>	139:856d2700e60b	1067	/* Timeout values for ADC operations are dependent to device clock */
<>	139:856d2700e60b	1068	/* configuration (system clock versus ADC clock), */
<>	139:856d2700e60b	1069	/* and therefore must be defined in user application. */
<>	139:856d2700e60b	1070	/* Indications for estimation of ADC timeout delays, for this */
<>	139:856d2700e60b	1071	/* STM32 serie: */
<>	139:856d2700e60b	1072	/* - ADC enable time: maximum delay is 2us */
<>	139:856d2700e60b	1073	/* (refer to device datasheet, parameter "tSTAB") */
<>	139:856d2700e60b	1074	/* - ADC conversion time: duration depending on ADC clock and ADC */
<>	139:856d2700e60b	1075	/* configuration. */
<>	139:856d2700e60b	1076	/* (refer to device reference manual, section "Timing") */
<>	139:856d2700e60b	1077
<>	139:856d2700e60b	1078	/* Delay for internal voltage reference stabilization time. */
<>	139:856d2700e60b	1079	/* Delay set to maximum value (refer to device datasheet, */
<>	139:856d2700e60b	1080	/* parameter "tSTART"). */
<>	139:856d2700e60b	1081	/* Unit: us */
<>	139:856d2700e60b	1082	#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
<>	139:856d2700e60b	1083
<>	139:856d2700e60b	1084	/* Delay for temperature sensor stabilization time. */
<>	139:856d2700e60b	1085	/* Literal set to maximum value (refer to device datasheet, */
<>	139:856d2700e60b	1086	/* parameter "tSTART"). */
<>	139:856d2700e60b	1087	/* Unit: us */
<>	139:856d2700e60b	1088	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
<>	139:856d2700e60b	1089
<>	139:856d2700e60b	1090	/**
<>	139:856d2700e60b	1091	* @}
<>	139:856d2700e60b	1092	*/
<>	139:856d2700e60b	1093
<>	139:856d2700e60b	1094	/**
<>	139:856d2700e60b	1095	* @}
<>	139:856d2700e60b	1096	*/
<>	139:856d2700e60b	1097
<>	139:856d2700e60b	1098
<>	139:856d2700e60b	1099	/* Exported macro ------------------------------------------------------------*/
<>	139:856d2700e60b	1100	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<>	139:856d2700e60b	1101	* @{
<>	139:856d2700e60b	1102	*/
<>	139:856d2700e60b	1103
<>	139:856d2700e60b	1104	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<>	139:856d2700e60b	1105	* @{
<>	139:856d2700e60b	1106	*/
<>	139:856d2700e60b	1107
<>	139:856d2700e60b	1108	/**
<>	139:856d2700e60b	1109	* @brief Write a value in ADC register
<>	139:856d2700e60b	1110	* @param __INSTANCE__ ADC Instance
<>	139:856d2700e60b	1111	* @param __REG__ Register to be written
<>	139:856d2700e60b	1112	* @param __VALUE__ Value to be written in the register
<>	139:856d2700e60b	1113	* @retval None
<>	139:856d2700e60b	1114	*/
<>	139:856d2700e60b	1115	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	139:856d2700e60b	1116
<>	139:856d2700e60b	1117	/**
<>	139:856d2700e60b	1118	* @brief Read a value in ADC register
<>	139:856d2700e60b	1119	* @param __INSTANCE__ ADC Instance
<>	139:856d2700e60b	1120	* @param __REG__ Register to be read
<>	139:856d2700e60b	1121	* @retval Register value
<>	139:856d2700e60b	1122	*/
<>	139:856d2700e60b	1123	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	139:856d2700e60b	1124	/**
<>	139:856d2700e60b	1125	* @}
<>	139:856d2700e60b	1126	*/
<>	139:856d2700e60b	1127
<>	139:856d2700e60b	1128	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<>	139:856d2700e60b	1129	* @{
<>	139:856d2700e60b	1130	*/
<>	139:856d2700e60b	1131
<>	139:856d2700e60b	1132	/**
<>	139:856d2700e60b	1133	* @brief Helper macro to get ADC channel number in decimal format
<>	139:856d2700e60b	1134	* from literals LL_ADC_CHANNEL_x.
<>	139:856d2700e60b	1135	* @note Example:
<>	139:856d2700e60b	1136	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<>	139:856d2700e60b	1137	* will return decimal number "4".
<>	139:856d2700e60b	1138	* @note The input can be a value from functions where a channel
<>	139:856d2700e60b	1139	* number is returned, either defined with number
<>	139:856d2700e60b	1140	* or with bitfield (only one bit must be set).
<>	139:856d2700e60b	1141	* @param __CHANNEL__ This parameter can be one of the following values:
<>	139:856d2700e60b	1142	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1143	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1144	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1145	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1146	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1147	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1148	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1149	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1150	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1151	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1152	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1153	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1154	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1155	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1156	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1157	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1158	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1159	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1160	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1161	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1162	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1163	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1164	*
<>	139:856d2700e60b	1165	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1166	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	1167	* @retval Value between Min_Data=0 and Max_Data=18
<>	139:856d2700e60b	1168	*/
<>	139:856d2700e60b	1169	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	139:856d2700e60b	1170	(((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<>	139:856d2700e60b	1171
<>	139:856d2700e60b	1172	/**
<>	139:856d2700e60b	1173	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<>	139:856d2700e60b	1174	* from number in decimal format.
<>	139:856d2700e60b	1175	* @note Example:
<>	139:856d2700e60b	1176	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<>	139:856d2700e60b	1177	* will return a data equivalent to "LL_ADC_CHANNEL_4".
AnnaBridge	163:e59c8e839560	1178	* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
<>	139:856d2700e60b	1179	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	1180	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1181	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1182	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1183	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1184	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1185	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1186	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1187	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1188	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1189	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1190	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1191	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1192	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1193	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1194	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1195	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1196	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1197	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1198	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1199	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1200	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1201	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1202	*
<>	139:856d2700e60b	1203	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1204	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	139:856d2700e60b	1205	* (1) For ADC channel read back from ADC register,
<>	139:856d2700e60b	1206	* comparison with internal channel parameter to be done
<>	139:856d2700e60b	1207	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	139:856d2700e60b	1208	*/
<>	139:856d2700e60b	1209	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	139:856d2700e60b	1210	(((__DECIMAL_NB__) <= 9U) \
<>	139:856d2700e60b	1211	? ( \
<>	139:856d2700e60b	1212	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	139:856d2700e60b	1213	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	139:856d2700e60b	1214	) \
<>	139:856d2700e60b	1215	: \
<>	139:856d2700e60b	1216	( \
<>	139:856d2700e60b	1217	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	139:856d2700e60b	1218	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	139:856d2700e60b	1219	) \
<>	139:856d2700e60b	1220	)
<>	139:856d2700e60b	1221
<>	139:856d2700e60b	1222	/**
<>	139:856d2700e60b	1223	* @brief Helper macro to determine whether the selected channel
<>	139:856d2700e60b	1224	* corresponds to literal definitions of driver.
<>	139:856d2700e60b	1225	* @note The different literal definitions of ADC channels are:
<>	139:856d2700e60b	1226	* - ADC internal channel:
<>	139:856d2700e60b	1227	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<>	139:856d2700e60b	1228	* - ADC external channel (channel connected to a GPIO pin):
<>	139:856d2700e60b	1229	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<>	139:856d2700e60b	1230	* @note The channel parameter must be a value defined from literal
<>	139:856d2700e60b	1231	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	139:856d2700e60b	1232	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	139:856d2700e60b	1233	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<>	139:856d2700e60b	1234	* must not be a value from functions where a channel number is
<>	139:856d2700e60b	1235	* returned from ADC registers,
<>	139:856d2700e60b	1236	* because internal and external channels share the same channel
<>	139:856d2700e60b	1237	* number in ADC registers. The differentiation is made only with
<>	139:856d2700e60b	1238	* parameters definitions of driver.
<>	139:856d2700e60b	1239	* @param __CHANNEL__ This parameter can be one of the following values:
<>	139:856d2700e60b	1240	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1241	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1242	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1243	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1244	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1245	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1246	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1247	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1248	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1249	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1250	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1251	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1252	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1253	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1254	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1255	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1256	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1257	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1258	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1259	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1260	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1261	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1262	*
<>	139:856d2700e60b	1263	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1264	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	1265	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<>	139:856d2700e60b	1266	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<>	139:856d2700e60b	1267	*/
<>	139:856d2700e60b	1268	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<>	139:856d2700e60b	1269	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<>	139:856d2700e60b	1270
<>	139:856d2700e60b	1271	/**
<>	139:856d2700e60b	1272	* @brief Helper macro to convert a channel defined from parameter
<>	139:856d2700e60b	1273	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	139:856d2700e60b	1274	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	139:856d2700e60b	1275	* to its equivalent parameter definition of a ADC external channel
<>	139:856d2700e60b	1276	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<>	139:856d2700e60b	1277	* @note The channel parameter can be, additionally to a value
<>	139:856d2700e60b	1278	* defined from parameter definition of a ADC internal channel
<>	139:856d2700e60b	1279	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	139:856d2700e60b	1280	* a value defined from parameter definition of
<>	139:856d2700e60b	1281	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	139:856d2700e60b	1282	* or a value from functions where a channel number is returned
<>	139:856d2700e60b	1283	* from ADC registers.
<>	139:856d2700e60b	1284	* @param __CHANNEL__ This parameter can be one of the following values:
<>	139:856d2700e60b	1285	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1286	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1287	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1288	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1289	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1290	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1291	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1292	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1293	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1294	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1295	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1296	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1297	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1298	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1299	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1300	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1301	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1302	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1303	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1304	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1305	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1306	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1307	*
<>	139:856d2700e60b	1308	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1309	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	1310	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	1311	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1312	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1313	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1314	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1315	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1316	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1317	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1318	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1319	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1320	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1321	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1322	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1323	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1324	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1325	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1326	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1327	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1328	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1329	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1330	*/
<>	139:856d2700e60b	1331	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<>	139:856d2700e60b	1332	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	139:856d2700e60b	1333
<>	139:856d2700e60b	1334	/**
<>	139:856d2700e60b	1335	* @brief Helper macro to determine whether the internal channel
<>	139:856d2700e60b	1336	* selected is available on the ADC instance selected.
<>	139:856d2700e60b	1337	* @note The channel parameter must be a value defined from parameter
<>	139:856d2700e60b	1338	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	139:856d2700e60b	1339	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	139:856d2700e60b	1340	* must not be a value defined from parameter definition of
<>	139:856d2700e60b	1341	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	139:856d2700e60b	1342	* or a value from functions where a channel number is
<>	139:856d2700e60b	1343	* returned from ADC registers,
<>	139:856d2700e60b	1344	* because internal and external channels share the same channel
<>	139:856d2700e60b	1345	* number in ADC registers. The differentiation is made only with
<>	139:856d2700e60b	1346	* parameters definitions of driver.
<>	139:856d2700e60b	1347	* @param __ADC_INSTANCE__ ADC instance
<>	139:856d2700e60b	1348	* @param __CHANNEL__ This parameter can be one of the following values:
<>	139:856d2700e60b	1349	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1350	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1351	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1352	*
<>	139:856d2700e60b	1353	* (1) On STM32F7, parameter available only on ADC instance: ADC1.
<>	139:856d2700e60b	1354	* (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	1355	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<>	139:856d2700e60b	1356	* Value "1" if the internal channel selected is available on the ADC instance selected.
<>	139:856d2700e60b	1357	*/
<>	139:856d2700e60b	1358	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	139:856d2700e60b	1359	( \
<>	139:856d2700e60b	1360	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	139:856d2700e60b	1361	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<>	139:856d2700e60b	1362	)
<>	139:856d2700e60b	1363	/**
<>	139:856d2700e60b	1364	* @brief Helper macro to define ADC analog watchdog parameter:
<>	139:856d2700e60b	1365	* define a single channel to monitor with analog watchdog
<>	139:856d2700e60b	1366	* from sequencer channel and groups definition.
<>	139:856d2700e60b	1367	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<>	139:856d2700e60b	1368	* Example:
<>	139:856d2700e60b	1369	* LL_ADC_SetAnalogWDMonitChannels(
<>	139:856d2700e60b	1370	* ADC1, LL_ADC_AWD1,
<>	139:856d2700e60b	1371	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<>	139:856d2700e60b	1372	* @param __CHANNEL__ This parameter can be one of the following values:
<>	139:856d2700e60b	1373	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	1374	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	1375	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	1376	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	1377	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	1378	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	1379	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	1380	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	1381	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	1382	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	1383	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	1384	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	1385	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	1386	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	1387	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	1388	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	1389	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	1390	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	1391	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	1392	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	1393	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	1394	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	1395	*
<>	139:856d2700e60b	1396	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1397	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	139:856d2700e60b	1398	* (1) For ADC channel read back from ADC register,
<>	139:856d2700e60b	1399	* comparison with internal channel parameter to be done
<>	139:856d2700e60b	1400	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	139:856d2700e60b	1401	* @param __GROUP__ This parameter can be one of the following values:
<>	139:856d2700e60b	1402	* @arg @ref LL_ADC_GROUP_REGULAR
<>	139:856d2700e60b	1403	* @arg @ref LL_ADC_GROUP_INJECTED
<>	139:856d2700e60b	1404	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
<>	139:856d2700e60b	1405	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	1406	* @arg @ref LL_ADC_AWD_DISABLE
<>	139:856d2700e60b	1407	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	139:856d2700e60b	1408	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	139:856d2700e60b	1409	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	139:856d2700e60b	1410	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	139:856d2700e60b	1411	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	139:856d2700e60b	1412	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	139:856d2700e60b	1413	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	139:856d2700e60b	1414	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	139:856d2700e60b	1415	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	139:856d2700e60b	1416	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	139:856d2700e60b	1417	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	139:856d2700e60b	1418	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	139:856d2700e60b	1419	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	139:856d2700e60b	1420	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	139:856d2700e60b	1421	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	139:856d2700e60b	1422	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	139:856d2700e60b	1423	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	139:856d2700e60b	1424	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	139:856d2700e60b	1425	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	139:856d2700e60b	1426	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	139:856d2700e60b	1427	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	139:856d2700e60b	1428	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	139:856d2700e60b	1429	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	139:856d2700e60b	1430	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	139:856d2700e60b	1431	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	139:856d2700e60b	1432	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	139:856d2700e60b	1433	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	139:856d2700e60b	1434	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	139:856d2700e60b	1435	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	139:856d2700e60b	1436	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	139:856d2700e60b	1437	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	139:856d2700e60b	1438	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	139:856d2700e60b	1439	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	139:856d2700e60b	1440	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	139:856d2700e60b	1441	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	139:856d2700e60b	1442	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	139:856d2700e60b	1443	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	139:856d2700e60b	1444	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	139:856d2700e60b	1445	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	139:856d2700e60b	1446	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	139:856d2700e60b	1447	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	139:856d2700e60b	1448	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	139:856d2700e60b	1449	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	139:856d2700e60b	1450	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	139:856d2700e60b	1451	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	139:856d2700e60b	1452	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	139:856d2700e60b	1453	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	139:856d2700e60b	1454	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	139:856d2700e60b	1455	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	139:856d2700e60b	1456	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	139:856d2700e60b	1457	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	139:856d2700e60b	1458	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	139:856d2700e60b	1459	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	139:856d2700e60b	1460	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	139:856d2700e60b	1461	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	139:856d2700e60b	1462	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	139:856d2700e60b	1463	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	139:856d2700e60b	1464	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	139:856d2700e60b	1465	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	139:856d2700e60b	1466	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	139:856d2700e60b	1467	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
<>	139:856d2700e60b	1468	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
<>	139:856d2700e60b	1469	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	139:856d2700e60b	1470	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
<>	139:856d2700e60b	1471	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
<>	139:856d2700e60b	1472	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
<>	139:856d2700e60b	1473	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	139:856d2700e60b	1474	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
<>	139:856d2700e60b	1475	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
<>	139:856d2700e60b	1476	*
<>	139:856d2700e60b	1477	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	1478	* (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	1479	*/
<>	139:856d2700e60b	1480	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<>	139:856d2700e60b	1481	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
<>	139:856d2700e60b	1482	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	139:856d2700e60b	1483	: \
<>	139:856d2700e60b	1484	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
<>	139:856d2700e60b	1485	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) \
<>	139:856d2700e60b	1486	: \
<>	139:856d2700e60b	1487	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	139:856d2700e60b	1488	)
<>	139:856d2700e60b	1489
<>	139:856d2700e60b	1490	/**
<>	139:856d2700e60b	1491	* @brief Helper macro to set the value of ADC analog watchdog threshold high
<>	139:856d2700e60b	1492	* or low in function of ADC resolution, when ADC resolution is
<>	139:856d2700e60b	1493	* different of 12 bits.
<>	139:856d2700e60b	1494	* @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
<>	139:856d2700e60b	1495	* Example, with a ADC resolution of 8 bits, to set the value of
<>	139:856d2700e60b	1496	* analog watchdog threshold high (on 8 bits):
<>	139:856d2700e60b	1497	* LL_ADC_SetAnalogWDThresholds
<>	139:856d2700e60b	1498	* (< ADCx param >,
<>	139:856d2700e60b	1499	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<>	139:856d2700e60b	1500	* );
<>	139:856d2700e60b	1501	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	139:856d2700e60b	1502	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1503	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1504	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1505	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1506	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1507	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1508	*/
<>	139:856d2700e60b	1509	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<>	139:856d2700e60b	1510	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	139:856d2700e60b	1511
<>	139:856d2700e60b	1512	/**
<>	139:856d2700e60b	1513	* @brief Helper macro to get the value of ADC analog watchdog threshold high
<>	139:856d2700e60b	1514	* or low in function of ADC resolution, when ADC resolution is
<>	139:856d2700e60b	1515	* different of 12 bits.
<>	139:856d2700e60b	1516	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	139:856d2700e60b	1517	* Example, with a ADC resolution of 8 bits, to get the value of
<>	139:856d2700e60b	1518	* analog watchdog threshold high (on 8 bits):
<>	139:856d2700e60b	1519	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<>	139:856d2700e60b	1520	* (LL_ADC_RESOLUTION_8B,
<>	139:856d2700e60b	1521	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<>	139:856d2700e60b	1522	* );
<>	139:856d2700e60b	1523	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	139:856d2700e60b	1524	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1525	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1526	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1527	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1528	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1529	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1530	*/
<>	139:856d2700e60b	1531	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<>	139:856d2700e60b	1532	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	139:856d2700e60b	1533
<>	139:856d2700e60b	1534	/**
<>	139:856d2700e60b	1535	* @brief Helper macro to get the ADC multimode conversion data of ADC master
<>	139:856d2700e60b	1536	* or ADC slave from raw value with both ADC conversion data concatenated.
<>	139:856d2700e60b	1537	* @note This macro is intended to be used when multimode transfer by DMA
<>	139:856d2700e60b	1538	* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
<>	139:856d2700e60b	1539	* In this case the transferred data need to processed with this macro
<>	139:856d2700e60b	1540	* to separate the conversion data of ADC master and ADC slave.
<>	139:856d2700e60b	1541	* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
<>	139:856d2700e60b	1542	* @arg @ref LL_ADC_MULTI_MASTER
<>	139:856d2700e60b	1543	* @arg @ref LL_ADC_MULTI_SLAVE
<>	139:856d2700e60b	1544	* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1545	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	1546	*/
<>	139:856d2700e60b	1547	#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
<>	139:856d2700e60b	1548	(((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
<>	139:856d2700e60b	1549
<>	139:856d2700e60b	1550	/**
<>	139:856d2700e60b	1551	* @brief Helper macro to select the ADC common instance
<>	139:856d2700e60b	1552	* to which is belonging the selected ADC instance.
<>	139:856d2700e60b	1553	* @note ADC common register instance can be used for:
<>	139:856d2700e60b	1554	* - Set parameters common to several ADC instances
<>	139:856d2700e60b	1555	* - Multimode (for devices with several ADC instances)
<>	139:856d2700e60b	1556	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	139:856d2700e60b	1557	* @param __ADCx__ ADC instance
<>	139:856d2700e60b	1558	* @retval ADC common register instance
<>	139:856d2700e60b	1559	*/
<>	139:856d2700e60b	1560	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	139:856d2700e60b	1561	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	139:856d2700e60b	1562	(ADC123_COMMON)
<>	139:856d2700e60b	1563	#elif defined(ADC1) && defined(ADC2)
<>	139:856d2700e60b	1564	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	139:856d2700e60b	1565	(ADC12_COMMON)
<>	139:856d2700e60b	1566	#else
<>	139:856d2700e60b	1567	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	139:856d2700e60b	1568	(ADC1_COMMON)
<>	139:856d2700e60b	1569	#endif
<>	139:856d2700e60b	1570
<>	139:856d2700e60b	1571	/**
<>	139:856d2700e60b	1572	* @brief Helper macro to check if all ADC instances sharing the same
<>	139:856d2700e60b	1573	* ADC common instance are disabled.
<>	139:856d2700e60b	1574	* @note This check is required by functions with setting conditioned to
<>	139:856d2700e60b	1575	* ADC state:
<>	139:856d2700e60b	1576	* All ADC instances of the ADC common group must be disabled.
<>	139:856d2700e60b	1577	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	139:856d2700e60b	1578	* @note On devices with only 1 ADC common instance, parameter of this macro
<>	139:856d2700e60b	1579	* is useless and can be ignored (parameter kept for compatibility
<>	139:856d2700e60b	1580	* with devices featuring several ADC common instances).
<>	139:856d2700e60b	1581	* @param __ADCXY_COMMON__ ADC common instance
<>	139:856d2700e60b	1582	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	1583	* @retval Value "0" if all ADC instances sharing the same ADC common instance
<>	139:856d2700e60b	1584	* are disabled.
<>	139:856d2700e60b	1585	* Value "1" if at least one ADC instance sharing the same ADC common instance
<>	139:856d2700e60b	1586	* is enabled.
<>	139:856d2700e60b	1587	*/
<>	139:856d2700e60b	1588	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	139:856d2700e60b	1589	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	139:856d2700e60b	1590	(LL_ADC_IsEnabled(ADC1) \| \
<>	139:856d2700e60b	1591	LL_ADC_IsEnabled(ADC2) \| \
<>	139:856d2700e60b	1592	LL_ADC_IsEnabled(ADC3) )
<>	139:856d2700e60b	1593	#elif defined(ADC1) && defined(ADC2)
<>	139:856d2700e60b	1594	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	139:856d2700e60b	1595	(LL_ADC_IsEnabled(ADC1) \| \
<>	139:856d2700e60b	1596	LL_ADC_IsEnabled(ADC2) )
<>	139:856d2700e60b	1597	#else
<>	139:856d2700e60b	1598	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	139:856d2700e60b	1599	(LL_ADC_IsEnabled(ADC1))
<>	139:856d2700e60b	1600	#endif
<>	139:856d2700e60b	1601
<>	139:856d2700e60b	1602	/**
<>	139:856d2700e60b	1603	* @brief Helper macro to define the ADC conversion data full-scale digital
<>	139:856d2700e60b	1604	* value corresponding to the selected ADC resolution.
<>	139:856d2700e60b	1605	* @note ADC conversion data full-scale corresponds to voltage range
<>	139:856d2700e60b	1606	* determined by analog voltage references Vref+ and Vref-
<>	139:856d2700e60b	1607	* (refer to reference manual).
<>	139:856d2700e60b	1608	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	139:856d2700e60b	1609	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1610	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1611	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1612	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1613	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	139:856d2700e60b	1614	*/
<>	139:856d2700e60b	1615	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1616	(0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
<>	139:856d2700e60b	1617
<>	139:856d2700e60b	1618	/**
<>	139:856d2700e60b	1619	* @brief Helper macro to convert the ADC conversion data from
<>	139:856d2700e60b	1620	* a resolution to another resolution.
<>	139:856d2700e60b	1621	* @param __DATA__ ADC conversion data to be converted
<>	139:856d2700e60b	1622	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<>	139:856d2700e60b	1623	* This parameter can be one of the following values:
<>	139:856d2700e60b	1624	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1625	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1626	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1627	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1628	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<>	139:856d2700e60b	1629	* This parameter can be one of the following values:
<>	139:856d2700e60b	1630	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1631	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1632	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1633	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1634	* @retval ADC conversion data to the requested resolution
<>	139:856d2700e60b	1635	*/
<>	139:856d2700e60b	1636	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
<>	139:856d2700e60b	1637	(((__DATA__) \
<>	139:856d2700e60b	1638	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
<>	139:856d2700e60b	1639	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
<>	139:856d2700e60b	1640	)
<>	139:856d2700e60b	1641
<>	139:856d2700e60b	1642	/**
<>	139:856d2700e60b	1643	* @brief Helper macro to calculate the voltage (unit: mVolt)
<>	139:856d2700e60b	1644	* corresponding to a ADC conversion data (unit: digital value).
<>	139:856d2700e60b	1645	* @note Analog reference voltage (Vref+) must be either known from
<>	139:856d2700e60b	1646	* user board environment or can be calculated using ADC measurement
<>	139:856d2700e60b	1647	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge	163:e59c8e839560	1648	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
<>	139:856d2700e60b	1649	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	139:856d2700e60b	1650	* (unit: digital value).
<>	139:856d2700e60b	1651	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	139:856d2700e60b	1652	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1653	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1654	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1655	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1656	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	139:856d2700e60b	1657	*/
<>	139:856d2700e60b	1658	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<>	139:856d2700e60b	1659	__ADC_DATA__,\
<>	139:856d2700e60b	1660	__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1661	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<>	139:856d2700e60b	1662	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1663	)
<>	139:856d2700e60b	1664
<>	139:856d2700e60b	1665	/**
<>	139:856d2700e60b	1666	* @brief Helper macro to calculate analog reference voltage (Vref+)
<>	139:856d2700e60b	1667	* (unit: mVolt) from ADC conversion data of internal voltage
<>	139:856d2700e60b	1668	* reference VrefInt.
<>	139:856d2700e60b	1669	* @note Computation is using VrefInt calibration value
<>	139:856d2700e60b	1670	* stored in system memory for each device during production.
<>	139:856d2700e60b	1671	* @note This voltage depends on user board environment: voltage level
<>	139:856d2700e60b	1672	* connected to pin Vref+.
<>	139:856d2700e60b	1673	* On devices with small package, the pin Vref+ is not present
<>	139:856d2700e60b	1674	* and internally bonded to pin Vdda.
<>	139:856d2700e60b	1675	* @note On this STM32 serie, calibration data of internal voltage reference
<>	139:856d2700e60b	1676	* VrefInt corresponds to a resolution of 12 bits,
<>	139:856d2700e60b	1677	* this is the recommended ADC resolution to convert voltage of
<>	139:856d2700e60b	1678	* internal voltage reference VrefInt.
<>	139:856d2700e60b	1679	* Otherwise, this macro performs the processing to scale
<>	139:856d2700e60b	1680	* ADC conversion data to 12 bits.
AnnaBridge	163:e59c8e839560	1681	* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	139:856d2700e60b	1682	* of internal voltage reference VrefInt (unit: digital value).
<>	139:856d2700e60b	1683	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	139:856d2700e60b	1684	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1685	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1686	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1687	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1688	* @retval Analog reference voltage (unit: mV)
<>	139:856d2700e60b	1689	*/
<>	139:856d2700e60b	1690	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<>	139:856d2700e60b	1691	__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1692	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
<>	139:856d2700e60b	1693	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<>	139:856d2700e60b	1694	(__ADC_RESOLUTION__), \
<>	139:856d2700e60b	1695	LL_ADC_RESOLUTION_12B) \
<>	139:856d2700e60b	1696	)
<>	139:856d2700e60b	1697
<>	139:856d2700e60b	1698	/**
<>	139:856d2700e60b	1699	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	139:856d2700e60b	1700	* from ADC conversion data of internal temperature sensor.
<>	139:856d2700e60b	1701	* @note Computation is using temperature sensor calibration values
<>	139:856d2700e60b	1702	* stored in system memory for each device during production.
<>	139:856d2700e60b	1703	* @note Calculation formula:
<>	139:856d2700e60b	1704	* Temperature = ((TS_ADC_DATA - TS_CAL1)
<>	139:856d2700e60b	1705	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<>	139:856d2700e60b	1706	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<>	139:856d2700e60b	1707	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	139:856d2700e60b	1708	* Avg_Slope = (TS_CAL2 - TS_CAL1)
<>	139:856d2700e60b	1709	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<>	139:856d2700e60b	1710	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
<>	139:856d2700e60b	1711	* TEMP_DEGC_CAL1 (calibrated in factory)
<>	139:856d2700e60b	1712	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
<>	139:856d2700e60b	1713	* TEMP_DEGC_CAL2 (calibrated in factory)
<>	139:856d2700e60b	1714	* Caution: Calculation relevancy under reserve that calibration
<>	139:856d2700e60b	1715	* parameters are correct (address and data).
<>	139:856d2700e60b	1716	* To calculate temperature using temperature sensor
<>	139:856d2700e60b	1717	* datasheet typical values (generic values less, therefore
<>	139:856d2700e60b	1718	* less accurate than calibrated values),
<>	139:856d2700e60b	1719	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<>	139:856d2700e60b	1720	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	139:856d2700e60b	1721	* defined as it impacts the ADC LSB equivalent voltage.
<>	139:856d2700e60b	1722	* @note Analog reference voltage (Vref+) must be either known from
<>	139:856d2700e60b	1723	* user board environment or can be calculated using ADC measurement
<>	139:856d2700e60b	1724	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	139:856d2700e60b	1725	* @note On this STM32 serie, calibration data of temperature sensor
<>	139:856d2700e60b	1726	* corresponds to a resolution of 12 bits,
<>	139:856d2700e60b	1727	* this is the recommended ADC resolution to convert voltage of
<>	139:856d2700e60b	1728	* temperature sensor.
<>	139:856d2700e60b	1729	* Otherwise, this macro performs the processing to scale
<>	139:856d2700e60b	1730	* ADC conversion data to 12 bits.
AnnaBridge	163:e59c8e839560	1731	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
<>	139:856d2700e60b	1732	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<>	139:856d2700e60b	1733	* temperature sensor (unit: digital value).
<>	139:856d2700e60b	1734	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<>	139:856d2700e60b	1735	* sensor voltage has been measured.
<>	139:856d2700e60b	1736	* This parameter can be one of the following values:
<>	139:856d2700e60b	1737	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1738	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1739	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1740	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1741	* @retval Temperature (unit: degree Celsius)
<>	139:856d2700e60b	1742	*/
<>	139:856d2700e60b	1743	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<>	139:856d2700e60b	1744	__TEMPSENSOR_ADC_DATA__,\
<>	139:856d2700e60b	1745	__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1746	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<>	139:856d2700e60b	1747	(__ADC_RESOLUTION__), \
<>	139:856d2700e60b	1748	LL_ADC_RESOLUTION_12B) \
<>	139:856d2700e60b	1749	* (__VREFANALOG_VOLTAGE__)) \
<>	139:856d2700e60b	1750	/ TEMPSENSOR_CAL_VREFANALOG) \
<>	139:856d2700e60b	1751	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<>	139:856d2700e60b	1752	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<>	139:856d2700e60b	1753	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
<>	139:856d2700e60b	1754	) + TEMPSENSOR_CAL1_TEMP \
<>	139:856d2700e60b	1755	)
<>	139:856d2700e60b	1756
<>	139:856d2700e60b	1757	/**
<>	139:856d2700e60b	1758	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	139:856d2700e60b	1759	* from ADC conversion data of internal temperature sensor.
<>	139:856d2700e60b	1760	* @note Computation is using temperature sensor typical values
<>	139:856d2700e60b	1761	* (refer to device datasheet).
<>	139:856d2700e60b	1762	* @note Calculation formula:
<>	139:856d2700e60b	1763	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<>	139:856d2700e60b	1764	* / Avg_Slope + CALx_TEMP
<>	139:856d2700e60b	1765	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	139:856d2700e60b	1766	* (unit: digital value)
<>	139:856d2700e60b	1767	* Avg_Slope = temperature sensor slope
<>	139:856d2700e60b	1768	* (unit: uV/Degree Celsius)
<>	139:856d2700e60b	1769	* TS_TYP_CALx_VOLT = temperature sensor digital value at
<>	139:856d2700e60b	1770	* temperature CALx_TEMP (unit: mV)
<>	139:856d2700e60b	1771	* Caution: Calculation relevancy under reserve the temperature sensor
<>	139:856d2700e60b	1772	* of the current device has characteristics in line with
<>	139:856d2700e60b	1773	* datasheet typical values.
<>	139:856d2700e60b	1774	* If temperature sensor calibration values are available on
<>	139:856d2700e60b	1775	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<>	139:856d2700e60b	1776	* temperature calculation will be more accurate using
<>	139:856d2700e60b	1777	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<>	139:856d2700e60b	1778	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	139:856d2700e60b	1779	* defined as it impacts the ADC LSB equivalent voltage.
<>	139:856d2700e60b	1780	* @note Analog reference voltage (Vref+) must be either known from
<>	139:856d2700e60b	1781	* user board environment or can be calculated using ADC measurement
<>	139:856d2700e60b	1782	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	139:856d2700e60b	1783	* @note ADC measurement data must correspond to a resolution of 12bits
<>	139:856d2700e60b	1784	* (full scale digital value 4095). If not the case, the data must be
<>	139:856d2700e60b	1785	* preliminarily rescaled to an equivalent resolution of 12 bits.
AnnaBridge	163:e59c8e839560	1786	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
<>	139:856d2700e60b	1787	* On STM32F7, refer to device datasheet parameter "Avg_Slope".
AnnaBridge	163:e59c8e839560	1788	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
<>	139:856d2700e60b	1789	* On STM32F4, refer to device datasheet parameter "V25".
AnnaBridge	163:e59c8e839560	1790	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
AnnaBridge	163:e59c8e839560	1791	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
AnnaBridge	163:e59c8e839560	1792	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
<>	139:856d2700e60b	1793	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<>	139:856d2700e60b	1794	* This parameter can be one of the following values:
<>	139:856d2700e60b	1795	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1796	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	1797	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	1798	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	1799	* @retval Temperature (unit: degree Celsius)
<>	139:856d2700e60b	1800	*/
<>	139:856d2700e60b	1801	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<>	139:856d2700e60b	1802	__TEMPSENSOR_TYP_CALX_V__,\
<>	139:856d2700e60b	1803	__TEMPSENSOR_CALX_TEMP__,\
<>	139:856d2700e60b	1804	__VREFANALOG_VOLTAGE__,\
<>	139:856d2700e60b	1805	__TEMPSENSOR_ADC_DATA__,\
<>	139:856d2700e60b	1806	__ADC_RESOLUTION__) \
<>	139:856d2700e60b	1807	((( ( \
<>	139:856d2700e60b	1808	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<>	139:856d2700e60b	1809	* 1000) \
<>	139:856d2700e60b	1810	- \
<>	139:856d2700e60b	1811	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<>	139:856d2700e60b	1812	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<>	139:856d2700e60b	1813	* 1000) \
<>	139:856d2700e60b	1814	) \
<>	139:856d2700e60b	1815	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<>	139:856d2700e60b	1816	) + (__TEMPSENSOR_CALX_TEMP__) \
<>	139:856d2700e60b	1817	)
<>	139:856d2700e60b	1818
<>	139:856d2700e60b	1819	/**
<>	139:856d2700e60b	1820	* @}
<>	139:856d2700e60b	1821	*/
<>	139:856d2700e60b	1822
<>	139:856d2700e60b	1823	/**
<>	139:856d2700e60b	1824	* @}
<>	139:856d2700e60b	1825	*/
<>	139:856d2700e60b	1826
<>	139:856d2700e60b	1827
<>	139:856d2700e60b	1828	/* Exported functions --------------------------------------------------------*/
<>	139:856d2700e60b	1829	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<>	139:856d2700e60b	1830	* @{
<>	139:856d2700e60b	1831	*/
<>	139:856d2700e60b	1832
<>	139:856d2700e60b	1833	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<>	139:856d2700e60b	1834	* @{
<>	139:856d2700e60b	1835	*/
<>	139:856d2700e60b	1836	/* Note: LL ADC functions to set DMA transfer are located into sections of */
<>	139:856d2700e60b	1837	/* configuration of ADC instance, groups and multimode (if available): */
<>	139:856d2700e60b	1838	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
<>	139:856d2700e60b	1839
<>	139:856d2700e60b	1840	/**
<>	139:856d2700e60b	1841	* @brief Function to help to configure DMA transfer from ADC: retrieve the
<>	139:856d2700e60b	1842	* ADC register address from ADC instance and a list of ADC registers
<>	139:856d2700e60b	1843	* intended to be used (most commonly) with DMA transfer.
<>	139:856d2700e60b	1844	* @note These ADC registers are data registers:
<>	139:856d2700e60b	1845	* when ADC conversion data is available in ADC data registers,
<>	139:856d2700e60b	1846	* ADC generates a DMA transfer request.
<>	139:856d2700e60b	1847	* @note This macro is intended to be used with LL DMA driver, refer to
<>	139:856d2700e60b	1848	* function "LL_DMA_ConfigAddresses()".
<>	139:856d2700e60b	1849	* Example:
<>	139:856d2700e60b	1850	* LL_DMA_ConfigAddresses(DMA1,
<>	139:856d2700e60b	1851	* LL_DMA_CHANNEL_1,
<>	139:856d2700e60b	1852	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<>	139:856d2700e60b	1853	* (uint32_t)&< array or variable >,
<>	139:856d2700e60b	1854	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<>	139:856d2700e60b	1855	* @note For devices with several ADC: in multimode, some devices
<>	139:856d2700e60b	1856	* use a different data register outside of ADC instance scope
<>	139:856d2700e60b	1857	* (common data register). This macro manages this register difference,
<>	139:856d2700e60b	1858	* only ADC instance has to be set as parameter.
<>	139:856d2700e60b	1859	* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
<>	139:856d2700e60b	1860	* CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
<>	139:856d2700e60b	1861	* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
<>	139:856d2700e60b	1862	* @param ADCx ADC instance
<>	139:856d2700e60b	1863	* @param Register This parameter can be one of the following values:
<>	139:856d2700e60b	1864	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<>	139:856d2700e60b	1865	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
<>	139:856d2700e60b	1866	*
<>	139:856d2700e60b	1867	* (1) Available on devices with several ADC instances.
<>	139:856d2700e60b	1868	* @retval ADC register address
<>	139:856d2700e60b	1869	*/
<>	139:856d2700e60b	1870	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	139:856d2700e60b	1871	{
<>	139:856d2700e60b	1872	register uint32_t data_reg_addr = 0U;
<>	139:856d2700e60b	1873
<>	139:856d2700e60b	1874	if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
<>	139:856d2700e60b	1875	{
<>	139:856d2700e60b	1876	/* Retrieve address of register DR */
<>	139:856d2700e60b	1877	data_reg_addr = (uint32_t)&(ADCx->DR);
<>	139:856d2700e60b	1878	}
<>	139:856d2700e60b	1879	else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
<>	139:856d2700e60b	1880	{
<>	139:856d2700e60b	1881	/* Retrieve address of register CDR */
<>	139:856d2700e60b	1882	data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
<>	139:856d2700e60b	1883	}
<>	139:856d2700e60b	1884
<>	139:856d2700e60b	1885	return data_reg_addr;
<>	139:856d2700e60b	1886	}
<>	139:856d2700e60b	1887
<>	139:856d2700e60b	1888	/**
<>	139:856d2700e60b	1889	* @}
<>	139:856d2700e60b	1890	*/
<>	139:856d2700e60b	1891
<>	139:856d2700e60b	1892	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<>	139:856d2700e60b	1893	* @{
<>	139:856d2700e60b	1894	*/
<>	139:856d2700e60b	1895
<>	139:856d2700e60b	1896	/**
<>	139:856d2700e60b	1897	* @brief Set parameter common to several ADC: Clock source and prescaler.
<>	139:856d2700e60b	1898	* @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
<>	139:856d2700e60b	1899	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	1900	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	1901	* @param CommonClock This parameter can be one of the following values:
<>	139:856d2700e60b	1902	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	139:856d2700e60b	1903	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	139:856d2700e60b	1904	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
<>	139:856d2700e60b	1905	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
<>	139:856d2700e60b	1906	* @retval None
<>	139:856d2700e60b	1907	*/
<>	139:856d2700e60b	1908	__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
<>	139:856d2700e60b	1909	{
<>	139:856d2700e60b	1910	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
<>	139:856d2700e60b	1911	}
<>	139:856d2700e60b	1912
<>	139:856d2700e60b	1913	/**
<>	139:856d2700e60b	1914	* @brief Get parameter common to several ADC: Clock source and prescaler.
<>	139:856d2700e60b	1915	* @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
<>	139:856d2700e60b	1916	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	1917	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	1918	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	1919	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	139:856d2700e60b	1920	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	139:856d2700e60b	1921	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
<>	139:856d2700e60b	1922	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
<>	139:856d2700e60b	1923	*/
<>	139:856d2700e60b	1924	__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	1925	{
<>	139:856d2700e60b	1926	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
<>	139:856d2700e60b	1927	}
<>	139:856d2700e60b	1928
<>	139:856d2700e60b	1929	/**
<>	139:856d2700e60b	1930	* @brief Set parameter common to several ADC: measurement path to internal
<>	139:856d2700e60b	1931	* channels (VrefInt, temperature sensor, ...).
<>	139:856d2700e60b	1932	* @note One or several values can be selected.
<>	139:856d2700e60b	1933	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	139:856d2700e60b	1934	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	139:856d2700e60b	1935	* @note Stabilization time of measurement path to internal channel:
<>	139:856d2700e60b	1936	* After enabling internal paths, before starting ADC conversion,
<>	139:856d2700e60b	1937	* a delay is required for internal voltage reference and
<>	139:856d2700e60b	1938	* temperature sensor stabilization time.
<>	139:856d2700e60b	1939	* Refer to device datasheet.
<>	139:856d2700e60b	1940	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<>	139:856d2700e60b	1941	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<>	139:856d2700e60b	1942	* @note ADC internal channel sampling time constraint:
<>	139:856d2700e60b	1943	* For ADC conversion of internal channels,
<>	139:856d2700e60b	1944	* a sampling time minimum value is required.
<>	139:856d2700e60b	1945	* Refer to device datasheet.
<>	139:856d2700e60b	1946	* @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
<>	139:856d2700e60b	1947	* CCR VBATE LL_ADC_SetCommonPathInternalCh
<>	139:856d2700e60b	1948	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	1949	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	1950	* @param PathInternal This parameter can be a combination of the following values:
<>	139:856d2700e60b	1951	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	139:856d2700e60b	1952	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	139:856d2700e60b	1953	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	139:856d2700e60b	1954	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	139:856d2700e60b	1955	* @retval None
<>	139:856d2700e60b	1956	*/
<>	139:856d2700e60b	1957	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<>	139:856d2700e60b	1958	{
<>	139:856d2700e60b	1959	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE \| ADC_CCR_VBATE, PathInternal);
<>	139:856d2700e60b	1960	}
<>	139:856d2700e60b	1961
<>	139:856d2700e60b	1962	/**
<>	139:856d2700e60b	1963	* @brief Get parameter common to several ADC: measurement path to internal
<>	139:856d2700e60b	1964	* channels (VrefInt, temperature sensor, ...).
<>	139:856d2700e60b	1965	* @note One or several values can be selected.
<>	139:856d2700e60b	1966	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	139:856d2700e60b	1967	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	139:856d2700e60b	1968	* @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
<>	139:856d2700e60b	1969	* CCR VBATE LL_ADC_GetCommonPathInternalCh
<>	139:856d2700e60b	1970	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	1971	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	1972	* @retval Returned value can be a combination of the following values:
<>	139:856d2700e60b	1973	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	139:856d2700e60b	1974	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	139:856d2700e60b	1975	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	139:856d2700e60b	1976	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	139:856d2700e60b	1977	*/
<>	139:856d2700e60b	1978	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	1979	{
<>	139:856d2700e60b	1980	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE \| ADC_CCR_VBATE));
<>	139:856d2700e60b	1981	}
<>	139:856d2700e60b	1982
<>	139:856d2700e60b	1983	/**
<>	139:856d2700e60b	1984	* @}
<>	139:856d2700e60b	1985	*/
<>	139:856d2700e60b	1986
<>	139:856d2700e60b	1987	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<>	139:856d2700e60b	1988	* @{
<>	139:856d2700e60b	1989	*/
<>	139:856d2700e60b	1990
<>	139:856d2700e60b	1991	/**
<>	139:856d2700e60b	1992	* @brief Set ADC resolution.
<>	139:856d2700e60b	1993	* Refer to reference manual for alignments formats
<>	139:856d2700e60b	1994	* dependencies to ADC resolutions.
<>	139:856d2700e60b	1995	* @rmtoll CR1 RES LL_ADC_SetResolution
<>	139:856d2700e60b	1996	* @param ADCx ADC instance
<>	139:856d2700e60b	1997	* @param Resolution This parameter can be one of the following values:
<>	139:856d2700e60b	1998	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	1999	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	2000	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	2001	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	2002	* @retval None
<>	139:856d2700e60b	2003	*/
<>	139:856d2700e60b	2004	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<>	139:856d2700e60b	2005	{
<>	139:856d2700e60b	2006	MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
<>	139:856d2700e60b	2007	}
<>	139:856d2700e60b	2008
<>	139:856d2700e60b	2009	/**
<>	139:856d2700e60b	2010	* @brief Get ADC resolution.
<>	139:856d2700e60b	2011	* Refer to reference manual for alignments formats
<>	139:856d2700e60b	2012	* dependencies to ADC resolutions.
<>	139:856d2700e60b	2013	* @rmtoll CR1 RES LL_ADC_GetResolution
<>	139:856d2700e60b	2014	* @param ADCx ADC instance
<>	139:856d2700e60b	2015	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2016	* @arg @ref LL_ADC_RESOLUTION_12B
<>	139:856d2700e60b	2017	* @arg @ref LL_ADC_RESOLUTION_10B
<>	139:856d2700e60b	2018	* @arg @ref LL_ADC_RESOLUTION_8B
<>	139:856d2700e60b	2019	* @arg @ref LL_ADC_RESOLUTION_6B
<>	139:856d2700e60b	2020	*/
<>	139:856d2700e60b	2021	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2022	{
<>	139:856d2700e60b	2023	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
<>	139:856d2700e60b	2024	}
<>	139:856d2700e60b	2025
<>	139:856d2700e60b	2026	/**
<>	139:856d2700e60b	2027	* @brief Set ADC conversion data alignment.
<>	139:856d2700e60b	2028	* @note Refer to reference manual for alignments formats
<>	139:856d2700e60b	2029	* dependencies to ADC resolutions.
<>	139:856d2700e60b	2030	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	139:856d2700e60b	2031	* @param ADCx ADC instance
<>	139:856d2700e60b	2032	* @param DataAlignment This parameter can be one of the following values:
<>	139:856d2700e60b	2033	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	139:856d2700e60b	2034	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	139:856d2700e60b	2035	* @retval None
<>	139:856d2700e60b	2036	*/
<>	139:856d2700e60b	2037	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<>	139:856d2700e60b	2038	{
<>	139:856d2700e60b	2039	MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
<>	139:856d2700e60b	2040	}
<>	139:856d2700e60b	2041
<>	139:856d2700e60b	2042	/**
<>	139:856d2700e60b	2043	* @brief Get ADC conversion data alignment.
<>	139:856d2700e60b	2044	* @note Refer to reference manual for alignments formats
<>	139:856d2700e60b	2045	* dependencies to ADC resolutions.
<>	139:856d2700e60b	2046	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	139:856d2700e60b	2047	* @param ADCx ADC instance
<>	139:856d2700e60b	2048	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2049	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	139:856d2700e60b	2050	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	139:856d2700e60b	2051	*/
<>	139:856d2700e60b	2052	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2053	{
<>	139:856d2700e60b	2054	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
<>	139:856d2700e60b	2055	}
<>	139:856d2700e60b	2056
<>	139:856d2700e60b	2057	/**
<>	139:856d2700e60b	2058	* @brief Set ADC sequencers scan mode, for all ADC groups
<>	139:856d2700e60b	2059	* (group regular, group injected).
<>	139:856d2700e60b	2060	* @note According to sequencers scan mode :
<>	139:856d2700e60b	2061	* - If disabled: ADC conversion is performed in unitary conversion
<>	139:856d2700e60b	2062	* mode (one channel converted, that defined in rank 1).
<>	139:856d2700e60b	2063	* Configuration of sequencers of all ADC groups
<>	139:856d2700e60b	2064	* (sequencer scan length, ...) is discarded: equivalent to
<>	139:856d2700e60b	2065	* scan length of 1 rank.
<>	139:856d2700e60b	2066	* - If enabled: ADC conversions are performed in sequence conversions
<>	139:856d2700e60b	2067	* mode, according to configuration of sequencers of
<>	139:856d2700e60b	2068	* each ADC group (sequencer scan length, ...).
<>	139:856d2700e60b	2069	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	139:856d2700e60b	2070	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	139:856d2700e60b	2071	* @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
<>	139:856d2700e60b	2072	* @param ADCx ADC instance
<>	139:856d2700e60b	2073	* @param ScanMode This parameter can be one of the following values:
<>	139:856d2700e60b	2074	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2075	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	139:856d2700e60b	2076	* @retval None
<>	139:856d2700e60b	2077	*/
<>	139:856d2700e60b	2078	__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
<>	139:856d2700e60b	2079	{
<>	139:856d2700e60b	2080	MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
<>	139:856d2700e60b	2081	}
<>	139:856d2700e60b	2082
<>	139:856d2700e60b	2083	/**
<>	139:856d2700e60b	2084	* @brief Get ADC sequencers scan mode, for all ADC groups
<>	139:856d2700e60b	2085	* (group regular, group injected).
<>	139:856d2700e60b	2086	* @note According to sequencers scan mode :
<>	139:856d2700e60b	2087	* - If disabled: ADC conversion is performed in unitary conversion
<>	139:856d2700e60b	2088	* mode (one channel converted, that defined in rank 1).
<>	139:856d2700e60b	2089	* Configuration of sequencers of all ADC groups
<>	139:856d2700e60b	2090	* (sequencer scan length, ...) is discarded: equivalent to
<>	139:856d2700e60b	2091	* scan length of 1 rank.
<>	139:856d2700e60b	2092	* - If enabled: ADC conversions are performed in sequence conversions
<>	139:856d2700e60b	2093	* mode, according to configuration of sequencers of
<>	139:856d2700e60b	2094	* each ADC group (sequencer scan length, ...).
<>	139:856d2700e60b	2095	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	139:856d2700e60b	2096	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	139:856d2700e60b	2097	* @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
<>	139:856d2700e60b	2098	* @param ADCx ADC instance
<>	139:856d2700e60b	2099	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2100	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2101	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	139:856d2700e60b	2102	*/
<>	139:856d2700e60b	2103	__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2104	{
<>	139:856d2700e60b	2105	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
<>	139:856d2700e60b	2106	}
<>	139:856d2700e60b	2107
<>	139:856d2700e60b	2108	/**
<>	139:856d2700e60b	2109	* @}
<>	139:856d2700e60b	2110	*/
<>	139:856d2700e60b	2111
<>	139:856d2700e60b	2112	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<>	139:856d2700e60b	2113	* @{
<>	139:856d2700e60b	2114	*/
<>	139:856d2700e60b	2115
<>	139:856d2700e60b	2116	/**
<>	139:856d2700e60b	2117	* @brief Set ADC group regular conversion trigger source:
<>	139:856d2700e60b	2118	* internal (SW start) or from external IP (timer event,
<>	139:856d2700e60b	2119	* external interrupt line).
<>	139:856d2700e60b	2120	* @note On this STM32 serie, setting of external trigger edge is performed
<>	139:856d2700e60b	2121	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	139:856d2700e60b	2122	* @note Availability of parameters of trigger sources from timer
<>	139:856d2700e60b	2123	* depends on timers availability on the selected device.
<>	139:856d2700e60b	2124	* @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
<>	139:856d2700e60b	2125	* CR2 EXTEN LL_ADC_REG_SetTriggerSource
<>	139:856d2700e60b	2126	* @param ADCx ADC instance
<>	139:856d2700e60b	2127	* @param TriggerSource This parameter can be one of the following values:
<>	139:856d2700e60b	2128	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	139:856d2700e60b	2129	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	139:856d2700e60b	2130	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	139:856d2700e60b	2131	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	139:856d2700e60b	2132	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	139:856d2700e60b	2133	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
<>	139:856d2700e60b	2134	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	139:856d2700e60b	2135	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	139:856d2700e60b	2136	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	139:856d2700e60b	2137	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	139:856d2700e60b	2138	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	139:856d2700e60b	2139	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	139:856d2700e60b	2140	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	139:856d2700e60b	2141	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	139:856d2700e60b	2142	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	139:856d2700e60b	2143	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	139:856d2700e60b	2144	* @retval None
<>	139:856d2700e60b	2145	*/
<>	139:856d2700e60b	2146	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	139:856d2700e60b	2147	{
<>	139:856d2700e60b	2148	/* Note: On this STM32 serie, ADC group regular external trigger edge */
<>	139:856d2700e60b	2149	/* is used to perform a ADC conversion start. */
<>	139:856d2700e60b	2150	/* This function does not set external trigger edge. */
<>	139:856d2700e60b	2151	/* This feature is set using function */
<>	139:856d2700e60b	2152	/* @ref LL_ADC_REG_StartConversionExtTrig(). */
<>	139:856d2700e60b	2153	MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
<>	139:856d2700e60b	2154	}
<>	139:856d2700e60b	2155
<>	139:856d2700e60b	2156	/**
<>	139:856d2700e60b	2157	* @brief Get ADC group regular conversion trigger source:
<>	139:856d2700e60b	2158	* internal (SW start) or from external IP (timer event,
<>	139:856d2700e60b	2159	* external interrupt line).
<>	139:856d2700e60b	2160	* @note To determine whether group regular trigger source is
<>	139:856d2700e60b	2161	* internal (SW start) or external, without detail
<>	139:856d2700e60b	2162	* of which peripheral is selected as external trigger,
<>	139:856d2700e60b	2163	* (equivalent to
<>	139:856d2700e60b	2164	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<>	139:856d2700e60b	2165	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<>	139:856d2700e60b	2166	* @note Availability of parameters of trigger sources from timer
<>	139:856d2700e60b	2167	* depends on timers availability on the selected device.
<>	139:856d2700e60b	2168	* @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
<>	139:856d2700e60b	2169	* CR2 EXTEN LL_ADC_REG_GetTriggerSource
<>	139:856d2700e60b	2170	* @param ADCx ADC instance
<>	139:856d2700e60b	2171	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2172	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	139:856d2700e60b	2173	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	139:856d2700e60b	2174	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	139:856d2700e60b	2175	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	139:856d2700e60b	2176	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	139:856d2700e60b	2177	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
<>	139:856d2700e60b	2178	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	139:856d2700e60b	2179	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	139:856d2700e60b	2180	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	139:856d2700e60b	2181	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	139:856d2700e60b	2182	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	139:856d2700e60b	2183	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	139:856d2700e60b	2184	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	139:856d2700e60b	2185	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	139:856d2700e60b	2186	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	139:856d2700e60b	2187	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	139:856d2700e60b	2188	*/
<>	139:856d2700e60b	2189	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2190	{
<>	139:856d2700e60b	2191	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL \| ADC_CR2_EXTEN);
<>	139:856d2700e60b	2192
<>	139:856d2700e60b	2193	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	139:856d2700e60b	2194	/* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
<>	139:856d2700e60b	2195	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	139:856d2700e60b	2196
<>	139:856d2700e60b	2197	/* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
<>	139:856d2700e60b	2198	/* to match with triggers literals definition. */
<>	139:856d2700e60b	2199	return ((TriggerSource
<>	139:856d2700e60b	2200	& (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
<>	139:856d2700e60b	2201	\| ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
<>	139:856d2700e60b	2202	);
<>	139:856d2700e60b	2203	}
<>	139:856d2700e60b	2204
<>	139:856d2700e60b	2205	/**
<>	139:856d2700e60b	2206	* @brief Get ADC group regular conversion trigger source internal (SW start)
<>	139:856d2700e60b	2207	or external.
<>	139:856d2700e60b	2208	* @note In case of group regular trigger source set to external trigger,
<>	139:856d2700e60b	2209	* to determine which peripheral is selected as external trigger,
<>	139:856d2700e60b	2210	* use function @ref LL_ADC_REG_GetTriggerSource().
<>	139:856d2700e60b	2211	* @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<>	139:856d2700e60b	2212	* @param ADCx ADC instance
<>	139:856d2700e60b	2213	* @retval Value "0" if trigger source external trigger
<>	139:856d2700e60b	2214	* Value "1" if trigger source SW start.
<>	139:856d2700e60b	2215	*/
<>	139:856d2700e60b	2216	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2217	{
<>	139:856d2700e60b	2218	return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
<>	139:856d2700e60b	2219	}
<>	139:856d2700e60b	2220
<>	139:856d2700e60b	2221	/**
<>	139:856d2700e60b	2222	* @brief Get ADC group regular conversion trigger polarity.
<>	139:856d2700e60b	2223	* @note Applicable only for trigger source set to external trigger.
<>	139:856d2700e60b	2224	* @note On this STM32 serie, setting of external trigger edge is performed
<>	139:856d2700e60b	2225	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	139:856d2700e60b	2226	* @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
<>	139:856d2700e60b	2227	* @param ADCx ADC instance
<>	139:856d2700e60b	2228	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2229	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	139:856d2700e60b	2230	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	139:856d2700e60b	2231	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	139:856d2700e60b	2232	*/
<>	139:856d2700e60b	2233	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2234	{
<>	139:856d2700e60b	2235	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
<>	139:856d2700e60b	2236	}
<>	139:856d2700e60b	2237
<>	139:856d2700e60b	2238
<>	139:856d2700e60b	2239	/**
<>	139:856d2700e60b	2240	* @brief Set ADC group regular sequencer length and scan direction.
<>	139:856d2700e60b	2241	* @note Description of ADC group regular sequencer features:
<>	139:856d2700e60b	2242	* - For devices with sequencer fully configurable
<>	139:856d2700e60b	2243	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	139:856d2700e60b	2244	* sequencer length and each rank affectation to a channel
<>	139:856d2700e60b	2245	* are configurable.
<>	139:856d2700e60b	2246	* This function performs configuration of:
<>	139:856d2700e60b	2247	* - Sequence length: Number of ranks in the scan sequence.
<>	139:856d2700e60b	2248	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2249	* scan direction is forward (from rank 1 to rank n).
<>	139:856d2700e60b	2250	* Sequencer ranks are selected using
<>	139:856d2700e60b	2251	* function "LL_ADC_REG_SetSequencerRanks()".
<>	139:856d2700e60b	2252	* - For devices with sequencer not fully configurable
<>	139:856d2700e60b	2253	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	139:856d2700e60b	2254	* sequencer length and each rank affectation to a channel
<>	139:856d2700e60b	2255	* are defined by channel number.
<>	139:856d2700e60b	2256	* This function performs configuration of:
<>	139:856d2700e60b	2257	* - Sequence length: Number of ranks in the scan sequence is
<>	139:856d2700e60b	2258	* defined by number of channels set in the sequence,
<>	139:856d2700e60b	2259	* rank of each channel is fixed by channel HW number.
<>	139:856d2700e60b	2260	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	139:856d2700e60b	2261	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2262	* scan direction is forward (from lowest channel number to
<>	139:856d2700e60b	2263	* highest channel number).
<>	139:856d2700e60b	2264	* Sequencer ranks are selected using
<>	139:856d2700e60b	2265	* function "LL_ADC_REG_SetSequencerChannels()".
<>	139:856d2700e60b	2266	* @note On this STM32 serie, group regular sequencer configuration
<>	139:856d2700e60b	2267	* is conditioned to ADC instance sequencer mode.
<>	139:856d2700e60b	2268	* If ADC instance sequencer mode is disabled, sequencers of
<>	139:856d2700e60b	2269	* all groups (group regular, group injected) can be configured
<>	139:856d2700e60b	2270	* but their execution is disabled (limited to rank 1).
<>	139:856d2700e60b	2271	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	139:856d2700e60b	2272	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	139:856d2700e60b	2273	* ADC conversion on only 1 channel.
<>	139:856d2700e60b	2274	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	139:856d2700e60b	2275	* @param ADCx ADC instance
<>	139:856d2700e60b	2276	* @param SequencerNbRanks This parameter can be one of the following values:
<>	139:856d2700e60b	2277	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2278	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	139:856d2700e60b	2279	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	139:856d2700e60b	2280	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	139:856d2700e60b	2281	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	139:856d2700e60b	2282	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	139:856d2700e60b	2283	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	139:856d2700e60b	2284	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	139:856d2700e60b	2285	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	139:856d2700e60b	2286	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	139:856d2700e60b	2287	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	139:856d2700e60b	2288	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	139:856d2700e60b	2289	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	139:856d2700e60b	2290	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	139:856d2700e60b	2291	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	139:856d2700e60b	2292	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	139:856d2700e60b	2293	* @retval None
<>	139:856d2700e60b	2294	*/
<>	139:856d2700e60b	2295	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	139:856d2700e60b	2296	{
<>	139:856d2700e60b	2297	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
<>	139:856d2700e60b	2298	}
<>	139:856d2700e60b	2299
<>	139:856d2700e60b	2300	/**
<>	139:856d2700e60b	2301	* @brief Get ADC group regular sequencer length and scan direction.
<>	139:856d2700e60b	2302	* @note Description of ADC group regular sequencer features:
<>	139:856d2700e60b	2303	* - For devices with sequencer fully configurable
<>	139:856d2700e60b	2304	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	139:856d2700e60b	2305	* sequencer length and each rank affectation to a channel
<>	139:856d2700e60b	2306	* are configurable.
<>	139:856d2700e60b	2307	* This function retrieves:
<>	139:856d2700e60b	2308	* - Sequence length: Number of ranks in the scan sequence.
<>	139:856d2700e60b	2309	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2310	* scan direction is forward (from rank 1 to rank n).
<>	139:856d2700e60b	2311	* Sequencer ranks are selected using
<>	139:856d2700e60b	2312	* function "LL_ADC_REG_SetSequencerRanks()".
<>	139:856d2700e60b	2313	* - For devices with sequencer not fully configurable
<>	139:856d2700e60b	2314	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	139:856d2700e60b	2315	* sequencer length and each rank affectation to a channel
<>	139:856d2700e60b	2316	* are defined by channel number.
<>	139:856d2700e60b	2317	* This function retrieves:
<>	139:856d2700e60b	2318	* - Sequence length: Number of ranks in the scan sequence is
<>	139:856d2700e60b	2319	* defined by number of channels set in the sequence,
<>	139:856d2700e60b	2320	* rank of each channel is fixed by channel HW number.
<>	139:856d2700e60b	2321	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	139:856d2700e60b	2322	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2323	* scan direction is forward (from lowest channel number to
<>	139:856d2700e60b	2324	* highest channel number).
<>	139:856d2700e60b	2325	* Sequencer ranks are selected using
<>	139:856d2700e60b	2326	* function "LL_ADC_REG_SetSequencerChannels()".
<>	139:856d2700e60b	2327	* @note On this STM32 serie, group regular sequencer configuration
<>	139:856d2700e60b	2328	* is conditioned to ADC instance sequencer mode.
<>	139:856d2700e60b	2329	* If ADC instance sequencer mode is disabled, sequencers of
<>	139:856d2700e60b	2330	* all groups (group regular, group injected) can be configured
<>	139:856d2700e60b	2331	* but their execution is disabled (limited to rank 1).
<>	139:856d2700e60b	2332	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	139:856d2700e60b	2333	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	139:856d2700e60b	2334	* ADC conversion on only 1 channel.
<>	139:856d2700e60b	2335	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	139:856d2700e60b	2336	* @param ADCx ADC instance
<>	139:856d2700e60b	2337	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2338	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2339	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	139:856d2700e60b	2340	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	139:856d2700e60b	2341	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	139:856d2700e60b	2342	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	139:856d2700e60b	2343	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	139:856d2700e60b	2344	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	139:856d2700e60b	2345	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	139:856d2700e60b	2346	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	139:856d2700e60b	2347	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	139:856d2700e60b	2348	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	139:856d2700e60b	2349	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	139:856d2700e60b	2350	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	139:856d2700e60b	2351	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	139:856d2700e60b	2352	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	139:856d2700e60b	2353	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	139:856d2700e60b	2354	*/
<>	139:856d2700e60b	2355	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2356	{
<>	139:856d2700e60b	2357	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
<>	139:856d2700e60b	2358	}
<>	139:856d2700e60b	2359
<>	139:856d2700e60b	2360	/**
<>	139:856d2700e60b	2361	* @brief Set ADC group regular sequencer discontinuous mode:
<>	139:856d2700e60b	2362	* sequence subdivided and scan conversions interrupted every selected
<>	139:856d2700e60b	2363	* number of ranks.
<>	139:856d2700e60b	2364	* @note It is not possible to enable both ADC group regular
<>	139:856d2700e60b	2365	* continuous mode and sequencer discontinuous mode.
<>	139:856d2700e60b	2366	* @note It is not possible to enable both ADC auto-injected mode
<>	139:856d2700e60b	2367	* and ADC group regular sequencer discontinuous mode.
<>	139:856d2700e60b	2368	* @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
<>	139:856d2700e60b	2369	* CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
<>	139:856d2700e60b	2370	* @param ADCx ADC instance
<>	139:856d2700e60b	2371	* @param SeqDiscont This parameter can be one of the following values:
<>	139:856d2700e60b	2372	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	139:856d2700e60b	2373	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	139:856d2700e60b	2374	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	139:856d2700e60b	2375	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	139:856d2700e60b	2376	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	139:856d2700e60b	2377	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	139:856d2700e60b	2378	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	139:856d2700e60b	2379	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	139:856d2700e60b	2380	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	139:856d2700e60b	2381	* @retval None
<>	139:856d2700e60b	2382	*/
<>	139:856d2700e60b	2383	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	139:856d2700e60b	2384	{
<>	139:856d2700e60b	2385	MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM, SeqDiscont);
<>	139:856d2700e60b	2386	}
<>	139:856d2700e60b	2387
<>	139:856d2700e60b	2388	/**
<>	139:856d2700e60b	2389	* @brief Get ADC group regular sequencer discontinuous mode:
<>	139:856d2700e60b	2390	* sequence subdivided and scan conversions interrupted every selected
<>	139:856d2700e60b	2391	* number of ranks.
<>	139:856d2700e60b	2392	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
<>	139:856d2700e60b	2393	* CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
<>	139:856d2700e60b	2394	* @param ADCx ADC instance
<>	139:856d2700e60b	2395	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2396	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	139:856d2700e60b	2397	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	139:856d2700e60b	2398	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	139:856d2700e60b	2399	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	139:856d2700e60b	2400	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	139:856d2700e60b	2401	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	139:856d2700e60b	2402	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	139:856d2700e60b	2403	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	139:856d2700e60b	2404	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	139:856d2700e60b	2405	*/
<>	139:856d2700e60b	2406	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2407	{
<>	139:856d2700e60b	2408	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM));
<>	139:856d2700e60b	2409	}
<>	139:856d2700e60b	2410
<>	139:856d2700e60b	2411	/**
<>	139:856d2700e60b	2412	* @brief Set ADC group regular sequence: channel on the selected
<>	139:856d2700e60b	2413	* scan sequence rank.
<>	139:856d2700e60b	2414	* @note This function performs configuration of:
<>	139:856d2700e60b	2415	* - Channels ordering into each rank of scan sequence:
<>	139:856d2700e60b	2416	* whatever channel can be placed into whatever rank.
<>	139:856d2700e60b	2417	* @note On this STM32 serie, ADC group regular sequencer is
<>	139:856d2700e60b	2418	* fully configurable: sequencer length and each rank
<>	139:856d2700e60b	2419	* affectation to a channel are configurable.
<>	139:856d2700e60b	2420	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	139:856d2700e60b	2421	* @note Depending on devices and packages, some channels may not be available.
<>	139:856d2700e60b	2422	* Refer to device datasheet for channels availability.
<>	139:856d2700e60b	2423	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	139:856d2700e60b	2424	* TempSensor, ...), measurement paths to internal channels must be
<>	139:856d2700e60b	2425	* enabled separately.
<>	139:856d2700e60b	2426	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	139:856d2700e60b	2427	* @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2428	* SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2429	* SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2430	* SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2431	* SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2432	* SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2433	* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2434	* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2435	* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2436	* SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2437	* SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2438	* SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2439	* SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2440	* SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2441	* SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
<>	139:856d2700e60b	2442	* SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
<>	139:856d2700e60b	2443	* @param ADCx ADC instance
<>	139:856d2700e60b	2444	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	2445	* @arg @ref LL_ADC_REG_RANK_1
<>	139:856d2700e60b	2446	* @arg @ref LL_ADC_REG_RANK_2
<>	139:856d2700e60b	2447	* @arg @ref LL_ADC_REG_RANK_3
<>	139:856d2700e60b	2448	* @arg @ref LL_ADC_REG_RANK_4
<>	139:856d2700e60b	2449	* @arg @ref LL_ADC_REG_RANK_5
<>	139:856d2700e60b	2450	* @arg @ref LL_ADC_REG_RANK_6
<>	139:856d2700e60b	2451	* @arg @ref LL_ADC_REG_RANK_7
<>	139:856d2700e60b	2452	* @arg @ref LL_ADC_REG_RANK_8
<>	139:856d2700e60b	2453	* @arg @ref LL_ADC_REG_RANK_9
<>	139:856d2700e60b	2454	* @arg @ref LL_ADC_REG_RANK_10
<>	139:856d2700e60b	2455	* @arg @ref LL_ADC_REG_RANK_11
<>	139:856d2700e60b	2456	* @arg @ref LL_ADC_REG_RANK_12
<>	139:856d2700e60b	2457	* @arg @ref LL_ADC_REG_RANK_13
<>	139:856d2700e60b	2458	* @arg @ref LL_ADC_REG_RANK_14
<>	139:856d2700e60b	2459	* @arg @ref LL_ADC_REG_RANK_15
<>	139:856d2700e60b	2460	* @arg @ref LL_ADC_REG_RANK_16
<>	139:856d2700e60b	2461	* @param Channel This parameter can be one of the following values:
<>	139:856d2700e60b	2462	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	2463	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	2464	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	2465	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	2466	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	2467	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	2468	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	2469	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	2470	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	2471	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	2472	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	2473	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	2474	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	2475	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	2476	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	2477	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	2478	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	2479	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	2480	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	2481	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	2482	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	2483	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	2484	*
<>	139:856d2700e60b	2485	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	2486	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	2487	* @retval None
<>	139:856d2700e60b	2488	*/
<>	139:856d2700e60b	2489	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	139:856d2700e60b	2490	{
<>	139:856d2700e60b	2491	/* Set bits with content of parameter "Channel" with bits position */
<>	139:856d2700e60b	2492	/* in register and register position depending on parameter "Rank". */
<>	139:856d2700e60b	2493	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	139:856d2700e60b	2494	/* other bits reserved for other purpose. */
<>	139:856d2700e60b	2495	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	139:856d2700e60b	2496
<>	139:856d2700e60b	2497	MODIFY_REG(*preg,
<>	139:856d2700e60b	2498	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
<>	139:856d2700e60b	2499	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
<>	139:856d2700e60b	2500	}
<>	139:856d2700e60b	2501
<>	139:856d2700e60b	2502	/**
<>	139:856d2700e60b	2503	* @brief Get ADC group regular sequence: channel on the selected
<>	139:856d2700e60b	2504	* scan sequence rank.
<>	139:856d2700e60b	2505	* @note On this STM32 serie, ADC group regular sequencer is
<>	139:856d2700e60b	2506	* fully configurable: sequencer length and each rank
<>	139:856d2700e60b	2507	* affectation to a channel are configurable.
<>	139:856d2700e60b	2508	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	139:856d2700e60b	2509	* @note Depending on devices and packages, some channels may not be available.
<>	139:856d2700e60b	2510	* Refer to device datasheet for channels availability.
<>	139:856d2700e60b	2511	* @note Usage of the returned channel number:
<>	139:856d2700e60b	2512	* - To reinject this channel into another function LL_ADC_xxx:
<>	139:856d2700e60b	2513	* the returned channel number is only partly formatted on definition
<>	139:856d2700e60b	2514	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	139:856d2700e60b	2515	* with parts of literals LL_ADC_CHANNEL_x or using
<>	139:856d2700e60b	2516	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	2517	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	139:856d2700e60b	2518	* as parameter for another function.
<>	139:856d2700e60b	2519	* - To get the channel number in decimal format:
<>	139:856d2700e60b	2520	* process the returned value with the helper macro
<>	139:856d2700e60b	2521	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	2522	* @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2523	* SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2524	* SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2525	* SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2526	* SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2527	* SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2528	* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2529	* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2530	* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2531	* SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2532	* SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2533	* SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2534	* SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2535	* SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2536	* SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
<>	139:856d2700e60b	2537	* SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
<>	139:856d2700e60b	2538	* @param ADCx ADC instance
<>	139:856d2700e60b	2539	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	2540	* @arg @ref LL_ADC_REG_RANK_1
<>	139:856d2700e60b	2541	* @arg @ref LL_ADC_REG_RANK_2
<>	139:856d2700e60b	2542	* @arg @ref LL_ADC_REG_RANK_3
<>	139:856d2700e60b	2543	* @arg @ref LL_ADC_REG_RANK_4
<>	139:856d2700e60b	2544	* @arg @ref LL_ADC_REG_RANK_5
<>	139:856d2700e60b	2545	* @arg @ref LL_ADC_REG_RANK_6
<>	139:856d2700e60b	2546	* @arg @ref LL_ADC_REG_RANK_7
<>	139:856d2700e60b	2547	* @arg @ref LL_ADC_REG_RANK_8
<>	139:856d2700e60b	2548	* @arg @ref LL_ADC_REG_RANK_9
<>	139:856d2700e60b	2549	* @arg @ref LL_ADC_REG_RANK_10
<>	139:856d2700e60b	2550	* @arg @ref LL_ADC_REG_RANK_11
<>	139:856d2700e60b	2551	* @arg @ref LL_ADC_REG_RANK_12
<>	139:856d2700e60b	2552	* @arg @ref LL_ADC_REG_RANK_13
<>	139:856d2700e60b	2553	* @arg @ref LL_ADC_REG_RANK_14
<>	139:856d2700e60b	2554	* @arg @ref LL_ADC_REG_RANK_15
<>	139:856d2700e60b	2555	* @arg @ref LL_ADC_REG_RANK_16
<>	139:856d2700e60b	2556	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2557	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	2558	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	2559	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	2560	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	2561	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	2562	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	2563	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	2564	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	2565	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	2566	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	2567	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	2568	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	2569	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	2570	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	2571	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	2572	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	2573	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	2574	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	2575	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	2576	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	2577	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	2578	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	2579	*
<>	139:856d2700e60b	2580	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	2581	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	139:856d2700e60b	2582	* (1) For ADC channel read back from ADC register,
<>	139:856d2700e60b	2583	* comparison with internal channel parameter to be done
<>	139:856d2700e60b	2584	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	139:856d2700e60b	2585	*/
<>	139:856d2700e60b	2586	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	2587	{
<>	139:856d2700e60b	2588	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	139:856d2700e60b	2589
<>	139:856d2700e60b	2590	return (uint32_t) (READ_BIT(*preg,
<>	139:856d2700e60b	2591	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<>	139:856d2700e60b	2592	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
<>	139:856d2700e60b	2593	);
<>	139:856d2700e60b	2594	}
<>	139:856d2700e60b	2595
<>	139:856d2700e60b	2596	/**
<>	139:856d2700e60b	2597	* @brief Set ADC continuous conversion mode on ADC group regular.
<>	139:856d2700e60b	2598	* @note Description of ADC continuous conversion mode:
<>	139:856d2700e60b	2599	* - single mode: one conversion per trigger
<>	139:856d2700e60b	2600	* - continuous mode: after the first trigger, following
<>	139:856d2700e60b	2601	* conversions launched successively automatically.
<>	139:856d2700e60b	2602	* @note It is not possible to enable both ADC group regular
<>	139:856d2700e60b	2603	* continuous mode and sequencer discontinuous mode.
<>	139:856d2700e60b	2604	* @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
<>	139:856d2700e60b	2605	* @param ADCx ADC instance
<>	139:856d2700e60b	2606	* @param Continuous This parameter can be one of the following values:
<>	139:856d2700e60b	2607	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	139:856d2700e60b	2608	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	139:856d2700e60b	2609	* @retval None
<>	139:856d2700e60b	2610	*/
<>	139:856d2700e60b	2611	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<>	139:856d2700e60b	2612	{
<>	139:856d2700e60b	2613	MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
<>	139:856d2700e60b	2614	}
<>	139:856d2700e60b	2615
<>	139:856d2700e60b	2616	/**
<>	139:856d2700e60b	2617	* @brief Get ADC continuous conversion mode on ADC group regular.
<>	139:856d2700e60b	2618	* @note Description of ADC continuous conversion mode:
<>	139:856d2700e60b	2619	* - single mode: one conversion per trigger
<>	139:856d2700e60b	2620	* - continuous mode: after the first trigger, following
<>	139:856d2700e60b	2621	* conversions launched successively automatically.
<>	139:856d2700e60b	2622	* @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
<>	139:856d2700e60b	2623	* @param ADCx ADC instance
<>	139:856d2700e60b	2624	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2625	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	139:856d2700e60b	2626	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	139:856d2700e60b	2627	*/
<>	139:856d2700e60b	2628	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2629	{
<>	139:856d2700e60b	2630	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
<>	139:856d2700e60b	2631	}
<>	139:856d2700e60b	2632
<>	139:856d2700e60b	2633	/**
<>	139:856d2700e60b	2634	* @brief Set ADC group regular conversion data transfer: no transfer or
<>	139:856d2700e60b	2635	* transfer by DMA, and DMA requests mode.
<>	139:856d2700e60b	2636	* @note If transfer by DMA selected, specifies the DMA requests
<>	139:856d2700e60b	2637	* mode:
<>	139:856d2700e60b	2638	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	139:856d2700e60b	2639	* when number of DMA data transfers (number of
<>	139:856d2700e60b	2640	* ADC conversions) is reached.
<>	139:856d2700e60b	2641	* This ADC mode is intended to be used with DMA mode non-circular.
<>	139:856d2700e60b	2642	* - Unlimited mode: DMA transfer requests are unlimited,
<>	139:856d2700e60b	2643	* whatever number of DMA data transfers (number of
<>	139:856d2700e60b	2644	* ADC conversions).
<>	139:856d2700e60b	2645	* This ADC mode is intended to be used with DMA mode circular.
<>	139:856d2700e60b	2646	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	139:856d2700e60b	2647	* mode non-circular:
<>	139:856d2700e60b	2648	* when DMA transfers size will be reached, DMA will stop transfers of
<>	139:856d2700e60b	2649	* ADC conversions data ADC will raise an overrun error
<>	139:856d2700e60b	2650	* (overrun flag and interruption if enabled).
<>	139:856d2700e60b	2651	* @note For devices with several ADC instances: ADC multimode DMA
<>	139:856d2700e60b	2652	* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
<>	139:856d2700e60b	2653	* @note To configure DMA source address (peripheral address),
<>	139:856d2700e60b	2654	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	139:856d2700e60b	2655	* @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
<>	139:856d2700e60b	2656	* CR2 DDS LL_ADC_REG_SetDMATransfer
<>	139:856d2700e60b	2657	* @param ADCx ADC instance
<>	139:856d2700e60b	2658	* @param DMATransfer This parameter can be one of the following values:
<>	139:856d2700e60b	2659	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	139:856d2700e60b	2660	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	139:856d2700e60b	2661	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	139:856d2700e60b	2662	* @retval None
<>	139:856d2700e60b	2663	*/
<>	139:856d2700e60b	2664	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<>	139:856d2700e60b	2665	{
<>	139:856d2700e60b	2666	MODIFY_REG(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS, DMATransfer);
<>	139:856d2700e60b	2667	}
<>	139:856d2700e60b	2668
<>	139:856d2700e60b	2669	/**
<>	139:856d2700e60b	2670	* @brief Get ADC group regular conversion data transfer: no transfer or
<>	139:856d2700e60b	2671	* transfer by DMA, and DMA requests mode.
<>	139:856d2700e60b	2672	* @note If transfer by DMA selected, specifies the DMA requests
<>	139:856d2700e60b	2673	* mode:
<>	139:856d2700e60b	2674	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	139:856d2700e60b	2675	* when number of DMA data transfers (number of
<>	139:856d2700e60b	2676	* ADC conversions) is reached.
<>	139:856d2700e60b	2677	* This ADC mode is intended to be used with DMA mode non-circular.
<>	139:856d2700e60b	2678	* - Unlimited mode: DMA transfer requests are unlimited,
<>	139:856d2700e60b	2679	* whatever number of DMA data transfers (number of
<>	139:856d2700e60b	2680	* ADC conversions).
<>	139:856d2700e60b	2681	* This ADC mode is intended to be used with DMA mode circular.
<>	139:856d2700e60b	2682	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	139:856d2700e60b	2683	* mode non-circular:
<>	139:856d2700e60b	2684	* when DMA transfers size will be reached, DMA will stop transfers of
<>	139:856d2700e60b	2685	* ADC conversions data ADC will raise an overrun error
<>	139:856d2700e60b	2686	* (overrun flag and interruption if enabled).
<>	139:856d2700e60b	2687	* @note For devices with several ADC instances: ADC multimode DMA
<>	139:856d2700e60b	2688	* settings are available using function @ref LL_ADC_GetMultiDMATransfer().
<>	139:856d2700e60b	2689	* @note To configure DMA source address (peripheral address),
<>	139:856d2700e60b	2690	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	139:856d2700e60b	2691	* @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
<>	139:856d2700e60b	2692	* CR2 DDS LL_ADC_REG_GetDMATransfer
<>	139:856d2700e60b	2693	* @param ADCx ADC instance
<>	139:856d2700e60b	2694	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2695	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	139:856d2700e60b	2696	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	139:856d2700e60b	2697	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	139:856d2700e60b	2698	*/
<>	139:856d2700e60b	2699	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2700	{
<>	139:856d2700e60b	2701	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS));
<>	139:856d2700e60b	2702	}
<>	139:856d2700e60b	2703
<>	139:856d2700e60b	2704	/**
<>	139:856d2700e60b	2705	* @brief Specify which ADC flag between EOC (end of unitary conversion)
<>	139:856d2700e60b	2706	* or EOS (end of sequence conversions) is used to indicate
<>	139:856d2700e60b	2707	* the end of conversion.
<>	139:856d2700e60b	2708	* @note This feature is aimed to be set when using ADC with
<>	139:856d2700e60b	2709	* programming model by polling or interruption
<>	139:856d2700e60b	2710	* (programming model by DMA usually uses DMA interruptions
<>	139:856d2700e60b	2711	* to indicate end of conversion and data transfer).
<>	139:856d2700e60b	2712	* @note For ADC group injected, end of conversion (flag&IT) is raised
<>	139:856d2700e60b	2713	* only at the end of the sequence.
<>	139:856d2700e60b	2714	* @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
<>	139:856d2700e60b	2715	* @param ADCx ADC instance
<>	139:856d2700e60b	2716	* @param EocSelection This parameter can be one of the following values:
<>	139:856d2700e60b	2717	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	139:856d2700e60b	2718	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	139:856d2700e60b	2719	* @retval None
<>	139:856d2700e60b	2720	*/
<>	139:856d2700e60b	2721	__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
<>	139:856d2700e60b	2722	{
<>	139:856d2700e60b	2723	MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
<>	139:856d2700e60b	2724	}
<>	139:856d2700e60b	2725
<>	139:856d2700e60b	2726	/**
<>	139:856d2700e60b	2727	* @brief Get which ADC flag between EOC (end of unitary conversion)
<>	139:856d2700e60b	2728	* or EOS (end of sequence conversions) is used to indicate
<>	139:856d2700e60b	2729	* the end of conversion.
<>	139:856d2700e60b	2730	* @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
<>	139:856d2700e60b	2731	* @param ADCx ADC instance
<>	139:856d2700e60b	2732	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2733	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	139:856d2700e60b	2734	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	139:856d2700e60b	2735	*/
<>	139:856d2700e60b	2736	__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2737	{
<>	139:856d2700e60b	2738	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
<>	139:856d2700e60b	2739	}
<>	139:856d2700e60b	2740
<>	139:856d2700e60b	2741	/**
<>	139:856d2700e60b	2742	* @}
<>	139:856d2700e60b	2743	*/
<>	139:856d2700e60b	2744
<>	139:856d2700e60b	2745	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
<>	139:856d2700e60b	2746	* @{
<>	139:856d2700e60b	2747	*/
<>	139:856d2700e60b	2748
<>	139:856d2700e60b	2749	/**
<>	139:856d2700e60b	2750	* @brief Set ADC group injected conversion trigger source:
<>	139:856d2700e60b	2751	* internal (SW start) or from external IP (timer event,
<>	139:856d2700e60b	2752	* external interrupt line).
<>	139:856d2700e60b	2753	* @note On this STM32 serie, setting of external trigger edge is performed
<>	139:856d2700e60b	2754	* using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	139:856d2700e60b	2755	* @note Availability of parameters of trigger sources from timer
<>	139:856d2700e60b	2756	* depends on timers availability on the selected device.
<>	139:856d2700e60b	2757	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
<>	139:856d2700e60b	2758	* CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
<>	139:856d2700e60b	2759	* @param ADCx ADC instance
<>	139:856d2700e60b	2760	* @param TriggerSource This parameter can be one of the following values:
<>	139:856d2700e60b	2761	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	139:856d2700e60b	2762	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	139:856d2700e60b	2763	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	139:856d2700e60b	2764	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	139:856d2700e60b	2765	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	139:856d2700e60b	2766	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	139:856d2700e60b	2767	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	139:856d2700e60b	2768	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	139:856d2700e60b	2769	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	139:856d2700e60b	2770	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	139:856d2700e60b	2771	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	139:856d2700e60b	2772	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	139:856d2700e60b	2773	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
<>	139:856d2700e60b	2774	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	139:856d2700e60b	2775	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	139:856d2700e60b	2776	* @retval None
<>	139:856d2700e60b	2777	*/
<>	139:856d2700e60b	2778	__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	139:856d2700e60b	2779	{
<>	139:856d2700e60b	2780	/* Note: On this STM32 serie, ADC group injected external trigger edge */
<>	139:856d2700e60b	2781	/* is used to perform a ADC conversion start. */
<>	139:856d2700e60b	2782	/* This function does not set external trigger edge. */
<>	139:856d2700e60b	2783	/* This feature is set using function */
<>	139:856d2700e60b	2784	/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
<>	139:856d2700e60b	2785	MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
<>	139:856d2700e60b	2786	}
<>	139:856d2700e60b	2787
<>	139:856d2700e60b	2788	/**
<>	139:856d2700e60b	2789	* @brief Get ADC group injected conversion trigger source:
<>	139:856d2700e60b	2790	* internal (SW start) or from external IP (timer event,
<>	139:856d2700e60b	2791	* external interrupt line).
<>	139:856d2700e60b	2792	* @note To determine whether group injected trigger source is
<>	139:856d2700e60b	2793	* internal (SW start) or external, without detail
<>	139:856d2700e60b	2794	* of which peripheral is selected as external trigger,
<>	139:856d2700e60b	2795	* (equivalent to
<>	139:856d2700e60b	2796	* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
<>	139:856d2700e60b	2797	* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
<>	139:856d2700e60b	2798	* @note Availability of parameters of trigger sources from timer
<>	139:856d2700e60b	2799	* depends on timers availability on the selected device.
<>	139:856d2700e60b	2800	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
<>	139:856d2700e60b	2801	* CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
<>	139:856d2700e60b	2802	* @param ADCx ADC instance
<>	139:856d2700e60b	2803	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2804	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	139:856d2700e60b	2805	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	139:856d2700e60b	2806	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	139:856d2700e60b	2807	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	139:856d2700e60b	2808	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	139:856d2700e60b	2809	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	139:856d2700e60b	2810	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	139:856d2700e60b	2811	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	139:856d2700e60b	2812	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	139:856d2700e60b	2813	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	139:856d2700e60b	2814	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	139:856d2700e60b	2815	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	139:856d2700e60b	2816	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
<>	139:856d2700e60b	2817	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	139:856d2700e60b	2818	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	139:856d2700e60b	2819	*/
<>	139:856d2700e60b	2820	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2821	{
<>	139:856d2700e60b	2822	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL \| ADC_CR2_JEXTEN);
<>	139:856d2700e60b	2823
<>	139:856d2700e60b	2824	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	139:856d2700e60b	2825	/* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
<>	139:856d2700e60b	2826	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	139:856d2700e60b	2827
<>	139:856d2700e60b	2828	/* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
<>	139:856d2700e60b	2829	/* to match with triggers literals definition. */
<>	139:856d2700e60b	2830	return ((TriggerSource
<>	139:856d2700e60b	2831	& (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
<>	139:856d2700e60b	2832	\| ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
<>	139:856d2700e60b	2833	);
<>	139:856d2700e60b	2834	}
<>	139:856d2700e60b	2835
<>	139:856d2700e60b	2836	/**
<>	139:856d2700e60b	2837	* @brief Get ADC group injected conversion trigger source internal (SW start)
<>	139:856d2700e60b	2838	or external
<>	139:856d2700e60b	2839	* @note In case of group injected trigger source set to external trigger,
<>	139:856d2700e60b	2840	* to determine which peripheral is selected as external trigger,
<>	139:856d2700e60b	2841	* use function @ref LL_ADC_INJ_GetTriggerSource.
<>	139:856d2700e60b	2842	* @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
<>	139:856d2700e60b	2843	* @param ADCx ADC instance
<>	139:856d2700e60b	2844	* @retval Value "0" if trigger source external trigger
<>	139:856d2700e60b	2845	* Value "1" if trigger source SW start.
<>	139:856d2700e60b	2846	*/
<>	139:856d2700e60b	2847	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2848	{
<>	139:856d2700e60b	2849	return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
<>	139:856d2700e60b	2850	}
<>	139:856d2700e60b	2851
<>	139:856d2700e60b	2852	/**
<>	139:856d2700e60b	2853	* @brief Get ADC group injected conversion trigger polarity.
<>	139:856d2700e60b	2854	* Applicable only for trigger source set to external trigger.
<>	139:856d2700e60b	2855	* @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
<>	139:856d2700e60b	2856	* @param ADCx ADC instance
<>	139:856d2700e60b	2857	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2858	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	139:856d2700e60b	2859	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	139:856d2700e60b	2860	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	139:856d2700e60b	2861	*/
<>	139:856d2700e60b	2862	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2863	{
<>	139:856d2700e60b	2864	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
<>	139:856d2700e60b	2865	}
<>	139:856d2700e60b	2866
<>	139:856d2700e60b	2867	/**
<>	139:856d2700e60b	2868	* @brief Set ADC group injected sequencer length and scan direction.
<>	139:856d2700e60b	2869	* @note This function performs configuration of:
<>	139:856d2700e60b	2870	* - Sequence length: Number of ranks in the scan sequence.
<>	139:856d2700e60b	2871	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2872	* scan direction is forward (from rank 1 to rank n).
<>	139:856d2700e60b	2873	* @note On this STM32 serie, group injected sequencer configuration
<>	139:856d2700e60b	2874	* is conditioned to ADC instance sequencer mode.
<>	139:856d2700e60b	2875	* If ADC instance sequencer mode is disabled, sequencers of
<>	139:856d2700e60b	2876	* all groups (group regular, group injected) can be configured
<>	139:856d2700e60b	2877	* but their execution is disabled (limited to rank 1).
<>	139:856d2700e60b	2878	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	139:856d2700e60b	2879	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	139:856d2700e60b	2880	* ADC conversion on only 1 channel.
<>	139:856d2700e60b	2881	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
<>	139:856d2700e60b	2882	* @param ADCx ADC instance
<>	139:856d2700e60b	2883	* @param SequencerNbRanks This parameter can be one of the following values:
<>	139:856d2700e60b	2884	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2885	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	139:856d2700e60b	2886	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	139:856d2700e60b	2887	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	139:856d2700e60b	2888	* @retval None
<>	139:856d2700e60b	2889	*/
<>	139:856d2700e60b	2890	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	139:856d2700e60b	2891	{
<>	139:856d2700e60b	2892	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
<>	139:856d2700e60b	2893	}
<>	139:856d2700e60b	2894
<>	139:856d2700e60b	2895	/**
<>	139:856d2700e60b	2896	* @brief Get ADC group injected sequencer length and scan direction.
<>	139:856d2700e60b	2897	* @note This function retrieves:
<>	139:856d2700e60b	2898	* - Sequence length: Number of ranks in the scan sequence.
<>	139:856d2700e60b	2899	* - Sequence direction: Unless specified in parameters, sequencer
<>	139:856d2700e60b	2900	* scan direction is forward (from rank 1 to rank n).
<>	139:856d2700e60b	2901	* @note On this STM32 serie, group injected sequencer configuration
<>	139:856d2700e60b	2902	* is conditioned to ADC instance sequencer mode.
<>	139:856d2700e60b	2903	* If ADC instance sequencer mode is disabled, sequencers of
<>	139:856d2700e60b	2904	* all groups (group regular, group injected) can be configured
<>	139:856d2700e60b	2905	* but their execution is disabled (limited to rank 1).
<>	139:856d2700e60b	2906	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	139:856d2700e60b	2907	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	139:856d2700e60b	2908	* ADC conversion on only 1 channel.
<>	139:856d2700e60b	2909	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
<>	139:856d2700e60b	2910	* @param ADCx ADC instance
<>	139:856d2700e60b	2911	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2912	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	139:856d2700e60b	2913	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	139:856d2700e60b	2914	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	139:856d2700e60b	2915	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	139:856d2700e60b	2916	*/
<>	139:856d2700e60b	2917	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2918	{
<>	139:856d2700e60b	2919	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
<>	139:856d2700e60b	2920	}
<>	139:856d2700e60b	2921
<>	139:856d2700e60b	2922	/**
<>	139:856d2700e60b	2923	* @brief Set ADC group injected sequencer discontinuous mode:
<>	139:856d2700e60b	2924	* sequence subdivided and scan conversions interrupted every selected
<>	139:856d2700e60b	2925	* number of ranks.
<>	139:856d2700e60b	2926	* @note It is not possible to enable both ADC group injected
<>	139:856d2700e60b	2927	* auto-injected mode and sequencer discontinuous mode.
<>	139:856d2700e60b	2928	* @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
<>	139:856d2700e60b	2929	* @param ADCx ADC instance
<>	139:856d2700e60b	2930	* @param SeqDiscont This parameter can be one of the following values:
<>	139:856d2700e60b	2931	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	139:856d2700e60b	2932	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	139:856d2700e60b	2933	* @retval None
<>	139:856d2700e60b	2934	*/
<>	139:856d2700e60b	2935	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	139:856d2700e60b	2936	{
<>	139:856d2700e60b	2937	MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
<>	139:856d2700e60b	2938	}
<>	139:856d2700e60b	2939
<>	139:856d2700e60b	2940	/**
<>	139:856d2700e60b	2941	* @brief Get ADC group injected sequencer discontinuous mode:
<>	139:856d2700e60b	2942	* sequence subdivided and scan conversions interrupted every selected
<>	139:856d2700e60b	2943	* number of ranks.
<>	139:856d2700e60b	2944	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
<>	139:856d2700e60b	2945	* @param ADCx ADC instance
<>	139:856d2700e60b	2946	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	2947	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	139:856d2700e60b	2948	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	139:856d2700e60b	2949	*/
<>	139:856d2700e60b	2950	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	2951	{
<>	139:856d2700e60b	2952	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
<>	139:856d2700e60b	2953	}
<>	139:856d2700e60b	2954
<>	139:856d2700e60b	2955	/**
<>	139:856d2700e60b	2956	* @brief Set ADC group injected sequence: channel on the selected
<>	139:856d2700e60b	2957	* sequence rank.
<>	139:856d2700e60b	2958	* @note Depending on devices and packages, some channels may not be available.
<>	139:856d2700e60b	2959	* Refer to device datasheet for channels availability.
<>	139:856d2700e60b	2960	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	139:856d2700e60b	2961	* TempSensor, ...), measurement paths to internal channels must be
<>	139:856d2700e60b	2962	* enabled separately.
<>	139:856d2700e60b	2963	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	139:856d2700e60b	2964	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	2965	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	2966	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	2967	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	139:856d2700e60b	2968	* @param ADCx ADC instance
<>	139:856d2700e60b	2969	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	2970	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	2971	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	2972	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	2973	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	2974	* @param Channel This parameter can be one of the following values:
<>	139:856d2700e60b	2975	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	2976	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	2977	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	2978	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	2979	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	2980	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	2981	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	2982	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	2983	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	2984	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	2985	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	2986	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	2987	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	2988	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	2989	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	2990	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	2991	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	2992	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	2993	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	2994	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	2995	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	2996	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	2997	*
<>	139:856d2700e60b	2998	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	2999	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	3000	* @retval None
<>	139:856d2700e60b	3001	*/
<>	139:856d2700e60b	3002	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	139:856d2700e60b	3003	{
<>	139:856d2700e60b	3004	/* Set bits with content of parameter "Channel" with bits position */
<>	139:856d2700e60b	3005	/* in register depending on parameter "Rank". */
<>	139:856d2700e60b	3006	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	139:856d2700e60b	3007	/* other bits reserved for other purpose. */
<>	139:856d2700e60b	3008	MODIFY_REG(ADCx->JSQR,
<>	139:856d2700e60b	3009	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
<>	139:856d2700e60b	3010	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
<>	139:856d2700e60b	3011	}
<>	139:856d2700e60b	3012
<>	139:856d2700e60b	3013	/**
<>	139:856d2700e60b	3014	* @brief Get ADC group injected sequence: channel on the selected
<>	139:856d2700e60b	3015	* sequence rank.
<>	139:856d2700e60b	3016	* @note Depending on devices and packages, some channels may not be available.
<>	139:856d2700e60b	3017	* Refer to device datasheet for channels availability.
<>	139:856d2700e60b	3018	* @note Usage of the returned channel number:
<>	139:856d2700e60b	3019	* - To reinject this channel into another function LL_ADC_xxx:
<>	139:856d2700e60b	3020	* the returned channel number is only partly formatted on definition
<>	139:856d2700e60b	3021	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	139:856d2700e60b	3022	* with parts of literals LL_ADC_CHANNEL_x or using
<>	139:856d2700e60b	3023	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	3024	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	139:856d2700e60b	3025	* as parameter for another function.
<>	139:856d2700e60b	3026	* - To get the channel number in decimal format:
<>	139:856d2700e60b	3027	* process the returned value with the helper macro
<>	139:856d2700e60b	3028	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	3029	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	3030	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	3031	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	139:856d2700e60b	3032	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	139:856d2700e60b	3033	* @param ADCx ADC instance
<>	139:856d2700e60b	3034	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	3035	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	3036	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	3037	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	3038	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	3039	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3040	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	3041	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	3042	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	3043	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	3044	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	3045	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	3046	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	3047	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	3048	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	3049	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	3050	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	3051	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	3052	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	3053	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	3054	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	3055	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	3056	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	3057	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	3058	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	3059	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	3060	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	3061	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	3062	*
<>	139:856d2700e60b	3063	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	3064	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	139:856d2700e60b	3065	* (1) For ADC channel read back from ADC register,
<>	139:856d2700e60b	3066	* comparison with internal channel parameter to be done
<>	139:856d2700e60b	3067	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	139:856d2700e60b	3068	*/
<>	139:856d2700e60b	3069	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	3070	{
<>	139:856d2700e60b	3071	return (uint32_t)(READ_BIT(ADCx->JSQR,
<>	139:856d2700e60b	3072	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
<>	139:856d2700e60b	3073	>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
<>	139:856d2700e60b	3074	);
<>	139:856d2700e60b	3075	}
<>	139:856d2700e60b	3076
<>	139:856d2700e60b	3077	/**
<>	139:856d2700e60b	3078	* @brief Set ADC group injected conversion trigger:
<>	139:856d2700e60b	3079	* independent or from ADC group regular.
<>	139:856d2700e60b	3080	* @note This mode can be used to extend number of data registers
<>	139:856d2700e60b	3081	* updated after one ADC conversion trigger and with data
<>	139:856d2700e60b	3082	* permanently kept (not erased by successive conversions of scan of
<>	139:856d2700e60b	3083	* ADC sequencer ranks), up to 5 data registers:
<>	139:856d2700e60b	3084	* 1 data register on ADC group regular, 4 data registers
<>	139:856d2700e60b	3085	* on ADC group injected.
<>	139:856d2700e60b	3086	* @note If ADC group injected injected trigger source is set to an
<>	139:856d2700e60b	3087	* external trigger, this feature must be must be set to
<>	139:856d2700e60b	3088	* independent trigger.
<>	139:856d2700e60b	3089	* ADC group injected automatic trigger is compliant only with
<>	139:856d2700e60b	3090	* group injected trigger source set to SW start, without any
<>	139:856d2700e60b	3091	* further action on ADC group injected conversion start or stop:
<>	139:856d2700e60b	3092	* in this case, ADC group injected is controlled only
<>	139:856d2700e60b	3093	* from ADC group regular.
<>	139:856d2700e60b	3094	* @note It is not possible to enable both ADC group injected
<>	139:856d2700e60b	3095	* auto-injected mode and sequencer discontinuous mode.
<>	139:856d2700e60b	3096	* @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
<>	139:856d2700e60b	3097	* @param ADCx ADC instance
<>	139:856d2700e60b	3098	* @param TrigAuto This parameter can be one of the following values:
<>	139:856d2700e60b	3099	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	139:856d2700e60b	3100	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	139:856d2700e60b	3101	* @retval None
<>	139:856d2700e60b	3102	*/
<>	139:856d2700e60b	3103	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
<>	139:856d2700e60b	3104	{
<>	139:856d2700e60b	3105	MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
<>	139:856d2700e60b	3106	}
<>	139:856d2700e60b	3107
<>	139:856d2700e60b	3108	/**
<>	139:856d2700e60b	3109	* @brief Get ADC group injected conversion trigger:
<>	139:856d2700e60b	3110	* independent or from ADC group regular.
<>	139:856d2700e60b	3111	* @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
<>	139:856d2700e60b	3112	* @param ADCx ADC instance
<>	139:856d2700e60b	3113	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3114	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	139:856d2700e60b	3115	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	139:856d2700e60b	3116	*/
<>	139:856d2700e60b	3117	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3118	{
<>	139:856d2700e60b	3119	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
<>	139:856d2700e60b	3120	}
<>	139:856d2700e60b	3121
<>	139:856d2700e60b	3122	/**
<>	139:856d2700e60b	3123	* @brief Set ADC group injected offset.
<>	139:856d2700e60b	3124	* @note It sets:
<>	139:856d2700e60b	3125	* - ADC group injected rank to which the offset programmed
<>	139:856d2700e60b	3126	* will be applied
<>	139:856d2700e60b	3127	* - Offset level (offset to be subtracted from the raw
<>	139:856d2700e60b	3128	* converted data).
<>	139:856d2700e60b	3129	* Caution: Offset format is dependent to ADC resolution:
<>	139:856d2700e60b	3130	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	139:856d2700e60b	3131	* are set to 0.
<>	139:856d2700e60b	3132	* @note Offset cannot be enabled or disabled.
<>	139:856d2700e60b	3133	* To emulate offset disabled, set an offset value equal to 0.
<>	139:856d2700e60b	3134	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
<>	139:856d2700e60b	3135	* JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
<>	139:856d2700e60b	3136	* JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
<>	139:856d2700e60b	3137	* JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
<>	139:856d2700e60b	3138	* @param ADCx ADC instance
<>	139:856d2700e60b	3139	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	3140	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	3141	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	3142	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	3143	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	3144	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	3145	* @retval None
<>	139:856d2700e60b	3146	*/
<>	139:856d2700e60b	3147	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
<>	139:856d2700e60b	3148	{
<>	139:856d2700e60b	3149	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	139:856d2700e60b	3150
<>	139:856d2700e60b	3151	MODIFY_REG(*preg,
<>	139:856d2700e60b	3152	ADC_JOFR1_JOFFSET1,
<>	139:856d2700e60b	3153	OffsetLevel);
<>	139:856d2700e60b	3154	}
<>	139:856d2700e60b	3155
<>	139:856d2700e60b	3156	/**
<>	139:856d2700e60b	3157	* @brief Get ADC group injected offset.
<>	139:856d2700e60b	3158	* @note It gives offset level (offset to be subtracted from the raw converted data).
<>	139:856d2700e60b	3159	* Caution: Offset format is dependent to ADC resolution:
<>	139:856d2700e60b	3160	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	139:856d2700e60b	3161	* are set to 0.
<>	139:856d2700e60b	3162	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
<>	139:856d2700e60b	3163	* JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
<>	139:856d2700e60b	3164	* JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
<>	139:856d2700e60b	3165	* JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
<>	139:856d2700e60b	3166	* @param ADCx ADC instance
<>	139:856d2700e60b	3167	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	3168	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	3169	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	3170	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	3171	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	3172	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	3173	*/
<>	139:856d2700e60b	3174	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	3175	{
<>	139:856d2700e60b	3176	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	139:856d2700e60b	3177
<>	139:856d2700e60b	3178	return (uint32_t)(READ_BIT(*preg,
<>	139:856d2700e60b	3179	ADC_JOFR1_JOFFSET1)
<>	139:856d2700e60b	3180	);
<>	139:856d2700e60b	3181	}
<>	139:856d2700e60b	3182
<>	139:856d2700e60b	3183	/**
<>	139:856d2700e60b	3184	* @}
<>	139:856d2700e60b	3185	*/
<>	139:856d2700e60b	3186
<>	139:856d2700e60b	3187	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
<>	139:856d2700e60b	3188	* @{
<>	139:856d2700e60b	3189	*/
<>	139:856d2700e60b	3190
<>	139:856d2700e60b	3191	/**
<>	139:856d2700e60b	3192	* @brief Set sampling time of the selected ADC channel
<>	139:856d2700e60b	3193	* Unit: ADC clock cycles.
<>	139:856d2700e60b	3194	* @note On this device, sampling time is on channel scope: independently
<>	139:856d2700e60b	3195	* of channel mapped on ADC group regular or injected.
<>	139:856d2700e60b	3196	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
<>	139:856d2700e60b	3197	* converted:
<>	139:856d2700e60b	3198	* sampling time constraints must be respected (sampling time can be
<>	139:856d2700e60b	3199	* adjusted in function of ADC clock frequency and sampling time
<>	139:856d2700e60b	3200	* setting).
<>	139:856d2700e60b	3201	* Refer to device datasheet for timings values (parameters TS_vrefint,
<>	139:856d2700e60b	3202	* TS_temp, ...).
<>	139:856d2700e60b	3203	* @note Conversion time is the addition of sampling time and processing time.
<>	139:856d2700e60b	3204	* Refer to reference manual for ADC processing time of
<>	139:856d2700e60b	3205	* this STM32 serie.
<>	139:856d2700e60b	3206	* @note In case of ADC conversion of internal channel (VrefInt,
<>	139:856d2700e60b	3207	* temperature sensor, ...), a sampling time minimum value
<>	139:856d2700e60b	3208	* is required.
<>	139:856d2700e60b	3209	* Refer to device datasheet.
<>	139:856d2700e60b	3210	* @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3211	* SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3212	* SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3213	* SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3214	* SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3215	* SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3216	* SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3217	* SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3218	* SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3219	* SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3220	* SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3221	* SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3222	* SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3223	* SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3224	* SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3225	* SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3226	* SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3227	* SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
<>	139:856d2700e60b	3228	* SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
<>	139:856d2700e60b	3229	* @param ADCx ADC instance
<>	139:856d2700e60b	3230	* @param Channel This parameter can be one of the following values:
<>	139:856d2700e60b	3231	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	3232	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	3233	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	3234	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	3235	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	3236	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	3237	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	3238	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	3239	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	3240	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	3241	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	3242	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	3243	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	3244	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	3245	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	3246	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	3247	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	3248	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	3249	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	3250	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	3251	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	3252	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	3253	*
<>	139:856d2700e60b	3254	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	3255	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	3256	* @param SamplingTime This parameter can be one of the following values:
<>	139:856d2700e60b	3257	* @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
<>	139:856d2700e60b	3258	* @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
<>	139:856d2700e60b	3259	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
<>	139:856d2700e60b	3260	* @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
<>	139:856d2700e60b	3261	* @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
<>	139:856d2700e60b	3262	* @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
<>	139:856d2700e60b	3263	* @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
<>	139:856d2700e60b	3264	* @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
<>	139:856d2700e60b	3265	* @retval None
<>	139:856d2700e60b	3266	*/
<>	139:856d2700e60b	3267	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
<>	139:856d2700e60b	3268	{
<>	139:856d2700e60b	3269	/* Set bits with content of parameter "SamplingTime" with bits position */
<>	139:856d2700e60b	3270	/* in register and register position depending on parameter "Channel". */
<>	139:856d2700e60b	3271	/* Parameter "Channel" is used with masks because containing */
<>	139:856d2700e60b	3272	/* other bits reserved for other purpose. */
<>	139:856d2700e60b	3273	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	139:856d2700e60b	3274
<>	139:856d2700e60b	3275	MODIFY_REG(*preg,
<>	139:856d2700e60b	3276	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
<>	139:856d2700e60b	3277	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
<>	139:856d2700e60b	3278	}
<>	139:856d2700e60b	3279
<>	139:856d2700e60b	3280	/**
<>	139:856d2700e60b	3281	* @brief Get sampling time of the selected ADC channel
<>	139:856d2700e60b	3282	* Unit: ADC clock cycles.
<>	139:856d2700e60b	3283	* @note On this device, sampling time is on channel scope: independently
<>	139:856d2700e60b	3284	* of channel mapped on ADC group regular or injected.
<>	139:856d2700e60b	3285	* @note Conversion time is the addition of sampling time and processing time.
<>	139:856d2700e60b	3286	* Refer to reference manual for ADC processing time of
<>	139:856d2700e60b	3287	* this STM32 serie.
<>	139:856d2700e60b	3288	* @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3289	* SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3290	* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3291	* SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3292	* SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3293	* SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3294	* SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3295	* SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3296	* SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3297	* SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3298	* SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3299	* SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3300	* SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3301	* SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3302	* SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3303	* SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3304	* SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3305	* SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
<>	139:856d2700e60b	3306	* SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
<>	139:856d2700e60b	3307	* @param ADCx ADC instance
<>	139:856d2700e60b	3308	* @param Channel This parameter can be one of the following values:
<>	139:856d2700e60b	3309	* @arg @ref LL_ADC_CHANNEL_0
<>	139:856d2700e60b	3310	* @arg @ref LL_ADC_CHANNEL_1
<>	139:856d2700e60b	3311	* @arg @ref LL_ADC_CHANNEL_2
<>	139:856d2700e60b	3312	* @arg @ref LL_ADC_CHANNEL_3
<>	139:856d2700e60b	3313	* @arg @ref LL_ADC_CHANNEL_4
<>	139:856d2700e60b	3314	* @arg @ref LL_ADC_CHANNEL_5
<>	139:856d2700e60b	3315	* @arg @ref LL_ADC_CHANNEL_6
<>	139:856d2700e60b	3316	* @arg @ref LL_ADC_CHANNEL_7
<>	139:856d2700e60b	3317	* @arg @ref LL_ADC_CHANNEL_8
<>	139:856d2700e60b	3318	* @arg @ref LL_ADC_CHANNEL_9
<>	139:856d2700e60b	3319	* @arg @ref LL_ADC_CHANNEL_10
<>	139:856d2700e60b	3320	* @arg @ref LL_ADC_CHANNEL_11
<>	139:856d2700e60b	3321	* @arg @ref LL_ADC_CHANNEL_12
<>	139:856d2700e60b	3322	* @arg @ref LL_ADC_CHANNEL_13
<>	139:856d2700e60b	3323	* @arg @ref LL_ADC_CHANNEL_14
<>	139:856d2700e60b	3324	* @arg @ref LL_ADC_CHANNEL_15
<>	139:856d2700e60b	3325	* @arg @ref LL_ADC_CHANNEL_16
<>	139:856d2700e60b	3326	* @arg @ref LL_ADC_CHANNEL_17
<>	139:856d2700e60b	3327	* @arg @ref LL_ADC_CHANNEL_18
<>	139:856d2700e60b	3328	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	139:856d2700e60b	3329	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	139:856d2700e60b	3330	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	139:856d2700e60b	3331	*
<>	139:856d2700e60b	3332	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	3333	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	3334	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3335	* @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
<>	139:856d2700e60b	3336	* @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
<>	139:856d2700e60b	3337	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
<>	139:856d2700e60b	3338	* @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
<>	139:856d2700e60b	3339	* @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
<>	139:856d2700e60b	3340	* @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
<>	139:856d2700e60b	3341	* @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
<>	139:856d2700e60b	3342	* @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
<>	139:856d2700e60b	3343	*/
<>	139:856d2700e60b	3344	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
<>	139:856d2700e60b	3345	{
<>	139:856d2700e60b	3346	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	139:856d2700e60b	3347
<>	139:856d2700e60b	3348	return (uint32_t)(READ_BIT(*preg,
<>	139:856d2700e60b	3349	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
<>	139:856d2700e60b	3350	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
<>	139:856d2700e60b	3351	);
<>	139:856d2700e60b	3352	}
<>	139:856d2700e60b	3353
<>	139:856d2700e60b	3354	/**
<>	139:856d2700e60b	3355	* @}
<>	139:856d2700e60b	3356	*/
<>	139:856d2700e60b	3357
<>	139:856d2700e60b	3358	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<>	139:856d2700e60b	3359	* @{
<>	139:856d2700e60b	3360	*/
<>	139:856d2700e60b	3361
<>	139:856d2700e60b	3362	/**
<>	139:856d2700e60b	3363	* @brief Set ADC analog watchdog monitored channels:
<>	139:856d2700e60b	3364	* a single channel or all channels,
<>	139:856d2700e60b	3365	* on ADC groups regular and-or injected.
<>	139:856d2700e60b	3366	* @note Once monitored channels are selected, analog watchdog
<>	139:856d2700e60b	3367	* is enabled.
<>	139:856d2700e60b	3368	* @note In case of need to define a single channel to monitor
<>	139:856d2700e60b	3369	* with analog watchdog from sequencer channel definition,
<>	139:856d2700e60b	3370	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<>	139:856d2700e60b	3371	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	139:856d2700e60b	3372	* instance:
<>	139:856d2700e60b	3373	* - AWD standard (instance AWD1):
<>	139:856d2700e60b	3374	* - channels monitored: can monitor 1 channel or all channels.
<>	139:856d2700e60b	3375	* - groups monitored: ADC groups regular and-or injected.
<>	139:856d2700e60b	3376	* - resolution: resolution is not limited (corresponds to
<>	139:856d2700e60b	3377	* ADC resolution configured).
<>	139:856d2700e60b	3378	* @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
<>	139:856d2700e60b	3379	* CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
<>	139:856d2700e60b	3380	* CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
<>	139:856d2700e60b	3381	* @param ADCx ADC instance
<>	139:856d2700e60b	3382	* @param AWDChannelGroup This parameter can be one of the following values:
<>	139:856d2700e60b	3383	* @arg @ref LL_ADC_AWD_DISABLE
<>	139:856d2700e60b	3384	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	139:856d2700e60b	3385	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	139:856d2700e60b	3386	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	139:856d2700e60b	3387	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	139:856d2700e60b	3388	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	139:856d2700e60b	3389	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	139:856d2700e60b	3390	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	139:856d2700e60b	3391	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	139:856d2700e60b	3392	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	139:856d2700e60b	3393	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	139:856d2700e60b	3394	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	139:856d2700e60b	3395	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	139:856d2700e60b	3396	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	139:856d2700e60b	3397	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	139:856d2700e60b	3398	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	139:856d2700e60b	3399	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	139:856d2700e60b	3400	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	139:856d2700e60b	3401	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	139:856d2700e60b	3402	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	139:856d2700e60b	3403	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	139:856d2700e60b	3404	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	139:856d2700e60b	3405	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	139:856d2700e60b	3406	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	139:856d2700e60b	3407	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	139:856d2700e60b	3408	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	139:856d2700e60b	3409	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	139:856d2700e60b	3410	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	139:856d2700e60b	3411	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	139:856d2700e60b	3412	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	139:856d2700e60b	3413	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	139:856d2700e60b	3414	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	139:856d2700e60b	3415	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	139:856d2700e60b	3416	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	139:856d2700e60b	3417	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	139:856d2700e60b	3418	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	139:856d2700e60b	3419	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	139:856d2700e60b	3420	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	139:856d2700e60b	3421	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	139:856d2700e60b	3422	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	139:856d2700e60b	3423	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	139:856d2700e60b	3424	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	139:856d2700e60b	3425	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	139:856d2700e60b	3426	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	139:856d2700e60b	3427	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	139:856d2700e60b	3428	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	139:856d2700e60b	3429	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	139:856d2700e60b	3430	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	139:856d2700e60b	3431	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	139:856d2700e60b	3432	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	139:856d2700e60b	3433	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	139:856d2700e60b	3434	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	139:856d2700e60b	3435	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	139:856d2700e60b	3436	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	139:856d2700e60b	3437	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	139:856d2700e60b	3438	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	139:856d2700e60b	3439	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	139:856d2700e60b	3440	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	139:856d2700e60b	3441	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	139:856d2700e60b	3442	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	139:856d2700e60b	3443	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	139:856d2700e60b	3444	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
<>	139:856d2700e60b	3445	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
<>	139:856d2700e60b	3446	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	139:856d2700e60b	3447	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
<>	139:856d2700e60b	3448	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
<>	139:856d2700e60b	3449	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
<>	139:856d2700e60b	3450	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	139:856d2700e60b	3451	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
<>	139:856d2700e60b	3452	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
<>	139:856d2700e60b	3453	*
<>	139:856d2700e60b	3454	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	139:856d2700e60b	3455	* (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	139:856d2700e60b	3456	* @retval None
<>	139:856d2700e60b	3457	*/
<>	139:856d2700e60b	3458	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
<>	139:856d2700e60b	3459	{
<>	139:856d2700e60b	3460	MODIFY_REG(ADCx->CR1,
<>	139:856d2700e60b	3461	(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH),
<>	139:856d2700e60b	3462	AWDChannelGroup);
<>	139:856d2700e60b	3463	}
<>	139:856d2700e60b	3464
<>	139:856d2700e60b	3465	/**
<>	139:856d2700e60b	3466	* @brief Get ADC analog watchdog monitored channel.
<>	139:856d2700e60b	3467	* @note Usage of the returned channel number:
<>	139:856d2700e60b	3468	* - To reinject this channel into another function LL_ADC_xxx:
<>	139:856d2700e60b	3469	* the returned channel number is only partly formatted on definition
<>	139:856d2700e60b	3470	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	139:856d2700e60b	3471	* with parts of literals LL_ADC_CHANNEL_x or using
<>	139:856d2700e60b	3472	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	3473	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	139:856d2700e60b	3474	* as parameter for another function.
<>	139:856d2700e60b	3475	* - To get the channel number in decimal format:
<>	139:856d2700e60b	3476	* process the returned value with the helper macro
<>	139:856d2700e60b	3477	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	139:856d2700e60b	3478	* Applicable only when the analog watchdog is set to monitor
<>	139:856d2700e60b	3479	* one channel.
<>	139:856d2700e60b	3480	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	139:856d2700e60b	3481	* instance:
<>	139:856d2700e60b	3482	* - AWD standard (instance AWD1):
<>	139:856d2700e60b	3483	* - channels monitored: can monitor 1 channel or all channels.
<>	139:856d2700e60b	3484	* - groups monitored: ADC groups regular and-or injected.
<>	139:856d2700e60b	3485	* - resolution: resolution is not limited (corresponds to
<>	139:856d2700e60b	3486	* ADC resolution configured).
<>	139:856d2700e60b	3487	* @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
<>	139:856d2700e60b	3488	* CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
<>	139:856d2700e60b	3489	* CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
<>	139:856d2700e60b	3490	* @param ADCx ADC instance
<>	139:856d2700e60b	3491	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3492	* @arg @ref LL_ADC_AWD_DISABLE
<>	139:856d2700e60b	3493	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	139:856d2700e60b	3494	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	139:856d2700e60b	3495	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	139:856d2700e60b	3496	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	139:856d2700e60b	3497	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	139:856d2700e60b	3498	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	139:856d2700e60b	3499	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	139:856d2700e60b	3500	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	139:856d2700e60b	3501	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	139:856d2700e60b	3502	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	139:856d2700e60b	3503	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	139:856d2700e60b	3504	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	139:856d2700e60b	3505	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	139:856d2700e60b	3506	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	139:856d2700e60b	3507	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	139:856d2700e60b	3508	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	139:856d2700e60b	3509	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	139:856d2700e60b	3510	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	139:856d2700e60b	3511	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	139:856d2700e60b	3512	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	139:856d2700e60b	3513	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	139:856d2700e60b	3514	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	139:856d2700e60b	3515	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	139:856d2700e60b	3516	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	139:856d2700e60b	3517	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	139:856d2700e60b	3518	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	139:856d2700e60b	3519	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	139:856d2700e60b	3520	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	139:856d2700e60b	3521	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	139:856d2700e60b	3522	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	139:856d2700e60b	3523	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	139:856d2700e60b	3524	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	139:856d2700e60b	3525	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	139:856d2700e60b	3526	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	139:856d2700e60b	3527	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	139:856d2700e60b	3528	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	139:856d2700e60b	3529	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	139:856d2700e60b	3530	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	139:856d2700e60b	3531	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	139:856d2700e60b	3532	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	139:856d2700e60b	3533	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	139:856d2700e60b	3534	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	139:856d2700e60b	3535	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	139:856d2700e60b	3536	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	139:856d2700e60b	3537	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	139:856d2700e60b	3538	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	139:856d2700e60b	3539	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	139:856d2700e60b	3540	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	139:856d2700e60b	3541	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	139:856d2700e60b	3542	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	139:856d2700e60b	3543	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	139:856d2700e60b	3544	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	139:856d2700e60b	3545	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	139:856d2700e60b	3546	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	139:856d2700e60b	3547	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	139:856d2700e60b	3548	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	139:856d2700e60b	3549	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	139:856d2700e60b	3550	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	139:856d2700e60b	3551	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	139:856d2700e60b	3552	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	139:856d2700e60b	3553	*/
<>	139:856d2700e60b	3554	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3555	{
<>	139:856d2700e60b	3556	return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH)));
<>	139:856d2700e60b	3557	}
<>	139:856d2700e60b	3558
<>	139:856d2700e60b	3559	/**
<>	139:856d2700e60b	3560	* @brief Set ADC analog watchdog threshold value of threshold
<>	139:856d2700e60b	3561	* high or low.
<>	139:856d2700e60b	3562	* @note In case of ADC resolution different of 12 bits,
<>	139:856d2700e60b	3563	* analog watchdog thresholds data require a specific shift.
<>	139:856d2700e60b	3564	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	139:856d2700e60b	3565	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	139:856d2700e60b	3566	* instance:
<>	139:856d2700e60b	3567	* - AWD standard (instance AWD1):
<>	139:856d2700e60b	3568	* - channels monitored: can monitor 1 channel or all channels.
<>	139:856d2700e60b	3569	* - groups monitored: ADC groups regular and-or injected.
<>	139:856d2700e60b	3570	* - resolution: resolution is not limited (corresponds to
<>	139:856d2700e60b	3571	* ADC resolution configured).
<>	139:856d2700e60b	3572	* @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
<>	139:856d2700e60b	3573	* LTR LT LL_ADC_SetAnalogWDThresholds
<>	139:856d2700e60b	3574	* @param ADCx ADC instance
<>	139:856d2700e60b	3575	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	139:856d2700e60b	3576	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	139:856d2700e60b	3577	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
AnnaBridge	163:e59c8e839560	3578	* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	3579	* @retval None
<>	139:856d2700e60b	3580	*/
<>	139:856d2700e60b	3581	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<>	139:856d2700e60b	3582	{
<>	139:856d2700e60b	3583	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	139:856d2700e60b	3584
<>	139:856d2700e60b	3585	MODIFY_REG(*preg,
<>	139:856d2700e60b	3586	ADC_HTR_HT,
<>	139:856d2700e60b	3587	AWDThresholdValue);
<>	139:856d2700e60b	3588	}
<>	139:856d2700e60b	3589
<>	139:856d2700e60b	3590	/**
<>	139:856d2700e60b	3591	* @brief Get ADC analog watchdog threshold value of threshold high or
<>	139:856d2700e60b	3592	* threshold low.
<>	139:856d2700e60b	3593	* @note In case of ADC resolution different of 12 bits,
<>	139:856d2700e60b	3594	* analog watchdog thresholds data require a specific shift.
<>	139:856d2700e60b	3595	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<>	139:856d2700e60b	3596	* @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
<>	139:856d2700e60b	3597	* LTR LT LL_ADC_GetAnalogWDThresholds
<>	139:856d2700e60b	3598	* @param ADCx ADC instance
<>	139:856d2700e60b	3599	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	139:856d2700e60b	3600	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	139:856d2700e60b	3601	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	139:856d2700e60b	3602	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	3603	*/
<>	139:856d2700e60b	3604	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
<>	139:856d2700e60b	3605	{
<>	139:856d2700e60b	3606	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	139:856d2700e60b	3607
<>	139:856d2700e60b	3608	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
<>	139:856d2700e60b	3609	}
<>	139:856d2700e60b	3610
<>	139:856d2700e60b	3611	/**
<>	139:856d2700e60b	3612	* @}
<>	139:856d2700e60b	3613	*/
<>	139:856d2700e60b	3614
<>	139:856d2700e60b	3615	/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
<>	139:856d2700e60b	3616	* @{
<>	139:856d2700e60b	3617	*/
<>	139:856d2700e60b	3618
<>	139:856d2700e60b	3619	/**
<>	139:856d2700e60b	3620	* @brief Set ADC multimode configuration to operate in independent mode
<>	139:856d2700e60b	3621	* or multimode (for devices with several ADC instances).
<>	139:856d2700e60b	3622	* @note If multimode configuration: the selected ADC instance is
<>	139:856d2700e60b	3623	* either master or slave depending on hardware.
<>	139:856d2700e60b	3624	* Refer to reference manual.
<>	139:856d2700e60b	3625	* @rmtoll CCR MULTI LL_ADC_SetMultimode
<>	139:856d2700e60b	3626	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3627	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3628	* @param Multimode This parameter can be one of the following values:
<>	139:856d2700e60b	3629	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	139:856d2700e60b	3630	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	139:856d2700e60b	3631	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	139:856d2700e60b	3632	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	139:856d2700e60b	3633	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	139:856d2700e60b	3634	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	139:856d2700e60b	3635	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	139:856d2700e60b	3636	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	139:856d2700e60b	3637	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
<>	139:856d2700e60b	3638	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
<>	139:856d2700e60b	3639	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
<>	139:856d2700e60b	3640	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
<>	139:856d2700e60b	3641	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
<>	139:856d2700e60b	3642	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
<>	139:856d2700e60b	3643	* @retval None
<>	139:856d2700e60b	3644	*/
<>	139:856d2700e60b	3645	__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
<>	139:856d2700e60b	3646	{
<>	139:856d2700e60b	3647	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
<>	139:856d2700e60b	3648	}
<>	139:856d2700e60b	3649
<>	139:856d2700e60b	3650	/**
<>	139:856d2700e60b	3651	* @brief Get ADC multimode configuration to operate in independent mode
<>	139:856d2700e60b	3652	* or multimode (for devices with several ADC instances).
<>	139:856d2700e60b	3653	* @note If multimode configuration: the selected ADC instance is
<>	139:856d2700e60b	3654	* either master or slave depending on hardware.
<>	139:856d2700e60b	3655	* Refer to reference manual.
<>	139:856d2700e60b	3656	* @rmtoll CCR MULTI LL_ADC_GetMultimode
<>	139:856d2700e60b	3657	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3658	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3659	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3660	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	139:856d2700e60b	3661	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	139:856d2700e60b	3662	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	139:856d2700e60b	3663	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	139:856d2700e60b	3664	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	139:856d2700e60b	3665	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	139:856d2700e60b	3666	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	139:856d2700e60b	3667	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	139:856d2700e60b	3668	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
<>	139:856d2700e60b	3669	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
<>	139:856d2700e60b	3670	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
<>	139:856d2700e60b	3671	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
<>	139:856d2700e60b	3672	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
<>	139:856d2700e60b	3673	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
<>	139:856d2700e60b	3674	*/
<>	139:856d2700e60b	3675	__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	3676	{
<>	139:856d2700e60b	3677	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
<>	139:856d2700e60b	3678	}
<>	139:856d2700e60b	3679
<>	139:856d2700e60b	3680	/**
<>	139:856d2700e60b	3681	* @brief Set ADC multimode conversion data transfer: no transfer
<>	139:856d2700e60b	3682	* or transfer by DMA.
<>	139:856d2700e60b	3683	* @note If ADC multimode transfer by DMA is not selected:
<>	139:856d2700e60b	3684	* each ADC uses its own DMA channel, with its individual
<>	139:856d2700e60b	3685	* DMA transfer settings.
<>	139:856d2700e60b	3686	* If ADC multimode transfer by DMA is selected:
<>	139:856d2700e60b	3687	* One DMA channel is used for both ADC (DMA of ADC master)
<>	139:856d2700e60b	3688	* Specifies the DMA requests mode:
<>	139:856d2700e60b	3689	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	139:856d2700e60b	3690	* when number of DMA data transfers (number of
<>	139:856d2700e60b	3691	* ADC conversions) is reached.
<>	139:856d2700e60b	3692	* This ADC mode is intended to be used with DMA mode non-circular.
<>	139:856d2700e60b	3693	* - Unlimited mode: DMA transfer requests are unlimited,
<>	139:856d2700e60b	3694	* whatever number of DMA data transfers (number of
<>	139:856d2700e60b	3695	* ADC conversions).
<>	139:856d2700e60b	3696	* This ADC mode is intended to be used with DMA mode circular.
<>	139:856d2700e60b	3697	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	139:856d2700e60b	3698	* mode non-circular:
<>	139:856d2700e60b	3699	* when DMA transfers size will be reached, DMA will stop transfers of
<>	139:856d2700e60b	3700	* ADC conversions data ADC will raise an overrun error
<>	139:856d2700e60b	3701	* (overrun flag and interruption if enabled).
<>	139:856d2700e60b	3702	* @note How to retrieve multimode conversion data:
<>	139:856d2700e60b	3703	* Whatever multimode transfer by DMA setting: using function
<>	139:856d2700e60b	3704	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	139:856d2700e60b	3705	* If ADC multimode transfer by DMA is selected: conversion data
<>	139:856d2700e60b	3706	* is a raw data with ADC master and slave concatenated.
<>	139:856d2700e60b	3707	* A macro is available to get the conversion data of
<>	139:856d2700e60b	3708	* ADC master or ADC slave: see helper macro
<>	139:856d2700e60b	3709	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	139:856d2700e60b	3710	* @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
<>	139:856d2700e60b	3711	* CCR DDS LL_ADC_SetMultiDMATransfer
<>	139:856d2700e60b	3712	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3713	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3714	* @param MultiDMATransfer This parameter can be one of the following values:
<>	139:856d2700e60b	3715	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	139:856d2700e60b	3716	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
<>	139:856d2700e60b	3717	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
<>	139:856d2700e60b	3718	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
<>	139:856d2700e60b	3719	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
<>	139:856d2700e60b	3720	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
<>	139:856d2700e60b	3721	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
<>	139:856d2700e60b	3722	* @retval None
<>	139:856d2700e60b	3723	*/
<>	139:856d2700e60b	3724	__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
<>	139:856d2700e60b	3725	{
<>	139:856d2700e60b	3726	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA \| ADC_CCR_DDS, MultiDMATransfer);
<>	139:856d2700e60b	3727	}
<>	139:856d2700e60b	3728
<>	139:856d2700e60b	3729	/**
<>	139:856d2700e60b	3730	* @brief Get ADC multimode conversion data transfer: no transfer
<>	139:856d2700e60b	3731	* or transfer by DMA.
<>	139:856d2700e60b	3732	* @note If ADC multimode transfer by DMA is not selected:
<>	139:856d2700e60b	3733	* each ADC uses its own DMA channel, with its individual
<>	139:856d2700e60b	3734	* DMA transfer settings.
<>	139:856d2700e60b	3735	* If ADC multimode transfer by DMA is selected:
<>	139:856d2700e60b	3736	* One DMA channel is used for both ADC (DMA of ADC master)
<>	139:856d2700e60b	3737	* Specifies the DMA requests mode:
<>	139:856d2700e60b	3738	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	139:856d2700e60b	3739	* when number of DMA data transfers (number of
<>	139:856d2700e60b	3740	* ADC conversions) is reached.
<>	139:856d2700e60b	3741	* This ADC mode is intended to be used with DMA mode non-circular.
<>	139:856d2700e60b	3742	* - Unlimited mode: DMA transfer requests are unlimited,
<>	139:856d2700e60b	3743	* whatever number of DMA data transfers (number of
<>	139:856d2700e60b	3744	* ADC conversions).
<>	139:856d2700e60b	3745	* This ADC mode is intended to be used with DMA mode circular.
<>	139:856d2700e60b	3746	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	139:856d2700e60b	3747	* mode non-circular:
<>	139:856d2700e60b	3748	* when DMA transfers size will be reached, DMA will stop transfers of
<>	139:856d2700e60b	3749	* ADC conversions data ADC will raise an overrun error
<>	139:856d2700e60b	3750	* (overrun flag and interruption if enabled).
<>	139:856d2700e60b	3751	* @note How to retrieve multimode conversion data:
<>	139:856d2700e60b	3752	* Whatever multimode transfer by DMA setting: using function
<>	139:856d2700e60b	3753	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	139:856d2700e60b	3754	* If ADC multimode transfer by DMA is selected: conversion data
<>	139:856d2700e60b	3755	* is a raw data with ADC master and slave concatenated.
<>	139:856d2700e60b	3756	* A macro is available to get the conversion data of
<>	139:856d2700e60b	3757	* ADC master or ADC slave: see helper macro
<>	139:856d2700e60b	3758	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	139:856d2700e60b	3759	* @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
<>	139:856d2700e60b	3760	* CCR DDS LL_ADC_GetMultiDMATransfer
<>	139:856d2700e60b	3761	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3762	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3763	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3764	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	139:856d2700e60b	3765	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
<>	139:856d2700e60b	3766	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
<>	139:856d2700e60b	3767	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
<>	139:856d2700e60b	3768	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
<>	139:856d2700e60b	3769	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
<>	139:856d2700e60b	3770	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
<>	139:856d2700e60b	3771	*/
<>	139:856d2700e60b	3772	__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	3773	{
<>	139:856d2700e60b	3774	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA \| ADC_CCR_DDS));
<>	139:856d2700e60b	3775	}
<>	139:856d2700e60b	3776
<>	139:856d2700e60b	3777	/**
<>	139:856d2700e60b	3778	* @brief Set ADC multimode delay between 2 sampling phases.
<>	139:856d2700e60b	3779	* @note The sampling delay range depends on ADC resolution:
<>	139:856d2700e60b	3780	* - ADC resolution 12 bits can have maximum delay of 12 cycles.
<>	139:856d2700e60b	3781	* - ADC resolution 10 bits can have maximum delay of 10 cycles.
<>	139:856d2700e60b	3782	* - ADC resolution 8 bits can have maximum delay of 8 cycles.
<>	139:856d2700e60b	3783	* - ADC resolution 6 bits can have maximum delay of 6 cycles.
<>	139:856d2700e60b	3784	* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
<>	139:856d2700e60b	3785	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3786	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3787	* @param MultiTwoSamplingDelay This parameter can be one of the following values:
<>	139:856d2700e60b	3788	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	139:856d2700e60b	3789	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
<>	139:856d2700e60b	3790	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
<>	139:856d2700e60b	3791	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
<>	139:856d2700e60b	3792	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
<>	139:856d2700e60b	3793	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
<>	139:856d2700e60b	3794	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
<>	139:856d2700e60b	3795	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
<>	139:856d2700e60b	3796	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
<>	139:856d2700e60b	3797	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
<>	139:856d2700e60b	3798	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
<>	139:856d2700e60b	3799	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
<>	139:856d2700e60b	3800	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
<>	139:856d2700e60b	3801	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
<>	139:856d2700e60b	3802	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
<>	139:856d2700e60b	3803	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
<>	139:856d2700e60b	3804	* @retval None
<>	139:856d2700e60b	3805	*/
<>	139:856d2700e60b	3806	__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
<>	139:856d2700e60b	3807	{
<>	139:856d2700e60b	3808	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
<>	139:856d2700e60b	3809	}
<>	139:856d2700e60b	3810
<>	139:856d2700e60b	3811	/**
<>	139:856d2700e60b	3812	* @brief Get ADC multimode delay between 2 sampling phases.
<>	139:856d2700e60b	3813	* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
<>	139:856d2700e60b	3814	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	3815	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	3816	* @retval Returned value can be one of the following values:
<>	139:856d2700e60b	3817	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	139:856d2700e60b	3818	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
<>	139:856d2700e60b	3819	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
<>	139:856d2700e60b	3820	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
<>	139:856d2700e60b	3821	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
<>	139:856d2700e60b	3822	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
<>	139:856d2700e60b	3823	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
<>	139:856d2700e60b	3824	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
<>	139:856d2700e60b	3825	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
<>	139:856d2700e60b	3826	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
<>	139:856d2700e60b	3827	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
<>	139:856d2700e60b	3828	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
<>	139:856d2700e60b	3829	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
<>	139:856d2700e60b	3830	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
<>	139:856d2700e60b	3831	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
<>	139:856d2700e60b	3832	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
<>	139:856d2700e60b	3833	*/
<>	139:856d2700e60b	3834	__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	3835	{
<>	139:856d2700e60b	3836	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
<>	139:856d2700e60b	3837	}
<>	139:856d2700e60b	3838
<>	139:856d2700e60b	3839	/**
<>	139:856d2700e60b	3840	* @}
<>	139:856d2700e60b	3841	*/
<>	139:856d2700e60b	3842	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<>	139:856d2700e60b	3843	* @{
<>	139:856d2700e60b	3844	*/
<>	139:856d2700e60b	3845
<>	139:856d2700e60b	3846	/**
<>	139:856d2700e60b	3847	* @brief Enable the selected ADC instance.
<>	139:856d2700e60b	3848	* @note On this STM32 serie, after ADC enable, a delay for
<>	139:856d2700e60b	3849	* ADC internal analog stabilization is required before performing a
<>	139:856d2700e60b	3850	* ADC conversion start.
<>	139:856d2700e60b	3851	* Refer to device datasheet, parameter tSTAB.
<>	139:856d2700e60b	3852	* @rmtoll CR2 ADON LL_ADC_Enable
<>	139:856d2700e60b	3853	* @param ADCx ADC instance
<>	139:856d2700e60b	3854	* @retval None
<>	139:856d2700e60b	3855	*/
<>	139:856d2700e60b	3856	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3857	{
<>	139:856d2700e60b	3858	SET_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	139:856d2700e60b	3859	}
<>	139:856d2700e60b	3860
<>	139:856d2700e60b	3861	/**
<>	139:856d2700e60b	3862	* @brief Disable the selected ADC instance.
<>	139:856d2700e60b	3863	* @rmtoll CR2 ADON LL_ADC_Disable
<>	139:856d2700e60b	3864	* @param ADCx ADC instance
<>	139:856d2700e60b	3865	* @retval None
<>	139:856d2700e60b	3866	*/
<>	139:856d2700e60b	3867	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3868	{
<>	139:856d2700e60b	3869	CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	139:856d2700e60b	3870	}
<>	139:856d2700e60b	3871
<>	139:856d2700e60b	3872	/**
<>	139:856d2700e60b	3873	* @brief Get the selected ADC instance enable state.
<>	139:856d2700e60b	3874	* @rmtoll CR2 ADON LL_ADC_IsEnabled
<>	139:856d2700e60b	3875	* @param ADCx ADC instance
<>	139:856d2700e60b	3876	* @retval 0: ADC is disabled, 1: ADC is enabled.
<>	139:856d2700e60b	3877	*/
<>	139:856d2700e60b	3878	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3879	{
<>	139:856d2700e60b	3880	return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
<>	139:856d2700e60b	3881	}
<>	139:856d2700e60b	3882
<>	139:856d2700e60b	3883	/**
<>	139:856d2700e60b	3884	* @}
<>	139:856d2700e60b	3885	*/
<>	139:856d2700e60b	3886
<>	139:856d2700e60b	3887	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<>	139:856d2700e60b	3888	* @{
<>	139:856d2700e60b	3889	*/
<>	139:856d2700e60b	3890
<>	139:856d2700e60b	3891	/**
<>	139:856d2700e60b	3892	* @brief Start ADC group regular conversion.
<>	139:856d2700e60b	3893	* @note On this STM32 serie, this function is relevant only for
<>	139:856d2700e60b	3894	* internal trigger (SW start), not for external trigger:
<>	139:856d2700e60b	3895	* - If ADC trigger has been set to software start, ADC conversion
<>	139:856d2700e60b	3896	* starts immediately.
<>	139:856d2700e60b	3897	* - If ADC trigger has been set to external trigger, ADC conversion
<>	139:856d2700e60b	3898	* start must be performed using function
<>	139:856d2700e60b	3899	* @ref LL_ADC_REG_StartConversionExtTrig().
<>	139:856d2700e60b	3900	* (if external trigger edge would have been set during ADC other
<>	139:856d2700e60b	3901	* settings, ADC conversion would start at trigger event
<>	139:856d2700e60b	3902	* as soon as ADC is enabled).
<>	139:856d2700e60b	3903	* @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
<>	139:856d2700e60b	3904	* @param ADCx ADC instance
<>	139:856d2700e60b	3905	* @retval None
<>	139:856d2700e60b	3906	*/
<>	139:856d2700e60b	3907	__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3908	{
<>	139:856d2700e60b	3909	SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
<>	139:856d2700e60b	3910	}
<>	139:856d2700e60b	3911
<>	139:856d2700e60b	3912	/**
<>	139:856d2700e60b	3913	* @brief Start ADC group regular conversion from external trigger.
<>	139:856d2700e60b	3914	* @note ADC conversion will start at next trigger event (on the selected
<>	139:856d2700e60b	3915	* trigger edge) following the ADC start conversion command.
<>	139:856d2700e60b	3916	* @note On this STM32 serie, this function is relevant for
<>	139:856d2700e60b	3917	* ADC conversion start from external trigger.
<>	139:856d2700e60b	3918	* If internal trigger (SW start) is needed, perform ADC conversion
<>	139:856d2700e60b	3919	* start using function @ref LL_ADC_REG_StartConversionSWStart().
<>	139:856d2700e60b	3920	* @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
<>	139:856d2700e60b	3921	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	139:856d2700e60b	3922	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	139:856d2700e60b	3923	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	139:856d2700e60b	3924	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	139:856d2700e60b	3925	* @param ADCx ADC instance
<>	139:856d2700e60b	3926	* @retval None
<>	139:856d2700e60b	3927	*/
<>	139:856d2700e60b	3928	__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	139:856d2700e60b	3929	{
<>	139:856d2700e60b	3930	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	139:856d2700e60b	3931	}
<>	139:856d2700e60b	3932
<>	139:856d2700e60b	3933	/**
<>	139:856d2700e60b	3934	* @brief Stop ADC group regular conversion from external trigger.
<>	139:856d2700e60b	3935	* @note No more ADC conversion will start at next trigger event
<>	139:856d2700e60b	3936	* following the ADC stop conversion command.
<>	139:856d2700e60b	3937	* If a conversion is on-going, it will be completed.
<>	139:856d2700e60b	3938	* @note On this STM32 serie, there is no specific command
<>	139:856d2700e60b	3939	* to stop a conversion on-going or to stop ADC converting
<>	139:856d2700e60b	3940	* in continuous mode. These actions can be performed
<>	139:856d2700e60b	3941	* using function @ref LL_ADC_Disable().
<>	139:856d2700e60b	3942	* @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
<>	139:856d2700e60b	3943	* @param ADCx ADC instance
<>	139:856d2700e60b	3944	* @retval None
<>	139:856d2700e60b	3945	*/
<>	139:856d2700e60b	3946	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3947	{
<>	139:856d2700e60b	3948	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
<>	139:856d2700e60b	3949	}
<>	139:856d2700e60b	3950
<>	139:856d2700e60b	3951	/**
<>	139:856d2700e60b	3952	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	3953	* all ADC configurations: all ADC resolutions and
<>	139:856d2700e60b	3954	* all oversampling increased data width (for devices
<>	139:856d2700e60b	3955	* with feature oversampling).
<>	139:856d2700e60b	3956	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
<>	139:856d2700e60b	3957	* @param ADCx ADC instance
<>	139:856d2700e60b	3958	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	139:856d2700e60b	3959	*/
<>	139:856d2700e60b	3960	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3961	{
<>	139:856d2700e60b	3962	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	139:856d2700e60b	3963	}
<>	139:856d2700e60b	3964
<>	139:856d2700e60b	3965	/**
<>	139:856d2700e60b	3966	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	3967	* ADC resolution 12 bits.
<>	139:856d2700e60b	3968	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	3969	* can increase data width, function for extended range
<>	139:856d2700e60b	3970	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	139:856d2700e60b	3971	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
<>	139:856d2700e60b	3972	* @param ADCx ADC instance
<>	139:856d2700e60b	3973	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	3974	*/
<>	139:856d2700e60b	3975	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3976	{
<>	139:856d2700e60b	3977	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	139:856d2700e60b	3978	}
<>	139:856d2700e60b	3979
<>	139:856d2700e60b	3980	/**
<>	139:856d2700e60b	3981	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	3982	* ADC resolution 10 bits.
<>	139:856d2700e60b	3983	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	3984	* can increase data width, function for extended range
<>	139:856d2700e60b	3985	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	139:856d2700e60b	3986	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
<>	139:856d2700e60b	3987	* @param ADCx ADC instance
<>	139:856d2700e60b	3988	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	139:856d2700e60b	3989	*/
<>	139:856d2700e60b	3990	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	3991	{
<>	139:856d2700e60b	3992	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	139:856d2700e60b	3993	}
<>	139:856d2700e60b	3994
<>	139:856d2700e60b	3995	/**
<>	139:856d2700e60b	3996	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	3997	* ADC resolution 8 bits.
<>	139:856d2700e60b	3998	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	3999	* can increase data width, function for extended range
<>	139:856d2700e60b	4000	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	139:856d2700e60b	4001	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
<>	139:856d2700e60b	4002	* @param ADCx ADC instance
<>	139:856d2700e60b	4003	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	139:856d2700e60b	4004	*/
<>	139:856d2700e60b	4005	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4006	{
<>	139:856d2700e60b	4007	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	139:856d2700e60b	4008	}
<>	139:856d2700e60b	4009
<>	139:856d2700e60b	4010	/**
<>	139:856d2700e60b	4011	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	4012	* ADC resolution 6 bits.
<>	139:856d2700e60b	4013	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	4014	* can increase data width, function for extended range
<>	139:856d2700e60b	4015	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	139:856d2700e60b	4016	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
<>	139:856d2700e60b	4017	* @param ADCx ADC instance
<>	139:856d2700e60b	4018	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	139:856d2700e60b	4019	*/
<>	139:856d2700e60b	4020	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4021	{
<>	139:856d2700e60b	4022	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	139:856d2700e60b	4023	}
<>	139:856d2700e60b	4024
<>	139:856d2700e60b	4025	/**
<>	139:856d2700e60b	4026	* @brief Get ADC multimode conversion data of ADC master, ADC slave
<>	139:856d2700e60b	4027	* or raw data with ADC master and slave concatenated.
<>	139:856d2700e60b	4028	* @note If raw data with ADC master and slave concatenated is retrieved,
<>	139:856d2700e60b	4029	* a macro is available to get the conversion data of
<>	139:856d2700e60b	4030	* ADC master or ADC slave: see helper macro
<>	139:856d2700e60b	4031	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	139:856d2700e60b	4032	* (however this macro is mainly intended for multimode
<>	139:856d2700e60b	4033	* transfer by DMA, because this function can do the same
<>	139:856d2700e60b	4034	* by getting multimode conversion data of ADC master or ADC slave
<>	139:856d2700e60b	4035	* separately).
<>	139:856d2700e60b	4036	* @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
<>	139:856d2700e60b	4037	* CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
<>	139:856d2700e60b	4038	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4039	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4040	* @param ConversionData This parameter can be one of the following values:
<>	139:856d2700e60b	4041	* @arg @ref LL_ADC_MULTI_MASTER
<>	139:856d2700e60b	4042	* @arg @ref LL_ADC_MULTI_SLAVE
<>	139:856d2700e60b	4043	* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
<>	139:856d2700e60b	4044	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	139:856d2700e60b	4045	*/
<>	139:856d2700e60b	4046	__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
<>	139:856d2700e60b	4047	{
<>	139:856d2700e60b	4048	return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
<>	139:856d2700e60b	4049	ADC_DR_ADC2DATA)
<>	139:856d2700e60b	4050	>> POSITION_VAL(ConversionData)
<>	139:856d2700e60b	4051	);
<>	139:856d2700e60b	4052	}
<>	139:856d2700e60b	4053
<>	139:856d2700e60b	4054	/**
<>	139:856d2700e60b	4055	* @}
<>	139:856d2700e60b	4056	*/
<>	139:856d2700e60b	4057
<>	139:856d2700e60b	4058	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
<>	139:856d2700e60b	4059	* @{
<>	139:856d2700e60b	4060	*/
<>	139:856d2700e60b	4061
<>	139:856d2700e60b	4062	/**
<>	139:856d2700e60b	4063	* @brief Start ADC group injected conversion.
<>	139:856d2700e60b	4064	* @note On this STM32 serie, this function is relevant only for
<>	139:856d2700e60b	4065	* internal trigger (SW start), not for external trigger:
<>	139:856d2700e60b	4066	* - If ADC trigger has been set to software start, ADC conversion
<>	139:856d2700e60b	4067	* starts immediately.
<>	139:856d2700e60b	4068	* - If ADC trigger has been set to external trigger, ADC conversion
<>	139:856d2700e60b	4069	* start must be performed using function
<>	139:856d2700e60b	4070	* @ref LL_ADC_INJ_StartConversionExtTrig().
<>	139:856d2700e60b	4071	* (if external trigger edge would have been set during ADC other
<>	139:856d2700e60b	4072	* settings, ADC conversion would start at trigger event
<>	139:856d2700e60b	4073	* as soon as ADC is enabled).
<>	139:856d2700e60b	4074	* @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
<>	139:856d2700e60b	4075	* @param ADCx ADC instance
<>	139:856d2700e60b	4076	* @retval None
<>	139:856d2700e60b	4077	*/
<>	139:856d2700e60b	4078	__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4079	{
<>	139:856d2700e60b	4080	SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
<>	139:856d2700e60b	4081	}
<>	139:856d2700e60b	4082
<>	139:856d2700e60b	4083	/**
<>	139:856d2700e60b	4084	* @brief Start ADC group injected conversion from external trigger.
<>	139:856d2700e60b	4085	* @note ADC conversion will start at next trigger event (on the selected
<>	139:856d2700e60b	4086	* trigger edge) following the ADC start conversion command.
<>	139:856d2700e60b	4087	* @note On this STM32 serie, this function is relevant for
<>	139:856d2700e60b	4088	* ADC conversion start from external trigger.
<>	139:856d2700e60b	4089	* If internal trigger (SW start) is needed, perform ADC conversion
<>	139:856d2700e60b	4090	* start using function @ref LL_ADC_INJ_StartConversionSWStart().
<>	139:856d2700e60b	4091	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
<>	139:856d2700e60b	4092	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	139:856d2700e60b	4093	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	139:856d2700e60b	4094	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	139:856d2700e60b	4095	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	139:856d2700e60b	4096	* @param ADCx ADC instance
<>	139:856d2700e60b	4097	* @retval None
<>	139:856d2700e60b	4098	*/
<>	139:856d2700e60b	4099	__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	139:856d2700e60b	4100	{
<>	139:856d2700e60b	4101	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	139:856d2700e60b	4102	}
<>	139:856d2700e60b	4103
<>	139:856d2700e60b	4104	/**
<>	139:856d2700e60b	4105	* @brief Stop ADC group injected conversion from external trigger.
<>	139:856d2700e60b	4106	* @note No more ADC conversion will start at next trigger event
<>	139:856d2700e60b	4107	* following the ADC stop conversion command.
<>	139:856d2700e60b	4108	* If a conversion is on-going, it will be completed.
<>	139:856d2700e60b	4109	* @note On this STM32 serie, there is no specific command
<>	139:856d2700e60b	4110	* to stop a conversion on-going or to stop ADC converting
<>	139:856d2700e60b	4111	* in continuous mode. These actions can be performed
<>	139:856d2700e60b	4112	* using function @ref LL_ADC_Disable().
<>	139:856d2700e60b	4113	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
<>	139:856d2700e60b	4114	* @param ADCx ADC instance
<>	139:856d2700e60b	4115	* @retval None
<>	139:856d2700e60b	4116	*/
<>	139:856d2700e60b	4117	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4118	{
<>	139:856d2700e60b	4119	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
<>	139:856d2700e60b	4120	}
<>	139:856d2700e60b	4121
<>	139:856d2700e60b	4122	/**
<>	139:856d2700e60b	4123	* @brief Get ADC group regular conversion data, range fit for
<>	139:856d2700e60b	4124	* all ADC configurations: all ADC resolutions and
<>	139:856d2700e60b	4125	* all oversampling increased data width (for devices
<>	139:856d2700e60b	4126	* with feature oversampling).
<>	139:856d2700e60b	4127	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	139:856d2700e60b	4128	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	139:856d2700e60b	4129	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	139:856d2700e60b	4130	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
<>	139:856d2700e60b	4131	* @param ADCx ADC instance
<>	139:856d2700e60b	4132	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	4133	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	4134	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	4135	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	4136	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	4137	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	139:856d2700e60b	4138	*/
<>	139:856d2700e60b	4139	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	4140	{
<>	139:856d2700e60b	4141	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	139:856d2700e60b	4142
<>	139:856d2700e60b	4143	return (uint32_t)(READ_BIT(*preg,
<>	139:856d2700e60b	4144	ADC_JDR1_JDATA)
<>	139:856d2700e60b	4145	);
<>	139:856d2700e60b	4146	}
<>	139:856d2700e60b	4147
<>	139:856d2700e60b	4148	/**
<>	139:856d2700e60b	4149	* @brief Get ADC group injected conversion data, range fit for
<>	139:856d2700e60b	4150	* ADC resolution 12 bits.
<>	139:856d2700e60b	4151	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	4152	* can increase data width, function for extended range
<>	139:856d2700e60b	4153	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	139:856d2700e60b	4154	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	139:856d2700e60b	4155	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	139:856d2700e60b	4156	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	139:856d2700e60b	4157	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
<>	139:856d2700e60b	4158	* @param ADCx ADC instance
<>	139:856d2700e60b	4159	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	4160	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	4161	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	4162	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	4163	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	4164	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	139:856d2700e60b	4165	*/
<>	139:856d2700e60b	4166	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	4167	{
<>	139:856d2700e60b	4168	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	139:856d2700e60b	4169
<>	139:856d2700e60b	4170	return (uint16_t)(READ_BIT(*preg,
<>	139:856d2700e60b	4171	ADC_JDR1_JDATA)
<>	139:856d2700e60b	4172	);
<>	139:856d2700e60b	4173	}
<>	139:856d2700e60b	4174
<>	139:856d2700e60b	4175	/**
<>	139:856d2700e60b	4176	* @brief Get ADC group injected conversion data, range fit for
<>	139:856d2700e60b	4177	* ADC resolution 10 bits.
<>	139:856d2700e60b	4178	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	4179	* can increase data width, function for extended range
<>	139:856d2700e60b	4180	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	139:856d2700e60b	4181	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	139:856d2700e60b	4182	* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	139:856d2700e60b	4183	* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	139:856d2700e60b	4184	* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
<>	139:856d2700e60b	4185	* @param ADCx ADC instance
<>	139:856d2700e60b	4186	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	4187	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	4188	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	4189	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	4190	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	4191	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	139:856d2700e60b	4192	*/
<>	139:856d2700e60b	4193	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	4194	{
<>	139:856d2700e60b	4195	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	139:856d2700e60b	4196
<>	139:856d2700e60b	4197	return (uint16_t)(READ_BIT(*preg,
<>	139:856d2700e60b	4198	ADC_JDR1_JDATA)
<>	139:856d2700e60b	4199	);
<>	139:856d2700e60b	4200	}
<>	139:856d2700e60b	4201
<>	139:856d2700e60b	4202	/**
<>	139:856d2700e60b	4203	* @brief Get ADC group injected conversion data, range fit for
<>	139:856d2700e60b	4204	* ADC resolution 8 bits.
<>	139:856d2700e60b	4205	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	4206	* can increase data width, function for extended range
<>	139:856d2700e60b	4207	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	139:856d2700e60b	4208	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	139:856d2700e60b	4209	* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	139:856d2700e60b	4210	* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	139:856d2700e60b	4211	* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
<>	139:856d2700e60b	4212	* @param ADCx ADC instance
<>	139:856d2700e60b	4213	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	4214	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	4215	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	4216	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	4217	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	4218	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	139:856d2700e60b	4219	*/
<>	139:856d2700e60b	4220	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	4221	{
<>	139:856d2700e60b	4222	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	139:856d2700e60b	4223
<>	139:856d2700e60b	4224	return (uint8_t)(READ_BIT(*preg,
<>	139:856d2700e60b	4225	ADC_JDR1_JDATA)
<>	139:856d2700e60b	4226	);
<>	139:856d2700e60b	4227	}
<>	139:856d2700e60b	4228
<>	139:856d2700e60b	4229	/**
<>	139:856d2700e60b	4230	* @brief Get ADC group injected conversion data, range fit for
<>	139:856d2700e60b	4231	* ADC resolution 6 bits.
<>	139:856d2700e60b	4232	* @note For devices with feature oversampling: Oversampling
<>	139:856d2700e60b	4233	* can increase data width, function for extended range
<>	139:856d2700e60b	4234	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	139:856d2700e60b	4235	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	139:856d2700e60b	4236	* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	139:856d2700e60b	4237	* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	139:856d2700e60b	4238	* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
<>	139:856d2700e60b	4239	* @param ADCx ADC instance
<>	139:856d2700e60b	4240	* @param Rank This parameter can be one of the following values:
<>	139:856d2700e60b	4241	* @arg @ref LL_ADC_INJ_RANK_1
<>	139:856d2700e60b	4242	* @arg @ref LL_ADC_INJ_RANK_2
<>	139:856d2700e60b	4243	* @arg @ref LL_ADC_INJ_RANK_3
<>	139:856d2700e60b	4244	* @arg @ref LL_ADC_INJ_RANK_4
<>	139:856d2700e60b	4245	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	139:856d2700e60b	4246	*/
<>	139:856d2700e60b	4247	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
<>	139:856d2700e60b	4248	{
<>	139:856d2700e60b	4249	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	139:856d2700e60b	4250
<>	139:856d2700e60b	4251	return (uint8_t)(READ_BIT(*preg,
<>	139:856d2700e60b	4252	ADC_JDR1_JDATA)
<>	139:856d2700e60b	4253	);
<>	139:856d2700e60b	4254	}
<>	139:856d2700e60b	4255
<>	139:856d2700e60b	4256	/**
<>	139:856d2700e60b	4257	* @}
<>	139:856d2700e60b	4258	*/
<>	139:856d2700e60b	4259
<>	139:856d2700e60b	4260	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<>	139:856d2700e60b	4261	* @{
<>	139:856d2700e60b	4262	*/
<>	139:856d2700e60b	4263
<>	139:856d2700e60b	4264	/**
<>	139:856d2700e60b	4265	* @brief Get flag ADC group regular end of unitary conversion
<>	139:856d2700e60b	4266	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4267	* ADC configuration.
<>	139:856d2700e60b	4268	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4269	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4270	* @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
<>	139:856d2700e60b	4271	* @param ADCx ADC instance
<>	139:856d2700e60b	4272	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4273	*/
<>	139:856d2700e60b	4274	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4275	{
<>	139:856d2700e60b	4276	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
<>	139:856d2700e60b	4277	}
<>	139:856d2700e60b	4278
<>	139:856d2700e60b	4279	/**
<>	139:856d2700e60b	4280	* @brief Get flag ADC group regular overrun.
<>	139:856d2700e60b	4281	* @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
<>	139:856d2700e60b	4282	* @param ADCx ADC instance
<>	139:856d2700e60b	4283	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4284	*/
<>	139:856d2700e60b	4285	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4286	{
<>	139:856d2700e60b	4287	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<>	139:856d2700e60b	4288	}
<>	139:856d2700e60b	4289
<>	139:856d2700e60b	4290
<>	139:856d2700e60b	4291	/**
<>	139:856d2700e60b	4292	* @brief Get flag ADC group injected end of sequence conversions.
<>	139:856d2700e60b	4293	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
<>	139:856d2700e60b	4294	* @param ADCx ADC instance
<>	139:856d2700e60b	4295	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4296	*/
<>	139:856d2700e60b	4297	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4298	{
<>	139:856d2700e60b	4299	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4300	/* end of unitary conversion. */
<>	139:856d2700e60b	4301	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4302	/* in other STM32 families). */
<>	139:856d2700e60b	4303	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
<>	139:856d2700e60b	4304	}
<>	139:856d2700e60b	4305
<>	139:856d2700e60b	4306	/**
<>	139:856d2700e60b	4307	* @brief Get flag ADC analog watchdog 1 flag
<>	139:856d2700e60b	4308	* @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
<>	139:856d2700e60b	4309	* @param ADCx ADC instance
<>	139:856d2700e60b	4310	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4311	*/
<>	139:856d2700e60b	4312	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4313	{
<>	139:856d2700e60b	4314	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<>	139:856d2700e60b	4315	}
<>	139:856d2700e60b	4316
<>	139:856d2700e60b	4317	/**
<>	139:856d2700e60b	4318	* @brief Clear flag ADC group regular end of unitary conversion
<>	139:856d2700e60b	4319	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4320	* ADC configuration.
<>	139:856d2700e60b	4321	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4322	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4323	* @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
<>	139:856d2700e60b	4324	* @param ADCx ADC instance
<>	139:856d2700e60b	4325	* @retval None
<>	139:856d2700e60b	4326	*/
<>	139:856d2700e60b	4327	__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4328	{
<>	139:856d2700e60b	4329	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
<>	139:856d2700e60b	4330	}
<>	139:856d2700e60b	4331
<>	139:856d2700e60b	4332	/**
<>	139:856d2700e60b	4333	* @brief Clear flag ADC group regular overrun.
<>	139:856d2700e60b	4334	* @rmtoll SR OVR LL_ADC_ClearFlag_OVR
<>	139:856d2700e60b	4335	* @param ADCx ADC instance
<>	139:856d2700e60b	4336	* @retval None
<>	139:856d2700e60b	4337	*/
<>	139:856d2700e60b	4338	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4339	{
<>	139:856d2700e60b	4340	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
<>	139:856d2700e60b	4341	}
<>	139:856d2700e60b	4342
<>	139:856d2700e60b	4343
<>	139:856d2700e60b	4344	/**
<>	139:856d2700e60b	4345	* @brief Clear flag ADC group injected end of sequence conversions.
<>	139:856d2700e60b	4346	* @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
<>	139:856d2700e60b	4347	* @param ADCx ADC instance
<>	139:856d2700e60b	4348	* @retval None
<>	139:856d2700e60b	4349	*/
<>	139:856d2700e60b	4350	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4351	{
<>	139:856d2700e60b	4352	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4353	/* end of unitary conversion. */
<>	139:856d2700e60b	4354	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4355	/* in other STM32 families). */
<>	139:856d2700e60b	4356	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
<>	139:856d2700e60b	4357	}
<>	139:856d2700e60b	4358
<>	139:856d2700e60b	4359	/**
<>	139:856d2700e60b	4360	* @brief Clear flag ADC analog watchdog 1.
<>	139:856d2700e60b	4361	* @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
<>	139:856d2700e60b	4362	* @param ADCx ADC instance
<>	139:856d2700e60b	4363	* @retval None
<>	139:856d2700e60b	4364	*/
<>	139:856d2700e60b	4365	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4366	{
<>	139:856d2700e60b	4367	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
<>	139:856d2700e60b	4368	}
<>	139:856d2700e60b	4369
<>	139:856d2700e60b	4370	/**
<>	139:856d2700e60b	4371	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	139:856d2700e60b	4372	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4373	* ADC configuration, of the ADC master.
<>	139:856d2700e60b	4374	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4375	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4376	* @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
<>	139:856d2700e60b	4377	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4378	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4379	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4380	*/
<>	139:856d2700e60b	4381	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4382	{
<>	139:856d2700e60b	4383	return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
<>	139:856d2700e60b	4384	}
<>	139:856d2700e60b	4385
<>	139:856d2700e60b	4386	/**
<>	139:856d2700e60b	4387	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	139:856d2700e60b	4388	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4389	* ADC configuration, of the ADC slave 1.
<>	139:856d2700e60b	4390	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4391	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4392	* @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
<>	139:856d2700e60b	4393	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4394	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4395	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4396	*/
<>	139:856d2700e60b	4397	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4398	{
<>	139:856d2700e60b	4399	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
<>	139:856d2700e60b	4400	}
<>	139:856d2700e60b	4401
<>	139:856d2700e60b	4402	/**
<>	139:856d2700e60b	4403	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	139:856d2700e60b	4404	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4405	* ADC configuration, of the ADC slave 2.
<>	139:856d2700e60b	4406	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4407	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4408	* @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
<>	139:856d2700e60b	4409	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4410	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4411	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4412	*/
<>	139:856d2700e60b	4413	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4414	{
<>	139:856d2700e60b	4415	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
<>	139:856d2700e60b	4416	}
<>	139:856d2700e60b	4417	/**
<>	139:856d2700e60b	4418	* @brief Get flag multimode ADC group regular overrun of the ADC master.
<>	139:856d2700e60b	4419	* @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
<>	139:856d2700e60b	4420	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4421	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4422	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4423	*/
<>	139:856d2700e60b	4424	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4425	{
<>	139:856d2700e60b	4426	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
<>	139:856d2700e60b	4427	}
<>	139:856d2700e60b	4428
<>	139:856d2700e60b	4429	/**
<>	139:856d2700e60b	4430	* @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
<>	139:856d2700e60b	4431	* @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
<>	139:856d2700e60b	4432	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4433	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4434	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4435	*/
<>	139:856d2700e60b	4436	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4437	{
<>	139:856d2700e60b	4438	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
<>	139:856d2700e60b	4439	}
<>	139:856d2700e60b	4440
<>	139:856d2700e60b	4441	/**
<>	139:856d2700e60b	4442	* @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
<>	139:856d2700e60b	4443	* @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
<>	139:856d2700e60b	4444	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4445	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4446	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4447	*/
<>	139:856d2700e60b	4448	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4449	{
<>	139:856d2700e60b	4450	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
<>	139:856d2700e60b	4451	}
<>	139:856d2700e60b	4452
<>	139:856d2700e60b	4453
<>	139:856d2700e60b	4454	/**
<>	139:856d2700e60b	4455	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
<>	139:856d2700e60b	4456	* @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
<>	139:856d2700e60b	4457	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4458	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4459	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4460	*/
<>	139:856d2700e60b	4461	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4462	{
<>	139:856d2700e60b	4463	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4464	/* end of unitary conversion. */
<>	139:856d2700e60b	4465	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4466	/* in other STM32 families). */
<>	139:856d2700e60b	4467	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
<>	139:856d2700e60b	4468	}
<>	139:856d2700e60b	4469
<>	139:856d2700e60b	4470	/**
<>	139:856d2700e60b	4471	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
<>	139:856d2700e60b	4472	* @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
<>	139:856d2700e60b	4473	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4474	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4475	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4476	*/
<>	139:856d2700e60b	4477	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4478	{
<>	139:856d2700e60b	4479	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4480	/* end of unitary conversion. */
<>	139:856d2700e60b	4481	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4482	/* in other STM32 families). */
<>	139:856d2700e60b	4483	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
<>	139:856d2700e60b	4484	}
<>	139:856d2700e60b	4485
<>	139:856d2700e60b	4486	/**
<>	139:856d2700e60b	4487	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
<>	139:856d2700e60b	4488	* @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
<>	139:856d2700e60b	4489	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4490	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4491	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4492	*/
<>	139:856d2700e60b	4493	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4494	{
<>	139:856d2700e60b	4495	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4496	/* end of unitary conversion. */
<>	139:856d2700e60b	4497	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4498	/* in other STM32 families). */
<>	139:856d2700e60b	4499	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
<>	139:856d2700e60b	4500	}
<>	139:856d2700e60b	4501
<>	139:856d2700e60b	4502	/**
<>	139:856d2700e60b	4503	* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
<>	139:856d2700e60b	4504	* @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
<>	139:856d2700e60b	4505	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4506	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4507	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4508	*/
<>	139:856d2700e60b	4509	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4510	{
<>	139:856d2700e60b	4511	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
<>	139:856d2700e60b	4512	}
<>	139:856d2700e60b	4513
<>	139:856d2700e60b	4514	/**
<>	139:856d2700e60b	4515	* @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
<>	139:856d2700e60b	4516	* @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
<>	139:856d2700e60b	4517	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4518	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4519	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4520	*/
<>	139:856d2700e60b	4521	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4522	{
<>	139:856d2700e60b	4523	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
<>	139:856d2700e60b	4524	}
<>	139:856d2700e60b	4525
<>	139:856d2700e60b	4526	/**
<>	139:856d2700e60b	4527	* @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
<>	139:856d2700e60b	4528	* @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
<>	139:856d2700e60b	4529	* @param ADCxy_COMMON ADC common instance
<>	139:856d2700e60b	4530	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	139:856d2700e60b	4531	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4532	*/
<>	139:856d2700e60b	4533	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	139:856d2700e60b	4534	{
<>	139:856d2700e60b	4535	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
<>	139:856d2700e60b	4536	}
<>	139:856d2700e60b	4537
<>	139:856d2700e60b	4538
<>	139:856d2700e60b	4539	/**
<>	139:856d2700e60b	4540	* @}
<>	139:856d2700e60b	4541	*/
<>	139:856d2700e60b	4542
<>	139:856d2700e60b	4543	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
<>	139:856d2700e60b	4544	* @{
<>	139:856d2700e60b	4545	*/
<>	139:856d2700e60b	4546
<>	139:856d2700e60b	4547	/**
<>	139:856d2700e60b	4548	* @brief Enable interruption ADC group regular end of unitary conversion
<>	139:856d2700e60b	4549	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4550	* ADC configuration.
<>	139:856d2700e60b	4551	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4552	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4553	* @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
<>	139:856d2700e60b	4554	* @param ADCx ADC instance
<>	139:856d2700e60b	4555	* @retval None
<>	139:856d2700e60b	4556	*/
<>	139:856d2700e60b	4557	__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4558	{
<>	139:856d2700e60b	4559	SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	139:856d2700e60b	4560	}
<>	139:856d2700e60b	4561
<>	139:856d2700e60b	4562	/**
<>	139:856d2700e60b	4563	* @brief Enable ADC group regular interruption overrun.
<>	139:856d2700e60b	4564	* @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
<>	139:856d2700e60b	4565	* @param ADCx ADC instance
<>	139:856d2700e60b	4566	* @retval None
<>	139:856d2700e60b	4567	*/
<>	139:856d2700e60b	4568	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4569	{
<>	139:856d2700e60b	4570	SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	139:856d2700e60b	4571	}
<>	139:856d2700e60b	4572
<>	139:856d2700e60b	4573
<>	139:856d2700e60b	4574	/**
<>	139:856d2700e60b	4575	* @brief Enable interruption ADC group injected end of sequence conversions.
<>	139:856d2700e60b	4576	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	139:856d2700e60b	4577	* @param ADCx ADC instance
<>	139:856d2700e60b	4578	* @retval None
<>	139:856d2700e60b	4579	*/
<>	139:856d2700e60b	4580	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4581	{
<>	139:856d2700e60b	4582	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4583	/* end of unitary conversion. */
<>	139:856d2700e60b	4584	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4585	/* in other STM32 families). */
<>	139:856d2700e60b	4586	SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	139:856d2700e60b	4587	}
<>	139:856d2700e60b	4588
<>	139:856d2700e60b	4589	/**
<>	139:856d2700e60b	4590	* @brief Enable interruption ADC analog watchdog 1.
<>	139:856d2700e60b	4591	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	139:856d2700e60b	4592	* @param ADCx ADC instance
<>	139:856d2700e60b	4593	* @retval None
<>	139:856d2700e60b	4594	*/
<>	139:856d2700e60b	4595	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4596	{
<>	139:856d2700e60b	4597	SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	139:856d2700e60b	4598	}
<>	139:856d2700e60b	4599
<>	139:856d2700e60b	4600	/**
<>	139:856d2700e60b	4601	* @brief Disable interruption ADC group regular end of unitary conversion
<>	139:856d2700e60b	4602	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4603	* ADC configuration.
<>	139:856d2700e60b	4604	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4605	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4606	* @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
<>	139:856d2700e60b	4607	* @param ADCx ADC instance
<>	139:856d2700e60b	4608	* @retval None
<>	139:856d2700e60b	4609	*/
<>	139:856d2700e60b	4610	__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4611	{
<>	139:856d2700e60b	4612	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	139:856d2700e60b	4613	}
<>	139:856d2700e60b	4614
<>	139:856d2700e60b	4615	/**
<>	139:856d2700e60b	4616	* @brief Disable interruption ADC group regular overrun.
<>	139:856d2700e60b	4617	* @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
<>	139:856d2700e60b	4618	* @param ADCx ADC instance
<>	139:856d2700e60b	4619	* @retval None
<>	139:856d2700e60b	4620	*/
<>	139:856d2700e60b	4621	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4622	{
<>	139:856d2700e60b	4623	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	139:856d2700e60b	4624	}
<>	139:856d2700e60b	4625
<>	139:856d2700e60b	4626
<>	139:856d2700e60b	4627	/**
<>	139:856d2700e60b	4628	* @brief Disable interruption ADC group injected end of sequence conversions.
<>	139:856d2700e60b	4629	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	139:856d2700e60b	4630	* @param ADCx ADC instance
<>	139:856d2700e60b	4631	* @retval None
<>	139:856d2700e60b	4632	*/
<>	139:856d2700e60b	4633	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4634	{
<>	139:856d2700e60b	4635	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4636	/* end of unitary conversion. */
<>	139:856d2700e60b	4637	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4638	/* in other STM32 families). */
<>	139:856d2700e60b	4639	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	139:856d2700e60b	4640	}
<>	139:856d2700e60b	4641
<>	139:856d2700e60b	4642	/**
<>	139:856d2700e60b	4643	* @brief Disable interruption ADC analog watchdog 1.
<>	139:856d2700e60b	4644	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	139:856d2700e60b	4645	* @param ADCx ADC instance
<>	139:856d2700e60b	4646	* @retval None
<>	139:856d2700e60b	4647	*/
<>	139:856d2700e60b	4648	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4649	{
<>	139:856d2700e60b	4650	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	139:856d2700e60b	4651	}
<>	139:856d2700e60b	4652
<>	139:856d2700e60b	4653	/**
<>	139:856d2700e60b	4654	* @brief Get state of interruption ADC group regular end of unitary conversion
<>	139:856d2700e60b	4655	* or end of sequence conversions, depending on
<>	139:856d2700e60b	4656	* ADC configuration.
<>	139:856d2700e60b	4657	* @note To configure flag of end of conversion,
<>	139:856d2700e60b	4658	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	139:856d2700e60b	4659	* (0: interrupt disabled, 1: interrupt enabled)
<>	139:856d2700e60b	4660	* @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
<>	139:856d2700e60b	4661	* @param ADCx ADC instance
<>	139:856d2700e60b	4662	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4663	*/
<>	139:856d2700e60b	4664	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4665	{
<>	139:856d2700e60b	4666	return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
<>	139:856d2700e60b	4667	}
<>	139:856d2700e60b	4668
<>	139:856d2700e60b	4669	/**
<>	139:856d2700e60b	4670	* @brief Get state of interruption ADC group regular overrun
<>	139:856d2700e60b	4671	* (0: interrupt disabled, 1: interrupt enabled).
<>	139:856d2700e60b	4672	* @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
<>	139:856d2700e60b	4673	* @param ADCx ADC instance
<>	139:856d2700e60b	4674	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4675	*/
<>	139:856d2700e60b	4676	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4677	{
<>	139:856d2700e60b	4678	return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<>	139:856d2700e60b	4679	}
<>	139:856d2700e60b	4680
<>	139:856d2700e60b	4681
<>	139:856d2700e60b	4682	/**
<>	139:856d2700e60b	4683	* @brief Get state of interruption ADC group injected end of sequence conversions
<>	139:856d2700e60b	4684	* (0: interrupt disabled, 1: interrupt enabled).
<>	139:856d2700e60b	4685	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	139:856d2700e60b	4686	* @param ADCx ADC instance
<>	139:856d2700e60b	4687	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4688	*/
<>	139:856d2700e60b	4689	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4690	{
<>	139:856d2700e60b	4691	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	139:856d2700e60b	4692	/* end of unitary conversion. */
<>	139:856d2700e60b	4693	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	139:856d2700e60b	4694	/* in other STM32 families). */
<>	139:856d2700e60b	4695	return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
<>	139:856d2700e60b	4696	}
<>	139:856d2700e60b	4697
<>	139:856d2700e60b	4698	/**
<>	139:856d2700e60b	4699	* @brief Get state of interruption ADC analog watchdog 1
<>	139:856d2700e60b	4700	* (0: interrupt disabled, 1: interrupt enabled).
<>	139:856d2700e60b	4701	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	139:856d2700e60b	4702	* @param ADCx ADC instance
<>	139:856d2700e60b	4703	* @retval State of bit (1 or 0).
<>	139:856d2700e60b	4704	*/
<>	139:856d2700e60b	4705	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<>	139:856d2700e60b	4706	{
<>	139:856d2700e60b	4707	return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<>	139:856d2700e60b	4708	}
<>	139:856d2700e60b	4709
<>	139:856d2700e60b	4710	/**
<>	139:856d2700e60b	4711	* @}
<>	139:856d2700e60b	4712	*/
<>	139:856d2700e60b	4713
<>	139:856d2700e60b	4714	#if defined(USE_FULL_LL_DRIVER)
<>	139:856d2700e60b	4715	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<>	139:856d2700e60b	4716	* @{
<>	139:856d2700e60b	4717	*/
<>	139:856d2700e60b	4718
<>	139:856d2700e60b	4719	/* Initialization of some features of ADC common parameters and multimode */
<>	139:856d2700e60b	4720	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<>	139:856d2700e60b	4721	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct);
<>	139:856d2700e60b	4722	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
<>	139:856d2700e60b	4723
<>	139:856d2700e60b	4724	/* De-initialization of ADC instance, ADC group regular and ADC group injected */
<>	139:856d2700e60b	4725	/* (availability of ADC group injected depends on STM32 families) */
<>	139:856d2700e60b	4726	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<>	139:856d2700e60b	4727
<>	139:856d2700e60b	4728	/* Initialization of some features of ADC instance */
<>	139:856d2700e60b	4729	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
<>	139:856d2700e60b	4730	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<>	139:856d2700e60b	4731
<>	139:856d2700e60b	4732	/* Initialization of some features of ADC instance and ADC group regular */
<>	139:856d2700e60b	4733	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
<>	139:856d2700e60b	4734	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<>	139:856d2700e60b	4735
<>	139:856d2700e60b	4736	/* Initialization of some features of ADC instance and ADC group injected */
<>	139:856d2700e60b	4737	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct);
<>	139:856d2700e60b	4738	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
<>	139:856d2700e60b	4739
<>	139:856d2700e60b	4740	/**
<>	139:856d2700e60b	4741	* @}
<>	139:856d2700e60b	4742	*/
<>	139:856d2700e60b	4743	#endif /* USE_FULL_LL_DRIVER */
<>	139:856d2700e60b	4744
<>	139:856d2700e60b	4745	/**
<>	139:856d2700e60b	4746	* @}
<>	139:856d2700e60b	4747	*/
<>	139:856d2700e60b	4748
<>	139:856d2700e60b	4749	/**
<>	139:856d2700e60b	4750	* @}
<>	139:856d2700e60b	4751	*/
<>	139:856d2700e60b	4752
<>	139:856d2700e60b	4753	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
<>	139:856d2700e60b	4754
<>	139:856d2700e60b	4755	/**
<>	139:856d2700e60b	4756	* @}
<>	139:856d2700e60b	4757	*/
<>	139:856d2700e60b	4758
<>	139:856d2700e60b	4759	#ifdef __cplusplus
<>	139:856d2700e60b	4760	}
<>	139:856d2700e60b	4761	#endif
<>	139:856d2700e60b	4762
<>	139:856d2700e60b	4763	#endif /* __STM32F7xx_LL_ADC_H */
<>	139:856d2700e60b	4764
<>	139:856d2700e60b	4765	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/