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TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.h@163:e59c8e839560, 2018-03-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Tue Mar 20 13:30:58 2018 +0000
- Revision:
- 163:e59c8e839560
- Child:
- 168:b9e159c1930a
mbed library. Release version 160
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /** |
| AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_ll_fmc.h |
| AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
| AnnaBridge | 163:e59c8e839560 | 5 | * @version V1.4.0 |
| AnnaBridge | 163:e59c8e839560 | 6 | * @date 16-December-2016 |
| AnnaBridge | 163:e59c8e839560 | 7 | * @brief Header file of FMC HAL module. |
| AnnaBridge | 163:e59c8e839560 | 8 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 9 | * @attention |
| AnnaBridge | 163:e59c8e839560 | 10 | * |
| AnnaBridge | 163:e59c8e839560 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 163:e59c8e839560 | 12 | * |
| AnnaBridge | 163:e59c8e839560 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 163:e59c8e839560 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 163:e59c8e839560 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 163:e59c8e839560 | 22 | * without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 23 | * |
| AnnaBridge | 163:e59c8e839560 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 163:e59c8e839560 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 163:e59c8e839560 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 163:e59c8e839560 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 163:e59c8e839560 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 163:e59c8e839560 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 163:e59c8e839560 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 163:e59c8e839560 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 163:e59c8e839560 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 34 | * |
| AnnaBridge | 163:e59c8e839560 | 35 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 36 | */ |
| AnnaBridge | 163:e59c8e839560 | 37 | |
| AnnaBridge | 163:e59c8e839560 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 39 | #ifndef __STM32F3xx_LL_FMC_H |
| AnnaBridge | 163:e59c8e839560 | 40 | #define __STM32F3xx_LL_FMC_H |
| AnnaBridge | 163:e59c8e839560 | 41 | |
| AnnaBridge | 163:e59c8e839560 | 42 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 43 | extern "C" { |
| AnnaBridge | 163:e59c8e839560 | 44 | #endif |
| AnnaBridge | 163:e59c8e839560 | 45 | |
| AnnaBridge | 163:e59c8e839560 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 47 | #include "stm32f3xx_hal_def.h" |
| AnnaBridge | 163:e59c8e839560 | 48 | |
| AnnaBridge | 163:e59c8e839560 | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
| AnnaBridge | 163:e59c8e839560 | 50 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 51 | */ |
| AnnaBridge | 163:e59c8e839560 | 52 | |
| AnnaBridge | 163:e59c8e839560 | 53 | #if defined(FMC_BANK1) |
| AnnaBridge | 163:e59c8e839560 | 54 | |
| AnnaBridge | 163:e59c8e839560 | 55 | /** @addtogroup FMC_LL |
| AnnaBridge | 163:e59c8e839560 | 56 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 57 | */ |
| AnnaBridge | 163:e59c8e839560 | 58 | |
| AnnaBridge | 163:e59c8e839560 | 59 | /** @addtogroup FMC_LL_Private_Macros |
| AnnaBridge | 163:e59c8e839560 | 60 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 61 | */ |
| AnnaBridge | 163:e59c8e839560 | 62 | |
| AnnaBridge | 163:e59c8e839560 | 63 | #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ |
| AnnaBridge | 163:e59c8e839560 | 64 | ((__BANK__) == FMC_NORSRAM_BANK2) || \ |
| AnnaBridge | 163:e59c8e839560 | 65 | ((__BANK__) == FMC_NORSRAM_BANK3) || \ |
| AnnaBridge | 163:e59c8e839560 | 66 | ((__BANK__) == FMC_NORSRAM_BANK4)) |
| AnnaBridge | 163:e59c8e839560 | 67 | |
| AnnaBridge | 163:e59c8e839560 | 68 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 69 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 70 | |
| AnnaBridge | 163:e59c8e839560 | 71 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
| AnnaBridge | 163:e59c8e839560 | 72 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
| AnnaBridge | 163:e59c8e839560 | 73 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
| AnnaBridge | 163:e59c8e839560 | 74 | |
| AnnaBridge | 163:e59c8e839560 | 75 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| AnnaBridge | 163:e59c8e839560 | 76 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| AnnaBridge | 163:e59c8e839560 | 77 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| AnnaBridge | 163:e59c8e839560 | 78 | |
| AnnaBridge | 163:e59c8e839560 | 79 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 80 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 81 | |
| AnnaBridge | 163:e59c8e839560 | 82 | #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| AnnaBridge | 163:e59c8e839560 | 83 | ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| AnnaBridge | 163:e59c8e839560 | 84 | |
| AnnaBridge | 163:e59c8e839560 | 85 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
| AnnaBridge | 163:e59c8e839560 | 86 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
| AnnaBridge | 163:e59c8e839560 | 87 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
| AnnaBridge | 163:e59c8e839560 | 88 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
| AnnaBridge | 163:e59c8e839560 | 89 | |
| AnnaBridge | 163:e59c8e839560 | 90 | #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \ |
| AnnaBridge | 163:e59c8e839560 | 91 | ((__BANK__) == FMC_NAND_BANK3)) |
| AnnaBridge | 163:e59c8e839560 | 92 | |
| AnnaBridge | 163:e59c8e839560 | 93 | #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 94 | ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 95 | |
| AnnaBridge | 163:e59c8e839560 | 96 | #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| AnnaBridge | 163:e59c8e839560 | 97 | ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| AnnaBridge | 163:e59c8e839560 | 98 | |
| AnnaBridge | 163:e59c8e839560 | 99 | #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 100 | ((__STATE__) == FMC_NAND_ECC_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 101 | |
| AnnaBridge | 163:e59c8e839560 | 102 | #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| AnnaBridge | 163:e59c8e839560 | 103 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| AnnaBridge | 163:e59c8e839560 | 104 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| AnnaBridge | 163:e59c8e839560 | 105 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| AnnaBridge | 163:e59c8e839560 | 106 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| AnnaBridge | 163:e59c8e839560 | 107 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| AnnaBridge | 163:e59c8e839560 | 108 | |
| AnnaBridge | 163:e59c8e839560 | 109 | /** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 110 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 111 | */ |
| AnnaBridge | 163:e59c8e839560 | 112 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 113 | /** |
| AnnaBridge | 163:e59c8e839560 | 114 | * @} |
| AnnaBridge | 163:e59c8e839560 | 115 | */ |
| AnnaBridge | 163:e59c8e839560 | 116 | |
| AnnaBridge | 163:e59c8e839560 | 117 | /** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 118 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 119 | */ |
| AnnaBridge | 163:e59c8e839560 | 120 | #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 121 | /** |
| AnnaBridge | 163:e59c8e839560 | 122 | * @} |
| AnnaBridge | 163:e59c8e839560 | 123 | */ |
| AnnaBridge | 163:e59c8e839560 | 124 | |
| AnnaBridge | 163:e59c8e839560 | 125 | /** @defgroup FMC_Setup_Time FMC_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 126 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 127 | */ |
| AnnaBridge | 163:e59c8e839560 | 128 | #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 129 | /** |
| AnnaBridge | 163:e59c8e839560 | 130 | * @} |
| AnnaBridge | 163:e59c8e839560 | 131 | */ |
| AnnaBridge | 163:e59c8e839560 | 132 | |
| AnnaBridge | 163:e59c8e839560 | 133 | /** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 134 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 135 | */ |
| AnnaBridge | 163:e59c8e839560 | 136 | #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 137 | /** |
| AnnaBridge | 163:e59c8e839560 | 138 | * @} |
| AnnaBridge | 163:e59c8e839560 | 139 | */ |
| AnnaBridge | 163:e59c8e839560 | 140 | |
| AnnaBridge | 163:e59c8e839560 | 141 | /** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 142 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 143 | */ |
| AnnaBridge | 163:e59c8e839560 | 144 | #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 145 | /** |
| AnnaBridge | 163:e59c8e839560 | 146 | * @} |
| AnnaBridge | 163:e59c8e839560 | 147 | */ |
| AnnaBridge | 163:e59c8e839560 | 148 | |
| AnnaBridge | 163:e59c8e839560 | 149 | /** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time |
| AnnaBridge | 163:e59c8e839560 | 150 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 151 | */ |
| AnnaBridge | 163:e59c8e839560 | 152 | #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 163:e59c8e839560 | 153 | /** |
| AnnaBridge | 163:e59c8e839560 | 154 | * @} |
| AnnaBridge | 163:e59c8e839560 | 155 | */ |
| AnnaBridge | 163:e59c8e839560 | 156 | |
| AnnaBridge | 163:e59c8e839560 | 157 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance |
| AnnaBridge | 163:e59c8e839560 | 158 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 159 | */ |
| AnnaBridge | 163:e59c8e839560 | 160 | |
| AnnaBridge | 163:e59c8e839560 | 161 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
| AnnaBridge | 163:e59c8e839560 | 162 | |
| AnnaBridge | 163:e59c8e839560 | 163 | /** |
| AnnaBridge | 163:e59c8e839560 | 164 | * @} |
| AnnaBridge | 163:e59c8e839560 | 165 | */ |
| AnnaBridge | 163:e59c8e839560 | 166 | |
| AnnaBridge | 163:e59c8e839560 | 167 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance |
| AnnaBridge | 163:e59c8e839560 | 168 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 169 | */ |
| AnnaBridge | 163:e59c8e839560 | 170 | |
| AnnaBridge | 163:e59c8e839560 | 171 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
| AnnaBridge | 163:e59c8e839560 | 172 | |
| AnnaBridge | 163:e59c8e839560 | 173 | /** |
| AnnaBridge | 163:e59c8e839560 | 174 | * @} |
| AnnaBridge | 163:e59c8e839560 | 175 | */ |
| AnnaBridge | 163:e59c8e839560 | 176 | |
| AnnaBridge | 163:e59c8e839560 | 177 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
| AnnaBridge | 163:e59c8e839560 | 178 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 179 | */ |
| AnnaBridge | 163:e59c8e839560 | 180 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
| AnnaBridge | 163:e59c8e839560 | 181 | /** |
| AnnaBridge | 163:e59c8e839560 | 182 | * @} |
| AnnaBridge | 163:e59c8e839560 | 183 | */ |
| AnnaBridge | 163:e59c8e839560 | 184 | |
| AnnaBridge | 163:e59c8e839560 | 185 | /** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance |
| AnnaBridge | 163:e59c8e839560 | 186 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 187 | */ |
| AnnaBridge | 163:e59c8e839560 | 188 | #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) |
| AnnaBridge | 163:e59c8e839560 | 189 | |
| AnnaBridge | 163:e59c8e839560 | 190 | /** |
| AnnaBridge | 163:e59c8e839560 | 191 | * @} |
| AnnaBridge | 163:e59c8e839560 | 192 | */ |
| AnnaBridge | 163:e59c8e839560 | 193 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 194 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 195 | |
| AnnaBridge | 163:e59c8e839560 | 196 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| AnnaBridge | 163:e59c8e839560 | 197 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| AnnaBridge | 163:e59c8e839560 | 198 | |
| AnnaBridge | 163:e59c8e839560 | 199 | #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 200 | ((__MODE__) == FMC_WRAP_MODE_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 201 | |
| AnnaBridge | 163:e59c8e839560 | 202 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
| AnnaBridge | 163:e59c8e839560 | 203 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
| AnnaBridge | 163:e59c8e839560 | 204 | |
| AnnaBridge | 163:e59c8e839560 | 205 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 206 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 207 | |
| AnnaBridge | 163:e59c8e839560 | 208 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 209 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 210 | |
| AnnaBridge | 163:e59c8e839560 | 211 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 212 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 213 | |
| AnnaBridge | 163:e59c8e839560 | 214 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| AnnaBridge | 163:e59c8e839560 | 215 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| AnnaBridge | 163:e59c8e839560 | 216 | |
| AnnaBridge | 163:e59c8e839560 | 217 | #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| AnnaBridge | 163:e59c8e839560 | 218 | |
| AnnaBridge | 163:e59c8e839560 | 219 | /** @defgroup FMC_Data_Latency FMC Data Latency |
| AnnaBridge | 163:e59c8e839560 | 220 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 221 | */ |
| AnnaBridge | 163:e59c8e839560 | 222 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| AnnaBridge | 163:e59c8e839560 | 223 | /** |
| AnnaBridge | 163:e59c8e839560 | 224 | * @} |
| AnnaBridge | 163:e59c8e839560 | 225 | */ |
| AnnaBridge | 163:e59c8e839560 | 226 | |
| AnnaBridge | 163:e59c8e839560 | 227 | /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time |
| AnnaBridge | 163:e59c8e839560 | 228 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 229 | */ |
| AnnaBridge | 163:e59c8e839560 | 230 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 163:e59c8e839560 | 231 | /** |
| AnnaBridge | 163:e59c8e839560 | 232 | * @} |
| AnnaBridge | 163:e59c8e839560 | 233 | */ |
| AnnaBridge | 163:e59c8e839560 | 234 | |
| AnnaBridge | 163:e59c8e839560 | 235 | /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time |
| AnnaBridge | 163:e59c8e839560 | 236 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 237 | */ |
| AnnaBridge | 163:e59c8e839560 | 238 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| AnnaBridge | 163:e59c8e839560 | 239 | /** |
| AnnaBridge | 163:e59c8e839560 | 240 | * @} |
| AnnaBridge | 163:e59c8e839560 | 241 | */ |
| AnnaBridge | 163:e59c8e839560 | 242 | |
| AnnaBridge | 163:e59c8e839560 | 243 | /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time |
| AnnaBridge | 163:e59c8e839560 | 244 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 245 | */ |
| AnnaBridge | 163:e59c8e839560 | 246 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| AnnaBridge | 163:e59c8e839560 | 247 | /** |
| AnnaBridge | 163:e59c8e839560 | 248 | * @} |
| AnnaBridge | 163:e59c8e839560 | 249 | */ |
| AnnaBridge | 163:e59c8e839560 | 250 | |
| AnnaBridge | 163:e59c8e839560 | 251 | /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration |
| AnnaBridge | 163:e59c8e839560 | 252 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 253 | */ |
| AnnaBridge | 163:e59c8e839560 | 254 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 163:e59c8e839560 | 255 | /** |
| AnnaBridge | 163:e59c8e839560 | 256 | * @} |
| AnnaBridge | 163:e59c8e839560 | 257 | */ |
| AnnaBridge | 163:e59c8e839560 | 258 | |
| AnnaBridge | 163:e59c8e839560 | 259 | /** |
| AnnaBridge | 163:e59c8e839560 | 260 | * @} |
| AnnaBridge | 163:e59c8e839560 | 261 | */ |
| AnnaBridge | 163:e59c8e839560 | 262 | |
| AnnaBridge | 163:e59c8e839560 | 263 | /* Exported typedef ----------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 264 | |
| AnnaBridge | 163:e59c8e839560 | 265 | /** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types |
| AnnaBridge | 163:e59c8e839560 | 266 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 267 | */ |
| AnnaBridge | 163:e59c8e839560 | 268 | |
| AnnaBridge | 163:e59c8e839560 | 269 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
| AnnaBridge | 163:e59c8e839560 | 270 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
| AnnaBridge | 163:e59c8e839560 | 271 | #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef |
| AnnaBridge | 163:e59c8e839560 | 272 | #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef |
| AnnaBridge | 163:e59c8e839560 | 273 | |
| AnnaBridge | 163:e59c8e839560 | 274 | #define FMC_NORSRAM_DEVICE FMC_Bank1 |
| AnnaBridge | 163:e59c8e839560 | 275 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E |
| AnnaBridge | 163:e59c8e839560 | 276 | #define FMC_NAND_DEVICE FMC_Bank2_3 |
| AnnaBridge | 163:e59c8e839560 | 277 | #define FMC_PCCARD_DEVICE FMC_Bank4 |
| AnnaBridge | 163:e59c8e839560 | 278 | |
| AnnaBridge | 163:e59c8e839560 | 279 | /** |
| AnnaBridge | 163:e59c8e839560 | 280 | * @brief FMC_NORSRAM Configuration Structure definition |
| AnnaBridge | 163:e59c8e839560 | 281 | */ |
| AnnaBridge | 163:e59c8e839560 | 282 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 283 | { |
| AnnaBridge | 163:e59c8e839560 | 284 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| AnnaBridge | 163:e59c8e839560 | 285 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
| AnnaBridge | 163:e59c8e839560 | 286 | |
| AnnaBridge | 163:e59c8e839560 | 287 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| AnnaBridge | 163:e59c8e839560 | 288 | multiplexed on the data bus or not. |
| AnnaBridge | 163:e59c8e839560 | 289 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
| AnnaBridge | 163:e59c8e839560 | 290 | |
| AnnaBridge | 163:e59c8e839560 | 291 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| AnnaBridge | 163:e59c8e839560 | 292 | the corresponding memory device. |
| AnnaBridge | 163:e59c8e839560 | 293 | This parameter can be a value of @ref FMC_Memory_Type */ |
| AnnaBridge | 163:e59c8e839560 | 294 | |
| AnnaBridge | 163:e59c8e839560 | 295 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| AnnaBridge | 163:e59c8e839560 | 296 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
| AnnaBridge | 163:e59c8e839560 | 297 | |
| AnnaBridge | 163:e59c8e839560 | 298 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| AnnaBridge | 163:e59c8e839560 | 299 | valid only with synchronous burst Flash memories. |
| AnnaBridge | 163:e59c8e839560 | 300 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
| AnnaBridge | 163:e59c8e839560 | 301 | |
| AnnaBridge | 163:e59c8e839560 | 302 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| AnnaBridge | 163:e59c8e839560 | 303 | the Flash memory in burst mode. |
| AnnaBridge | 163:e59c8e839560 | 304 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 305 | |
| AnnaBridge | 163:e59c8e839560 | 306 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| AnnaBridge | 163:e59c8e839560 | 307 | memory, valid only when accessing Flash memories in burst mode. |
| AnnaBridge | 163:e59c8e839560 | 308 | This parameter can be a value of @ref FMC_Wrap_Mode */ |
| AnnaBridge | 163:e59c8e839560 | 309 | |
| AnnaBridge | 163:e59c8e839560 | 310 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| AnnaBridge | 163:e59c8e839560 | 311 | clock cycle before the wait state or during the wait state, |
| AnnaBridge | 163:e59c8e839560 | 312 | valid only when accessing memories in burst mode. |
| AnnaBridge | 163:e59c8e839560 | 313 | This parameter can be a value of @ref FMC_Wait_Timing */ |
| AnnaBridge | 163:e59c8e839560 | 314 | |
| AnnaBridge | 163:e59c8e839560 | 315 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
| AnnaBridge | 163:e59c8e839560 | 316 | This parameter can be a value of @ref FMC_Write_Operation */ |
| AnnaBridge | 163:e59c8e839560 | 317 | |
| AnnaBridge | 163:e59c8e839560 | 318 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| AnnaBridge | 163:e59c8e839560 | 319 | signal, valid for Flash memory access in burst mode. |
| AnnaBridge | 163:e59c8e839560 | 320 | This parameter can be a value of @ref FMC_Wait_Signal */ |
| AnnaBridge | 163:e59c8e839560 | 321 | |
| AnnaBridge | 163:e59c8e839560 | 322 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| AnnaBridge | 163:e59c8e839560 | 323 | This parameter can be a value of @ref FMC_Extended_Mode */ |
| AnnaBridge | 163:e59c8e839560 | 324 | |
| AnnaBridge | 163:e59c8e839560 | 325 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| AnnaBridge | 163:e59c8e839560 | 326 | valid only with asynchronous Flash memories. |
| AnnaBridge | 163:e59c8e839560 | 327 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
| AnnaBridge | 163:e59c8e839560 | 328 | |
| AnnaBridge | 163:e59c8e839560 | 329 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| AnnaBridge | 163:e59c8e839560 | 330 | This parameter can be a value of @ref FMC_Write_Burst */ |
| AnnaBridge | 163:e59c8e839560 | 331 | |
| AnnaBridge | 163:e59c8e839560 | 332 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
| AnnaBridge | 163:e59c8e839560 | 333 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| AnnaBridge | 163:e59c8e839560 | 334 | through FMC_BCR2..4 registers. |
| AnnaBridge | 163:e59c8e839560 | 335 | This parameter can be a value of @ref FMC_Continous_Clock */ |
| AnnaBridge | 163:e59c8e839560 | 336 | |
| AnnaBridge | 163:e59c8e839560 | 337 | }FMC_NORSRAM_InitTypeDef; |
| AnnaBridge | 163:e59c8e839560 | 338 | |
| AnnaBridge | 163:e59c8e839560 | 339 | /** |
| AnnaBridge | 163:e59c8e839560 | 340 | * @brief FMC_NORSRAM Timing parameters structure definition |
| AnnaBridge | 163:e59c8e839560 | 341 | */ |
| AnnaBridge | 163:e59c8e839560 | 342 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 343 | { |
| AnnaBridge | 163:e59c8e839560 | 344 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 163:e59c8e839560 | 345 | the duration of the address setup time. |
| AnnaBridge | 163:e59c8e839560 | 346 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 163:e59c8e839560 | 347 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 163:e59c8e839560 | 348 | |
| AnnaBridge | 163:e59c8e839560 | 349 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 163:e59c8e839560 | 350 | the duration of the address hold time. |
| AnnaBridge | 163:e59c8e839560 | 351 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| AnnaBridge | 163:e59c8e839560 | 352 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 163:e59c8e839560 | 353 | |
| AnnaBridge | 163:e59c8e839560 | 354 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 163:e59c8e839560 | 355 | the duration of the data setup time. |
| AnnaBridge | 163:e59c8e839560 | 356 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| AnnaBridge | 163:e59c8e839560 | 357 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| AnnaBridge | 163:e59c8e839560 | 358 | NOR Flash memories. */ |
| AnnaBridge | 163:e59c8e839560 | 359 | |
| AnnaBridge | 163:e59c8e839560 | 360 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 163:e59c8e839560 | 361 | the duration of the bus turnaround. |
| AnnaBridge | 163:e59c8e839560 | 362 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 163:e59c8e839560 | 363 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| AnnaBridge | 163:e59c8e839560 | 364 | |
| AnnaBridge | 163:e59c8e839560 | 365 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| AnnaBridge | 163:e59c8e839560 | 366 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| AnnaBridge | 163:e59c8e839560 | 367 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| AnnaBridge | 163:e59c8e839560 | 368 | accesses. */ |
| AnnaBridge | 163:e59c8e839560 | 369 | |
| AnnaBridge | 163:e59c8e839560 | 370 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| AnnaBridge | 163:e59c8e839560 | 371 | to the memory before getting the first data. |
| AnnaBridge | 163:e59c8e839560 | 372 | The parameter value depends on the memory type as shown below: |
| AnnaBridge | 163:e59c8e839560 | 373 | - It must be set to 0 in case of a CRAM |
| AnnaBridge | 163:e59c8e839560 | 374 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| AnnaBridge | 163:e59c8e839560 | 375 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| AnnaBridge | 163:e59c8e839560 | 376 | with synchronous burst mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 377 | |
| AnnaBridge | 163:e59c8e839560 | 378 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| AnnaBridge | 163:e59c8e839560 | 379 | This parameter can be a value of @ref FMC_Access_Mode */ |
| AnnaBridge | 163:e59c8e839560 | 380 | |
| AnnaBridge | 163:e59c8e839560 | 381 | }FMC_NORSRAM_TimingTypeDef; |
| AnnaBridge | 163:e59c8e839560 | 382 | |
| AnnaBridge | 163:e59c8e839560 | 383 | /** |
| AnnaBridge | 163:e59c8e839560 | 384 | * @brief FMC_NAND Configuration Structure definition |
| AnnaBridge | 163:e59c8e839560 | 385 | */ |
| AnnaBridge | 163:e59c8e839560 | 386 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 387 | { |
| AnnaBridge | 163:e59c8e839560 | 388 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| AnnaBridge | 163:e59c8e839560 | 389 | This parameter can be a value of @ref FMC_NAND_Bank */ |
| AnnaBridge | 163:e59c8e839560 | 390 | |
| AnnaBridge | 163:e59c8e839560 | 391 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| AnnaBridge | 163:e59c8e839560 | 392 | This parameter can be any value of @ref FMC_Wait_feature */ |
| AnnaBridge | 163:e59c8e839560 | 393 | |
| AnnaBridge | 163:e59c8e839560 | 394 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| AnnaBridge | 163:e59c8e839560 | 395 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
| AnnaBridge | 163:e59c8e839560 | 396 | |
| AnnaBridge | 163:e59c8e839560 | 397 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| AnnaBridge | 163:e59c8e839560 | 398 | This parameter can be any value of @ref FMC_ECC */ |
| AnnaBridge | 163:e59c8e839560 | 399 | |
| AnnaBridge | 163:e59c8e839560 | 400 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| AnnaBridge | 163:e59c8e839560 | 401 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
| AnnaBridge | 163:e59c8e839560 | 402 | |
| AnnaBridge | 163:e59c8e839560 | 403 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 163:e59c8e839560 | 404 | delay between CLE low and RE low. |
| AnnaBridge | 163:e59c8e839560 | 405 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 406 | |
| AnnaBridge | 163:e59c8e839560 | 407 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 163:e59c8e839560 | 408 | delay between ALE low and RE low. |
| AnnaBridge | 163:e59c8e839560 | 409 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 410 | |
| AnnaBridge | 163:e59c8e839560 | 411 | }FMC_NAND_InitTypeDef; |
| AnnaBridge | 163:e59c8e839560 | 412 | |
| AnnaBridge | 163:e59c8e839560 | 413 | /** |
| AnnaBridge | 163:e59c8e839560 | 414 | * @brief FMC_NAND_PCC Timing parameters structure definition |
| AnnaBridge | 163:e59c8e839560 | 415 | */ |
| AnnaBridge | 163:e59c8e839560 | 416 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 417 | { |
| AnnaBridge | 163:e59c8e839560 | 418 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| AnnaBridge | 163:e59c8e839560 | 419 | the command assertion for NAND-Flash read or write access |
| AnnaBridge | 163:e59c8e839560 | 420 | to common/Attribute or I/O memory space (depending on |
| AnnaBridge | 163:e59c8e839560 | 421 | the memory space timing to be configured). |
| AnnaBridge | 163:e59c8e839560 | 422 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 423 | |
| AnnaBridge | 163:e59c8e839560 | 424 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| AnnaBridge | 163:e59c8e839560 | 425 | command for NAND-Flash read or write access to |
| AnnaBridge | 163:e59c8e839560 | 426 | common/Attribute or I/O memory space (depending on the |
| AnnaBridge | 163:e59c8e839560 | 427 | memory space timing to be configured). |
| AnnaBridge | 163:e59c8e839560 | 428 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 429 | |
| AnnaBridge | 163:e59c8e839560 | 430 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| AnnaBridge | 163:e59c8e839560 | 431 | (and data for write access) after the command de-assertion |
| AnnaBridge | 163:e59c8e839560 | 432 | for NAND-Flash read or write access to common/Attribute |
| AnnaBridge | 163:e59c8e839560 | 433 | or I/O memory space (depending on the memory space timing |
| AnnaBridge | 163:e59c8e839560 | 434 | to be configured). |
| AnnaBridge | 163:e59c8e839560 | 435 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 436 | |
| AnnaBridge | 163:e59c8e839560 | 437 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| AnnaBridge | 163:e59c8e839560 | 438 | data bus is kept in HiZ after the start of a NAND-Flash |
| AnnaBridge | 163:e59c8e839560 | 439 | write access to common/Attribute or I/O memory space (depending |
| AnnaBridge | 163:e59c8e839560 | 440 | on the memory space timing to be configured). |
| AnnaBridge | 163:e59c8e839560 | 441 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 442 | |
| AnnaBridge | 163:e59c8e839560 | 443 | }FMC_NAND_PCC_TimingTypeDef; |
| AnnaBridge | 163:e59c8e839560 | 444 | |
| AnnaBridge | 163:e59c8e839560 | 445 | /** |
| AnnaBridge | 163:e59c8e839560 | 446 | * @brief FMC_NAND Configuration Structure definition |
| AnnaBridge | 163:e59c8e839560 | 447 | */ |
| AnnaBridge | 163:e59c8e839560 | 448 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 449 | { |
| AnnaBridge | 163:e59c8e839560 | 450 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| AnnaBridge | 163:e59c8e839560 | 451 | This parameter can be any value of @ref FMC_Wait_feature */ |
| AnnaBridge | 163:e59c8e839560 | 452 | |
| AnnaBridge | 163:e59c8e839560 | 453 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 163:e59c8e839560 | 454 | delay between CLE low and RE low. |
| AnnaBridge | 163:e59c8e839560 | 455 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 456 | |
| AnnaBridge | 163:e59c8e839560 | 457 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 163:e59c8e839560 | 458 | delay between ALE low and RE low. |
| AnnaBridge | 163:e59c8e839560 | 459 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 163:e59c8e839560 | 460 | |
| AnnaBridge | 163:e59c8e839560 | 461 | }FMC_PCCARD_InitTypeDef; |
| AnnaBridge | 163:e59c8e839560 | 462 | |
| AnnaBridge | 163:e59c8e839560 | 463 | /** |
| AnnaBridge | 163:e59c8e839560 | 464 | * @} |
| AnnaBridge | 163:e59c8e839560 | 465 | */ |
| AnnaBridge | 163:e59c8e839560 | 466 | |
| AnnaBridge | 163:e59c8e839560 | 467 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 468 | |
| AnnaBridge | 163:e59c8e839560 | 469 | /** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants |
| AnnaBridge | 163:e59c8e839560 | 470 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 471 | */ |
| AnnaBridge | 163:e59c8e839560 | 472 | |
| AnnaBridge | 163:e59c8e839560 | 473 | /** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants |
| AnnaBridge | 163:e59c8e839560 | 474 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 475 | */ |
| AnnaBridge | 163:e59c8e839560 | 476 | |
| AnnaBridge | 163:e59c8e839560 | 477 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
| AnnaBridge | 163:e59c8e839560 | 478 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 479 | */ |
| AnnaBridge | 163:e59c8e839560 | 480 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 481 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| AnnaBridge | 163:e59c8e839560 | 482 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| AnnaBridge | 163:e59c8e839560 | 483 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| AnnaBridge | 163:e59c8e839560 | 484 | |
| AnnaBridge | 163:e59c8e839560 | 485 | /** |
| AnnaBridge | 163:e59c8e839560 | 486 | * @} |
| AnnaBridge | 163:e59c8e839560 | 487 | */ |
| AnnaBridge | 163:e59c8e839560 | 488 | |
| AnnaBridge | 163:e59c8e839560 | 489 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
| AnnaBridge | 163:e59c8e839560 | 490 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 491 | */ |
| AnnaBridge | 163:e59c8e839560 | 492 | |
| AnnaBridge | 163:e59c8e839560 | 493 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 494 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) |
| AnnaBridge | 163:e59c8e839560 | 495 | |
| AnnaBridge | 163:e59c8e839560 | 496 | /** |
| AnnaBridge | 163:e59c8e839560 | 497 | * @} |
| AnnaBridge | 163:e59c8e839560 | 498 | */ |
| AnnaBridge | 163:e59c8e839560 | 499 | |
| AnnaBridge | 163:e59c8e839560 | 500 | /** @defgroup FMC_Memory_Type FMC Memory Type |
| AnnaBridge | 163:e59c8e839560 | 501 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 502 | */ |
| AnnaBridge | 163:e59c8e839560 | 503 | |
| AnnaBridge | 163:e59c8e839560 | 504 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 505 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) |
| AnnaBridge | 163:e59c8e839560 | 506 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) |
| AnnaBridge | 163:e59c8e839560 | 507 | |
| AnnaBridge | 163:e59c8e839560 | 508 | /** |
| AnnaBridge | 163:e59c8e839560 | 509 | * @} |
| AnnaBridge | 163:e59c8e839560 | 510 | */ |
| AnnaBridge | 163:e59c8e839560 | 511 | |
| AnnaBridge | 163:e59c8e839560 | 512 | /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width |
| AnnaBridge | 163:e59c8e839560 | 513 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 514 | */ |
| AnnaBridge | 163:e59c8e839560 | 515 | |
| AnnaBridge | 163:e59c8e839560 | 516 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 517 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) |
| AnnaBridge | 163:e59c8e839560 | 518 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) |
| AnnaBridge | 163:e59c8e839560 | 519 | |
| AnnaBridge | 163:e59c8e839560 | 520 | /** |
| AnnaBridge | 163:e59c8e839560 | 521 | * @} |
| AnnaBridge | 163:e59c8e839560 | 522 | */ |
| AnnaBridge | 163:e59c8e839560 | 523 | |
| AnnaBridge | 163:e59c8e839560 | 524 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access |
| AnnaBridge | 163:e59c8e839560 | 525 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 526 | */ |
| AnnaBridge | 163:e59c8e839560 | 527 | |
| AnnaBridge | 163:e59c8e839560 | 528 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) |
| AnnaBridge | 163:e59c8e839560 | 529 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 530 | /** |
| AnnaBridge | 163:e59c8e839560 | 531 | * @} |
| AnnaBridge | 163:e59c8e839560 | 532 | */ |
| AnnaBridge | 163:e59c8e839560 | 533 | |
| AnnaBridge | 163:e59c8e839560 | 534 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
| AnnaBridge | 163:e59c8e839560 | 535 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 536 | */ |
| AnnaBridge | 163:e59c8e839560 | 537 | |
| AnnaBridge | 163:e59c8e839560 | 538 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 539 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) |
| AnnaBridge | 163:e59c8e839560 | 540 | |
| AnnaBridge | 163:e59c8e839560 | 541 | /** |
| AnnaBridge | 163:e59c8e839560 | 542 | * @} |
| AnnaBridge | 163:e59c8e839560 | 543 | */ |
| AnnaBridge | 163:e59c8e839560 | 544 | |
| AnnaBridge | 163:e59c8e839560 | 545 | |
| AnnaBridge | 163:e59c8e839560 | 546 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
| AnnaBridge | 163:e59c8e839560 | 547 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 548 | */ |
| AnnaBridge | 163:e59c8e839560 | 549 | |
| AnnaBridge | 163:e59c8e839560 | 550 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 551 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) |
| AnnaBridge | 163:e59c8e839560 | 552 | |
| AnnaBridge | 163:e59c8e839560 | 553 | /** |
| AnnaBridge | 163:e59c8e839560 | 554 | * @} |
| AnnaBridge | 163:e59c8e839560 | 555 | */ |
| AnnaBridge | 163:e59c8e839560 | 556 | |
| AnnaBridge | 163:e59c8e839560 | 557 | /** @defgroup FMC_Wrap_Mode FMC Wrap Mode |
| AnnaBridge | 163:e59c8e839560 | 558 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 559 | */ |
| AnnaBridge | 163:e59c8e839560 | 560 | |
| AnnaBridge | 163:e59c8e839560 | 561 | #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 562 | #define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD) |
| AnnaBridge | 163:e59c8e839560 | 563 | |
| AnnaBridge | 163:e59c8e839560 | 564 | /** |
| AnnaBridge | 163:e59c8e839560 | 565 | * @} |
| AnnaBridge | 163:e59c8e839560 | 566 | */ |
| AnnaBridge | 163:e59c8e839560 | 567 | |
| AnnaBridge | 163:e59c8e839560 | 568 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
| AnnaBridge | 163:e59c8e839560 | 569 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 570 | */ |
| AnnaBridge | 163:e59c8e839560 | 571 | |
| AnnaBridge | 163:e59c8e839560 | 572 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 573 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) |
| AnnaBridge | 163:e59c8e839560 | 574 | |
| AnnaBridge | 163:e59c8e839560 | 575 | /** |
| AnnaBridge | 163:e59c8e839560 | 576 | * @} |
| AnnaBridge | 163:e59c8e839560 | 577 | */ |
| AnnaBridge | 163:e59c8e839560 | 578 | |
| AnnaBridge | 163:e59c8e839560 | 579 | /** @defgroup FMC_Write_Operation FMC Write Operation |
| AnnaBridge | 163:e59c8e839560 | 580 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 581 | */ |
| AnnaBridge | 163:e59c8e839560 | 582 | |
| AnnaBridge | 163:e59c8e839560 | 583 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 584 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) |
| AnnaBridge | 163:e59c8e839560 | 585 | |
| AnnaBridge | 163:e59c8e839560 | 586 | /** |
| AnnaBridge | 163:e59c8e839560 | 587 | * @} |
| AnnaBridge | 163:e59c8e839560 | 588 | */ |
| AnnaBridge | 163:e59c8e839560 | 589 | |
| AnnaBridge | 163:e59c8e839560 | 590 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
| AnnaBridge | 163:e59c8e839560 | 591 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 592 | */ |
| AnnaBridge | 163:e59c8e839560 | 593 | |
| AnnaBridge | 163:e59c8e839560 | 594 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 595 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) |
| AnnaBridge | 163:e59c8e839560 | 596 | |
| AnnaBridge | 163:e59c8e839560 | 597 | /** |
| AnnaBridge | 163:e59c8e839560 | 598 | * @} |
| AnnaBridge | 163:e59c8e839560 | 599 | */ |
| AnnaBridge | 163:e59c8e839560 | 600 | |
| AnnaBridge | 163:e59c8e839560 | 601 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
| AnnaBridge | 163:e59c8e839560 | 602 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 603 | */ |
| AnnaBridge | 163:e59c8e839560 | 604 | |
| AnnaBridge | 163:e59c8e839560 | 605 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 606 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) |
| AnnaBridge | 163:e59c8e839560 | 607 | |
| AnnaBridge | 163:e59c8e839560 | 608 | /** |
| AnnaBridge | 163:e59c8e839560 | 609 | * @} |
| AnnaBridge | 163:e59c8e839560 | 610 | */ |
| AnnaBridge | 163:e59c8e839560 | 611 | |
| AnnaBridge | 163:e59c8e839560 | 612 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
| AnnaBridge | 163:e59c8e839560 | 613 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 614 | */ |
| AnnaBridge | 163:e59c8e839560 | 615 | |
| AnnaBridge | 163:e59c8e839560 | 616 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 617 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) |
| AnnaBridge | 163:e59c8e839560 | 618 | |
| AnnaBridge | 163:e59c8e839560 | 619 | /** |
| AnnaBridge | 163:e59c8e839560 | 620 | * @} |
| AnnaBridge | 163:e59c8e839560 | 621 | */ |
| AnnaBridge | 163:e59c8e839560 | 622 | |
| AnnaBridge | 163:e59c8e839560 | 623 | /** @defgroup FMC_Write_Burst FMC Write Burst |
| AnnaBridge | 163:e59c8e839560 | 624 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 625 | */ |
| AnnaBridge | 163:e59c8e839560 | 626 | |
| AnnaBridge | 163:e59c8e839560 | 627 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 628 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) |
| AnnaBridge | 163:e59c8e839560 | 629 | |
| AnnaBridge | 163:e59c8e839560 | 630 | /** |
| AnnaBridge | 163:e59c8e839560 | 631 | * @} |
| AnnaBridge | 163:e59c8e839560 | 632 | */ |
| AnnaBridge | 163:e59c8e839560 | 633 | |
| AnnaBridge | 163:e59c8e839560 | 634 | /** @defgroup FMC_Continous_Clock FMC Continous Clock |
| AnnaBridge | 163:e59c8e839560 | 635 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 636 | */ |
| AnnaBridge | 163:e59c8e839560 | 637 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 638 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) |
| AnnaBridge | 163:e59c8e839560 | 639 | /** |
| AnnaBridge | 163:e59c8e839560 | 640 | * @} |
| AnnaBridge | 163:e59c8e839560 | 641 | */ |
| AnnaBridge | 163:e59c8e839560 | 642 | |
| AnnaBridge | 163:e59c8e839560 | 643 | /** @defgroup FMC_Access_Mode FMC Access Mode |
| AnnaBridge | 163:e59c8e839560 | 644 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 645 | */ |
| AnnaBridge | 163:e59c8e839560 | 646 | |
| AnnaBridge | 163:e59c8e839560 | 647 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 648 | #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) |
| AnnaBridge | 163:e59c8e839560 | 649 | #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) |
| AnnaBridge | 163:e59c8e839560 | 650 | #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) |
| AnnaBridge | 163:e59c8e839560 | 651 | |
| AnnaBridge | 163:e59c8e839560 | 652 | /** |
| AnnaBridge | 163:e59c8e839560 | 653 | * @} |
| AnnaBridge | 163:e59c8e839560 | 654 | */ |
| AnnaBridge | 163:e59c8e839560 | 655 | |
| AnnaBridge | 163:e59c8e839560 | 656 | /** |
| AnnaBridge | 163:e59c8e839560 | 657 | * @} |
| AnnaBridge | 163:e59c8e839560 | 658 | */ |
| AnnaBridge | 163:e59c8e839560 | 659 | |
| AnnaBridge | 163:e59c8e839560 | 660 | /** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller |
| AnnaBridge | 163:e59c8e839560 | 661 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 662 | */ |
| AnnaBridge | 163:e59c8e839560 | 663 | |
| AnnaBridge | 163:e59c8e839560 | 664 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 665 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 666 | */ |
| AnnaBridge | 163:e59c8e839560 | 667 | #define FMC_NAND_BANK2 ((uint32_t)0x00000010) |
| AnnaBridge | 163:e59c8e839560 | 668 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
| AnnaBridge | 163:e59c8e839560 | 669 | |
| AnnaBridge | 163:e59c8e839560 | 670 | /** |
| AnnaBridge | 163:e59c8e839560 | 671 | * @} |
| AnnaBridge | 163:e59c8e839560 | 672 | */ |
| AnnaBridge | 163:e59c8e839560 | 673 | |
| AnnaBridge | 163:e59c8e839560 | 674 | /** @defgroup FMC_Wait_feature FMC Wait feature |
| AnnaBridge | 163:e59c8e839560 | 675 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 676 | */ |
| AnnaBridge | 163:e59c8e839560 | 677 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 678 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN) |
| AnnaBridge | 163:e59c8e839560 | 679 | |
| AnnaBridge | 163:e59c8e839560 | 680 | /** |
| AnnaBridge | 163:e59c8e839560 | 681 | * @} |
| AnnaBridge | 163:e59c8e839560 | 682 | */ |
| AnnaBridge | 163:e59c8e839560 | 683 | |
| AnnaBridge | 163:e59c8e839560 | 684 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
| AnnaBridge | 163:e59c8e839560 | 685 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 686 | */ |
| AnnaBridge | 163:e59c8e839560 | 687 | #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 688 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP) |
| AnnaBridge | 163:e59c8e839560 | 689 | /** |
| AnnaBridge | 163:e59c8e839560 | 690 | * @} |
| AnnaBridge | 163:e59c8e839560 | 691 | */ |
| AnnaBridge | 163:e59c8e839560 | 692 | |
| AnnaBridge | 163:e59c8e839560 | 693 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
| AnnaBridge | 163:e59c8e839560 | 694 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 695 | */ |
| AnnaBridge | 163:e59c8e839560 | 696 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 697 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0) |
| AnnaBridge | 163:e59c8e839560 | 698 | |
| AnnaBridge | 163:e59c8e839560 | 699 | /** |
| AnnaBridge | 163:e59c8e839560 | 700 | * @} |
| AnnaBridge | 163:e59c8e839560 | 701 | */ |
| AnnaBridge | 163:e59c8e839560 | 702 | |
| AnnaBridge | 163:e59c8e839560 | 703 | /** @defgroup FMC_ECC FMC NAND ECC |
| AnnaBridge | 163:e59c8e839560 | 704 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 705 | */ |
| AnnaBridge | 163:e59c8e839560 | 706 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 707 | #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN) |
| AnnaBridge | 163:e59c8e839560 | 708 | |
| AnnaBridge | 163:e59c8e839560 | 709 | /** |
| AnnaBridge | 163:e59c8e839560 | 710 | * @} |
| AnnaBridge | 163:e59c8e839560 | 711 | */ |
| AnnaBridge | 163:e59c8e839560 | 712 | |
| AnnaBridge | 163:e59c8e839560 | 713 | /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size |
| AnnaBridge | 163:e59c8e839560 | 714 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 715 | */ |
| AnnaBridge | 163:e59c8e839560 | 716 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| AnnaBridge | 163:e59c8e839560 | 717 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0) |
| AnnaBridge | 163:e59c8e839560 | 718 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1) |
| AnnaBridge | 163:e59c8e839560 | 719 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1) |
| AnnaBridge | 163:e59c8e839560 | 720 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2) |
| AnnaBridge | 163:e59c8e839560 | 721 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2) |
| AnnaBridge | 163:e59c8e839560 | 722 | |
| AnnaBridge | 163:e59c8e839560 | 723 | /** |
| AnnaBridge | 163:e59c8e839560 | 724 | * @} |
| AnnaBridge | 163:e59c8e839560 | 725 | */ |
| AnnaBridge | 163:e59c8e839560 | 726 | |
| AnnaBridge | 163:e59c8e839560 | 727 | /** @defgroup FMC_Interrupt_definition FMC Interrupt definition |
| AnnaBridge | 163:e59c8e839560 | 728 | * @brief FMC Interrupt definition |
| AnnaBridge | 163:e59c8e839560 | 729 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 730 | */ |
| AnnaBridge | 163:e59c8e839560 | 731 | #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN) |
| AnnaBridge | 163:e59c8e839560 | 732 | #define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN) |
| AnnaBridge | 163:e59c8e839560 | 733 | #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN) |
| AnnaBridge | 163:e59c8e839560 | 734 | |
| AnnaBridge | 163:e59c8e839560 | 735 | /** |
| AnnaBridge | 163:e59c8e839560 | 736 | * @} |
| AnnaBridge | 163:e59c8e839560 | 737 | */ |
| AnnaBridge | 163:e59c8e839560 | 738 | |
| AnnaBridge | 163:e59c8e839560 | 739 | /** @defgroup FMC_Flag_definition FMC Flag definition |
| AnnaBridge | 163:e59c8e839560 | 740 | * @brief FMC Flag definition |
| AnnaBridge | 163:e59c8e839560 | 741 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 742 | */ |
| AnnaBridge | 163:e59c8e839560 | 743 | #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS) |
| AnnaBridge | 163:e59c8e839560 | 744 | #define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS) |
| AnnaBridge | 163:e59c8e839560 | 745 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS) |
| AnnaBridge | 163:e59c8e839560 | 746 | #define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT) |
| AnnaBridge | 163:e59c8e839560 | 747 | |
| AnnaBridge | 163:e59c8e839560 | 748 | /** |
| AnnaBridge | 163:e59c8e839560 | 749 | * @} |
| AnnaBridge | 163:e59c8e839560 | 750 | */ |
| AnnaBridge | 163:e59c8e839560 | 751 | |
| AnnaBridge | 163:e59c8e839560 | 752 | /** |
| AnnaBridge | 163:e59c8e839560 | 753 | * @} |
| AnnaBridge | 163:e59c8e839560 | 754 | */ |
| AnnaBridge | 163:e59c8e839560 | 755 | |
| AnnaBridge | 163:e59c8e839560 | 756 | /** |
| AnnaBridge | 163:e59c8e839560 | 757 | * @} |
| AnnaBridge | 163:e59c8e839560 | 758 | */ |
| AnnaBridge | 163:e59c8e839560 | 759 | |
| AnnaBridge | 163:e59c8e839560 | 760 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 761 | |
| AnnaBridge | 163:e59c8e839560 | 762 | /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros |
| AnnaBridge | 163:e59c8e839560 | 763 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 764 | */ |
| AnnaBridge | 163:e59c8e839560 | 765 | |
| AnnaBridge | 163:e59c8e839560 | 766 | /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros |
| AnnaBridge | 163:e59c8e839560 | 767 | * @brief macros to handle NOR device enable/disable and read/write operations |
| AnnaBridge | 163:e59c8e839560 | 768 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 769 | */ |
| AnnaBridge | 163:e59c8e839560 | 770 | |
| AnnaBridge | 163:e59c8e839560 | 771 | /** |
| AnnaBridge | 163:e59c8e839560 | 772 | * @brief Enable the NORSRAM device access. |
| AnnaBridge | 163:e59c8e839560 | 773 | * @param __INSTANCE__ FMC_NORSRAM Instance |
| AnnaBridge | 163:e59c8e839560 | 774 | * @param __BANK__ FMC_NORSRAM Bank |
| AnnaBridge | 163:e59c8e839560 | 775 | * @retval none |
| AnnaBridge | 163:e59c8e839560 | 776 | */ |
| AnnaBridge | 163:e59c8e839560 | 777 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| AnnaBridge | 163:e59c8e839560 | 778 | |
| AnnaBridge | 163:e59c8e839560 | 779 | /** |
| AnnaBridge | 163:e59c8e839560 | 780 | * @brief Disable the NORSRAM device access. |
| AnnaBridge | 163:e59c8e839560 | 781 | * @param __INSTANCE__ FMC_NORSRAM Instance |
| AnnaBridge | 163:e59c8e839560 | 782 | * @param __BANK__ FMC_NORSRAM Bank |
| AnnaBridge | 163:e59c8e839560 | 783 | * @retval none |
| AnnaBridge | 163:e59c8e839560 | 784 | */ |
| AnnaBridge | 163:e59c8e839560 | 785 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| AnnaBridge | 163:e59c8e839560 | 786 | |
| AnnaBridge | 163:e59c8e839560 | 787 | /** |
| AnnaBridge | 163:e59c8e839560 | 788 | * @} |
| AnnaBridge | 163:e59c8e839560 | 789 | */ |
| AnnaBridge | 163:e59c8e839560 | 790 | |
| AnnaBridge | 163:e59c8e839560 | 791 | /** @defgroup FMC_NAND_Macros FMC NAND Macros |
| AnnaBridge | 163:e59c8e839560 | 792 | * @brief macros to handle NAND device enable/disable |
| AnnaBridge | 163:e59c8e839560 | 793 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 794 | */ |
| AnnaBridge | 163:e59c8e839560 | 795 | |
| AnnaBridge | 163:e59c8e839560 | 796 | /** |
| AnnaBridge | 163:e59c8e839560 | 797 | * @brief Enable the NAND device access. |
| AnnaBridge | 163:e59c8e839560 | 798 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 799 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 800 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 801 | */ |
| AnnaBridge | 163:e59c8e839560 | 802 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \ |
| AnnaBridge | 163:e59c8e839560 | 803 | SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) |
| AnnaBridge | 163:e59c8e839560 | 804 | |
| AnnaBridge | 163:e59c8e839560 | 805 | /** |
| AnnaBridge | 163:e59c8e839560 | 806 | * @brief Disable the NAND device access. |
| AnnaBridge | 163:e59c8e839560 | 807 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 808 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 809 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 810 | */ |
| AnnaBridge | 163:e59c8e839560 | 811 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \ |
| AnnaBridge | 163:e59c8e839560 | 812 | CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) |
| AnnaBridge | 163:e59c8e839560 | 813 | |
| AnnaBridge | 163:e59c8e839560 | 814 | /** |
| AnnaBridge | 163:e59c8e839560 | 815 | * @} |
| AnnaBridge | 163:e59c8e839560 | 816 | */ |
| AnnaBridge | 163:e59c8e839560 | 817 | |
| AnnaBridge | 163:e59c8e839560 | 818 | /** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros |
| AnnaBridge | 163:e59c8e839560 | 819 | * @brief macros to handle PCCARD read/write operations |
| AnnaBridge | 163:e59c8e839560 | 820 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 821 | */ |
| AnnaBridge | 163:e59c8e839560 | 822 | |
| AnnaBridge | 163:e59c8e839560 | 823 | /** |
| AnnaBridge | 163:e59c8e839560 | 824 | * @brief Enable the PCCARD device access. |
| AnnaBridge | 163:e59c8e839560 | 825 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 826 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 827 | */ |
| AnnaBridge | 163:e59c8e839560 | 828 | #define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN) |
| AnnaBridge | 163:e59c8e839560 | 829 | |
| AnnaBridge | 163:e59c8e839560 | 830 | /** |
| AnnaBridge | 163:e59c8e839560 | 831 | * @brief Disable the PCCARD device access. |
| AnnaBridge | 163:e59c8e839560 | 832 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 833 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 834 | */ |
| AnnaBridge | 163:e59c8e839560 | 835 | #define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN) |
| AnnaBridge | 163:e59c8e839560 | 836 | /** |
| AnnaBridge | 163:e59c8e839560 | 837 | * @} |
| AnnaBridge | 163:e59c8e839560 | 838 | */ |
| AnnaBridge | 163:e59c8e839560 | 839 | |
| AnnaBridge | 163:e59c8e839560 | 840 | /** @defgroup FMC_Interrupt FMC Interrupt |
| AnnaBridge | 163:e59c8e839560 | 841 | * @brief macros to handle FMC interrupts |
| AnnaBridge | 163:e59c8e839560 | 842 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 843 | */ |
| AnnaBridge | 163:e59c8e839560 | 844 | |
| AnnaBridge | 163:e59c8e839560 | 845 | /** |
| AnnaBridge | 163:e59c8e839560 | 846 | * @brief Enable the NAND device interrupt. |
| AnnaBridge | 163:e59c8e839560 | 847 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 848 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 849 | * @param __INTERRUPT__ FMC_NAND interrupt |
| AnnaBridge | 163:e59c8e839560 | 850 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 851 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 163:e59c8e839560 | 852 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 163:e59c8e839560 | 853 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 163:e59c8e839560 | 854 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 855 | */ |
| AnnaBridge | 163:e59c8e839560 | 856 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| AnnaBridge | 163:e59c8e839560 | 857 | SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| AnnaBridge | 163:e59c8e839560 | 858 | |
| AnnaBridge | 163:e59c8e839560 | 859 | /** |
| AnnaBridge | 163:e59c8e839560 | 860 | * @brief Disable the NAND device interrupt. |
| AnnaBridge | 163:e59c8e839560 | 861 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 862 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 863 | * @param __INTERRUPT__ FMC_NAND interrupt |
| AnnaBridge | 163:e59c8e839560 | 864 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 865 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 163:e59c8e839560 | 866 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 163:e59c8e839560 | 867 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 163:e59c8e839560 | 868 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 869 | */ |
| AnnaBridge | 163:e59c8e839560 | 870 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| AnnaBridge | 163:e59c8e839560 | 871 | CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| AnnaBridge | 163:e59c8e839560 | 872 | |
| AnnaBridge | 163:e59c8e839560 | 873 | /** |
| AnnaBridge | 163:e59c8e839560 | 874 | * @brief Get flag status of the NAND device. |
| AnnaBridge | 163:e59c8e839560 | 875 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 876 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 877 | * @param __FLAG__ FMC_NAND flag |
| AnnaBridge | 163:e59c8e839560 | 878 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 879 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 163:e59c8e839560 | 880 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 163:e59c8e839560 | 881 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 163:e59c8e839560 | 882 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 163:e59c8e839560 | 883 | * @retval The state of FLAG (SET or RESET). |
| AnnaBridge | 163:e59c8e839560 | 884 | */ |
| AnnaBridge | 163:e59c8e839560 | 885 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| AnnaBridge | 163:e59c8e839560 | 886 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| AnnaBridge | 163:e59c8e839560 | 887 | |
| AnnaBridge | 163:e59c8e839560 | 888 | /** |
| AnnaBridge | 163:e59c8e839560 | 889 | * @brief Clear flag status of the NAND device. |
| AnnaBridge | 163:e59c8e839560 | 890 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 163:e59c8e839560 | 891 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 163:e59c8e839560 | 892 | * @param __FLAG__ FMC_NAND flag |
| AnnaBridge | 163:e59c8e839560 | 893 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 894 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 163:e59c8e839560 | 895 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 163:e59c8e839560 | 896 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 163:e59c8e839560 | 897 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 163:e59c8e839560 | 898 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 899 | */ |
| AnnaBridge | 163:e59c8e839560 | 900 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \ |
| AnnaBridge | 163:e59c8e839560 | 901 | CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__))) |
| AnnaBridge | 163:e59c8e839560 | 902 | |
| AnnaBridge | 163:e59c8e839560 | 903 | /** |
| AnnaBridge | 163:e59c8e839560 | 904 | * @brief Enable the PCCARD device interrupt. |
| AnnaBridge | 163:e59c8e839560 | 905 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 906 | * @param __INTERRUPT__ FMC_PCCARD interrupt |
| AnnaBridge | 163:e59c8e839560 | 907 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 908 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 163:e59c8e839560 | 909 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 163:e59c8e839560 | 910 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 163:e59c8e839560 | 911 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 912 | */ |
| AnnaBridge | 163:e59c8e839560 | 913 | #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| AnnaBridge | 163:e59c8e839560 | 914 | |
| AnnaBridge | 163:e59c8e839560 | 915 | /** |
| AnnaBridge | 163:e59c8e839560 | 916 | * @brief Disable the PCCARD device interrupt. |
| AnnaBridge | 163:e59c8e839560 | 917 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 918 | * @param __INTERRUPT__ FMC_PCCARD interrupt |
| AnnaBridge | 163:e59c8e839560 | 919 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 920 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 163:e59c8e839560 | 921 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 163:e59c8e839560 | 922 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 163:e59c8e839560 | 923 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 924 | */ |
| AnnaBridge | 163:e59c8e839560 | 925 | #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| AnnaBridge | 163:e59c8e839560 | 926 | |
| AnnaBridge | 163:e59c8e839560 | 927 | /** |
| AnnaBridge | 163:e59c8e839560 | 928 | * @brief Get flag status of the PCCARD device. |
| AnnaBridge | 163:e59c8e839560 | 929 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 930 | * @param __FLAG__ FMC_PCCARD flag |
| AnnaBridge | 163:e59c8e839560 | 931 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 932 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 163:e59c8e839560 | 933 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 163:e59c8e839560 | 934 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 163:e59c8e839560 | 935 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 163:e59c8e839560 | 936 | * @retval The state of FLAG (SET or RESET). |
| AnnaBridge | 163:e59c8e839560 | 937 | */ |
| AnnaBridge | 163:e59c8e839560 | 938 | #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 163:e59c8e839560 | 939 | |
| AnnaBridge | 163:e59c8e839560 | 940 | /** |
| AnnaBridge | 163:e59c8e839560 | 941 | * @brief Clear flag status of the PCCARD device. |
| AnnaBridge | 163:e59c8e839560 | 942 | * @param __INSTANCE__ FMC_PCCARD Instance |
| AnnaBridge | 163:e59c8e839560 | 943 | * @param __FLAG__ FMC_PCCARD flag |
| AnnaBridge | 163:e59c8e839560 | 944 | * This parameter can be any combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 945 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 163:e59c8e839560 | 946 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 163:e59c8e839560 | 947 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 163:e59c8e839560 | 948 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 163:e59c8e839560 | 949 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 950 | */ |
| AnnaBridge | 163:e59c8e839560 | 951 | #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__)) |
| AnnaBridge | 163:e59c8e839560 | 952 | |
| AnnaBridge | 163:e59c8e839560 | 953 | /** |
| AnnaBridge | 163:e59c8e839560 | 954 | * @} |
| AnnaBridge | 163:e59c8e839560 | 955 | */ |
| AnnaBridge | 163:e59c8e839560 | 956 | |
| AnnaBridge | 163:e59c8e839560 | 957 | |
| AnnaBridge | 163:e59c8e839560 | 958 | /** |
| AnnaBridge | 163:e59c8e839560 | 959 | * @} |
| AnnaBridge | 163:e59c8e839560 | 960 | */ |
| AnnaBridge | 163:e59c8e839560 | 961 | |
| AnnaBridge | 163:e59c8e839560 | 962 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 963 | |
| AnnaBridge | 163:e59c8e839560 | 964 | /** @addtogroup FMC_LL_Exported_Functions |
| AnnaBridge | 163:e59c8e839560 | 965 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 966 | */ |
| AnnaBridge | 163:e59c8e839560 | 967 | |
| AnnaBridge | 163:e59c8e839560 | 968 | /** @addtogroup FMC_NORSRAM |
| AnnaBridge | 163:e59c8e839560 | 969 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 970 | */ |
| AnnaBridge | 163:e59c8e839560 | 971 | |
| AnnaBridge | 163:e59c8e839560 | 972 | /** @addtogroup FMC_NORSRAM_Group1 |
| AnnaBridge | 163:e59c8e839560 | 973 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 974 | */ |
| AnnaBridge | 163:e59c8e839560 | 975 | |
| AnnaBridge | 163:e59c8e839560 | 976 | /* FMC_NORSRAM Controller functions ******************************************/ |
| AnnaBridge | 163:e59c8e839560 | 977 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 163:e59c8e839560 | 978 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
| AnnaBridge | 163:e59c8e839560 | 979 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 980 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| AnnaBridge | 163:e59c8e839560 | 981 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 982 | |
| AnnaBridge | 163:e59c8e839560 | 983 | /** |
| AnnaBridge | 163:e59c8e839560 | 984 | * @} |
| AnnaBridge | 163:e59c8e839560 | 985 | */ |
| AnnaBridge | 163:e59c8e839560 | 986 | |
| AnnaBridge | 163:e59c8e839560 | 987 | /** @addtogroup FMC_NORSRAM_Group2 |
| AnnaBridge | 163:e59c8e839560 | 988 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 989 | */ |
| AnnaBridge | 163:e59c8e839560 | 990 | |
| AnnaBridge | 163:e59c8e839560 | 991 | /* FMC_NORSRAM Control functions */ |
| AnnaBridge | 163:e59c8e839560 | 992 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 993 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 994 | |
| AnnaBridge | 163:e59c8e839560 | 995 | /** |
| AnnaBridge | 163:e59c8e839560 | 996 | * @} |
| AnnaBridge | 163:e59c8e839560 | 997 | */ |
| AnnaBridge | 163:e59c8e839560 | 998 | |
| AnnaBridge | 163:e59c8e839560 | 999 | /** |
| AnnaBridge | 163:e59c8e839560 | 1000 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1001 | */ |
| AnnaBridge | 163:e59c8e839560 | 1002 | |
| AnnaBridge | 163:e59c8e839560 | 1003 | /** @addtogroup FMC_NAND |
| AnnaBridge | 163:e59c8e839560 | 1004 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1005 | */ |
| AnnaBridge | 163:e59c8e839560 | 1006 | |
| AnnaBridge | 163:e59c8e839560 | 1007 | /* FMC_NAND Controller functions **********************************************/ |
| AnnaBridge | 163:e59c8e839560 | 1008 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 163:e59c8e839560 | 1009 | /** @addtogroup FMC_NAND_Exported_Functions_Group1 |
| AnnaBridge | 163:e59c8e839560 | 1010 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1011 | */ |
| AnnaBridge | 163:e59c8e839560 | 1012 | |
| AnnaBridge | 163:e59c8e839560 | 1013 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
| AnnaBridge | 163:e59c8e839560 | 1014 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 1015 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 1016 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 1017 | |
| AnnaBridge | 163:e59c8e839560 | 1018 | /** |
| AnnaBridge | 163:e59c8e839560 | 1019 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1020 | */ |
| AnnaBridge | 163:e59c8e839560 | 1021 | |
| AnnaBridge | 163:e59c8e839560 | 1022 | /* FMC_NAND Control functions */ |
| AnnaBridge | 163:e59c8e839560 | 1023 | /** @addtogroup FMC_NAND_Exported_Functions_Group2 |
| AnnaBridge | 163:e59c8e839560 | 1024 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1025 | */ |
| AnnaBridge | 163:e59c8e839560 | 1026 | |
| AnnaBridge | 163:e59c8e839560 | 1027 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 1028 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 163:e59c8e839560 | 1029 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| AnnaBridge | 163:e59c8e839560 | 1030 | |
| AnnaBridge | 163:e59c8e839560 | 1031 | /** |
| AnnaBridge | 163:e59c8e839560 | 1032 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1033 | */ |
| AnnaBridge | 163:e59c8e839560 | 1034 | |
| AnnaBridge | 163:e59c8e839560 | 1035 | /** |
| AnnaBridge | 163:e59c8e839560 | 1036 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1037 | */ |
| AnnaBridge | 163:e59c8e839560 | 1038 | |
| AnnaBridge | 163:e59c8e839560 | 1039 | /** @addtogroup FMC_PCCARD |
| AnnaBridge | 163:e59c8e839560 | 1040 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1041 | */ |
| AnnaBridge | 163:e59c8e839560 | 1042 | |
| AnnaBridge | 163:e59c8e839560 | 1043 | /* FMC_PCCARD Controller functions ********************************************/ |
| AnnaBridge | 163:e59c8e839560 | 1044 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 163:e59c8e839560 | 1045 | /** @addtogroup FMC_PCCARD_Exported_Functions_Group1 |
| AnnaBridge | 163:e59c8e839560 | 1046 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1047 | */ |
| AnnaBridge | 163:e59c8e839560 | 1048 | |
| AnnaBridge | 163:e59c8e839560 | 1049 | HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); |
| AnnaBridge | 163:e59c8e839560 | 1050 | HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); |
| AnnaBridge | 163:e59c8e839560 | 1051 | HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); |
| AnnaBridge | 163:e59c8e839560 | 1052 | HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); |
| AnnaBridge | 163:e59c8e839560 | 1053 | HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); |
| AnnaBridge | 163:e59c8e839560 | 1054 | |
| AnnaBridge | 163:e59c8e839560 | 1055 | /** |
| AnnaBridge | 163:e59c8e839560 | 1056 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1057 | */ |
| AnnaBridge | 163:e59c8e839560 | 1058 | |
| AnnaBridge | 163:e59c8e839560 | 1059 | /** |
| AnnaBridge | 163:e59c8e839560 | 1060 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1061 | */ |
| AnnaBridge | 163:e59c8e839560 | 1062 | |
| AnnaBridge | 163:e59c8e839560 | 1063 | /** |
| AnnaBridge | 163:e59c8e839560 | 1064 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1065 | */ |
| AnnaBridge | 163:e59c8e839560 | 1066 | |
| AnnaBridge | 163:e59c8e839560 | 1067 | /** |
| AnnaBridge | 163:e59c8e839560 | 1068 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1069 | */ |
| AnnaBridge | 163:e59c8e839560 | 1070 | |
| AnnaBridge | 163:e59c8e839560 | 1071 | #endif /* FMC_BANK1 */ |
| AnnaBridge | 163:e59c8e839560 | 1072 | |
| AnnaBridge | 163:e59c8e839560 | 1073 | /** |
| AnnaBridge | 163:e59c8e839560 | 1074 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1075 | */ |
| AnnaBridge | 163:e59c8e839560 | 1076 | |
| AnnaBridge | 163:e59c8e839560 | 1077 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 1078 | } |
| AnnaBridge | 163:e59c8e839560 | 1079 | #endif |
| AnnaBridge | 163:e59c8e839560 | 1080 | |
| AnnaBridge | 163:e59c8e839560 | 1081 | #endif /* __STM32F3xx_LL_FMC_H */ |
| AnnaBridge | 163:e59c8e839560 | 1082 | |
| AnnaBridge | 163:e59c8e839560 | 1083 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 163:e59c8e839560 | 1084 |
