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TARGET_LPC812/system_LPC8xx.h@64:e3affc9e7238, 2013-08-05 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Aug 05 12:28:09 2013 +0300
- Revision:
- 64:e3affc9e7238
- Parent:
- LPC812/system_LPC8xx.h@62:7e6c9f46b3bd
- Child:
- 65:5798e58a58b1
New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 62:7e6c9f46b3bd | 1 | /****************************************************************************** |
| emilmont | 62:7e6c9f46b3bd | 2 | * @file: system_LPC8xx.h |
| emilmont | 62:7e6c9f46b3bd | 3 | * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File |
| emilmont | 62:7e6c9f46b3bd | 4 | * for the NXP LPC8xx Device Series |
| emilmont | 62:7e6c9f46b3bd | 5 | * @version: V1.0 |
| emilmont | 62:7e6c9f46b3bd | 6 | * @date: 16. Aug. 2012 |
| emilmont | 62:7e6c9f46b3bd | 7 | *---------------------------------------------------------------------------- |
| emilmont | 62:7e6c9f46b3bd | 8 | * |
| emilmont | 62:7e6c9f46b3bd | 9 | * Copyright (C) 2012 ARM Limited. All rights reserved. |
| emilmont | 62:7e6c9f46b3bd | 10 | * |
| emilmont | 62:7e6c9f46b3bd | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ |
| emilmont | 62:7e6c9f46b3bd | 12 | * processor based microcontrollers. This file can be freely distributed |
| emilmont | 62:7e6c9f46b3bd | 13 | * within development tools that are supporting such ARM based processors. |
| emilmont | 62:7e6c9f46b3bd | 14 | * |
| emilmont | 62:7e6c9f46b3bd | 15 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| emilmont | 62:7e6c9f46b3bd | 16 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| emilmont | 62:7e6c9f46b3bd | 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| emilmont | 62:7e6c9f46b3bd | 18 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| emilmont | 62:7e6c9f46b3bd | 19 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| emilmont | 62:7e6c9f46b3bd | 20 | * |
| emilmont | 62:7e6c9f46b3bd | 21 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 22 | |
| emilmont | 62:7e6c9f46b3bd | 23 | |
| emilmont | 62:7e6c9f46b3bd | 24 | #ifndef __SYSTEM_LPC8xx_H |
| emilmont | 62:7e6c9f46b3bd | 25 | #define __SYSTEM_LPC8xx_H |
| emilmont | 62:7e6c9f46b3bd | 26 | |
| emilmont | 62:7e6c9f46b3bd | 27 | #ifdef __cplusplus |
| emilmont | 62:7e6c9f46b3bd | 28 | extern "C" { |
| emilmont | 62:7e6c9f46b3bd | 29 | #endif |
| emilmont | 62:7e6c9f46b3bd | 30 | |
| emilmont | 62:7e6c9f46b3bd | 31 | #include <stdint.h> |
| emilmont | 62:7e6c9f46b3bd | 32 | |
| emilmont | 62:7e6c9f46b3bd | 33 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
| emilmont | 62:7e6c9f46b3bd | 34 | |
| emilmont | 62:7e6c9f46b3bd | 35 | |
| emilmont | 62:7e6c9f46b3bd | 36 | /** |
| emilmont | 62:7e6c9f46b3bd | 37 | * Initialize the system |
| emilmont | 62:7e6c9f46b3bd | 38 | * |
| emilmont | 62:7e6c9f46b3bd | 39 | * @param none |
| emilmont | 62:7e6c9f46b3bd | 40 | * @return none |
| emilmont | 62:7e6c9f46b3bd | 41 | * |
| emilmont | 62:7e6c9f46b3bd | 42 | * @brief Setup the microcontroller system. |
| emilmont | 62:7e6c9f46b3bd | 43 | * Initialize the System and update the SystemCoreClock variable. |
| emilmont | 62:7e6c9f46b3bd | 44 | */ |
| emilmont | 62:7e6c9f46b3bd | 45 | extern void SystemInit (void); |
| emilmont | 62:7e6c9f46b3bd | 46 | |
| emilmont | 62:7e6c9f46b3bd | 47 | /** |
| emilmont | 62:7e6c9f46b3bd | 48 | * Update SystemCoreClock variable |
| emilmont | 62:7e6c9f46b3bd | 49 | * |
| emilmont | 62:7e6c9f46b3bd | 50 | * @param none |
| emilmont | 62:7e6c9f46b3bd | 51 | * @return none |
| emilmont | 62:7e6c9f46b3bd | 52 | * |
| emilmont | 62:7e6c9f46b3bd | 53 | * @brief Updates the SystemCoreClock with current core Clock |
| emilmont | 62:7e6c9f46b3bd | 54 | * retrieved from cpu registers. |
| emilmont | 62:7e6c9f46b3bd | 55 | */ |
| emilmont | 62:7e6c9f46b3bd | 56 | extern void SystemCoreClockUpdate (void); |
| emilmont | 62:7e6c9f46b3bd | 57 | |
| emilmont | 62:7e6c9f46b3bd | 58 | #ifdef __cplusplus |
| emilmont | 62:7e6c9f46b3bd | 59 | } |
| emilmont | 62:7e6c9f46b3bd | 60 | #endif |
| emilmont | 62:7e6c9f46b3bd | 61 | |
| emilmont | 62:7e6c9f46b3bd | 62 | #endif /* __SYSTEM_LPC8xx_H */ |
