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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.h@165:d1b4690b3f8b, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 14:31:27 2018 +0100
Revision:
165:d1b4690b3f8b
Parent:
128:9bcdf88f62b0 
mbed library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @brief This file contains all the functions prototypes for the HAL
<> 128:9bcdf88f62b0 6 * module driver.
<> 128:9bcdf88f62b0 7 ******************************************************************************
<> 128:9bcdf88f62b0 8 * @attention
<> 128:9bcdf88f62b0 9 *
AnnaBridge 165:d1b4690b3f8b 10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 11 *
<> 128:9bcdf88f62b0 12 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 13 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 15 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 17 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 18 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 20 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 21 * without specific prior written permission.
<> 128:9bcdf88f62b0 22 *
<> 128:9bcdf88f62b0 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 33 *
<> 128:9bcdf88f62b0 34 ******************************************************************************
<> 128:9bcdf88f62b0 35 */
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 38 #ifndef __STM32L1xx_HAL_H
<> 128:9bcdf88f62b0 39 #define __STM32L1xx_HAL_H
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 #ifdef __cplusplus
<> 128:9bcdf88f62b0 42 extern "C" {
<> 128:9bcdf88f62b0 43 #endif
<> 128:9bcdf88f62b0 44
<> 128:9bcdf88f62b0 45 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 46 #include "stm32l1xx_hal_conf.h"
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 49 * @{
<> 128:9bcdf88f62b0 50 */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 /** @addtogroup HAL
<> 128:9bcdf88f62b0 53 * @{
<> 128:9bcdf88f62b0 54 */
<> 128:9bcdf88f62b0 55
<> 128:9bcdf88f62b0 56 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 57 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
<> 128:9bcdf88f62b0 63 * @{
<> 128:9bcdf88f62b0 64 */
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 /** @defgroup SYSCFG_BootMode Boot Mode
<> 128:9bcdf88f62b0 67 * @{
<> 128:9bcdf88f62b0 68 */
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 #define SYSCFG_BOOT_MAINFLASH (0x00000000U)
<> 128:9bcdf88f62b0 71 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
<> 128:9bcdf88f62b0 72 #if defined(FSMC_R_BASE)
<> 128:9bcdf88f62b0 73 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
<> 128:9bcdf88f62b0 74 #endif /* FSMC_R_BASE */
<> 128:9bcdf88f62b0 75 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 /**
<> 128:9bcdf88f62b0 78 * @}
<> 128:9bcdf88f62b0 79 */
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 /**
<> 128:9bcdf88f62b0 82 * @}
<> 128:9bcdf88f62b0 83 */
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 /** @defgroup RI_Constants RI: Routing Interface
<> 128:9bcdf88f62b0 86 * @{
<> 128:9bcdf88f62b0 87 */
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 /** @defgroup RI_InputCapture Input Capture
<> 128:9bcdf88f62b0 90 * @{
<> 128:9bcdf88f62b0 91 */
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
<> 128:9bcdf88f62b0 94 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
<> 128:9bcdf88f62b0 95 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
<> 128:9bcdf88f62b0 96 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /**
<> 128:9bcdf88f62b0 99 * @}
<> 128:9bcdf88f62b0 100 */
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 /** @defgroup TIM_Select TIM Select
<> 128:9bcdf88f62b0 103 * @{
<> 128:9bcdf88f62b0 104 */
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 #define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
<> 128:9bcdf88f62b0 107 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
<> 128:9bcdf88f62b0 108 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
<> 128:9bcdf88f62b0 109 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
<> 128:9bcdf88f62b0 112 ((__TIM__) == TIM_SELECT_TIM2) || \
<> 128:9bcdf88f62b0 113 ((__TIM__) == TIM_SELECT_TIM3) || \
<> 128:9bcdf88f62b0 114 ((__TIM__) == TIM_SELECT_TIM4))
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 /**
<> 128:9bcdf88f62b0 117 * @}
<> 128:9bcdf88f62b0 118 */
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 /** @defgroup RI_InputCaptureRouting Input Capture Routing
<> 128:9bcdf88f62b0 121 * @{
<> 128:9bcdf88f62b0 122 */
<> 128:9bcdf88f62b0 123 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
<> 128:9bcdf88f62b0 124 #define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
<> 128:9bcdf88f62b0 125 #define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
<> 128:9bcdf88f62b0 126 #define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
<> 128:9bcdf88f62b0 127 #define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
<> 128:9bcdf88f62b0 128 #define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
<> 128:9bcdf88f62b0 129 #define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
<> 128:9bcdf88f62b0 130 #define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
<> 128:9bcdf88f62b0 131 #define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
<> 128:9bcdf88f62b0 132 #define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
<> 128:9bcdf88f62b0 133 #define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
<> 128:9bcdf88f62b0 134 #define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
<> 128:9bcdf88f62b0 135 #define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
<> 128:9bcdf88f62b0 136 #define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
<> 128:9bcdf88f62b0 137 #define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
<> 128:9bcdf88f62b0 138 #define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
<> 128:9bcdf88f62b0 139 #define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
<> 128:9bcdf88f62b0 142 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
<> 128:9bcdf88f62b0 143 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
<> 128:9bcdf88f62b0 144 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
<> 128:9bcdf88f62b0 145 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
<> 128:9bcdf88f62b0 146 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
<> 128:9bcdf88f62b0 147 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
<> 128:9bcdf88f62b0 148 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
<> 128:9bcdf88f62b0 149 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
<> 128:9bcdf88f62b0 150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
<> 128:9bcdf88f62b0 151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
<> 128:9bcdf88f62b0 152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
<> 128:9bcdf88f62b0 153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
<> 128:9bcdf88f62b0 154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
<> 128:9bcdf88f62b0 155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
<> 128:9bcdf88f62b0 156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 /**
<> 128:9bcdf88f62b0 159 * @}
<> 128:9bcdf88f62b0 160 */
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /** @defgroup RI_IOSwitch IO Switch
<> 128:9bcdf88f62b0 163 * @{
<> 128:9bcdf88f62b0 164 */
<> 128:9bcdf88f62b0 165 #define RI_ASCR1_REGISTER (0x80000000U)
<> 128:9bcdf88f62b0 166 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
<> 128:9bcdf88f62b0 167 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
<> 128:9bcdf88f62b0 168 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
<> 128:9bcdf88f62b0 169 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
<> 128:9bcdf88f62b0 170 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
<> 128:9bcdf88f62b0 171 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
<> 128:9bcdf88f62b0 172 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
<> 128:9bcdf88f62b0 173 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
<> 128:9bcdf88f62b0 174 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
<> 128:9bcdf88f62b0 175 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
<> 128:9bcdf88f62b0 176 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
<> 128:9bcdf88f62b0 177 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
<> 128:9bcdf88f62b0 178 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
<> 128:9bcdf88f62b0 179 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
<> 128:9bcdf88f62b0 180 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
<> 128:9bcdf88f62b0 181 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
<> 128:9bcdf88f62b0 182 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
<> 128:9bcdf88f62b0 183 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
<> 128:9bcdf88f62b0 184 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
<> 128:9bcdf88f62b0 185 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
<> 128:9bcdf88f62b0 186 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
<> 128:9bcdf88f62b0 187 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
<> 128:9bcdf88f62b0 188 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
<> 128:9bcdf88f62b0 189 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
<> 128:9bcdf88f62b0 190 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
<> 128:9bcdf88f62b0 191 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
<> 128:9bcdf88f62b0 192 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 193 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
<> 128:9bcdf88f62b0 194 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
<> 128:9bcdf88f62b0 195 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
<> 128:9bcdf88f62b0 196 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
<> 128:9bcdf88f62b0 197 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
<> 128:9bcdf88f62b0 198 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 199
<> 128:9bcdf88f62b0 200 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
<> 128:9bcdf88f62b0 201 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
<> 128:9bcdf88f62b0 202 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
<> 128:9bcdf88f62b0 203 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
<> 128:9bcdf88f62b0 204 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
<> 128:9bcdf88f62b0 205 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
<> 128:9bcdf88f62b0 206 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
<> 128:9bcdf88f62b0 207 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
<> 128:9bcdf88f62b0 208 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
<> 128:9bcdf88f62b0 209 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
<> 128:9bcdf88f62b0 210 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
<> 128:9bcdf88f62b0 211 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
<> 128:9bcdf88f62b0 212 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
<> 128:9bcdf88f62b0 213 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 214 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
<> 128:9bcdf88f62b0 215 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 216 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
<> 128:9bcdf88f62b0 217 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
<> 128:9bcdf88f62b0 218 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
<> 128:9bcdf88f62b0 219 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
<> 128:9bcdf88f62b0 220 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
<> 128:9bcdf88f62b0 221 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
<> 128:9bcdf88f62b0 222 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
<> 128:9bcdf88f62b0 223 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
<> 128:9bcdf88f62b0 224 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
<> 128:9bcdf88f62b0 225 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
<> 128:9bcdf88f62b0 226 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 227 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
<> 128:9bcdf88f62b0 228 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
<> 128:9bcdf88f62b0 229 #endif /* RI_ASCR2_CH0b */
<> 128:9bcdf88f62b0 230
<> 128:9bcdf88f62b0 231
<> 128:9bcdf88f62b0 232 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 235 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 236 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 237 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 238 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 239 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 240 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 241 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 242 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 243 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 244 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 245 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 246 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \
<> 128:9bcdf88f62b0 247 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \
<> 128:9bcdf88f62b0 248 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \
<> 128:9bcdf88f62b0 249 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
<> 128:9bcdf88f62b0 250 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
<> 128:9bcdf88f62b0 251 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \
<> 128:9bcdf88f62b0 252 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \
<> 128:9bcdf88f62b0 253 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \
<> 128:9bcdf88f62b0 254 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \
<> 128:9bcdf88f62b0 255 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \
<> 128:9bcdf88f62b0 256 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \
<> 128:9bcdf88f62b0 257 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \
<> 128:9bcdf88f62b0 258 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \
<> 128:9bcdf88f62b0 259 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \
<> 128:9bcdf88f62b0 260 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \
<> 128:9bcdf88f62b0 261 ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 #else /* !RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
<> 128:9bcdf88f62b0 266
<> 128:9bcdf88f62b0 267 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 268 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 269 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 270 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 271 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 272 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 273 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 274 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 275 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 276 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 277 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 278 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 279 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 128:9bcdf88f62b0 280 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 128:9bcdf88f62b0 281 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 128:9bcdf88f62b0 282 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 128:9bcdf88f62b0 283 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 128:9bcdf88f62b0 284 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 128:9bcdf88f62b0 285 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 290 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 291 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 292 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 293 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 294 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 295 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 296 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 297 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 298 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 299 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 300 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 301 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 128:9bcdf88f62b0 302 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 128:9bcdf88f62b0 303 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 128:9bcdf88f62b0 304 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 128:9bcdf88f62b0 305 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 128:9bcdf88f62b0 306 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 128:9bcdf88f62b0 307 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 #endif /* RI_ASCR2_CH0b */
<> 128:9bcdf88f62b0 310 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312 /**
<> 128:9bcdf88f62b0 313 * @}
<> 128:9bcdf88f62b0 314 */
<> 128:9bcdf88f62b0 315
<> 128:9bcdf88f62b0 316 /** @defgroup RI_Pin PIN define
<> 128:9bcdf88f62b0 317 * @{
<> 128:9bcdf88f62b0 318 */
<> 128:9bcdf88f62b0 319 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
<> 128:9bcdf88f62b0 320 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
<> 128:9bcdf88f62b0 321 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
<> 128:9bcdf88f62b0 322 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
<> 128:9bcdf88f62b0 323 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
<> 128:9bcdf88f62b0 324 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
<> 128:9bcdf88f62b0 325 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
<> 128:9bcdf88f62b0 326 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
<> 128:9bcdf88f62b0 327 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
<> 128:9bcdf88f62b0 328 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
<> 128:9bcdf88f62b0 329 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
<> 128:9bcdf88f62b0 330 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
<> 128:9bcdf88f62b0 331 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
<> 128:9bcdf88f62b0 332 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
<> 128:9bcdf88f62b0 333 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
<> 128:9bcdf88f62b0 334 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
<> 128:9bcdf88f62b0 335 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
<> 128:9bcdf88f62b0 336
<> 128:9bcdf88f62b0 337 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
<> 128:9bcdf88f62b0 338
<> 128:9bcdf88f62b0 339 /**
<> 128:9bcdf88f62b0 340 * @}
<> 128:9bcdf88f62b0 341 */
<> 128:9bcdf88f62b0 342
<> 128:9bcdf88f62b0 343 /**
<> 128:9bcdf88f62b0 344 * @}
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 /**
<> 128:9bcdf88f62b0 348 * @}
<> 128:9bcdf88f62b0 349 */
<> 128:9bcdf88f62b0 350
<> 128:9bcdf88f62b0 351 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 352
<> 128:9bcdf88f62b0 353 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 128:9bcdf88f62b0 354 * @{
<> 128:9bcdf88f62b0 355 */
<> 128:9bcdf88f62b0 356
<> 128:9bcdf88f62b0 357 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
<> 128:9bcdf88f62b0 358 * @{
<> 128:9bcdf88f62b0 359 */
<> 128:9bcdf88f62b0 360
<> 128:9bcdf88f62b0 361 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
<> 128:9bcdf88f62b0 362 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 128:9bcdf88f62b0 363 * @{
<> 128:9bcdf88f62b0 364 */
<> 128:9bcdf88f62b0 365
<> 128:9bcdf88f62b0 366 /**
<> 128:9bcdf88f62b0 367 * @brief TIM2 Peripherals Debug mode
<> 128:9bcdf88f62b0 368 */
<> 128:9bcdf88f62b0 369 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 370 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 371 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 372 #endif
<> 128:9bcdf88f62b0 373
<> 128:9bcdf88f62b0 374 /**
<> 128:9bcdf88f62b0 375 * @brief TIM3 Peripherals Debug mode
<> 128:9bcdf88f62b0 376 */
<> 128:9bcdf88f62b0 377 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 378 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 379 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 380 #endif
<> 128:9bcdf88f62b0 381
<> 128:9bcdf88f62b0 382 /**
<> 128:9bcdf88f62b0 383 * @brief TIM4 Peripherals Debug mode
<> 128:9bcdf88f62b0 384 */
<> 128:9bcdf88f62b0 385 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 386 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 387 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 388 #endif
<> 128:9bcdf88f62b0 389
<> 128:9bcdf88f62b0 390 /**
<> 128:9bcdf88f62b0 391 * @brief TIM5 Peripherals Debug mode
<> 128:9bcdf88f62b0 392 */
<> 128:9bcdf88f62b0 393 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 394 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 395 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 396 #endif
<> 128:9bcdf88f62b0 397
<> 128:9bcdf88f62b0 398 /**
<> 128:9bcdf88f62b0 399 * @brief TIM6 Peripherals Debug mode
<> 128:9bcdf88f62b0 400 */
<> 128:9bcdf88f62b0 401 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 402 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 403 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 404 #endif
<> 128:9bcdf88f62b0 405
<> 128:9bcdf88f62b0 406 /**
<> 128:9bcdf88f62b0 407 * @brief TIM7 Peripherals Debug mode
<> 128:9bcdf88f62b0 408 */
<> 128:9bcdf88f62b0 409 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 410 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 411 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 412 #endif
<> 128:9bcdf88f62b0 413
<> 128:9bcdf88f62b0 414 /**
<> 128:9bcdf88f62b0 415 * @brief RTC Peripherals Debug mode
<> 128:9bcdf88f62b0 416 */
<> 128:9bcdf88f62b0 417 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 418 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 419 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 420 #endif
<> 128:9bcdf88f62b0 421
<> 128:9bcdf88f62b0 422 /**
<> 128:9bcdf88f62b0 423 * @brief WWDG Peripherals Debug mode
<> 128:9bcdf88f62b0 424 */
<> 128:9bcdf88f62b0 425 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 426 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 427 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 428 #endif
<> 128:9bcdf88f62b0 429
<> 128:9bcdf88f62b0 430 /**
<> 128:9bcdf88f62b0 431 * @brief IWDG Peripherals Debug mode
<> 128:9bcdf88f62b0 432 */
<> 128:9bcdf88f62b0 433 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 434 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 435 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 436 #endif
<> 128:9bcdf88f62b0 437
<> 128:9bcdf88f62b0 438 /**
<> 128:9bcdf88f62b0 439 * @brief I2C1 Peripherals Debug mode
<> 128:9bcdf88f62b0 440 */
<> 128:9bcdf88f62b0 441 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 442 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 443 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 444 #endif
<> 128:9bcdf88f62b0 445
<> 128:9bcdf88f62b0 446 /**
<> 128:9bcdf88f62b0 447 * @brief I2C2 Peripherals Debug mode
<> 128:9bcdf88f62b0 448 */
<> 128:9bcdf88f62b0 449 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 450 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 451 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 452 #endif
<> 128:9bcdf88f62b0 453
<> 128:9bcdf88f62b0 454 /**
<> 128:9bcdf88f62b0 455 * @brief TIM9 Peripherals Debug mode
<> 128:9bcdf88f62b0 456 */
<> 128:9bcdf88f62b0 457 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 458 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 459 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 460 #endif
<> 128:9bcdf88f62b0 461
<> 128:9bcdf88f62b0 462 /**
<> 128:9bcdf88f62b0 463 * @brief TIM10 Peripherals Debug mode
<> 128:9bcdf88f62b0 464 */
<> 128:9bcdf88f62b0 465 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 466 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 467 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 468 #endif
<> 128:9bcdf88f62b0 469
<> 128:9bcdf88f62b0 470 /**
<> 128:9bcdf88f62b0 471 * @brief TIM11 Peripherals Debug mode
<> 128:9bcdf88f62b0 472 */
<> 128:9bcdf88f62b0 473 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 474 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 475 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 476 #endif
<> 128:9bcdf88f62b0 477
<> 128:9bcdf88f62b0 478
<> 128:9bcdf88f62b0 479 /**
<> 128:9bcdf88f62b0 480 * @}
<> 128:9bcdf88f62b0 481 */
<> 128:9bcdf88f62b0 482
<> 128:9bcdf88f62b0 483 /**
<> 128:9bcdf88f62b0 484 * @}
<> 128:9bcdf88f62b0 485 */
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
<> 128:9bcdf88f62b0 488 * @{
<> 128:9bcdf88f62b0 489 */
<> 128:9bcdf88f62b0 490
<> 128:9bcdf88f62b0 491 /** @defgroup SYSCFG_VrefInt VREFINT configuration
<> 128:9bcdf88f62b0 492 * @{
<> 128:9bcdf88f62b0 493 */
<> 128:9bcdf88f62b0 494
<> 128:9bcdf88f62b0 495 /**
<> 128:9bcdf88f62b0 496 * @brief Enables or disables the output of internal reference voltage
<> 128:9bcdf88f62b0 497 * (VREFINT) on I/O pin.
<> 128:9bcdf88f62b0 498 * The VREFINT output can be routed to any I/O in group 3:
<> 128:9bcdf88f62b0 499 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
<> 128:9bcdf88f62b0 500 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
<> 128:9bcdf88f62b0 501 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
<> 128:9bcdf88f62b0 502 * CH1b (PF11) or CH2b (PF12).
<> 128:9bcdf88f62b0 503 * Note: Comparator peripheral clock must be preliminarility enabled,
<> 128:9bcdf88f62b0 504 * either in COMP user function "HAL_COMP_MspInit()" (should be
<> 128:9bcdf88f62b0 505 * done if comparators are used) or by direct clock enable:
<> 128:9bcdf88f62b0 506 * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
<> 128:9bcdf88f62b0 507 * Note: In addition with this macro, Vrefint output buffer must be
<> 128:9bcdf88f62b0 508 * connected to the selected I/O pin. Refer to macro
<> 128:9bcdf88f62b0 509 * "__HAL_RI_IOSWITCH_CLOSE()".
<> 128:9bcdf88f62b0 510 * @note ENABLE: Internal reference voltage connected to I/O group 3
<> 128:9bcdf88f62b0 511 * @note DISABLE: Internal reference voltage disconnected from I/O group 3
<> 128:9bcdf88f62b0 512 * @retval None
<> 128:9bcdf88f62b0 513 */
<> 128:9bcdf88f62b0 514 #define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 128:9bcdf88f62b0 515 #define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 128:9bcdf88f62b0 516
<> 128:9bcdf88f62b0 517 /**
<> 128:9bcdf88f62b0 518 * @}
<> 128:9bcdf88f62b0 519 */
<> 128:9bcdf88f62b0 520
<> 128:9bcdf88f62b0 521 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
<> 128:9bcdf88f62b0 522 * @{
<> 128:9bcdf88f62b0 523 */
<> 128:9bcdf88f62b0 524
<> 128:9bcdf88f62b0 525 /**
<> 128:9bcdf88f62b0 526 * @brief Main Flash memory mapped at 0x00000000
<> 128:9bcdf88f62b0 527 */
<> 128:9bcdf88f62b0 528 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
<> 128:9bcdf88f62b0 529
<> 128:9bcdf88f62b0 530 /** @brief System Flash memory mapped at 0x00000000
<> 128:9bcdf88f62b0 531 */
<> 128:9bcdf88f62b0 532 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
<> 128:9bcdf88f62b0 533
<> 128:9bcdf88f62b0 534 /** @brief Embedded SRAM mapped at 0x00000000
<> 128:9bcdf88f62b0 535 */
<> 128:9bcdf88f62b0 536 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
<> 128:9bcdf88f62b0 537
<> 128:9bcdf88f62b0 538 #if defined(FSMC_R_BASE)
<> 128:9bcdf88f62b0 539 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
<> 128:9bcdf88f62b0 540 */
<> 128:9bcdf88f62b0 541 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
<> 128:9bcdf88f62b0 542
<> 128:9bcdf88f62b0 543 #endif /* FSMC_R_BASE */
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 /**
<> 128:9bcdf88f62b0 546 * @brief Returns the boot mode as configured by user.
<> 128:9bcdf88f62b0 547 * @retval The boot mode as configured by user. The returned value can be one
<> 128:9bcdf88f62b0 548 * of the following values:
<> 128:9bcdf88f62b0 549 * @arg SYSCFG_BOOT_MAINFLASH
<> 128:9bcdf88f62b0 550 * @arg SYSCFG_BOOT_SYSTEMFLASH
<> 128:9bcdf88f62b0 551 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
<> 128:9bcdf88f62b0 552 * @arg SYSCFG_BOOT_SRAM
<> 128:9bcdf88f62b0 553 */
<> 128:9bcdf88f62b0 554 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
<> 128:9bcdf88f62b0 555
<> 128:9bcdf88f62b0 556 /**
<> 128:9bcdf88f62b0 557 * @}
<> 128:9bcdf88f62b0 558 */
<> 128:9bcdf88f62b0 559
<> 128:9bcdf88f62b0 560 /** @defgroup SYSCFG_USBConfig USB DP line Configuration
<> 128:9bcdf88f62b0 561 * @{
<> 128:9bcdf88f62b0 562 */
<> 128:9bcdf88f62b0 563
<> 128:9bcdf88f62b0 564 /**
<> 128:9bcdf88f62b0 565 * @brief Control the internal pull-up on USB DP line.
<> 128:9bcdf88f62b0 566 */
<> 128:9bcdf88f62b0 567 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 128:9bcdf88f62b0 570
<> 128:9bcdf88f62b0 571 /**
<> 128:9bcdf88f62b0 572 * @}
<> 128:9bcdf88f62b0 573 */
<> 128:9bcdf88f62b0 574
<> 128:9bcdf88f62b0 575 /**
<> 128:9bcdf88f62b0 576 * @}
<> 128:9bcdf88f62b0 577 */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 /** @defgroup RI_Macris RI: Routing Interface
<> 128:9bcdf88f62b0 580 * @{
<> 128:9bcdf88f62b0 581 */
<> 128:9bcdf88f62b0 582
<> 128:9bcdf88f62b0 583 /** @defgroup RI_InputCaputureConfig Input Capture configuration
<> 128:9bcdf88f62b0 584 * @{
<> 128:9bcdf88f62b0 585 */
<> 128:9bcdf88f62b0 586
<> 128:9bcdf88f62b0 587 /**
<> 128:9bcdf88f62b0 588 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 589 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 590 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 591 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 592 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 593 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 594 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 595 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 596 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 597 * e.g.
<> 128:9bcdf88f62b0 598 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
<> 128:9bcdf88f62b0 599 * allows routing of Input capture IC1 of TIM2 to PA4.
<> 128:9bcdf88f62b0 600 * For details about correspondence between RI_INPUTCAPTUREROUTING_x
<> 128:9bcdf88f62b0 601 * and I/O pins refer to the parameters' description in the header file
<> 128:9bcdf88f62b0 602 * or refer to the product reference manual.
<> 128:9bcdf88f62b0 603 * @note Input capture selection bits are not reset by this function.
<> 128:9bcdf88f62b0 604 * To reset input capture selection bits, use SYSCFG_RIDeInit() function.
<> 128:9bcdf88f62b0 605 * @note The I/O should be configured in alternate function mode (AF14) using
<> 128:9bcdf88f62b0 606 * GPIO_PinAFConfig() function.
<> 128:9bcdf88f62b0 607 * @retval None.
<> 128:9bcdf88f62b0 608 */
<> 128:9bcdf88f62b0 609 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 610 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 611 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 612 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 613 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
<> 128:9bcdf88f62b0 614 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
<> 128:9bcdf88f62b0 615 }while(0)
<> 128:9bcdf88f62b0 616
<> 128:9bcdf88f62b0 617 /**
<> 128:9bcdf88f62b0 618 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 619 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 620 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 621 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 622 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 623 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 624 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 625 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 626 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 627 * @retval None.
<> 128:9bcdf88f62b0 628 */
<> 128:9bcdf88f62b0 629 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 630 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 631 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 632 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 633 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
<> 128:9bcdf88f62b0 634 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
<> 128:9bcdf88f62b0 635 }while(0)
<> 128:9bcdf88f62b0 636
<> 128:9bcdf88f62b0 637 /**
<> 128:9bcdf88f62b0 638 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 639 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 640 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 641 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 642 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 643 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 644 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 645 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 646 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 647 * @retval None.
<> 128:9bcdf88f62b0 648 */
<> 128:9bcdf88f62b0 649 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 650 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 651 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 652 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 653 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
<> 128:9bcdf88f62b0 654 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
<> 128:9bcdf88f62b0 655 }while(0)
<> 128:9bcdf88f62b0 656
<> 128:9bcdf88f62b0 657 /**
<> 128:9bcdf88f62b0 658 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 659 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 660 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 661 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 662 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 663 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 664 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 665 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 666 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 667 * @retval None.
<> 128:9bcdf88f62b0 668 */
<> 128:9bcdf88f62b0 669 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 670 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 671 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 672 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 673 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
<> 128:9bcdf88f62b0 674 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
<> 128:9bcdf88f62b0 675 }while(0)
<> 128:9bcdf88f62b0 676
<> 128:9bcdf88f62b0 677 /**
<> 128:9bcdf88f62b0 678 * @}
<> 128:9bcdf88f62b0 679 */
<> 128:9bcdf88f62b0 680
<> 128:9bcdf88f62b0 681 /** @defgroup RI_SwitchControlConfig Switch Control configuration
<> 128:9bcdf88f62b0 682 * @{
<> 128:9bcdf88f62b0 683 */
<> 128:9bcdf88f62b0 684
<> 128:9bcdf88f62b0 685 /**
<> 128:9bcdf88f62b0 686 * @brief Enable or disable the switch control mode.
<> 128:9bcdf88f62b0 687 * @note ENABLE: ADC analog switches closed if the corresponding
<> 128:9bcdf88f62b0 688 * I/O switch is also closed.
<> 128:9bcdf88f62b0 689 * When using COMP1, switch control mode must be enabled.
<> 128:9bcdf88f62b0 690 * @note DISABLE: ADC analog switches open or controlled by the ADC interface.
<> 128:9bcdf88f62b0 691 * When using the ADC for acquisition, switch control mode
<> 128:9bcdf88f62b0 692 * must be disabled.
<> 128:9bcdf88f62b0 693 * @note COMP1 comparator and ADC cannot be used at the same time since
<> 128:9bcdf88f62b0 694 * they share the ADC switch matrix.
<> 128:9bcdf88f62b0 695 * @retval None
<> 128:9bcdf88f62b0 696 */
<> 128:9bcdf88f62b0 697 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 128:9bcdf88f62b0 698
<> 128:9bcdf88f62b0 699 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 /*
<> 128:9bcdf88f62b0 702 * @brief Close or Open the routing interface Input Output switches.
<> 128:9bcdf88f62b0 703 * @param __IOSWITCH__: selects the I/O analog switch number.
<> 128:9bcdf88f62b0 704 * This parameter must be a value of @ref RI_IOSwitch
<> 128:9bcdf88f62b0 705 * @retval None
<> 128:9bcdf88f62b0 706 */
<> 128:9bcdf88f62b0 707 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 128:9bcdf88f62b0 708 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 128:9bcdf88f62b0 709 { \
<> 128:9bcdf88f62b0 710 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 128:9bcdf88f62b0 711 } \
<> 128:9bcdf88f62b0 712 else \
<> 128:9bcdf88f62b0 713 { \
<> 128:9bcdf88f62b0 714 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 128:9bcdf88f62b0 715 } \
<> 128:9bcdf88f62b0 716 }while(0)
<> 128:9bcdf88f62b0 717
<> 128:9bcdf88f62b0 718 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 128:9bcdf88f62b0 719 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 128:9bcdf88f62b0 720 { \
<> 128:9bcdf88f62b0 721 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 128:9bcdf88f62b0 722 } \
<> 128:9bcdf88f62b0 723 else \
<> 128:9bcdf88f62b0 724 { \
<> 128:9bcdf88f62b0 725 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 128:9bcdf88f62b0 726 } \
<> 128:9bcdf88f62b0 727 }while(0)
<> 128:9bcdf88f62b0 728
<> 128:9bcdf88f62b0 729 #if defined (COMP_CSR_SW1)
<> 128:9bcdf88f62b0 730 /**
<> 128:9bcdf88f62b0 731 * @brief Close or open the internal switch COMP1_SW1.
<> 128:9bcdf88f62b0 732 * This switch connects I/O pin PC3 (can be used as ADC channel 13)
<> 128:9bcdf88f62b0 733 * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
<> 128:9bcdf88f62b0 734 * 26) and COMP1 non-inverting input.
<> 128:9bcdf88f62b0 735 * Pin PC3 connection depends on another switch setting, refer to
<> 128:9bcdf88f62b0 736 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
<> 128:9bcdf88f62b0 737 * @retval None.
<> 128:9bcdf88f62b0 738 */
<> 128:9bcdf88f62b0 739 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
<> 128:9bcdf88f62b0 740
<> 128:9bcdf88f62b0 741 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
<> 128:9bcdf88f62b0 742 #endif /* COMP_CSR_SW1 */
<> 128:9bcdf88f62b0 743
<> 128:9bcdf88f62b0 744 /**
<> 128:9bcdf88f62b0 745 * @}
<> 128:9bcdf88f62b0 746 */
<> 128:9bcdf88f62b0 747
<> 128:9bcdf88f62b0 748 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
<> 128:9bcdf88f62b0 749 * @{
<> 128:9bcdf88f62b0 750 */
<> 128:9bcdf88f62b0 751
<> 128:9bcdf88f62b0 752 /**
<> 128:9bcdf88f62b0 753 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
<> 128:9bcdf88f62b0 754 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 755 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 756 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 757 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 758 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 759 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 760 * @retval None
<> 128:9bcdf88f62b0 761 */
<> 128:9bcdf88f62b0 762 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 763 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 128:9bcdf88f62b0 764 } while(0)
<> 128:9bcdf88f62b0 765
<> 128:9bcdf88f62b0 766 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 767 SET_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 128:9bcdf88f62b0 768 } while(0)
<> 128:9bcdf88f62b0 769
<> 128:9bcdf88f62b0 770 /**
<> 128:9bcdf88f62b0 771 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
<> 128:9bcdf88f62b0 772 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 773 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 774 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 775 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 776 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 777 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 778 * @retval None
<> 128:9bcdf88f62b0 779 */
<> 128:9bcdf88f62b0 780 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 781 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 782 } while(0)
<> 128:9bcdf88f62b0 783
<> 128:9bcdf88f62b0 784 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 785 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 786 } while(0)
<> 128:9bcdf88f62b0 787
<> 128:9bcdf88f62b0 788 /**
<> 128:9bcdf88f62b0 789 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
<> 128:9bcdf88f62b0 790 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 791 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 792 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 793 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 794 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 795 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 796 * @retval None
<> 128:9bcdf88f62b0 797 */
<> 128:9bcdf88f62b0 798 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 799 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 128:9bcdf88f62b0 800 } while(0)
<> 128:9bcdf88f62b0 801
<> 128:9bcdf88f62b0 802 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 803 SET_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 128:9bcdf88f62b0 804 } while(0)
<> 128:9bcdf88f62b0 805
<> 128:9bcdf88f62b0 806 /**
<> 128:9bcdf88f62b0 807 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
<> 128:9bcdf88f62b0 808 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 809 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 810 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 811 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 812 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 813 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 814 * @retval None
<> 128:9bcdf88f62b0 815 */
<> 128:9bcdf88f62b0 816 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 817 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 818 } while(0)
<> 128:9bcdf88f62b0 819
<> 128:9bcdf88f62b0 820 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 821 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 822 } while(0)
<> 128:9bcdf88f62b0 823
<> 128:9bcdf88f62b0 824 #if defined (GPIOE_BASE)
<> 128:9bcdf88f62b0 825
<> 128:9bcdf88f62b0 826 /**
<> 128:9bcdf88f62b0 827 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
<> 128:9bcdf88f62b0 828 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 829 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 830 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 831 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 832 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 833 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 834 * @retval None
<> 128:9bcdf88f62b0 835 */
<> 128:9bcdf88f62b0 836 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 837 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 128:9bcdf88f62b0 838 } while(0)
<> 128:9bcdf88f62b0 839
<> 128:9bcdf88f62b0 840 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 841 SET_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 128:9bcdf88f62b0 842 } while(0)
<> 128:9bcdf88f62b0 843
<> 128:9bcdf88f62b0 844 #endif /* GPIOE_BASE */
<> 128:9bcdf88f62b0 845
<> 128:9bcdf88f62b0 846 #if defined(GPIOF_BASE) || defined(GPIOG_BASE)
<> 128:9bcdf88f62b0 847
<> 128:9bcdf88f62b0 848 /**
<> 128:9bcdf88f62b0 849 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
<> 128:9bcdf88f62b0 850 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 851 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 852 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 853 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 854 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 855 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 856 * @retval None
<> 128:9bcdf88f62b0 857 */
<> 128:9bcdf88f62b0 858 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 859 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 860 } while(0)
<> 128:9bcdf88f62b0 861
<> 128:9bcdf88f62b0 862 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 863 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 864 } while(0)
<> 128:9bcdf88f62b0 865
<> 128:9bcdf88f62b0 866 /**
<> 128:9bcdf88f62b0 867 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
<> 128:9bcdf88f62b0 868 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 869 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 870 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 871 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 872 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 873 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 874 * @retval None
<> 128:9bcdf88f62b0 875 */
<> 128:9bcdf88f62b0 876 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 877 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 128:9bcdf88f62b0 878 } while(0)
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 881 SET_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 128:9bcdf88f62b0 882 } while(0)
<> 128:9bcdf88f62b0 883
<> 128:9bcdf88f62b0 884 #endif /* GPIOF_BASE || GPIOG_BASE */
<> 128:9bcdf88f62b0 885
<> 128:9bcdf88f62b0 886 /**
<> 128:9bcdf88f62b0 887 * @}
<> 128:9bcdf88f62b0 888 */
<> 128:9bcdf88f62b0 889
<> 128:9bcdf88f62b0 890 /**
<> 128:9bcdf88f62b0 891 * @}
<> 128:9bcdf88f62b0 892 */
<> 128:9bcdf88f62b0 893
<> 128:9bcdf88f62b0 894 /**
<> 128:9bcdf88f62b0 895 * @}
<> 128:9bcdf88f62b0 896 */
<> 128:9bcdf88f62b0 897
<> 128:9bcdf88f62b0 898 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 899
<> 128:9bcdf88f62b0 900 /** @addtogroup HAL_Exported_Functions
<> 128:9bcdf88f62b0 901 * @{
<> 128:9bcdf88f62b0 902 */
<> 128:9bcdf88f62b0 903
<> 128:9bcdf88f62b0 904 /** @addtogroup HAL_Exported_Functions_Group1
<> 128:9bcdf88f62b0 905 * @{
<> 128:9bcdf88f62b0 906 */
<> 128:9bcdf88f62b0 907
<> 128:9bcdf88f62b0 908 /* Initialization and de-initialization functions ******************************/
<> 128:9bcdf88f62b0 909 HAL_StatusTypeDef HAL_Init(void);
<> 128:9bcdf88f62b0 910 HAL_StatusTypeDef HAL_DeInit(void);
<> 128:9bcdf88f62b0 911 void HAL_MspInit(void);
<> 128:9bcdf88f62b0 912 void HAL_MspDeInit(void);
<> 128:9bcdf88f62b0 913 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 128:9bcdf88f62b0 914
<> 128:9bcdf88f62b0 915 /**
<> 128:9bcdf88f62b0 916 * @}
<> 128:9bcdf88f62b0 917 */
<> 128:9bcdf88f62b0 918
<> 128:9bcdf88f62b0 919 /** @addtogroup HAL_Exported_Functions_Group2
<> 128:9bcdf88f62b0 920 * @{
<> 128:9bcdf88f62b0 921 */
<> 128:9bcdf88f62b0 922
<> 128:9bcdf88f62b0 923 /* Peripheral Control functions ************************************************/
<> 128:9bcdf88f62b0 924 void HAL_IncTick(void);
<> 128:9bcdf88f62b0 925 void HAL_Delay(__IO uint32_t Delay);
<> 128:9bcdf88f62b0 926 uint32_t HAL_GetTick(void);
<> 128:9bcdf88f62b0 927 void HAL_SuspendTick(void);
<> 128:9bcdf88f62b0 928 void HAL_ResumeTick(void);
<> 128:9bcdf88f62b0 929 uint32_t HAL_GetHalVersion(void);
<> 128:9bcdf88f62b0 930 uint32_t HAL_GetREVID(void);
<> 128:9bcdf88f62b0 931 uint32_t HAL_GetDEVID(void);
<> 128:9bcdf88f62b0 932 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 128:9bcdf88f62b0 933 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 128:9bcdf88f62b0 934 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 128:9bcdf88f62b0 935 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 128:9bcdf88f62b0 936 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 128:9bcdf88f62b0 937 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 128:9bcdf88f62b0 938
<> 128:9bcdf88f62b0 939 /**
<> 128:9bcdf88f62b0 940 * @}
<> 128:9bcdf88f62b0 941 */
<> 128:9bcdf88f62b0 942
<> 128:9bcdf88f62b0 943 /**
<> 128:9bcdf88f62b0 944 * @}
<> 128:9bcdf88f62b0 945 */
<> 128:9bcdf88f62b0 946
<> 128:9bcdf88f62b0 947
<> 128:9bcdf88f62b0 948 /**
<> 128:9bcdf88f62b0 949 * @}
<> 128:9bcdf88f62b0 950 */
<> 128:9bcdf88f62b0 951
<> 128:9bcdf88f62b0 952 /**
<> 128:9bcdf88f62b0 953 * @}
<> 128:9bcdf88f62b0 954 */
<> 128:9bcdf88f62b0 955
<> 128:9bcdf88f62b0 956 #ifdef __cplusplus
<> 128:9bcdf88f62b0 957 }
<> 128:9bcdf88f62b0 958 #endif
<> 128:9bcdf88f62b0 959
<> 128:9bcdf88f62b0 960 #endif /* __STM32L1xx_HAL_H */
<> 128:9bcdf88f62b0 961
<> 128:9bcdf88f62b0 962 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/