mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief This file contains all the functions prototypes for the HAL
<> 128:9bcdf88f62b0 8 * module driver.
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 * @attention
<> 128:9bcdf88f62b0 11 *
<> 128:9bcdf88f62b0 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 15 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 17 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 19 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 20 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 22 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 23 * without specific prior written permission.
<> 128:9bcdf88f62b0 24 *
<> 128:9bcdf88f62b0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 35 *
<> 128:9bcdf88f62b0 36 ******************************************************************************
<> 128:9bcdf88f62b0 37 */
<> 128:9bcdf88f62b0 38
<> 128:9bcdf88f62b0 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 40 #ifndef __STM32L1xx_HAL_H
<> 128:9bcdf88f62b0 41 #define __STM32L1xx_HAL_H
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 #ifdef __cplusplus
<> 128:9bcdf88f62b0 44 extern "C" {
<> 128:9bcdf88f62b0 45 #endif
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 48 #include "stm32l1xx_hal_conf.h"
<> 128:9bcdf88f62b0 49
<> 128:9bcdf88f62b0 50 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 51 * @{
<> 128:9bcdf88f62b0 52 */
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /** @addtogroup HAL
<> 128:9bcdf88f62b0 55 * @{
<> 128:9bcdf88f62b0 56 */
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 59 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 128:9bcdf88f62b0 61 * @{
<> 128:9bcdf88f62b0 62 */
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
<> 128:9bcdf88f62b0 65 * @{
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 /** @defgroup SYSCFG_BootMode Boot Mode
<> 128:9bcdf88f62b0 69 * @{
<> 128:9bcdf88f62b0 70 */
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 #define SYSCFG_BOOT_MAINFLASH (0x00000000U)
<> 128:9bcdf88f62b0 73 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
<> 128:9bcdf88f62b0 74 #if defined(FSMC_R_BASE)
<> 128:9bcdf88f62b0 75 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
<> 128:9bcdf88f62b0 76 #endif /* FSMC_R_BASE */
<> 128:9bcdf88f62b0 77 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /**
<> 128:9bcdf88f62b0 80 * @}
<> 128:9bcdf88f62b0 81 */
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 /**
<> 128:9bcdf88f62b0 84 * @}
<> 128:9bcdf88f62b0 85 */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 /** @defgroup RI_Constants RI: Routing Interface
<> 128:9bcdf88f62b0 88 * @{
<> 128:9bcdf88f62b0 89 */
<> 128:9bcdf88f62b0 90
<> 128:9bcdf88f62b0 91 /** @defgroup RI_InputCapture Input Capture
<> 128:9bcdf88f62b0 92 * @{
<> 128:9bcdf88f62b0 93 */
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
<> 128:9bcdf88f62b0 96 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
<> 128:9bcdf88f62b0 97 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
<> 128:9bcdf88f62b0 98 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /**
<> 128:9bcdf88f62b0 101 * @}
<> 128:9bcdf88f62b0 102 */
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104 /** @defgroup TIM_Select TIM Select
<> 128:9bcdf88f62b0 105 * @{
<> 128:9bcdf88f62b0 106 */
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 #define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
<> 128:9bcdf88f62b0 109 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
<> 128:9bcdf88f62b0 110 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
<> 128:9bcdf88f62b0 111 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
<> 128:9bcdf88f62b0 114 ((__TIM__) == TIM_SELECT_TIM2) || \
<> 128:9bcdf88f62b0 115 ((__TIM__) == TIM_SELECT_TIM3) || \
<> 128:9bcdf88f62b0 116 ((__TIM__) == TIM_SELECT_TIM4))
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 /**
<> 128:9bcdf88f62b0 119 * @}
<> 128:9bcdf88f62b0 120 */
<> 128:9bcdf88f62b0 121
<> 128:9bcdf88f62b0 122 /** @defgroup RI_InputCaptureRouting Input Capture Routing
<> 128:9bcdf88f62b0 123 * @{
<> 128:9bcdf88f62b0 124 */
<> 128:9bcdf88f62b0 125 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
<> 128:9bcdf88f62b0 126 #define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
<> 128:9bcdf88f62b0 127 #define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
<> 128:9bcdf88f62b0 128 #define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
<> 128:9bcdf88f62b0 129 #define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
<> 128:9bcdf88f62b0 130 #define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
<> 128:9bcdf88f62b0 131 #define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
<> 128:9bcdf88f62b0 132 #define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
<> 128:9bcdf88f62b0 133 #define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
<> 128:9bcdf88f62b0 134 #define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
<> 128:9bcdf88f62b0 135 #define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
<> 128:9bcdf88f62b0 136 #define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
<> 128:9bcdf88f62b0 137 #define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
<> 128:9bcdf88f62b0 138 #define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
<> 128:9bcdf88f62b0 139 #define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
<> 128:9bcdf88f62b0 140 #define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
<> 128:9bcdf88f62b0 141 #define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
<> 128:9bcdf88f62b0 144 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
<> 128:9bcdf88f62b0 145 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
<> 128:9bcdf88f62b0 146 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
<> 128:9bcdf88f62b0 147 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
<> 128:9bcdf88f62b0 148 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
<> 128:9bcdf88f62b0 149 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
<> 128:9bcdf88f62b0 150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
<> 128:9bcdf88f62b0 151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
<> 128:9bcdf88f62b0 152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
<> 128:9bcdf88f62b0 153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
<> 128:9bcdf88f62b0 154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
<> 128:9bcdf88f62b0 155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
<> 128:9bcdf88f62b0 156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
<> 128:9bcdf88f62b0 157 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
<> 128:9bcdf88f62b0 158 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 /**
<> 128:9bcdf88f62b0 161 * @}
<> 128:9bcdf88f62b0 162 */
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** @defgroup RI_IOSwitch IO Switch
<> 128:9bcdf88f62b0 165 * @{
<> 128:9bcdf88f62b0 166 */
<> 128:9bcdf88f62b0 167 #define RI_ASCR1_REGISTER (0x80000000U)
<> 128:9bcdf88f62b0 168 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
<> 128:9bcdf88f62b0 169 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
<> 128:9bcdf88f62b0 170 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
<> 128:9bcdf88f62b0 171 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
<> 128:9bcdf88f62b0 172 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
<> 128:9bcdf88f62b0 173 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
<> 128:9bcdf88f62b0 174 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
<> 128:9bcdf88f62b0 175 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
<> 128:9bcdf88f62b0 176 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
<> 128:9bcdf88f62b0 177 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
<> 128:9bcdf88f62b0 178 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
<> 128:9bcdf88f62b0 179 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
<> 128:9bcdf88f62b0 180 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
<> 128:9bcdf88f62b0 181 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
<> 128:9bcdf88f62b0 182 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
<> 128:9bcdf88f62b0 183 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
<> 128:9bcdf88f62b0 184 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
<> 128:9bcdf88f62b0 185 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
<> 128:9bcdf88f62b0 186 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
<> 128:9bcdf88f62b0 187 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
<> 128:9bcdf88f62b0 188 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
<> 128:9bcdf88f62b0 189 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
<> 128:9bcdf88f62b0 190 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
<> 128:9bcdf88f62b0 191 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
<> 128:9bcdf88f62b0 192 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
<> 128:9bcdf88f62b0 193 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
<> 128:9bcdf88f62b0 194 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 195 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
<> 128:9bcdf88f62b0 196 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
<> 128:9bcdf88f62b0 197 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
<> 128:9bcdf88f62b0 198 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
<> 128:9bcdf88f62b0 199 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
<> 128:9bcdf88f62b0 200 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
<> 128:9bcdf88f62b0 203 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
<> 128:9bcdf88f62b0 204 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
<> 128:9bcdf88f62b0 205 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
<> 128:9bcdf88f62b0 206 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
<> 128:9bcdf88f62b0 207 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
<> 128:9bcdf88f62b0 208 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
<> 128:9bcdf88f62b0 209 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
<> 128:9bcdf88f62b0 210 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
<> 128:9bcdf88f62b0 211 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
<> 128:9bcdf88f62b0 212 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
<> 128:9bcdf88f62b0 213 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
<> 128:9bcdf88f62b0 214 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
<> 128:9bcdf88f62b0 215 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 216 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
<> 128:9bcdf88f62b0 217 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 218 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
<> 128:9bcdf88f62b0 219 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
<> 128:9bcdf88f62b0 220 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
<> 128:9bcdf88f62b0 221 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
<> 128:9bcdf88f62b0 222 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
<> 128:9bcdf88f62b0 223 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
<> 128:9bcdf88f62b0 224 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
<> 128:9bcdf88f62b0 225 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
<> 128:9bcdf88f62b0 226 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
<> 128:9bcdf88f62b0 227 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
<> 128:9bcdf88f62b0 228 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 229 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
<> 128:9bcdf88f62b0 230 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
<> 128:9bcdf88f62b0 231 #endif /* RI_ASCR2_CH0b */
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 237 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 238 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 239 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 240 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 241 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 242 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 243 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 244 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 245 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 246 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 247 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 248 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \
<> 128:9bcdf88f62b0 249 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \
<> 128:9bcdf88f62b0 250 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \
<> 128:9bcdf88f62b0 251 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
<> 128:9bcdf88f62b0 252 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
<> 128:9bcdf88f62b0 253 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \
<> 128:9bcdf88f62b0 254 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \
<> 128:9bcdf88f62b0 255 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \
<> 128:9bcdf88f62b0 256 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \
<> 128:9bcdf88f62b0 257 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \
<> 128:9bcdf88f62b0 258 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \
<> 128:9bcdf88f62b0 259 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \
<> 128:9bcdf88f62b0 260 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \
<> 128:9bcdf88f62b0 261 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \
<> 128:9bcdf88f62b0 262 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \
<> 128:9bcdf88f62b0 263 ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 #else /* !RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 266
<> 128:9bcdf88f62b0 267 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
<> 128:9bcdf88f62b0 268
<> 128:9bcdf88f62b0 269 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 270 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 271 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 272 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 273 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 274 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 275 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 276 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 277 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 278 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 279 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 280 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 281 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 128:9bcdf88f62b0 282 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 128:9bcdf88f62b0 283 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 128:9bcdf88f62b0 284 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 128:9bcdf88f62b0 285 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 128:9bcdf88f62b0 286 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 128:9bcdf88f62b0 287 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */
<> 128:9bcdf88f62b0 290
<> 128:9bcdf88f62b0 291 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
<> 128:9bcdf88f62b0 292 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
<> 128:9bcdf88f62b0 293 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
<> 128:9bcdf88f62b0 294 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
<> 128:9bcdf88f62b0 295 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
<> 128:9bcdf88f62b0 296 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
<> 128:9bcdf88f62b0 297 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
<> 128:9bcdf88f62b0 298 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
<> 128:9bcdf88f62b0 299 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
<> 128:9bcdf88f62b0 300 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
<> 128:9bcdf88f62b0 301 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
<> 128:9bcdf88f62b0 302 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
<> 128:9bcdf88f62b0 303 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
<> 128:9bcdf88f62b0 304 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
<> 128:9bcdf88f62b0 305 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
<> 128:9bcdf88f62b0 306 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
<> 128:9bcdf88f62b0 307 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
<> 128:9bcdf88f62b0 308 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
<> 128:9bcdf88f62b0 309 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
<> 128:9bcdf88f62b0 310
<> 128:9bcdf88f62b0 311 #endif /* RI_ASCR2_CH0b */
<> 128:9bcdf88f62b0 312 #endif /* RI_ASCR2_CH1b */
<> 128:9bcdf88f62b0 313
<> 128:9bcdf88f62b0 314 /**
<> 128:9bcdf88f62b0 315 * @}
<> 128:9bcdf88f62b0 316 */
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 /** @defgroup RI_Pin PIN define
<> 128:9bcdf88f62b0 319 * @{
<> 128:9bcdf88f62b0 320 */
<> 128:9bcdf88f62b0 321 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
<> 128:9bcdf88f62b0 322 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
<> 128:9bcdf88f62b0 323 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
<> 128:9bcdf88f62b0 324 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
<> 128:9bcdf88f62b0 325 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
<> 128:9bcdf88f62b0 326 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
<> 128:9bcdf88f62b0 327 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
<> 128:9bcdf88f62b0 328 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
<> 128:9bcdf88f62b0 329 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
<> 128:9bcdf88f62b0 330 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
<> 128:9bcdf88f62b0 331 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
<> 128:9bcdf88f62b0 332 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
<> 128:9bcdf88f62b0 333 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
<> 128:9bcdf88f62b0 334 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
<> 128:9bcdf88f62b0 335 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
<> 128:9bcdf88f62b0 336 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
<> 128:9bcdf88f62b0 337 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
<> 128:9bcdf88f62b0 338
<> 128:9bcdf88f62b0 339 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
<> 128:9bcdf88f62b0 340
<> 128:9bcdf88f62b0 341 /**
<> 128:9bcdf88f62b0 342 * @}
<> 128:9bcdf88f62b0 343 */
<> 128:9bcdf88f62b0 344
<> 128:9bcdf88f62b0 345 /**
<> 128:9bcdf88f62b0 346 * @}
<> 128:9bcdf88f62b0 347 */
<> 128:9bcdf88f62b0 348
<> 128:9bcdf88f62b0 349 /**
<> 128:9bcdf88f62b0 350 * @}
<> 128:9bcdf88f62b0 351 */
<> 128:9bcdf88f62b0 352
<> 128:9bcdf88f62b0 353 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 354
<> 128:9bcdf88f62b0 355 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 128:9bcdf88f62b0 356 * @{
<> 128:9bcdf88f62b0 357 */
<> 128:9bcdf88f62b0 358
<> 128:9bcdf88f62b0 359 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
<> 128:9bcdf88f62b0 360 * @{
<> 128:9bcdf88f62b0 361 */
<> 128:9bcdf88f62b0 362
<> 128:9bcdf88f62b0 363 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
<> 128:9bcdf88f62b0 364 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 128:9bcdf88f62b0 365 * @{
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367
<> 128:9bcdf88f62b0 368 /**
<> 128:9bcdf88f62b0 369 * @brief TIM2 Peripherals Debug mode
<> 128:9bcdf88f62b0 370 */
<> 128:9bcdf88f62b0 371 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 372 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 373 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 128:9bcdf88f62b0 374 #endif
<> 128:9bcdf88f62b0 375
<> 128:9bcdf88f62b0 376 /**
<> 128:9bcdf88f62b0 377 * @brief TIM3 Peripherals Debug mode
<> 128:9bcdf88f62b0 378 */
<> 128:9bcdf88f62b0 379 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 380 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 381 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 128:9bcdf88f62b0 382 #endif
<> 128:9bcdf88f62b0 383
<> 128:9bcdf88f62b0 384 /**
<> 128:9bcdf88f62b0 385 * @brief TIM4 Peripherals Debug mode
<> 128:9bcdf88f62b0 386 */
<> 128:9bcdf88f62b0 387 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 388 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 389 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 128:9bcdf88f62b0 390 #endif
<> 128:9bcdf88f62b0 391
<> 128:9bcdf88f62b0 392 /**
<> 128:9bcdf88f62b0 393 * @brief TIM5 Peripherals Debug mode
<> 128:9bcdf88f62b0 394 */
<> 128:9bcdf88f62b0 395 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 396 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 397 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 128:9bcdf88f62b0 398 #endif
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 /**
<> 128:9bcdf88f62b0 401 * @brief TIM6 Peripherals Debug mode
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 404 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 405 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 128:9bcdf88f62b0 406 #endif
<> 128:9bcdf88f62b0 407
<> 128:9bcdf88f62b0 408 /**
<> 128:9bcdf88f62b0 409 * @brief TIM7 Peripherals Debug mode
<> 128:9bcdf88f62b0 410 */
<> 128:9bcdf88f62b0 411 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 412 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 413 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 128:9bcdf88f62b0 414 #endif
<> 128:9bcdf88f62b0 415
<> 128:9bcdf88f62b0 416 /**
<> 128:9bcdf88f62b0 417 * @brief RTC Peripherals Debug mode
<> 128:9bcdf88f62b0 418 */
<> 128:9bcdf88f62b0 419 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 420 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 421 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 128:9bcdf88f62b0 422 #endif
<> 128:9bcdf88f62b0 423
<> 128:9bcdf88f62b0 424 /**
<> 128:9bcdf88f62b0 425 * @brief WWDG Peripherals Debug mode
<> 128:9bcdf88f62b0 426 */
<> 128:9bcdf88f62b0 427 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 428 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 429 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 128:9bcdf88f62b0 430 #endif
<> 128:9bcdf88f62b0 431
<> 128:9bcdf88f62b0 432 /**
<> 128:9bcdf88f62b0 433 * @brief IWDG Peripherals Debug mode
<> 128:9bcdf88f62b0 434 */
<> 128:9bcdf88f62b0 435 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 436 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 437 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 128:9bcdf88f62b0 438 #endif
<> 128:9bcdf88f62b0 439
<> 128:9bcdf88f62b0 440 /**
<> 128:9bcdf88f62b0 441 * @brief I2C1 Peripherals Debug mode
<> 128:9bcdf88f62b0 442 */
<> 128:9bcdf88f62b0 443 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 444 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 445 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 446 #endif
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 /**
<> 128:9bcdf88f62b0 449 * @brief I2C2 Peripherals Debug mode
<> 128:9bcdf88f62b0 450 */
<> 128:9bcdf88f62b0 451 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 452 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 453 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 128:9bcdf88f62b0 454 #endif
<> 128:9bcdf88f62b0 455
<> 128:9bcdf88f62b0 456 /**
<> 128:9bcdf88f62b0 457 * @brief TIM9 Peripherals Debug mode
<> 128:9bcdf88f62b0 458 */
<> 128:9bcdf88f62b0 459 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 460 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 461 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
<> 128:9bcdf88f62b0 462 #endif
<> 128:9bcdf88f62b0 463
<> 128:9bcdf88f62b0 464 /**
<> 128:9bcdf88f62b0 465 * @brief TIM10 Peripherals Debug mode
<> 128:9bcdf88f62b0 466 */
<> 128:9bcdf88f62b0 467 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 468 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 469 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
<> 128:9bcdf88f62b0 470 #endif
<> 128:9bcdf88f62b0 471
<> 128:9bcdf88f62b0 472 /**
<> 128:9bcdf88f62b0 473 * @brief TIM11 Peripherals Debug mode
<> 128:9bcdf88f62b0 474 */
<> 128:9bcdf88f62b0 475 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 476 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 477 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
<> 128:9bcdf88f62b0 478 #endif
<> 128:9bcdf88f62b0 479
<> 128:9bcdf88f62b0 480
<> 128:9bcdf88f62b0 481 /**
<> 128:9bcdf88f62b0 482 * @}
<> 128:9bcdf88f62b0 483 */
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485 /**
<> 128:9bcdf88f62b0 486 * @}
<> 128:9bcdf88f62b0 487 */
<> 128:9bcdf88f62b0 488
<> 128:9bcdf88f62b0 489 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
<> 128:9bcdf88f62b0 490 * @{
<> 128:9bcdf88f62b0 491 */
<> 128:9bcdf88f62b0 492
<> 128:9bcdf88f62b0 493 /** @defgroup SYSCFG_VrefInt VREFINT configuration
<> 128:9bcdf88f62b0 494 * @{
<> 128:9bcdf88f62b0 495 */
<> 128:9bcdf88f62b0 496
<> 128:9bcdf88f62b0 497 /**
<> 128:9bcdf88f62b0 498 * @brief Enables or disables the output of internal reference voltage
<> 128:9bcdf88f62b0 499 * (VREFINT) on I/O pin.
<> 128:9bcdf88f62b0 500 * The VREFINT output can be routed to any I/O in group 3:
<> 128:9bcdf88f62b0 501 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
<> 128:9bcdf88f62b0 502 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
<> 128:9bcdf88f62b0 503 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
<> 128:9bcdf88f62b0 504 * CH1b (PF11) or CH2b (PF12).
<> 128:9bcdf88f62b0 505 * Note: Comparator peripheral clock must be preliminarility enabled,
<> 128:9bcdf88f62b0 506 * either in COMP user function "HAL_COMP_MspInit()" (should be
<> 128:9bcdf88f62b0 507 * done if comparators are used) or by direct clock enable:
<> 128:9bcdf88f62b0 508 * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
<> 128:9bcdf88f62b0 509 * Note: In addition with this macro, Vrefint output buffer must be
<> 128:9bcdf88f62b0 510 * connected to the selected I/O pin. Refer to macro
<> 128:9bcdf88f62b0 511 * "__HAL_RI_IOSWITCH_CLOSE()".
<> 128:9bcdf88f62b0 512 * @note ENABLE: Internal reference voltage connected to I/O group 3
<> 128:9bcdf88f62b0 513 * @note DISABLE: Internal reference voltage disconnected from I/O group 3
<> 128:9bcdf88f62b0 514 * @retval None
<> 128:9bcdf88f62b0 515 */
<> 128:9bcdf88f62b0 516 #define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 128:9bcdf88f62b0 517 #define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
<> 128:9bcdf88f62b0 518
<> 128:9bcdf88f62b0 519 /**
<> 128:9bcdf88f62b0 520 * @}
<> 128:9bcdf88f62b0 521 */
<> 128:9bcdf88f62b0 522
<> 128:9bcdf88f62b0 523 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
<> 128:9bcdf88f62b0 524 * @{
<> 128:9bcdf88f62b0 525 */
<> 128:9bcdf88f62b0 526
<> 128:9bcdf88f62b0 527 /**
<> 128:9bcdf88f62b0 528 * @brief Main Flash memory mapped at 0x00000000
<> 128:9bcdf88f62b0 529 */
<> 128:9bcdf88f62b0 530 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
<> 128:9bcdf88f62b0 531
<> 128:9bcdf88f62b0 532 /** @brief System Flash memory mapped at 0x00000000
<> 128:9bcdf88f62b0 533 */
<> 128:9bcdf88f62b0 534 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
<> 128:9bcdf88f62b0 535
<> 128:9bcdf88f62b0 536 /** @brief Embedded SRAM mapped at 0x00000000
<> 128:9bcdf88f62b0 537 */
<> 128:9bcdf88f62b0 538 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
<> 128:9bcdf88f62b0 539
<> 128:9bcdf88f62b0 540 #if defined(FSMC_R_BASE)
<> 128:9bcdf88f62b0 541 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
<> 128:9bcdf88f62b0 542 */
<> 128:9bcdf88f62b0 543 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 #endif /* FSMC_R_BASE */
<> 128:9bcdf88f62b0 546
<> 128:9bcdf88f62b0 547 /**
<> 128:9bcdf88f62b0 548 * @brief Returns the boot mode as configured by user.
<> 128:9bcdf88f62b0 549 * @retval The boot mode as configured by user. The returned value can be one
<> 128:9bcdf88f62b0 550 * of the following values:
<> 128:9bcdf88f62b0 551 * @arg SYSCFG_BOOT_MAINFLASH
<> 128:9bcdf88f62b0 552 * @arg SYSCFG_BOOT_SYSTEMFLASH
<> 128:9bcdf88f62b0 553 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
<> 128:9bcdf88f62b0 554 * @arg SYSCFG_BOOT_SRAM
<> 128:9bcdf88f62b0 555 */
<> 128:9bcdf88f62b0 556 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
<> 128:9bcdf88f62b0 557
<> 128:9bcdf88f62b0 558 /**
<> 128:9bcdf88f62b0 559 * @}
<> 128:9bcdf88f62b0 560 */
<> 128:9bcdf88f62b0 561
<> 128:9bcdf88f62b0 562 /** @defgroup SYSCFG_USBConfig USB DP line Configuration
<> 128:9bcdf88f62b0 563 * @{
<> 128:9bcdf88f62b0 564 */
<> 128:9bcdf88f62b0 565
<> 128:9bcdf88f62b0 566 /**
<> 128:9bcdf88f62b0 567 * @brief Control the internal pull-up on USB DP line.
<> 128:9bcdf88f62b0 568 */
<> 128:9bcdf88f62b0 569 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 128:9bcdf88f62b0 570
<> 128:9bcdf88f62b0 571 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
<> 128:9bcdf88f62b0 572
<> 128:9bcdf88f62b0 573 /**
<> 128:9bcdf88f62b0 574 * @}
<> 128:9bcdf88f62b0 575 */
<> 128:9bcdf88f62b0 576
<> 128:9bcdf88f62b0 577 /**
<> 128:9bcdf88f62b0 578 * @}
<> 128:9bcdf88f62b0 579 */
<> 128:9bcdf88f62b0 580
<> 128:9bcdf88f62b0 581 /** @defgroup RI_Macris RI: Routing Interface
<> 128:9bcdf88f62b0 582 * @{
<> 128:9bcdf88f62b0 583 */
<> 128:9bcdf88f62b0 584
<> 128:9bcdf88f62b0 585 /** @defgroup RI_InputCaputureConfig Input Capture configuration
<> 128:9bcdf88f62b0 586 * @{
<> 128:9bcdf88f62b0 587 */
<> 128:9bcdf88f62b0 588
<> 128:9bcdf88f62b0 589 /**
<> 128:9bcdf88f62b0 590 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 591 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 592 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 593 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 594 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 595 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 596 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 597 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 598 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 599 * e.g.
<> 128:9bcdf88f62b0 600 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
<> 128:9bcdf88f62b0 601 * allows routing of Input capture IC1 of TIM2 to PA4.
<> 128:9bcdf88f62b0 602 * For details about correspondence between RI_INPUTCAPTUREROUTING_x
<> 128:9bcdf88f62b0 603 * and I/O pins refer to the parameters' description in the header file
<> 128:9bcdf88f62b0 604 * or refer to the product reference manual.
<> 128:9bcdf88f62b0 605 * @note Input capture selection bits are not reset by this function.
<> 128:9bcdf88f62b0 606 * To reset input capture selection bits, use SYSCFG_RIDeInit() function.
<> 128:9bcdf88f62b0 607 * @note The I/O should be configured in alternate function mode (AF14) using
<> 128:9bcdf88f62b0 608 * GPIO_PinAFConfig() function.
<> 128:9bcdf88f62b0 609 * @retval None.
<> 128:9bcdf88f62b0 610 */
<> 128:9bcdf88f62b0 611 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 612 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 613 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
<> 128:9bcdf88f62b0 616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
<> 128:9bcdf88f62b0 617 }while(0)
<> 128:9bcdf88f62b0 618
<> 128:9bcdf88f62b0 619 /**
<> 128:9bcdf88f62b0 620 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 621 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 622 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 623 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 624 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 625 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 626 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 627 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 628 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 629 * @retval None.
<> 128:9bcdf88f62b0 630 */
<> 128:9bcdf88f62b0 631 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 632 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 633 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
<> 128:9bcdf88f62b0 636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
<> 128:9bcdf88f62b0 637 }while(0)
<> 128:9bcdf88f62b0 638
<> 128:9bcdf88f62b0 639 /**
<> 128:9bcdf88f62b0 640 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 641 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 642 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 643 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 644 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 645 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 646 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 647 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 648 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 649 * @retval None.
<> 128:9bcdf88f62b0 650 */
<> 128:9bcdf88f62b0 651 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 652 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 653 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
<> 128:9bcdf88f62b0 656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
<> 128:9bcdf88f62b0 657 }while(0)
<> 128:9bcdf88f62b0 658
<> 128:9bcdf88f62b0 659 /**
<> 128:9bcdf88f62b0 660 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
<> 128:9bcdf88f62b0 661 * @param __TIMSELECT__: Timer select.
<> 128:9bcdf88f62b0 662 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 663 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
<> 128:9bcdf88f62b0 664 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
<> 128:9bcdf88f62b0 665 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
<> 128:9bcdf88f62b0 666 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
<> 128:9bcdf88f62b0 667 * @param __INPUT__: selects which pin to be routed to Input Capture.
<> 128:9bcdf88f62b0 668 * This parameter must be a value of @ref RI_InputCaptureRouting
<> 128:9bcdf88f62b0 669 * @retval None.
<> 128:9bcdf88f62b0 670 */
<> 128:9bcdf88f62b0 671 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
<> 128:9bcdf88f62b0 672 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
<> 128:9bcdf88f62b0 673 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
<> 128:9bcdf88f62b0 674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
<> 128:9bcdf88f62b0 675 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
<> 128:9bcdf88f62b0 676 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
<> 128:9bcdf88f62b0 677 }while(0)
<> 128:9bcdf88f62b0 678
<> 128:9bcdf88f62b0 679 /**
<> 128:9bcdf88f62b0 680 * @}
<> 128:9bcdf88f62b0 681 */
<> 128:9bcdf88f62b0 682
<> 128:9bcdf88f62b0 683 /** @defgroup RI_SwitchControlConfig Switch Control configuration
<> 128:9bcdf88f62b0 684 * @{
<> 128:9bcdf88f62b0 685 */
<> 128:9bcdf88f62b0 686
<> 128:9bcdf88f62b0 687 /**
<> 128:9bcdf88f62b0 688 * @brief Enable or disable the switch control mode.
<> 128:9bcdf88f62b0 689 * @note ENABLE: ADC analog switches closed if the corresponding
<> 128:9bcdf88f62b0 690 * I/O switch is also closed.
<> 128:9bcdf88f62b0 691 * When using COMP1, switch control mode must be enabled.
<> 128:9bcdf88f62b0 692 * @note DISABLE: ADC analog switches open or controlled by the ADC interface.
<> 128:9bcdf88f62b0 693 * When using the ADC for acquisition, switch control mode
<> 128:9bcdf88f62b0 694 * must be disabled.
<> 128:9bcdf88f62b0 695 * @note COMP1 comparator and ADC cannot be used at the same time since
<> 128:9bcdf88f62b0 696 * they share the ADC switch matrix.
<> 128:9bcdf88f62b0 697 * @retval None
<> 128:9bcdf88f62b0 698 */
<> 128:9bcdf88f62b0 699 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
<> 128:9bcdf88f62b0 702
<> 128:9bcdf88f62b0 703 /*
<> 128:9bcdf88f62b0 704 * @brief Close or Open the routing interface Input Output switches.
<> 128:9bcdf88f62b0 705 * @param __IOSWITCH__: selects the I/O analog switch number.
<> 128:9bcdf88f62b0 706 * This parameter must be a value of @ref RI_IOSwitch
<> 128:9bcdf88f62b0 707 * @retval None
<> 128:9bcdf88f62b0 708 */
<> 128:9bcdf88f62b0 709 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 128:9bcdf88f62b0 710 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 128:9bcdf88f62b0 711 { \
<> 128:9bcdf88f62b0 712 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 128:9bcdf88f62b0 713 } \
<> 128:9bcdf88f62b0 714 else \
<> 128:9bcdf88f62b0 715 { \
<> 128:9bcdf88f62b0 716 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 128:9bcdf88f62b0 717 } \
<> 128:9bcdf88f62b0 718 }while(0)
<> 128:9bcdf88f62b0 719
<> 128:9bcdf88f62b0 720 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
<> 128:9bcdf88f62b0 721 if ((__IOSWITCH__) >> 31 != 0 ) \
<> 128:9bcdf88f62b0 722 { \
<> 128:9bcdf88f62b0 723 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
<> 128:9bcdf88f62b0 724 } \
<> 128:9bcdf88f62b0 725 else \
<> 128:9bcdf88f62b0 726 { \
<> 128:9bcdf88f62b0 727 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
<> 128:9bcdf88f62b0 728 } \
<> 128:9bcdf88f62b0 729 }while(0)
<> 128:9bcdf88f62b0 730
<> 128:9bcdf88f62b0 731 #if defined (COMP_CSR_SW1)
<> 128:9bcdf88f62b0 732 /**
<> 128:9bcdf88f62b0 733 * @brief Close or open the internal switch COMP1_SW1.
<> 128:9bcdf88f62b0 734 * This switch connects I/O pin PC3 (can be used as ADC channel 13)
<> 128:9bcdf88f62b0 735 * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
<> 128:9bcdf88f62b0 736 * 26) and COMP1 non-inverting input.
<> 128:9bcdf88f62b0 737 * Pin PC3 connection depends on another switch setting, refer to
<> 128:9bcdf88f62b0 738 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
<> 128:9bcdf88f62b0 739 * @retval None.
<> 128:9bcdf88f62b0 740 */
<> 128:9bcdf88f62b0 741 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
<> 128:9bcdf88f62b0 742
<> 128:9bcdf88f62b0 743 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
<> 128:9bcdf88f62b0 744 #endif /* COMP_CSR_SW1 */
<> 128:9bcdf88f62b0 745
<> 128:9bcdf88f62b0 746 /**
<> 128:9bcdf88f62b0 747 * @}
<> 128:9bcdf88f62b0 748 */
<> 128:9bcdf88f62b0 749
<> 128:9bcdf88f62b0 750 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
<> 128:9bcdf88f62b0 751 * @{
<> 128:9bcdf88f62b0 752 */
<> 128:9bcdf88f62b0 753
<> 128:9bcdf88f62b0 754 /**
<> 128:9bcdf88f62b0 755 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
<> 128:9bcdf88f62b0 756 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 757 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 758 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 759 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 760 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 761 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 762 * @retval None
<> 128:9bcdf88f62b0 763 */
<> 128:9bcdf88f62b0 764 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 765 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 128:9bcdf88f62b0 766 } while(0)
<> 128:9bcdf88f62b0 767
<> 128:9bcdf88f62b0 768 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 769 SET_BIT(RI->HYSCR1, (__IOPIN__)); \
<> 128:9bcdf88f62b0 770 } while(0)
<> 128:9bcdf88f62b0 771
<> 128:9bcdf88f62b0 772 /**
<> 128:9bcdf88f62b0 773 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
<> 128:9bcdf88f62b0 774 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 775 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 776 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 777 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 778 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 779 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 780 * @retval None
<> 128:9bcdf88f62b0 781 */
<> 128:9bcdf88f62b0 782 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 783 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 784 } while(0)
<> 128:9bcdf88f62b0 785
<> 128:9bcdf88f62b0 786 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 787 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 788 } while(0)
<> 128:9bcdf88f62b0 789
<> 128:9bcdf88f62b0 790 /**
<> 128:9bcdf88f62b0 791 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
<> 128:9bcdf88f62b0 792 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 793 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 794 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 795 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 796 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 797 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 798 * @retval None
<> 128:9bcdf88f62b0 799 */
<> 128:9bcdf88f62b0 800 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 801 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 128:9bcdf88f62b0 802 } while(0)
<> 128:9bcdf88f62b0 803
<> 128:9bcdf88f62b0 804 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 805 SET_BIT(RI->HYSCR2, (__IOPIN__)); \
<> 128:9bcdf88f62b0 806 } while(0)
<> 128:9bcdf88f62b0 807
<> 128:9bcdf88f62b0 808 /**
<> 128:9bcdf88f62b0 809 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
<> 128:9bcdf88f62b0 810 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 811 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 812 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 813 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 814 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 815 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 816 * @retval None
<> 128:9bcdf88f62b0 817 */
<> 128:9bcdf88f62b0 818 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 819 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 820 } while(0)
<> 128:9bcdf88f62b0 821
<> 128:9bcdf88f62b0 822 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 823 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 824 } while(0)
<> 128:9bcdf88f62b0 825
<> 128:9bcdf88f62b0 826 #if defined (GPIOE_BASE)
<> 128:9bcdf88f62b0 827
<> 128:9bcdf88f62b0 828 /**
<> 128:9bcdf88f62b0 829 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
<> 128:9bcdf88f62b0 830 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 831 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 832 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 833 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 834 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 835 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 836 * @retval None
<> 128:9bcdf88f62b0 837 */
<> 128:9bcdf88f62b0 838 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 839 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 128:9bcdf88f62b0 840 } while(0)
<> 128:9bcdf88f62b0 841
<> 128:9bcdf88f62b0 842 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 843 SET_BIT(RI->HYSCR3, (__IOPIN__)); \
<> 128:9bcdf88f62b0 844 } while(0)
<> 128:9bcdf88f62b0 845
<> 128:9bcdf88f62b0 846 #endif /* GPIOE_BASE */
<> 128:9bcdf88f62b0 847
<> 128:9bcdf88f62b0 848 #if defined(GPIOF_BASE) || defined(GPIOG_BASE)
<> 128:9bcdf88f62b0 849
<> 128:9bcdf88f62b0 850 /**
<> 128:9bcdf88f62b0 851 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
<> 128:9bcdf88f62b0 852 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 853 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 854 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 855 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 856 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 857 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 858 * @retval None
<> 128:9bcdf88f62b0 859 */
<> 128:9bcdf88f62b0 860 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 861 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 862 } while(0)
<> 128:9bcdf88f62b0 863
<> 128:9bcdf88f62b0 864 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 865 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
<> 128:9bcdf88f62b0 866 } while(0)
<> 128:9bcdf88f62b0 867
<> 128:9bcdf88f62b0 868 /**
<> 128:9bcdf88f62b0 869 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
<> 128:9bcdf88f62b0 870 * When the I/Os are programmed in input mode by standard I/O port
<> 128:9bcdf88f62b0 871 * registers, the Schmitt trigger and the hysteresis are enabled by default.
<> 128:9bcdf88f62b0 872 * When hysteresis is disabled, it is possible to read the
<> 128:9bcdf88f62b0 873 * corresponding port with a trigger level of VDDIO/2.
<> 128:9bcdf88f62b0 874 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
<> 128:9bcdf88f62b0 875 * This parameter must be a value of @ref RI_Pin
<> 128:9bcdf88f62b0 876 * @retval None
<> 128:9bcdf88f62b0 877 */
<> 128:9bcdf88f62b0 878 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 879 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 128:9bcdf88f62b0 880 } while(0)
<> 128:9bcdf88f62b0 881
<> 128:9bcdf88f62b0 882 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
<> 128:9bcdf88f62b0 883 SET_BIT(RI->HYSCR4, (__IOPIN__)); \
<> 128:9bcdf88f62b0 884 } while(0)
<> 128:9bcdf88f62b0 885
<> 128:9bcdf88f62b0 886 #endif /* GPIOF_BASE || GPIOG_BASE */
<> 128:9bcdf88f62b0 887
<> 128:9bcdf88f62b0 888 /**
<> 128:9bcdf88f62b0 889 * @}
<> 128:9bcdf88f62b0 890 */
<> 128:9bcdf88f62b0 891
<> 128:9bcdf88f62b0 892 /**
<> 128:9bcdf88f62b0 893 * @}
<> 128:9bcdf88f62b0 894 */
<> 128:9bcdf88f62b0 895
<> 128:9bcdf88f62b0 896 /**
<> 128:9bcdf88f62b0 897 * @}
<> 128:9bcdf88f62b0 898 */
<> 128:9bcdf88f62b0 899
<> 128:9bcdf88f62b0 900 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 901
<> 128:9bcdf88f62b0 902 /** @addtogroup HAL_Exported_Functions
<> 128:9bcdf88f62b0 903 * @{
<> 128:9bcdf88f62b0 904 */
<> 128:9bcdf88f62b0 905
<> 128:9bcdf88f62b0 906 /** @addtogroup HAL_Exported_Functions_Group1
<> 128:9bcdf88f62b0 907 * @{
<> 128:9bcdf88f62b0 908 */
<> 128:9bcdf88f62b0 909
<> 128:9bcdf88f62b0 910 /* Initialization and de-initialization functions ******************************/
<> 128:9bcdf88f62b0 911 HAL_StatusTypeDef HAL_Init(void);
<> 128:9bcdf88f62b0 912 HAL_StatusTypeDef HAL_DeInit(void);
<> 128:9bcdf88f62b0 913 void HAL_MspInit(void);
<> 128:9bcdf88f62b0 914 void HAL_MspDeInit(void);
<> 128:9bcdf88f62b0 915 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 128:9bcdf88f62b0 916
<> 128:9bcdf88f62b0 917 /**
<> 128:9bcdf88f62b0 918 * @}
<> 128:9bcdf88f62b0 919 */
<> 128:9bcdf88f62b0 920
<> 128:9bcdf88f62b0 921 /** @addtogroup HAL_Exported_Functions_Group2
<> 128:9bcdf88f62b0 922 * @{
<> 128:9bcdf88f62b0 923 */
<> 128:9bcdf88f62b0 924
<> 128:9bcdf88f62b0 925 /* Peripheral Control functions ************************************************/
<> 128:9bcdf88f62b0 926 void HAL_IncTick(void);
<> 128:9bcdf88f62b0 927 void HAL_Delay(__IO uint32_t Delay);
<> 128:9bcdf88f62b0 928 uint32_t HAL_GetTick(void);
<> 128:9bcdf88f62b0 929 void HAL_SuspendTick(void);
<> 128:9bcdf88f62b0 930 void HAL_ResumeTick(void);
<> 128:9bcdf88f62b0 931 uint32_t HAL_GetHalVersion(void);
<> 128:9bcdf88f62b0 932 uint32_t HAL_GetREVID(void);
<> 128:9bcdf88f62b0 933 uint32_t HAL_GetDEVID(void);
<> 128:9bcdf88f62b0 934 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 128:9bcdf88f62b0 935 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 128:9bcdf88f62b0 936 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 128:9bcdf88f62b0 937 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 128:9bcdf88f62b0 938 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 128:9bcdf88f62b0 939 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 128:9bcdf88f62b0 940
<> 128:9bcdf88f62b0 941 /**
<> 128:9bcdf88f62b0 942 * @}
<> 128:9bcdf88f62b0 943 */
<> 128:9bcdf88f62b0 944
<> 128:9bcdf88f62b0 945 /**
<> 128:9bcdf88f62b0 946 * @}
<> 128:9bcdf88f62b0 947 */
<> 128:9bcdf88f62b0 948
<> 128:9bcdf88f62b0 949
<> 128:9bcdf88f62b0 950 /**
<> 128:9bcdf88f62b0 951 * @}
<> 128:9bcdf88f62b0 952 */
<> 128:9bcdf88f62b0 953
<> 128:9bcdf88f62b0 954 /**
<> 128:9bcdf88f62b0 955 * @}
<> 128:9bcdf88f62b0 956 */
<> 128:9bcdf88f62b0 957
<> 128:9bcdf88f62b0 958 #ifdef __cplusplus
<> 128:9bcdf88f62b0 959 }
<> 128:9bcdf88f62b0 960 #endif
<> 128:9bcdf88f62b0 961
<> 128:9bcdf88f62b0 962 #endif /* __STM32L1xx_HAL_H */
<> 128:9bcdf88f62b0 963
<> 128:9bcdf88f62b0 964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/