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TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.h@168:b9e159c1930a, 2018-05-24 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu May 24 15:35:55 2018 +0100
- Revision:
- 168:b9e159c1930a
- Parent:
- 163:e59c8e839560
mbed library. Release version 162
Who changed what in which revision?
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AnnaBridge | 163:e59c8e839560 | 1 | /** |
AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_hal_tim.h |
AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
AnnaBridge | 163:e59c8e839560 | 5 | * @brief Header file of TIM HAL module. |
AnnaBridge | 163:e59c8e839560 | 6 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 7 | * @attention |
AnnaBridge | 163:e59c8e839560 | 8 | * |
AnnaBridge | 163:e59c8e839560 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 163:e59c8e839560 | 10 | * |
AnnaBridge | 163:e59c8e839560 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 163:e59c8e839560 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 163:e59c8e839560 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 163:e59c8e839560 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 163:e59c8e839560 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 163:e59c8e839560 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 163:e59c8e839560 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 163:e59c8e839560 | 20 | * without specific prior written permission. |
AnnaBridge | 163:e59c8e839560 | 21 | * |
AnnaBridge | 163:e59c8e839560 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 163:e59c8e839560 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 163:e59c8e839560 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 163:e59c8e839560 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 163:e59c8e839560 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 163:e59c8e839560 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 163:e59c8e839560 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 163:e59c8e839560 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 163:e59c8e839560 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 163:e59c8e839560 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 163:e59c8e839560 | 32 | * |
AnnaBridge | 163:e59c8e839560 | 33 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 34 | */ |
AnnaBridge | 163:e59c8e839560 | 35 | |
AnnaBridge | 163:e59c8e839560 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 37 | #ifndef __STM32F3xx_HAL_TIM_H |
AnnaBridge | 163:e59c8e839560 | 38 | #define __STM32F3xx_HAL_TIM_H |
AnnaBridge | 163:e59c8e839560 | 39 | |
AnnaBridge | 163:e59c8e839560 | 40 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 41 | extern "C" { |
AnnaBridge | 163:e59c8e839560 | 42 | #endif |
AnnaBridge | 163:e59c8e839560 | 43 | |
AnnaBridge | 163:e59c8e839560 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 45 | #include "stm32f3xx_hal_def.h" |
AnnaBridge | 163:e59c8e839560 | 46 | |
AnnaBridge | 163:e59c8e839560 | 47 | /** @addtogroup STM32F3xx_HAL_Driver |
AnnaBridge | 163:e59c8e839560 | 48 | * @{ |
AnnaBridge | 163:e59c8e839560 | 49 | */ |
AnnaBridge | 163:e59c8e839560 | 50 | |
AnnaBridge | 163:e59c8e839560 | 51 | /** @addtogroup TIM |
AnnaBridge | 163:e59c8e839560 | 52 | * @{ |
AnnaBridge | 163:e59c8e839560 | 53 | */ |
AnnaBridge | 163:e59c8e839560 | 54 | |
AnnaBridge | 163:e59c8e839560 | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
AnnaBridge | 163:e59c8e839560 | 57 | * @{ |
AnnaBridge | 163:e59c8e839560 | 58 | */ |
AnnaBridge | 163:e59c8e839560 | 59 | /** |
AnnaBridge | 163:e59c8e839560 | 60 | * @brief TIM Time base Configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 61 | */ |
AnnaBridge | 163:e59c8e839560 | 62 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 63 | { |
AnnaBridge | 163:e59c8e839560 | 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 163:e59c8e839560 | 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ |
AnnaBridge | 163:e59c8e839560 | 66 | |
AnnaBridge | 163:e59c8e839560 | 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 163:e59c8e839560 | 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
AnnaBridge | 163:e59c8e839560 | 69 | |
AnnaBridge | 163:e59c8e839560 | 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
AnnaBridge | 163:e59c8e839560 | 71 | Auto-Reload Register at the next update event. |
AnnaBridge | 163:e59c8e839560 | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 163:e59c8e839560 | 73 | |
AnnaBridge | 163:e59c8e839560 | 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 163:e59c8e839560 | 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
AnnaBridge | 163:e59c8e839560 | 76 | |
AnnaBridge | 163:e59c8e839560 | 77 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
AnnaBridge | 163:e59c8e839560 | 78 | reaches zero, an update event is generated and counting restarts |
AnnaBridge | 163:e59c8e839560 | 79 | from the RCR value (N). |
AnnaBridge | 163:e59c8e839560 | 80 | This means in PWM mode that (N+1U) corresponds to: |
AnnaBridge | 163:e59c8e839560 | 81 | - the number of PWM periods in edge-aligned mode |
AnnaBridge | 163:e59c8e839560 | 82 | - the number of half PWM period in center-aligned mode |
AnnaBridge | 163:e59c8e839560 | 83 | GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
AnnaBridge | 163:e59c8e839560 | 84 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 163:e59c8e839560 | 85 | |
AnnaBridge | 163:e59c8e839560 | 86 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
AnnaBridge | 163:e59c8e839560 | 87 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
AnnaBridge | 163:e59c8e839560 | 88 | } TIM_Base_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 89 | |
AnnaBridge | 163:e59c8e839560 | 90 | /** |
AnnaBridge | 163:e59c8e839560 | 91 | * @brief TIM Output Compare Configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 92 | */ |
AnnaBridge | 163:e59c8e839560 | 93 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 94 | { |
AnnaBridge | 163:e59c8e839560 | 95 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 163:e59c8e839560 | 96 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
AnnaBridge | 163:e59c8e839560 | 97 | |
AnnaBridge | 163:e59c8e839560 | 98 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 163:e59c8e839560 | 99 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ |
AnnaBridge | 163:e59c8e839560 | 100 | |
AnnaBridge | 163:e59c8e839560 | 101 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 163:e59c8e839560 | 102 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 103 | |
AnnaBridge | 163:e59c8e839560 | 104 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 163:e59c8e839560 | 105 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 163:e59c8e839560 | 106 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 107 | |
AnnaBridge | 163:e59c8e839560 | 108 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
AnnaBridge | 163:e59c8e839560 | 109 | This parameter can be a value of @ref TIM_Output_Fast_State |
AnnaBridge | 163:e59c8e839560 | 110 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
AnnaBridge | 163:e59c8e839560 | 111 | |
AnnaBridge | 163:e59c8e839560 | 112 | |
AnnaBridge | 163:e59c8e839560 | 113 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 163:e59c8e839560 | 114 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 163:e59c8e839560 | 115 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 116 | |
AnnaBridge | 163:e59c8e839560 | 117 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 163:e59c8e839560 | 118 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 163:e59c8e839560 | 119 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 120 | } TIM_OC_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 121 | |
AnnaBridge | 163:e59c8e839560 | 122 | /** |
AnnaBridge | 163:e59c8e839560 | 123 | * @brief TIM One Pulse Mode Configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 124 | */ |
AnnaBridge | 163:e59c8e839560 | 125 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 126 | { |
AnnaBridge | 163:e59c8e839560 | 127 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 163:e59c8e839560 | 128 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
AnnaBridge | 163:e59c8e839560 | 129 | |
AnnaBridge | 163:e59c8e839560 | 130 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 163:e59c8e839560 | 131 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ |
AnnaBridge | 163:e59c8e839560 | 132 | |
AnnaBridge | 163:e59c8e839560 | 133 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 163:e59c8e839560 | 134 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 135 | |
AnnaBridge | 163:e59c8e839560 | 136 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 163:e59c8e839560 | 137 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 163:e59c8e839560 | 138 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 139 | |
AnnaBridge | 163:e59c8e839560 | 140 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 163:e59c8e839560 | 141 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 163:e59c8e839560 | 142 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 143 | |
AnnaBridge | 163:e59c8e839560 | 144 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 163:e59c8e839560 | 145 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 163:e59c8e839560 | 146 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 163:e59c8e839560 | 147 | |
AnnaBridge | 163:e59c8e839560 | 148 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 163:e59c8e839560 | 149 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 150 | |
AnnaBridge | 163:e59c8e839560 | 151 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 163:e59c8e839560 | 152 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 163:e59c8e839560 | 153 | |
AnnaBridge | 163:e59c8e839560 | 154 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 163:e59c8e839560 | 155 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 156 | } TIM_OnePulse_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 157 | |
AnnaBridge | 163:e59c8e839560 | 158 | |
AnnaBridge | 163:e59c8e839560 | 159 | /** |
AnnaBridge | 163:e59c8e839560 | 160 | * @brief TIM Input Capture Configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 161 | */ |
AnnaBridge | 163:e59c8e839560 | 162 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 163 | { |
AnnaBridge | 163:e59c8e839560 | 164 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 163:e59c8e839560 | 165 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 166 | |
AnnaBridge | 163:e59c8e839560 | 167 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 163:e59c8e839560 | 168 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 163:e59c8e839560 | 169 | |
AnnaBridge | 163:e59c8e839560 | 170 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 163:e59c8e839560 | 171 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 172 | |
AnnaBridge | 163:e59c8e839560 | 173 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 163:e59c8e839560 | 174 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 175 | } TIM_IC_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 176 | |
AnnaBridge | 163:e59c8e839560 | 177 | /** |
AnnaBridge | 163:e59c8e839560 | 178 | * @brief TIM Encoder Configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 179 | */ |
AnnaBridge | 163:e59c8e839560 | 180 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 181 | { |
AnnaBridge | 163:e59c8e839560 | 182 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 163:e59c8e839560 | 183 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
AnnaBridge | 163:e59c8e839560 | 184 | |
AnnaBridge | 163:e59c8e839560 | 185 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 163:e59c8e839560 | 186 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 187 | |
AnnaBridge | 163:e59c8e839560 | 188 | uint32_t IC1Selection; /*!< Specifies the input. |
AnnaBridge | 163:e59c8e839560 | 189 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 163:e59c8e839560 | 190 | |
AnnaBridge | 163:e59c8e839560 | 191 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 163:e59c8e839560 | 192 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 193 | |
AnnaBridge | 163:e59c8e839560 | 194 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 163:e59c8e839560 | 195 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 196 | |
AnnaBridge | 163:e59c8e839560 | 197 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 163:e59c8e839560 | 198 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 199 | |
AnnaBridge | 163:e59c8e839560 | 200 | uint32_t IC2Selection; /*!< Specifies the input. |
AnnaBridge | 163:e59c8e839560 | 201 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 163:e59c8e839560 | 202 | |
AnnaBridge | 163:e59c8e839560 | 203 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 163:e59c8e839560 | 204 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 205 | |
AnnaBridge | 163:e59c8e839560 | 206 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 163:e59c8e839560 | 207 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 208 | } TIM_Encoder_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 209 | |
AnnaBridge | 163:e59c8e839560 | 210 | |
AnnaBridge | 163:e59c8e839560 | 211 | /** |
AnnaBridge | 163:e59c8e839560 | 212 | * @brief TIM Clock Configuration Handle Structure definition |
AnnaBridge | 163:e59c8e839560 | 213 | */ |
AnnaBridge | 163:e59c8e839560 | 214 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 215 | { |
AnnaBridge | 163:e59c8e839560 | 216 | uint32_t ClockSource; /*!< TIM clock sources |
AnnaBridge | 163:e59c8e839560 | 217 | This parameter can be a value of @ref TIM_Clock_Source */ |
AnnaBridge | 163:e59c8e839560 | 218 | uint32_t ClockPolarity; /*!< TIM clock polarity |
AnnaBridge | 163:e59c8e839560 | 219 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 220 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
AnnaBridge | 163:e59c8e839560 | 221 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 222 | uint32_t ClockFilter; /*!< TIM clock filter |
AnnaBridge | 163:e59c8e839560 | 223 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 224 | }TIM_ClockConfigTypeDef; |
AnnaBridge | 163:e59c8e839560 | 225 | |
AnnaBridge | 163:e59c8e839560 | 226 | /** |
AnnaBridge | 163:e59c8e839560 | 227 | * @brief TIM Clear Input Configuration Handle Structure definition |
AnnaBridge | 163:e59c8e839560 | 228 | */ |
AnnaBridge | 163:e59c8e839560 | 229 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 230 | { |
AnnaBridge | 163:e59c8e839560 | 231 | uint32_t ClearInputState; /*!< TIM clear Input state |
AnnaBridge | 163:e59c8e839560 | 232 | This parameter can be ENABLE or DISABLE */ |
AnnaBridge | 163:e59c8e839560 | 233 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
AnnaBridge | 163:e59c8e839560 | 234 | This parameter can be a value of @ref TIMEx_ClearInput_Source */ |
AnnaBridge | 163:e59c8e839560 | 235 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
AnnaBridge | 163:e59c8e839560 | 236 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 237 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
AnnaBridge | 163:e59c8e839560 | 238 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 239 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
AnnaBridge | 163:e59c8e839560 | 240 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 241 | }TIM_ClearInputConfigTypeDef; |
AnnaBridge | 163:e59c8e839560 | 242 | |
AnnaBridge | 163:e59c8e839560 | 243 | /** |
AnnaBridge | 163:e59c8e839560 | 244 | * @brief TIM Slave configuration Structure definition |
AnnaBridge | 163:e59c8e839560 | 245 | */ |
AnnaBridge | 163:e59c8e839560 | 246 | typedef struct { |
AnnaBridge | 163:e59c8e839560 | 247 | uint32_t SlaveMode; /*!< Slave mode selection |
AnnaBridge | 163:e59c8e839560 | 248 | This parameter can be a value of @ref TIMEx_Slave_Mode */ |
AnnaBridge | 163:e59c8e839560 | 249 | uint32_t InputTrigger; /*!< Input Trigger source |
AnnaBridge | 163:e59c8e839560 | 250 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
AnnaBridge | 163:e59c8e839560 | 251 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
AnnaBridge | 163:e59c8e839560 | 252 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
AnnaBridge | 163:e59c8e839560 | 253 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
AnnaBridge | 163:e59c8e839560 | 254 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
AnnaBridge | 163:e59c8e839560 | 255 | uint32_t TriggerFilter; /*!< Input trigger filter |
AnnaBridge | 163:e59c8e839560 | 256 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ |
AnnaBridge | 163:e59c8e839560 | 257 | |
AnnaBridge | 163:e59c8e839560 | 258 | }TIM_SlaveConfigTypeDef; |
AnnaBridge | 163:e59c8e839560 | 259 | |
AnnaBridge | 163:e59c8e839560 | 260 | /** |
AnnaBridge | 163:e59c8e839560 | 261 | * @brief HAL State structures definition |
AnnaBridge | 163:e59c8e839560 | 262 | */ |
AnnaBridge | 163:e59c8e839560 | 263 | typedef enum |
AnnaBridge | 163:e59c8e839560 | 264 | { |
AnnaBridge | 163:e59c8e839560 | 265 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
AnnaBridge | 163:e59c8e839560 | 266 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
AnnaBridge | 163:e59c8e839560 | 267 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
AnnaBridge | 163:e59c8e839560 | 268 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
AnnaBridge | 163:e59c8e839560 | 269 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
AnnaBridge | 163:e59c8e839560 | 270 | }HAL_TIM_StateTypeDef; |
AnnaBridge | 163:e59c8e839560 | 271 | |
AnnaBridge | 163:e59c8e839560 | 272 | /** |
AnnaBridge | 163:e59c8e839560 | 273 | * @brief HAL Active channel structures definition |
AnnaBridge | 163:e59c8e839560 | 274 | */ |
AnnaBridge | 163:e59c8e839560 | 275 | typedef enum |
AnnaBridge | 163:e59c8e839560 | 276 | { |
AnnaBridge | 163:e59c8e839560 | 277 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
AnnaBridge | 163:e59c8e839560 | 278 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
AnnaBridge | 163:e59c8e839560 | 279 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
AnnaBridge | 163:e59c8e839560 | 280 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
AnnaBridge | 163:e59c8e839560 | 281 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
AnnaBridge | 163:e59c8e839560 | 282 | }HAL_TIM_ActiveChannel; |
AnnaBridge | 163:e59c8e839560 | 283 | |
AnnaBridge | 163:e59c8e839560 | 284 | /** |
AnnaBridge | 163:e59c8e839560 | 285 | * @brief TIM Time Base Handle Structure definition |
AnnaBridge | 163:e59c8e839560 | 286 | */ |
AnnaBridge | 163:e59c8e839560 | 287 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 288 | { |
AnnaBridge | 163:e59c8e839560 | 289 | TIM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 163:e59c8e839560 | 290 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
AnnaBridge | 163:e59c8e839560 | 291 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
AnnaBridge | 163:e59c8e839560 | 292 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
AnnaBridge | 163:e59c8e839560 | 293 | This array is accessed by a @ref TIM_DMA_Handle_index */ |
AnnaBridge | 163:e59c8e839560 | 294 | HAL_LockTypeDef Lock; /*!< Locking object */ |
AnnaBridge | 163:e59c8e839560 | 295 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
AnnaBridge | 163:e59c8e839560 | 296 | }TIM_HandleTypeDef; |
AnnaBridge | 163:e59c8e839560 | 297 | |
AnnaBridge | 163:e59c8e839560 | 298 | /** |
AnnaBridge | 163:e59c8e839560 | 299 | * @} |
AnnaBridge | 163:e59c8e839560 | 300 | */ |
AnnaBridge | 163:e59c8e839560 | 301 | /* End of exported types -----------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 302 | |
AnnaBridge | 163:e59c8e839560 | 303 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 304 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
AnnaBridge | 163:e59c8e839560 | 305 | * @{ |
AnnaBridge | 163:e59c8e839560 | 306 | */ |
AnnaBridge | 163:e59c8e839560 | 307 | |
AnnaBridge | 163:e59c8e839560 | 308 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
AnnaBridge | 163:e59c8e839560 | 309 | * @{ |
AnnaBridge | 163:e59c8e839560 | 310 | */ |
AnnaBridge | 163:e59c8e839560 | 311 | #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ |
AnnaBridge | 163:e59c8e839560 | 312 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
AnnaBridge | 163:e59c8e839560 | 313 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
AnnaBridge | 163:e59c8e839560 | 314 | /** |
AnnaBridge | 163:e59c8e839560 | 315 | * @} |
AnnaBridge | 163:e59c8e839560 | 316 | */ |
AnnaBridge | 163:e59c8e839560 | 317 | |
AnnaBridge | 163:e59c8e839560 | 318 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
AnnaBridge | 163:e59c8e839560 | 319 | * @{ |
AnnaBridge | 163:e59c8e839560 | 320 | */ |
AnnaBridge | 163:e59c8e839560 | 321 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 163:e59c8e839560 | 322 | #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ |
AnnaBridge | 163:e59c8e839560 | 323 | /** |
AnnaBridge | 163:e59c8e839560 | 324 | * @} |
AnnaBridge | 163:e59c8e839560 | 325 | */ |
AnnaBridge | 163:e59c8e839560 | 326 | |
AnnaBridge | 163:e59c8e839560 | 327 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
AnnaBridge | 163:e59c8e839560 | 328 | * @{ |
AnnaBridge | 163:e59c8e839560 | 329 | */ |
AnnaBridge | 163:e59c8e839560 | 330 | #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ |
AnnaBridge | 163:e59c8e839560 | 331 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */ |
AnnaBridge | 163:e59c8e839560 | 332 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */ |
AnnaBridge | 163:e59c8e839560 | 333 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */ |
AnnaBridge | 163:e59c8e839560 | 334 | /** |
AnnaBridge | 163:e59c8e839560 | 335 | * @} |
AnnaBridge | 163:e59c8e839560 | 336 | */ |
AnnaBridge | 163:e59c8e839560 | 337 | |
AnnaBridge | 163:e59c8e839560 | 338 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
AnnaBridge | 163:e59c8e839560 | 339 | * @{ |
AnnaBridge | 163:e59c8e839560 | 340 | */ |
AnnaBridge | 163:e59c8e839560 | 341 | #define TIM_COUNTERMODE_UP (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 342 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
AnnaBridge | 163:e59c8e839560 | 343 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
AnnaBridge | 163:e59c8e839560 | 344 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
AnnaBridge | 163:e59c8e839560 | 345 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
AnnaBridge | 163:e59c8e839560 | 346 | /** |
AnnaBridge | 163:e59c8e839560 | 347 | * @} |
AnnaBridge | 163:e59c8e839560 | 348 | */ |
AnnaBridge | 163:e59c8e839560 | 349 | |
AnnaBridge | 163:e59c8e839560 | 350 | /** @defgroup TIM_ClockDivision TIM Clock Division |
AnnaBridge | 163:e59c8e839560 | 351 | * @{ |
AnnaBridge | 163:e59c8e839560 | 352 | */ |
AnnaBridge | 163:e59c8e839560 | 353 | #define TIM_CLOCKDIVISION_DIV1 (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 354 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
AnnaBridge | 163:e59c8e839560 | 355 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
AnnaBridge | 163:e59c8e839560 | 356 | /** |
AnnaBridge | 163:e59c8e839560 | 357 | * @} |
AnnaBridge | 163:e59c8e839560 | 358 | */ |
AnnaBridge | 163:e59c8e839560 | 359 | |
AnnaBridge | 163:e59c8e839560 | 360 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
AnnaBridge | 163:e59c8e839560 | 361 | * @{ |
AnnaBridge | 163:e59c8e839560 | 362 | */ |
AnnaBridge | 163:e59c8e839560 | 363 | #define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ |
AnnaBridge | 163:e59c8e839560 | 364 | #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ |
AnnaBridge | 163:e59c8e839560 | 365 | |
AnnaBridge | 163:e59c8e839560 | 366 | /** |
AnnaBridge | 163:e59c8e839560 | 367 | * @} |
AnnaBridge | 163:e59c8e839560 | 368 | */ |
AnnaBridge | 163:e59c8e839560 | 369 | |
AnnaBridge | 163:e59c8e839560 | 370 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
AnnaBridge | 163:e59c8e839560 | 371 | * @{ |
AnnaBridge | 163:e59c8e839560 | 372 | */ |
AnnaBridge | 163:e59c8e839560 | 373 | #define TIM_OCFAST_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 374 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
AnnaBridge | 163:e59c8e839560 | 375 | /** |
AnnaBridge | 163:e59c8e839560 | 376 | * @} |
AnnaBridge | 163:e59c8e839560 | 377 | */ |
AnnaBridge | 163:e59c8e839560 | 378 | |
AnnaBridge | 163:e59c8e839560 | 379 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
AnnaBridge | 163:e59c8e839560 | 380 | * @{ |
AnnaBridge | 163:e59c8e839560 | 381 | */ |
AnnaBridge | 163:e59c8e839560 | 382 | #define TIM_OCPOLARITY_HIGH (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 383 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
AnnaBridge | 163:e59c8e839560 | 384 | /** |
AnnaBridge | 163:e59c8e839560 | 385 | * @} |
AnnaBridge | 163:e59c8e839560 | 386 | */ |
AnnaBridge | 163:e59c8e839560 | 387 | |
AnnaBridge | 163:e59c8e839560 | 388 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
AnnaBridge | 163:e59c8e839560 | 389 | * @{ |
AnnaBridge | 163:e59c8e839560 | 390 | */ |
AnnaBridge | 163:e59c8e839560 | 391 | #define TIM_OCNPOLARITY_HIGH (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 392 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
AnnaBridge | 163:e59c8e839560 | 393 | /** |
AnnaBridge | 163:e59c8e839560 | 394 | * @} |
AnnaBridge | 163:e59c8e839560 | 395 | */ |
AnnaBridge | 163:e59c8e839560 | 396 | |
AnnaBridge | 163:e59c8e839560 | 397 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
AnnaBridge | 163:e59c8e839560 | 398 | * @{ |
AnnaBridge | 163:e59c8e839560 | 399 | */ |
AnnaBridge | 163:e59c8e839560 | 400 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
AnnaBridge | 163:e59c8e839560 | 401 | #define TIM_OCIDLESTATE_RESET (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 402 | /** |
AnnaBridge | 163:e59c8e839560 | 403 | * @} |
AnnaBridge | 163:e59c8e839560 | 404 | */ |
AnnaBridge | 163:e59c8e839560 | 405 | |
AnnaBridge | 163:e59c8e839560 | 406 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State |
AnnaBridge | 163:e59c8e839560 | 407 | * @{ |
AnnaBridge | 163:e59c8e839560 | 408 | */ |
AnnaBridge | 163:e59c8e839560 | 409 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
AnnaBridge | 163:e59c8e839560 | 410 | #define TIM_OCNIDLESTATE_RESET (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 411 | /** |
AnnaBridge | 163:e59c8e839560 | 412 | * @} |
AnnaBridge | 163:e59c8e839560 | 413 | */ |
AnnaBridge | 163:e59c8e839560 | 414 | |
AnnaBridge | 163:e59c8e839560 | 415 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
AnnaBridge | 163:e59c8e839560 | 416 | * @{ |
AnnaBridge | 163:e59c8e839560 | 417 | */ |
AnnaBridge | 163:e59c8e839560 | 418 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
AnnaBridge | 163:e59c8e839560 | 419 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
AnnaBridge | 163:e59c8e839560 | 420 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
AnnaBridge | 163:e59c8e839560 | 421 | /** |
AnnaBridge | 163:e59c8e839560 | 422 | * @} |
AnnaBridge | 163:e59c8e839560 | 423 | */ |
AnnaBridge | 163:e59c8e839560 | 424 | |
AnnaBridge | 163:e59c8e839560 | 425 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
AnnaBridge | 163:e59c8e839560 | 426 | * @{ |
AnnaBridge | 163:e59c8e839560 | 427 | */ |
AnnaBridge | 163:e59c8e839560 | 428 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be |
AnnaBridge | 163:e59c8e839560 | 429 | connected to IC1, IC2, IC3 or IC4, respectively */ |
AnnaBridge | 163:e59c8e839560 | 430 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be |
AnnaBridge | 163:e59c8e839560 | 431 | connected to IC2, IC1, IC4 or IC3, respectively */ |
AnnaBridge | 163:e59c8e839560 | 432 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */ |
AnnaBridge | 163:e59c8e839560 | 433 | /** |
AnnaBridge | 163:e59c8e839560 | 434 | * @} |
AnnaBridge | 163:e59c8e839560 | 435 | */ |
AnnaBridge | 163:e59c8e839560 | 436 | |
AnnaBridge | 163:e59c8e839560 | 437 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
AnnaBridge | 163:e59c8e839560 | 438 | * @{ |
AnnaBridge | 163:e59c8e839560 | 439 | */ |
AnnaBridge | 163:e59c8e839560 | 440 | #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ |
AnnaBridge | 163:e59c8e839560 | 441 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
AnnaBridge | 163:e59c8e839560 | 442 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
AnnaBridge | 163:e59c8e839560 | 443 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
AnnaBridge | 163:e59c8e839560 | 444 | /** |
AnnaBridge | 163:e59c8e839560 | 445 | * @} |
AnnaBridge | 163:e59c8e839560 | 446 | */ |
AnnaBridge | 163:e59c8e839560 | 447 | |
AnnaBridge | 163:e59c8e839560 | 448 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
AnnaBridge | 163:e59c8e839560 | 449 | * @{ |
AnnaBridge | 163:e59c8e839560 | 450 | */ |
AnnaBridge | 163:e59c8e839560 | 451 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 163:e59c8e839560 | 452 | #define TIM_OPMODE_REPETITIVE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 453 | /** |
AnnaBridge | 163:e59c8e839560 | 454 | * @} |
AnnaBridge | 163:e59c8e839560 | 455 | */ |
AnnaBridge | 163:e59c8e839560 | 456 | |
AnnaBridge | 163:e59c8e839560 | 457 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
AnnaBridge | 163:e59c8e839560 | 458 | * @{ |
AnnaBridge | 163:e59c8e839560 | 459 | */ |
AnnaBridge | 163:e59c8e839560 | 460 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
AnnaBridge | 163:e59c8e839560 | 461 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
AnnaBridge | 163:e59c8e839560 | 462 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
AnnaBridge | 163:e59c8e839560 | 463 | /** |
AnnaBridge | 163:e59c8e839560 | 464 | * @} |
AnnaBridge | 163:e59c8e839560 | 465 | */ |
AnnaBridge | 163:e59c8e839560 | 466 | |
AnnaBridge | 163:e59c8e839560 | 467 | /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition |
AnnaBridge | 163:e59c8e839560 | 468 | * @{ |
AnnaBridge | 163:e59c8e839560 | 469 | */ |
AnnaBridge | 163:e59c8e839560 | 470 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
AnnaBridge | 163:e59c8e839560 | 471 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
AnnaBridge | 163:e59c8e839560 | 472 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
AnnaBridge | 163:e59c8e839560 | 473 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
AnnaBridge | 163:e59c8e839560 | 474 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
AnnaBridge | 163:e59c8e839560 | 475 | #define TIM_IT_COM (TIM_DIER_COMIE) |
AnnaBridge | 163:e59c8e839560 | 476 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
AnnaBridge | 163:e59c8e839560 | 477 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
AnnaBridge | 163:e59c8e839560 | 478 | /** |
AnnaBridge | 163:e59c8e839560 | 479 | * @} |
AnnaBridge | 163:e59c8e839560 | 480 | */ |
AnnaBridge | 163:e59c8e839560 | 481 | |
AnnaBridge | 163:e59c8e839560 | 482 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
AnnaBridge | 163:e59c8e839560 | 483 | * @{ |
AnnaBridge | 163:e59c8e839560 | 484 | */ |
AnnaBridge | 163:e59c8e839560 | 485 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
AnnaBridge | 163:e59c8e839560 | 486 | #define TIM_COMMUTATION_SOFTWARE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 487 | |
AnnaBridge | 163:e59c8e839560 | 488 | /** |
AnnaBridge | 163:e59c8e839560 | 489 | * @} |
AnnaBridge | 163:e59c8e839560 | 490 | */ |
AnnaBridge | 163:e59c8e839560 | 491 | |
AnnaBridge | 163:e59c8e839560 | 492 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
AnnaBridge | 163:e59c8e839560 | 493 | * @{ |
AnnaBridge | 163:e59c8e839560 | 494 | */ |
AnnaBridge | 163:e59c8e839560 | 495 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
AnnaBridge | 163:e59c8e839560 | 496 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
AnnaBridge | 163:e59c8e839560 | 497 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
AnnaBridge | 163:e59c8e839560 | 498 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
AnnaBridge | 163:e59c8e839560 | 499 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
AnnaBridge | 163:e59c8e839560 | 500 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
AnnaBridge | 163:e59c8e839560 | 501 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
AnnaBridge | 163:e59c8e839560 | 502 | /** |
AnnaBridge | 163:e59c8e839560 | 503 | * @} |
AnnaBridge | 163:e59c8e839560 | 504 | */ |
AnnaBridge | 163:e59c8e839560 | 505 | |
AnnaBridge | 163:e59c8e839560 | 506 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
AnnaBridge | 163:e59c8e839560 | 507 | * @{ |
AnnaBridge | 163:e59c8e839560 | 508 | */ |
AnnaBridge | 163:e59c8e839560 | 509 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
AnnaBridge | 163:e59c8e839560 | 510 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
AnnaBridge | 163:e59c8e839560 | 511 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
AnnaBridge | 163:e59c8e839560 | 512 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
AnnaBridge | 163:e59c8e839560 | 513 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
AnnaBridge | 163:e59c8e839560 | 514 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
AnnaBridge | 163:e59c8e839560 | 515 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
AnnaBridge | 163:e59c8e839560 | 516 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
AnnaBridge | 168:b9e159c1930a | 517 | #if defined(TIM_SR_B2IF) |
AnnaBridge | 168:b9e159c1930a | 518 | #define TIM_FLAG_BREAK2 (TIM_SR_B2IF) |
AnnaBridge | 168:b9e159c1930a | 519 | #endif |
AnnaBridge | 163:e59c8e839560 | 520 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
AnnaBridge | 163:e59c8e839560 | 521 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
AnnaBridge | 163:e59c8e839560 | 522 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
AnnaBridge | 163:e59c8e839560 | 523 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
AnnaBridge | 163:e59c8e839560 | 524 | /** |
AnnaBridge | 163:e59c8e839560 | 525 | * @} |
AnnaBridge | 163:e59c8e839560 | 526 | */ |
AnnaBridge | 163:e59c8e839560 | 527 | |
AnnaBridge | 163:e59c8e839560 | 528 | /** @defgroup TIM_Clock_Source TIM Clock Source |
AnnaBridge | 163:e59c8e839560 | 529 | * @{ |
AnnaBridge | 163:e59c8e839560 | 530 | */ |
AnnaBridge | 163:e59c8e839560 | 531 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
AnnaBridge | 163:e59c8e839560 | 532 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 163:e59c8e839560 | 533 | #define TIM_CLOCKSOURCE_ITR0 (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 534 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
AnnaBridge | 163:e59c8e839560 | 535 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
AnnaBridge | 163:e59c8e839560 | 536 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
AnnaBridge | 163:e59c8e839560 | 537 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
AnnaBridge | 163:e59c8e839560 | 538 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
AnnaBridge | 163:e59c8e839560 | 539 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
AnnaBridge | 163:e59c8e839560 | 540 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
AnnaBridge | 163:e59c8e839560 | 541 | /** |
AnnaBridge | 163:e59c8e839560 | 542 | * @} |
AnnaBridge | 163:e59c8e839560 | 543 | */ |
AnnaBridge | 163:e59c8e839560 | 544 | |
AnnaBridge | 163:e59c8e839560 | 545 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
AnnaBridge | 163:e59c8e839560 | 546 | * @{ |
AnnaBridge | 163:e59c8e839560 | 547 | */ |
AnnaBridge | 163:e59c8e839560 | 548 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 163:e59c8e839560 | 549 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 163:e59c8e839560 | 550 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 163:e59c8e839560 | 551 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 163:e59c8e839560 | 552 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
AnnaBridge | 163:e59c8e839560 | 553 | /** |
AnnaBridge | 163:e59c8e839560 | 554 | * @} |
AnnaBridge | 163:e59c8e839560 | 555 | */ |
AnnaBridge | 163:e59c8e839560 | 556 | |
AnnaBridge | 163:e59c8e839560 | 557 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
AnnaBridge | 163:e59c8e839560 | 558 | * @{ |
AnnaBridge | 163:e59c8e839560 | 559 | */ |
AnnaBridge | 163:e59c8e839560 | 560 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 163:e59c8e839560 | 561 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
AnnaBridge | 163:e59c8e839560 | 562 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
AnnaBridge | 163:e59c8e839560 | 563 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
AnnaBridge | 163:e59c8e839560 | 564 | /** |
AnnaBridge | 163:e59c8e839560 | 565 | * @} |
AnnaBridge | 163:e59c8e839560 | 566 | */ |
AnnaBridge | 163:e59c8e839560 | 567 | |
AnnaBridge | 163:e59c8e839560 | 568 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
AnnaBridge | 163:e59c8e839560 | 569 | * @{ |
AnnaBridge | 163:e59c8e839560 | 570 | */ |
AnnaBridge | 163:e59c8e839560 | 571 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 163:e59c8e839560 | 572 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 163:e59c8e839560 | 573 | /** |
AnnaBridge | 163:e59c8e839560 | 574 | * @} |
AnnaBridge | 163:e59c8e839560 | 575 | */ |
AnnaBridge | 163:e59c8e839560 | 576 | |
AnnaBridge | 163:e59c8e839560 | 577 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
AnnaBridge | 163:e59c8e839560 | 578 | * @{ |
AnnaBridge | 163:e59c8e839560 | 579 | */ |
AnnaBridge | 163:e59c8e839560 | 580 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 163:e59c8e839560 | 581 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
AnnaBridge | 163:e59c8e839560 | 582 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
AnnaBridge | 163:e59c8e839560 | 583 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
AnnaBridge | 163:e59c8e839560 | 584 | /** |
AnnaBridge | 163:e59c8e839560 | 585 | * @} |
AnnaBridge | 163:e59c8e839560 | 586 | */ |
AnnaBridge | 163:e59c8e839560 | 587 | |
AnnaBridge | 163:e59c8e839560 | 588 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state |
AnnaBridge | 163:e59c8e839560 | 589 | * @{ |
AnnaBridge | 163:e59c8e839560 | 590 | */ |
AnnaBridge | 163:e59c8e839560 | 591 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
AnnaBridge | 163:e59c8e839560 | 592 | #define TIM_OSSR_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 593 | /** |
AnnaBridge | 163:e59c8e839560 | 594 | * @} |
AnnaBridge | 163:e59c8e839560 | 595 | */ |
AnnaBridge | 163:e59c8e839560 | 596 | |
AnnaBridge | 163:e59c8e839560 | 597 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state |
AnnaBridge | 163:e59c8e839560 | 598 | * @{ |
AnnaBridge | 163:e59c8e839560 | 599 | */ |
AnnaBridge | 163:e59c8e839560 | 600 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
AnnaBridge | 163:e59c8e839560 | 601 | #define TIM_OSSI_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 602 | /** |
AnnaBridge | 163:e59c8e839560 | 603 | * @} |
AnnaBridge | 163:e59c8e839560 | 604 | */ |
AnnaBridge | 163:e59c8e839560 | 605 | |
AnnaBridge | 163:e59c8e839560 | 606 | /** @defgroup TIM_Lock_level TIM Lock level |
AnnaBridge | 163:e59c8e839560 | 607 | * @{ |
AnnaBridge | 163:e59c8e839560 | 608 | */ |
AnnaBridge | 163:e59c8e839560 | 609 | #define TIM_LOCKLEVEL_OFF (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 610 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
AnnaBridge | 163:e59c8e839560 | 611 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
AnnaBridge | 163:e59c8e839560 | 612 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
AnnaBridge | 163:e59c8e839560 | 613 | /** |
AnnaBridge | 163:e59c8e839560 | 614 | * @} |
AnnaBridge | 163:e59c8e839560 | 615 | */ |
AnnaBridge | 163:e59c8e839560 | 616 | |
AnnaBridge | 163:e59c8e839560 | 617 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable |
AnnaBridge | 163:e59c8e839560 | 618 | * @{ |
AnnaBridge | 163:e59c8e839560 | 619 | */ |
AnnaBridge | 163:e59c8e839560 | 620 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
AnnaBridge | 163:e59c8e839560 | 621 | #define TIM_BREAK_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 622 | /** |
AnnaBridge | 163:e59c8e839560 | 623 | * @} |
AnnaBridge | 163:e59c8e839560 | 624 | */ |
AnnaBridge | 163:e59c8e839560 | 625 | |
AnnaBridge | 163:e59c8e839560 | 626 | /** @defgroup TIM_Break_Polarity TIM Break Input Polarity |
AnnaBridge | 163:e59c8e839560 | 627 | * @{ |
AnnaBridge | 163:e59c8e839560 | 628 | */ |
AnnaBridge | 163:e59c8e839560 | 629 | #define TIM_BREAKPOLARITY_LOW (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 630 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
AnnaBridge | 163:e59c8e839560 | 631 | /** |
AnnaBridge | 163:e59c8e839560 | 632 | * @} |
AnnaBridge | 163:e59c8e839560 | 633 | */ |
AnnaBridge | 163:e59c8e839560 | 634 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
AnnaBridge | 163:e59c8e839560 | 635 | * @{ |
AnnaBridge | 163:e59c8e839560 | 636 | */ |
AnnaBridge | 163:e59c8e839560 | 637 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
AnnaBridge | 163:e59c8e839560 | 638 | #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 639 | /** |
AnnaBridge | 163:e59c8e839560 | 640 | * @} |
AnnaBridge | 163:e59c8e839560 | 641 | */ |
AnnaBridge | 163:e59c8e839560 | 642 | |
AnnaBridge | 163:e59c8e839560 | 643 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
AnnaBridge | 163:e59c8e839560 | 644 | * @{ |
AnnaBridge | 163:e59c8e839560 | 645 | */ |
AnnaBridge | 163:e59c8e839560 | 646 | #define TIM_TRGO_RESET (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 647 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
AnnaBridge | 163:e59c8e839560 | 648 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
AnnaBridge | 163:e59c8e839560 | 649 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 163:e59c8e839560 | 650 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
AnnaBridge | 163:e59c8e839560 | 651 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
AnnaBridge | 163:e59c8e839560 | 652 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
AnnaBridge | 163:e59c8e839560 | 653 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 163:e59c8e839560 | 654 | /** |
AnnaBridge | 163:e59c8e839560 | 655 | * @} |
AnnaBridge | 163:e59c8e839560 | 656 | */ |
AnnaBridge | 163:e59c8e839560 | 657 | |
AnnaBridge | 163:e59c8e839560 | 658 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
AnnaBridge | 163:e59c8e839560 | 659 | * @{ |
AnnaBridge | 163:e59c8e839560 | 660 | */ |
AnnaBridge | 163:e59c8e839560 | 661 | #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) |
AnnaBridge | 163:e59c8e839560 | 662 | #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 663 | /** |
AnnaBridge | 163:e59c8e839560 | 664 | * @} |
AnnaBridge | 163:e59c8e839560 | 665 | */ |
AnnaBridge | 163:e59c8e839560 | 666 | |
AnnaBridge | 163:e59c8e839560 | 667 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
AnnaBridge | 163:e59c8e839560 | 668 | * @{ |
AnnaBridge | 163:e59c8e839560 | 669 | */ |
AnnaBridge | 163:e59c8e839560 | 670 | #define TIM_TS_ITR0 (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 671 | #define TIM_TS_ITR1 (0x0010U) |
AnnaBridge | 163:e59c8e839560 | 672 | #define TIM_TS_ITR2 (0x0020U) |
AnnaBridge | 163:e59c8e839560 | 673 | #define TIM_TS_ITR3 (0x0030U) |
AnnaBridge | 163:e59c8e839560 | 674 | #define TIM_TS_TI1F_ED (0x0040U) |
AnnaBridge | 163:e59c8e839560 | 675 | #define TIM_TS_TI1FP1 (0x0050U) |
AnnaBridge | 163:e59c8e839560 | 676 | #define TIM_TS_TI2FP2 (0x0060U) |
AnnaBridge | 163:e59c8e839560 | 677 | #define TIM_TS_ETRF (0x0070U) |
AnnaBridge | 163:e59c8e839560 | 678 | #define TIM_TS_NONE (0xFFFFU) |
AnnaBridge | 163:e59c8e839560 | 679 | /** |
AnnaBridge | 163:e59c8e839560 | 680 | * @} |
AnnaBridge | 163:e59c8e839560 | 681 | */ |
AnnaBridge | 163:e59c8e839560 | 682 | |
AnnaBridge | 163:e59c8e839560 | 683 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
AnnaBridge | 163:e59c8e839560 | 684 | * @{ |
AnnaBridge | 163:e59c8e839560 | 685 | */ |
AnnaBridge | 163:e59c8e839560 | 686 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 163:e59c8e839560 | 687 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 163:e59c8e839560 | 688 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 163:e59c8e839560 | 689 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 163:e59c8e839560 | 690 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 163:e59c8e839560 | 691 | /** |
AnnaBridge | 163:e59c8e839560 | 692 | * @} |
AnnaBridge | 163:e59c8e839560 | 693 | */ |
AnnaBridge | 163:e59c8e839560 | 694 | |
AnnaBridge | 163:e59c8e839560 | 695 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
AnnaBridge | 163:e59c8e839560 | 696 | * @{ |
AnnaBridge | 163:e59c8e839560 | 697 | */ |
AnnaBridge | 163:e59c8e839560 | 698 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 163:e59c8e839560 | 699 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
AnnaBridge | 163:e59c8e839560 | 700 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
AnnaBridge | 163:e59c8e839560 | 701 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
AnnaBridge | 163:e59c8e839560 | 702 | /** |
AnnaBridge | 163:e59c8e839560 | 703 | * @} |
AnnaBridge | 163:e59c8e839560 | 704 | */ |
AnnaBridge | 163:e59c8e839560 | 705 | |
AnnaBridge | 163:e59c8e839560 | 706 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
AnnaBridge | 163:e59c8e839560 | 707 | * @{ |
AnnaBridge | 163:e59c8e839560 | 708 | */ |
AnnaBridge | 163:e59c8e839560 | 709 | #define TIM_TI1SELECTION_CH1 (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 710 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
AnnaBridge | 163:e59c8e839560 | 711 | /** |
AnnaBridge | 163:e59c8e839560 | 712 | * @} |
AnnaBridge | 163:e59c8e839560 | 713 | */ |
AnnaBridge | 163:e59c8e839560 | 714 | |
AnnaBridge | 163:e59c8e839560 | 715 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
AnnaBridge | 163:e59c8e839560 | 716 | * @{ |
AnnaBridge | 163:e59c8e839560 | 717 | */ |
AnnaBridge | 163:e59c8e839560 | 718 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) |
AnnaBridge | 163:e59c8e839560 | 719 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) |
AnnaBridge | 163:e59c8e839560 | 720 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) |
AnnaBridge | 163:e59c8e839560 | 721 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) |
AnnaBridge | 163:e59c8e839560 | 722 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) |
AnnaBridge | 163:e59c8e839560 | 723 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) |
AnnaBridge | 163:e59c8e839560 | 724 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) |
AnnaBridge | 163:e59c8e839560 | 725 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) |
AnnaBridge | 163:e59c8e839560 | 726 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) |
AnnaBridge | 163:e59c8e839560 | 727 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) |
AnnaBridge | 163:e59c8e839560 | 728 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) |
AnnaBridge | 163:e59c8e839560 | 729 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) |
AnnaBridge | 163:e59c8e839560 | 730 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) |
AnnaBridge | 163:e59c8e839560 | 731 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) |
AnnaBridge | 163:e59c8e839560 | 732 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) |
AnnaBridge | 163:e59c8e839560 | 733 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) |
AnnaBridge | 163:e59c8e839560 | 734 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) |
AnnaBridge | 163:e59c8e839560 | 735 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) |
AnnaBridge | 163:e59c8e839560 | 736 | /** |
AnnaBridge | 163:e59c8e839560 | 737 | * @} |
AnnaBridge | 163:e59c8e839560 | 738 | */ |
AnnaBridge | 163:e59c8e839560 | 739 | |
AnnaBridge | 163:e59c8e839560 | 740 | /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index |
AnnaBridge | 163:e59c8e839560 | 741 | * @{ |
AnnaBridge | 163:e59c8e839560 | 742 | */ |
AnnaBridge | 163:e59c8e839560 | 743 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 744 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 745 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 746 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 747 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 748 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 749 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ |
AnnaBridge | 163:e59c8e839560 | 750 | /** |
AnnaBridge | 163:e59c8e839560 | 751 | * @} |
AnnaBridge | 163:e59c8e839560 | 752 | */ |
AnnaBridge | 163:e59c8e839560 | 753 | |
AnnaBridge | 163:e59c8e839560 | 754 | /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State |
AnnaBridge | 163:e59c8e839560 | 755 | * @{ |
AnnaBridge | 163:e59c8e839560 | 756 | */ |
AnnaBridge | 163:e59c8e839560 | 757 | #define TIM_CCx_ENABLE (0x0001U) |
AnnaBridge | 163:e59c8e839560 | 758 | #define TIM_CCx_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 759 | #define TIM_CCxN_ENABLE (0x0004U) |
AnnaBridge | 163:e59c8e839560 | 760 | #define TIM_CCxN_DISABLE (0x0000U) |
AnnaBridge | 163:e59c8e839560 | 761 | /** |
AnnaBridge | 163:e59c8e839560 | 762 | * @} |
AnnaBridge | 163:e59c8e839560 | 763 | */ |
AnnaBridge | 163:e59c8e839560 | 764 | |
AnnaBridge | 163:e59c8e839560 | 765 | /** |
AnnaBridge | 163:e59c8e839560 | 766 | * @} |
AnnaBridge | 163:e59c8e839560 | 767 | */ |
AnnaBridge | 163:e59c8e839560 | 768 | /* End of exported constants -------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 769 | |
AnnaBridge | 163:e59c8e839560 | 770 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 771 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
AnnaBridge | 163:e59c8e839560 | 772 | * @{ |
AnnaBridge | 163:e59c8e839560 | 773 | */ |
AnnaBridge | 163:e59c8e839560 | 774 | |
AnnaBridge | 163:e59c8e839560 | 775 | /** @brief Reset TIM handle state |
AnnaBridge | 168:b9e159c1930a | 776 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 163:e59c8e839560 | 777 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 778 | */ |
AnnaBridge | 163:e59c8e839560 | 779 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
AnnaBridge | 163:e59c8e839560 | 780 | |
AnnaBridge | 163:e59c8e839560 | 781 | /** |
AnnaBridge | 163:e59c8e839560 | 782 | * @brief Enable the TIM peripheral. |
AnnaBridge | 168:b9e159c1930a | 783 | * @param __HANDLE__ TIM handle |
AnnaBridge | 163:e59c8e839560 | 784 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 785 | */ |
AnnaBridge | 163:e59c8e839560 | 786 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
AnnaBridge | 163:e59c8e839560 | 787 | |
AnnaBridge | 163:e59c8e839560 | 788 | /** |
AnnaBridge | 163:e59c8e839560 | 789 | * @brief Enable the TIM main Output. |
AnnaBridge | 168:b9e159c1930a | 790 | * @param __HANDLE__ TIM handle |
AnnaBridge | 163:e59c8e839560 | 791 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 792 | */ |
AnnaBridge | 163:e59c8e839560 | 793 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
AnnaBridge | 163:e59c8e839560 | 794 | |
AnnaBridge | 163:e59c8e839560 | 795 | /** |
AnnaBridge | 163:e59c8e839560 | 796 | * @brief Disable the TIM peripheral. |
AnnaBridge | 168:b9e159c1930a | 797 | * @param __HANDLE__ TIM handle |
AnnaBridge | 163:e59c8e839560 | 798 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 799 | */ |
AnnaBridge | 163:e59c8e839560 | 800 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 801 | do { \ |
AnnaBridge | 163:e59c8e839560 | 802 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ |
AnnaBridge | 163:e59c8e839560 | 803 | { \ |
AnnaBridge | 163:e59c8e839560 | 804 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ |
AnnaBridge | 163:e59c8e839560 | 805 | { \ |
AnnaBridge | 163:e59c8e839560 | 806 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
AnnaBridge | 163:e59c8e839560 | 807 | } \ |
AnnaBridge | 163:e59c8e839560 | 808 | } \ |
AnnaBridge | 163:e59c8e839560 | 809 | } while(0U) |
AnnaBridge | 163:e59c8e839560 | 810 | /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 163:e59c8e839560 | 811 | channels have been disabled */ |
AnnaBridge | 163:e59c8e839560 | 812 | /** |
AnnaBridge | 163:e59c8e839560 | 813 | * @brief Disable the TIM main Output. |
AnnaBridge | 168:b9e159c1930a | 814 | * @param __HANDLE__ TIM handle |
AnnaBridge | 163:e59c8e839560 | 815 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 816 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
AnnaBridge | 163:e59c8e839560 | 817 | */ |
AnnaBridge | 163:e59c8e839560 | 818 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 819 | do { \ |
AnnaBridge | 163:e59c8e839560 | 820 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ |
AnnaBridge | 163:e59c8e839560 | 821 | { \ |
AnnaBridge | 163:e59c8e839560 | 822 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ |
AnnaBridge | 163:e59c8e839560 | 823 | { \ |
AnnaBridge | 163:e59c8e839560 | 824 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
AnnaBridge | 163:e59c8e839560 | 825 | } \ |
AnnaBridge | 163:e59c8e839560 | 826 | } \ |
AnnaBridge | 163:e59c8e839560 | 827 | } while(0U) |
AnnaBridge | 163:e59c8e839560 | 828 | |
AnnaBridge | 163:e59c8e839560 | 829 | /* The Main Output Enable of a timer instance is disabled unconditionally */ |
AnnaBridge | 163:e59c8e839560 | 830 | /** |
AnnaBridge | 163:e59c8e839560 | 831 | * @brief Disable the TIM main Output. |
AnnaBridge | 168:b9e159c1930a | 832 | * @param __HANDLE__ TIM handle |
AnnaBridge | 163:e59c8e839560 | 833 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 834 | * @note The Main Output Enable of a timer instance is disabled uncondiotionally |
AnnaBridge | 163:e59c8e839560 | 835 | */ |
AnnaBridge | 163:e59c8e839560 | 836 | #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) |
AnnaBridge | 163:e59c8e839560 | 837 | |
AnnaBridge | 163:e59c8e839560 | 838 | /** |
AnnaBridge | 163:e59c8e839560 | 839 | * @brief Enables the specified TIM interrupt. |
AnnaBridge | 168:b9e159c1930a | 840 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 841 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
AnnaBridge | 163:e59c8e839560 | 842 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 843 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 163:e59c8e839560 | 844 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 163:e59c8e839560 | 845 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 163:e59c8e839560 | 846 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 163:e59c8e839560 | 847 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 163:e59c8e839560 | 848 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 163:e59c8e839560 | 849 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 163:e59c8e839560 | 850 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 163:e59c8e839560 | 851 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 852 | */ |
AnnaBridge | 163:e59c8e839560 | 853 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
AnnaBridge | 163:e59c8e839560 | 854 | |
AnnaBridge | 163:e59c8e839560 | 855 | /** |
AnnaBridge | 163:e59c8e839560 | 856 | * @brief Disables the specified TIM interrupt. |
AnnaBridge | 168:b9e159c1930a | 857 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 858 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
AnnaBridge | 163:e59c8e839560 | 859 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 860 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 163:e59c8e839560 | 861 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 163:e59c8e839560 | 862 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 163:e59c8e839560 | 863 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 163:e59c8e839560 | 864 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 163:e59c8e839560 | 865 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 163:e59c8e839560 | 866 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 163:e59c8e839560 | 867 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 163:e59c8e839560 | 868 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 869 | */ |
AnnaBridge | 163:e59c8e839560 | 870 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
AnnaBridge | 163:e59c8e839560 | 871 | |
AnnaBridge | 163:e59c8e839560 | 872 | /** |
AnnaBridge | 163:e59c8e839560 | 873 | * @brief Enables the specified DMA request. |
AnnaBridge | 168:b9e159c1930a | 874 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 875 | * @param __DMA__ specifies the TIM DMA request to enable. |
AnnaBridge | 163:e59c8e839560 | 876 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 877 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 163:e59c8e839560 | 878 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 163:e59c8e839560 | 879 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 163:e59c8e839560 | 880 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 163:e59c8e839560 | 881 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 163:e59c8e839560 | 882 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 163:e59c8e839560 | 883 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 163:e59c8e839560 | 884 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 885 | */ |
AnnaBridge | 163:e59c8e839560 | 886 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
AnnaBridge | 163:e59c8e839560 | 887 | |
AnnaBridge | 163:e59c8e839560 | 888 | /** |
AnnaBridge | 163:e59c8e839560 | 889 | * @brief Disables the specified DMA request. |
AnnaBridge | 168:b9e159c1930a | 890 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 891 | * @param __DMA__ specifies the TIM DMA request to disable. |
AnnaBridge | 163:e59c8e839560 | 892 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 893 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 163:e59c8e839560 | 894 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 163:e59c8e839560 | 895 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 163:e59c8e839560 | 896 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 163:e59c8e839560 | 897 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 163:e59c8e839560 | 898 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 163:e59c8e839560 | 899 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 163:e59c8e839560 | 900 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 901 | */ |
AnnaBridge | 163:e59c8e839560 | 902 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
AnnaBridge | 163:e59c8e839560 | 903 | |
AnnaBridge | 163:e59c8e839560 | 904 | /** |
AnnaBridge | 163:e59c8e839560 | 905 | * @brief Checks whether the specified TIM interrupt flag is set or not. |
AnnaBridge | 168:b9e159c1930a | 906 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 907 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
AnnaBridge | 163:e59c8e839560 | 908 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 909 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 163:e59c8e839560 | 910 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 911 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 912 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 913 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 914 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 163:e59c8e839560 | 915 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 163:e59c8e839560 | 916 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 163:e59c8e839560 | 917 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 918 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 919 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 920 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 921 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 163:e59c8e839560 | 922 | */ |
AnnaBridge | 163:e59c8e839560 | 923 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
AnnaBridge | 163:e59c8e839560 | 924 | |
AnnaBridge | 163:e59c8e839560 | 925 | /** |
AnnaBridge | 163:e59c8e839560 | 926 | * @brief Clears the specified TIM interrupt flag. |
AnnaBridge | 168:b9e159c1930a | 927 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 168:b9e159c1930a | 928 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
AnnaBridge | 163:e59c8e839560 | 929 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 930 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 163:e59c8e839560 | 931 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 932 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 933 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 934 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 163:e59c8e839560 | 935 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 163:e59c8e839560 | 936 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 163:e59c8e839560 | 937 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 163:e59c8e839560 | 938 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 939 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 940 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 941 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 163:e59c8e839560 | 942 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 163:e59c8e839560 | 943 | */ |
AnnaBridge | 163:e59c8e839560 | 944 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
AnnaBridge | 163:e59c8e839560 | 945 | |
AnnaBridge | 163:e59c8e839560 | 946 | /** |
AnnaBridge | 163:e59c8e839560 | 947 | * @brief Checks whether the specified TIM interrupt has occurred or not. |
AnnaBridge | 168:b9e159c1930a | 948 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 949 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
AnnaBridge | 163:e59c8e839560 | 950 | * @retval The state of TIM_IT (SET or RESET). |
AnnaBridge | 163:e59c8e839560 | 951 | */ |
AnnaBridge | 163:e59c8e839560 | 952 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
AnnaBridge | 163:e59c8e839560 | 953 | |
AnnaBridge | 163:e59c8e839560 | 954 | /** |
AnnaBridge | 163:e59c8e839560 | 955 | * @brief Clear the TIM interrupt pending bits |
AnnaBridge | 168:b9e159c1930a | 956 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 957 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 163:e59c8e839560 | 958 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 959 | */ |
AnnaBridge | 163:e59c8e839560 | 960 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
AnnaBridge | 163:e59c8e839560 | 961 | |
AnnaBridge | 163:e59c8e839560 | 962 | /** |
AnnaBridge | 163:e59c8e839560 | 963 | * @brief Indicates whether or not the TIM Counter is used as downcounter |
AnnaBridge | 168:b9e159c1930a | 964 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 163:e59c8e839560 | 965 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
AnnaBridge | 163:e59c8e839560 | 966 | * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. |
AnnaBridge | 163:e59c8e839560 | 967 | */ |
AnnaBridge | 163:e59c8e839560 | 968 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
AnnaBridge | 163:e59c8e839560 | 969 | |
AnnaBridge | 163:e59c8e839560 | 970 | /** |
AnnaBridge | 163:e59c8e839560 | 971 | * @brief Sets the TIM active prescaler register value on update event. |
AnnaBridge | 168:b9e159c1930a | 972 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 973 | * @param __PRESC__ specifies the active prescaler register new value. |
AnnaBridge | 163:e59c8e839560 | 974 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 975 | */ |
AnnaBridge | 168:b9e159c1930a | 976 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
AnnaBridge | 163:e59c8e839560 | 977 | |
AnnaBridge | 163:e59c8e839560 | 978 | /** |
AnnaBridge | 163:e59c8e839560 | 979 | * @brief Sets the TIM Counter Register value on runtime. |
AnnaBridge | 168:b9e159c1930a | 980 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 981 | * @param __COUNTER__ specifies the Counter register new value. |
AnnaBridge | 163:e59c8e839560 | 982 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 983 | */ |
AnnaBridge | 163:e59c8e839560 | 984 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
AnnaBridge | 163:e59c8e839560 | 985 | |
AnnaBridge | 163:e59c8e839560 | 986 | /** |
AnnaBridge | 163:e59c8e839560 | 987 | * @brief Gets the TIM Counter Register value on runtime. |
AnnaBridge | 168:b9e159c1930a | 988 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 989 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
AnnaBridge | 163:e59c8e839560 | 990 | */ |
AnnaBridge | 163:e59c8e839560 | 991 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 992 | ((__HANDLE__)->Instance->CNT) |
AnnaBridge | 163:e59c8e839560 | 993 | |
AnnaBridge | 163:e59c8e839560 | 994 | /** |
AnnaBridge | 163:e59c8e839560 | 995 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
AnnaBridge | 163:e59c8e839560 | 996 | * another time any Init function. |
AnnaBridge | 168:b9e159c1930a | 997 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 998 | * @param __AUTORELOAD__ specifies the Counter register new value. |
AnnaBridge | 163:e59c8e839560 | 999 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1000 | */ |
AnnaBridge | 163:e59c8e839560 | 1001 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
AnnaBridge | 163:e59c8e839560 | 1002 | do{ \ |
AnnaBridge | 163:e59c8e839560 | 1003 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
AnnaBridge | 163:e59c8e839560 | 1004 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
AnnaBridge | 163:e59c8e839560 | 1005 | } while(0U) |
AnnaBridge | 163:e59c8e839560 | 1006 | |
AnnaBridge | 163:e59c8e839560 | 1007 | /** |
AnnaBridge | 163:e59c8e839560 | 1008 | * @brief Gets the TIM Autoreload Register value on runtime |
AnnaBridge | 168:b9e159c1930a | 1009 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1010 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
AnnaBridge | 163:e59c8e839560 | 1011 | */ |
AnnaBridge | 163:e59c8e839560 | 1012 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 1013 | ((__HANDLE__)->Instance->ARR) |
AnnaBridge | 163:e59c8e839560 | 1014 | |
AnnaBridge | 163:e59c8e839560 | 1015 | /** |
AnnaBridge | 163:e59c8e839560 | 1016 | * @brief Sets the TIM Clock Division value on runtime without calling |
AnnaBridge | 163:e59c8e839560 | 1017 | * another time any Init function. |
AnnaBridge | 168:b9e159c1930a | 1018 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1019 | * @param __CKD__ specifies the clock division value. |
AnnaBridge | 163:e59c8e839560 | 1020 | * This parameter can be one of the following value: |
AnnaBridge | 168:b9e159c1930a | 1021 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 168:b9e159c1930a | 1022 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 168:b9e159c1930a | 1023 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 163:e59c8e839560 | 1024 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1025 | */ |
AnnaBridge | 163:e59c8e839560 | 1026 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
AnnaBridge | 163:e59c8e839560 | 1027 | do{ \ |
AnnaBridge | 163:e59c8e839560 | 1028 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
AnnaBridge | 163:e59c8e839560 | 1029 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
AnnaBridge | 163:e59c8e839560 | 1030 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
AnnaBridge | 163:e59c8e839560 | 1031 | } while(0U) |
AnnaBridge | 163:e59c8e839560 | 1032 | |
AnnaBridge | 163:e59c8e839560 | 1033 | /** |
AnnaBridge | 163:e59c8e839560 | 1034 | * @brief Gets the TIM Clock Division value on runtime |
AnnaBridge | 168:b9e159c1930a | 1035 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1036 | * @retval The clock division can be one of the following values: |
AnnaBridge | 168:b9e159c1930a | 1037 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 168:b9e159c1930a | 1038 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 168:b9e159c1930a | 1039 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 163:e59c8e839560 | 1040 | */ |
AnnaBridge | 163:e59c8e839560 | 1041 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 1042 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
AnnaBridge | 163:e59c8e839560 | 1043 | |
AnnaBridge | 163:e59c8e839560 | 1044 | /** |
AnnaBridge | 163:e59c8e839560 | 1045 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
AnnaBridge | 163:e59c8e839560 | 1046 | * another time HAL_TIM_IC_ConfigChannel() function. |
AnnaBridge | 168:b9e159c1930a | 1047 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1048 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 163:e59c8e839560 | 1049 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1050 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 163:e59c8e839560 | 1051 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 163:e59c8e839560 | 1052 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 163:e59c8e839560 | 1053 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 168:b9e159c1930a | 1054 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
AnnaBridge | 163:e59c8e839560 | 1055 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1056 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 163:e59c8e839560 | 1057 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 163:e59c8e839560 | 1058 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 163:e59c8e839560 | 1059 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 163:e59c8e839560 | 1060 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1061 | */ |
AnnaBridge | 163:e59c8e839560 | 1062 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 163:e59c8e839560 | 1063 | do{ \ |
AnnaBridge | 163:e59c8e839560 | 1064 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 163:e59c8e839560 | 1065 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
AnnaBridge | 163:e59c8e839560 | 1066 | } while(0U) |
AnnaBridge | 163:e59c8e839560 | 1067 | |
AnnaBridge | 163:e59c8e839560 | 1068 | /** |
AnnaBridge | 163:e59c8e839560 | 1069 | * @brief Gets the TIM Input Capture prescaler on runtime |
AnnaBridge | 168:b9e159c1930a | 1070 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1071 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 163:e59c8e839560 | 1072 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1073 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
AnnaBridge | 163:e59c8e839560 | 1074 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
AnnaBridge | 163:e59c8e839560 | 1075 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
AnnaBridge | 163:e59c8e839560 | 1076 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
AnnaBridge | 168:b9e159c1930a | 1077 | * @retval The input capture prescaler can be one of the following values: |
AnnaBridge | 168:b9e159c1930a | 1078 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 168:b9e159c1930a | 1079 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 168:b9e159c1930a | 1080 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 168:b9e159c1930a | 1081 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 163:e59c8e839560 | 1082 | */ |
AnnaBridge | 163:e59c8e839560 | 1083 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 163:e59c8e839560 | 1084 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 163:e59c8e839560 | 1085 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
AnnaBridge | 163:e59c8e839560 | 1086 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 163:e59c8e839560 | 1087 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
AnnaBridge | 163:e59c8e839560 | 1088 | |
AnnaBridge | 163:e59c8e839560 | 1089 | /** |
AnnaBridge | 163:e59c8e839560 | 1090 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 168:b9e159c1930a | 1091 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 163:e59c8e839560 | 1092 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
AnnaBridge | 163:e59c8e839560 | 1093 | * overflow/underflow generates an update interrupt or DMA request (if |
AnnaBridge | 163:e59c8e839560 | 1094 | * enabled) |
AnnaBridge | 163:e59c8e839560 | 1095 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1096 | */ |
AnnaBridge | 163:e59c8e839560 | 1097 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 1098 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
AnnaBridge | 163:e59c8e839560 | 1099 | |
AnnaBridge | 163:e59c8e839560 | 1100 | /** |
AnnaBridge | 163:e59c8e839560 | 1101 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 168:b9e159c1930a | 1102 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 163:e59c8e839560 | 1103 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
AnnaBridge | 163:e59c8e839560 | 1104 | * following events generate an update interrupt or DMA request (if |
AnnaBridge | 163:e59c8e839560 | 1105 | * enabled): |
AnnaBridge | 163:e59c8e839560 | 1106 | * (+) Counter overflow/underflow |
AnnaBridge | 163:e59c8e839560 | 1107 | * (+) Setting the UG bit |
AnnaBridge | 163:e59c8e839560 | 1108 | * (+) Update generation through the slave mode controller |
AnnaBridge | 163:e59c8e839560 | 1109 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1110 | */ |
AnnaBridge | 163:e59c8e839560 | 1111 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
AnnaBridge | 163:e59c8e839560 | 1112 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
AnnaBridge | 163:e59c8e839560 | 1113 | |
AnnaBridge | 163:e59c8e839560 | 1114 | /** |
AnnaBridge | 163:e59c8e839560 | 1115 | * @brief Sets the TIM Capture x input polarity on runtime. |
AnnaBridge | 168:b9e159c1930a | 1116 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 168:b9e159c1930a | 1117 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 163:e59c8e839560 | 1118 | * This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1119 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 163:e59c8e839560 | 1120 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 163:e59c8e839560 | 1121 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 163:e59c8e839560 | 1122 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 168:b9e159c1930a | 1123 | * @param __POLARITY__ Polarity for TIx source |
AnnaBridge | 163:e59c8e839560 | 1124 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
AnnaBridge | 163:e59c8e839560 | 1125 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
AnnaBridge | 163:e59c8e839560 | 1126 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
AnnaBridge | 163:e59c8e839560 | 1127 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1128 | */ |
AnnaBridge | 163:e59c8e839560 | 1129 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 163:e59c8e839560 | 1130 | do{ \ |
AnnaBridge | 163:e59c8e839560 | 1131 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 163:e59c8e839560 | 1132 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
AnnaBridge | 163:e59c8e839560 | 1133 | }while(0U) |
AnnaBridge | 163:e59c8e839560 | 1134 | |
AnnaBridge | 163:e59c8e839560 | 1135 | /** |
AnnaBridge | 163:e59c8e839560 | 1136 | * @} |
AnnaBridge | 163:e59c8e839560 | 1137 | */ |
AnnaBridge | 163:e59c8e839560 | 1138 | /* End of exported macros ----------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1139 | |
AnnaBridge | 163:e59c8e839560 | 1140 | /* Private Constants -----------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1141 | /** @defgroup TIM_Private_Constants TIM Private Constants |
AnnaBridge | 163:e59c8e839560 | 1142 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1143 | */ |
AnnaBridge | 163:e59c8e839560 | 1144 | |
AnnaBridge | 163:e59c8e839560 | 1145 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 163:e59c8e839560 | 1146 | channels have been disabled */ |
AnnaBridge | 163:e59c8e839560 | 1147 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
AnnaBridge | 163:e59c8e839560 | 1148 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
AnnaBridge | 163:e59c8e839560 | 1149 | |
AnnaBridge | 163:e59c8e839560 | 1150 | /** |
AnnaBridge | 163:e59c8e839560 | 1151 | * @} |
AnnaBridge | 163:e59c8e839560 | 1152 | */ |
AnnaBridge | 163:e59c8e839560 | 1153 | /* End of private constants --------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1154 | |
AnnaBridge | 163:e59c8e839560 | 1155 | /* Private Macros -----------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1156 | /** @defgroup TIM_Private_Macros TIM Private Macros |
AnnaBridge | 163:e59c8e839560 | 1157 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1158 | */ |
AnnaBridge | 163:e59c8e839560 | 1159 | |
AnnaBridge | 163:e59c8e839560 | 1160 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
AnnaBridge | 163:e59c8e839560 | 1161 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
AnnaBridge | 163:e59c8e839560 | 1162 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
AnnaBridge | 163:e59c8e839560 | 1163 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
AnnaBridge | 163:e59c8e839560 | 1164 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
AnnaBridge | 163:e59c8e839560 | 1165 | |
AnnaBridge | 163:e59c8e839560 | 1166 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
AnnaBridge | 163:e59c8e839560 | 1167 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
AnnaBridge | 163:e59c8e839560 | 1168 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
AnnaBridge | 163:e59c8e839560 | 1169 | |
AnnaBridge | 163:e59c8e839560 | 1170 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1171 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
AnnaBridge | 163:e59c8e839560 | 1172 | |
AnnaBridge | 163:e59c8e839560 | 1173 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1174 | ((STATE) == TIM_OCFAST_ENABLE)) |
AnnaBridge | 163:e59c8e839560 | 1175 | |
AnnaBridge | 163:e59c8e839560 | 1176 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
AnnaBridge | 163:e59c8e839560 | 1177 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
AnnaBridge | 163:e59c8e839560 | 1178 | |
AnnaBridge | 163:e59c8e839560 | 1179 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ |
AnnaBridge | 163:e59c8e839560 | 1180 | ((POLARITY) == TIM_OCNPOLARITY_LOW)) |
AnnaBridge | 163:e59c8e839560 | 1181 | |
AnnaBridge | 163:e59c8e839560 | 1182 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
AnnaBridge | 163:e59c8e839560 | 1183 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
AnnaBridge | 163:e59c8e839560 | 1184 | |
AnnaBridge | 163:e59c8e839560 | 1185 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ |
AnnaBridge | 163:e59c8e839560 | 1186 | ((STATE) == TIM_OCNIDLESTATE_RESET)) |
AnnaBridge | 163:e59c8e839560 | 1187 | |
AnnaBridge | 163:e59c8e839560 | 1188 | |
AnnaBridge | 163:e59c8e839560 | 1189 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
AnnaBridge | 163:e59c8e839560 | 1190 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
AnnaBridge | 163:e59c8e839560 | 1191 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
AnnaBridge | 163:e59c8e839560 | 1192 | |
AnnaBridge | 163:e59c8e839560 | 1193 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
AnnaBridge | 163:e59c8e839560 | 1194 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
AnnaBridge | 163:e59c8e839560 | 1195 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
AnnaBridge | 163:e59c8e839560 | 1196 | |
AnnaBridge | 163:e59c8e839560 | 1197 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
AnnaBridge | 163:e59c8e839560 | 1198 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
AnnaBridge | 163:e59c8e839560 | 1199 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
AnnaBridge | 163:e59c8e839560 | 1200 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
AnnaBridge | 163:e59c8e839560 | 1201 | |
AnnaBridge | 163:e59c8e839560 | 1202 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1203 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
AnnaBridge | 163:e59c8e839560 | 1204 | |
AnnaBridge | 163:e59c8e839560 | 1205 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
AnnaBridge | 163:e59c8e839560 | 1206 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
AnnaBridge | 163:e59c8e839560 | 1207 | ((MODE) == TIM_ENCODERMODE_TI12)) |
AnnaBridge | 163:e59c8e839560 | 1208 | |
AnnaBridge | 163:e59c8e839560 | 1209 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
AnnaBridge | 163:e59c8e839560 | 1210 | |
AnnaBridge | 163:e59c8e839560 | 1211 | |
AnnaBridge | 163:e59c8e839560 | 1212 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
AnnaBridge | 163:e59c8e839560 | 1213 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
AnnaBridge | 163:e59c8e839560 | 1214 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
AnnaBridge | 163:e59c8e839560 | 1215 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
AnnaBridge | 163:e59c8e839560 | 1216 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
AnnaBridge | 163:e59c8e839560 | 1217 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
AnnaBridge | 163:e59c8e839560 | 1218 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
AnnaBridge | 163:e59c8e839560 | 1219 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
AnnaBridge | 163:e59c8e839560 | 1220 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
AnnaBridge | 163:e59c8e839560 | 1221 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
AnnaBridge | 163:e59c8e839560 | 1222 | |
AnnaBridge | 163:e59c8e839560 | 1223 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
AnnaBridge | 163:e59c8e839560 | 1224 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
AnnaBridge | 163:e59c8e839560 | 1225 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
AnnaBridge | 163:e59c8e839560 | 1226 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
AnnaBridge | 163:e59c8e839560 | 1227 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
AnnaBridge | 163:e59c8e839560 | 1228 | |
AnnaBridge | 163:e59c8e839560 | 1229 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
AnnaBridge | 163:e59c8e839560 | 1230 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
AnnaBridge | 163:e59c8e839560 | 1231 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
AnnaBridge | 163:e59c8e839560 | 1232 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
AnnaBridge | 163:e59c8e839560 | 1233 | |
AnnaBridge | 163:e59c8e839560 | 1234 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 163:e59c8e839560 | 1235 | |
AnnaBridge | 163:e59c8e839560 | 1236 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
AnnaBridge | 163:e59c8e839560 | 1237 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
AnnaBridge | 163:e59c8e839560 | 1238 | |
AnnaBridge | 163:e59c8e839560 | 1239 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
AnnaBridge | 163:e59c8e839560 | 1240 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
AnnaBridge | 163:e59c8e839560 | 1241 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
AnnaBridge | 163:e59c8e839560 | 1242 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
AnnaBridge | 163:e59c8e839560 | 1243 | |
AnnaBridge | 163:e59c8e839560 | 1244 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 163:e59c8e839560 | 1245 | |
AnnaBridge | 163:e59c8e839560 | 1246 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1247 | ((STATE) == TIM_OSSR_DISABLE)) |
AnnaBridge | 163:e59c8e839560 | 1248 | |
AnnaBridge | 163:e59c8e839560 | 1249 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1250 | ((STATE) == TIM_OSSI_DISABLE)) |
AnnaBridge | 163:e59c8e839560 | 1251 | |
AnnaBridge | 163:e59c8e839560 | 1252 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
AnnaBridge | 163:e59c8e839560 | 1253 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
AnnaBridge | 163:e59c8e839560 | 1254 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
AnnaBridge | 163:e59c8e839560 | 1255 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
AnnaBridge | 163:e59c8e839560 | 1256 | |
AnnaBridge | 163:e59c8e839560 | 1257 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1258 | ((STATE) == TIM_BREAK_DISABLE)) |
AnnaBridge | 163:e59c8e839560 | 1259 | |
AnnaBridge | 163:e59c8e839560 | 1260 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ |
AnnaBridge | 163:e59c8e839560 | 1261 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) |
AnnaBridge | 163:e59c8e839560 | 1262 | |
AnnaBridge | 163:e59c8e839560 | 1263 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1264 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
AnnaBridge | 163:e59c8e839560 | 1265 | |
AnnaBridge | 163:e59c8e839560 | 1266 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
AnnaBridge | 163:e59c8e839560 | 1267 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1268 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
AnnaBridge | 163:e59c8e839560 | 1269 | ((SOURCE) == TIM_TRGO_OC1) || \ |
AnnaBridge | 163:e59c8e839560 | 1270 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
AnnaBridge | 163:e59c8e839560 | 1271 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
AnnaBridge | 163:e59c8e839560 | 1272 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
AnnaBridge | 163:e59c8e839560 | 1273 | ((SOURCE) == TIM_TRGO_OC4REF)) |
AnnaBridge | 163:e59c8e839560 | 1274 | |
AnnaBridge | 163:e59c8e839560 | 1275 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
AnnaBridge | 163:e59c8e839560 | 1276 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
AnnaBridge | 163:e59c8e839560 | 1277 | |
AnnaBridge | 163:e59c8e839560 | 1278 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
AnnaBridge | 163:e59c8e839560 | 1279 | ((SELECTION) == TIM_TS_ITR1) || \ |
AnnaBridge | 163:e59c8e839560 | 1280 | ((SELECTION) == TIM_TS_ITR2) || \ |
AnnaBridge | 163:e59c8e839560 | 1281 | ((SELECTION) == TIM_TS_ITR3) || \ |
AnnaBridge | 163:e59c8e839560 | 1282 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
AnnaBridge | 163:e59c8e839560 | 1283 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
AnnaBridge | 163:e59c8e839560 | 1284 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
AnnaBridge | 163:e59c8e839560 | 1285 | ((SELECTION) == TIM_TS_ETRF)) |
AnnaBridge | 163:e59c8e839560 | 1286 | |
AnnaBridge | 163:e59c8e839560 | 1287 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
AnnaBridge | 163:e59c8e839560 | 1288 | ((SELECTION) == TIM_TS_ITR1) || \ |
AnnaBridge | 163:e59c8e839560 | 1289 | ((SELECTION) == TIM_TS_ITR2) || \ |
AnnaBridge | 163:e59c8e839560 | 1290 | ((SELECTION) == TIM_TS_ITR3) || \ |
AnnaBridge | 163:e59c8e839560 | 1291 | ((SELECTION) == TIM_TS_NONE)) |
AnnaBridge | 163:e59c8e839560 | 1292 | |
AnnaBridge | 163:e59c8e839560 | 1293 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
AnnaBridge | 163:e59c8e839560 | 1294 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
AnnaBridge | 163:e59c8e839560 | 1295 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
AnnaBridge | 163:e59c8e839560 | 1296 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
AnnaBridge | 163:e59c8e839560 | 1297 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
AnnaBridge | 163:e59c8e839560 | 1298 | |
AnnaBridge | 163:e59c8e839560 | 1299 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
AnnaBridge | 163:e59c8e839560 | 1300 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
AnnaBridge | 163:e59c8e839560 | 1301 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
AnnaBridge | 163:e59c8e839560 | 1302 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
AnnaBridge | 163:e59c8e839560 | 1303 | |
AnnaBridge | 163:e59c8e839560 | 1304 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 163:e59c8e839560 | 1305 | |
AnnaBridge | 163:e59c8e839560 | 1306 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
AnnaBridge | 163:e59c8e839560 | 1307 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
AnnaBridge | 163:e59c8e839560 | 1308 | |
AnnaBridge | 163:e59c8e839560 | 1309 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
AnnaBridge | 163:e59c8e839560 | 1310 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1311 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1312 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1313 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1314 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1315 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1316 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1317 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1318 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1319 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1320 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1321 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1322 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1323 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1324 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1325 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
AnnaBridge | 163:e59c8e839560 | 1326 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
AnnaBridge | 163:e59c8e839560 | 1327 | |
AnnaBridge | 168:b9e159c1930a | 1328 | #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) |
AnnaBridge | 168:b9e159c1930a | 1329 | |
AnnaBridge | 163:e59c8e839560 | 1330 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 163:e59c8e839560 | 1331 | |
AnnaBridge | 163:e59c8e839560 | 1332 | /** @brief Set TIM IC prescaler |
AnnaBridge | 168:b9e159c1930a | 1333 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 1334 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 168:b9e159c1930a | 1335 | * @param __ICPSC__ specifies the prescaler value. |
AnnaBridge | 163:e59c8e839560 | 1336 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1337 | */ |
AnnaBridge | 163:e59c8e839560 | 1338 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 163:e59c8e839560 | 1339 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
AnnaBridge | 163:e59c8e839560 | 1340 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
AnnaBridge | 163:e59c8e839560 | 1341 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
AnnaBridge | 163:e59c8e839560 | 1342 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
AnnaBridge | 163:e59c8e839560 | 1343 | |
AnnaBridge | 163:e59c8e839560 | 1344 | /** @brief Reset TIM IC prescaler |
AnnaBridge | 168:b9e159c1930a | 1345 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 1346 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 163:e59c8e839560 | 1347 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1348 | */ |
AnnaBridge | 163:e59c8e839560 | 1349 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 163:e59c8e839560 | 1350 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 163:e59c8e839560 | 1351 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
AnnaBridge | 163:e59c8e839560 | 1352 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 163:e59c8e839560 | 1353 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
AnnaBridge | 163:e59c8e839560 | 1354 | |
AnnaBridge | 163:e59c8e839560 | 1355 | /** @brief Set TIM IC polarity |
AnnaBridge | 168:b9e159c1930a | 1356 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 1357 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 168:b9e159c1930a | 1358 | * @param __POLARITY__ specifies TIM Channel Polarity |
AnnaBridge | 163:e59c8e839560 | 1359 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1360 | */ |
AnnaBridge | 163:e59c8e839560 | 1361 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 163:e59c8e839560 | 1362 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
AnnaBridge | 163:e59c8e839560 | 1363 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
AnnaBridge | 163:e59c8e839560 | 1364 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
AnnaBridge | 163:e59c8e839560 | 1365 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) |
AnnaBridge | 163:e59c8e839560 | 1366 | |
AnnaBridge | 163:e59c8e839560 | 1367 | /** @brief Reset TIM IC polarity |
AnnaBridge | 168:b9e159c1930a | 1368 | * @param __HANDLE__ TIM handle |
AnnaBridge | 168:b9e159c1930a | 1369 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 163:e59c8e839560 | 1370 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1371 | */ |
AnnaBridge | 163:e59c8e839560 | 1372 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 163:e59c8e839560 | 1373 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
AnnaBridge | 163:e59c8e839560 | 1374 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
AnnaBridge | 163:e59c8e839560 | 1375 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
AnnaBridge | 163:e59c8e839560 | 1376 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
AnnaBridge | 163:e59c8e839560 | 1377 | /** |
AnnaBridge | 163:e59c8e839560 | 1378 | * @} |
AnnaBridge | 163:e59c8e839560 | 1379 | */ |
AnnaBridge | 163:e59c8e839560 | 1380 | /* End of private macros -----------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1381 | |
AnnaBridge | 163:e59c8e839560 | 1382 | /* Include TIM HAL Extended module */ |
AnnaBridge | 163:e59c8e839560 | 1383 | #include "stm32f3xx_hal_tim_ex.h" |
AnnaBridge | 163:e59c8e839560 | 1384 | |
AnnaBridge | 163:e59c8e839560 | 1385 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1386 | /** @addtogroup TIM_Exported_Functions |
AnnaBridge | 163:e59c8e839560 | 1387 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1388 | */ |
AnnaBridge | 163:e59c8e839560 | 1389 | |
AnnaBridge | 163:e59c8e839560 | 1390 | /** @addtogroup TIM_Exported_Functions_Group1 |
AnnaBridge | 163:e59c8e839560 | 1391 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1392 | */ |
AnnaBridge | 163:e59c8e839560 | 1393 | /* Time Base functions ********************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1394 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1395 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1396 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1397 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1398 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1399 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1400 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1401 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1402 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1403 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1404 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 163:e59c8e839560 | 1405 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
AnnaBridge | 163:e59c8e839560 | 1406 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1407 | /** |
AnnaBridge | 163:e59c8e839560 | 1408 | * @} |
AnnaBridge | 163:e59c8e839560 | 1409 | */ |
AnnaBridge | 163:e59c8e839560 | 1410 | |
AnnaBridge | 163:e59c8e839560 | 1411 | /** @addtogroup TIM_Exported_Functions_Group2 |
AnnaBridge | 163:e59c8e839560 | 1412 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1413 | */ |
AnnaBridge | 163:e59c8e839560 | 1414 | /* Timer Output Compare functions **********************************************/ |
AnnaBridge | 163:e59c8e839560 | 1415 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1416 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1417 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1418 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1419 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1420 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1421 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1422 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1423 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1424 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1425 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 163:e59c8e839560 | 1426 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 163:e59c8e839560 | 1427 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1428 | |
AnnaBridge | 163:e59c8e839560 | 1429 | /** |
AnnaBridge | 163:e59c8e839560 | 1430 | * @} |
AnnaBridge | 163:e59c8e839560 | 1431 | */ |
AnnaBridge | 163:e59c8e839560 | 1432 | |
AnnaBridge | 163:e59c8e839560 | 1433 | /** @addtogroup TIM_Exported_Functions_Group3 |
AnnaBridge | 163:e59c8e839560 | 1434 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1435 | */ |
AnnaBridge | 163:e59c8e839560 | 1436 | /* Timer PWM functions *********************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1437 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1438 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1439 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1440 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1441 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1442 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1443 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1444 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1445 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1446 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1447 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 163:e59c8e839560 | 1448 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 163:e59c8e839560 | 1449 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1450 | /** |
AnnaBridge | 163:e59c8e839560 | 1451 | * @} |
AnnaBridge | 163:e59c8e839560 | 1452 | */ |
AnnaBridge | 163:e59c8e839560 | 1453 | |
AnnaBridge | 163:e59c8e839560 | 1454 | /** @addtogroup TIM_Exported_Functions_Group4 |
AnnaBridge | 163:e59c8e839560 | 1455 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1456 | */ |
AnnaBridge | 163:e59c8e839560 | 1457 | /* Timer Input Capture functions ***********************************************/ |
AnnaBridge | 163:e59c8e839560 | 1458 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1459 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1460 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1461 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1462 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1463 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1464 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1465 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1466 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1467 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1468 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 163:e59c8e839560 | 1469 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 163:e59c8e839560 | 1470 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1471 | /** |
AnnaBridge | 163:e59c8e839560 | 1472 | * @} |
AnnaBridge | 163:e59c8e839560 | 1473 | */ |
AnnaBridge | 163:e59c8e839560 | 1474 | |
AnnaBridge | 163:e59c8e839560 | 1475 | /** @addtogroup TIM_Exported_Functions_Group5 |
AnnaBridge | 163:e59c8e839560 | 1476 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1477 | */ |
AnnaBridge | 163:e59c8e839560 | 1478 | /* Timer One Pulse functions ***************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1479 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
AnnaBridge | 163:e59c8e839560 | 1480 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1481 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1482 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1483 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1484 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 163:e59c8e839560 | 1485 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 163:e59c8e839560 | 1486 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1487 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 163:e59c8e839560 | 1488 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 163:e59c8e839560 | 1489 | /** |
AnnaBridge | 163:e59c8e839560 | 1490 | * @} |
AnnaBridge | 163:e59c8e839560 | 1491 | */ |
AnnaBridge | 163:e59c8e839560 | 1492 | |
AnnaBridge | 163:e59c8e839560 | 1493 | /** @addtogroup TIM_Exported_Functions_Group6 |
AnnaBridge | 163:e59c8e839560 | 1494 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1495 | */ |
AnnaBridge | 163:e59c8e839560 | 1496 | /* Timer Encoder functions *****************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1497 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
AnnaBridge | 163:e59c8e839560 | 1498 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1499 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1500 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1501 | /* Blocking mode: Polling */ |
AnnaBridge | 163:e59c8e839560 | 1502 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1503 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1504 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 163:e59c8e839560 | 1505 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1506 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1507 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 163:e59c8e839560 | 1508 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
AnnaBridge | 163:e59c8e839560 | 1509 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1510 | |
AnnaBridge | 163:e59c8e839560 | 1511 | /** |
AnnaBridge | 163:e59c8e839560 | 1512 | * @} |
AnnaBridge | 163:e59c8e839560 | 1513 | */ |
AnnaBridge | 163:e59c8e839560 | 1514 | |
AnnaBridge | 163:e59c8e839560 | 1515 | /** @addtogroup TIM_Exported_Functions_Group7 |
AnnaBridge | 163:e59c8e839560 | 1516 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1517 | */ |
AnnaBridge | 163:e59c8e839560 | 1518 | /* Interrupt Handler functions **********************************************/ |
AnnaBridge | 163:e59c8e839560 | 1519 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1520 | /** |
AnnaBridge | 163:e59c8e839560 | 1521 | * @} |
AnnaBridge | 163:e59c8e839560 | 1522 | */ |
AnnaBridge | 163:e59c8e839560 | 1523 | |
AnnaBridge | 163:e59c8e839560 | 1524 | /** @addtogroup TIM_Exported_Functions_Group8 |
AnnaBridge | 163:e59c8e839560 | 1525 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1526 | */ |
AnnaBridge | 163:e59c8e839560 | 1527 | /* Control functions *********************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1528 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1529 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1530 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1531 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
AnnaBridge | 163:e59c8e839560 | 1532 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1533 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
AnnaBridge | 163:e59c8e839560 | 1534 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
AnnaBridge | 163:e59c8e839560 | 1535 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 163:e59c8e839560 | 1536 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 163:e59c8e839560 | 1537 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 163:e59c8e839560 | 1538 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 168:b9e159c1930a | 1539 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 168:b9e159c1930a | 1540 | uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); |
AnnaBridge | 163:e59c8e839560 | 1541 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 163:e59c8e839560 | 1542 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 163:e59c8e839560 | 1543 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 168:b9e159c1930a | 1544 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 168:b9e159c1930a | 1545 | uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); |
AnnaBridge | 163:e59c8e839560 | 1546 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 163:e59c8e839560 | 1547 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
AnnaBridge | 163:e59c8e839560 | 1548 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 163:e59c8e839560 | 1549 | |
AnnaBridge | 163:e59c8e839560 | 1550 | /** |
AnnaBridge | 163:e59c8e839560 | 1551 | * @} |
AnnaBridge | 163:e59c8e839560 | 1552 | */ |
AnnaBridge | 163:e59c8e839560 | 1553 | |
AnnaBridge | 163:e59c8e839560 | 1554 | /** @addtogroup TIM_Exported_Functions_Group9 |
AnnaBridge | 163:e59c8e839560 | 1555 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1556 | */ |
AnnaBridge | 163:e59c8e839560 | 1557 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
AnnaBridge | 163:e59c8e839560 | 1558 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1559 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1560 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1561 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1562 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1563 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1564 | /** |
AnnaBridge | 163:e59c8e839560 | 1565 | * @} |
AnnaBridge | 163:e59c8e839560 | 1566 | */ |
AnnaBridge | 163:e59c8e839560 | 1567 | |
AnnaBridge | 163:e59c8e839560 | 1568 | /** @addtogroup TIM_Exported_Functions_Group10 |
AnnaBridge | 163:e59c8e839560 | 1569 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1570 | */ |
AnnaBridge | 163:e59c8e839560 | 1571 | /* Peripheral State functions **************************************************/ |
AnnaBridge | 163:e59c8e839560 | 1572 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1573 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1574 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1575 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1576 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1577 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 163:e59c8e839560 | 1578 | |
AnnaBridge | 163:e59c8e839560 | 1579 | /** |
AnnaBridge | 163:e59c8e839560 | 1580 | * @} |
AnnaBridge | 163:e59c8e839560 | 1581 | */ |
AnnaBridge | 163:e59c8e839560 | 1582 | |
AnnaBridge | 163:e59c8e839560 | 1583 | /** |
AnnaBridge | 163:e59c8e839560 | 1584 | * @} |
AnnaBridge | 163:e59c8e839560 | 1585 | */ |
AnnaBridge | 163:e59c8e839560 | 1586 | /* End of exported functions -------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1587 | |
AnnaBridge | 163:e59c8e839560 | 1588 | /* Private Functions --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1589 | /** @addtogroup TIM_Private_Functions |
AnnaBridge | 163:e59c8e839560 | 1590 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1591 | */ |
AnnaBridge | 163:e59c8e839560 | 1592 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
AnnaBridge | 163:e59c8e839560 | 1593 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
AnnaBridge | 163:e59c8e839560 | 1594 | void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 163:e59c8e839560 | 1595 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 163:e59c8e839560 | 1596 | void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 163:e59c8e839560 | 1597 | void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 163:e59c8e839560 | 1598 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
AnnaBridge | 163:e59c8e839560 | 1599 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
AnnaBridge | 163:e59c8e839560 | 1600 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 163:e59c8e839560 | 1601 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 163:e59c8e839560 | 1602 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 163:e59c8e839560 | 1603 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
AnnaBridge | 163:e59c8e839560 | 1604 | /** |
AnnaBridge | 163:e59c8e839560 | 1605 | * @} |
AnnaBridge | 163:e59c8e839560 | 1606 | */ |
AnnaBridge | 163:e59c8e839560 | 1607 | /* End of private functions --------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1608 | |
AnnaBridge | 163:e59c8e839560 | 1609 | /** |
AnnaBridge | 163:e59c8e839560 | 1610 | * @} |
AnnaBridge | 163:e59c8e839560 | 1611 | */ |
AnnaBridge | 163:e59c8e839560 | 1612 | |
AnnaBridge | 163:e59c8e839560 | 1613 | /** |
AnnaBridge | 163:e59c8e839560 | 1614 | * @} |
AnnaBridge | 163:e59c8e839560 | 1615 | */ |
AnnaBridge | 163:e59c8e839560 | 1616 | |
AnnaBridge | 163:e59c8e839560 | 1617 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 1618 | } |
AnnaBridge | 163:e59c8e839560 | 1619 | #endif |
AnnaBridge | 163:e59c8e839560 | 1620 | |
AnnaBridge | 163:e59c8e839560 | 1621 | #endif /* __STM32F3xx_HAL_TIM_H */ |
AnnaBridge | 163:e59c8e839560 | 1622 | |
AnnaBridge | 163:e59c8e839560 | 1623 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |