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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_fsmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 89:552587b429a1 7 * @brief Header file of FSMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @addtogroup FSMC_LL
bogdanm 89:552587b429a1 54 * @{
Kojto 99:dbbf35b96557 55 */
bogdanm 89:552587b429a1 56
Kojto 122:f9eeca106725 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
Kojto 99:dbbf35b96557 58 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
bogdanm 89:552587b429a1 62
bogdanm 89:552587b429a1 63 /**
Kojto 99:dbbf35b96557 64 * @brief FSMC NORSRAM Configuration Structure definition
bogdanm 89:552587b429a1 65 */
bogdanm 89:552587b429a1 66 typedef struct
bogdanm 89:552587b429a1 67 {
bogdanm 89:552587b429a1 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 89:552587b429a1 69 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 89:552587b429a1 70
bogdanm 89:552587b429a1 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 89:552587b429a1 72 multiplexed on the data bus or not.
bogdanm 89:552587b429a1 73 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 89:552587b429a1 74
bogdanm 89:552587b429a1 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 89:552587b429a1 76 the corresponding memory device.
bogdanm 89:552587b429a1 77 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 80 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 89:552587b429a1 83 valid only with synchronous burst Flash memories.
bogdanm 89:552587b429a1 84 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 89:552587b429a1 85
bogdanm 89:552587b429a1 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 89:552587b429a1 87 the Flash memory in burst mode.
bogdanm 89:552587b429a1 88 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 89:552587b429a1 91 memory, valid only when accessing Flash memories in burst mode.
Kojto 122:f9eeca106725 92 This parameter can be a value of @ref FSMC_Wrap_Mode
Kojto 122:f9eeca106725 93 This mode is available only for the STM32F405/407/4015/417xx devices */
bogdanm 89:552587b429a1 94
bogdanm 89:552587b429a1 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 89:552587b429a1 96 clock cycle before the wait state or during the wait state,
bogdanm 89:552587b429a1 97 valid only when accessing memories in burst mode.
bogdanm 89:552587b429a1 98 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 89:552587b429a1 99
bogdanm 89:552587b429a1 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm 89:552587b429a1 101 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 89:552587b429a1 104 signal, valid for Flash memory access in burst mode.
bogdanm 89:552587b429a1 105 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 89:552587b429a1 106
bogdanm 89:552587b429a1 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 89:552587b429a1 108 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 89:552587b429a1 109
bogdanm 89:552587b429a1 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 89:552587b429a1 111 valid only with asynchronous Flash memories.
bogdanm 89:552587b429a1 112 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 89:552587b429a1 113
bogdanm 89:552587b429a1 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 89:552587b429a1 115 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 89:552587b429a1 116
Kojto 122:f9eeca106725 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 122:f9eeca106725 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 119 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 120 This parameter can be a value of @ref FMC_Continous_Clock
Kojto 122:f9eeca106725 121 This mode is available only for the STM32F412Vx/Zx/Rx devices */
Kojto 122:f9eeca106725 122
Kojto 122:f9eeca106725 123 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 122:f9eeca106725 124 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 125 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 126 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 122:f9eeca106725 127 This mode is available only for the STM32F412Vx/Vx devices */
Kojto 122:f9eeca106725 128
Kojto 122:f9eeca106725 129 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 122:f9eeca106725 130 This parameter can be a value of @ref FMC_Page_Size */
bogdanm 89:552587b429a1 131 }FSMC_NORSRAM_InitTypeDef;
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 /**
Kojto 99:dbbf35b96557 134 * @brief FSMC NORSRAM Timing parameters structure definition
bogdanm 89:552587b429a1 135 */
bogdanm 89:552587b429a1 136 typedef struct
bogdanm 89:552587b429a1 137 {
bogdanm 89:552587b429a1 138 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 139 the duration of the address setup time.
bogdanm 89:552587b429a1 140 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 141 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 142
bogdanm 89:552587b429a1 143 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 144 the duration of the address hold time.
bogdanm 89:552587b429a1 145 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 89:552587b429a1 146 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 147
bogdanm 89:552587b429a1 148 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 149 the duration of the data setup time.
bogdanm 89:552587b429a1 150 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 89:552587b429a1 151 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 89:552587b429a1 152 NOR Flash memories. */
bogdanm 89:552587b429a1 153
bogdanm 89:552587b429a1 154 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 155 the duration of the bus turnaround.
bogdanm 89:552587b429a1 156 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 157 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 89:552587b429a1 158
bogdanm 89:552587b429a1 159 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 89:552587b429a1 160 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 89:552587b429a1 161 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 89:552587b429a1 162 accesses. */
bogdanm 89:552587b429a1 163
bogdanm 89:552587b429a1 164 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 89:552587b429a1 165 to the memory before getting the first data.
bogdanm 89:552587b429a1 166 The parameter value depends on the memory type as shown below:
bogdanm 89:552587b429a1 167 - It must be set to 0 in case of a CRAM
bogdanm 89:552587b429a1 168 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 89:552587b429a1 169 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 89:552587b429a1 170 with synchronous burst mode enable */
bogdanm 89:552587b429a1 171
bogdanm 89:552587b429a1 172 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 89:552587b429a1 173 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 89:552587b429a1 174
bogdanm 89:552587b429a1 175 }FSMC_NORSRAM_TimingTypeDef;
bogdanm 89:552587b429a1 176
Kojto 110:165afa46840b 177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 178 /**
Kojto 99:dbbf35b96557 179 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 180 */
bogdanm 89:552587b429a1 181 typedef struct
bogdanm 89:552587b429a1 182 {
bogdanm 89:552587b429a1 183 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 89:552587b429a1 184 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 89:552587b429a1 185
bogdanm 89:552587b429a1 186 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 89:552587b429a1 187 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 188
bogdanm 89:552587b429a1 189 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 190 This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm 89:552587b429a1 191
bogdanm 89:552587b429a1 192 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 89:552587b429a1 193 This parameter can be any value of @ref FSMC_ECC */
bogdanm 89:552587b429a1 194
bogdanm 89:552587b429a1 195 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 89:552587b429a1 196 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 89:552587b429a1 197
bogdanm 89:552587b429a1 198 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 199 delay between CLE low and RE low.
bogdanm 89:552587b429a1 200 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 201
bogdanm 89:552587b429a1 202 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 203 delay between ALE low and RE low.
bogdanm 89:552587b429a1 204 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 205
Kojto 122:f9eeca106725 206 }FSMC_NAND_InitTypeDef;
bogdanm 89:552587b429a1 207
bogdanm 89:552587b429a1 208 /**
Kojto 99:dbbf35b96557 209 * @brief FSMC NAND/PCCARD Timing parameters structure definition
bogdanm 89:552587b429a1 210 */
bogdanm 89:552587b429a1 211 typedef struct
bogdanm 89:552587b429a1 212 {
bogdanm 89:552587b429a1 213 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 89:552587b429a1 214 the command assertion for NAND-Flash read or write access
bogdanm 89:552587b429a1 215 to common/Attribute or I/O memory space (depending on
bogdanm 89:552587b429a1 216 the memory space timing to be configured).
bogdanm 89:552587b429a1 217 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 218
bogdanm 89:552587b429a1 219 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 89:552587b429a1 220 command for NAND-Flash read or write access to
bogdanm 89:552587b429a1 221 common/Attribute or I/O memory space (depending on the
bogdanm 89:552587b429a1 222 memory space timing to be configured).
bogdanm 89:552587b429a1 223 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 224
bogdanm 89:552587b429a1 225 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 89:552587b429a1 226 (and data for write access) after the command de-assertion
bogdanm 89:552587b429a1 227 for NAND-Flash read or write access to common/Attribute
bogdanm 89:552587b429a1 228 or I/O memory space (depending on the memory space timing
bogdanm 89:552587b429a1 229 to be configured).
bogdanm 89:552587b429a1 230 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 231
bogdanm 89:552587b429a1 232 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 89:552587b429a1 233 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 89:552587b429a1 234 write access to common/Attribute or I/O memory space (depending
bogdanm 89:552587b429a1 235 on the memory space timing to be configured).
bogdanm 89:552587b429a1 236 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 237
bogdanm 89:552587b429a1 238 }FSMC_NAND_PCC_TimingTypeDef;
bogdanm 89:552587b429a1 239
bogdanm 89:552587b429a1 240 /**
Kojto 99:dbbf35b96557 241 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 242 */
bogdanm 89:552587b429a1 243 typedef struct
bogdanm 89:552587b429a1 244 {
bogdanm 89:552587b429a1 245 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 89:552587b429a1 246 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 247
bogdanm 89:552587b429a1 248 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 249 delay between CLE low and RE low.
bogdanm 89:552587b429a1 250 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 251
bogdanm 89:552587b429a1 252 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 253 delay between ALE low and RE low.
bogdanm 89:552587b429a1 254 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 255
bogdanm 89:552587b429a1 256 }FSMC_PCCARD_InitTypeDef;
Kojto 99:dbbf35b96557 257 /**
Kojto 99:dbbf35b96557 258 * @}
Kojto 99:dbbf35b96557 259 */
Kojto 110:165afa46840b 260 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 261
Kojto 99:dbbf35b96557 262 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 263 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
Kojto 99:dbbf35b96557 264 * @{
Kojto 99:dbbf35b96557 265 */
bogdanm 89:552587b429a1 266
Kojto 99:dbbf35b96557 267 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
bogdanm 89:552587b429a1 268 * @{
bogdanm 89:552587b429a1 269 */
Kojto 99:dbbf35b96557 270 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
bogdanm 89:552587b429a1 271 * @{
bogdanm 89:552587b429a1 272 */
Kojto 122:f9eeca106725 273 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 274 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 275 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 276 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
bogdanm 89:552587b429a1 277 /**
bogdanm 89:552587b429a1 278 * @}
bogdanm 89:552587b429a1 279 */
bogdanm 89:552587b429a1 280
Kojto 99:dbbf35b96557 281 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
bogdanm 89:552587b429a1 282 * @{
bogdanm 89:552587b429a1 283 */
Kojto 122:f9eeca106725 284 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 285 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
bogdanm 89:552587b429a1 286 /**
bogdanm 89:552587b429a1 287 * @}
bogdanm 89:552587b429a1 288 */
bogdanm 89:552587b429a1 289
Kojto 99:dbbf35b96557 290 /** @defgroup FSMC_Memory_Type FSMC Memory Type
bogdanm 89:552587b429a1 291 * @{
bogdanm 89:552587b429a1 292 */
Kojto 122:f9eeca106725 293 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 294 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 295 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
bogdanm 89:552587b429a1 296 /**
bogdanm 89:552587b429a1 297 * @}
bogdanm 89:552587b429a1 298 */
bogdanm 89:552587b429a1 299
Kojto 99:dbbf35b96557 300 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
bogdanm 89:552587b429a1 301 * @{
bogdanm 89:552587b429a1 302 */
Kojto 122:f9eeca106725 303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
bogdanm 89:552587b429a1 306 /**
bogdanm 89:552587b429a1 307 * @}
bogdanm 89:552587b429a1 308 */
bogdanm 89:552587b429a1 309
Kojto 99:dbbf35b96557 310 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
bogdanm 89:552587b429a1 311 * @{
bogdanm 89:552587b429a1 312 */
Kojto 122:f9eeca106725 313 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 314 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
bogdanm 89:552587b429a1 315 /**
bogdanm 89:552587b429a1 316 * @}
bogdanm 89:552587b429a1 317 */
bogdanm 89:552587b429a1 318
Kojto 99:dbbf35b96557 319 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
bogdanm 89:552587b429a1 320 * @{
bogdanm 89:552587b429a1 321 */
Kojto 122:f9eeca106725 322 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 323 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
bogdanm 89:552587b429a1 324 /**
bogdanm 89:552587b429a1 325 * @}
bogdanm 89:552587b429a1 326 */
bogdanm 89:552587b429a1 327
Kojto 99:dbbf35b96557 328 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
bogdanm 89:552587b429a1 329 * @{
bogdanm 89:552587b429a1 330 */
Kojto 122:f9eeca106725 331 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 332 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
bogdanm 89:552587b429a1 333 /**
bogdanm 89:552587b429a1 334 * @}
bogdanm 89:552587b429a1 335 */
bogdanm 89:552587b429a1 336
Kojto 99:dbbf35b96557 337 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
Kojto 122:f9eeca106725 338 * @note These values are available only for the STM32F405/415/407/417xx devices.
Kojto 99:dbbf35b96557 339 * @{
Kojto 99:dbbf35b96557 340 */
Kojto 122:f9eeca106725 341 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 342 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
Kojto 99:dbbf35b96557 343 /**
Kojto 99:dbbf35b96557 344 * @}
Kojto 99:dbbf35b96557 345 */
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
bogdanm 89:552587b429a1 348 * @{
bogdanm 89:552587b429a1 349 */
Kojto 122:f9eeca106725 350 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 351 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
bogdanm 89:552587b429a1 352 /**
bogdanm 89:552587b429a1 353 * @}
bogdanm 89:552587b429a1 354 */
bogdanm 89:552587b429a1 355
Kojto 99:dbbf35b96557 356 /** @defgroup FSMC_Write_Operation FSMC Write Operation
bogdanm 89:552587b429a1 357 * @{
bogdanm 89:552587b429a1 358 */
Kojto 122:f9eeca106725 359 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 360 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
bogdanm 89:552587b429a1 361 /**
bogdanm 89:552587b429a1 362 * @}
bogdanm 89:552587b429a1 363 */
bogdanm 89:552587b429a1 364
Kojto 99:dbbf35b96557 365 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
Kojto 99:dbbf35b96557 366 * @{
Kojto 99:dbbf35b96557 367 */
Kojto 122:f9eeca106725 368 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 369 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
Kojto 99:dbbf35b96557 370 /**
Kojto 99:dbbf35b96557 371 * @}
Kojto 99:dbbf35b96557 372 */
Kojto 99:dbbf35b96557 373
Kojto 99:dbbf35b96557 374 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
Kojto 99:dbbf35b96557 375 * @{
Kojto 99:dbbf35b96557 376 */
Kojto 122:f9eeca106725 377 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 378 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
Kojto 99:dbbf35b96557 379 /**
Kojto 99:dbbf35b96557 380 * @}
Kojto 99:dbbf35b96557 381 */
Kojto 99:dbbf35b96557 382
Kojto 99:dbbf35b96557 383 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
bogdanm 89:552587b429a1 384 * @{
bogdanm 89:552587b429a1 385 */
Kojto 122:f9eeca106725 386 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 387 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
bogdanm 89:552587b429a1 388 /**
bogdanm 89:552587b429a1 389 * @}
Kojto 122:f9eeca106725 390 */
Kojto 122:f9eeca106725 391
Kojto 122:f9eeca106725 392 /** @defgroup FSMC_Page_Size FSMC Page Size
Kojto 122:f9eeca106725 393 * @{
Kojto 122:f9eeca106725 394 */
Kojto 122:f9eeca106725 395 #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 396 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
Kojto 122:f9eeca106725 397 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
Kojto 122:f9eeca106725 398 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
Kojto 122:f9eeca106725 399 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
Kojto 122:f9eeca106725 400 /**
Kojto 122:f9eeca106725 401 * @}
Kojto 122:f9eeca106725 402 */
Kojto 122:f9eeca106725 403
Kojto 122:f9eeca106725 404 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
Kojto 122:f9eeca106725 405 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
Kojto 122:f9eeca106725 406 * @{
Kojto 122:f9eeca106725 407 */
Kojto 122:f9eeca106725 408 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
Kojto 122:f9eeca106725 409 #define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 410 /**
Kojto 122:f9eeca106725 411 * @}
Kojto 122:f9eeca106725 412 */
bogdanm 89:552587b429a1 413
Kojto 99:dbbf35b96557 414 /** @defgroup FSMC_Write_Burst FSMC Write Burst
bogdanm 89:552587b429a1 415 * @{
bogdanm 89:552587b429a1 416 */
Kojto 122:f9eeca106725 417 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 418 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
bogdanm 89:552587b429a1 419 /**
bogdanm 89:552587b429a1 420 * @}
bogdanm 89:552587b429a1 421 */
bogdanm 89:552587b429a1 422
Kojto 99:dbbf35b96557 423 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
Kojto 122:f9eeca106725 424 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
bogdanm 89:552587b429a1 425 * @{
bogdanm 89:552587b429a1 426 */
Kojto 122:f9eeca106725 427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
bogdanm 89:552587b429a1 429 /**
bogdanm 89:552587b429a1 430 * @}
bogdanm 89:552587b429a1 431 */
bogdanm 89:552587b429a1 432
Kojto 99:dbbf35b96557 433 /** @defgroup FSMC_Access_Mode FSMC Access Mode
bogdanm 89:552587b429a1 434 * @{
bogdanm 89:552587b429a1 435 */
Kojto 122:f9eeca106725 436 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 437 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 438 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 439 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
bogdanm 89:552587b429a1 440 /**
bogdanm 89:552587b429a1 441 * @}
bogdanm 89:552587b429a1 442 */
bogdanm 89:552587b429a1 443 /**
bogdanm 89:552587b429a1 444 * @}
bogdanm 89:552587b429a1 445 */
bogdanm 89:552587b429a1 446
Kojto 110:165afa46840b 447 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 448 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
Kojto 99:dbbf35b96557 449 * @{
Kojto 99:dbbf35b96557 450 */
Kojto 99:dbbf35b96557 451 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
Kojto 99:dbbf35b96557 452 * @{
Kojto 99:dbbf35b96557 453 */
Kojto 122:f9eeca106725 454 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 455 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
Kojto 99:dbbf35b96557 456 /**
Kojto 99:dbbf35b96557 457 * @}
Kojto 99:dbbf35b96557 458 */
Kojto 99:dbbf35b96557 459
Kojto 99:dbbf35b96557 460 /** @defgroup FSMC_Wait_feature FSMC Wait feature
bogdanm 89:552587b429a1 461 * @{
bogdanm 89:552587b429a1 462 */
Kojto 122:f9eeca106725 463 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 464 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
bogdanm 89:552587b429a1 465 /**
bogdanm 89:552587b429a1 466 * @}
bogdanm 89:552587b429a1 467 */
bogdanm 89:552587b429a1 468
Kojto 99:dbbf35b96557 469 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
bogdanm 89:552587b429a1 470 * @{
bogdanm 89:552587b429a1 471 */
Kojto 122:f9eeca106725 472 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 473 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
bogdanm 89:552587b429a1 474 /**
bogdanm 89:552587b429a1 475 * @}
bogdanm 89:552587b429a1 476 */
bogdanm 89:552587b429a1 477
Kojto 99:dbbf35b96557 478 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
bogdanm 89:552587b429a1 479 * @{
bogdanm 89:552587b429a1 480 */
Kojto 122:f9eeca106725 481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
bogdanm 89:552587b429a1 483 /**
bogdanm 89:552587b429a1 484 * @}
bogdanm 89:552587b429a1 485 */
bogdanm 89:552587b429a1 486
Kojto 99:dbbf35b96557 487 /** @defgroup FSMC_ECC FSMC ECC
bogdanm 89:552587b429a1 488 * @{
bogdanm 89:552587b429a1 489 */
Kojto 122:f9eeca106725 490 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 491 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
bogdanm 89:552587b429a1 492 /**
bogdanm 89:552587b429a1 493 * @}
bogdanm 89:552587b429a1 494 */
bogdanm 89:552587b429a1 495
Kojto 99:dbbf35b96557 496 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
bogdanm 89:552587b429a1 497 * @{
bogdanm 89:552587b429a1 498 */
Kojto 122:f9eeca106725 499 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 500 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 501 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 502 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
Kojto 122:f9eeca106725 503 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 504 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
bogdanm 89:552587b429a1 505 /**
bogdanm 89:552587b429a1 506 * @}
bogdanm 89:552587b429a1 507 */
bogdanm 89:552587b429a1 508 /**
bogdanm 89:552587b429a1 509 * @}
bogdanm 89:552587b429a1 510 */
Kojto 110:165afa46840b 511 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 110:165afa46840b 512
Kojto 99:dbbf35b96557 513 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
bogdanm 89:552587b429a1 514 * @{
bogdanm 89:552587b429a1 515 */
Kojto 122:f9eeca106725 516 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 517 #define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 518 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 519 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
bogdanm 89:552587b429a1 520 /**
bogdanm 89:552587b429a1 521 * @}
bogdanm 89:552587b429a1 522 */
bogdanm 89:552587b429a1 523
Kojto 99:dbbf35b96557 524 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
bogdanm 89:552587b429a1 525 * @{
bogdanm 89:552587b429a1 526 */
Kojto 122:f9eeca106725 527 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 528 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 529 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 530 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
bogdanm 89:552587b429a1 531 /**
bogdanm 89:552587b429a1 532 * @}
bogdanm 89:552587b429a1 533 */
bogdanm 89:552587b429a1 534
Kojto 99:dbbf35b96557 535 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
Kojto 99:dbbf35b96557 536 * @{
bogdanm 89:552587b429a1 537 */
Kojto 99:dbbf35b96557 538 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
Kojto 99:dbbf35b96557 539 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
Kojto 110:165afa46840b 540 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 541 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
Kojto 99:dbbf35b96557 542 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
Kojto 110:165afa46840b 543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 544
Kojto 99:dbbf35b96557 545 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
Kojto 99:dbbf35b96557 546 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
Kojto 110:165afa46840b 547 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 548 #define FSMC_NAND_DEVICE FSMC_Bank2_3
Kojto 99:dbbf35b96557 549 #define FSMC_PCCARD_DEVICE FSMC_Bank4
Kojto 110:165afa46840b 550 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 551
Kojto 122:f9eeca106725 552 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
Kojto 122:f9eeca106725 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
Kojto 122:f9eeca106725 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
Kojto 122:f9eeca106725 555
bogdanm 89:552587b429a1 556 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 557 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 558 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
bogdanm 89:552587b429a1 559 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
bogdanm 89:552587b429a1 560
bogdanm 89:552587b429a1 561 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
bogdanm 89:552587b429a1 562 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
bogdanm 89:552587b429a1 563 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
bogdanm 89:552587b429a1 564 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
bogdanm 89:552587b429a1 565 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
bogdanm 89:552587b429a1 566 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
bogdanm 89:552587b429a1 567
bogdanm 89:552587b429a1 568 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
bogdanm 89:552587b429a1 569 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
bogdanm 89:552587b429a1 570
Kojto 110:165afa46840b 571 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 572 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
bogdanm 89:552587b429a1 573 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
bogdanm 89:552587b429a1 574 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
bogdanm 89:552587b429a1 575
bogdanm 89:552587b429a1 576 #define FMC_NAND_Init FSMC_NAND_Init
bogdanm 89:552587b429a1 577 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 578 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 579 #define FMC_NAND_DeInit FSMC_NAND_DeInit
bogdanm 89:552587b429a1 580 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
bogdanm 89:552587b429a1 581 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
bogdanm 89:552587b429a1 582 #define FMC_NAND_GetECC FSMC_NAND_GetECC
bogdanm 89:552587b429a1 583 #define FMC_PCCARD_Init FSMC_PCCARD_Init
bogdanm 89:552587b429a1 584 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 585 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 586 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
bogdanm 89:552587b429a1 587 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
bogdanm 89:552587b429a1 588
bogdanm 89:552587b429a1 589 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
bogdanm 89:552587b429a1 590 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
bogdanm 89:552587b429a1 591 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
bogdanm 89:552587b429a1 592 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
bogdanm 89:552587b429a1 593 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
bogdanm 89:552587b429a1 594 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
bogdanm 89:552587b429a1 595 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
bogdanm 89:552587b429a1 596 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
bogdanm 89:552587b429a1 597 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
bogdanm 89:552587b429a1 598 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
bogdanm 89:552587b429a1 599 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
bogdanm 89:552587b429a1 600 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
Kojto 110:165afa46840b 601 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 602
bogdanm 89:552587b429a1 603 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 604 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 110:165afa46840b 605 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 606 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
bogdanm 89:552587b429a1 607 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
Kojto 110:165afa46840b 608 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 609
Kojto 122:f9eeca106725 610 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
Kojto 110:165afa46840b 611 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
Kojto 110:165afa46840b 612 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 122:f9eeca106725 613 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
bogdanm 89:552587b429a1 614 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
bogdanm 89:552587b429a1 615
bogdanm 89:552587b429a1 616 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
Kojto 110:165afa46840b 617 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 618
bogdanm 92:4fc01daae5a5 619 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
bogdanm 92:4fc01daae5a5 620 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
bogdanm 92:4fc01daae5a5 621 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
bogdanm 92:4fc01daae5a5 622
bogdanm 89:552587b429a1 623 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
bogdanm 89:552587b429a1 624 #define FMC_IT_LEVEL FSMC_IT_LEVEL
bogdanm 89:552587b429a1 625 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
bogdanm 89:552587b429a1 626 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
bogdanm 89:552587b429a1 627
bogdanm 89:552587b429a1 628 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
bogdanm 89:552587b429a1 629 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
bogdanm 89:552587b429a1 630 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
bogdanm 89:552587b429a1 631 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
Kojto 99:dbbf35b96557 632 /**
Kojto 99:dbbf35b96557 633 * @}
Kojto 99:dbbf35b96557 634 */
bogdanm 89:552587b429a1 635
Kojto 99:dbbf35b96557 636 /**
Kojto 99:dbbf35b96557 637 * @}
Kojto 99:dbbf35b96557 638 */
Kojto 99:dbbf35b96557 639
Kojto 99:dbbf35b96557 640 /* Private macro -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 641 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
Kojto 99:dbbf35b96557 642 * @{
Kojto 99:dbbf35b96557 643 */
Kojto 99:dbbf35b96557 644
Kojto 99:dbbf35b96557 645 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
Kojto 99:dbbf35b96557 646 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 99:dbbf35b96557 647 * @{
Kojto 99:dbbf35b96557 648 */
Kojto 99:dbbf35b96557 649 /**
Kojto 99:dbbf35b96557 650 * @brief Enable the NORSRAM device access.
Kojto 99:dbbf35b96557 651 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 652 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 653 * @retval none
Kojto 99:dbbf35b96557 654 */
Kojto 99:dbbf35b96557 655 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 656
Kojto 99:dbbf35b96557 657 /**
Kojto 99:dbbf35b96557 658 * @brief Disable the NORSRAM device access.
Kojto 99:dbbf35b96557 659 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 660 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 661 * @retval none
Kojto 99:dbbf35b96557 662 */
Kojto 99:dbbf35b96557 663 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 664 /**
Kojto 99:dbbf35b96557 665 * @}
Kojto 99:dbbf35b96557 666 */
Kojto 99:dbbf35b96557 667
Kojto 99:dbbf35b96557 668 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
Kojto 99:dbbf35b96557 669 * @brief macros to handle NAND device enable/disable
Kojto 99:dbbf35b96557 670 * @{
Kojto 99:dbbf35b96557 671 */
Kojto 110:165afa46840b 672 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 673 /**
Kojto 99:dbbf35b96557 674 * @brief Enable the NAND device access.
Kojto 99:dbbf35b96557 675 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 676 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 677 * @retval none
Kojto 99:dbbf35b96557 678 */
Kojto 99:dbbf35b96557 679 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 680 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 681
Kojto 99:dbbf35b96557 682 /**
Kojto 99:dbbf35b96557 683 * @brief Disable the NAND device access.
Kojto 99:dbbf35b96557 684 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 685 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 686 * @retval none
Kojto 99:dbbf35b96557 687 */
Kojto 99:dbbf35b96557 688 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 689 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 690 /**
Kojto 99:dbbf35b96557 691 * @}
Kojto 99:dbbf35b96557 692 */
Kojto 99:dbbf35b96557 693
Kojto 99:dbbf35b96557 694 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
Kojto 99:dbbf35b96557 695 * @brief macros to handle SRAM read/write operations
Kojto 99:dbbf35b96557 696 * @{
Kojto 99:dbbf35b96557 697 */
Kojto 99:dbbf35b96557 698 /**
Kojto 99:dbbf35b96557 699 * @brief Enable the PCCARD device access.
Kojto 99:dbbf35b96557 700 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 701 * @retval none
Kojto 99:dbbf35b96557 702 */
Kojto 99:dbbf35b96557 703 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 704
Kojto 99:dbbf35b96557 705 /**
Kojto 99:dbbf35b96557 706 * @brief Disable the PCCARD device access.
Kojto 99:dbbf35b96557 707 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 708 * @retval none
Kojto 99:dbbf35b96557 709 */
Kojto 99:dbbf35b96557 710 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 711 /**
Kojto 99:dbbf35b96557 712 * @}
Kojto 99:dbbf35b96557 713 */
Kojto 99:dbbf35b96557 714
Kojto 99:dbbf35b96557 715 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
Kojto 99:dbbf35b96557 716 * @brief macros to handle FSMC flags and interrupts
Kojto 99:dbbf35b96557 717 * @{
Kojto 99:dbbf35b96557 718 */
Kojto 99:dbbf35b96557 719 /**
Kojto 99:dbbf35b96557 720 * @brief Enable the NAND device interrupt.
Kojto 99:dbbf35b96557 721 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 722 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 723 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 724 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 725 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 726 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 727 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 728 * @retval None
Kojto 99:dbbf35b96557 729 */
Kojto 99:dbbf35b96557 730 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 122:f9eeca106725 731 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 99:dbbf35b96557 732
Kojto 99:dbbf35b96557 733 /**
Kojto 99:dbbf35b96557 734 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 735 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 736 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 737 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 738 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 739 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 740 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 741 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 742 * @retval None
Kojto 99:dbbf35b96557 743 */
Kojto 99:dbbf35b96557 744 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 122:f9eeca106725 745 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 122:f9eeca106725 746
Kojto 99:dbbf35b96557 747 /**
Kojto 99:dbbf35b96557 748 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 749 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 750 * @param __BANK__ : FSMC_NAND Bank
Kojto 99:dbbf35b96557 751 * @param __FLAG__ : FSMC_NAND flag
Kojto 99:dbbf35b96557 752 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 753 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 754 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 755 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 756 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 757 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 758 */
Kojto 99:dbbf35b96557 759 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 122:f9eeca106725 760 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 122:f9eeca106725 761
Kojto 99:dbbf35b96557 762 /**
Kojto 99:dbbf35b96557 763 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 764 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 765 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 766 * @param __FLAG__: FSMC_NAND flag
Kojto 99:dbbf35b96557 767 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 768 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 769 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 770 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 771 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 772 * @retval None
Kojto 99:dbbf35b96557 773 */
Kojto 99:dbbf35b96557 774 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 122:f9eeca106725 775 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 122:f9eeca106725 776
Kojto 99:dbbf35b96557 777 /**
Kojto 99:dbbf35b96557 778 * @brief Enable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 779 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 780 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 781 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 782 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 783 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 784 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 785 * @retval None
Kojto 99:dbbf35b96557 786 */
Kojto 99:dbbf35b96557 787 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 788
Kojto 99:dbbf35b96557 789 /**
Kojto 99:dbbf35b96557 790 * @brief Disable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 791 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 792 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 793 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 794 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 795 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 796 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 797 * @retval None
Kojto 99:dbbf35b96557 798 */
Kojto 99:dbbf35b96557 799 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 800
Kojto 99:dbbf35b96557 801 /**
Kojto 99:dbbf35b96557 802 * @brief Get flag status of the PCCARD device.
Kojto 99:dbbf35b96557 803 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 804 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 805 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 806 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 807 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 808 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 809 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 810 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 811 */
Kojto 99:dbbf35b96557 812 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 813
Kojto 99:dbbf35b96557 814 /**
Kojto 99:dbbf35b96557 815 * @brief Clear flag status of the PCCARD device.
Kojto 99:dbbf35b96557 816 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 817 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 818 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 819 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 820 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 821 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 822 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 823 * @retval None
Kojto 99:dbbf35b96557 824 */
Kojto 99:dbbf35b96557 825 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 99:dbbf35b96557 826 /**
Kojto 99:dbbf35b96557 827 * @}
Kojto 99:dbbf35b96557 828 */
Kojto 110:165afa46840b 829 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 830
Kojto 99:dbbf35b96557 831 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 99:dbbf35b96557 832 * @{
Kojto 99:dbbf35b96557 833 */
Kojto 99:dbbf35b96557 834 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
Kojto 99:dbbf35b96557 835 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
Kojto 99:dbbf35b96557 836 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
Kojto 99:dbbf35b96557 837 ((__BANK__) == FSMC_NORSRAM_BANK4))
Kojto 99:dbbf35b96557 838
Kojto 99:dbbf35b96557 839 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 99:dbbf35b96557 840 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 99:dbbf35b96557 841
Kojto 99:dbbf35b96557 842 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
Kojto 99:dbbf35b96557 843 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
Kojto 99:dbbf35b96557 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
Kojto 99:dbbf35b96557 845
Kojto 99:dbbf35b96557 846 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 847 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 849
Kojto 99:dbbf35b96557 850 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
Kojto 99:dbbf35b96557 851 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
Kojto 99:dbbf35b96557 852 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
Kojto 99:dbbf35b96557 853 ((__MODE__) == FSMC_ACCESS_MODE_D))
Kojto 99:dbbf35b96557 854
Kojto 99:dbbf35b96557 855 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
Kojto 99:dbbf35b96557 856 ((BANK) == FSMC_NAND_BANK3))
Kojto 99:dbbf35b96557 857
Kojto 99:dbbf35b96557 858 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 99:dbbf35b96557 859 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 99:dbbf35b96557 860
Kojto 99:dbbf35b96557 861 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 862 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
Kojto 99:dbbf35b96557 865 ((STATE) == FSMC_NAND_ECC_ENABLE))
Kojto 99:dbbf35b96557 866
Kojto 99:dbbf35b96557 867 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 99:dbbf35b96557 868 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 99:dbbf35b96557 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 99:dbbf35b96557 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 99:dbbf35b96557 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 99:dbbf35b96557 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 99:dbbf35b96557 873
Kojto 122:f9eeca106725 874 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 875
Kojto 122:f9eeca106725 876 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 877
Kojto 122:f9eeca106725 878 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 879
Kojto 122:f9eeca106725 880 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 881
Kojto 122:f9eeca106725 882 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 883
Kojto 122:f9eeca106725 884 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 885
Kojto 99:dbbf35b96557 886 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
Kojto 99:dbbf35b96557 887
Kojto 99:dbbf35b96557 888 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
Kojto 99:dbbf35b96557 889
Kojto 99:dbbf35b96557 890 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
Kojto 99:dbbf35b96557 891
Kojto 99:dbbf35b96557 892 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
Kojto 99:dbbf35b96557 893
Kojto 99:dbbf35b96557 894 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 895 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
Kojto 99:dbbf35b96557 896
Kojto 99:dbbf35b96557 897 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 99:dbbf35b96557 898 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 99:dbbf35b96557 899
Kojto 99:dbbf35b96557 900 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 901 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
Kojto 99:dbbf35b96557 902
Kojto 99:dbbf35b96557 903 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 99:dbbf35b96557 904 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
Kojto 99:dbbf35b96557 905
Kojto 99:dbbf35b96557 906 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
Kojto 99:dbbf35b96557 907 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
Kojto 99:dbbf35b96557 908
Kojto 99:dbbf35b96557 909 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
Kojto 99:dbbf35b96557 910 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
Kojto 99:dbbf35b96557 911
Kojto 99:dbbf35b96557 912 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 913 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
Kojto 99:dbbf35b96557 914
Kojto 99:dbbf35b96557 915 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 99:dbbf35b96557 916 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 99:dbbf35b96557 917
Kojto 122:f9eeca106725 918 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
Kojto 99:dbbf35b96557 919
Kojto 99:dbbf35b96557 920 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
Kojto 99:dbbf35b96557 921 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
Kojto 99:dbbf35b96557 922
Kojto 122:f9eeca106725 923 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 924
Kojto 122:f9eeca106725 925 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
Kojto 99:dbbf35b96557 926
Kojto 122:f9eeca106725 927 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
Kojto 99:dbbf35b96557 928
Kojto 122:f9eeca106725 929 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 930
Kojto 99:dbbf35b96557 931 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 99:dbbf35b96557 932 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 99:dbbf35b96557 933
Kojto 122:f9eeca106725 934 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
Kojto 122:f9eeca106725 935
Kojto 122:f9eeca106725 936 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
Kojto 122:f9eeca106725 937 ((SIZE) == FSMC_PAGE_SIZE_128) || \
Kojto 122:f9eeca106725 938 ((SIZE) == FSMC_PAGE_SIZE_256) || \
Kojto 122:f9eeca106725 939 ((SIZE) == FSMC_PAGE_SIZE_1024))
Kojto 122:f9eeca106725 940
Kojto 122:f9eeca106725 941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
Kojto 122:f9eeca106725 942 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
Kojto 99:dbbf35b96557 943
Kojto 99:dbbf35b96557 944 /**
Kojto 99:dbbf35b96557 945 * @}
Kojto 99:dbbf35b96557 946 */
Kojto 99:dbbf35b96557 947 /**
Kojto 99:dbbf35b96557 948 * @}
Kojto 99:dbbf35b96557 949 */
Kojto 99:dbbf35b96557 950
Kojto 99:dbbf35b96557 951 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 952 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
Kojto 99:dbbf35b96557 953 * @{
Kojto 99:dbbf35b96557 954 */
Kojto 99:dbbf35b96557 955
Kojto 99:dbbf35b96557 956 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
Kojto 99:dbbf35b96557 957 * @{
Kojto 99:dbbf35b96557 958 */
Kojto 99:dbbf35b96557 959
Kojto 99:dbbf35b96557 960 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 961 * @{
Kojto 99:dbbf35b96557 962 */
Kojto 99:dbbf35b96557 963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
Kojto 99:dbbf35b96557 964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 99:dbbf35b96557 966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 99:dbbf35b96557 967 /**
Kojto 99:dbbf35b96557 968 * @}
Kojto 99:dbbf35b96557 969 */
Kojto 99:dbbf35b96557 970
Kojto 99:dbbf35b96557 971 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 99:dbbf35b96557 972 * @{
Kojto 99:dbbf35b96557 973 */
Kojto 99:dbbf35b96557 974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 976 /**
Kojto 99:dbbf35b96557 977 * @}
Kojto 99:dbbf35b96557 978 */
Kojto 99:dbbf35b96557 979 /**
Kojto 99:dbbf35b96557 980 * @}
Kojto 99:dbbf35b96557 981 */
Kojto 99:dbbf35b96557 982
Kojto 110:165afa46840b 983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 984 /** @defgroup FSMC_LL_NAND NAND
Kojto 99:dbbf35b96557 985 * @{
Kojto 99:dbbf35b96557 986 */
Kojto 99:dbbf35b96557 987 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 99:dbbf35b96557 988 * @{
Kojto 99:dbbf35b96557 989 */
Kojto 99:dbbf35b96557 990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
Kojto 99:dbbf35b96557 991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 994 /**
Kojto 99:dbbf35b96557 995 * @}
Kojto 99:dbbf35b96557 996 */
Kojto 99:dbbf35b96557 997
Kojto 99:dbbf35b96557 998 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 99:dbbf35b96557 999 * @{
Kojto 99:dbbf35b96557 1000 */
Kojto 99:dbbf35b96557 1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 99:dbbf35b96557 1004 /**
Kojto 99:dbbf35b96557 1005 * @}
Kojto 99:dbbf35b96557 1006 */
Kojto 99:dbbf35b96557 1007 /**
Kojto 99:dbbf35b96557 1008 * @}
Kojto 99:dbbf35b96557 1009 */
Kojto 99:dbbf35b96557 1010
Kojto 99:dbbf35b96557 1011 /** @defgroup FSMC_LL_PCCARD PCCARD
Kojto 99:dbbf35b96557 1012 * @{
Kojto 99:dbbf35b96557 1013 */
Kojto 99:dbbf35b96557 1014 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1015 * @{
Kojto 99:dbbf35b96557 1016 */
Kojto 99:dbbf35b96557 1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
Kojto 99:dbbf35b96557 1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
Kojto 99:dbbf35b96557 1022 /**
Kojto 99:dbbf35b96557 1023 * @}
Kojto 99:dbbf35b96557 1024 */
Kojto 99:dbbf35b96557 1025 /**
Kojto 99:dbbf35b96557 1026 * @}
Kojto 99:dbbf35b96557 1027 */
Kojto 110:165afa46840b 1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 1029
Kojto 99:dbbf35b96557 1030 /**
Kojto 99:dbbf35b96557 1031 * @}
Kojto 99:dbbf35b96557 1032 */
Kojto 122:f9eeca106725 1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
bogdanm 89:552587b429a1 1034
bogdanm 89:552587b429a1 1035 /**
bogdanm 89:552587b429a1 1036 * @}
bogdanm 89:552587b429a1 1037 */
bogdanm 89:552587b429a1 1038
bogdanm 89:552587b429a1 1039 /**
bogdanm 89:552587b429a1 1040 * @}
bogdanm 89:552587b429a1 1041 */
bogdanm 89:552587b429a1 1042
bogdanm 89:552587b429a1 1043 #ifdef __cplusplus
bogdanm 89:552587b429a1 1044 }
bogdanm 89:552587b429a1 1045 #endif
bogdanm 89:552587b429a1 1046
bogdanm 89:552587b429a1 1047 #endif /* __STM32F4xx_LL_FSMC_H */
bogdanm 89:552587b429a1 1048
bogdanm 89:552587b429a1 1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/